MipsGenInstrInfo.inc

Summary Report

Line number	Line	Number of hits	Tests that cover line
1	/===- TableGen'erated file -------------------------------------- C++ --===\	----
2	\|* *\|	----
3	\|* Target Instruction Enum Values and Descriptors *\|	----
4	\|* *\|	----
5	\|* Automatically generated file, do not edit! *\|	----
6	\|* *\|	----
7	\===----------------------------------------------------------------------===/	----
8		----
9	#ifdef GET_INSTRINFO_ENUM	----
10	#undef GET_INSTRINFO_ENUM	----
11	namespace llvm {	----
12		----
13	namespace Mips {	----
14	enum {	----
15	PHI = 0,	----
16	INLINEASM = 1,	----
17	INLINEASM_BR = 2,	----
18	CFI_INSTRUCTION = 3,	----
19	EH_LABEL = 4,	----
20	GC_LABEL = 5,	----
21	ANNOTATION_LABEL = 6,	----
22	KILL = 7,	----
23	EXTRACT_SUBREG = 8,	----
24	INSERT_SUBREG = 9,	----
25	IMPLICIT_DEF = 10,	----
26	SUBREG_TO_REG = 11,	----
27	COPY_TO_REGCLASS = 12,	----
28	DBG_VALUE = 13,	----
29	DBG_VALUE_LIST = 14,	----
30	DBG_INSTR_REF = 15,	----
31	DBG_PHI = 16,	----
32	DBG_LABEL = 17,	----
33	REG_SEQUENCE = 18,	----
34	COPY = 19,	----
35	BUNDLE = 20,	----
36	LIFETIME_START = 21,	----
37	LIFETIME_END = 22,	----
38	PSEUDO_PROBE = 23,	----
39	ARITH_FENCE = 24,	----
40	STACKMAP = 25,	----
41	FENTRY_CALL = 26,	----
42	PATCHPOINT = 27,	----
43	LOAD_STACK_GUARD = 28,	----
44	PREALLOCATED_SETUP = 29,	----
45	PREALLOCATED_ARG = 30,	----
46	STATEPOINT = 31,	----
47	LOCAL_ESCAPE = 32,	----
48	FAULTING_OP = 33,	----
49	PATCHABLE_OP = 34,	----
50	PATCHABLE_FUNCTION_ENTER = 35,	----
51	PATCHABLE_RET = 36,	----
52	PATCHABLE_FUNCTION_EXIT = 37,	----
53	PATCHABLE_TAIL_CALL = 38,	----
54	PATCHABLE_EVENT_CALL = 39,	----
55	PATCHABLE_TYPED_EVENT_CALL = 40,	----
56	ICALL_BRANCH_FUNNEL = 41,	----
57	MEMBARRIER = 42,	----
58	G_ASSERT_SEXT = 43,	----
59	G_ASSERT_ZEXT = 44,	----
60	G_ASSERT_ALIGN = 45,	----
61	G_ADD = 46,	----
62	G_SUB = 47,	----
63	G_MUL = 48,	----
64	G_SDIV = 49,	----
65	G_UDIV = 50,	----
66	G_SREM = 51,	----
67	G_UREM = 52,	----
68	G_SDIVREM = 53,	----
69	G_UDIVREM = 54,	----
70	G_AND = 55,	----
71	G_OR = 56,	----
72	G_XOR = 57,	----
73	G_IMPLICIT_DEF = 58,	----
74	G_PHI = 59,	----
75	G_FRAME_INDEX = 60,	----
76	G_GLOBAL_VALUE = 61,	----
77	G_CONSTANT_POOL = 62,	----
78	G_EXTRACT = 63,	----
79	G_UNMERGE_VALUES = 64,	----
80	G_INSERT = 65,	----
81	G_MERGE_VALUES = 66,	----
82	G_BUILD_VECTOR = 67,	----
83	G_BUILD_VECTOR_TRUNC = 68,	----
84	G_CONCAT_VECTORS = 69,	----
85	G_PTRTOINT = 70,	----
86	G_INTTOPTR = 71,	----
87	G_BITCAST = 72,	----
88	G_FREEZE = 73,	----
89	G_CONSTANT_FOLD_BARRIER = 74,	----
90	G_INTRINSIC_FPTRUNC_ROUND = 75,	----
91	G_INTRINSIC_TRUNC = 76,	----
92	G_INTRINSIC_ROUND = 77,	----
93	G_INTRINSIC_LRINT = 78,	----
94	G_INTRINSIC_ROUNDEVEN = 79,	----
95	G_READCYCLECOUNTER = 80,	----
96	G_LOAD = 81,	----
97	G_SEXTLOAD = 82,	----
98	G_ZEXTLOAD = 83,	----
99	G_INDEXED_LOAD = 84,	----
100	G_INDEXED_SEXTLOAD = 85,	----
101	G_INDEXED_ZEXTLOAD = 86,	----
102	G_STORE = 87,	----
103	G_INDEXED_STORE = 88,	----
104	G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89,	----
105	G_ATOMIC_CMPXCHG = 90,	----
106	G_ATOMICRMW_XCHG = 91,	----
107	G_ATOMICRMW_ADD = 92,	----
108	G_ATOMICRMW_SUB = 93,	----
109	G_ATOMICRMW_AND = 94,	----
110	G_ATOMICRMW_NAND = 95,	----
111	G_ATOMICRMW_OR = 96,	----
112	G_ATOMICRMW_XOR = 97,	----
113	G_ATOMICRMW_MAX = 98,	----
114	G_ATOMICRMW_MIN = 99,	----
115	G_ATOMICRMW_UMAX = 100,	----
116	G_ATOMICRMW_UMIN = 101,	----
117	G_ATOMICRMW_FADD = 102,	----
118	G_ATOMICRMW_FSUB = 103,	----
119	G_ATOMICRMW_FMAX = 104,	----
120	G_ATOMICRMW_FMIN = 105,	----
121	G_ATOMICRMW_UINC_WRAP = 106,	----
122	G_ATOMICRMW_UDEC_WRAP = 107,	----
123	G_FENCE = 108,	----
124	G_BRCOND = 109,	----
125	G_BRINDIRECT = 110,	----
126	G_INVOKE_REGION_START = 111,	----
127	G_INTRINSIC = 112,	----
128	G_INTRINSIC_W_SIDE_EFFECTS = 113,	----
129	G_ANYEXT = 114,	----
130	G_TRUNC = 115,	----
131	G_CONSTANT = 116,	----
132	G_FCONSTANT = 117,	----
133	G_VASTART = 118,	----
134	G_VAARG = 119,	----
135	G_SEXT = 120,	----
136	G_SEXT_INREG = 121,	----
137	G_ZEXT = 122,	----
138	G_SHL = 123,	----
139	G_LSHR = 124,	----
140	G_ASHR = 125,	----
141	G_FSHL = 126,	----
142	G_FSHR = 127,	----
143	G_ROTR = 128,	----
144	G_ROTL = 129,	----
145	G_ICMP = 130,	----
146	G_FCMP = 131,	----
147	G_SELECT = 132,	----
148	G_UADDO = 133,	----
149	G_UADDE = 134,	----
150	G_USUBO = 135,	----
151	G_USUBE = 136,	----
152	G_SADDO = 137,	----
153	G_SADDE = 138,	----
154	G_SSUBO = 139,	----
155	G_SSUBE = 140,	----
156	G_UMULO = 141,	----
157	G_SMULO = 142,	----
158	G_UMULH = 143,	----
159	G_SMULH = 144,	----
160	G_UADDSAT = 145,	----
161	G_SADDSAT = 146,	----
162	G_USUBSAT = 147,	----
163	G_SSUBSAT = 148,	----
164	G_USHLSAT = 149,	----
165	G_SSHLSAT = 150,	----
166	G_SMULFIX = 151,	----
167	G_UMULFIX = 152,	----
168	G_SMULFIXSAT = 153,	----
169	G_UMULFIXSAT = 154,	----
170	G_SDIVFIX = 155,	----
171	G_UDIVFIX = 156,	----
172	G_SDIVFIXSAT = 157,	----
173	G_UDIVFIXSAT = 158,	----
174	G_FADD = 159,	----
175	G_FSUB = 160,	----
176	G_FMUL = 161,	----
177	G_FMA = 162,	----
178	G_FMAD = 163,	----
179	G_FDIV = 164,	----
180	G_FREM = 165,	----
181	G_FPOW = 166,	----
182	G_FPOWI = 167,	----
183	G_FEXP = 168,	----
184	G_FEXP2 = 169,	----
185	G_FLOG = 170,	----
186	G_FLOG2 = 171,	----
187	G_FLOG10 = 172,	----
188	G_FLDEXP = 173,	----
189	G_FFREXP = 174,	----
190	G_FNEG = 175,	----
191	G_FPEXT = 176,	----
192	G_FPTRUNC = 177,	----
193	G_FPTOSI = 178,	----
194	G_FPTOUI = 179,	----
195	G_SITOFP = 180,	----
196	G_UITOFP = 181,	----
197	G_FABS = 182,	----
198	G_FCOPYSIGN = 183,	----
199	G_IS_FPCLASS = 184,	----
200	G_FCANONICALIZE = 185,	----
201	G_FMINNUM = 186,	----
202	G_FMAXNUM = 187,	----
203	G_FMINNUM_IEEE = 188,	----
204	G_FMAXNUM_IEEE = 189,	----
205	G_FMINIMUM = 190,	----
206	G_FMAXIMUM = 191,	----
207	G_PTR_ADD = 192,	----
208	G_PTRMASK = 193,	----
209	G_SMIN = 194,	----
210	G_SMAX = 195,	----
211	G_UMIN = 196,	----
212	G_UMAX = 197,	----
213	G_ABS = 198,	----
214	G_LROUND = 199,	----
215	G_LLROUND = 200,	----
216	G_BR = 201,	----
217	G_BRJT = 202,	----
218	G_INSERT_VECTOR_ELT = 203,	----
219	G_EXTRACT_VECTOR_ELT = 204,	----
220	G_SHUFFLE_VECTOR = 205,	----
221	G_CTTZ = 206,	----
222	G_CTTZ_ZERO_UNDEF = 207,	----
223	G_CTLZ = 208,	----
224	G_CTLZ_ZERO_UNDEF = 209,	----
225	G_CTPOP = 210,	----
226	G_BSWAP = 211,	----
227	G_BITREVERSE = 212,	----
228	G_FCEIL = 213,	----
229	G_FCOS = 214,	----
230	G_FSIN = 215,	----
231	G_FSQRT = 216,	----
232	G_FFLOOR = 217,	----
233	G_FRINT = 218,	----
234	G_FNEARBYINT = 219,	----
235	G_ADDRSPACE_CAST = 220,	----
236	G_BLOCK_ADDR = 221,	----
237	G_JUMP_TABLE = 222,	----
238	G_DYN_STACKALLOC = 223,	----
239	G_STRICT_FADD = 224,	----
240	G_STRICT_FSUB = 225,	----
241	G_STRICT_FMUL = 226,	----
242	G_STRICT_FDIV = 227,	----
243	G_STRICT_FREM = 228,	----
244	G_STRICT_FMA = 229,	----
245	G_STRICT_FSQRT = 230,	----
246	G_STRICT_FLDEXP = 231,	----
247	G_READ_REGISTER = 232,	----
248	G_WRITE_REGISTER = 233,	----
249	G_MEMCPY = 234,	----
250	G_MEMCPY_INLINE = 235,	----
251	G_MEMMOVE = 236,	----
252	G_MEMSET = 237,	----
253	G_BZERO = 238,	----
254	G_VECREDUCE_SEQ_FADD = 239,	----
255	G_VECREDUCE_SEQ_FMUL = 240,	----
256	G_VECREDUCE_FADD = 241,	----
257	G_VECREDUCE_FMUL = 242,	----
258	G_VECREDUCE_FMAX = 243,	----
259	G_VECREDUCE_FMIN = 244,	----
260	G_VECREDUCE_ADD = 245,	----
261	G_VECREDUCE_MUL = 246,	----
262	G_VECREDUCE_AND = 247,	----
263	G_VECREDUCE_OR = 248,	----
264	G_VECREDUCE_XOR = 249,	----
265	G_VECREDUCE_SMAX = 250,	----
266	G_VECREDUCE_SMIN = 251,	----
267	G_VECREDUCE_UMAX = 252,	----
268	G_VECREDUCE_UMIN = 253,	----
269	G_SBFX = 254,	----
270	G_UBFX = 255,	----
271	ABSMacro = 256,	----
272	ADJCALLSTACKDOWN = 257,	----
273	ADJCALLSTACKUP = 258,	----
274	AND_V_D_PSEUDO = 259,	----
275	AND_V_H_PSEUDO = 260,	----
276	AND_V_W_PSEUDO = 261,	----
277	ATOMIC_CMP_SWAP_I16 = 262,	----
278	ATOMIC_CMP_SWAP_I16_POSTRA = 263,	----
279	ATOMIC_CMP_SWAP_I32 = 264,	----
280	ATOMIC_CMP_SWAP_I32_POSTRA = 265,	----
281	ATOMIC_CMP_SWAP_I64 = 266,	----
282	ATOMIC_CMP_SWAP_I64_POSTRA = 267,	----
283	ATOMIC_CMP_SWAP_I8 = 268,	----
284	ATOMIC_CMP_SWAP_I8_POSTRA = 269,	----
285	ATOMIC_LOAD_ADD_I16 = 270,	----
286	ATOMIC_LOAD_ADD_I16_POSTRA = 271,	----
287	ATOMIC_LOAD_ADD_I32 = 272,	----
288	ATOMIC_LOAD_ADD_I32_POSTRA = 273,	----
289	ATOMIC_LOAD_ADD_I64 = 274,	----
290	ATOMIC_LOAD_ADD_I64_POSTRA = 275,	----
291	ATOMIC_LOAD_ADD_I8 = 276,	----
292	ATOMIC_LOAD_ADD_I8_POSTRA = 277,	----
293	ATOMIC_LOAD_AND_I16 = 278,	----
294	ATOMIC_LOAD_AND_I16_POSTRA = 279,	----
295	ATOMIC_LOAD_AND_I32 = 280,	----
296	ATOMIC_LOAD_AND_I32_POSTRA = 281,	----
297	ATOMIC_LOAD_AND_I64 = 282,	----
298	ATOMIC_LOAD_AND_I64_POSTRA = 283,	----
299	ATOMIC_LOAD_AND_I8 = 284,	----
300	ATOMIC_LOAD_AND_I8_POSTRA = 285,	----
301	ATOMIC_LOAD_MAX_I16 = 286,	----
302	ATOMIC_LOAD_MAX_I16_POSTRA = 287,	----
303	ATOMIC_LOAD_MAX_I32 = 288,	----
304	ATOMIC_LOAD_MAX_I32_POSTRA = 289,	----
305	ATOMIC_LOAD_MAX_I64 = 290,	----
306	ATOMIC_LOAD_MAX_I64_POSTRA = 291,	----
307	ATOMIC_LOAD_MAX_I8 = 292,	----
308	ATOMIC_LOAD_MAX_I8_POSTRA = 293,	----
309	ATOMIC_LOAD_MIN_I16 = 294,	----
310	ATOMIC_LOAD_MIN_I16_POSTRA = 295,	----
311	ATOMIC_LOAD_MIN_I32 = 296,	----
312	ATOMIC_LOAD_MIN_I32_POSTRA = 297,	----
313	ATOMIC_LOAD_MIN_I64 = 298,	----
314	ATOMIC_LOAD_MIN_I64_POSTRA = 299,	----
315	ATOMIC_LOAD_MIN_I8 = 300,	----
316	ATOMIC_LOAD_MIN_I8_POSTRA = 301,	----
317	ATOMIC_LOAD_NAND_I16 = 302,	----
318	ATOMIC_LOAD_NAND_I16_POSTRA = 303,	----
319	ATOMIC_LOAD_NAND_I32 = 304,	----
320	ATOMIC_LOAD_NAND_I32_POSTRA = 305,	----
321	ATOMIC_LOAD_NAND_I64 = 306,	----
322	ATOMIC_LOAD_NAND_I64_POSTRA = 307,	----
323	ATOMIC_LOAD_NAND_I8 = 308,	----
324	ATOMIC_LOAD_NAND_I8_POSTRA = 309,	----
325	ATOMIC_LOAD_OR_I16 = 310,	----
326	ATOMIC_LOAD_OR_I16_POSTRA = 311,	----
327	ATOMIC_LOAD_OR_I32 = 312,	----
328	ATOMIC_LOAD_OR_I32_POSTRA = 313,	----
329	ATOMIC_LOAD_OR_I64 = 314,	----
330	ATOMIC_LOAD_OR_I64_POSTRA = 315,	----
331	ATOMIC_LOAD_OR_I8 = 316,	----
332	ATOMIC_LOAD_OR_I8_POSTRA = 317,	----
333	ATOMIC_LOAD_SUB_I16 = 318,	----
334	ATOMIC_LOAD_SUB_I16_POSTRA = 319,	----
335	ATOMIC_LOAD_SUB_I32 = 320,	----
336	ATOMIC_LOAD_SUB_I32_POSTRA = 321,	----
337	ATOMIC_LOAD_SUB_I64 = 322,	----
338	ATOMIC_LOAD_SUB_I64_POSTRA = 323,	----
339	ATOMIC_LOAD_SUB_I8 = 324,	----
340	ATOMIC_LOAD_SUB_I8_POSTRA = 325,	----
341	ATOMIC_LOAD_UMAX_I16 = 326,	----
342	ATOMIC_LOAD_UMAX_I16_POSTRA = 327,	----
343	ATOMIC_LOAD_UMAX_I32 = 328,	----
344	ATOMIC_LOAD_UMAX_I32_POSTRA = 329,	----
345	ATOMIC_LOAD_UMAX_I64 = 330,	----
346	ATOMIC_LOAD_UMAX_I64_POSTRA = 331,	----
347	ATOMIC_LOAD_UMAX_I8 = 332,	----
348	ATOMIC_LOAD_UMAX_I8_POSTRA = 333,	----
349	ATOMIC_LOAD_UMIN_I16 = 334,	----
350	ATOMIC_LOAD_UMIN_I16_POSTRA = 335,	----
351	ATOMIC_LOAD_UMIN_I32 = 336,	----
352	ATOMIC_LOAD_UMIN_I32_POSTRA = 337,	----
353	ATOMIC_LOAD_UMIN_I64 = 338,	----
354	ATOMIC_LOAD_UMIN_I64_POSTRA = 339,	----
355	ATOMIC_LOAD_UMIN_I8 = 340,	----
356	ATOMIC_LOAD_UMIN_I8_POSTRA = 341,	----
357	ATOMIC_LOAD_XOR_I16 = 342,	----
358	ATOMIC_LOAD_XOR_I16_POSTRA = 343,	----
359	ATOMIC_LOAD_XOR_I32 = 344,	----
360	ATOMIC_LOAD_XOR_I32_POSTRA = 345,	----
361	ATOMIC_LOAD_XOR_I64 = 346,	----
362	ATOMIC_LOAD_XOR_I64_POSTRA = 347,	----
363	ATOMIC_LOAD_XOR_I8 = 348,	----
364	ATOMIC_LOAD_XOR_I8_POSTRA = 349,	----
365	ATOMIC_SWAP_I16 = 350,	----
366	ATOMIC_SWAP_I16_POSTRA = 351,	----
367	ATOMIC_SWAP_I32 = 352,	----
368	ATOMIC_SWAP_I32_POSTRA = 353,	----
369	ATOMIC_SWAP_I64 = 354,	----
370	ATOMIC_SWAP_I64_POSTRA = 355,	----
371	ATOMIC_SWAP_I8 = 356,	----
372	ATOMIC_SWAP_I8_POSTRA = 357,	----
373	B = 358,	----
374	BAL_BR = 359,	----
375	BAL_BR_MM = 360,	----
376	BEQLImmMacro = 361,	----
377	BGE = 362,	----
378	BGEImmMacro = 363,	----
379	BGEL = 364,	----
380	BGELImmMacro = 365,	----
381	BGEU = 366,	----
382	BGEUImmMacro = 367,	----
383	BGEUL = 368,	----
384	BGEULImmMacro = 369,	----
385	BGT = 370,	----
386	BGTImmMacro = 371,	----
387	BGTL = 372,	----
388	BGTLImmMacro = 373,	----
389	BGTU = 374,	----
390	BGTUImmMacro = 375,	----
391	BGTUL = 376,	----
392	BGTULImmMacro = 377,	----
393	BLE = 378,	----
394	BLEImmMacro = 379,	----
395	BLEL = 380,	----
396	BLELImmMacro = 381,	----
397	BLEU = 382,	----
398	BLEUImmMacro = 383,	----
399	BLEUL = 384,	----
400	BLEULImmMacro = 385,	----
401	BLT = 386,	----
402	BLTImmMacro = 387,	----
403	BLTL = 388,	----
404	BLTLImmMacro = 389,	----
405	BLTU = 390,	----
406	BLTUImmMacro = 391,	----
407	BLTUL = 392,	----
408	BLTULImmMacro = 393,	----
409	BNELImmMacro = 394,	----
410	BPOSGE32_PSEUDO = 395,	----
411	BSEL_D_PSEUDO = 396,	----
412	BSEL_FD_PSEUDO = 397,	----
413	BSEL_FW_PSEUDO = 398,	----
414	BSEL_H_PSEUDO = 399,	----
415	BSEL_W_PSEUDO = 400,	----
416	B_MM = 401,	----
417	B_MMR6_Pseudo = 402,	----
418	B_MM_Pseudo = 403,	----
419	BeqImm = 404,	----
420	BneImm = 405,	----
421	BteqzT8CmpX16 = 406,	----
422	BteqzT8CmpiX16 = 407,	----
423	BteqzT8SltX16 = 408,	----
424	BteqzT8SltiX16 = 409,	----
425	BteqzT8SltiuX16 = 410,	----
426	BteqzT8SltuX16 = 411,	----
427	BtnezT8CmpX16 = 412,	----
428	BtnezT8CmpiX16 = 413,	----
429	BtnezT8SltX16 = 414,	----
430	BtnezT8SltiX16 = 415,	----
431	BtnezT8SltiuX16 = 416,	----
432	BtnezT8SltuX16 = 417,	----
433	BuildPairF64 = 418,	----
434	BuildPairF64_64 = 419,	----
435	CFTC1 = 420,	----
436	CONSTPOOL_ENTRY = 421,	----
437	COPY_FD_PSEUDO = 422,	----
438	COPY_FW_PSEUDO = 423,	----
439	CTTC1 = 424,	----
440	Constant32 = 425,	----
441	DMULImmMacro = 426,	----
442	DMULMacro = 427,	----
443	DMULOMacro = 428,	----
444	DMULOUMacro = 429,	----
445	DROL = 430,	----
446	DROLImm = 431,	----
447	DROR = 432,	----
448	DRORImm = 433,	----
449	DSDivIMacro = 434,	----
450	DSDivMacro = 435,	----
451	DSRemIMacro = 436,	----
452	DSRemMacro = 437,	----
453	DUDivIMacro = 438,	----
454	DUDivMacro = 439,	----
455	DURemIMacro = 440,	----
456	DURemMacro = 441,	----
457	ERet = 442,	----
458	ExtractElementF64 = 443,	----
459	ExtractElementF64_64 = 444,	----
460	FABS_D = 445,	----
461	FABS_W = 446,	----
462	FEXP2_D_1_PSEUDO = 447,	----
463	FEXP2_W_1_PSEUDO = 448,	----
464	FILL_FD_PSEUDO = 449,	----
465	FILL_FW_PSEUDO = 450,	----
466	GotPrologue16 = 451,	----
467	INSERT_B_VIDX64_PSEUDO = 452,	----
468	INSERT_B_VIDX_PSEUDO = 453,	----
469	INSERT_D_VIDX64_PSEUDO = 454,	----
470	INSERT_D_VIDX_PSEUDO = 455,	----
471	INSERT_FD_PSEUDO = 456,	----
472	INSERT_FD_VIDX64_PSEUDO = 457,	----
473	INSERT_FD_VIDX_PSEUDO = 458,	----
474	INSERT_FW_PSEUDO = 459,	----
475	INSERT_FW_VIDX64_PSEUDO = 460,	----
476	INSERT_FW_VIDX_PSEUDO = 461,	----
477	INSERT_H_VIDX64_PSEUDO = 462,	----
478	INSERT_H_VIDX_PSEUDO = 463,	----
479	INSERT_W_VIDX64_PSEUDO = 464,	----
480	INSERT_W_VIDX_PSEUDO = 465,	----
481	JALR64Pseudo = 466,	----
482	JALRHB64Pseudo = 467,	----
483	JALRHBPseudo = 468,	----
484	JALRPseudo = 469,	----
485	JAL_MMR6 = 470,	----
486	JalOneReg = 471,	----
487	JalTwoReg = 472,	----
488	LDMacro = 473,	----
489	LDR_D = 474,	----
490	LDR_W = 475,	----
491	LD_F16 = 476,	----
492	LOAD_ACC128 = 477,	----
493	LOAD_ACC64 = 478,	----
494	LOAD_ACC64DSP = 479,	----
495	LOAD_CCOND_DSP = 480,	----
496	LONG_BRANCH_ADDiu = 481,	----
497	LONG_BRANCH_ADDiu2Op = 482,	----
498	LONG_BRANCH_DADDiu = 483,	----
499	LONG_BRANCH_DADDiu2Op = 484,	----
500	LONG_BRANCH_LUi = 485,	----
501	LONG_BRANCH_LUi2Op = 486,	----
502	LONG_BRANCH_LUi2Op_64 = 487,	----
503	LWM_MM = 488,	----
504	LoadAddrImm32 = 489,	----
505	LoadAddrImm64 = 490,	----
506	LoadAddrReg32 = 491,	----
507	LoadAddrReg64 = 492,	----
508	LoadImm32 = 493,	----
509	LoadImm64 = 494,	----
510	LoadImmDoubleFGR = 495,	----
511	LoadImmDoubleFGR_32 = 496,	----
512	LoadImmDoubleGPR = 497,	----
513	LoadImmSingleFGR = 498,	----
514	LoadImmSingleGPR = 499,	----
515	LwConstant32 = 500,	----
516	MFTACX = 501,	----
517	MFTC0 = 502,	----
518	MFTC1 = 503,	----
519	MFTDSP = 504,	----
520	MFTGPR = 505,	----
521	MFTHC1 = 506,	----
522	MFTHI = 507,	----
523	MFTLO = 508,	----
524	MIPSeh_return32 = 509,	----
525	MIPSeh_return64 = 510,	----
526	MSA_FP_EXTEND_D_PSEUDO = 511,	----
527	MSA_FP_EXTEND_W_PSEUDO = 512,	----
528	MSA_FP_ROUND_D_PSEUDO = 513,	----
529	MSA_FP_ROUND_W_PSEUDO = 514,	----
530	MTTACX = 515,	----
531	MTTC0 = 516,	----
532	MTTC1 = 517,	----
533	MTTDSP = 518,	----
534	MTTGPR = 519,	----
535	MTTHC1 = 520,	----
536	MTTHI = 521,	----
537	MTTLO = 522,	----
538	MULImmMacro = 523,	----
539	MULOMacro = 524,	----
540	MULOUMacro = 525,	----
541	MultRxRy16 = 526,	----
542	MultRxRyRz16 = 527,	----
543	MultuRxRy16 = 528,	----
544	MultuRxRyRz16 = 529,	----
545	NOP = 530,	----
546	NORImm = 531,	----
547	NORImm64 = 532,	----
548	NOR_V_D_PSEUDO = 533,	----
549	NOR_V_H_PSEUDO = 534,	----
550	NOR_V_W_PSEUDO = 535,	----
551	OR_V_D_PSEUDO = 536,	----
552	OR_V_H_PSEUDO = 537,	----
553	OR_V_W_PSEUDO = 538,	----
554	PseudoCMPU_EQ_QB = 539,	----
555	PseudoCMPU_LE_QB = 540,	----
556	PseudoCMPU_LT_QB = 541,	----
557	PseudoCMP_EQ_PH = 542,	----
558	PseudoCMP_LE_PH = 543,	----
559	PseudoCMP_LT_PH = 544,	----
560	PseudoCVT_D32_W = 545,	----
561	PseudoCVT_D64_L = 546,	----
562	PseudoCVT_D64_W = 547,	----
563	PseudoCVT_S_L = 548,	----
564	PseudoCVT_S_W = 549,	----
565	PseudoDMULT = 550,	----
566	PseudoDMULTu = 551,	----
567	PseudoDSDIV = 552,	----
568	PseudoDUDIV = 553,	----
569	PseudoD_SELECT_I = 554,	----
570	PseudoD_SELECT_I64 = 555,	----
571	PseudoIndirectBranch = 556,	----
572	PseudoIndirectBranch64 = 557,	----
573	PseudoIndirectBranch64R6 = 558,	----
574	PseudoIndirectBranchR6 = 559,	----
575	PseudoIndirectBranch_MM = 560,	----
576	PseudoIndirectBranch_MMR6 = 561,	----
577	PseudoIndirectHazardBranch = 562,	----
578	PseudoIndirectHazardBranch64 = 563,	----
579	PseudoIndrectHazardBranch64R6 = 564,	----
580	PseudoIndrectHazardBranchR6 = 565,	----
581	PseudoMADD = 566,	----
582	PseudoMADDU = 567,	----
583	PseudoMADDU_MM = 568,	----
584	PseudoMADD_MM = 569,	----
585	PseudoMFHI = 570,	----
586	PseudoMFHI64 = 571,	----
587	PseudoMFHI_MM = 572,	----
588	PseudoMFLO = 573,	----
589	PseudoMFLO64 = 574,	----
590	PseudoMFLO_MM = 575,	----
591	PseudoMSUB = 576,	----
592	PseudoMSUBU = 577,	----
593	PseudoMSUBU_MM = 578,	----
594	PseudoMSUB_MM = 579,	----
595	PseudoMTLOHI = 580,	----
596	PseudoMTLOHI64 = 581,	----
597	PseudoMTLOHI_DSP = 582,	----
598	PseudoMTLOHI_MM = 583,	----
599	PseudoMULT = 584,	----
600	PseudoMULT_MM = 585,	----
601	PseudoMULTu = 586,	----
602	PseudoMULTu_MM = 587,	----
603	PseudoPICK_PH = 588,	----
604	PseudoPICK_QB = 589,	----
605	PseudoReturn = 590,	----
606	PseudoReturn64 = 591,	----
607	PseudoSDIV = 592,	----
608	PseudoSELECTFP_F_D32 = 593,	----
609	PseudoSELECTFP_F_D64 = 594,	----
610	PseudoSELECTFP_F_I = 595,	----
611	PseudoSELECTFP_F_I64 = 596,	----
612	PseudoSELECTFP_F_S = 597,	----
613	PseudoSELECTFP_T_D32 = 598,	----
614	PseudoSELECTFP_T_D64 = 599,	----
615	PseudoSELECTFP_T_I = 600,	----
616	PseudoSELECTFP_T_I64 = 601,	----
617	PseudoSELECTFP_T_S = 602,	----
618	PseudoSELECT_D32 = 603,	----
619	PseudoSELECT_D64 = 604,	----
620	PseudoSELECT_I = 605,	----
621	PseudoSELECT_I64 = 606,	----
622	PseudoSELECT_S = 607,	----
623	PseudoTRUNC_W_D = 608,	----
624	PseudoTRUNC_W_D32 = 609,	----
625	PseudoTRUNC_W_S = 610,	----
626	PseudoUDIV = 611,	----
627	ROL = 612,	----
628	ROLImm = 613,	----
629	ROR = 614,	----
630	RORImm = 615,	----
631	RetRA = 616,	----
632	RetRA16 = 617,	----
633	SDC1_M1 = 618,	----
634	SDIV_MM_Pseudo = 619,	----
635	SDMacro = 620,	----
636	SDivIMacro = 621,	----
637	SDivMacro = 622,	----
638	SEQIMacro = 623,	----
639	SEQMacro = 624,	----
640	SGE = 625,	----
641	SGEImm = 626,	----
642	SGEImm64 = 627,	----
643	SGEU = 628,	----
644	SGEUImm = 629,	----
645	SGEUImm64 = 630,	----
646	SGTImm = 631,	----
647	SGTImm64 = 632,	----
648	SGTUImm = 633,	----
649	SGTUImm64 = 634,	----
650	SLE = 635,	----
651	SLEImm = 636,	----
652	SLEImm64 = 637,	----
653	SLEU = 638,	----
654	SLEUImm = 639,	----
655	SLEUImm64 = 640,	----
656	SLTImm64 = 641,	----
657	SLTUImm64 = 642,	----
658	SNEIMacro = 643,	----
659	SNEMacro = 644,	----
660	SNZ_B_PSEUDO = 645,	----
661	SNZ_D_PSEUDO = 646,	----
662	SNZ_H_PSEUDO = 647,	----
663	SNZ_V_PSEUDO = 648,	----
664	SNZ_W_PSEUDO = 649,	----
665	SRemIMacro = 650,	----
666	SRemMacro = 651,	----
667	STORE_ACC128 = 652,	----
668	STORE_ACC64 = 653,	----
669	STORE_ACC64DSP = 654,	----
670	STORE_CCOND_DSP = 655,	----
671	STR_D = 656,	----
672	STR_W = 657,	----
673	ST_F16 = 658,	----
674	SWM_MM = 659,	----
675	SZ_B_PSEUDO = 660,	----
676	SZ_D_PSEUDO = 661,	----
677	SZ_H_PSEUDO = 662,	----
678	SZ_V_PSEUDO = 663,	----
679	SZ_W_PSEUDO = 664,	----
680	SaaAddr = 665,	----
681	SaadAddr = 666,	----
682	SelBeqZ = 667,	----
683	SelBneZ = 668,	----
684	SelTBteqZCmp = 669,	----
685	SelTBteqZCmpi = 670,	----
686	SelTBteqZSlt = 671,	----
687	SelTBteqZSlti = 672,	----
688	SelTBteqZSltiu = 673,	----
689	SelTBteqZSltu = 674,	----
690	SelTBtneZCmp = 675,	----
691	SelTBtneZCmpi = 676,	----
692	SelTBtneZSlt = 677,	----
693	SelTBtneZSlti = 678,	----
694	SelTBtneZSltiu = 679,	----
695	SelTBtneZSltu = 680,	----
696	SltCCRxRy16 = 681,	----
697	SltiCCRxImmX16 = 682,	----
698	SltiuCCRxImmX16 = 683,	----
699	SltuCCRxRy16 = 684,	----
700	SltuRxRyRz16 = 685,	----
701	TAILCALL = 686,	----
702	TAILCALL64R6REG = 687,	----
703	TAILCALLHB64R6REG = 688,	----
704	TAILCALLHBR6REG = 689,	----
705	TAILCALLR6REG = 690,	----
706	TAILCALLREG = 691,	----
707	TAILCALLREG64 = 692,	----
708	TAILCALLREGHB = 693,	----
709	TAILCALLREGHB64 = 694,	----
710	TAILCALLREG_MM = 695,	----
711	TAILCALLREG_MMR6 = 696,	----
712	TAILCALL_MM = 697,	----
713	TAILCALL_MMR6 = 698,	----
714	TRAP = 699,	----
715	TRAP_MM = 700,	----
716	UDIV_MM_Pseudo = 701,	----
717	UDivIMacro = 702,	----
718	UDivMacro = 703,	----
719	URemIMacro = 704,	----
720	URemMacro = 705,	----
721	Ulh = 706,	----
722	Ulhu = 707,	----
723	Ulw = 708,	----
724	Ush = 709,	----
725	Usw = 710,	----
726	XOR_V_D_PSEUDO = 711,	----
727	XOR_V_H_PSEUDO = 712,	----
728	XOR_V_W_PSEUDO = 713,	----
729	ABSQ_S_PH = 714,	----
730	ABSQ_S_PH_MM = 715,	----
731	ABSQ_S_QB = 716,	----
732	ABSQ_S_QB_MMR2 = 717,	----
733	ABSQ_S_W = 718,	----
734	ABSQ_S_W_MM = 719,	----
735	ADD = 720,	----
736	ADDIUPC = 721,	----
737	ADDIUPC_MM = 722,	----
738	ADDIUPC_MMR6 = 723,	----
739	ADDIUR1SP_MM = 724,	----
740	ADDIUR2_MM = 725,	----
741	ADDIUS5_MM = 726,	----
742	ADDIUSP_MM = 727,	----
743	ADDIU_MMR6 = 728,	----
744	ADDQH_PH = 729,	----
745	ADDQH_PH_MMR2 = 730,	----
746	ADDQH_R_PH = 731,	----
747	ADDQH_R_PH_MMR2 = 732,	----
748	ADDQH_R_W = 733,	----
749	ADDQH_R_W_MMR2 = 734,	----
750	ADDQH_W = 735,	----
751	ADDQH_W_MMR2 = 736,	----
752	ADDQ_PH = 737,	----
753	ADDQ_PH_MM = 738,	----
754	ADDQ_S_PH = 739,	----
755	ADDQ_S_PH_MM = 740,	----
756	ADDQ_S_W = 741,	----
757	ADDQ_S_W_MM = 742,	----
758	ADDR_PS64 = 743,	----
759	ADDSC = 744,	----
760	ADDSC_MM = 745,	----
761	ADDS_A_B = 746,	----
762	ADDS_A_D = 747,	----
763	ADDS_A_H = 748,	----
764	ADDS_A_W = 749,	----
765	ADDS_S_B = 750,	----
766	ADDS_S_D = 751,	----
767	ADDS_S_H = 752,	----
768	ADDS_S_W = 753,	----
769	ADDS_U_B = 754,	----
770	ADDS_U_D = 755,	----
771	ADDS_U_H = 756,	----
772	ADDS_U_W = 757,	----
773	ADDU16_MM = 758,	----
774	ADDU16_MMR6 = 759,	----
775	ADDUH_QB = 760,	----
776	ADDUH_QB_MMR2 = 761,	----
777	ADDUH_R_QB = 762,	----
778	ADDUH_R_QB_MMR2 = 763,	----
779	ADDU_MMR6 = 764,	----
780	ADDU_PH = 765,	----
781	ADDU_PH_MMR2 = 766,	----
782	ADDU_QB = 767,	----
783	ADDU_QB_MM = 768,	----
784	ADDU_S_PH = 769,	----
785	ADDU_S_PH_MMR2 = 770,	----
786	ADDU_S_QB = 771,	----
787	ADDU_S_QB_MM = 772,	----
788	ADDVI_B = 773,	----
789	ADDVI_D = 774,	----
790	ADDVI_H = 775,	----
791	ADDVI_W = 776,	----
792	ADDV_B = 777,	----
793	ADDV_D = 778,	----
794	ADDV_H = 779,	----
795	ADDV_W = 780,	----
796	ADDWC = 781,	----
797	ADDWC_MM = 782,	----
798	ADD_A_B = 783,	----
799	ADD_A_D = 784,	----
800	ADD_A_H = 785,	----
801	ADD_A_W = 786,	----
802	ADD_MM = 787,	----
803	ADD_MMR6 = 788,	----
804	ADDi = 789,	----
805	ADDi_MM = 790,	----
806	ADDiu = 791,	----
807	ADDiu_MM = 792,	----
808	ADDu = 793,	----
809	ADDu_MM = 794,	----
810	ALIGN = 795,	----
811	ALIGN_MMR6 = 796,	----
812	ALUIPC = 797,	----
813	ALUIPC_MMR6 = 798,	----
814	AND = 799,	----
815	AND16_MM = 800,	----
816	AND16_MMR6 = 801,	----
817	AND64 = 802,	----
818	ANDI16_MM = 803,	----
819	ANDI16_MMR6 = 804,	----
820	ANDI_B = 805,	----
821	ANDI_MMR6 = 806,	----
822	AND_MM = 807,	----
823	AND_MMR6 = 808,	----
824	AND_V = 809,	----
825	ANDi = 810,	----
826	ANDi64 = 811,	----
827	ANDi_MM = 812,	----
828	APPEND = 813,	----
829	APPEND_MMR2 = 814,	----
830	ASUB_S_B = 815,	----
831	ASUB_S_D = 816,	----
832	ASUB_S_H = 817,	----
833	ASUB_S_W = 818,	----
834	ASUB_U_B = 819,	----
835	ASUB_U_D = 820,	----
836	ASUB_U_H = 821,	----
837	ASUB_U_W = 822,	----
838	AUI = 823,	----
839	AUIPC = 824,	----
840	AUIPC_MMR6 = 825,	----
841	AUI_MMR6 = 826,	----
842	AVER_S_B = 827,	----
843	AVER_S_D = 828,	----
844	AVER_S_H = 829,	----
845	AVER_S_W = 830,	----
846	AVER_U_B = 831,	----
847	AVER_U_D = 832,	----
848	AVER_U_H = 833,	----
849	AVER_U_W = 834,	----
850	AVE_S_B = 835,	----
851	AVE_S_D = 836,	----
852	AVE_S_H = 837,	----
853	AVE_S_W = 838,	----
854	AVE_U_B = 839,	----
855	AVE_U_D = 840,	----
856	AVE_U_H = 841,	----
857	AVE_U_W = 842,	----
858	AddiuRxImmX16 = 843,	----
859	AddiuRxPcImmX16 = 844,	----
860	AddiuRxRxImm16 = 845,	----
861	AddiuRxRxImmX16 = 846,	----
862	AddiuRxRyOffMemX16 = 847,	----
863	AddiuSpImm16 = 848,	----
864	AddiuSpImmX16 = 849,	----
865	AdduRxRyRz16 = 850,	----
866	AndRxRxRy16 = 851,	----
867	B16_MM = 852,	----
868	BADDu = 853,	----
869	BAL = 854,	----
870	BALC = 855,	----
871	BALC_MMR6 = 856,	----
872	BALIGN = 857,	----
873	BALIGN_MMR2 = 858,	----
874	BBIT0 = 859,	----
875	BBIT032 = 860,	----
876	BBIT1 = 861,	----
877	BBIT132 = 862,	----
878	BC = 863,	----
879	BC16_MMR6 = 864,	----
880	BC1EQZ = 865,	----
881	BC1EQZC_MMR6 = 866,	----
882	BC1F = 867,	----
883	BC1FL = 868,	----
884	BC1F_MM = 869,	----
885	BC1NEZ = 870,	----
886	BC1NEZC_MMR6 = 871,	----
887	BC1T = 872,	----
888	BC1TL = 873,	----
889	BC1T_MM = 874,	----
890	BC2EQZ = 875,	----
891	BC2EQZC_MMR6 = 876,	----
892	BC2NEZ = 877,	----
893	BC2NEZC_MMR6 = 878,	----
894	BCLRI_B = 879,	----
895	BCLRI_D = 880,	----
896	BCLRI_H = 881,	----
897	BCLRI_W = 882,	----
898	BCLR_B = 883,	----
899	BCLR_D = 884,	----
900	BCLR_H = 885,	----
901	BCLR_W = 886,	----
902	BC_MMR6 = 887,	----
903	BEQ = 888,	----
904	BEQ64 = 889,	----
905	BEQC = 890,	----
906	BEQC64 = 891,	----
907	BEQC_MMR6 = 892,	----
908	BEQL = 893,	----
909	BEQZ16_MM = 894,	----
910	BEQZALC = 895,	----
911	BEQZALC_MMR6 = 896,	----
912	BEQZC = 897,	----
913	BEQZC16_MMR6 = 898,	----
914	BEQZC64 = 899,	----
915	BEQZC_MM = 900,	----
916	BEQZC_MMR6 = 901,	----
917	BEQ_MM = 902,	----
918	BGEC = 903,	----
919	BGEC64 = 904,	----
920	BGEC_MMR6 = 905,	----
921	BGEUC = 906,	----
922	BGEUC64 = 907,	----
923	BGEUC_MMR6 = 908,	----
924	BGEZ = 909,	----
925	BGEZ64 = 910,	----
926	BGEZAL = 911,	----
927	BGEZALC = 912,	----
928	BGEZALC_MMR6 = 913,	----
929	BGEZALL = 914,	----
930	BGEZALS_MM = 915,	----
931	BGEZAL_MM = 916,	----
932	BGEZC = 917,	----
933	BGEZC64 = 918,	----
934	BGEZC_MMR6 = 919,	----
935	BGEZL = 920,	----
936	BGEZ_MM = 921,	----
937	BGTZ = 922,	----
938	BGTZ64 = 923,	----
939	BGTZALC = 924,	----
940	BGTZALC_MMR6 = 925,	----
941	BGTZC = 926,	----
942	BGTZC64 = 927,	----
943	BGTZC_MMR6 = 928,	----
944	BGTZL = 929,	----
945	BGTZ_MM = 930,	----
946	BINSLI_B = 931,	----
947	BINSLI_D = 932,	----
948	BINSLI_H = 933,	----
949	BINSLI_W = 934,	----
950	BINSL_B = 935,	----
951	BINSL_D = 936,	----
952	BINSL_H = 937,	----
953	BINSL_W = 938,	----
954	BINSRI_B = 939,	----
955	BINSRI_D = 940,	----
956	BINSRI_H = 941,	----
957	BINSRI_W = 942,	----
958	BINSR_B = 943,	----
959	BINSR_D = 944,	----
960	BINSR_H = 945,	----
961	BINSR_W = 946,	----
962	BITREV = 947,	----
963	BITREV_MM = 948,	----
964	BITSWAP = 949,	----
965	BITSWAP_MMR6 = 950,	----
966	BLEZ = 951,	----
967	BLEZ64 = 952,	----
968	BLEZALC = 953,	----
969	BLEZALC_MMR6 = 954,	----
970	BLEZC = 955,	----
971	BLEZC64 = 956,	----
972	BLEZC_MMR6 = 957,	----
973	BLEZL = 958,	----
974	BLEZ_MM = 959,	----
975	BLTC = 960,	----
976	BLTC64 = 961,	----
977	BLTC_MMR6 = 962,	----
978	BLTUC = 963,	----
979	BLTUC64 = 964,	----
980	BLTUC_MMR6 = 965,	----
981	BLTZ = 966,	----
982	BLTZ64 = 967,	----
983	BLTZAL = 968,	----
984	BLTZALC = 969,	----
985	BLTZALC_MMR6 = 970,	----
986	BLTZALL = 971,	----
987	BLTZALS_MM = 972,	----
988	BLTZAL_MM = 973,	----
989	BLTZC = 974,	----
990	BLTZC64 = 975,	----
991	BLTZC_MMR6 = 976,	----
992	BLTZL = 977,	----
993	BLTZ_MM = 978,	----
994	BMNZI_B = 979,	----
995	BMNZ_V = 980,	----
996	BMZI_B = 981,	----
997	BMZ_V = 982,	----
998	BNE = 983,	----
999	BNE64 = 984,	----
1000	BNEC = 985,	----
1001	BNEC64 = 986,	----
1002	BNEC_MMR6 = 987,	----
1003	BNEGI_B = 988,	----
1004	BNEGI_D = 989,	----
1005	BNEGI_H = 990,	----
1006	BNEGI_W = 991,	----
1007	BNEG_B = 992,	----
1008	BNEG_D = 993,	----
1009	BNEG_H = 994,	----
1010	BNEG_W = 995,	----
1011	BNEL = 996,	----
1012	BNEZ16_MM = 997,	----
1013	BNEZALC = 998,	----
1014	BNEZALC_MMR6 = 999,	----
1015	BNEZC = 1000,	----
1016	BNEZC16_MMR6 = 1001,	----
1017	BNEZC64 = 1002,	----
1018	BNEZC_MM = 1003,	----
1019	BNEZC_MMR6 = 1004,	----
1020	BNE_MM = 1005,	----
1021	BNVC = 1006,	----
1022	BNVC_MMR6 = 1007,	----
1023	BNZ_B = 1008,	----
1024	BNZ_D = 1009,	----
1025	BNZ_H = 1010,	----
1026	BNZ_V = 1011,	----
1027	BNZ_W = 1012,	----
1028	BOVC = 1013,	----
1029	BOVC_MMR6 = 1014,	----
1030	BPOSGE32 = 1015,	----
1031	BPOSGE32C_MMR3 = 1016,	----
1032	BPOSGE32_MM = 1017,	----
1033	BREAK = 1018,	----
1034	BREAK16_MM = 1019,	----
1035	BREAK16_MMR6 = 1020,	----
1036	BREAK_MM = 1021,	----
1037	BREAK_MMR6 = 1022,	----
1038	BSELI_B = 1023,	----
1039	BSEL_V = 1024,	----
1040	BSETI_B = 1025,	----
1041	BSETI_D = 1026,	----
1042	BSETI_H = 1027,	----
1043	BSETI_W = 1028,	----
1044	BSET_B = 1029,	----
1045	BSET_D = 1030,	----
1046	BSET_H = 1031,	----
1047	BSET_W = 1032,	----
1048	BZ_B = 1033,	----
1049	BZ_D = 1034,	----
1050	BZ_H = 1035,	----
1051	BZ_V = 1036,	----
1052	BZ_W = 1037,	----
1053	BeqzRxImm16 = 1038,	----
1054	BeqzRxImmX16 = 1039,	----
1055	Bimm16 = 1040,	----
1056	BimmX16 = 1041,	----
1057	BnezRxImm16 = 1042,	----
1058	BnezRxImmX16 = 1043,	----
1059	Break16 = 1044,	----
1060	Bteqz16 = 1045,	----
1061	BteqzX16 = 1046,	----
1062	Btnez16 = 1047,	----
1063	BtnezX16 = 1048,	----
1064	CACHE = 1049,	----
1065	CACHEE = 1050,	----
1066	CACHEE_MM = 1051,	----
1067	CACHE_MM = 1052,	----
1068	CACHE_MMR6 = 1053,	----
1069	CACHE_R6 = 1054,	----
1070	CEIL_L_D64 = 1055,	----
1071	CEIL_L_D_MMR6 = 1056,	----
1072	CEIL_L_S = 1057,	----
1073	CEIL_L_S_MMR6 = 1058,	----
1074	CEIL_W_D32 = 1059,	----
1075	CEIL_W_D64 = 1060,	----
1076	CEIL_W_D_MMR6 = 1061,	----
1077	CEIL_W_MM = 1062,	----
1078	CEIL_W_S = 1063,	----
1079	CEIL_W_S_MM = 1064,	----
1080	CEIL_W_S_MMR6 = 1065,	----
1081	CEQI_B = 1066,	----
1082	CEQI_D = 1067,	----
1083	CEQI_H = 1068,	----
1084	CEQI_W = 1069,	----
1085	CEQ_B = 1070,	----
1086	CEQ_D = 1071,	----
1087	CEQ_H = 1072,	----
1088	CEQ_W = 1073,	----
1089	CFC1 = 1074,	----
1090	CFC1_MM = 1075,	----
1091	CFC2_MM = 1076,	----
1092	CFCMSA = 1077,	----
1093	CINS = 1078,	----
1094	CINS32 = 1079,	----
1095	CINS64_32 = 1080,	----
1096	CINS_i32 = 1081,	----
1097	CLASS_D = 1082,	----
1098	CLASS_D_MMR6 = 1083,	----
1099	CLASS_S = 1084,	----
1100	CLASS_S_MMR6 = 1085,	----
1101	CLEI_S_B = 1086,	----
1102	CLEI_S_D = 1087,	----
1103	CLEI_S_H = 1088,	----
1104	CLEI_S_W = 1089,	----
1105	CLEI_U_B = 1090,	----
1106	CLEI_U_D = 1091,	----
1107	CLEI_U_H = 1092,	----
1108	CLEI_U_W = 1093,	----
1109	CLE_S_B = 1094,	----
1110	CLE_S_D = 1095,	----
1111	CLE_S_H = 1096,	----
1112	CLE_S_W = 1097,	----
1113	CLE_U_B = 1098,	----
1114	CLE_U_D = 1099,	----
1115	CLE_U_H = 1100,	----
1116	CLE_U_W = 1101,	----
1117	CLO = 1102,	----
1118	CLO_MM = 1103,	----
1119	CLO_MMR6 = 1104,	----
1120	CLO_R6 = 1105,	----
1121	CLTI_S_B = 1106,	----
1122	CLTI_S_D = 1107,	----
1123	CLTI_S_H = 1108,	----
1124	CLTI_S_W = 1109,	----
1125	CLTI_U_B = 1110,	----
1126	CLTI_U_D = 1111,	----
1127	CLTI_U_H = 1112,	----
1128	CLTI_U_W = 1113,	----
1129	CLT_S_B = 1114,	----
1130	CLT_S_D = 1115,	----
1131	CLT_S_H = 1116,	----
1132	CLT_S_W = 1117,	----
1133	CLT_U_B = 1118,	----
1134	CLT_U_D = 1119,	----
1135	CLT_U_H = 1120,	----
1136	CLT_U_W = 1121,	----
1137	CLZ = 1122,	----
1138	CLZ_MM = 1123,	----
1139	CLZ_MMR6 = 1124,	----
1140	CLZ_R6 = 1125,	----
1141	CMPGDU_EQ_QB = 1126,	----
1142	CMPGDU_EQ_QB_MMR2 = 1127,	----
1143	CMPGDU_LE_QB = 1128,	----
1144	CMPGDU_LE_QB_MMR2 = 1129,	----
1145	CMPGDU_LT_QB = 1130,	----
1146	CMPGDU_LT_QB_MMR2 = 1131,	----
1147	CMPGU_EQ_QB = 1132,	----
1148	CMPGU_EQ_QB_MM = 1133,	----
1149	CMPGU_LE_QB = 1134,	----
1150	CMPGU_LE_QB_MM = 1135,	----
1151	CMPGU_LT_QB = 1136,	----
1152	CMPGU_LT_QB_MM = 1137,	----
1153	CMPU_EQ_QB = 1138,	----
1154	CMPU_EQ_QB_MM = 1139,	----
1155	CMPU_LE_QB = 1140,	----
1156	CMPU_LE_QB_MM = 1141,	----
1157	CMPU_LT_QB = 1142,	----
1158	CMPU_LT_QB_MM = 1143,	----
1159	CMP_AF_D_MMR6 = 1144,	----
1160	CMP_AF_S_MMR6 = 1145,	----
1161	CMP_EQ_D = 1146,	----
1162	CMP_EQ_D_MMR6 = 1147,	----
1163	CMP_EQ_PH = 1148,	----
1164	CMP_EQ_PH_MM = 1149,	----
1165	CMP_EQ_S = 1150,	----
1166	CMP_EQ_S_MMR6 = 1151,	----
1167	CMP_F_D = 1152,	----
1168	CMP_F_S = 1153,	----
1169	CMP_LE_D = 1154,	----
1170	CMP_LE_D_MMR6 = 1155,	----
1171	CMP_LE_PH = 1156,	----
1172	CMP_LE_PH_MM = 1157,	----
1173	CMP_LE_S = 1158,	----
1174	CMP_LE_S_MMR6 = 1159,	----
1175	CMP_LT_D = 1160,	----
1176	CMP_LT_D_MMR6 = 1161,	----
1177	CMP_LT_PH = 1162,	----
1178	CMP_LT_PH_MM = 1163,	----
1179	CMP_LT_S = 1164,	----
1180	CMP_LT_S_MMR6 = 1165,	----
1181	CMP_SAF_D = 1166,	----
1182	CMP_SAF_D_MMR6 = 1167,	----
1183	CMP_SAF_S = 1168,	----
1184	CMP_SAF_S_MMR6 = 1169,	----
1185	CMP_SEQ_D = 1170,	----
1186	CMP_SEQ_D_MMR6 = 1171,	----
1187	CMP_SEQ_S = 1172,	----
1188	CMP_SEQ_S_MMR6 = 1173,	----
1189	CMP_SLE_D = 1174,	----
1190	CMP_SLE_D_MMR6 = 1175,	----
1191	CMP_SLE_S = 1176,	----
1192	CMP_SLE_S_MMR6 = 1177,	----
1193	CMP_SLT_D = 1178,	----
1194	CMP_SLT_D_MMR6 = 1179,	----
1195	CMP_SLT_S = 1180,	----
1196	CMP_SLT_S_MMR6 = 1181,	----
1197	CMP_SUEQ_D = 1182,	----
1198	CMP_SUEQ_D_MMR6 = 1183,	----
1199	CMP_SUEQ_S = 1184,	----
1200	CMP_SUEQ_S_MMR6 = 1185,	----
1201	CMP_SULE_D = 1186,	----
1202	CMP_SULE_D_MMR6 = 1187,	----
1203	CMP_SULE_S = 1188,	----
1204	CMP_SULE_S_MMR6 = 1189,	----
1205	CMP_SULT_D = 1190,	----
1206	CMP_SULT_D_MMR6 = 1191,	----
1207	CMP_SULT_S = 1192,	----
1208	CMP_SULT_S_MMR6 = 1193,	----
1209	CMP_SUN_D = 1194,	----
1210	CMP_SUN_D_MMR6 = 1195,	----
1211	CMP_SUN_S = 1196,	----
1212	CMP_SUN_S_MMR6 = 1197,	----
1213	CMP_UEQ_D = 1198,	----
1214	CMP_UEQ_D_MMR6 = 1199,	----
1215	CMP_UEQ_S = 1200,	----
1216	CMP_UEQ_S_MMR6 = 1201,	----
1217	CMP_ULE_D = 1202,	----
1218	CMP_ULE_D_MMR6 = 1203,	----
1219	CMP_ULE_S = 1204,	----
1220	CMP_ULE_S_MMR6 = 1205,	----
1221	CMP_ULT_D = 1206,	----
1222	CMP_ULT_D_MMR6 = 1207,	----
1223	CMP_ULT_S = 1208,	----
1224	CMP_ULT_S_MMR6 = 1209,	----
1225	CMP_UN_D = 1210,	----
1226	CMP_UN_D_MMR6 = 1211,	----
1227	CMP_UN_S = 1212,	----
1228	CMP_UN_S_MMR6 = 1213,	----
1229	COPY_S_B = 1214,	----
1230	COPY_S_D = 1215,	----
1231	COPY_S_H = 1216,	----
1232	COPY_S_W = 1217,	----
1233	COPY_U_B = 1218,	----
1234	COPY_U_H = 1219,	----
1235	COPY_U_W = 1220,	----
1236	CRC32B = 1221,	----
1237	CRC32CB = 1222,	----
1238	CRC32CD = 1223,	----
1239	CRC32CH = 1224,	----
1240	CRC32CW = 1225,	----
1241	CRC32D = 1226,	----
1242	CRC32H = 1227,	----
1243	CRC32W = 1228,	----
1244	CTC1 = 1229,	----
1245	CTC1_MM = 1230,	----
1246	CTC2_MM = 1231,	----
1247	CTCMSA = 1232,	----
1248	CVT_D32_S = 1233,	----
1249	CVT_D32_S_MM = 1234,	----
1250	CVT_D32_W = 1235,	----
1251	CVT_D32_W_MM = 1236,	----
1252	CVT_D64_L = 1237,	----
1253	CVT_D64_S = 1238,	----
1254	CVT_D64_S_MM = 1239,	----
1255	CVT_D64_W = 1240,	----
1256	CVT_D64_W_MM = 1241,	----
1257	CVT_D_L_MMR6 = 1242,	----
1258	CVT_L_D64 = 1243,	----
1259	CVT_L_D64_MM = 1244,	----
1260	CVT_L_D_MMR6 = 1245,	----
1261	CVT_L_S = 1246,	----
1262	CVT_L_S_MM = 1247,	----
1263	CVT_L_S_MMR6 = 1248,	----
1264	CVT_PS_PW64 = 1249,	----
1265	CVT_PS_S64 = 1250,	----
1266	CVT_PW_PS64 = 1251,	----
1267	CVT_S_D32 = 1252,	----
1268	CVT_S_D32_MM = 1253,	----
1269	CVT_S_D64 = 1254,	----
1270	CVT_S_D64_MM = 1255,	----
1271	CVT_S_L = 1256,	----
1272	CVT_S_L_MMR6 = 1257,	----
1273	CVT_S_PL64 = 1258,	----
1274	CVT_S_PU64 = 1259,	----
1275	CVT_S_W = 1260,	----
1276	CVT_S_W_MM = 1261,	----
1277	CVT_S_W_MMR6 = 1262,	----
1278	CVT_W_D32 = 1263,	----
1279	CVT_W_D32_MM = 1264,	----
1280	CVT_W_D64 = 1265,	----
1281	CVT_W_D64_MM = 1266,	----
1282	CVT_W_S = 1267,	----
1283	CVT_W_S_MM = 1268,	----
1284	CVT_W_S_MMR6 = 1269,	----
1285	C_EQ_D32 = 1270,	----
1286	C_EQ_D32_MM = 1271,	----
1287	C_EQ_D64 = 1272,	----
1288	C_EQ_D64_MM = 1273,	----
1289	C_EQ_S = 1274,	----
1290	C_EQ_S_MM = 1275,	----
1291	C_F_D32 = 1276,	----
1292	C_F_D32_MM = 1277,	----
1293	C_F_D64 = 1278,	----
1294	C_F_D64_MM = 1279,	----
1295	C_F_S = 1280,	----
1296	C_F_S_MM = 1281,	----
1297	C_LE_D32 = 1282,	----
1298	C_LE_D32_MM = 1283,	----
1299	C_LE_D64 = 1284,	----
1300	C_LE_D64_MM = 1285,	----
1301	C_LE_S = 1286,	----
1302	C_LE_S_MM = 1287,	----
1303	C_LT_D32 = 1288,	----
1304	C_LT_D32_MM = 1289,	----
1305	C_LT_D64 = 1290,	----
1306	C_LT_D64_MM = 1291,	----
1307	C_LT_S = 1292,	----
1308	C_LT_S_MM = 1293,	----
1309	C_NGE_D32 = 1294,	----
1310	C_NGE_D32_MM = 1295,	----
1311	C_NGE_D64 = 1296,	----
1312	C_NGE_D64_MM = 1297,	----
1313	C_NGE_S = 1298,	----
1314	C_NGE_S_MM = 1299,	----
1315	C_NGLE_D32 = 1300,	----
1316	C_NGLE_D32_MM = 1301,	----
1317	C_NGLE_D64 = 1302,	----
1318	C_NGLE_D64_MM = 1303,	----
1319	C_NGLE_S = 1304,	----
1320	C_NGLE_S_MM = 1305,	----
1321	C_NGL_D32 = 1306,	----
1322	C_NGL_D32_MM = 1307,	----
1323	C_NGL_D64 = 1308,	----
1324	C_NGL_D64_MM = 1309,	----
1325	C_NGL_S = 1310,	----
1326	C_NGL_S_MM = 1311,	----
1327	C_NGT_D32 = 1312,	----
1328	C_NGT_D32_MM = 1313,	----
1329	C_NGT_D64 = 1314,	----
1330	C_NGT_D64_MM = 1315,	----
1331	C_NGT_S = 1316,	----
1332	C_NGT_S_MM = 1317,	----
1333	C_OLE_D32 = 1318,	----
1334	C_OLE_D32_MM = 1319,	----
1335	C_OLE_D64 = 1320,	----
1336	C_OLE_D64_MM = 1321,	----
1337	C_OLE_S = 1322,	----
1338	C_OLE_S_MM = 1323,	----
1339	C_OLT_D32 = 1324,	----
1340	C_OLT_D32_MM = 1325,	----
1341	C_OLT_D64 = 1326,	----
1342	C_OLT_D64_MM = 1327,	----
1343	C_OLT_S = 1328,	----
1344	C_OLT_S_MM = 1329,	----
1345	C_SEQ_D32 = 1330,	----
1346	C_SEQ_D32_MM = 1331,	----
1347	C_SEQ_D64 = 1332,	----
1348	C_SEQ_D64_MM = 1333,	----
1349	C_SEQ_S = 1334,	----
1350	C_SEQ_S_MM = 1335,	----
1351	C_SF_D32 = 1336,	----
1352	C_SF_D32_MM = 1337,	----
1353	C_SF_D64 = 1338,	----
1354	C_SF_D64_MM = 1339,	----
1355	C_SF_S = 1340,	----
1356	C_SF_S_MM = 1341,	----
1357	C_UEQ_D32 = 1342,	----
1358	C_UEQ_D32_MM = 1343,	----
1359	C_UEQ_D64 = 1344,	----
1360	C_UEQ_D64_MM = 1345,	----
1361	C_UEQ_S = 1346,	----
1362	C_UEQ_S_MM = 1347,	----
1363	C_ULE_D32 = 1348,	----
1364	C_ULE_D32_MM = 1349,	----
1365	C_ULE_D64 = 1350,	----
1366	C_ULE_D64_MM = 1351,	----
1367	C_ULE_S = 1352,	----
1368	C_ULE_S_MM = 1353,	----
1369	C_ULT_D32 = 1354,	----
1370	C_ULT_D32_MM = 1355,	----
1371	C_ULT_D64 = 1356,	----
1372	C_ULT_D64_MM = 1357,	----
1373	C_ULT_S = 1358,	----
1374	C_ULT_S_MM = 1359,	----
1375	C_UN_D32 = 1360,	----
1376	C_UN_D32_MM = 1361,	----
1377	C_UN_D64 = 1362,	----
1378	C_UN_D64_MM = 1363,	----
1379	C_UN_S = 1364,	----
1380	C_UN_S_MM = 1365,	----
1381	CmpRxRy16 = 1366,	----
1382	CmpiRxImm16 = 1367,	----
1383	CmpiRxImmX16 = 1368,	----
1384	DADD = 1369,	----
1385	DADDi = 1370,	----
1386	DADDiu = 1371,	----
1387	DADDu = 1372,	----
1388	DAHI = 1373,	----
1389	DALIGN = 1374,	----
1390	DATI = 1375,	----
1391	DAUI = 1376,	----
1392	DBITSWAP = 1377,	----
1393	DCLO = 1378,	----
1394	DCLO_R6 = 1379,	----
1395	DCLZ = 1380,	----
1396	DCLZ_R6 = 1381,	----
1397	DDIV = 1382,	----
1398	DDIVU = 1383,	----
1399	DERET = 1384,	----
1400	DERET_MM = 1385,	----
1401	DERET_MMR6 = 1386,	----
1402	DEXT = 1387,	----
1403	DEXT64_32 = 1388,	----
1404	DEXTM = 1389,	----
1405	DEXTU = 1390,	----
1406	DI = 1391,	----
1407	DINS = 1392,	----
1408	DINSM = 1393,	----
1409	DINSU = 1394,	----
1410	DIV = 1395,	----
1411	DIVU = 1396,	----
1412	DIVU_MMR6 = 1397,	----
1413	DIV_MMR6 = 1398,	----
1414	DIV_S_B = 1399,	----
1415	DIV_S_D = 1400,	----
1416	DIV_S_H = 1401,	----
1417	DIV_S_W = 1402,	----
1418	DIV_U_B = 1403,	----
1419	DIV_U_D = 1404,	----
1420	DIV_U_H = 1405,	----
1421	DIV_U_W = 1406,	----
1422	DI_MM = 1407,	----
1423	DI_MMR6 = 1408,	----
1424	DLSA = 1409,	----
1425	DLSA_R6 = 1410,	----
1426	DMFC0 = 1411,	----
1427	DMFC1 = 1412,	----
1428	DMFC2 = 1413,	----
1429	DMFC2_OCTEON = 1414,	----
1430	DMFGC0 = 1415,	----
1431	DMOD = 1416,	----
1432	DMODU = 1417,	----
1433	DMT = 1418,	----
1434	DMTC0 = 1419,	----
1435	DMTC1 = 1420,	----
1436	DMTC2 = 1421,	----
1437	DMTC2_OCTEON = 1422,	----
1438	DMTGC0 = 1423,	----
1439	DMUH = 1424,	----
1440	DMUHU = 1425,	----
1441	DMUL = 1426,	----
1442	DMULT = 1427,	----
1443	DMULTu = 1428,	----
1444	DMULU = 1429,	----
1445	DMUL_R6 = 1430,	----
1446	DOTP_S_D = 1431,	----
1447	DOTP_S_H = 1432,	----
1448	DOTP_S_W = 1433,	----
1449	DOTP_U_D = 1434,	----
1450	DOTP_U_H = 1435,	----
1451	DOTP_U_W = 1436,	----
1452	DPADD_S_D = 1437,	----
1453	DPADD_S_H = 1438,	----
1454	DPADD_S_W = 1439,	----
1455	DPADD_U_D = 1440,	----
1456	DPADD_U_H = 1441,	----
1457	DPADD_U_W = 1442,	----
1458	DPAQX_SA_W_PH = 1443,	----
1459	DPAQX_SA_W_PH_MMR2 = 1444,	----
1460	DPAQX_S_W_PH = 1445,	----
1461	DPAQX_S_W_PH_MMR2 = 1446,	----
1462	DPAQ_SA_L_W = 1447,	----
1463	DPAQ_SA_L_W_MM = 1448,	----
1464	DPAQ_S_W_PH = 1449,	----
1465	DPAQ_S_W_PH_MM = 1450,	----
1466	DPAU_H_QBL = 1451,	----
1467	DPAU_H_QBL_MM = 1452,	----
1468	DPAU_H_QBR = 1453,	----
1469	DPAU_H_QBR_MM = 1454,	----
1470	DPAX_W_PH = 1455,	----
1471	DPAX_W_PH_MMR2 = 1456,	----
1472	DPA_W_PH = 1457,	----
1473	DPA_W_PH_MMR2 = 1458,	----
1474	DPOP = 1459,	----
1475	DPSQX_SA_W_PH = 1460,	----
1476	DPSQX_SA_W_PH_MMR2 = 1461,	----
1477	DPSQX_S_W_PH = 1462,	----
1478	DPSQX_S_W_PH_MMR2 = 1463,	----
1479	DPSQ_SA_L_W = 1464,	----
1480	DPSQ_SA_L_W_MM = 1465,	----
1481	DPSQ_S_W_PH = 1466,	----
1482	DPSQ_S_W_PH_MM = 1467,	----
1483	DPSUB_S_D = 1468,	----
1484	DPSUB_S_H = 1469,	----
1485	DPSUB_S_W = 1470,	----
1486	DPSUB_U_D = 1471,	----
1487	DPSUB_U_H = 1472,	----
1488	DPSUB_U_W = 1473,	----
1489	DPSU_H_QBL = 1474,	----
1490	DPSU_H_QBL_MM = 1475,	----
1491	DPSU_H_QBR = 1476,	----
1492	DPSU_H_QBR_MM = 1477,	----
1493	DPSX_W_PH = 1478,	----
1494	DPSX_W_PH_MMR2 = 1479,	----
1495	DPS_W_PH = 1480,	----
1496	DPS_W_PH_MMR2 = 1481,	----
1497	DROTR = 1482,	----
1498	DROTR32 = 1483,	----
1499	DROTRV = 1484,	----
1500	DSBH = 1485,	----
1501	DSDIV = 1486,	----
1502	DSHD = 1487,	----
1503	DSLL = 1488,	----
1504	DSLL32 = 1489,	----
1505	DSLL64_32 = 1490,	----
1506	DSLLV = 1491,	----
1507	DSRA = 1492,	----
1508	DSRA32 = 1493,	----
1509	DSRAV = 1494,	----
1510	DSRL = 1495,	----
1511	DSRL32 = 1496,	----
1512	DSRLV = 1497,	----
1513	DSUB = 1498,	----
1514	DSUBu = 1499,	----
1515	DUDIV = 1500,	----
1516	DVP = 1501,	----
1517	DVPE = 1502,	----
1518	DVP_MMR6 = 1503,	----
1519	DivRxRy16 = 1504,	----
1520	DivuRxRy16 = 1505,	----
1521	EHB = 1506,	----
1522	EHB_MM = 1507,	----
1523	EHB_MMR6 = 1508,	----
1524	EI = 1509,	----
1525	EI_MM = 1510,	----
1526	EI_MMR6 = 1511,	----
1527	EMT = 1512,	----
1528	ERET = 1513,	----
1529	ERETNC = 1514,	----
1530	ERETNC_MMR6 = 1515,	----
1531	ERET_MM = 1516,	----
1532	ERET_MMR6 = 1517,	----
1533	EVP = 1518,	----
1534	EVPE = 1519,	----
1535	EVP_MMR6 = 1520,	----
1536	EXT = 1521,	----
1537	EXTP = 1522,	----
1538	EXTPDP = 1523,	----
1539	EXTPDPV = 1524,	----
1540	EXTPDPV_MM = 1525,	----
1541	EXTPDP_MM = 1526,	----
1542	EXTPV = 1527,	----
1543	EXTPV_MM = 1528,	----
1544	EXTP_MM = 1529,	----
1545	EXTRV_RS_W = 1530,	----
1546	EXTRV_RS_W_MM = 1531,	----
1547	EXTRV_R_W = 1532,	----
1548	EXTRV_R_W_MM = 1533,	----
1549	EXTRV_S_H = 1534,	----
1550	EXTRV_S_H_MM = 1535,	----
1551	EXTRV_W = 1536,	----
1552	EXTRV_W_MM = 1537,	----
1553	EXTR_RS_W = 1538,	----
1554	EXTR_RS_W_MM = 1539,	----
1555	EXTR_R_W = 1540,	----
1556	EXTR_R_W_MM = 1541,	----
1557	EXTR_S_H = 1542,	----
1558	EXTR_S_H_MM = 1543,	----
1559	EXTR_W = 1544,	----
1560	EXTR_W_MM = 1545,	----
1561	EXTS = 1546,	----
1562	EXTS32 = 1547,	----
1563	EXT_MM = 1548,	----
1564	EXT_MMR6 = 1549,	----
1565	FABS_D32 = 1550,	----
1566	FABS_D32_MM = 1551,	----
1567	FABS_D64 = 1552,	----
1568	FABS_D64_MM = 1553,	----
1569	FABS_S = 1554,	----
1570	FABS_S_MM = 1555,	----
1571	FADD_D = 1556,	----
1572	FADD_D32 = 1557,	----
1573	FADD_D32_MM = 1558,	----
1574	FADD_D64 = 1559,	----
1575	FADD_D64_MM = 1560,	----
1576	FADD_PS64 = 1561,	----
1577	FADD_S = 1562,	----
1578	FADD_S_MM = 1563,	----
1579	FADD_S_MMR6 = 1564,	----
1580	FADD_W = 1565,	----
1581	FCAF_D = 1566,	----
1582	FCAF_W = 1567,	----
1583	FCEQ_D = 1568,	----
1584	FCEQ_W = 1569,	----
1585	FCLASS_D = 1570,	----
1586	FCLASS_W = 1571,	----
1587	FCLE_D = 1572,	----
1588	FCLE_W = 1573,	----
1589	FCLT_D = 1574,	----
1590	FCLT_W = 1575,	----
1591	FCMP_D32 = 1576,	----
1592	FCMP_D32_MM = 1577,	----
1593	FCMP_D64 = 1578,	----
1594	FCMP_S32 = 1579,	----
1595	FCMP_S32_MM = 1580,	----
1596	FCNE_D = 1581,	----
1597	FCNE_W = 1582,	----
1598	FCOR_D = 1583,	----
1599	FCOR_W = 1584,	----
1600	FCUEQ_D = 1585,	----
1601	FCUEQ_W = 1586,	----
1602	FCULE_D = 1587,	----
1603	FCULE_W = 1588,	----
1604	FCULT_D = 1589,	----
1605	FCULT_W = 1590,	----
1606	FCUNE_D = 1591,	----
1607	FCUNE_W = 1592,	----
1608	FCUN_D = 1593,	----
1609	FCUN_W = 1594,	----
1610	FDIV_D = 1595,	----
1611	FDIV_D32 = 1596,	----
1612	FDIV_D32_MM = 1597,	----
1613	FDIV_D64 = 1598,	----
1614	FDIV_D64_MM = 1599,	----
1615	FDIV_S = 1600,	----
1616	FDIV_S_MM = 1601,	----
1617	FDIV_S_MMR6 = 1602,	----
1618	FDIV_W = 1603,	----
1619	FEXDO_H = 1604,	----
1620	FEXDO_W = 1605,	----
1621	FEXP2_D = 1606,	----
1622	FEXP2_W = 1607,	----
1623	FEXUPL_D = 1608,	----
1624	FEXUPL_W = 1609,	----
1625	FEXUPR_D = 1610,	----
1626	FEXUPR_W = 1611,	----
1627	FFINT_S_D = 1612,	----
1628	FFINT_S_W = 1613,	----
1629	FFINT_U_D = 1614,	----
1630	FFINT_U_W = 1615,	----
1631	FFQL_D = 1616,	----
1632	FFQL_W = 1617,	----
1633	FFQR_D = 1618,	----
1634	FFQR_W = 1619,	----
1635	FILL_B = 1620,	----
1636	FILL_D = 1621,	----
1637	FILL_H = 1622,	----
1638	FILL_W = 1623,	----
1639	FLOG2_D = 1624,	----
1640	FLOG2_W = 1625,	----
1641	FLOOR_L_D64 = 1626,	----
1642	FLOOR_L_D_MMR6 = 1627,	----
1643	FLOOR_L_S = 1628,	----
1644	FLOOR_L_S_MMR6 = 1629,	----
1645	FLOOR_W_D32 = 1630,	----
1646	FLOOR_W_D64 = 1631,	----
1647	FLOOR_W_D_MMR6 = 1632,	----
1648	FLOOR_W_MM = 1633,	----
1649	FLOOR_W_S = 1634,	----
1650	FLOOR_W_S_MM = 1635,	----
1651	FLOOR_W_S_MMR6 = 1636,	----
1652	FMADD_D = 1637,	----
1653	FMADD_W = 1638,	----
1654	FMAX_A_D = 1639,	----
1655	FMAX_A_W = 1640,	----
1656	FMAX_D = 1641,	----
1657	FMAX_W = 1642,	----
1658	FMIN_A_D = 1643,	----
1659	FMIN_A_W = 1644,	----
1660	FMIN_D = 1645,	----
1661	FMIN_W = 1646,	----
1662	FMOV_D32 = 1647,	----
1663	FMOV_D32_MM = 1648,	----
1664	FMOV_D64 = 1649,	----
1665	FMOV_D64_MM = 1650,	----
1666	FMOV_D_MMR6 = 1651,	----
1667	FMOV_S = 1652,	----
1668	FMOV_S_MM = 1653,	----
1669	FMOV_S_MMR6 = 1654,	----
1670	FMSUB_D = 1655,	----
1671	FMSUB_W = 1656,	----
1672	FMUL_D = 1657,	----
1673	FMUL_D32 = 1658,	----
1674	FMUL_D32_MM = 1659,	----
1675	FMUL_D64 = 1660,	----
1676	FMUL_D64_MM = 1661,	----
1677	FMUL_PS64 = 1662,	----
1678	FMUL_S = 1663,	----
1679	FMUL_S_MM = 1664,	----
1680	FMUL_S_MMR6 = 1665,	----
1681	FMUL_W = 1666,	----
1682	FNEG_D32 = 1667,	----
1683	FNEG_D32_MM = 1668,	----
1684	FNEG_D64 = 1669,	----
1685	FNEG_D64_MM = 1670,	----
1686	FNEG_S = 1671,	----
1687	FNEG_S_MM = 1672,	----
1688	FNEG_S_MMR6 = 1673,	----
1689	FORK = 1674,	----
1690	FRCP_D = 1675,	----
1691	FRCP_W = 1676,	----
1692	FRINT_D = 1677,	----
1693	FRINT_W = 1678,	----
1694	FRSQRT_D = 1679,	----
1695	FRSQRT_W = 1680,	----
1696	FSAF_D = 1681,	----
1697	FSAF_W = 1682,	----
1698	FSEQ_D = 1683,	----
1699	FSEQ_W = 1684,	----
1700	FSLE_D = 1685,	----
1701	FSLE_W = 1686,	----
1702	FSLT_D = 1687,	----
1703	FSLT_W = 1688,	----
1704	FSNE_D = 1689,	----
1705	FSNE_W = 1690,	----
1706	FSOR_D = 1691,	----
1707	FSOR_W = 1692,	----
1708	FSQRT_D = 1693,	----
1709	FSQRT_D32 = 1694,	----
1710	FSQRT_D32_MM = 1695,	----
1711	FSQRT_D64 = 1696,	----
1712	FSQRT_D64_MM = 1697,	----
1713	FSQRT_S = 1698,	----
1714	FSQRT_S_MM = 1699,	----
1715	FSQRT_W = 1700,	----
1716	FSUB_D = 1701,	----
1717	FSUB_D32 = 1702,	----
1718	FSUB_D32_MM = 1703,	----
1719	FSUB_D64 = 1704,	----
1720	FSUB_D64_MM = 1705,	----
1721	FSUB_PS64 = 1706,	----
1722	FSUB_S = 1707,	----
1723	FSUB_S_MM = 1708,	----
1724	FSUB_S_MMR6 = 1709,	----
1725	FSUB_W = 1710,	----
1726	FSUEQ_D = 1711,	----
1727	FSUEQ_W = 1712,	----
1728	FSULE_D = 1713,	----
1729	FSULE_W = 1714,	----
1730	FSULT_D = 1715,	----
1731	FSULT_W = 1716,	----
1732	FSUNE_D = 1717,	----
1733	FSUNE_W = 1718,	----
1734	FSUN_D = 1719,	----
1735	FSUN_W = 1720,	----
1736	FTINT_S_D = 1721,	----
1737	FTINT_S_W = 1722,	----
1738	FTINT_U_D = 1723,	----
1739	FTINT_U_W = 1724,	----
1740	FTQ_H = 1725,	----
1741	FTQ_W = 1726,	----
1742	FTRUNC_S_D = 1727,	----
1743	FTRUNC_S_W = 1728,	----
1744	FTRUNC_U_D = 1729,	----
1745	FTRUNC_U_W = 1730,	----
1746	GINVI = 1731,	----
1747	GINVI_MMR6 = 1732,	----
1748	GINVT = 1733,	----
1749	GINVT_MMR6 = 1734,	----
1750	HADD_S_D = 1735,	----
1751	HADD_S_H = 1736,	----
1752	HADD_S_W = 1737,	----
1753	HADD_U_D = 1738,	----
1754	HADD_U_H = 1739,	----
1755	HADD_U_W = 1740,	----
1756	HSUB_S_D = 1741,	----
1757	HSUB_S_H = 1742,	----
1758	HSUB_S_W = 1743,	----
1759	HSUB_U_D = 1744,	----
1760	HSUB_U_H = 1745,	----
1761	HSUB_U_W = 1746,	----
1762	HYPCALL = 1747,	----
1763	HYPCALL_MM = 1748,	----
1764	ILVEV_B = 1749,	----
1765	ILVEV_D = 1750,	----
1766	ILVEV_H = 1751,	----
1767	ILVEV_W = 1752,	----
1768	ILVL_B = 1753,	----
1769	ILVL_D = 1754,	----
1770	ILVL_H = 1755,	----
1771	ILVL_W = 1756,	----
1772	ILVOD_B = 1757,	----
1773	ILVOD_D = 1758,	----
1774	ILVOD_H = 1759,	----
1775	ILVOD_W = 1760,	----
1776	ILVR_B = 1761,	----
1777	ILVR_D = 1762,	----
1778	ILVR_H = 1763,	----
1779	ILVR_W = 1764,	----
1780	INS = 1765,	----
1781	INSERT_B = 1766,	----
1782	INSERT_D = 1767,	----
1783	INSERT_H = 1768,	----
1784	INSERT_W = 1769,	----
1785	INSV = 1770,	----
1786	INSVE_B = 1771,	----
1787	INSVE_D = 1772,	----
1788	INSVE_H = 1773,	----
1789	INSVE_W = 1774,	----
1790	INSV_MM = 1775,	----
1791	INS_MM = 1776,	----
1792	INS_MMR6 = 1777,	----
1793	J = 1778,	----
1794	JAL = 1779,	----
1795	JALR = 1780,	----
1796	JALR16_MM = 1781,	----
1797	JALR64 = 1782,	----
1798	JALRC16_MMR6 = 1783,	----
1799	JALRC_HB_MMR6 = 1784,	----
1800	JALRC_MMR6 = 1785,	----
1801	JALRS16_MM = 1786,	----
1802	JALRS_MM = 1787,	----
1803	JALR_HB = 1788,	----
1804	JALR_HB64 = 1789,	----
1805	JALR_MM = 1790,	----
1806	JALS_MM = 1791,	----
1807	JALX = 1792,	----
1808	JALX_MM = 1793,	----
1809	JAL_MM = 1794,	----
1810	JIALC = 1795,	----
1811	JIALC64 = 1796,	----
1812	JIALC_MMR6 = 1797,	----
1813	JIC = 1798,	----
1814	JIC64 = 1799,	----
1815	JIC_MMR6 = 1800,	----
1816	JR = 1801,	----
1817	JR16_MM = 1802,	----
1818	JR64 = 1803,	----
1819	JRADDIUSP = 1804,	----
1820	JRC16_MM = 1805,	----
1821	JRC16_MMR6 = 1806,	----
1822	JRCADDIUSP_MMR6 = 1807,	----
1823	JR_HB = 1808,	----
1824	JR_HB64 = 1809,	----
1825	JR_HB64_R6 = 1810,	----
1826	JR_HB_R6 = 1811,	----
1827	JR_MM = 1812,	----
1828	J_MM = 1813,	----
1829	Jal16 = 1814,	----
1830	JalB16 = 1815,	----
1831	JrRa16 = 1816,	----
1832	JrcRa16 = 1817,	----
1833	JrcRx16 = 1818,	----
1834	JumpLinkReg16 = 1819,	----
1835	LB = 1820,	----
1836	LB64 = 1821,	----
1837	LBE = 1822,	----
1838	LBE_MM = 1823,	----
1839	LBU16_MM = 1824,	----
1840	LBUX = 1825,	----
1841	LBUX_MM = 1826,	----
1842	LBU_MMR6 = 1827,	----
1843	LB_MM = 1828,	----
1844	LB_MMR6 = 1829,	----
1845	LBu = 1830,	----
1846	LBu64 = 1831,	----
1847	LBuE = 1832,	----
1848	LBuE_MM = 1833,	----
1849	LBu_MM = 1834,	----
1850	LD = 1835,	----
1851	LDC1 = 1836,	----
1852	LDC164 = 1837,	----
1853	LDC1_D64_MMR6 = 1838,	----
1854	LDC1_MM_D32 = 1839,	----
1855	LDC1_MM_D64 = 1840,	----
1856	LDC2 = 1841,	----
1857	LDC2_MMR6 = 1842,	----
1858	LDC2_R6 = 1843,	----
1859	LDC3 = 1844,	----
1860	LDI_B = 1845,	----
1861	LDI_D = 1846,	----
1862	LDI_H = 1847,	----
1863	LDI_W = 1848,	----
1864	LDL = 1849,	----
1865	LDPC = 1850,	----
1866	LDR = 1851,	----
1867	LDXC1 = 1852,	----
1868	LDXC164 = 1853,	----
1869	LD_B = 1854,	----
1870	LD_D = 1855,	----
1871	LD_H = 1856,	----
1872	LD_W = 1857,	----
1873	LEA_ADDiu = 1858,	----
1874	LEA_ADDiu64 = 1859,	----
1875	LEA_ADDiu_MM = 1860,	----
1876	LH = 1861,	----
1877	LH64 = 1862,	----
1878	LHE = 1863,	----
1879	LHE_MM = 1864,	----
1880	LHU16_MM = 1865,	----
1881	LHX = 1866,	----
1882	LHX_MM = 1867,	----
1883	LH_MM = 1868,	----
1884	LHu = 1869,	----
1885	LHu64 = 1870,	----
1886	LHuE = 1871,	----
1887	LHuE_MM = 1872,	----
1888	LHu_MM = 1873,	----
1889	LI16_MM = 1874,	----
1890	LI16_MMR6 = 1875,	----
1891	LL = 1876,	----
1892	LL64 = 1877,	----
1893	LL64_R6 = 1878,	----
1894	LLD = 1879,	----
1895	LLD_R6 = 1880,	----
1896	LLE = 1881,	----
1897	LLE_MM = 1882,	----
1898	LL_MM = 1883,	----
1899	LL_MMR6 = 1884,	----
1900	LL_R6 = 1885,	----
1901	LSA = 1886,	----
1902	LSA_MMR6 = 1887,	----
1903	LSA_R6 = 1888,	----
1904	LUI_MMR6 = 1889,	----
1905	LUXC1 = 1890,	----
1906	LUXC164 = 1891,	----
1907	LUXC1_MM = 1892,	----
1908	LUi = 1893,	----
1909	LUi64 = 1894,	----
1910	LUi_MM = 1895,	----
1911	LW = 1896,	----
1912	LW16_MM = 1897,	----
1913	LW64 = 1898,	----
1914	LWC1 = 1899,	----
1915	LWC1_MM = 1900,	----
1916	LWC2 = 1901,	----
1917	LWC2_MMR6 = 1902,	----
1918	LWC2_R6 = 1903,	----
1919	LWC3 = 1904,	----
1920	LWDSP = 1905,	----
1921	LWDSP_MM = 1906,	----
1922	LWE = 1907,	----
1923	LWE_MM = 1908,	----
1924	LWGP_MM = 1909,	----
1925	LWL = 1910,	----
1926	LWL64 = 1911,	----
1927	LWLE = 1912,	----
1928	LWLE_MM = 1913,	----
1929	LWL_MM = 1914,	----
1930	LWM16_MM = 1915,	----
1931	LWM16_MMR6 = 1916,	----
1932	LWM32_MM = 1917,	----
1933	LWPC = 1918,	----
1934	LWPC_MMR6 = 1919,	----
1935	LWP_MM = 1920,	----
1936	LWR = 1921,	----
1937	LWR64 = 1922,	----
1938	LWRE = 1923,	----
1939	LWRE_MM = 1924,	----
1940	LWR_MM = 1925,	----
1941	LWSP_MM = 1926,	----
1942	LWUPC = 1927,	----
1943	LWU_MM = 1928,	----
1944	LWX = 1929,	----
1945	LWXC1 = 1930,	----
1946	LWXC1_MM = 1931,	----
1947	LWXS_MM = 1932,	----
1948	LWX_MM = 1933,	----
1949	LW_MM = 1934,	----
1950	LW_MMR6 = 1935,	----
1951	LWu = 1936,	----
1952	LbRxRyOffMemX16 = 1937,	----
1953	LbuRxRyOffMemX16 = 1938,	----
1954	LhRxRyOffMemX16 = 1939,	----
1955	LhuRxRyOffMemX16 = 1940,	----
1956	LiRxImm16 = 1941,	----
1957	LiRxImmAlignX16 = 1942,	----
1958	LiRxImmX16 = 1943,	----
1959	LwRxPcTcp16 = 1944,	----
1960	LwRxPcTcpX16 = 1945,	----
1961	LwRxRyOffMemX16 = 1946,	----
1962	LwRxSpImmX16 = 1947,	----
1963	MADD = 1948,	----
1964	MADDF_D = 1949,	----
1965	MADDF_D_MMR6 = 1950,	----
1966	MADDF_S = 1951,	----
1967	MADDF_S_MMR6 = 1952,	----
1968	MADDR_Q_H = 1953,	----
1969	MADDR_Q_W = 1954,	----
1970	MADDU = 1955,	----
1971	MADDU_DSP = 1956,	----
1972	MADDU_DSP_MM = 1957,	----
1973	MADDU_MM = 1958,	----
1974	MADDV_B = 1959,	----
1975	MADDV_D = 1960,	----
1976	MADDV_H = 1961,	----
1977	MADDV_W = 1962,	----
1978	MADD_D32 = 1963,	----
1979	MADD_D32_MM = 1964,	----
1980	MADD_D64 = 1965,	----
1981	MADD_DSP = 1966,	----
1982	MADD_DSP_MM = 1967,	----
1983	MADD_MM = 1968,	----
1984	MADD_Q_H = 1969,	----
1985	MADD_Q_W = 1970,	----
1986	MADD_S = 1971,	----
1987	MADD_S_MM = 1972,	----
1988	MAQ_SA_W_PHL = 1973,	----
1989	MAQ_SA_W_PHL_MM = 1974,	----
1990	MAQ_SA_W_PHR = 1975,	----
1991	MAQ_SA_W_PHR_MM = 1976,	----
1992	MAQ_S_W_PHL = 1977,	----
1993	MAQ_S_W_PHL_MM = 1978,	----
1994	MAQ_S_W_PHR = 1979,	----
1995	MAQ_S_W_PHR_MM = 1980,	----
1996	MAXA_D = 1981,	----
1997	MAXA_D_MMR6 = 1982,	----
1998	MAXA_S = 1983,	----
1999	MAXA_S_MMR6 = 1984,	----
2000	MAXI_S_B = 1985,	----
2001	MAXI_S_D = 1986,	----
2002	MAXI_S_H = 1987,	----
2003	MAXI_S_W = 1988,	----
2004	MAXI_U_B = 1989,	----
2005	MAXI_U_D = 1990,	----
2006	MAXI_U_H = 1991,	----
2007	MAXI_U_W = 1992,	----
2008	MAX_A_B = 1993,	----
2009	MAX_A_D = 1994,	----
2010	MAX_A_H = 1995,	----
2011	MAX_A_W = 1996,	----
2012	MAX_D = 1997,	----
2013	MAX_D_MMR6 = 1998,	----
2014	MAX_S = 1999,	----
2015	MAX_S_B = 2000,	----
2016	MAX_S_D = 2001,	----
2017	MAX_S_H = 2002,	----
2018	MAX_S_MMR6 = 2003,	----
2019	MAX_S_W = 2004,	----
2020	MAX_U_B = 2005,	----
2021	MAX_U_D = 2006,	----
2022	MAX_U_H = 2007,	----
2023	MAX_U_W = 2008,	----
2024	MFC0 = 2009,	----
2025	MFC0_MMR6 = 2010,	----
2026	MFC1 = 2011,	----
2027	MFC1_D64 = 2012,	----
2028	MFC1_MM = 2013,	----
2029	MFC1_MMR6 = 2014,	----
2030	MFC2 = 2015,	----
2031	MFC2_MMR6 = 2016,	----
2032	MFGC0 = 2017,	----
2033	MFGC0_MM = 2018,	----
2034	MFHC0_MMR6 = 2019,	----
2035	MFHC1_D32 = 2020,	----
2036	MFHC1_D32_MM = 2021,	----
2037	MFHC1_D64 = 2022,	----
2038	MFHC1_D64_MM = 2023,	----
2039	MFHC2_MMR6 = 2024,	----
2040	MFHGC0 = 2025,	----
2041	MFHGC0_MM = 2026,	----
2042	MFHI = 2027,	----
2043	MFHI16_MM = 2028,	----
2044	MFHI64 = 2029,	----
2045	MFHI_DSP = 2030,	----
2046	MFHI_DSP_MM = 2031,	----
2047	MFHI_MM = 2032,	----
2048	MFLO = 2033,	----
2049	MFLO16_MM = 2034,	----
2050	MFLO64 = 2035,	----
2051	MFLO_DSP = 2036,	----
2052	MFLO_DSP_MM = 2037,	----
2053	MFLO_MM = 2038,	----
2054	MFTR = 2039,	----
2055	MINA_D = 2040,	----
2056	MINA_D_MMR6 = 2041,	----
2057	MINA_S = 2042,	----
2058	MINA_S_MMR6 = 2043,	----
2059	MINI_S_B = 2044,	----
2060	MINI_S_D = 2045,	----
2061	MINI_S_H = 2046,	----
2062	MINI_S_W = 2047,	----
2063	MINI_U_B = 2048,	----
2064	MINI_U_D = 2049,	----
2065	MINI_U_H = 2050,	----
2066	MINI_U_W = 2051,	----
2067	MIN_A_B = 2052,	----
2068	MIN_A_D = 2053,	----
2069	MIN_A_H = 2054,	----
2070	MIN_A_W = 2055,	----
2071	MIN_D = 2056,	----
2072	MIN_D_MMR6 = 2057,	----
2073	MIN_S = 2058,	----
2074	MIN_S_B = 2059,	----
2075	MIN_S_D = 2060,	----
2076	MIN_S_H = 2061,	----
2077	MIN_S_MMR6 = 2062,	----
2078	MIN_S_W = 2063,	----
2079	MIN_U_B = 2064,	----
2080	MIN_U_D = 2065,	----
2081	MIN_U_H = 2066,	----
2082	MIN_U_W = 2067,	----
2083	MOD = 2068,	----
2084	MODSUB = 2069,	----
2085	MODSUB_MM = 2070,	----
2086	MODU = 2071,	----
2087	MODU_MMR6 = 2072,	----
2088	MOD_MMR6 = 2073,	----
2089	MOD_S_B = 2074,	----
2090	MOD_S_D = 2075,	----
2091	MOD_S_H = 2076,	----
2092	MOD_S_W = 2077,	----
2093	MOD_U_B = 2078,	----
2094	MOD_U_D = 2079,	----
2095	MOD_U_H = 2080,	----
2096	MOD_U_W = 2081,	----
2097	MOVE16_MM = 2082,	----
2098	MOVE16_MMR6 = 2083,	----
2099	MOVEP_MM = 2084,	----
2100	MOVEP_MMR6 = 2085,	----
2101	MOVE_V = 2086,	----
2102	MOVF_D32 = 2087,	----
2103	MOVF_D32_MM = 2088,	----
2104	MOVF_D64 = 2089,	----
2105	MOVF_I = 2090,	----
2106	MOVF_I64 = 2091,	----
2107	MOVF_I_MM = 2092,	----
2108	MOVF_S = 2093,	----
2109	MOVF_S_MM = 2094,	----
2110	MOVN_I64_D64 = 2095,	----
2111	MOVN_I64_I = 2096,	----
2112	MOVN_I64_I64 = 2097,	----
2113	MOVN_I64_S = 2098,	----
2114	MOVN_I_D32 = 2099,	----
2115	MOVN_I_D32_MM = 2100,	----
2116	MOVN_I_D64 = 2101,	----
2117	MOVN_I_I = 2102,	----
2118	MOVN_I_I64 = 2103,	----
2119	MOVN_I_MM = 2104,	----
2120	MOVN_I_S = 2105,	----
2121	MOVN_I_S_MM = 2106,	----
2122	MOVT_D32 = 2107,	----
2123	MOVT_D32_MM = 2108,	----
2124	MOVT_D64 = 2109,	----
2125	MOVT_I = 2110,	----
2126	MOVT_I64 = 2111,	----
2127	MOVT_I_MM = 2112,	----
2128	MOVT_S = 2113,	----
2129	MOVT_S_MM = 2114,	----
2130	MOVZ_I64_D64 = 2115,	----
2131	MOVZ_I64_I = 2116,	----
2132	MOVZ_I64_I64 = 2117,	----
2133	MOVZ_I64_S = 2118,	----
2134	MOVZ_I_D32 = 2119,	----
2135	MOVZ_I_D32_MM = 2120,	----
2136	MOVZ_I_D64 = 2121,	----
2137	MOVZ_I_I = 2122,	----
2138	MOVZ_I_I64 = 2123,	----
2139	MOVZ_I_MM = 2124,	----
2140	MOVZ_I_S = 2125,	----
2141	MOVZ_I_S_MM = 2126,	----
2142	MSUB = 2127,	----
2143	MSUBF_D = 2128,	----
2144	MSUBF_D_MMR6 = 2129,	----
2145	MSUBF_S = 2130,	----
2146	MSUBF_S_MMR6 = 2131,	----
2147	MSUBR_Q_H = 2132,	----
2148	MSUBR_Q_W = 2133,	----
2149	MSUBU = 2134,	----
2150	MSUBU_DSP = 2135,	----
2151	MSUBU_DSP_MM = 2136,	----
2152	MSUBU_MM = 2137,	----
2153	MSUBV_B = 2138,	----
2154	MSUBV_D = 2139,	----
2155	MSUBV_H = 2140,	----
2156	MSUBV_W = 2141,	----
2157	MSUB_D32 = 2142,	----
2158	MSUB_D32_MM = 2143,	----
2159	MSUB_D64 = 2144,	----
2160	MSUB_DSP = 2145,	----
2161	MSUB_DSP_MM = 2146,	----
2162	MSUB_MM = 2147,	----
2163	MSUB_Q_H = 2148,	----
2164	MSUB_Q_W = 2149,	----
2165	MSUB_S = 2150,	----
2166	MSUB_S_MM = 2151,	----
2167	MTC0 = 2152,	----
2168	MTC0_MMR6 = 2153,	----
2169	MTC1 = 2154,	----
2170	MTC1_D64 = 2155,	----
2171	MTC1_D64_MM = 2156,	----
2172	MTC1_MM = 2157,	----
2173	MTC1_MMR6 = 2158,	----
2174	MTC2 = 2159,	----
2175	MTC2_MMR6 = 2160,	----
2176	MTGC0 = 2161,	----
2177	MTGC0_MM = 2162,	----
2178	MTHC0_MMR6 = 2163,	----
2179	MTHC1_D32 = 2164,	----
2180	MTHC1_D32_MM = 2165,	----
2181	MTHC1_D64 = 2166,	----
2182	MTHC1_D64_MM = 2167,	----
2183	MTHC2_MMR6 = 2168,	----
2184	MTHGC0 = 2169,	----
2185	MTHGC0_MM = 2170,	----
2186	MTHI = 2171,	----
2187	MTHI64 = 2172,	----
2188	MTHI_DSP = 2173,	----
2189	MTHI_DSP_MM = 2174,	----
2190	MTHI_MM = 2175,	----
2191	MTHLIP = 2176,	----
2192	MTHLIP_MM = 2177,	----
2193	MTLO = 2178,	----
2194	MTLO64 = 2179,	----
2195	MTLO_DSP = 2180,	----
2196	MTLO_DSP_MM = 2181,	----
2197	MTLO_MM = 2182,	----
2198	MTM0 = 2183,	----
2199	MTM1 = 2184,	----
2200	MTM2 = 2185,	----
2201	MTP0 = 2186,	----
2202	MTP1 = 2187,	----
2203	MTP2 = 2188,	----
2204	MTTR = 2189,	----
2205	MUH = 2190,	----
2206	MUHU = 2191,	----
2207	MUHU_MMR6 = 2192,	----
2208	MUH_MMR6 = 2193,	----
2209	MUL = 2194,	----
2210	MULEQ_S_W_PHL = 2195,	----
2211	MULEQ_S_W_PHL_MM = 2196,	----
2212	MULEQ_S_W_PHR = 2197,	----
2213	MULEQ_S_W_PHR_MM = 2198,	----
2214	MULEU_S_PH_QBL = 2199,	----
2215	MULEU_S_PH_QBL_MM = 2200,	----
2216	MULEU_S_PH_QBR = 2201,	----
2217	MULEU_S_PH_QBR_MM = 2202,	----
2218	MULQ_RS_PH = 2203,	----
2219	MULQ_RS_PH_MM = 2204,	----
2220	MULQ_RS_W = 2205,	----
2221	MULQ_RS_W_MMR2 = 2206,	----
2222	MULQ_S_PH = 2207,	----
2223	MULQ_S_PH_MMR2 = 2208,	----
2224	MULQ_S_W = 2209,	----
2225	MULQ_S_W_MMR2 = 2210,	----
2226	MULR_PS64 = 2211,	----
2227	MULR_Q_H = 2212,	----
2228	MULR_Q_W = 2213,	----
2229	MULSAQ_S_W_PH = 2214,	----
2230	MULSAQ_S_W_PH_MM = 2215,	----
2231	MULSA_W_PH = 2216,	----
2232	MULSA_W_PH_MMR2 = 2217,	----
2233	MULT = 2218,	----
2234	MULTU_DSP = 2219,	----
2235	MULTU_DSP_MM = 2220,	----
2236	MULT_DSP = 2221,	----
2237	MULT_DSP_MM = 2222,	----
2238	MULT_MM = 2223,	----
2239	MULTu = 2224,	----
2240	MULTu_MM = 2225,	----
2241	MULU = 2226,	----
2242	MULU_MMR6 = 2227,	----
2243	MULV_B = 2228,	----
2244	MULV_D = 2229,	----
2245	MULV_H = 2230,	----
2246	MULV_W = 2231,	----
2247	MUL_MM = 2232,	----
2248	MUL_MMR6 = 2233,	----
2249	MUL_PH = 2234,	----
2250	MUL_PH_MMR2 = 2235,	----
2251	MUL_Q_H = 2236,	----
2252	MUL_Q_W = 2237,	----
2253	MUL_R6 = 2238,	----
2254	MUL_S_PH = 2239,	----
2255	MUL_S_PH_MMR2 = 2240,	----
2256	Mfhi16 = 2241,	----
2257	Mflo16 = 2242,	----
2258	Move32R16 = 2243,	----
2259	MoveR3216 = 2244,	----
2260	NLOC_B = 2245,	----
2261	NLOC_D = 2246,	----
2262	NLOC_H = 2247,	----
2263	NLOC_W = 2248,	----
2264	NLZC_B = 2249,	----
2265	NLZC_D = 2250,	----
2266	NLZC_H = 2251,	----
2267	NLZC_W = 2252,	----
2268	NMADD_D32 = 2253,	----
2269	NMADD_D32_MM = 2254,	----
2270	NMADD_D64 = 2255,	----
2271	NMADD_S = 2256,	----
2272	NMADD_S_MM = 2257,	----
2273	NMSUB_D32 = 2258,	----
2274	NMSUB_D32_MM = 2259,	----
2275	NMSUB_D64 = 2260,	----
2276	NMSUB_S = 2261,	----
2277	NMSUB_S_MM = 2262,	----
2278	NOR = 2263,	----
2279	NOR64 = 2264,	----
2280	NORI_B = 2265,	----
2281	NOR_MM = 2266,	----
2282	NOR_MMR6 = 2267,	----
2283	NOR_V = 2268,	----
2284	NOT16_MM = 2269,	----
2285	NOT16_MMR6 = 2270,	----
2286	NegRxRy16 = 2271,	----
2287	NotRxRy16 = 2272,	----
2288	OR = 2273,	----
2289	OR16_MM = 2274,	----
2290	OR16_MMR6 = 2275,	----
2291	OR64 = 2276,	----
2292	ORI_B = 2277,	----
2293	ORI_MMR6 = 2278,	----
2294	OR_MM = 2279,	----
2295	OR_MMR6 = 2280,	----
2296	OR_V = 2281,	----
2297	ORi = 2282,	----
2298	ORi64 = 2283,	----
2299	ORi_MM = 2284,	----
2300	OrRxRxRy16 = 2285,	----
2301	PACKRL_PH = 2286,	----
2302	PACKRL_PH_MM = 2287,	----
2303	PAUSE = 2288,	----
2304	PAUSE_MM = 2289,	----
2305	PAUSE_MMR6 = 2290,	----
2306	PCKEV_B = 2291,	----
2307	PCKEV_D = 2292,	----
2308	PCKEV_H = 2293,	----
2309	PCKEV_W = 2294,	----
2310	PCKOD_B = 2295,	----
2311	PCKOD_D = 2296,	----
2312	PCKOD_H = 2297,	----
2313	PCKOD_W = 2298,	----
2314	PCNT_B = 2299,	----
2315	PCNT_D = 2300,	----
2316	PCNT_H = 2301,	----
2317	PCNT_W = 2302,	----
2318	PICK_PH = 2303,	----
2319	PICK_PH_MM = 2304,	----
2320	PICK_QB = 2305,	----
2321	PICK_QB_MM = 2306,	----
2322	PLL_PS64 = 2307,	----
2323	PLU_PS64 = 2308,	----
2324	POP = 2309,	----
2325	PRECEQU_PH_QBL = 2310,	----
2326	PRECEQU_PH_QBLA = 2311,	----
2327	PRECEQU_PH_QBLA_MM = 2312,	----
2328	PRECEQU_PH_QBL_MM = 2313,	----
2329	PRECEQU_PH_QBR = 2314,	----
2330	PRECEQU_PH_QBRA = 2315,	----
2331	PRECEQU_PH_QBRA_MM = 2316,	----
2332	PRECEQU_PH_QBR_MM = 2317,	----
2333	PRECEQ_W_PHL = 2318,	----
2334	PRECEQ_W_PHL_MM = 2319,	----
2335	PRECEQ_W_PHR = 2320,	----
2336	PRECEQ_W_PHR_MM = 2321,	----
2337	PRECEU_PH_QBL = 2322,	----
2338	PRECEU_PH_QBLA = 2323,	----
2339	PRECEU_PH_QBLA_MM = 2324,	----
2340	PRECEU_PH_QBL_MM = 2325,	----
2341	PRECEU_PH_QBR = 2326,	----
2342	PRECEU_PH_QBRA = 2327,	----
2343	PRECEU_PH_QBRA_MM = 2328,	----
2344	PRECEU_PH_QBR_MM = 2329,	----
2345	PRECRQU_S_QB_PH = 2330,	----
2346	PRECRQU_S_QB_PH_MM = 2331,	----
2347	PRECRQ_PH_W = 2332,	----
2348	PRECRQ_PH_W_MM = 2333,	----
2349	PRECRQ_QB_PH = 2334,	----
2350	PRECRQ_QB_PH_MM = 2335,	----
2351	PRECRQ_RS_PH_W = 2336,	----
2352	PRECRQ_RS_PH_W_MM = 2337,	----
2353	PRECR_QB_PH = 2338,	----
2354	PRECR_QB_PH_MMR2 = 2339,	----
2355	PRECR_SRA_PH_W = 2340,	----
2356	PRECR_SRA_PH_W_MMR2 = 2341,	----
2357	PRECR_SRA_R_PH_W = 2342,	----
2358	PRECR_SRA_R_PH_W_MMR2 = 2343,	----
2359	PREF = 2344,	----
2360	PREFE = 2345,	----
2361	PREFE_MM = 2346,	----
2362	PREFX_MM = 2347,	----
2363	PREF_MM = 2348,	----
2364	PREF_MMR6 = 2349,	----
2365	PREF_R6 = 2350,	----
2366	PREPEND = 2351,	----
2367	PREPEND_MMR2 = 2352,	----
2368	PUL_PS64 = 2353,	----
2369	PUU_PS64 = 2354,	----
2370	RADDU_W_QB = 2355,	----
2371	RADDU_W_QB_MM = 2356,	----
2372	RDDSP = 2357,	----
2373	RDDSP_MM = 2358,	----
2374	RDHWR = 2359,	----
2375	RDHWR64 = 2360,	----
2376	RDHWR_MM = 2361,	----
2377	RDHWR_MMR6 = 2362,	----
2378	RDPGPR_MMR6 = 2363,	----
2379	RECIP_D32 = 2364,	----
2380	RECIP_D32_MM = 2365,	----
2381	RECIP_D64 = 2366,	----
2382	RECIP_D64_MM = 2367,	----
2383	RECIP_S = 2368,	----
2384	RECIP_S_MM = 2369,	----
2385	REPLV_PH = 2370,	----
2386	REPLV_PH_MM = 2371,	----
2387	REPLV_QB = 2372,	----
2388	REPLV_QB_MM = 2373,	----
2389	REPL_PH = 2374,	----
2390	REPL_PH_MM = 2375,	----
2391	REPL_QB = 2376,	----
2392	REPL_QB_MM = 2377,	----
2393	RINT_D = 2378,	----
2394	RINT_D_MMR6 = 2379,	----
2395	RINT_S = 2380,	----
2396	RINT_S_MMR6 = 2381,	----
2397	ROTR = 2382,	----
2398	ROTRV = 2383,	----
2399	ROTRV_MM = 2384,	----
2400	ROTR_MM = 2385,	----
2401	ROUND_L_D64 = 2386,	----
2402	ROUND_L_D_MMR6 = 2387,	----
2403	ROUND_L_S = 2388,	----
2404	ROUND_L_S_MMR6 = 2389,	----
2405	ROUND_W_D32 = 2390,	----
2406	ROUND_W_D64 = 2391,	----
2407	ROUND_W_D_MMR6 = 2392,	----
2408	ROUND_W_MM = 2393,	----
2409	ROUND_W_S = 2394,	----
2410	ROUND_W_S_MM = 2395,	----
2411	ROUND_W_S_MMR6 = 2396,	----
2412	RSQRT_D32 = 2397,	----
2413	RSQRT_D32_MM = 2398,	----
2414	RSQRT_D64 = 2399,	----
2415	RSQRT_D64_MM = 2400,	----
2416	RSQRT_S = 2401,	----
2417	RSQRT_S_MM = 2402,	----
2418	Restore16 = 2403,	----
2419	RestoreX16 = 2404,	----
2420	SAA = 2405,	----
2421	SAAD = 2406,	----
2422	SAT_S_B = 2407,	----
2423	SAT_S_D = 2408,	----
2424	SAT_S_H = 2409,	----
2425	SAT_S_W = 2410,	----
2426	SAT_U_B = 2411,	----
2427	SAT_U_D = 2412,	----
2428	SAT_U_H = 2413,	----
2429	SAT_U_W = 2414,	----
2430	SB = 2415,	----
2431	SB16_MM = 2416,	----
2432	SB16_MMR6 = 2417,	----
2433	SB64 = 2418,	----
2434	SBE = 2419,	----
2435	SBE_MM = 2420,	----
2436	SB_MM = 2421,	----
2437	SB_MMR6 = 2422,	----
2438	SC = 2423,	----
2439	SC64 = 2424,	----
2440	SC64_R6 = 2425,	----
2441	SCD = 2426,	----
2442	SCD_R6 = 2427,	----
2443	SCE = 2428,	----
2444	SCE_MM = 2429,	----
2445	SC_MM = 2430,	----
2446	SC_MMR6 = 2431,	----
2447	SC_R6 = 2432,	----
2448	SD = 2433,	----
2449	SDBBP = 2434,	----
2450	SDBBP16_MM = 2435,	----
2451	SDBBP16_MMR6 = 2436,	----
2452	SDBBP_MM = 2437,	----
2453	SDBBP_MMR6 = 2438,	----
2454	SDBBP_R6 = 2439,	----
2455	SDC1 = 2440,	----
2456	SDC164 = 2441,	----
2457	SDC1_D64_MMR6 = 2442,	----
2458	SDC1_MM_D32 = 2443,	----
2459	SDC1_MM_D64 = 2444,	----
2460	SDC2 = 2445,	----
2461	SDC2_MMR6 = 2446,	----
2462	SDC2_R6 = 2447,	----
2463	SDC3 = 2448,	----
2464	SDIV = 2449,	----
2465	SDIV_MM = 2450,	----
2466	SDL = 2451,	----
2467	SDR = 2452,	----
2468	SDXC1 = 2453,	----
2469	SDXC164 = 2454,	----
2470	SEB = 2455,	----
2471	SEB64 = 2456,	----
2472	SEB_MM = 2457,	----
2473	SEH = 2458,	----
2474	SEH64 = 2459,	----
2475	SEH_MM = 2460,	----
2476	SELEQZ = 2461,	----
2477	SELEQZ64 = 2462,	----
2478	SELEQZ_D = 2463,	----
2479	SELEQZ_D_MMR6 = 2464,	----
2480	SELEQZ_MMR6 = 2465,	----
2481	SELEQZ_S = 2466,	----
2482	SELEQZ_S_MMR6 = 2467,	----
2483	SELNEZ = 2468,	----
2484	SELNEZ64 = 2469,	----
2485	SELNEZ_D = 2470,	----
2486	SELNEZ_D_MMR6 = 2471,	----
2487	SELNEZ_MMR6 = 2472,	----
2488	SELNEZ_S = 2473,	----
2489	SELNEZ_S_MMR6 = 2474,	----
2490	SEL_D = 2475,	----
2491	SEL_D_MMR6 = 2476,	----
2492	SEL_S = 2477,	----
2493	SEL_S_MMR6 = 2478,	----
2494	SEQ = 2479,	----
2495	SEQi = 2480,	----
2496	SH = 2481,	----
2497	SH16_MM = 2482,	----
2498	SH16_MMR6 = 2483,	----
2499	SH64 = 2484,	----
2500	SHE = 2485,	----
2501	SHE_MM = 2486,	----
2502	SHF_B = 2487,	----
2503	SHF_H = 2488,	----
2504	SHF_W = 2489,	----
2505	SHILO = 2490,	----
2506	SHILOV = 2491,	----
2507	SHILOV_MM = 2492,	----
2508	SHILO_MM = 2493,	----
2509	SHLLV_PH = 2494,	----
2510	SHLLV_PH_MM = 2495,	----
2511	SHLLV_QB = 2496,	----
2512	SHLLV_QB_MM = 2497,	----
2513	SHLLV_S_PH = 2498,	----
2514	SHLLV_S_PH_MM = 2499,	----
2515	SHLLV_S_W = 2500,	----
2516	SHLLV_S_W_MM = 2501,	----
2517	SHLL_PH = 2502,	----
2518	SHLL_PH_MM = 2503,	----
2519	SHLL_QB = 2504,	----
2520	SHLL_QB_MM = 2505,	----
2521	SHLL_S_PH = 2506,	----
2522	SHLL_S_PH_MM = 2507,	----
2523	SHLL_S_W = 2508,	----
2524	SHLL_S_W_MM = 2509,	----
2525	SHRAV_PH = 2510,	----
2526	SHRAV_PH_MM = 2511,	----
2527	SHRAV_QB = 2512,	----
2528	SHRAV_QB_MMR2 = 2513,	----
2529	SHRAV_R_PH = 2514,	----
2530	SHRAV_R_PH_MM = 2515,	----
2531	SHRAV_R_QB = 2516,	----
2532	SHRAV_R_QB_MMR2 = 2517,	----
2533	SHRAV_R_W = 2518,	----
2534	SHRAV_R_W_MM = 2519,	----
2535	SHRA_PH = 2520,	----
2536	SHRA_PH_MM = 2521,	----
2537	SHRA_QB = 2522,	----
2538	SHRA_QB_MMR2 = 2523,	----
2539	SHRA_R_PH = 2524,	----
2540	SHRA_R_PH_MM = 2525,	----
2541	SHRA_R_QB = 2526,	----
2542	SHRA_R_QB_MMR2 = 2527,	----
2543	SHRA_R_W = 2528,	----
2544	SHRA_R_W_MM = 2529,	----
2545	SHRLV_PH = 2530,	----
2546	SHRLV_PH_MMR2 = 2531,	----
2547	SHRLV_QB = 2532,	----
2548	SHRLV_QB_MM = 2533,	----
2549	SHRL_PH = 2534,	----
2550	SHRL_PH_MMR2 = 2535,	----
2551	SHRL_QB = 2536,	----
2552	SHRL_QB_MM = 2537,	----
2553	SH_MM = 2538,	----
2554	SH_MMR6 = 2539,	----
2555	SIGRIE = 2540,	----
2556	SIGRIE_MMR6 = 2541,	----
2557	SLDI_B = 2542,	----
2558	SLDI_D = 2543,	----
2559	SLDI_H = 2544,	----
2560	SLDI_W = 2545,	----
2561	SLD_B = 2546,	----
2562	SLD_D = 2547,	----
2563	SLD_H = 2548,	----
2564	SLD_W = 2549,	----
2565	SLL = 2550,	----
2566	SLL16_MM = 2551,	----
2567	SLL16_MMR6 = 2552,	----
2568	SLL64_32 = 2553,	----
2569	SLL64_64 = 2554,	----
2570	SLLI_B = 2555,	----
2571	SLLI_D = 2556,	----
2572	SLLI_H = 2557,	----
2573	SLLI_W = 2558,	----
2574	SLLV = 2559,	----
2575	SLLV_MM = 2560,	----
2576	SLL_B = 2561,	----
2577	SLL_D = 2562,	----
2578	SLL_H = 2563,	----
2579	SLL_MM = 2564,	----
2580	SLL_MMR6 = 2565,	----
2581	SLL_W = 2566,	----
2582	SLT = 2567,	----
2583	SLT64 = 2568,	----
2584	SLT_MM = 2569,	----
2585	SLTi = 2570,	----
2586	SLTi64 = 2571,	----
2587	SLTi_MM = 2572,	----
2588	SLTiu = 2573,	----
2589	SLTiu64 = 2574,	----
2590	SLTiu_MM = 2575,	----
2591	SLTu = 2576,	----
2592	SLTu64 = 2577,	----
2593	SLTu_MM = 2578,	----
2594	SNE = 2579,	----
2595	SNEi = 2580,	----
2596	SPLATI_B = 2581,	----
2597	SPLATI_D = 2582,	----
2598	SPLATI_H = 2583,	----
2599	SPLATI_W = 2584,	----
2600	SPLAT_B = 2585,	----
2601	SPLAT_D = 2586,	----
2602	SPLAT_H = 2587,	----
2603	SPLAT_W = 2588,	----
2604	SRA = 2589,	----
2605	SRAI_B = 2590,	----
2606	SRAI_D = 2591,	----
2607	SRAI_H = 2592,	----
2608	SRAI_W = 2593,	----
2609	SRARI_B = 2594,	----
2610	SRARI_D = 2595,	----
2611	SRARI_H = 2596,	----
2612	SRARI_W = 2597,	----
2613	SRAR_B = 2598,	----
2614	SRAR_D = 2599,	----
2615	SRAR_H = 2600,	----
2616	SRAR_W = 2601,	----
2617	SRAV = 2602,	----
2618	SRAV_MM = 2603,	----
2619	SRA_B = 2604,	----
2620	SRA_D = 2605,	----
2621	SRA_H = 2606,	----
2622	SRA_MM = 2607,	----
2623	SRA_W = 2608,	----
2624	SRL = 2609,	----
2625	SRL16_MM = 2610,	----
2626	SRL16_MMR6 = 2611,	----
2627	SRLI_B = 2612,	----
2628	SRLI_D = 2613,	----
2629	SRLI_H = 2614,	----
2630	SRLI_W = 2615,	----
2631	SRLRI_B = 2616,	----
2632	SRLRI_D = 2617,	----
2633	SRLRI_H = 2618,	----
2634	SRLRI_W = 2619,	----
2635	SRLR_B = 2620,	----
2636	SRLR_D = 2621,	----
2637	SRLR_H = 2622,	----
2638	SRLR_W = 2623,	----
2639	SRLV = 2624,	----
2640	SRLV_MM = 2625,	----
2641	SRL_B = 2626,	----
2642	SRL_D = 2627,	----
2643	SRL_H = 2628,	----
2644	SRL_MM = 2629,	----
2645	SRL_W = 2630,	----
2646	SSNOP = 2631,	----
2647	SSNOP_MM = 2632,	----
2648	SSNOP_MMR6 = 2633,	----
2649	ST_B = 2634,	----
2650	ST_D = 2635,	----
2651	ST_H = 2636,	----
2652	ST_W = 2637,	----
2653	SUB = 2638,	----
2654	SUBQH_PH = 2639,	----
2655	SUBQH_PH_MMR2 = 2640,	----
2656	SUBQH_R_PH = 2641,	----
2657	SUBQH_R_PH_MMR2 = 2642,	----
2658	SUBQH_R_W = 2643,	----
2659	SUBQH_R_W_MMR2 = 2644,	----
2660	SUBQH_W = 2645,	----
2661	SUBQH_W_MMR2 = 2646,	----
2662	SUBQ_PH = 2647,	----
2663	SUBQ_PH_MM = 2648,	----
2664	SUBQ_S_PH = 2649,	----
2665	SUBQ_S_PH_MM = 2650,	----
2666	SUBQ_S_W = 2651,	----
2667	SUBQ_S_W_MM = 2652,	----
2668	SUBSUS_U_B = 2653,	----
2669	SUBSUS_U_D = 2654,	----
2670	SUBSUS_U_H = 2655,	----
2671	SUBSUS_U_W = 2656,	----
2672	SUBSUU_S_B = 2657,	----
2673	SUBSUU_S_D = 2658,	----
2674	SUBSUU_S_H = 2659,	----
2675	SUBSUU_S_W = 2660,	----
2676	SUBS_S_B = 2661,	----
2677	SUBS_S_D = 2662,	----
2678	SUBS_S_H = 2663,	----
2679	SUBS_S_W = 2664,	----
2680	SUBS_U_B = 2665,	----
2681	SUBS_U_D = 2666,	----
2682	SUBS_U_H = 2667,	----
2683	SUBS_U_W = 2668,	----
2684	SUBU16_MM = 2669,	----
2685	SUBU16_MMR6 = 2670,	----
2686	SUBUH_QB = 2671,	----
2687	SUBUH_QB_MMR2 = 2672,	----
2688	SUBUH_R_QB = 2673,	----
2689	SUBUH_R_QB_MMR2 = 2674,	----
2690	SUBU_MMR6 = 2675,	----
2691	SUBU_PH = 2676,	----
2692	SUBU_PH_MMR2 = 2677,	----
2693	SUBU_QB = 2678,	----
2694	SUBU_QB_MM = 2679,	----
2695	SUBU_S_PH = 2680,	----
2696	SUBU_S_PH_MMR2 = 2681,	----
2697	SUBU_S_QB = 2682,	----
2698	SUBU_S_QB_MM = 2683,	----
2699	SUBVI_B = 2684,	----
2700	SUBVI_D = 2685,	----
2701	SUBVI_H = 2686,	----
2702	SUBVI_W = 2687,	----
2703	SUBV_B = 2688,	----
2704	SUBV_D = 2689,	----
2705	SUBV_H = 2690,	----
2706	SUBV_W = 2691,	----
2707	SUB_MM = 2692,	----
2708	SUB_MMR6 = 2693,	----
2709	SUBu = 2694,	----
2710	SUBu_MM = 2695,	----
2711	SUXC1 = 2696,	----
2712	SUXC164 = 2697,	----
2713	SUXC1_MM = 2698,	----
2714	SW = 2699,	----
2715	SW16_MM = 2700,	----
2716	SW16_MMR6 = 2701,	----
2717	SW64 = 2702,	----
2718	SWC1 = 2703,	----
2719	SWC1_MM = 2704,	----
2720	SWC2 = 2705,	----
2721	SWC2_MMR6 = 2706,	----
2722	SWC2_R6 = 2707,	----
2723	SWC3 = 2708,	----
2724	SWDSP = 2709,	----
2725	SWDSP_MM = 2710,	----
2726	SWE = 2711,	----
2727	SWE_MM = 2712,	----
2728	SWL = 2713,	----
2729	SWL64 = 2714,	----
2730	SWLE = 2715,	----
2731	SWLE_MM = 2716,	----
2732	SWL_MM = 2717,	----
2733	SWM16_MM = 2718,	----
2734	SWM16_MMR6 = 2719,	----
2735	SWM32_MM = 2720,	----
2736	SWP_MM = 2721,	----
2737	SWR = 2722,	----
2738	SWR64 = 2723,	----
2739	SWRE = 2724,	----
2740	SWRE_MM = 2725,	----
2741	SWR_MM = 2726,	----
2742	SWSP_MM = 2727,	----
2743	SWSP_MMR6 = 2728,	----
2744	SWXC1 = 2729,	----
2745	SWXC1_MM = 2730,	----
2746	SW_MM = 2731,	----
2747	SW_MMR6 = 2732,	----
2748	SYNC = 2733,	----
2749	SYNCI = 2734,	----
2750	SYNCI_MM = 2735,	----
2751	SYNCI_MMR6 = 2736,	----
2752	SYNC_MM = 2737,	----
2753	SYNC_MMR6 = 2738,	----
2754	SYSCALL = 2739,	----
2755	SYSCALL_MM = 2740,	----
2756	Save16 = 2741,	----
2757	SaveX16 = 2742,	----
2758	SbRxRyOffMemX16 = 2743,	----
2759	SebRx16 = 2744,	----
2760	SehRx16 = 2745,	----
2761	ShRxRyOffMemX16 = 2746,	----
2762	SllX16 = 2747,	----
2763	SllvRxRy16 = 2748,	----
2764	SltRxRy16 = 2749,	----
2765	SltiRxImm16 = 2750,	----
2766	SltiRxImmX16 = 2751,	----
2767	SltiuRxImm16 = 2752,	----
2768	SltiuRxImmX16 = 2753,	----
2769	SltuRxRy16 = 2754,	----
2770	SraX16 = 2755,	----
2771	SravRxRy16 = 2756,	----
2772	SrlX16 = 2757,	----
2773	SrlvRxRy16 = 2758,	----
2774	SubuRxRyRz16 = 2759,	----
2775	SwRxRyOffMemX16 = 2760,	----
2776	SwRxSpImmX16 = 2761,	----
2777	TEQ = 2762,	----
2778	TEQI = 2763,	----
2779	TEQI_MM = 2764,	----
2780	TEQ_MM = 2765,	----
2781	TGE = 2766,	----
2782	TGEI = 2767,	----
2783	TGEIU = 2768,	----
2784	TGEIU_MM = 2769,	----
2785	TGEI_MM = 2770,	----
2786	TGEU = 2771,	----
2787	TGEU_MM = 2772,	----
2788	TGE_MM = 2773,	----
2789	TLBGINV = 2774,	----
2790	TLBGINVF = 2775,	----
2791	TLBGINVF_MM = 2776,	----
2792	TLBGINV_MM = 2777,	----
2793	TLBGP = 2778,	----
2794	TLBGP_MM = 2779,	----
2795	TLBGR = 2780,	----
2796	TLBGR_MM = 2781,	----
2797	TLBGWI = 2782,	----
2798	TLBGWI_MM = 2783,	----
2799	TLBGWR = 2784,	----
2800	TLBGWR_MM = 2785,	----
2801	TLBINV = 2786,	----
2802	TLBINVF = 2787,	----
2803	TLBINVF_MMR6 = 2788,	----
2804	TLBINV_MMR6 = 2789,	----
2805	TLBP = 2790,	----
2806	TLBP_MM = 2791,	----
2807	TLBR = 2792,	----
2808	TLBR_MM = 2793,	----
2809	TLBWI = 2794,	----
2810	TLBWI_MM = 2795,	----
2811	TLBWR = 2796,	----
2812	TLBWR_MM = 2797,	----
2813	TLT = 2798,	----
2814	TLTI = 2799,	----
2815	TLTIU_MM = 2800,	----
2816	TLTI_MM = 2801,	----
2817	TLTU = 2802,	----
2818	TLTU_MM = 2803,	----
2819	TLT_MM = 2804,	----
2820	TNE = 2805,	----
2821	TNEI = 2806,	----
2822	TNEI_MM = 2807,	----
2823	TNE_MM = 2808,	----
2824	TRUNC_L_D64 = 2809,	----
2825	TRUNC_L_D_MMR6 = 2810,	----
2826	TRUNC_L_S = 2811,	----
2827	TRUNC_L_S_MMR6 = 2812,	----
2828	TRUNC_W_D32 = 2813,	----
2829	TRUNC_W_D64 = 2814,	----
2830	TRUNC_W_D_MMR6 = 2815,	----
2831	TRUNC_W_MM = 2816,	----
2832	TRUNC_W_S = 2817,	----
2833	TRUNC_W_S_MM = 2818,	----
2834	TRUNC_W_S_MMR6 = 2819,	----
2835	TTLTIU = 2820,	----
2836	UDIV = 2821,	----
2837	UDIV_MM = 2822,	----
2838	V3MULU = 2823,	----
2839	VMM0 = 2824,	----
2840	VMULU = 2825,	----
2841	VSHF_B = 2826,	----
2842	VSHF_D = 2827,	----
2843	VSHF_H = 2828,	----
2844	VSHF_W = 2829,	----
2845	WAIT = 2830,	----
2846	WAIT_MM = 2831,	----
2847	WAIT_MMR6 = 2832,	----
2848	WRDSP = 2833,	----
2849	WRDSP_MM = 2834,	----
2850	WRPGPR_MMR6 = 2835,	----
2851	WSBH = 2836,	----
2852	WSBH_MM = 2837,	----
2853	WSBH_MMR6 = 2838,	----
2854	XOR = 2839,	----
2855	XOR16_MM = 2840,	----
2856	XOR16_MMR6 = 2841,	----
2857	XOR64 = 2842,	----
2858	XORI_B = 2843,	----
2859	XORI_MMR6 = 2844,	----
2860	XOR_MM = 2845,	----
2861	XOR_MMR6 = 2846,	----
2862	XOR_V = 2847,	----
2863	XORi = 2848,	----
2864	XORi64 = 2849,	----
2865	XORi_MM = 2850,	----
2866	XorRxRxRy16 = 2851,	----
2867	YIELD = 2852,	----
2868	INSTRUCTION_LIST_END = 2853	----
2869	};	----
2870		----
2871	} // end namespace Mips	----
2872	} // end namespace llvm	----
2873	#endif // GET_INSTRINFO_ENUM	----
2874		----
2875	#ifdef GET_INSTRINFO_SCHED_ENUM	----
2876	#undef GET_INSTRINFO_SCHED_ENUM	----
2877	namespace llvm {	----
2878		----
2879	namespace Mips {	----
2880	namespace Sched {	----
2881	enum {	----
2882	NoInstrModel = 0,	----
2883	IIPseudo = 1,	----
2884	II_B = 2,	----
2885	II_BCCZAL = 3,	----
2886	II_MTC1 = 4,	----
2887	II_MFC1 = 5,	----
2888	II_JALR = 6,	----
2889	II_JAL = 7,	----
2890	II_CVT = 8,	----
2891	II_DMULT = 9,	----
2892	II_DMULTU = 10,	----
2893	II_DDIV = 11,	----
2894	II_DDIVU = 12,	----
2895	II_IndirectBranchPseudo = 13,	----
2896	II_MADD = 14,	----
2897	II_MADDU = 15,	----
2898	II_MFHI_MFLO = 16,	----
2899	II_MSUB = 17,	----
2900	II_MSUBU = 18,	----
2901	II_MTHI_MTLO = 19,	----
2902	II_MULT = 20,	----
2903	II_MULTU = 21,	----
2904	II_ReturnPseudo = 22,	----
2905	II_DIV = 23,	----
2906	II_DIVU = 24,	----
2907	II_J = 25,	----
2908	II_JR = 26,	----
2909	II_TRAP = 27,	----
2910	II_ADD = 28,	----
2911	II_ADDIUPC = 29,	----
2912	II_ADDIU = 30,	----
2913	II_ADDR_PS = 31,	----
2914	II_ADDU = 32,	----
2915	II_ADDI = 33,	----
2916	II_ALIGN = 34,	----
2917	II_ALUIPC = 35,	----
2918	II_AND = 36,	----
2919	II_ANDI = 37,	----
2920	II_AUI = 38,	----
2921	II_AUIPC = 39,	----
2922	IIM16Alu = 40,	----
2923	II_BADDU = 41,	----
2924	II_BC = 42,	----
2925	II_BALC = 43,	----
2926	II_BBIT = 44,	----
2927	II_BC1CCZ = 45,	----
2928	II_BC1F = 46,	----
2929	II_BC1FL = 47,	----
2930	II_BC1T = 48,	----
2931	II_BC1TL = 49,	----
2932	II_BC2CCZ = 50,	----
2933	II_BCC = 51,	----
2934	II_BCCC = 52,	----
2935	II_BCCZ = 53,	----
2936	II_BCCZC = 54,	----
2937	II_BCCZALS = 55,	----
2938	II_BITSWAP = 56,	----
2939	II_BREAK = 57,	----
2940	II_CACHE = 58,	----
2941	II_CACHEE = 59,	----
2942	II_CEIL = 60,	----
2943	II_CFC1 = 61,	----
2944	II_CFC2 = 62,	----
2945	II_INS = 63,	----
2946	II_CLASS_D = 64,	----
2947	II_CLASS_S = 65,	----
2948	II_CLO = 66,	----
2949	II_CLZ = 67,	----
2950	II_CMP_CC_D = 68,	----
2951	II_CMP_CC_S = 69,	----
2952	II_CRC32B = 70,	----
2953	II_CRC32CB = 71,	----
2954	II_CRC32CD = 72,	----
2955	II_CRC32CH = 73,	----
2956	II_CRC32CW = 74,	----
2957	II_CRC32D = 75,	----
2958	II_CRC32H = 76,	----
2959	II_CRC32W = 77,	----
2960	II_CTC1 = 78,	----
2961	II_CTC2 = 79,	----
2962	II_C_CC_D = 80,	----
2963	II_C_CC_S = 81,	----
2964	II_DADD = 82,	----
2965	II_DADDI = 83,	----
2966	II_DADDIU = 84,	----
2967	II_DADDU = 85,	----
2968	II_DAHI = 86,	----
2969	II_DALIGN = 87,	----
2970	II_DATI = 88,	----
2971	II_DAUI = 89,	----
2972	II_DBITSWAP = 90,	----
2973	II_DCLO = 91,	----
2974	II_DCLZ = 92,	----
2975	II_DERET = 93,	----
2976	II_EXT = 94,	----
2977	II_DI = 95,	----
2978	II_DLSA = 96,	----
2979	II_DMFC0 = 97,	----
2980	II_DMFC1 = 98,	----
2981	II_DMFC2 = 99,	----
2982	II_DMFGC0 = 100,	----
2983	II_DMOD = 101,	----
2984	II_DMODU = 102,	----
2985	II_DMT = 103,	----
2986	II_DMTC0 = 104,	----
2987	II_DMTC1 = 105,	----
2988	II_DMTC2 = 106,	----
2989	II_DMTGC0 = 107,	----
2990	II_DMUH = 108,	----
2991	II_DMUHU = 109,	----
2992	II_DMUL = 110,	----
2993	II_POP = 111,	----
2994	II_DROTR = 112,	----
2995	II_DROTR32 = 113,	----
2996	II_DROTRV = 114,	----
2997	II_DSBH = 115,	----
2998	II_DSHD = 116,	----
2999	II_DSLL = 117,	----
3000	II_DSLL32 = 118,	----
3001	II_DSLLV = 119,	----
3002	II_DSRA = 120,	----
3003	II_DSRA32 = 121,	----
3004	II_DSRAV = 122,	----
3005	II_DSRL = 123,	----
3006	II_DSRL32 = 124,	----
3007	II_DSRLV = 125,	----
3008	II_DSUB = 126,	----
3009	II_DSUBU = 127,	----
3010	II_DVP = 128,	----
3011	II_DVPE = 129,	----
3012	II_EHB = 130,	----
3013	II_EI = 131,	----
3014	II_EMT = 132,	----
3015	II_ERET = 133,	----
3016	II_ERETNC = 134,	----
3017	II_EVP = 135,	----
3018	II_EVPE = 136,	----
3019	II_ABS = 137,	----
3020	II_SQRT_D = 138,	----
3021	II_ADD_D = 139,	----
3022	II_ADD_PS = 140,	----
3023	II_ADD_S = 141,	----
3024	II_DIV_D = 142,	----
3025	II_DIV_S = 143,	----
3026	II_FLOOR = 144,	----
3027	II_MOV_D = 145,	----
3028	II_MOV_S = 146,	----
3029	II_MUL_D = 147,	----
3030	II_MUL_PS = 148,	----
3031	II_MUL_S = 149,	----
3032	II_NEG = 150,	----
3033	II_FORK = 151,	----
3034	II_SQRT_S = 152,	----
3035	II_SUB_D = 153,	----
3036	II_SUB_PS = 154,	----
3037	II_SUB_S = 155,	----
3038	II_GINVI = 156,	----
3039	II_GINVT = 157,	----
3040	II_HYPCALL = 158,	----
3041	II_JALR_HB = 159,	----
3042	II_JALRC = 160,	----
3043	II_JALRS = 161,	----
3044	II_JALS = 162,	----
3045	II_JIALC = 163,	----
3046	II_JIC = 164,	----
3047	II_JRADDIUSP = 165,	----
3048	II_JRC = 166,	----
3049	II_JR_HB = 167,	----
3050	II_LB = 168,	----
3051	II_LBE = 169,	----
3052	II_LBU = 170,	----
3053	II_LBUE = 171,	----
3054	II_LD = 172,	----
3055	II_LDC1 = 173,	----
3056	II_LDC2 = 174,	----
3057	II_LDC3 = 175,	----
3058	II_LDL = 176,	----
3059	II_LDPC = 177,	----
3060	II_LDR = 178,	----
3061	II_LDXC1 = 179,	----
3062	II_LH = 180,	----
3063	II_LHE = 181,	----
3064	II_LHU = 182,	----
3065	II_LHUE = 183,	----
3066	II_LI = 184,	----
3067	II_LL = 185,	----
3068	II_LLD = 186,	----
3069	II_LLE = 187,	----
3070	II_LSA = 188,	----
3071	II_LUI = 189,	----
3072	II_LUXC1 = 190,	----
3073	II_LW = 191,	----
3074	II_LWC1 = 192,	----
3075	II_LWC2 = 193,	----
3076	II_LWC3 = 194,	----
3077	II_LWE = 195,	----
3078	II_LWL = 196,	----
3079	II_LWLE = 197,	----
3080	II_LWM = 198,	----
3081	II_LWPC = 199,	----
3082	II_LWP = 200,	----
3083	II_LWR = 201,	----
3084	II_LWRE = 202,	----
3085	II_LWUPC = 203,	----
3086	II_LWU = 204,	----
3087	II_LWXC1 = 205,	----
3088	II_LWXS = 206,	----
3089	II_MADDF_D = 207,	----
3090	II_MADDF_S = 208,	----
3091	II_MADD_D = 209,	----
3092	II_MADD_S = 210,	----
3093	II_MAX_D = 211,	----
3094	II_MAXA_D = 212,	----
3095	II_MAX_S = 213,	----
3096	II_MAXA_S = 214,	----
3097	II_MFC0 = 215,	----
3098	II_MFC2 = 216,	----
3099	II_MFGC0 = 217,	----
3100	II_MFHC0 = 218,	----
3101	II_MFHC1 = 219,	----
3102	II_MFHGC0 = 220,	----
3103	II_MFTR = 221,	----
3104	II_MIN_S = 222,	----
3105	II_MINA_D = 223,	----
3106	II_MIN_D = 224,	----
3107	II_MINA_S = 225,	----
3108	II_MOD = 226,	----
3109	II_MODU = 227,	----
3110	II_MOVE = 228,	----
3111	II_MOVF_D = 229,	----
3112	II_MOVF = 230,	----
3113	II_MOVF_S = 231,	----
3114	II_MOVN_D = 232,	----
3115	II_MOVN = 233,	----
3116	II_MOVN_S = 234,	----
3117	II_MOVT_D = 235,	----
3118	II_MOVT = 236,	----
3119	II_MOVT_S = 237,	----
3120	II_MOVZ_D = 238,	----
3121	II_MOVZ = 239,	----
3122	II_MOVZ_S = 240,	----
3123	II_MSUBF_D = 241,	----
3124	II_MSUBF_S = 242,	----
3125	II_MSUB_D = 243,	----
3126	II_MSUB_S = 244,	----
3127	II_MTC0 = 245,	----
3128	II_MTC2 = 246,	----
3129	II_MTGC0 = 247,	----
3130	II_MTHC0 = 248,	----
3131	II_MTHC1 = 249,	----
3132	II_MTHGC0 = 250,	----
3133	II_MTTR = 251,	----
3134	II_MUH = 252,	----
3135	II_MUHU = 253,	----
3136	II_MUL = 254,	----
3137	II_MULR_PS = 255,	----
3138	II_MULU = 256,	----
3139	II_NMADD_D = 257,	----
3140	II_NMADD_S = 258,	----
3141	II_NMSUB_D = 259,	----
3142	II_NMSUB_S = 260,	----
3143	II_NOR = 261,	----
3144	II_NOT = 262,	----
3145	II_OR = 263,	----
3146	II_ORI = 264,	----
3147	II_PAUSE = 265,	----
3148	II_PREF = 266,	----
3149	II_PREFE = 267,	----
3150	II_RDHWR = 268,	----
3151	II_RDPGPR = 269,	----
3152	II_RECIP_D = 270,	----
3153	II_RECIP_S = 271,	----
3154	II_RINT_D = 272,	----
3155	II_RINT_S = 273,	----
3156	II_ROTR = 274,	----
3157	II_ROTRV = 275,	----
3158	II_ROUND = 276,	----
3159	II_RSQRT_D = 277,	----
3160	II_RSQRT_S = 278,	----
3161	II_RESTORE = 279,	----
3162	II_SB = 280,	----
3163	II_SBE = 281,	----
3164	II_SC = 282,	----
3165	II_SCD = 283,	----
3166	II_SCE = 284,	----
3167	II_SD = 285,	----
3168	II_SDBBP = 286,	----
3169	II_SDC1 = 287,	----
3170	II_SDC2 = 288,	----
3171	II_SDC3 = 289,	----
3172	II_SDL = 290,	----
3173	II_SDR = 291,	----
3174	II_SDXC1 = 292,	----
3175	II_SEB = 293,	----
3176	II_SEH = 294,	----
3177	II_SELCCZ = 295,	----
3178	II_SELCCZ_D = 296,	----
3179	II_SELCCZ_S = 297,	----
3180	II_SEL_D = 298,	----
3181	II_SEL_S = 299,	----
3182	II_SEQ_SNE = 300,	----
3183	II_SEQI_SNEI = 301,	----
3184	II_SH = 302,	----
3185	II_SHE = 303,	----
3186	II_SIGRIE = 304,	----
3187	II_SLL = 305,	----
3188	II_SLLV = 306,	----
3189	II_SLT_SLTU = 307,	----
3190	II_SLTI_SLTIU = 308,	----
3191	II_SRA = 309,	----
3192	II_SRAV = 310,	----
3193	II_SRL = 311,	----
3194	II_SRLV = 312,	----
3195	II_SSNOP = 313,	----
3196	II_SUB = 314,	----
3197	II_SUBU = 315,	----
3198	II_SUXC1 = 316,	----
3199	II_SW = 317,	----
3200	II_SWC1 = 318,	----
3201	II_SWC2 = 319,	----
3202	II_SWC3 = 320,	----
3203	II_SWE = 321,	----
3204	II_SWL = 322,	----
3205	II_SWLE = 323,	----
3206	II_SWM = 324,	----
3207	II_SWP = 325,	----
3208	II_SWR = 326,	----
3209	II_SWRE = 327,	----
3210	II_SWXC1 = 328,	----
3211	II_SYNC = 329,	----
3212	II_SYNCI = 330,	----
3213	II_SYSCALL = 331,	----
3214	II_SAVE = 332,	----
3215	II_TEQ = 333,	----
3216	II_TEQI = 334,	----
3217	II_TGE = 335,	----
3218	II_TGEI = 336,	----
3219	II_TGEIU = 337,	----
3220	II_TGEU = 338,	----
3221	II_TLBGINV = 339,	----
3222	II_TLBGINVF = 340,	----
3223	II_TLBGP = 341,	----
3224	II_TLBGR = 342,	----
3225	II_TLBGWI = 343,	----
3226	II_TLBGWR = 344,	----
3227	II_TLBINV = 345,	----
3228	II_TLBINVF = 346,	----
3229	II_TLBP = 347,	----
3230	II_TLBR = 348,	----
3231	II_TLBWI = 349,	----
3232	II_TLBWR = 350,	----
3233	II_TLT = 351,	----
3234	II_TLTI = 352,	----
3235	II_TTLTIU = 353,	----
3236	II_TLTU = 354,	----
3237	II_TNE = 355,	----
3238	II_TNEI = 356,	----
3239	II_TRUNC = 357,	----
3240	II_WAIT = 358,	----
3241	II_WRPGPR = 359,	----
3242	II_WSBH = 360,	----
3243	II_XOR = 361,	----
3244	II_XORI = 362,	----
3245	II_YIELD = 363,	----
3246	AND = 364,	----
3247	LUi = 365,	----
3248	NOR = 366,	----
3249	OR = 367,	----
3250	SLTi_SLTiu = 368,	----
3251	SUB = 369,	----
3252	SUBu = 370,	----
3253	XOR = 371,	----
3254	SSNOP = 372,	----
3255	NOP = 373,	----
3256	B = 374,	----
3257	BAL = 375,	----
3258	BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,	----
3259	BEQ_BEQL_BNE_BNEL = 377,	----
3260	BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,	----
3261	BREAK = 379,	----
3262	DERET = 380,	----
3263	ERET = 381,	----
3264	ERet_RetRA = 382,	----
3265	ERETNC = 383,	----
3266	J_TAILCALL = 384,	----
3267	JR_TAILCALLREG_TAILCALLREGHB = 385,	----
3268	JR_HB = 386,	----
3269	PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,	----
3270	PseudoReturn = 388,	----
3271	SDBBP = 389,	----
3272	SYSCALL = 390,	----
3273	TEQ = 391,	----
3274	TEQI = 392,	----
3275	TGE = 393,	----
3276	TGEI = 394,	----
3277	TGEIU = 395,	----
3278	TGEU = 396,	----
3279	TLT = 397,	----
3280	TLTI = 398,	----
3281	TLTU = 399,	----
3282	TNE = 400,	----
3283	TNEI = 401,	----
3284	TRAP = 402,	----
3285	TTLTIU = 403,	----
3286	WAIT = 404,	----
3287	PAUSE = 405,	----
3288	JAL = 406,	----
3289	JALR_JALRHBPseudo_JALRPseudo = 407,	----
3290	JALR_HB = 408,	----
3291	JALX = 409,	----
3292	TLBINV = 410,	----
3293	TLBINVF = 411,	----
3294	TLBP = 412,	----
3295	TLBR = 413,	----
3296	TLBWI = 414,	----
3297	TLBWR = 415,	----
3298	MFC0 = 416,	----
3299	MTC0 = 417,	----
3300	MFC2 = 418,	----
3301	MTC2 = 419,	----
3302	HYPCALL = 420,	----
3303	MFGC0 = 421,	----
3304	MFHGC0 = 422,	----
3305	MTGC0 = 423,	----
3306	MTHGC0 = 424,	----
3307	TLBGINV = 425,	----
3308	TLBGINVF = 426,	----
3309	TLBGP = 427,	----
3310	TLBGR = 428,	----
3311	TLBGWI = 429,	----
3312	TLBGWR = 430,	----
3313	LB = 431,	----
3314	LBu = 432,	----
3315	LH = 433,	----
3316	LHu = 434,	----
3317	LW = 435,	----
3318	LL = 436,	----
3319	LWC2 = 437,	----
3320	LWC3 = 438,	----
3321	LDC2 = 439,	----
3322	LDC3 = 440,	----
3323	LBE = 441,	----
3324	LBuE = 442,	----
3325	LHE = 443,	----
3326	LHuE = 444,	----
3327	LWE = 445,	----
3328	LLE = 446,	----
3329	LWPC = 447,	----
3330	LWL = 448,	----
3331	LWR = 449,	----
3332	LWLE = 450,	----
3333	LWRE = 451,	----
3334	SB = 452,	----
3335	SH = 453,	----
3336	SW = 454,	----
3337	SWC2 = 455,	----
3338	SWC3 = 456,	----
3339	SDC2 = 457,	----
3340	SDC3 = 458,	----
3341	SC = 459,	----
3342	SBE = 460,	----
3343	SHE = 461,	----
3344	SWE = 462,	----
3345	SCE = 463,	----
3346	SWL = 464,	----
3347	SWR = 465,	----
3348	SWLE = 466,	----
3349	SWRE = 467,	----
3350	PREF = 468,	----
3351	PREFE = 469,	----
3352	CACHE = 470,	----
3353	CACHEE = 471,	----
3354	SYNC = 472,	----
3355	SYNCI = 473,	----
3356	CLO = 474,	----
3357	CLZ = 475,	----
3358	DI = 476,	----
3359	EI = 477,	----
3360	MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,	----
3361	EHB = 479,	----
3362	RDHWR = 480,	----
3363	WSBH = 481,	----
3364	MOVN_I_I = 482,	----
3365	MOVZ_I_I = 483,	----
3366	DIV_PseudoSDIV_SDIV = 484,	----
3367	DIVU_PseudoUDIV_UDIV = 485,	----
3368	MUL = 486,	----
3369	MULT_PseudoMULT = 487,	----
3370	MULTu_PseudoMULTu = 488,	----
3371	MADD_PseudoMADD = 489,	----
3372	MADDU_PseudoMADDU = 490,	----
3373	MSUB_PseudoMSUB = 491,	----
3374	MSUBU_PseudoMSUBU = 492,	----
3375	MTHI_MTLO_PseudoMTLOHI = 493,	----
3376	EXT = 494,	----
3377	INS = 495,	----
3378	ADD = 496,	----
3379	ADDi = 497,	----
3380	ADDiu = 498,	----
3381	ANDi = 499,	----
3382	ORi = 500,	----
3383	ROTR = 501,	----
3384	SEB = 502,	----
3385	SEH = 503,	----
3386	SLT_SLTu = 504,	----
3387	SLL = 505,	----
3388	SRA = 506,	----
3389	SRL = 507,	----
3390	XORi = 508,	----
3391	ADDu = 509,	----
3392	SLLV = 510,	----
3393	SRAV = 511,	----
3394	SRLV = 512,	----
3395	LSA = 513,	----
3396	COPY = 514,	----
3397	VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,	----
3398	BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,	----
3399	BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,	----
3400	INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,	----
3401	SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,	----
3402	BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,	----
3403	BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,	----
3404	BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,	----
3405	BSELI_B_BSEL_V = 523,	----
3406	BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,	----
3407	BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,	----
3408	PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,	----
3409	SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,	----
3410	BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,	----
3411	CFCMSA_CTCMSA = 529,	----
3412	FABS_S_FABS_D32_FABS_D64 = 530,	----
3413	MOVF_D32_MOVF_D64 = 531,	----
3414	MOVF_S = 532,	----
3415	MOVT_D32_MOVT_D64 = 533,	----
3416	MOVT_S = 534,	----
3417	FMOV_D32_FMOV_D64 = 535,	----
3418	FMOV_S = 536,	----
3419	FNEG_S_FNEG_D32_FNEG_D64 = 537,	----
3420	ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,	----
3421	ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,	----
3422	ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,	----
3423	ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,	----
3424	AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,	----
3425	SHF_B_SHF_H_SHF_W = 543,	----
3426	FILL_B_FILL_D_FILL_H_FILL_W = 544,	----
3427	SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,	----
3428	MOVE_V = 546,	----
3429	LDI_B_LDI_D_LDI_H_LDI_W = 547,	----
3430	AND_V_NOR_V_OR_V_XOR_V = 548,	----
3431	ANDI_B_NORI_B_ORI_B_XORI_B = 549,	----
3432	AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,	----
3433	FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,	----
3434	INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,	----
3435	FEXP2_D_FEXP2_W = 553,	----
3436	CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,	----
3437	CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,	----
3438	CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,	----
3439	CMP_UN_D = 557,	----
3440	CMP_UN_S = 558,	----
3441	CMP_UEQ_D = 559,	----
3442	CMP_UEQ_S = 560,	----
3443	CMP_EQ_D = 561,	----
3444	CMP_EQ_S = 562,	----
3445	CMP_LT_D = 563,	----
3446	CMP_LT_S = 564,	----
3447	CMP_ULT_D = 565,	----
3448	CMP_ULT_S = 566,	----
3449	CMP_LE_D = 567,	----
3450	CMP_LE_S = 568,	----
3451	CMP_ULE_D = 569,	----
3452	CMP_ULE_S = 570,	----
3453	FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,	----
3454	FSUEQ_D_FSUEQ_W = 572,	----
3455	FSULE_D_FSULE_W = 573,	----
3456	FSULT_D_FSULT_W = 574,	----
3457	FSUNE_D_FSUNE_W = 575,	----
3458	FSUN_D_FSUN_W = 576,	----
3459	FCAF_D_FCAF_W = 577,	----
3460	FCEQ_D_FCEQ_W = 578,	----
3461	FCLE_D_FCLE_W = 579,	----
3462	FCLT_D_FCLT_W = 580,	----
3463	FCNE_D_FCNE_W = 581,	----
3464	FCOR_D_FCOR_W = 582,	----
3465	FCUEQ_D_FCUEQ_W = 583,	----
3466	FCULE_D_FCULE_W = 584,	----
3467	FCULT_D_FCULT_W = 585,	----
3468	FCUNE_D_FCUNE_W = 586,	----
3469	FCUN_D_FCUN_W = 587,	----
3470	FABS_D_FABS_W = 588,	----
3471	FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,	----
3472	FFQL_D_FFQL_W = 590,	----
3473	FFQR_D_FFQR_W = 591,	----
3474	FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,	----
3475	FRINT_D_FRINT_W = 593,	----
3476	FTQ_H_FTQ_W = 594,	----
3477	FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,	----
3478	FEXDO_H_FEXDO_W = 596,	----
3479	FEXUPL_D_FEXUPL_W = 597,	----
3480	FEXUPR_D_FEXUPR_W = 598,	----
3481	FCLASS_D_FCLASS_W = 599,	----
3482	FMAX_A_D_FMAX_A_W = 600,	----
3483	FMAX_D_FMAX_W = 601,	----
3484	FMIN_A_D_FMIN_A_W = 602,	----
3485	FMIN_D_FMIN_W = 603,	----
3486	FLOG2_D_FLOG2_W = 604,	----
3487	ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,	----
3488	ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,	----
3489	INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,	----
3490	SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,	----
3491	SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,	----
3492	SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,	----
3493	SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,	----
3494	SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,	----
3495	MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,	----
3496	DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,	----
3497	HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,	----
3498	HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,	----
3499	MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,	----
3500	MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,	----
3501	MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,	----
3502	MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,	----
3503	SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,	----
3504	SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,	----
3505	SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,	----
3506	SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,	----
3507	SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,	----
3508	PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,	----
3509	NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,	----
3510	FADD_D32_FADD_D64 = 628,	----
3511	FADD_PS64 = 629,	----
3512	FADD_S = 630,	----
3513	FMUL_D32_FMUL_D64 = 631,	----
3514	FMUL_PS64 = 632,	----
3515	FMUL_S = 633,	----
3516	FSUB_D32_FSUB_D64 = 634,	----
3517	FSUB_PS64 = 635,	----
3518	FSUB_S = 636,	----
3519	TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,	----
3520	CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,	----
3521	CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,	----
3522	C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,	----
3523	C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,	----
3524	FCMP_D32_FCMP_D64 = 642,	----
3525	FCMP_S32 = 643,	----
3526	PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,	----
3527	PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,	----
3528	FDIV_S = 646,	----
3529	FDIV_D32_FDIV_D64 = 647,	----
3530	FSQRT_S = 648,	----
3531	FSQRT_D32_FSQRT_D64 = 649,	----
3532	FRCP_D_FRCP_W = 650,	----
3533	FRSQRT_D_FRSQRT_W = 651,	----
3534	RECIP_D32_RECIP_D64 = 652,	----
3535	RSQRT_D32_RSQRT_D64 = 653,	----
3536	RECIP_S = 654,	----
3537	RSQRT_S = 655,	----
3538	FMADD_D_FMADD_W = 656,	----
3539	FMSUB_D_FMSUB_W = 657,	----
3540	FDIV_W = 658,	----
3541	FDIV_D = 659,	----
3542	FSQRT_W = 660,	----
3543	FSQRT_D = 661,	----
3544	FMUL_D_FMUL_W = 662,	----
3545	FADD_D_FADD_W = 663,	----
3546	FSUB_D_FSUB_W = 664,	----
3547	DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,	----
3548	DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,	----
3549	DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,	----
3550	MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,	----
3551	MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,	----
3552	MULV_B_MULV_D_MULV_H_MULV_W = 670,	----
3553	MADDR_Q_H_MADDR_Q_W = 671,	----
3554	MADD_Q_H_MADD_Q_W = 672,	----
3555	MSUBR_Q_H_MSUBR_Q_W = 673,	----
3556	MSUB_Q_H_MSUB_Q_W = 674,	----
3557	MULR_Q_H_MULR_Q_W = 675,	----
3558	MUL_Q_H_MUL_Q_W = 676,	----
3559	MADD_D32_MADD_D64 = 677,	----
3560	MADD_S = 678,	----
3561	MSUB_D32_MSUB_D64 = 679,	----
3562	MSUB_S = 680,	----
3563	NMADD_D32_NMADD_D64 = 681,	----
3564	NMADD_S = 682,	----
3565	NMSUB_D32_NMSUB_D64 = 683,	----
3566	NMSUB_S = 684,	----
3567	CTC1 = 685,	----
3568	MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,	----
3569	MTHC1_D32_MTHC1_D64 = 687,	----
3570	COPY_U_B_COPY_U_H_COPY_U_W = 688,	----
3571	COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,	----
3572	BC1F = 690,	----
3573	BC1FL = 691,	----
3574	BC1T = 692,	----
3575	BC1TL = 693,	----
3576	CFC1 = 694,	----
3577	MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,	----
3578	MFHC1_D32_MFHC1_D64 = 696,	----
3579	MOVF_I = 697,	----
3580	MOVT_I = 698,	----
3581	SDC1_SDC164 = 699,	----
3582	SDXC1_SDXC164 = 700,	----
3583	SWC1 = 701,	----
3584	SWXC1 = 702,	----
3585	SUXC1_SUXC164 = 703,	----
3586	ST_B_ST_D_ST_H_ST_W = 704,	----
3587	ST_F16 = 705,	----
3588	MOVN_I_D32_MOVN_I_D64 = 706,	----
3589	MOVN_I_S = 707,	----
3590	MOVZ_I_D32_MOVZ_I_D64 = 708,	----
3591	MOVZ_I_S = 709,	----
3592	LDC1_LDC164 = 710,	----
3593	LDXC1_LDXC164 = 711,	----
3594	LWC1 = 712,	----
3595	LWXC1 = 713,	----
3596	LUXC1_LUXC164 = 714,	----
3597	LD_B_LD_D_LD_H_LD_W = 715,	----
3598	LD_F16 = 716,	----
3599	CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,	----
3600	FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,	----
3601	ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,	----
3602	ROTRV = 720,	----
3603	ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,	----
3604	ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,	----
3605	ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,	----
3606	LEA_ADDiu = 724,	----
3607	ADDIUPC = 725,	----
3608	ALIGN = 726,	----
3609	ALUIPC = 727,	----
3610	AUI = 728,	----
3611	AUIPC = 729,	----
3612	BITSWAP = 730,	----
3613	CLO_R6 = 731,	----
3614	CLZ_R6 = 732,	----
3615	LSA_R6 = 733,	----
3616	SELEQZ_SELNEZ = 734,	----
3617	AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,	----
3618	SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,	----
3619	Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,	----
3620	ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,	----
3621	ADDU16_MM_ADDu_MM = 739,	----
3622	ADD_MM = 740,	----
3623	ADDi_MM = 741,	----
3624	AND16_MM_ANDI16_MM_AND_MM = 742,	----
3625	ANDi_MM = 743,	----
3626	CLO_MM = 744,	----
3627	CLZ_MM = 745,	----
3628	EXT_MM = 746,	----
3629	INS_MM = 747,	----
3630	LI16_MM = 748,	----
3631	LUi_MM = 749,	----
3632	MOVE16_MM = 750,	----
3633	MOVEP_MM = 751,	----
3634	NOR_MM = 752,	----
3635	NOT16_MM = 753,	----
3636	OR16_MM_OR_MM = 754,	----
3637	ORi_MM = 755,	----
3638	ROTRV_MM = 756,	----
3639	ROTR_MM = 757,	----
3640	SEB_MM = 758,	----
3641	SEH_MM = 759,	----
3642	SLL16_MM_SLL_MM = 760,	----
3643	SLLV_MM = 761,	----
3644	SLT_MM_SLTu_MM = 762,	----
3645	SLTi_MM_SLTiu_MM = 763,	----
3646	SRAV_MM = 764,	----
3647	SRA_MM = 765,	----
3648	SRL16_MM_SRL_MM = 766,	----
3649	SRLV_MM = 767,	----
3650	SSNOP_MM = 768,	----
3651	SUBU16_MM_SUBu_MM = 769,	----
3652	SUB_MM = 770,	----
3653	WSBH_MM = 771,	----
3654	XOR16_MM_XOR_MM = 772,	----
3655	XORi_MM = 773,	----
3656	ADDIUPC_MMR6 = 774,	----
3657	ADDIU_MMR6 = 775,	----
3658	ADDU16_MMR6_ADDU_MMR6 = 776,	----
3659	ADD_MMR6 = 777,	----
3660	ALIGN_MMR6 = 778,	----
3661	ALUIPC_MMR6 = 779,	----
3662	AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,	----
3663	ANDI_MMR6 = 781,	----
3664	AUIPC_MMR6 = 782,	----
3665	AUI_MMR6 = 783,	----
3666	BITSWAP_MMR6 = 784,	----
3667	CLO_MMR6 = 785,	----
3668	CLZ_MMR6 = 786,	----
3669	EXT_MMR6 = 787,	----
3670	INS_MMR6 = 788,	----
3671	LI16_MMR6 = 789,	----
3672	LSA_MMR6 = 790,	----
3673	LUI_MMR6 = 791,	----
3674	MOVE16_MMR6 = 792,	----
3675	NOR_MMR6 = 793,	----
3676	NOT16_MMR6 = 794,	----
3677	OR16_MMR6_OR_MMR6 = 795,	----
3678	ORI_MMR6 = 796,	----
3679	SELEQZ_MMR6_SELNEZ_MMR6 = 797,	----
3680	SLL16_MMR6_SLL_MMR6 = 798,	----
3681	SRL16_MMR6 = 799,	----
3682	SSNOP_MMR6 = 800,	----
3683	SUBU16_MMR6_SUBU_MMR6 = 801,	----
3684	SUB_MMR6 = 802,	----
3685	WSBH_MMR6 = 803,	----
3686	XOR16_MMR6_XOR_MMR6 = 804,	----
3687	XORI_MMR6 = 805,	----
3688	AND64_ANDi64 = 806,	----
3689	DEXT64_32 = 807,	----
3690	DSLL64_32 = 808,	----
3691	ORi64 = 809,	----
3692	SEB64 = 810,	----
3693	SEH64 = 811,	----
3694	SLL64_32_SLL64_64 = 812,	----
3695	SLT64_SLTu64 = 813,	----
3696	SLTi64_SLTiu64 = 814,	----
3697	XOR64_XORi64 = 815,	----
3698	DADD = 816,	----
3699	DADDi = 817,	----
3700	DADDiu = 818,	----
3701	DADDu = 819,	----
3702	DCLO = 820,	----
3703	DCLZ = 821,	----
3704	DEXT_DEXTM_DEXTU = 822,	----
3705	DINS_DINSM_DINSU = 823,	----
3706	DROTR = 824,	----
3707	DROTR32 = 825,	----
3708	DROTRV = 826,	----
3709	DSBH = 827,	----
3710	DSHD = 828,	----
3711	DSLL = 829,	----
3712	DSLL32 = 830,	----
3713	DSLLV = 831,	----
3714	DSRA = 832,	----
3715	DSRA32 = 833,	----
3716	DSRAV = 834,	----
3717	DSRL = 835,	----
3718	DSRL32 = 836,	----
3719	DSRLV = 837,	----
3720	DSUB = 838,	----
3721	DSUBu = 839,	----
3722	LEA_ADDiu64 = 840,	----
3723	LUi64 = 841,	----
3724	NOR64 = 842,	----
3725	OR64 = 843,	----
3726	DALIGN = 844,	----
3727	DAHI = 845,	----
3728	DATI = 846,	----
3729	DAUI = 847,	----
3730	DCLO_R6 = 848,	----
3731	DCLZ_R6 = 849,	----
3732	DBITSWAP = 850,	----
3733	DLSA_DLSA_R6 = 851,	----
3734	SELEQZ64_SELNEZ64 = 852,	----
3735	MADD = 853,	----
3736	MADDU = 854,	----
3737	MSUB = 855,	----
3738	MSUBU = 856,	----
3739	PseudoMADD_MM = 857,	----
3740	PseudoMADDU_MM = 858,	----
3741	PseudoMSUB_MM = 859,	----
3742	PseudoMSUBU_MM = 860,	----
3743	PseudoMULT_MM = 861,	----
3744	PseudoMULTu_MM = 862,	----
3745	PseudoMULT = 863,	----
3746	PseudoMULTu = 864,	----
3747	PseudoSDIV_SDIV = 865,	----
3748	PseudoUDIV_UDIV = 866,	----
3749	PseudoMFHI_MM_PseudoMFLO_MM = 867,	----
3750	PseudoMTLOHI_MM = 868,	----
3751	MUH = 869,	----
3752	MUHU = 870,	----
3753	MULU = 871,	----
3754	MUL_R6 = 872,	----
3755	MOD = 873,	----
3756	MODU = 874,	----
3757	MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,	----
3758	DivRxRy16 = 876,	----
3759	DivuRxRy16 = 877,	----
3760	MULT_MM = 878,	----
3761	MULTu_MM = 879,	----
3762	MADD_MM = 880,	----
3763	MADDU_MM = 881,	----
3764	MSUB_MM = 882,	----
3765	MSUBU_MM = 883,	----
3766	MUL_MM = 884,	----
3767	SDIV_MM_SDIV_MM_Pseudo = 885,	----
3768	UDIV_MM_UDIV_MM_Pseudo = 886,	----
3769	MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,	----
3770	MOVF_I_MM = 888,	----
3771	MOVT_I_MM = 889,	----
3772	MTHI_MM_MTLO_MM = 890,	----
3773	RDHWR_MM = 891,	----
3774	MUHU_MMR6 = 892,	----
3775	MUH_MMR6 = 893,	----
3776	MULU_MMR6 = 894,	----
3777	MUL_MMR6 = 895,	----
3778	MODU_MMR6 = 896,	----
3779	MOD_MMR6 = 897,	----
3780	DIVU_MMR6 = 898,	----
3781	DIV_MMR6 = 899,	----
3782	RDHWR_MMR6 = 900,	----
3783	DMULU = 901,	----
3784	DMULT_PseudoDMULT = 902,	----
3785	DMULTu_PseudoDMULTu = 903,	----
3786	DSDIV_PseudoDSDIV = 904,	----
3787	DUDIV_PseudoDUDIV = 905,	----
3788	MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,	----
3789	PseudoMTLOHI64 = 907,	----
3790	MTHI64_MTLO64 = 908,	----
3791	RDHWR64 = 909,	----
3792	MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,	----
3793	MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,	----
3794	DMUH = 912,	----
3795	DMUHU = 913,	----
3796	DMUL_R6 = 914,	----
3797	DDIV = 915,	----
3798	DMOD = 916,	----
3799	DDIVU = 917,	----
3800	DMODU = 918,	----
3801	BAL_BR_BLTZAL = 919,	----
3802	BEQ_BNE = 920,	----
3803	BGTZ_BGEZ_BLEZ_BLTZ = 921,	----
3804	J = 922,	----
3805	JR = 923,	----
3806	ERet = 924,	----
3807	BGEZAL = 925,	----
3808	BALC = 926,	----
3809	BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927,	----
3810	JIALC = 928,	----
3811	BC = 929,	----
3812	BC2EQZ_BC2NEZ = 930,	----
3813	BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931,	----
3814	BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932,	----
3815	JIC = 933,	----
3816	JR_HB_R6 = 934,	----
3817	SIGRIE = 935,	----
3818	PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936,	----
3819	TAILCALLR6REG_TAILCALLHBR6REG = 937,	----
3820	SDBBP_R6 = 938,	----
3821	Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939,	----
3822	BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940,	----
3823	Jal16_JalB16 = 941,	----
3824	JumpLinkReg16 = 942,	----
3825	Break16 = 943,	----
3826	SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944,	----
3827	B16_MM_B_MM = 945,	----
3828	BAL_BR_MM = 946,	----
3829	BC1F_MM = 947,	----
3830	BC1T_MM = 948,	----
3831	BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949,	----
3832	BEQZC_MM_BNEZC_MM = 950,	----
3833	BEQ_MM_BNE_MM = 951,	----
3834	DERET_MM = 952,	----
3835	ERET_MM = 953,	----
3836	JR16_MM_JR_MM = 954,	----
3837	J_MM = 955,	----
3838	B_MM_Pseudo = 956,	----
3839	BGEZALS_MM_BLTZALS_MM = 957,	----
3840	BGEZAL_MM_BLTZAL_MM = 958,	----
3841	JALR16_MM_JALR_MM = 959,	----
3842	JALRS16_MM_JALRS_MM = 960,	----
3843	JALS_MM = 961,	----
3844	JALX_MM_JAL_MM = 962,	----
3845	TAILCALLREG_MM = 963,	----
3846	TAILCALL_MM = 964,	----
3847	PseudoIndirectBranch_MM = 965,	----
3848	BREAK16_MM_BREAK_MM = 966,	----
3849	SDBBP16_MM_SDBBP_MM = 967,	----
3850	SYSCALL_MM = 968,	----
3851	TEQI_MM = 969,	----
3852	TEQ_MM = 970,	----
3853	TGEIU_MM = 971,	----
3854	TGEI_MM = 972,	----
3855	TGEU_MM = 973,	----
3856	TGE_MM = 974,	----
3857	TLTIU_MM = 975,	----
3858	TLTI_MM = 976,	----
3859	TLTU_MM = 977,	----
3860	TLT_MM = 978,	----
3861	TNEI_MM = 979,	----
3862	TNE_MM = 980,	----
3863	TRAP_MM = 981,	----
3864	BC16_MMR6_BC_MMR6 = 982,	----
3865	BC1EQZC_MMR6_BC1NEZC_MMR6 = 983,	----
3866	BC2EQZC_MMR6_BC2NEZC_MMR6 = 984,	----
3867	BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985,	----
3868	BEQZC16_MMR6_BNEZC16_MMR6 = 986,	----
3869	BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987,	----
3870	DERET_MMR6 = 988,	----
3871	ERETNC_MMR6 = 989,	----
3872	JAL_MMR6 = 990,	----
3873	ERET_MMR6 = 991,	----
3874	JIC_MMR6 = 992,	----
3875	JRADDIUSP_JRCADDIUSP_MMR6 = 993,	----
3876	JRC16_MM = 994,	----
3877	JRC16_MMR6 = 995,	----
3878	SIGRIE_MMR6 = 996,	----
3879	B_MMR6_Pseudo = 997,	----
3880	PseudoIndirectBranch_MMR6 = 998,	----
3881	BALC_MMR6 = 999,	----
3882	BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000,	----
3883	JALRC16_MMR6 = 1001,	----
3884	JALRC_HB_MMR6 = 1002,	----
3885	JALRC_MMR6 = 1003,	----
3886	JIALC_MMR6 = 1004,	----
3887	TAILCALLREG_MMR6 = 1005,	----
3888	TAILCALL_MMR6 = 1006,	----
3889	BREAK16_MMR6_BREAK_MMR6 = 1007,	----
3890	SDBBP_MMR6_SDBBP16_MMR6 = 1008,	----
3891	BEQ64_BNE64 = 1009,	----
3892	BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010,	----
3893	JR64 = 1011,	----
3894	JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012,	----
3895	JALR_HB64 = 1013,	----
3896	JR_HB64 = 1014,	----
3897	TAILCALLREG64_TAILCALLREGHB64 = 1015,	----
3898	PseudoReturn64 = 1016,	----
3899	BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017,	----
3900	BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018,	----
3901	JIC64 = 1019,	----
3902	PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020,	----
3903	JIALC64 = 1021,	----
3904	JR_HB64_R6 = 1022,	----
3905	TAILCALL64R6REG_TAILCALLHB64R6REG = 1023,	----
3906	PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024,	----
3907	EVP = 1025,	----
3908	DVP = 1026,	----
3909	TLBP_MM = 1027,	----
3910	TLBR_MM = 1028,	----
3911	TLBWI_MM = 1029,	----
3912	TLBWR_MM = 1030,	----
3913	DI_MM = 1031,	----
3914	EI_MM = 1032,	----
3915	EHB_MM = 1033,	----
3916	PAUSE_MM = 1034,	----
3917	WAIT_MM = 1035,	----
3918	RDPGPR_MMR6 = 1036,	----
3919	WRPGPR_MMR6 = 1037,	----
3920	TLBINV_MMR6 = 1038,	----
3921	TLBINVF_MMR6 = 1039,	----
3922	MFHC0_MMR6 = 1040,	----
3923	MFC0_MMR6 = 1041,	----
3924	MFHC2_MMR6_MFC2_MMR6 = 1042,	----
3925	MTHC0_MMR6 = 1043,	----
3926	MTC0_MMR6 = 1044,	----
3927	MTHC2_MMR6_MTC2_MMR6 = 1045,	----
3928	EVP_MMR6 = 1046,	----
3929	DVP_MMR6 = 1047,	----
3930	DI_MMR6 = 1048,	----
3931	EI_MMR6 = 1049,	----
3932	EHB_MMR6 = 1050,	----
3933	PAUSE_MMR6 = 1051,	----
3934	WAIT_MMR6 = 1052,	----
3935	DMFC0 = 1053,	----
3936	DMTC0 = 1054,	----
3937	DMFC2 = 1055,	----
3938	DMTC2 = 1056,	----
3939	CFC2_MM = 1057,	----
3940	CTC2_MM = 1058,	----
3941	DMT = 1059,	----
3942	DVPE = 1060,	----
3943	EMT = 1061,	----
3944	EVPE = 1062,	----
3945	MFTR = 1063,	----
3946	MTTR = 1064,	----
3947	YIELD = 1065,	----
3948	FORK = 1066,	----
3949	DMFGC0 = 1067,	----
3950	DMTGC0 = 1068,	----
3951	HYPCALL_MM = 1069,	----
3952	TLBGINVF_MM = 1070,	----
3953	TLBGINV_MM = 1071,	----
3954	TLBGP_MM = 1072,	----
3955	TLBGR_MM = 1073,	----
3956	TLBGWI_MM = 1074,	----
3957	TLBGWR_MM = 1075,	----
3958	MFGC0_MM = 1076,	----
3959	MFHGC0_MM = 1077,	----
3960	MTGC0_MM = 1078,	----
3961	MTHGC0_MM = 1079,	----
3962	SC_MMR6 = 1080,	----
3963	LDC2_R6 = 1081,	----
3964	LL_R6 = 1082,	----
3965	LWC2_R6 = 1083,	----
3966	SWC2_R6 = 1084,	----
3967	SDC2_R6 = 1085,	----
3968	SC_R6 = 1086,	----
3969	PREF_R6 = 1087,	----
3970	CACHE_R6 = 1088,	----
3971	GINVI = 1089,	----
3972	GINVT = 1090,	----
3973	LBE_MM = 1091,	----
3974	LBuE_MM = 1092,	----
3975	LHE_MM = 1093,	----
3976	LHuE_MM = 1094,	----
3977	LWE_MM = 1095,	----
3978	LWLE_MM = 1096,	----
3979	LWRE_MM = 1097,	----
3980	LLE_MM = 1098,	----
3981	SBE_MM = 1099,	----
3982	SB_MM = 1100,	----
3983	SHE_MM = 1101,	----
3984	SWE_MM = 1102,	----
3985	SWLE_MM = 1103,	----
3986	SWRE_MM = 1104,	----
3987	SCE_MM = 1105,	----
3988	PREFE_MM = 1106,	----
3989	CACHEE_MM = 1107,	----
3990	Restore16_RestoreX16 = 1108,	----
3991	LbRxRyOffMemX16 = 1109,	----
3992	LbuRxRyOffMemX16 = 1110,	----
3993	LhRxRyOffMemX16 = 1111,	----
3994	LhuRxRyOffMemX16 = 1112,	----
3995	LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113,	----
3996	Save16_SaveX16 = 1114,	----
3997	SbRxRyOffMemX16 = 1115,	----
3998	ShRxRyOffMemX16 = 1116,	----
3999	SwRxRyOffMemX16_SwRxSpImmX16 = 1117,	----
4000	LBU16_MM_LBu_MM = 1118,	----
4001	LB_MM = 1119,	----
4002	LHU16_MM_LHu_MM = 1120,	----
4003	LH_MM = 1121,	----
4004	LL_MM = 1122,	----
4005	LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123,	----
4006	LWL_MM = 1124,	----
4007	LWM16_MM_LWM32_MM = 1125,	----
4008	LWP_MM = 1126,	----
4009	LWR_MM = 1127,	----
4010	LWU_MM = 1128,	----
4011	LWXS_MM = 1129,	----
4012	SB16_MM = 1130,	----
4013	SC_MM = 1131,	----
4014	SH16_MM_SH_MM = 1132,	----
4015	SW16_MM_SWSP_MM_SW_MM = 1133,	----
4016	SWL_MM = 1134,	----
4017	SWM16_MM_SWM32_MM = 1135,	----
4018	SWM_MM = 1136,	----
4019	SWP_MM = 1137,	----
4020	SWR_MM = 1138,	----
4021	PREF_MM_PREFX_MM = 1139,	----
4022	CACHE_MM = 1140,	----
4023	SYNC_MM = 1141,	----
4024	SYNCI_MM = 1142,	----
4025	GINVI_MMR6 = 1143,	----
4026	GINVT_MMR6 = 1144,	----
4027	LBU_MMR6 = 1145,	----
4028	LB_MMR6 = 1146,	----
4029	LDC2_MMR6 = 1147,	----
4030	LL_MMR6 = 1148,	----
4031	LWM16_MMR6 = 1149,	----
4032	LWC2_MMR6 = 1150,	----
4033	LWPC_MMR6 = 1151,	----
4034	LW_MMR6 = 1152,	----
4035	SB16_MMR6_SB_MMR6 = 1153,	----
4036	SDC2_MMR6 = 1154,	----
4037	SH16_MMR6_SH_MMR6 = 1155,	----
4038	SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156,	----
4039	SWC2_MMR6 = 1157,	----
4040	SWM16_MMR6 = 1158,	----
4041	SYNC_MMR6 = 1159,	----
4042	SYNCI_MMR6 = 1160,	----
4043	PREF_MMR6 = 1161,	----
4044	CACHE_MMR6 = 1162,	----
4045	LD = 1163,	----
4046	LL64_LLD = 1164,	----
4047	LWu = 1165,	----
4048	LB64 = 1166,	----
4049	LBu64 = 1167,	----
4050	LH64 = 1168,	----
4051	LHu64 = 1169,	----
4052	LW64 = 1170,	----
4053	LWL64 = 1171,	----
4054	LWR64 = 1172,	----
4055	LDL = 1173,	----
4056	LDR = 1174,	----
4057	SD = 1175,	----
4058	SC64_SCD = 1176,	----
4059	SB64 = 1177,	----
4060	SH64 = 1178,	----
4061	SW64 = 1179,	----
4062	SWL64 = 1180,	----
4063	SWR64 = 1181,	----
4064	SDL = 1182,	----
4065	SDR = 1183,	----
4066	LWUPC = 1184,	----
4067	LDPC = 1185,	----
4068	LLD_R6 = 1186,	----
4069	LL64_R6 = 1187,	----
4070	SC64_R6 = 1188,	----
4071	SCD_R6 = 1189,	----
4072	CRC32B = 1190,	----
4073	CRC32H = 1191,	----
4074	CRC32W = 1192,	----
4075	CRC32CB = 1193,	----
4076	CRC32CH = 1194,	----
4077	CRC32CW = 1195,	----
4078	CRC32D = 1196,	----
4079	CRC32CD = 1197,	----
4080	BADDu = 1198,	----
4081	BBIT0_BBIT032_BBIT1_BBIT132 = 1199,	----
4082	CINS_CINS32_CINS64_32_CINS_i32 = 1200,	----
4083	DMFC2_OCTEON = 1201,	----
4084	DMTC2_OCTEON = 1202,	----
4085	DPOP_POP = 1203,	----
4086	EXTS_EXTS32 = 1204,	----
4087	MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205,	----
4088	SEQ_SNE = 1206,	----
4089	SEQi_SNEi = 1207,	----
4090	V3MULU_VMM0_VMULU = 1208,	----
4091	DMUL = 1209,	----
4092	SAA_SAAD = 1210,	----
4093	ADDR_PS64 = 1211,	----
4094	CVT_PS_PW64_CVT_PW_PS64 = 1212,	----
4095	MULR_PS64 = 1213,	----
4096	PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214,	----
4097	MOVT_I64 = 1215,	----
4098	MOVF_I64 = 1216,	----
4099	MOVZ_I64_S = 1217,	----
4100	MOVN_I64_D64 = 1218,	----
4101	MOVN_I64_S = 1219,	----
4102	MOVZ_I64_D64 = 1220,	----
4103	SELEQZ_S_SELNEZ_S = 1221,	----
4104	SELEQZ_D_SELNEZ_D = 1222,	----
4105	MAX_S_MAXA_S = 1223,	----
4106	MAX_D_MAXA_D = 1224,	----
4107	MIN_S_MINA_D = 1225,	----
4108	MIN_D_MINA_S = 1226,	----
4109	CLASS_S = 1227,	----
4110	CLASS_D = 1228,	----
4111	RINT_S = 1229,	----
4112	RINT_D = 1230,	----
4113	BC1EQZ_BC1NEZ = 1231,	----
4114	SEL_D = 1232,	----
4115	SEL_S = 1233,	----
4116	MADDF_S = 1234,	----
4117	MSUBF_S = 1235,	----
4118	MADDF_D = 1236,	----
4119	MSUBF_D = 1237,	----
4120	MOVF_D32_MM = 1238,	----
4121	MOVF_S_MM = 1239,	----
4122	MOVN_I_D32_MM = 1240,	----
4123	MOVN_I_S_MM = 1241,	----
4124	MOVT_D32_MM = 1242,	----
4125	MOVT_S_MM = 1243,	----
4126	MOVZ_I_D32_MM = 1244,	----
4127	MOVZ_I_S_MM = 1245,	----
4128	CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246,	----
4129	CEIL_W_MM_CEIL_W_S_MM = 1247,	----
4130	FLOOR_W_MM_FLOOR_W_S_MM = 1248,	----
4131	NMADD_S_MM = 1249,	----
4132	NMADD_D32_MM = 1250,	----
4133	NMSUB_S_MM = 1251,	----
4134	NMSUB_D32_MM = 1252,	----
4135	MADD_S_MM = 1253,	----
4136	MADD_D32_MM = 1254,	----
4137	ROUND_W_MM_ROUND_W_S_MM = 1255,	----
4138	TRUNC_W_MM_TRUNC_W_S_MM = 1256,	----
4139	C_F_D32_MM_C_F_D64_MM = 1257,	----
4140	C_F_S_MM = 1258,	----
4141	C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259,	----
4142	C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260,	----
4143	C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261,	----
4144	C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262,	----
4145	C_NGLE_D32_MM_C_NGLE_D64_MM = 1263,	----
4146	C_NGLE_S_MM = 1264,	----
4147	FCMP_S32_MM = 1265,	----
4148	FCMP_D32_MM = 1266,	----
4149	MFC1_MM = 1267,	----
4150	MFHC1_D32_MM_MFHC1_D64_MM = 1268,	----
4151	MTC1_MM_MTC1_D64_MM = 1269,	----
4152	MTHC1_D32_MM_MTHC1_D64_MM = 1270,	----
4153	FABS_D32_MM_FABS_D64_MM = 1271,	----
4154	FABS_S_MM = 1272,	----
4155	FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273,	----
4156	FADD_D32_MM_FADD_D64_MM = 1274,	----
4157	FADD_S_MM = 1275,	----
4158	FMOV_D32_MM_FMOV_D64_MM = 1276,	----
4159	FMOV_S_MM = 1277,	----
4160	FMUL_D32_MM_FMUL_D64_MM = 1278,	----
4161	FMUL_S_MM = 1279,	----
4162	FSUB_D32_MM_FSUB_D64_MM = 1280,	----
4163	FSUB_S_MM = 1281,	----
4164	MSUB_S_MM = 1282,	----
4165	MSUB_D32_MM = 1283,	----
4166	FDIV_S_MM = 1284,	----
4167	FDIV_D32_MM_FDIV_D64_MM = 1285,	----
4168	FSQRT_S_MM = 1286,	----
4169	FSQRT_D32_MM_FSQRT_D64_MM = 1287,	----
4170	RECIP_S_MM_RSQRT_S_MM = 1288,	----
4171	RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289,	----
4172	SDC1_MM_D32_SDC1_MM_D64 = 1290,	----
4173	SWC1_MM = 1291,	----
4174	SUXC1_MM = 1292,	----
4175	SWXC1_MM = 1293,	----
4176	CFC1_MM = 1294,	----
4177	CTC1_MM = 1295,	----
4178	LDC1_MM_D32_LDC1_MM_D64 = 1296,	----
4179	LUXC1_MM = 1297,	----
4180	LWC1_MM = 1298,	----
4181	LWXC1_MM = 1299,	----
4182	FNEG_S_MMR6 = 1300,	----
4183	CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301,	----
4184	CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302,	----
4185	CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303,	----
4186	CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304,	----
4187	CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305,	----
4188	CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306,	----
4189	CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307,	----
4190	TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308,	----
4191	ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309,	----
4192	FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310,	----
4193	CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311,	----
4194	MFC1_MMR6 = 1312,	----
4195	MTC1_MMR6 = 1313,	----
4196	CLASS_S_MMR6_CLASS_D_MMR6 = 1314,	----
4197	FADD_S_MMR6 = 1315,	----
4198	MAX_D_MMR6 = 1316,	----
4199	MAX_S_MMR6 = 1317,	----
4200	MIN_D_MMR6 = 1318,	----
4201	MIN_S_MMR6 = 1319,	----
4202	MAXA_D_MMR6 = 1320,	----
4203	MAXA_S_MMR6 = 1321,	----
4204	MINA_D_MMR6 = 1322,	----
4205	MINA_S_MMR6 = 1323,	----
4206	SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324,	----
4207	SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325,	----
4208	SEL_D_MMR6 = 1326,	----
4209	SEL_S_MMR6 = 1327,	----
4210	RINT_S_MMR6_RINT_D_MMR6 = 1328,	----
4211	MADDF_D_MMR6 = 1329,	----
4212	MADDF_S_MMR6 = 1330,	----
4213	MSUBF_D_MMR6 = 1331,	----
4214	MSUBF_S_MMR6 = 1332,	----
4215	FMOV_S_MMR6 = 1333,	----
4216	FMUL_S_MMR6 = 1334,	----
4217	FSUB_S_MMR6 = 1335,	----
4218	FMOV_D_MMR6 = 1336,	----
4219	FDIV_S_MMR6 = 1337,	----
4220	SDC1_D64_MMR6 = 1338,	----
4221	LDC1_D64_MMR6 = 1339,	----
4222	DMFC1 = 1340,	----
4223	DMTC1 = 1341,	----
4224	SWDSP = 1342,	----
4225	LWDSP = 1343,	----
4226	PseudoMTLOHI_DSP = 1344,	----
4227	EXTRV_RS_W = 1345,	----
4228	EXTRV_R_W = 1346,	----
4229	EXTRV_S_H = 1347,	----
4230	EXTRV_W = 1348,	----
4231	EXTR_RS_W = 1349,	----
4232	EXTR_R_W = 1350,	----
4233	EXTR_S_H = 1351,	----
4234	EXTR_W = 1352,	----
4235	INSV = 1353,	----
4236	MTHLIP = 1354,	----
4237	MTHI_DSP = 1355,	----
4238	MTLO_DSP = 1356,	----
4239	ABSQ_S_PH = 1357,	----
4240	ABSQ_S_W = 1358,	----
4241	ADDQ_PH = 1359,	----
4242	ADDQ_S_PH = 1360,	----
4243	ADDQ_S_W = 1361,	----
4244	ADDSC = 1362,	----
4245	ADDU_QB = 1363,	----
4246	ADDU_S_QB = 1364,	----
4247	ADDWC = 1365,	----
4248	BITREV = 1366,	----
4249	BPOSGE32 = 1367,	----
4250	CMPGU_EQ_QB = 1368,	----
4251	CMPGU_LE_QB = 1369,	----
4252	CMPGU_LT_QB = 1370,	----
4253	CMPU_EQ_QB = 1371,	----
4254	CMPU_LE_QB = 1372,	----
4255	CMPU_LT_QB = 1373,	----
4256	CMP_EQ_PH = 1374,	----
4257	CMP_LE_PH = 1375,	----
4258	CMP_LT_PH = 1376,	----
4259	DPAQ_SA_L_W = 1377,	----
4260	DPAQ_S_W_PH = 1378,	----
4261	DPAU_H_QBL = 1379,	----
4262	DPAU_H_QBR = 1380,	----
4263	DPSQ_SA_L_W = 1381,	----
4264	DPSQ_S_W_PH = 1382,	----
4265	DPSU_H_QBL = 1383,	----
4266	DPSU_H_QBR = 1384,	----
4267	EXTPDPV = 1385,	----
4268	EXTPDP = 1386,	----
4269	EXTPV = 1387,	----
4270	EXTP = 1388,	----
4271	LBUX = 1389,	----
4272	LHX = 1390,	----
4273	LWX = 1391,	----
4274	MADDU_DSP = 1392,	----
4275	MADD_DSP = 1393,	----
4276	MAQ_SA_W_PHL = 1394,	----
4277	MAQ_SA_W_PHR = 1395,	----
4278	MAQ_S_W_PHL = 1396,	----
4279	MAQ_S_W_PHR = 1397,	----
4280	MFHI_DSP = 1398,	----
4281	MFLO_DSP = 1399,	----
4282	MODSUB = 1400,	----
4283	MSUBU_DSP = 1401,	----
4284	MSUB_DSP = 1402,	----
4285	MULEQ_S_W_PHL = 1403,	----
4286	MULEQ_S_W_PHR = 1404,	----
4287	MULEU_S_PH_QBL = 1405,	----
4288	MULEU_S_PH_QBR = 1406,	----
4289	MULQ_RS_PH = 1407,	----
4290	MULSAQ_S_W_PH = 1408,	----
4291	MULTU_DSP = 1409,	----
4292	MULT_DSP = 1410,	----
4293	PACKRL_PH = 1411,	----
4294	PICK_PH = 1412,	----
4295	PICK_QB = 1413,	----
4296	PRECEQU_PH_QBLA = 1414,	----
4297	PRECEQU_PH_QBL = 1415,	----
4298	PRECEQU_PH_QBRA = 1416,	----
4299	PRECEQU_PH_QBR = 1417,	----
4300	PRECEQ_W_PHL = 1418,	----
4301	PRECEQ_W_PHR = 1419,	----
4302	PRECEU_PH_QBLA = 1420,	----
4303	PRECEU_PH_QBL = 1421,	----
4304	PRECEU_PH_QBRA = 1422,	----
4305	PRECEU_PH_QBR = 1423,	----
4306	PRECRQU_S_QB_PH = 1424,	----
4307	PRECRQ_PH_W = 1425,	----
4308	PRECRQ_QB_PH = 1426,	----
4309	PRECRQ_RS_PH_W = 1427,	----
4310	RADDU_W_QB = 1428,	----
4311	RDDSP = 1429,	----
4312	REPLV_PH = 1430,	----
4313	REPLV_QB = 1431,	----
4314	REPL_PH = 1432,	----
4315	REPL_QB = 1433,	----
4316	SHILOV = 1434,	----
4317	SHILO = 1435,	----
4318	SHLLV_PH = 1436,	----
4319	SHLLV_QB = 1437,	----
4320	SHLLV_S_PH = 1438,	----
4321	SHLLV_S_W = 1439,	----
4322	SHLL_PH = 1440,	----
4323	SHLL_QB = 1441,	----
4324	SHLL_S_PH = 1442,	----
4325	SHLL_S_W = 1443,	----
4326	SHRAV_PH = 1444,	----
4327	SHRAV_R_PH = 1445,	----
4328	SHRAV_R_W = 1446,	----
4329	SHRA_PH = 1447,	----
4330	SHRA_R_PH = 1448,	----
4331	SHRA_R_W = 1449,	----
4332	SHRLV_QB = 1450,	----
4333	SHRL_QB = 1451,	----
4334	SUBQ_PH = 1452,	----
4335	SUBQ_S_PH = 1453,	----
4336	SUBQ_S_W = 1454,	----
4337	SUBU_QB = 1455,	----
4338	SUBU_S_QB = 1456,	----
4339	WRDSP = 1457,	----
4340	PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458,	----
4341	PseudoPICK_PH_PseudoPICK_QB = 1459,	----
4342	ABSQ_S_QB = 1460,	----
4343	ADDQH_PH = 1461,	----
4344	ADDQH_R_PH = 1462,	----
4345	ADDQH_R_W = 1463,	----
4346	ADDQH_W = 1464,	----
4347	ADDUH_QB = 1465,	----
4348	ADDUH_R_QB = 1466,	----
4349	ADDU_PH = 1467,	----
4350	ADDU_S_PH = 1468,	----
4351	APPEND = 1469,	----
4352	BALIGN = 1470,	----
4353	CMPGDU_EQ_QB = 1471,	----
4354	CMPGDU_LE_QB = 1472,	----
4355	CMPGDU_LT_QB = 1473,	----
4356	DPA_W_PH = 1474,	----
4357	DPAQX_SA_W_PH = 1475,	----
4358	DPAQX_S_W_PH = 1476,	----
4359	DPAX_W_PH = 1477,	----
4360	DPS_W_PH = 1478,	----
4361	DPSQX_S_W_PH = 1479,	----
4362	DPSQX_SA_W_PH = 1480,	----
4363	DPSX_W_PH = 1481,	----
4364	MUL_PH = 1482,	----
4365	MUL_S_PH = 1483,	----
4366	MULQ_RS_W = 1484,	----
4367	MULQ_S_PH = 1485,	----
4368	MULQ_S_W = 1486,	----
4369	MULSA_W_PH = 1487,	----
4370	PRECR_QB_PH = 1488,	----
4371	PRECR_SRA_PH_W = 1489,	----
4372	PRECR_SRA_R_PH_W = 1490,	----
4373	PREPEND = 1491,	----
4374	SHRA_QB = 1492,	----
4375	SHRA_R_QB = 1493,	----
4376	SHRAV_QB = 1494,	----
4377	SHRAV_R_QB = 1495,	----
4378	SHRL_PH = 1496,	----
4379	SHRLV_PH = 1497,	----
4380	SUBQH_PH = 1498,	----
4381	SUBQH_R_PH = 1499,	----
4382	SUBQH_W = 1500,	----
4383	SUBQH_R_W = 1501,	----
4384	SUBU_PH = 1502,	----
4385	SUBU_S_PH = 1503,	----
4386	SUBUH_QB = 1504,	----
4387	SUBUH_R_QB = 1505,	----
4388	LWDSP_MM = 1506,	----
4389	SWDSP_MM = 1507,	----
4390	ABSQ_S_PH_MM = 1508,	----
4391	ABSQ_S_W_MM = 1509,	----
4392	ADDQ_PH_MM = 1510,	----
4393	ADDQ_S_PH_MM = 1511,	----
4394	ADDQ_S_W_MM = 1512,	----
4395	ADDSC_MM = 1513,	----
4396	ADDU_QB_MM = 1514,	----
4397	ADDU_S_QB_MM = 1515,	----
4398	ADDWC_MM = 1516,	----
4399	BITREV_MM = 1517,	----
4400	BPOSGE32_MM = 1518,	----
4401	CMPGU_EQ_QB_MM = 1519,	----
4402	CMPGU_LE_QB_MM = 1520,	----
4403	CMPGU_LT_QB_MM = 1521,	----
4404	CMPU_EQ_QB_MM = 1522,	----
4405	CMPU_LE_QB_MM = 1523,	----
4406	CMPU_LT_QB_MM = 1524,	----
4407	CMP_EQ_PH_MM = 1525,	----
4408	CMP_LE_PH_MM = 1526,	----
4409	CMP_LT_PH_MM = 1527,	----
4410	DPAQ_SA_L_W_MM = 1528,	----
4411	DPAQ_S_W_PH_MM = 1529,	----
4412	DPAU_H_QBL_MM = 1530,	----
4413	DPAU_H_QBR_MM = 1531,	----
4414	DPSQ_SA_L_W_MM = 1532,	----
4415	DPSQ_S_W_PH_MM = 1533,	----
4416	DPSU_H_QBL_MM = 1534,	----
4417	DPSU_H_QBR_MM = 1535,	----
4418	EXTPDPV_MM = 1536,	----
4419	EXTPDP_MM = 1537,	----
4420	EXTPV_MM = 1538,	----
4421	EXTP_MM = 1539,	----
4422	EXTRV_RS_W_MM = 1540,	----
4423	EXTRV_R_W_MM = 1541,	----
4424	EXTRV_S_H_MM = 1542,	----
4425	EXTRV_W_MM = 1543,	----
4426	EXTR_RS_W_MM = 1544,	----
4427	EXTR_R_W_MM = 1545,	----
4428	EXTR_S_H_MM = 1546,	----
4429	EXTR_W_MM = 1547,	----
4430	INSV_MM = 1548,	----
4431	LBUX_MM = 1549,	----
4432	LHX_MM = 1550,	----
4433	LWX_MM = 1551,	----
4434	MADDU_DSP_MM = 1552,	----
4435	MADD_DSP_MM = 1553,	----
4436	MAQ_SA_W_PHL_MM = 1554,	----
4437	MAQ_SA_W_PHR_MM = 1555,	----
4438	MAQ_S_W_PHL_MM = 1556,	----
4439	MAQ_S_W_PHR_MM = 1557,	----
4440	MFHI_DSP_MM = 1558,	----
4441	MFLO_DSP_MM = 1559,	----
4442	MODSUB_MM = 1560,	----
4443	MOVEP_MMR6 = 1561,	----
4444	MOVN_I_MM = 1562,	----
4445	MOVZ_I_MM = 1563,	----
4446	MSUBU_DSP_MM = 1564,	----
4447	MSUB_DSP_MM = 1565,	----
4448	MTHI_DSP_MM = 1566,	----
4449	MTHLIP_MM = 1567,	----
4450	MTLO_DSP_MM = 1568,	----
4451	MULEQ_S_W_PHL_MM = 1569,	----
4452	MULEQ_S_W_PHR_MM = 1570,	----
4453	MULEU_S_PH_QBL_MM = 1571,	----
4454	MULEU_S_PH_QBR_MM = 1572,	----
4455	MULQ_RS_PH_MM = 1573,	----
4456	MULSAQ_S_W_PH_MM = 1574,	----
4457	MULTU_DSP_MM = 1575,	----
4458	MULT_DSP_MM = 1576,	----
4459	PACKRL_PH_MM = 1577,	----
4460	PICK_PH_MM = 1578,	----
4461	PICK_QB_MM = 1579,	----
4462	PRECEQU_PH_QBLA_MM = 1580,	----
4463	PRECEQU_PH_QBL_MM = 1581,	----
4464	PRECEQU_PH_QBRA_MM = 1582,	----
4465	PRECEQU_PH_QBR_MM = 1583,	----
4466	PRECEQ_W_PHL_MM = 1584,	----
4467	PRECEQ_W_PHR_MM = 1585,	----
4468	PRECEU_PH_QBLA_MM = 1586,	----
4469	PRECEU_PH_QBL_MM = 1587,	----
4470	PRECEU_PH_QBRA_MM = 1588,	----
4471	PRECEU_PH_QBR_MM = 1589,	----
4472	PRECRQU_S_QB_PH_MM = 1590,	----
4473	PRECRQ_PH_W_MM = 1591,	----
4474	PRECRQ_QB_PH_MM = 1592,	----
4475	PRECRQ_RS_PH_W_MM = 1593,	----
4476	RADDU_W_QB_MM = 1594,	----
4477	RDDSP_MM = 1595,	----
4478	REPLV_PH_MM = 1596,	----
4479	REPLV_QB_MM = 1597,	----
4480	REPL_PH_MM = 1598,	----
4481	REPL_QB_MM = 1599,	----
4482	SHILOV_MM = 1600,	----
4483	SHILO_MM = 1601,	----
4484	SHLLV_PH_MM = 1602,	----
4485	SHLLV_QB_MM = 1603,	----
4486	SHLLV_S_PH_MM = 1604,	----
4487	SHLLV_S_W_MM = 1605,	----
4488	SHLL_PH_MM = 1606,	----
4489	SHLL_QB_MM = 1607,	----
4490	SHLL_S_PH_MM = 1608,	----
4491	SHLL_S_W_MM = 1609,	----
4492	SHRAV_PH_MM = 1610,	----
4493	SHRAV_R_PH_MM = 1611,	----
4494	SHRAV_R_W_MM = 1612,	----
4495	SHRA_PH_MM = 1613,	----
4496	SHRA_R_PH_MM = 1614,	----
4497	SHRA_R_W_MM = 1615,	----
4498	SHRLV_QB_MM = 1616,	----
4499	SHRL_QB_MM = 1617,	----
4500	SUBQ_PH_MM = 1618,	----
4501	SUBQ_S_PH_MM = 1619,	----
4502	SUBQ_S_W_MM = 1620,	----
4503	SUBU_QB_MM = 1621,	----
4504	SUBU_S_QB_MM = 1622,	----
4505	WRDSP_MM = 1623,	----
4506	ABSQ_S_QB_MMR2 = 1624,	----
4507	ADDQH_PH_MMR2 = 1625,	----
4508	ADDQH_R_PH_MMR2 = 1626,	----
4509	ADDQH_R_W_MMR2 = 1627,	----
4510	ADDQH_W_MMR2 = 1628,	----
4511	ADDUH_QB_MMR2 = 1629,	----
4512	ADDUH_R_QB_MMR2 = 1630,	----
4513	ADDU_PH_MMR2 = 1631,	----
4514	ADDU_S_PH_MMR2 = 1632,	----
4515	APPEND_MMR2 = 1633,	----
4516	BALIGN_MMR2 = 1634,	----
4517	CMPGDU_EQ_QB_MMR2 = 1635,	----
4518	CMPGDU_LE_QB_MMR2 = 1636,	----
4519	CMPGDU_LT_QB_MMR2 = 1637,	----
4520	DPA_W_PH_MMR2 = 1638,	----
4521	DPAQX_SA_W_PH_MMR2 = 1639,	----
4522	DPAQX_S_W_PH_MMR2 = 1640,	----
4523	DPAX_W_PH_MMR2 = 1641,	----
4524	DPS_W_PH_MMR2 = 1642,	----
4525	DPSQX_S_W_PH_MMR2 = 1643,	----
4526	DPSQX_SA_W_PH_MMR2 = 1644,	----
4527	DPSX_W_PH_MMR2 = 1645,	----
4528	MUL_PH_MMR2 = 1646,	----
4529	MUL_S_PH_MMR2 = 1647,	----
4530	MULQ_RS_W_MMR2 = 1648,	----
4531	MULQ_S_PH_MMR2 = 1649,	----
4532	MULQ_S_W_MMR2 = 1650,	----
4533	MULSA_W_PH_MMR2 = 1651,	----
4534	PRECR_QB_PH_MMR2 = 1652,	----
4535	PRECR_SRA_PH_W_MMR2 = 1653,	----
4536	PRECR_SRA_R_PH_W_MMR2 = 1654,	----
4537	PREPEND_MMR2 = 1655,	----
4538	SHRA_QB_MMR2 = 1656,	----
4539	SHRA_R_QB_MMR2 = 1657,	----
4540	SHRAV_QB_MMR2 = 1658,	----
4541	SHRAV_R_QB_MMR2 = 1659,	----
4542	SHRL_PH_MMR2 = 1660,	----
4543	SHRLV_PH_MMR2 = 1661,	----
4544	SUBQH_PH_MMR2 = 1662,	----
4545	SUBQH_R_PH_MMR2 = 1663,	----
4546	SUBQH_W_MMR2 = 1664,	----
4547	SUBQH_R_W_MMR2 = 1665,	----
4548	SUBU_PH_MMR2 = 1666,	----
4549	SUBU_S_PH_MMR2 = 1667,	----
4550	SUBUH_QB_MMR2 = 1668,	----
4551	SUBUH_R_QB_MMR2 = 1669,	----
4552	BPOSGE32C_MMR3 = 1670,	----
4553	CMP_F_D = 1671,	----
4554	CMP_F_S = 1672,	----
4555	CMP_SAF_D = 1673,	----
4556	CMP_SAF_S = 1674,	----
4557	CMP_SEQ_D = 1675,	----
4558	CMP_SEQ_S = 1676,	----
4559	CMP_SLE_D = 1677,	----
4560	CMP_SLE_S = 1678,	----
4561	CMP_SLT_D = 1679,	----
4562	CMP_SLT_S = 1680,	----
4563	CMP_SUEQ_D = 1681,	----
4564	CMP_SUEQ_S = 1682,	----
4565	CMP_SULE_D = 1683,	----
4566	CMP_SULE_S = 1684,	----
4567	CMP_SULT_D = 1685,	----
4568	CMP_SULT_S = 1686,	----
4569	CMP_SUN_D = 1687,	----
4570	CMP_SUN_S = 1688,	----
4571	SCHED_LIST_END = 1689	----
4572	};	----
4573	} // end namespace Sched	----
4574	} // end namespace Mips	----
4575	} // end namespace llvm	----
4576	#endif // GET_INSTRINFO_SCHED_ENUM	----
4577		----
4578	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	----
4579	namespace llvm {	----
4580		----
4581	struct MipsInstrTable {	----
4582	MCInstrDesc Insts[2853];	----
4583	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");	----
4584	MCOperandInfo OperandInfo[1126];	----
4585	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");	----
4586	MCPhysReg ImplicitOps[67];	----
4587	};	----
4588		----
4589	} // end namespace llvm	----
4590	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	----
4591		----
4592	#ifdef GET_INSTRINFO_MC_DESC	----
4593	#undef GET_INSTRINFO_MC_DESC	----
4594	namespace llvm {	----
4595		----
4596	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);	----
4597	static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));	----
4598		----
4599	extern const MipsInstrTable MipsDescs = {	----
4600	{	----
4601	{ 2852, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
4602	{ 2851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	----
4603	{ 2850, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4604	{ 2849, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
4605	{ 2848, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4606	{ 2847, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2847 = XOR_V	----
4607	{ 2846, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4608	{ 2845, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4609	{ 2844, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4610	{ 2843, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2843 = XORI_B	----
4611	{ 2842, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
4612	{ 2841, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
4613	{ 2840, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
4614	{ 2839, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4615	{ 2838, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2838 = WSBH_MMR6	----
4616	{ 2837, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2837 = WSBH_MM	----
4617	{ 2836, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2836 = WSBH	----
4618	{ 2835, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2835 = WRPGPR_MMR6	----
4619	{ 2834, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4620	{ 2833, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4621	{ 2832, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4622	{ 2831, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4623	{ 2830, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4624	{ 2829, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2829 = VSHF_W	----
4625	{ 2828, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2828 = VSHF_H	----
4626	{ 2827, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2827 = VSHF_D	----
4627	{ 2826, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2826 = VSHF_B	----
4628	{ 2825, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 219, 0\|(1ULL<	----
4629	{ 2824, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 219, 0\|(1ULL<	----
4630	{ 2823, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 219, 0\|(1ULL<	----
4631	{ 2822, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
4632	{ 2821, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
4633	{ 2820, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4634	{ 2819, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2819 = TRUNC_W_S_MMR6	----
4635	{ 2818, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2818 = TRUNC_W_S_MM	----
4636	{ 2817, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2817 = TRUNC_W_S	----
4637	{ 2816, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2816 = TRUNC_W_MM	----
4638	{ 2815, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2815 = TRUNC_W_D_MMR6	----
4639	{ 2814, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2814 = TRUNC_W_D64	----
4640	{ 2813, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2813 = TRUNC_W_D32	----
4641	{ 2812, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2812 = TRUNC_L_S_MMR6	----
4642	{ 2811, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2811 = TRUNC_L_S	----
4643	{ 2810, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2810 = TRUNC_L_D_MMR6	----
4644	{ 2809, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2809 = TRUNC_L_D64	----
4645	{ 2808, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4646	{ 2807, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4647	{ 2806, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4648	{ 2805, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4649	{ 2804, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4650	{ 2803, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4651	{ 2802, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4652	{ 2801, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4653	{ 2800, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4654	{ 2799, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4655	{ 2798, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4656	{ 2797, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4657	{ 2796, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4658	{ 2795, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4659	{ 2794, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4660	{ 2793, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4661	{ 2792, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4662	{ 2791, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4663	{ 2790, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4664	{ 2789, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4665	{ 2788, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4666	{ 2787, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4667	{ 2786, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4668	{ 2785, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4669	{ 2784, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4670	{ 2783, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4671	{ 2782, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4672	{ 2781, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4673	{ 2780, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4674	{ 2779, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4675	{ 2778, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4676	{ 2777, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4677	{ 2776, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4678	{ 2775, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4679	{ 2774, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4680	{ 2773, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4681	{ 2772, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4682	{ 2771, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4683	{ 2770, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4684	{ 2769, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4685	{ 2768, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4686	{ 2767, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4687	{ 2766, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4688	{ 2765, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4689	{ 2764, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4690	{ 2763, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
4691	{ 2762, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4692	{ 2761, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	----
4693	{ 2760, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
4694	{ 2759, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	----
4695	{ 2758, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2758 = SrlvRxRy16	----
4696	{ 2757, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2757 = SrlX16	----
4697	{ 2756, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2756 = SravRxRy16	----
4698	{ 2755, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2755 = SraX16	----
4699	{ 2754, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	----
4700	{ 2753, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
4701	{ 2752, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
4702	{ 2751, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
4703	{ 2750, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
4704	{ 2749, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	----
4705	{ 2748, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2748 = SllvRxRy16	----
4706	{ 2747, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2747 = SllX16	----
4707	{ 2746, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
4708	{ 2745, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2745 = SehRx16	----
4709	{ 2744, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2744 = SebRx16	----
4710	{ 2743, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
4711	{ 2742, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4712	{ 2741, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4713	{ 2740, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4714	{ 2739, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4715	{ 2738, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4716	{ 2737, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4717	{ 2736, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	----
4718	{ 2735, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	----
4719	{ 2734, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	----
4720	{ 2733, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4721	{ 2732, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4722	{ 2731, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4723	{ 2730, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	----
4724	{ 2729, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	----
4725	{ 2728, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	----
4726	{ 2727, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	----
4727	{ 2726, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4728	{ 2725, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4729	{ 2724, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4730	{ 2723, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
4731	{ 2722, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4732	{ 2721, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	----
4733	{ 2720, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	----
4734	{ 2719, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	----
4735	{ 2718, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	----
4736	{ 2717, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4737	{ 2716, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4738	{ 2715, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4739	{ 2714, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
4740	{ 2713, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4741	{ 2712, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4742	{ 2711, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4743	{ 2710, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	----
4744	{ 2709, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	----
4745	{ 2708, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	----
4746	{ 2707, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
4747	{ 2706, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	----
4748	{ 2705, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
4749	{ 2704, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	----
4750	{ 2703, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	----
4751	{ 2702, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
4752	{ 2701, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
4753	{ 2700, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
4754	{ 2699, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4755	{ 2698, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
4756	{ 2697, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
4757	{ 2696, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	----
4758	{ 2695, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4759	{ 2694, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4760	{ 2693, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4761	{ 2692, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4762	{ 2691, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2691 = SUBV_W	----
4763	{ 2690, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2690 = SUBV_H	----
4764	{ 2689, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2689 = SUBV_D	----
4765	{ 2688, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2688 = SUBV_B	----
4766	{ 2687, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2687 = SUBVI_W	----
4767	{ 2686, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2686 = SUBVI_H	----
4768	{ 2685, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2685 = SUBVI_D	----
4769	{ 2684, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2684 = SUBVI_B	----
4770	{ 2683, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2683 = SUBU_S_QB_MM	----
4771	{ 2682, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2682 = SUBU_S_QB	----
4772	{ 2681, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4773	{ 2680, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4774	{ 2679, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4775	{ 2678, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2678 = SUBU_QB	----
4776	{ 2677, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4777	{ 2676, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4778	{ 2675, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4779	{ 2674, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2674 = SUBUH_R_QB_MMR2	----
4780	{ 2673, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2673 = SUBUH_R_QB	----
4781	{ 2672, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2672 = SUBUH_QB_MMR2	----
4782	{ 2671, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2671 = SUBUH_QB	----
4783	{ 2670, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2670 = SUBU16_MMR6	----
4784	{ 2669, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2669 = SUBU16_MM	----
4785	{ 2668, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2668 = SUBS_U_W	----
4786	{ 2667, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2667 = SUBS_U_H	----
4787	{ 2666, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2666 = SUBS_U_D	----
4788	{ 2665, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2665 = SUBS_U_B	----
4789	{ 2664, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2664 = SUBS_S_W	----
4790	{ 2663, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2663 = SUBS_S_H	----
4791	{ 2662, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2662 = SUBS_S_D	----
4792	{ 2661, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2661 = SUBS_S_B	----
4793	{ 2660, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2660 = SUBSUU_S_W	----
4794	{ 2659, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2659 = SUBSUU_S_H	----
4795	{ 2658, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2658 = SUBSUU_S_D	----
4796	{ 2657, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2657 = SUBSUU_S_B	----
4797	{ 2656, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2656 = SUBSUS_U_W	----
4798	{ 2655, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2655 = SUBSUS_U_H	----
4799	{ 2654, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2654 = SUBSUS_U_D	----
4800	{ 2653, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2653 = SUBSUS_U_B	----
4801	{ 2652, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	----
4802	{ 2651, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	----
4803	{ 2650, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2650 = SUBQ_S_PH_MM	----
4804	{ 2649, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2649 = SUBQ_S_PH	----
4805	{ 2648, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
4806	{ 2647, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2647 = SUBQ_PH	----
4807	{ 2646, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2646 = SUBQH_W_MMR2	----
4808	{ 2645, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2645 = SUBQH_W	----
4809	{ 2644, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2644 = SUBQH_R_W_MMR2	----
4810	{ 2643, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2643 = SUBQH_R_W	----
4811	{ 2642, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2642 = SUBQH_R_PH_MMR2	----
4812	{ 2641, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2641 = SUBQH_R_PH	----
4813	{ 2640, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2640 = SUBQH_PH_MMR2	----
4814	{ 2639, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2639 = SUBQH_PH	----
4815	{ 2638, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
4816	{ 2637, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	----
4817	{ 2636, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	----
4818	{ 2635, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	----
4819	{ 2634, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	----
4820	{ 2633, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4821	{ 2632, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4822	{ 2631, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
4823	{ 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2630 = SRL_W	----
4824	{ 2629, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2629 = SRL_MM	----
4825	{ 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2628 = SRL_H	----
4826	{ 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2627 = SRL_D	----
4827	{ 2626, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2626 = SRL_B	----
4828	{ 2625, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2625 = SRLV_MM	----
4829	{ 2624, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2624 = SRLV	----
4830	{ 2623, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2623 = SRLR_W	----
4831	{ 2622, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2622 = SRLR_H	----
4832	{ 2621, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2621 = SRLR_D	----
4833	{ 2620, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2620 = SRLR_B	----
4834	{ 2619, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2619 = SRLRI_W	----
4835	{ 2618, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2618 = SRLRI_H	----
4836	{ 2617, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2617 = SRLRI_D	----
4837	{ 2616, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2616 = SRLRI_B	----
4838	{ 2615, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2615 = SRLI_W	----
4839	{ 2614, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2614 = SRLI_H	----
4840	{ 2613, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2613 = SRLI_D	----
4841	{ 2612, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2612 = SRLI_B	----
4842	{ 2611, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	----
4843	{ 2610, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2610 = SRL16_MM	----
4844	{ 2609, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2609 = SRL	----
4845	{ 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2608 = SRA_W	----
4846	{ 2607, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2607 = SRA_MM	----
4847	{ 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2606 = SRA_H	----
4848	{ 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2605 = SRA_D	----
4849	{ 2604, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2604 = SRA_B	----
4850	{ 2603, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2603 = SRAV_MM	----
4851	{ 2602, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2602 = SRAV	----
4852	{ 2601, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2601 = SRAR_W	----
4853	{ 2600, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2600 = SRAR_H	----
4854	{ 2599, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2599 = SRAR_D	----
4855	{ 2598, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2598 = SRAR_B	----
4856	{ 2597, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2597 = SRARI_W	----
4857	{ 2596, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2596 = SRARI_H	----
4858	{ 2595, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2595 = SRARI_D	----
4859	{ 2594, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2594 = SRARI_B	----
4860	{ 2593, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2593 = SRAI_W	----
4861	{ 2592, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2592 = SRAI_H	----
4862	{ 2591, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2591 = SRAI_D	----
4863	{ 2590, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2590 = SRAI_B	----
4864	{ 2589, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2589 = SRA	----
4865	{ 2588, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1119, 0, 0x6ULL }, // Inst #2588 = SPLAT_W	----
4866	{ 2587, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2587 = SPLAT_H	----
4867	{ 2586, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1113, 0, 0x6ULL }, // Inst #2586 = SPLAT_D	----
4868	{ 2585, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1110, 0, 0x6ULL }, // Inst #2585 = SPLAT_B	----
4869	{ 2584, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2584 = SPLATI_W	----
4870	{ 2583, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2583 = SPLATI_H	----
4871	{ 2582, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2582 = SPLATI_D	----
4872	{ 2581, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2581 = SPLATI_B	----
4873	{ 2580, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2580 = SNEi	----
4874	{ 2579, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2579 = SNE	----
4875	{ 2578, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2578 = SLTu_MM	----
4876	{ 2577, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2577 = SLTu64	----
4877	{ 2576, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2576 = SLTu	----
4878	{ 2575, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2575 = SLTiu_MM	----
4879	{ 2574, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2574 = SLTiu64	----
4880	{ 2573, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2573 = SLTiu	----
4881	{ 2572, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2572 = SLTi_MM	----
4882	{ 2571, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2571 = SLTi64	----
4883	{ 2570, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2570 = SLTi	----
4884	{ 2569, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2569 = SLT_MM	----
4885	{ 2568, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2568 = SLT64	----
4886	{ 2567, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2567 = SLT	----
4887	{ 2566, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2566 = SLL_W	----
4888	{ 2565, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4889	{ 2564, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2564 = SLL_MM	----
4890	{ 2563, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2563 = SLL_H	----
4891	{ 2562, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2562 = SLL_D	----
4892	{ 2561, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2561 = SLL_B	----
4893	{ 2560, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2560 = SLLV_MM	----
4894	{ 2559, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2559 = SLLV	----
4895	{ 2558, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2558 = SLLI_W	----
4896	{ 2557, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2557 = SLLI_H	----
4897	{ 2556, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2556 = SLLI_D	----
4898	{ 2555, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2555 = SLLI_B	----
4899	{ 2554, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	----
4900	{ 2553, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	----
4901	{ 2552, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	----
4902	{ 2551, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2551 = SLL16_MM	----
4903	{ 2550, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2550 = SLL	----
4904	{ 2549, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2549 = SLD_W	----
4905	{ 2548, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2548 = SLD_H	----
4906	{ 2547, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2547 = SLD_D	----
4907	{ 2546, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1088, 0, 0x6ULL }, // Inst #2546 = SLD_B	----
4908	{ 2545, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2545 = SLDI_W	----
4909	{ 2544, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2544 = SLDI_H	----
4910	{ 2543, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2543 = SLDI_D	----
4911	{ 2542, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #2542 = SLDI_B	----
4912	{ 2541, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4913	{ 2540, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
4914	{ 2539, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4915	{ 2538, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4916	{ 2537, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4917	{ 2536, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4918	{ 2535, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4919	{ 2534, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4920	{ 2533, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2533 = SHRLV_QB_MM	----
4921	{ 2532, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2532 = SHRLV_QB	----
4922	{ 2531, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2531 = SHRLV_PH_MMR2	----
4923	{ 2530, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2530 = SHRLV_PH	----
4924	{ 2529, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4925	{ 2528, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
4926	{ 2527, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4927	{ 2526, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4928	{ 2525, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4929	{ 2524, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4930	{ 2523, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4931	{ 2522, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4932	{ 2521, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4933	{ 2520, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	----
4934	{ 2519, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2519 = SHRAV_R_W_MM	----
4935	{ 2518, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2518 = SHRAV_R_W	----
4936	{ 2517, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2517 = SHRAV_R_QB_MMR2	----
4937	{ 2516, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2516 = SHRAV_R_QB	----
4938	{ 2515, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2515 = SHRAV_R_PH_MM	----
4939	{ 2514, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2514 = SHRAV_R_PH	----
4940	{ 2513, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2513 = SHRAV_QB_MMR2	----
4941	{ 2512, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2512 = SHRAV_QB	----
4942	{ 2511, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2511 = SHRAV_PH_MM	----
4943	{ 2510, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2510 = SHRAV_PH	----
4944	{ 2509, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	----
4945	{ 2508, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	----
4946	{ 2507, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4947	{ 2506, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4948	{ 2505, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4949	{ 2504, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4950	{ 2503, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4951	{ 2502, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	----
4952	{ 2501, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	----
4953	{ 2500, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	----
4954	{ 2499, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4955	{ 2498, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4956	{ 2497, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4957	{ 2496, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4958	{ 2495, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4959	{ 2494, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	----
4960	{ 2493, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SHILO_MM	----
4961	{ 2492, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2492 = SHILOV_MM	----
4962	{ 2491, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2491 = SHILOV	----
4963	{ 2490, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2490 = SHILO	----
4964	{ 2489, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2489 = SHF_W	----
4965	{ 2488, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2488 = SHF_H	----
4966	{ 2487, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2487 = SHF_B	----
4967	{ 2486, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4968	{ 2485, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4969	{ 2484, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
4970	{ 2483, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
4971	{ 2482, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
4972	{ 2481, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
4973	{ 2480, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2480 = SEQi	----
4974	{ 2479, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2479 = SEQ	----
4975	{ 2478, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2478 = SEL_S_MMR6	----
4976	{ 2477, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2477 = SEL_S	----
4977	{ 2476, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2476 = SEL_D_MMR6	----
4978	{ 2475, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2475 = SEL_D	----
4979	{ 2474, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
4980	{ 2473, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
4981	{ 2472, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2472 = SELNEZ_MMR6	----
4982	{ 2471, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
4983	{ 2470, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
4984	{ 2469, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2469 = SELNEZ64	----
4985	{ 2468, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2468 = SELNEZ	----
4986	{ 2467, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
4987	{ 2466, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
4988	{ 2465, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2465 = SELEQZ_MMR6	----
4989	{ 2464, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
4990	{ 2463, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
4991	{ 2462, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2462 = SELEQZ64	----
4992	{ 2461, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2461 = SELEQZ	----
4993	{ 2460, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2460 = SEH_MM	----
4994	{ 2459, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2459 = SEH64	----
4995	{ 2458, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2458 = SEH	----
4996	{ 2457, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2457 = SEB_MM	----
4997	{ 2456, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2456 = SEB64	----
4998	{ 2455, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2455 = SEB	----
4999	{ 2454, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
5000	{ 2453, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	----
5001	{ 2452, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5002	{ 2451, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5003	{ 2450, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5004	{ 2449, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5005	{ 2448, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	----
5006	{ 2447, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5007	{ 2446, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	----
5008	{ 2445, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5009	{ 2444, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5010	{ 2443, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	----
5011	{ 2442, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5012	{ 2441, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5013	{ 2440, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	----
5014	{ 2439, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5015	{ 2438, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5016	{ 2437, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5017	{ 2436, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5018	{ 2435, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5019	{ 2434, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5020	{ 2433, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5021	{ 2432, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	----
5022	{ 2431, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5023	{ 2430, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5024	{ 2429, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5025	{ 2428, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5026	{ 2427, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1071, 0\|(1ULL<	----
5027	{ 2426, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1067, 0\|(1ULL<	----
5028	{ 2425, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	----
5029	{ 2424, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5030	{ 2423, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	----
5031	{ 2422, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5032	{ 2421, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5033	{ 2420, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5034	{ 2419, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5035	{ 2418, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5036	{ 2417, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
5037	{ 2416, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	----
5038	{ 2415, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5039	{ 2414, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2414 = SAT_U_W	----
5040	{ 2413, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2413 = SAT_U_H	----
5041	{ 2412, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2412 = SAT_U_D	----
5042	{ 2411, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2411 = SAT_U_B	----
5043	{ 2410, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2410 = SAT_S_W	----
5044	{ 2409, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2409 = SAT_S_H	----
5045	{ 2408, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2408 = SAT_S_D	----
5046	{ 2407, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2407 = SAT_S_B	----
5047	{ 2406, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	----
5048	{ 2405, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	----
5049	{ 2404, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5050	{ 2403, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5051	{ 2402, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2402 = RSQRT_S_MM	----
5052	{ 2401, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2401 = RSQRT_S	----
5053	{ 2400, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2400 = RSQRT_D64_MM	----
5054	{ 2399, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2399 = RSQRT_D64	----
5055	{ 2398, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2398 = RSQRT_D32_MM	----
5056	{ 2397, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2397 = RSQRT_D32	----
5057	{ 2396, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2396 = ROUND_W_S_MMR6	----
5058	{ 2395, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2395 = ROUND_W_S_MM	----
5059	{ 2394, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2394 = ROUND_W_S	----
5060	{ 2393, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2393 = ROUND_W_MM	----
5061	{ 2392, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2392 = ROUND_W_D_MMR6	----
5062	{ 2391, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2391 = ROUND_W_D64	----
5063	{ 2390, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2390 = ROUND_W_D32	----
5064	{ 2389, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2389 = ROUND_L_S_MMR6	----
5065	{ 2388, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2388 = ROUND_L_S	----
5066	{ 2387, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2387 = ROUND_L_D_MMR6	----
5067	{ 2386, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2386 = ROUND_L_D64	----
5068	{ 2385, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2385 = ROTR_MM	----
5069	{ 2384, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2384 = ROTRV_MM	----
5070	{ 2383, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2383 = ROTRV	----
5071	{ 2382, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2382 = ROTR	----
5072	{ 2381, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
5073	{ 2380, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
5074	{ 2379, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	----
5075	{ 2378, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	----
5076	{ 2377, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2377 = REPL_QB_MM	----
5077	{ 2376, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2376 = REPL_QB	----
5078	{ 2375, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2375 = REPL_PH_MM	----
5079	{ 2374, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2374 = REPL_PH	----
5080	{ 2373, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = REPLV_QB_MM	----
5081	{ 2372, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = REPLV_QB	----
5082	{ 2371, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2371 = REPLV_PH_MM	----
5083	{ 2370, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2370 = REPLV_PH	----
5084	{ 2369, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2369 = RECIP_S_MM	----
5085	{ 2368, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2368 = RECIP_S	----
5086	{ 2367, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2367 = RECIP_D64_MM	----
5087	{ 2366, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2366 = RECIP_D64	----
5088	{ 2365, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2365 = RECIP_D32_MM	----
5089	{ 2364, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2364 = RECIP_D32	----
5090	{ 2363, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
5091	{ 2362, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	----
5092	{ 2361, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	----
5093	{ 2360, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1049, 0\|(1ULL<	----
5094	{ 2359, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	----
5095	{ 2358, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5096	{ 2357, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5097	{ 2356, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2356 = RADDU_W_QB_MM	----
5098	{ 2355, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2355 = RADDU_W_QB	----
5099	{ 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5100	{ 2353, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5101	{ 2352, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2352 = PREPEND_MMR2	----
5102	{ 2351, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2351 = PREPEND	----
5103	{ 2350, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5104	{ 2349, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5105	{ 2348, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5106	{ 2347, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1043, 0\|(1ULL<	----
5107	{ 2346, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5108	{ 2345, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5109	{ 2344, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
5110	{ 2343, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2343 = PRECR_SRA_R_PH_W_MMR2	----
5111	{ 2342, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2342 = PRECR_SRA_R_PH_W	----
5112	{ 2341, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2341 = PRECR_SRA_PH_W_MMR2	----
5113	{ 2340, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2340 = PRECR_SRA_PH_W	----
5114	{ 2339, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
5115	{ 2338, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
5116	{ 2337, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	----
5117	{ 2336, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	----
5118	{ 2335, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2335 = PRECRQ_QB_PH_MM	----
5119	{ 2334, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2334 = PRECRQ_QB_PH	----
5120	{ 2333, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2333 = PRECRQ_PH_W_MM	----
5121	{ 2332, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2332 = PRECRQ_PH_W	----
5122	{ 2331, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	----
5123	{ 2330, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	----
5124	{ 2329, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2329 = PRECEU_PH_QBR_MM	----
5125	{ 2328, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2328 = PRECEU_PH_QBRA_MM	----
5126	{ 2327, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2327 = PRECEU_PH_QBRA	----
5127	{ 2326, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2326 = PRECEU_PH_QBR	----
5128	{ 2325, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2325 = PRECEU_PH_QBL_MM	----
5129	{ 2324, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2324 = PRECEU_PH_QBLA_MM	----
5130	{ 2323, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2323 = PRECEU_PH_QBLA	----
5131	{ 2322, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2322 = PRECEU_PH_QBL	----
5132	{ 2321, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2321 = PRECEQ_W_PHR_MM	----
5133	{ 2320, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2320 = PRECEQ_W_PHR	----
5134	{ 2319, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2319 = PRECEQ_W_PHL_MM	----
5135	{ 2318, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2318 = PRECEQ_W_PHL	----
5136	{ 2317, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2317 = PRECEQU_PH_QBR_MM	----
5137	{ 2316, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2316 = PRECEQU_PH_QBRA_MM	----
5138	{ 2315, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2315 = PRECEQU_PH_QBRA	----
5139	{ 2314, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2314 = PRECEQU_PH_QBR	----
5140	{ 2313, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2313 = PRECEQU_PH_QBL_MM	----
5141	{ 2312, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2312 = PRECEQU_PH_QBLA_MM	----
5142	{ 2311, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2311 = PRECEQU_PH_QBLA	----
5143	{ 2310, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2310 = PRECEQU_PH_QBL	----
5144	{ 2309, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2309 = POP	----
5145	{ 2308, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5146	{ 2307, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5147	{ 2306, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	----
5148	{ 2305, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	----
5149	{ 2304, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	----
5150	{ 2303, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	----
5151	{ 2302, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2302 = PCNT_W	----
5152	{ 2301, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2301 = PCNT_H	----
5153	{ 2300, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2300 = PCNT_D	----
5154	{ 2299, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2299 = PCNT_B	----
5155	{ 2298, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2298 = PCKOD_W	----
5156	{ 2297, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2297 = PCKOD_H	----
5157	{ 2296, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2296 = PCKOD_D	----
5158	{ 2295, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2295 = PCKOD_B	----
5159	{ 2294, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2294 = PCKEV_W	----
5160	{ 2293, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2293 = PCKEV_H	----
5161	{ 2292, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2292 = PCKEV_D	----
5162	{ 2291, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2291 = PCKEV_B	----
5163	{ 2290, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5164	{ 2289, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5165	{ 2288, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5166	{ 2287, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2287 = PACKRL_PH_MM	----
5167	{ 2286, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2286 = PACKRL_PH	----
5168	{ 2285, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	----
5169	{ 2284, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
5170	{ 2283, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
5171	{ 2282, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
5172	{ 2281, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2281 = OR_V	----
5173	{ 2280, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5174	{ 2279, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5175	{ 2278, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
5176	{ 2277, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2277 = ORI_B	----
5177	{ 2276, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
5178	{ 2275, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
5179	{ 2274, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
5180	{ 2273, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5181	{ 2272, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2272 = NotRxRy16	----
5182	{ 2271, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2271 = NegRxRy16	----
5183	{ 2270, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2270 = NOT16_MMR6	----
5184	{ 2269, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2269 = NOT16_MM	----
5185	{ 2268, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2268 = NOR_V	----
5186	{ 2267, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5187	{ 2266, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5188	{ 2265, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2265 = NORI_B	----
5189	{ 2264, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
5190	{ 2263, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5191	{ 2262, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2262 = NMSUB_S_MM	----
5192	{ 2261, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2261 = NMSUB_S	----
5193	{ 2260, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2260 = NMSUB_D64	----
5194	{ 2259, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2259 = NMSUB_D32_MM	----
5195	{ 2258, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2258 = NMSUB_D32	----
5196	{ 2257, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2257 = NMADD_S_MM	----
5197	{ 2256, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2256 = NMADD_S	----
5198	{ 2255, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2255 = NMADD_D64	----
5199	{ 2254, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2254 = NMADD_D32_MM	----
5200	{ 2253, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2253 = NMADD_D32	----
5201	{ 2252, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2252 = NLZC_W	----
5202	{ 2251, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2251 = NLZC_H	----
5203	{ 2250, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2250 = NLZC_D	----
5204	{ 2249, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2249 = NLZC_B	----
5205	{ 2248, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2248 = NLOC_W	----
5206	{ 2247, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2247 = NLOC_H	----
5207	{ 2246, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2246 = NLOC_D	----
5208	{ 2245, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2245 = NLOC_B	----
5209	{ 2244, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1028, 0\|(1ULL<	----
5210	{ 2243, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1026, 0\|(1ULL<	----
5211	{ 2242, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 829, 0, 0x0ULL }, // Inst #2242 = Mflo16	----
5212	{ 2241, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 829, 0\|(1ULL<	----
5213	{ 2240, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5214	{ 2239, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5215	{ 2238, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2238 = MUL_R6	----
5216	{ 2237, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2237 = MUL_Q_W	----
5217	{ 2236, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2236 = MUL_Q_H	----
5218	{ 2235, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5219	{ 2234, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5220	{ 2233, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5221	{ 2232, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	----
5222	{ 2231, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2231 = MULV_W	----
5223	{ 2230, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2230 = MULV_H	----
5224	{ 2229, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2229 = MULV_D	----
5225	{ 2228, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2228 = MULV_B	----
5226	{ 2227, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5227	{ 2226, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5228	{ 2225, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5229	{ 2224, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5230	{ 2223, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5231	{ 2222, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	----
5232	{ 2221, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	----
5233	{ 2220, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	----
5234	{ 2219, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	----
5235	{ 2218, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	----
5236	{ 2217, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2217 = MULSA_W_PH_MMR2	----
5237	{ 2216, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2216 = MULSA_W_PH	----
5238	{ 2215, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5239	{ 2214, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5240	{ 2213, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2213 = MULR_Q_W	----
5241	{ 2212, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2212 = MULR_Q_H	----
5242	{ 2211, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5243	{ 2210, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	----
5244	{ 2209, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	----
5245	{ 2208, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5246	{ 2207, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5247	{ 2206, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	----
5248	{ 2205, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	----
5249	{ 2204, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5250	{ 2203, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5251	{ 2202, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5252	{ 2201, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5253	{ 2200, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5254	{ 2199, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	----
5255	{ 2198, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	----
5256	{ 2197, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	----
5257	{ 2196, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	----
5258	{ 2195, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	----
5259	{ 2194, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	----
5260	{ 2193, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5261	{ 2192, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5262	{ 2191, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2191 = MUHU	----
5263	{ 2190, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2190 = MUH	----
5264	{ 2189, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	----
5265	{ 2188, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 302, 0\|(1ULL<	----
5266	{ 2187, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 302, 0\|(1ULL<	----
5267	{ 2186, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 302, 0\|(1ULL<	----
5268	{ 2185, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 302, 0\|(1ULL<	----
5269	{ 2184, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 302, 0\|(1ULL<	----
5270	{ 2183, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 302, 0\|(1ULL<	----
5271	{ 2182, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	----
5272	{ 2181, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	----
5273	{ 2180, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	----
5274	{ 2179, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 302, 0\|(1ULL<	----
5275	{ 2178, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	----
5276	{ 2177, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	----
5277	{ 2176, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	----
5278	{ 2175, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	----
5279	{ 2174, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	----
5280	{ 2173, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	----
5281	{ 2172, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 302, 0\|(1ULL<	----
5282	{ 2171, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	----
5283	{ 2170, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5284	{ 2169, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5285	{ 2168, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	----
5286	{ 2167, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	----
5287	{ 2166, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	----
5288	{ 2165, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	----
5289	{ 2164, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	----
5290	{ 2163, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5291	{ 2162, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5292	{ 2161, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5293	{ 2160, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	----
5294	{ 2159, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1010, 0\|(1ULL<	----
5295	{ 2158, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
5296	{ 2157, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
5297	{ 2156, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	----
5298	{ 2155, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	----
5299	{ 2154, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
5300	{ 2153, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5301	{ 2152, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
5302	{ 2151, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	----
5303	{ 2150, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2150 = MSUB_S	----
5304	{ 2149, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2149 = MSUB_Q_W	----
5305	{ 2148, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUB_Q_H	----
5306	{ 2147, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5307	{ 2146, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2146 = MSUB_DSP_MM	----
5308	{ 2145, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2145 = MSUB_DSP	----
5309	{ 2144, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2144 = MSUB_D64	----
5310	{ 2143, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	----
5311	{ 2142, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2142 = MSUB_D32	----
5312	{ 2141, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2141 = MSUBV_W	----
5313	{ 2140, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2140 = MSUBV_H	----
5314	{ 2139, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2139 = MSUBV_D	----
5315	{ 2138, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2138 = MSUBV_B	----
5316	{ 2137, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5317	{ 2136, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2136 = MSUBU_DSP_MM	----
5318	{ 2135, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2135 = MSUBU_DSP	----
5319	{ 2134, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5320	{ 2133, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2133 = MSUBR_Q_W	----
5321	{ 2132, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2132 = MSUBR_Q_H	----
5322	{ 2131, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	----
5323	{ 2130, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	----
5324	{ 2129, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	----
5325	{ 2128, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	----
5326	{ 2127, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5327	{ 2126, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2126 = MOVZ_I_S_MM	----
5328	{ 2125, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2125 = MOVZ_I_S	----
5329	{ 2124, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2124 = MOVZ_I_MM	----
5330	{ 2123, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2123 = MOVZ_I_I64	----
5331	{ 2122, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2122 = MOVZ_I_I	----
5332	{ 2121, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2121 = MOVZ_I_D64	----
5333	{ 2120, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2120 = MOVZ_I_D32_MM	----
5334	{ 2119, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2119 = MOVZ_I_D32	----
5335	{ 2118, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2118 = MOVZ_I64_S	----
5336	{ 2117, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2117 = MOVZ_I64_I64	----
5337	{ 2116, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2116 = MOVZ_I64_I	----
5338	{ 2115, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2115 = MOVZ_I64_D64	----
5339	{ 2114, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2114 = MOVT_S_MM	----
5340	{ 2113, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2113 = MOVT_S	----
5341	{ 2112, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2112 = MOVT_I_MM	----
5342	{ 2111, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2111 = MOVT_I64	----
5343	{ 2110, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2110 = MOVT_I	----
5344	{ 2109, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2109 = MOVT_D64	----
5345	{ 2108, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2108 = MOVT_D32_MM	----
5346	{ 2107, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2107 = MOVT_D32	----
5347	{ 2106, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2106 = MOVN_I_S_MM	----
5348	{ 2105, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2105 = MOVN_I_S	----
5349	{ 2104, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2104 = MOVN_I_MM	----
5350	{ 2103, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2103 = MOVN_I_I64	----
5351	{ 2102, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2102 = MOVN_I_I	----
5352	{ 2101, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2101 = MOVN_I_D64	----
5353	{ 2100, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2100 = MOVN_I_D32_MM	----
5354	{ 2099, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2099 = MOVN_I_D32	----
5355	{ 2098, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2098 = MOVN_I64_S	----
5356	{ 2097, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2097 = MOVN_I64_I64	----
5357	{ 2096, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2096 = MOVN_I64_I	----
5358	{ 2095, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2095 = MOVN_I64_D64	----
5359	{ 2094, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2094 = MOVF_S_MM	----
5360	{ 2093, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2093 = MOVF_S	----
5361	{ 2092, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2092 = MOVF_I_MM	----
5362	{ 2091, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2091 = MOVF_I64	----
5363	{ 2090, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2090 = MOVF_I	----
5364	{ 2089, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2089 = MOVF_D64	----
5365	{ 2088, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2088 = MOVF_D32_MM	----
5366	{ 2087, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2087 = MOVF_D32	----
5367	{ 2086, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 952, 0\|(1ULL<	----
5368	{ 2085, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	----
5369	{ 2084, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	----
5370	{ 2083, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
5371	{ 2082, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
5372	{ 2081, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2081 = MOD_U_W	----
5373	{ 2080, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2080 = MOD_U_H	----
5374	{ 2079, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2079 = MOD_U_D	----
5375	{ 2078, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2078 = MOD_U_B	----
5376	{ 2077, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2077 = MOD_S_W	----
5377	{ 2076, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2076 = MOD_S_H	----
5378	{ 2075, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2075 = MOD_S_D	----
5379	{ 2074, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2074 = MOD_S_B	----
5380	{ 2073, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5381	{ 2072, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5382	{ 2071, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5383	{ 2070, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2070 = MODSUB_MM	----
5384	{ 2069, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2069 = MODSUB	----
5385	{ 2068, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5386	{ 2067, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2067 = MIN_U_W	----
5387	{ 2066, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2066 = MIN_U_H	----
5388	{ 2065, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2065 = MIN_U_D	----
5389	{ 2064, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2064 = MIN_U_B	----
5390	{ 2063, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2063 = MIN_S_W	----
5391	{ 2062, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5392	{ 2061, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2061 = MIN_S_H	----
5393	{ 2060, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2060 = MIN_S_D	----
5394	{ 2059, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2059 = MIN_S_B	----
5395	{ 2058, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5396	{ 2057, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5397	{ 2056, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5398	{ 2055, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2055 = MIN_A_W	----
5399	{ 2054, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2054 = MIN_A_H	----
5400	{ 2053, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2053 = MIN_A_D	----
5401	{ 2052, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2052 = MIN_A_B	----
5402	{ 2051, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2051 = MINI_U_W	----
5403	{ 2050, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2050 = MINI_U_H	----
5404	{ 2049, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2049 = MINI_U_D	----
5405	{ 2048, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2048 = MINI_U_B	----
5406	{ 2047, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2047 = MINI_S_W	----
5407	{ 2046, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2046 = MINI_S_H	----
5408	{ 2045, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2045 = MINI_S_D	----
5409	{ 2044, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2044 = MINI_S_B	----
5410	{ 2043, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5411	{ 2042, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5412	{ 2041, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5413	{ 2040, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5414	{ 2039, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	----
5415	{ 2038, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5416	{ 2037, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2037 = MFLO_DSP_MM	----
5417	{ 2036, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	----
5418	{ 2035, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	----
5419	{ 2034, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5420	{ 2033, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5421	{ 2032, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5422	{ 2031, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2031 = MFHI_DSP_MM	----
5423	{ 2030, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	----
5424	{ 2029, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	----
5425	{ 2028, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5426	{ 2027, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	----
5427	{ 2026, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5428	{ 2025, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5429	{ 2024, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	----
5430	{ 2023, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	----
5431	{ 2022, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	----
5432	{ 2021, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	----
5433	{ 2020, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	----
5434	{ 2019, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5435	{ 2018, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5436	{ 2017, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5437	{ 2016, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	----
5438	{ 2015, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 938, 0\|(1ULL<	----
5439	{ 2014, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	----
5440	{ 2013, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	----
5441	{ 2012, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	----
5442	{ 2011, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	----
5443	{ 2010, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5444	{ 2009, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
5445	{ 2008, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2008 = MAX_U_W	----
5446	{ 2007, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2007 = MAX_U_H	----
5447	{ 2006, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2006 = MAX_U_D	----
5448	{ 2005, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2005 = MAX_U_B	----
5449	{ 2004, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2004 = MAX_S_W	----
5450	{ 2003, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5451	{ 2002, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2002 = MAX_S_H	----
5452	{ 2001, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2001 = MAX_S_D	----
5453	{ 2000, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2000 = MAX_S_B	----
5454	{ 1999, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5455	{ 1998, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5456	{ 1997, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5457	{ 1996, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1996 = MAX_A_W	----
5458	{ 1995, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1995 = MAX_A_H	----
5459	{ 1994, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1994 = MAX_A_D	----
5460	{ 1993, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1993 = MAX_A_B	----
5461	{ 1992, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1992 = MAXI_U_W	----
5462	{ 1991, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1991 = MAXI_U_H	----
5463	{ 1990, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1990 = MAXI_U_D	----
5464	{ 1989, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1989 = MAXI_U_B	----
5465	{ 1988, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1988 = MAXI_S_W	----
5466	{ 1987, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1987 = MAXI_S_H	----
5467	{ 1986, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1986 = MAXI_S_D	----
5468	{ 1985, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1985 = MAXI_S_B	----
5469	{ 1984, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5470	{ 1983, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5471	{ 1982, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5472	{ 1981, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5473	{ 1980, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5474	{ 1979, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5475	{ 1978, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5476	{ 1977, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5477	{ 1976, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5478	{ 1975, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5479	{ 1974, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5480	{ 1973, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5481	{ 1972, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	----
5482	{ 1971, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1971 = MADD_S	----
5483	{ 1970, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1970 = MADD_Q_W	----
5484	{ 1969, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADD_Q_H	----
5485	{ 1968, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5486	{ 1967, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1967 = MADD_DSP_MM	----
5487	{ 1966, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1966 = MADD_DSP	----
5488	{ 1965, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1965 = MADD_D64	----
5489	{ 1964, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	----
5490	{ 1963, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #1963 = MADD_D32	----
5491	{ 1962, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1962 = MADDV_W	----
5492	{ 1961, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1961 = MADDV_H	----
5493	{ 1960, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1960 = MADDV_D	----
5494	{ 1959, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1959 = MADDV_B	----
5495	{ 1958, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5496	{ 1957, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1957 = MADDU_DSP_MM	----
5497	{ 1956, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1956 = MADDU_DSP	----
5498	{ 1955, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5499	{ 1954, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1954 = MADDR_Q_W	----
5500	{ 1953, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1953 = MADDR_Q_H	----
5501	{ 1952, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	----
5502	{ 1951, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	----
5503	{ 1950, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	----
5504	{ 1949, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	----
5505	{ 1948, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	----
5506	{ 1947, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	----
5507	{ 1946, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
5508	{ 1945, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	----
5509	{ 1944, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	----
5510	{ 1943, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0, 0x0ULL }, // Inst #1943 = LiRxImmX16	----
5511	{ 1942, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	----
5512	{ 1941, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	----
5513	{ 1940, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
5514	{ 1939, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
5515	{ 1938, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
5516	{ 1937, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	----
5517	{ 1936, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5518	{ 1935, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5519	{ 1934, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5520	{ 1933, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5521	{ 1932, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5522	{ 1931, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	----
5523	{ 1930, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	----
5524	{ 1929, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5525	{ 1928, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5526	{ 1927, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5527	{ 1926, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	----
5528	{ 1925, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5529	{ 1924, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5530	{ 1923, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5531	{ 1922, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	----
5532	{ 1921, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5533	{ 1920, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	----
5534	{ 1919, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5535	{ 1918, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5536	{ 1917, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	----
5537	{ 1916, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	----
5538	{ 1915, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	----
5539	{ 1914, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5540	{ 1913, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5541	{ 1912, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5542	{ 1911, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	----
5543	{ 1910, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	----
5544	{ 1909, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 890, 0\|(1ULL<	----
5545	{ 1908, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5546	{ 1907, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5547	{ 1906, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	----
5548	{ 1905, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	----
5549	{ 1904, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	----
5550	{ 1903, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5551	{ 1902, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	----
5552	{ 1901, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5553	{ 1900, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	----
5554	{ 1899, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	----
5555	{ 1898, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5556	{ 1897, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	----
5557	{ 1896, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5558	{ 1895, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5559	{ 1894, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
5560	{ 1893, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5561	{ 1892, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
5562	{ 1891, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
5563	{ 1890, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	----
5564	{ 1889, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5565	{ 1888, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	----
5566	{ 1887, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	----
5567	{ 1886, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 553, 0, 0x6ULL }, // Inst #1886 = LSA	----
5568	{ 1885, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	----
5569	{ 1884, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5570	{ 1883, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5571	{ 1882, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5572	{ 1881, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5573	{ 1880, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 881, 0\|(1ULL<	----
5574	{ 1879, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5575	{ 1878, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	----
5576	{ 1877, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5577	{ 1876, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5578	{ 1875, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	----
5579	{ 1874, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	----
5580	{ 1873, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5581	{ 1872, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5582	{ 1871, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5583	{ 1870, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5584	{ 1869, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5585	{ 1868, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5586	{ 1867, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5587	{ 1866, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5588	{ 1865, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	----
5589	{ 1864, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5590	{ 1863, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5591	{ 1862, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5592	{ 1861, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5593	{ 1860, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1860 = LEA_ADDiu_MM	----
5594	{ 1859, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 352, 0, 0x2ULL }, // Inst #1859 = LEA_ADDiu64	----
5595	{ 1858, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1858 = LEA_ADDiu	----
5596	{ 1857, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	----
5597	{ 1856, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	----
5598	{ 1855, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	----
5599	{ 1854, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	----
5600	{ 1853, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	----
5601	{ 1852, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	----
5602	{ 1851, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	----
5603	{ 1850, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
5604	{ 1849, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	----
5605	{ 1848, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0\|(1ULL<	----
5606	{ 1847, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0\|(1ULL<	----
5607	{ 1846, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 850, 0\|(1ULL<	----
5608	{ 1845, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 848, 0\|(1ULL<	----
5609	{ 1844, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	----
5610	{ 1843, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5611	{ 1842, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	----
5612	{ 1841, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	----
5613	{ 1840, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5614	{ 1839, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	----
5615	{ 1838, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5616	{ 1837, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	----
5617	{ 1836, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	----
5618	{ 1835, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5619	{ 1834, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5620	{ 1833, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5621	{ 1832, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5622	{ 1831, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5623	{ 1830, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5624	{ 1829, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5625	{ 1828, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5626	{ 1827, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5627	{ 1826, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5628	{ 1825, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	----
5629	{ 1824, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	----
5630	{ 1823, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5631	{ 1822, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5632	{ 1821, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
5633	{ 1820, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
5634	{ 1819, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 829, 0\|(1ULL<	----
5635	{ 1818, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 829, 0\|(1ULL<	----
5636	{ 1817, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5637	{ 1816, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5638	{ 1815, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5639	{ 1814, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5640	{ 1813, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	----
5641	{ 1812, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5642	{ 1811, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5643	{ 1810, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
5644	{ 1809, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
5645	{ 1808, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5646	{ 1807, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5647	{ 1806, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5648	{ 1805, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5649	{ 1804, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5650	{ 1803, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
5651	{ 1802, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5652	{ 1801, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5653	{ 1800, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	----
5654	{ 1799, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 350, 0\|(1ULL<	----
5655	{ 1798, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	----
5656	{ 1797, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	----
5657	{ 1796, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 350, 0\|(1ULL<	----
5658	{ 1795, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	----
5659	{ 1794, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5660	{ 1793, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5661	{ 1792, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5662	{ 1791, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5663	{ 1790, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	----
5664	{ 1789, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	----
5665	{ 1788, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
5666	{ 1787, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	----
5667	{ 1786, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	----
5668	{ 1785, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	----
5669	{ 1784, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
5670	{ 1783, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	----
5671	{ 1782, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 373, 0\|(1ULL<	----
5672	{ 1781, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	----
5673	{ 1780, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	----
5674	{ 1779, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
5675	{ 1778, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	----
5676	{ 1777, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 785, 0, 0x1ULL }, // Inst #1777 = INS_MMR6	----
5677	{ 1776, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	----
5678	{ 1775, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	----
5679	{ 1774, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 824, 0, 0x6ULL }, // Inst #1774 = INSVE_W	----
5680	{ 1773, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 819, 0, 0x6ULL }, // Inst #1773 = INSVE_H	----
5681	{ 1772, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1772 = INSVE_D	----
5682	{ 1771, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 809, 0, 0x6ULL }, // Inst #1771 = INSVE_B	----
5683	{ 1770, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	----
5684	{ 1769, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1769 = INSERT_W	----
5685	{ 1768, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1768 = INSERT_H	----
5686	{ 1767, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1767 = INSERT_D	----
5687	{ 1766, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 790, 0, 0x6ULL }, // Inst #1766 = INSERT_B	----
5688	{ 1765, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	----
5689	{ 1764, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1764 = ILVR_W	----
5690	{ 1763, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1763 = ILVR_H	----
5691	{ 1762, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1762 = ILVR_D	----
5692	{ 1761, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1761 = ILVR_B	----
5693	{ 1760, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1760 = ILVOD_W	----
5694	{ 1759, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1759 = ILVOD_H	----
5695	{ 1758, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1758 = ILVOD_D	----
5696	{ 1757, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1757 = ILVOD_B	----
5697	{ 1756, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1756 = ILVL_W	----
5698	{ 1755, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1755 = ILVL_H	----
5699	{ 1754, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1754 = ILVL_D	----
5700	{ 1753, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1753 = ILVL_B	----
5701	{ 1752, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1752 = ILVEV_W	----
5702	{ 1751, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1751 = ILVEV_H	----
5703	{ 1750, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1750 = ILVEV_D	----
5704	{ 1749, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1749 = ILVEV_B	----
5705	{ 1748, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5706	{ 1747, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
5707	{ 1746, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1746 = HSUB_U_W	----
5708	{ 1745, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1745 = HSUB_U_H	----
5709	{ 1744, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1744 = HSUB_U_D	----
5710	{ 1743, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1743 = HSUB_S_W	----
5711	{ 1742, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1742 = HSUB_S_H	----
5712	{ 1741, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1741 = HSUB_S_D	----
5713	{ 1740, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1740 = HADD_U_W	----
5714	{ 1739, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1739 = HADD_U_H	----
5715	{ 1738, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1738 = HADD_U_D	----
5716	{ 1737, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1737 = HADD_S_W	----
5717	{ 1736, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1736 = HADD_S_H	----
5718	{ 1735, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1735 = HADD_S_D	----
5719	{ 1734, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5720	{ 1733, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
5721	{ 1732, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5722	{ 1731, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5723	{ 1730, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1730 = FTRUNC_U_W	----
5724	{ 1729, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1729 = FTRUNC_U_D	----
5725	{ 1728, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1728 = FTRUNC_S_W	----
5726	{ 1727, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1727 = FTRUNC_S_D	----
5727	{ 1726, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1726 = FTQ_W	----
5728	{ 1725, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1725 = FTQ_H	----
5729	{ 1724, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1724 = FTINT_U_W	----
5730	{ 1723, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1723 = FTINT_U_D	----
5731	{ 1722, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1722 = FTINT_S_W	----
5732	{ 1721, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1721 = FTINT_S_D	----
5733	{ 1720, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1720 = FSUN_W	----
5734	{ 1719, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1719 = FSUN_D	----
5735	{ 1718, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1718 = FSUNE_W	----
5736	{ 1717, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1717 = FSUNE_D	----
5737	{ 1716, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1716 = FSULT_W	----
5738	{ 1715, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1715 = FSULT_D	----
5739	{ 1714, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1714 = FSULE_W	----
5740	{ 1713, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1713 = FSULE_D	----
5741	{ 1712, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1712 = FSUEQ_W	----
5742	{ 1711, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1711 = FSUEQ_D	----
5743	{ 1710, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1710 = FSUB_W	----
5744	{ 1709, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1709 = FSUB_S_MMR6	----
5745	{ 1708, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1708 = FSUB_S_MM	----
5746	{ 1707, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1707 = FSUB_S	----
5747	{ 1706, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5748	{ 1705, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1705 = FSUB_D64_MM	----
5749	{ 1704, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1704 = FSUB_D64	----
5750	{ 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1703 = FSUB_D32_MM	----
5751	{ 1702, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1702 = FSUB_D32	----
5752	{ 1701, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1701 = FSUB_D	----
5753	{ 1700, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1700 = FSQRT_W	----
5754	{ 1699, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1699 = FSQRT_S_MM	----
5755	{ 1698, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1698 = FSQRT_S	----
5756	{ 1697, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1697 = FSQRT_D64_MM	----
5757	{ 1696, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1696 = FSQRT_D64	----
5758	{ 1695, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1695 = FSQRT_D32_MM	----
5759	{ 1694, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1694 = FSQRT_D32	----
5760	{ 1693, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1693 = FSQRT_D	----
5761	{ 1692, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1692 = FSOR_W	----
5762	{ 1691, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1691 = FSOR_D	----
5763	{ 1690, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1690 = FSNE_W	----
5764	{ 1689, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1689 = FSNE_D	----
5765	{ 1688, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1688 = FSLT_W	----
5766	{ 1687, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1687 = FSLT_D	----
5767	{ 1686, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1686 = FSLE_W	----
5768	{ 1685, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1685 = FSLE_D	----
5769	{ 1684, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1684 = FSEQ_W	----
5770	{ 1683, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1683 = FSEQ_D	----
5771	{ 1682, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1682 = FSAF_W	----
5772	{ 1681, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1681 = FSAF_D	----
5773	{ 1680, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1680 = FRSQRT_W	----
5774	{ 1679, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1679 = FRSQRT_D	----
5775	{ 1678, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1678 = FRINT_W	----
5776	{ 1677, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1677 = FRINT_D	----
5777	{ 1676, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1676 = FRCP_W	----
5778	{ 1675, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1675 = FRCP_D	----
5779	{ 1674, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
5780	{ 1673, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1673 = FNEG_S_MMR6	----
5781	{ 1672, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1672 = FNEG_S_MM	----
5782	{ 1671, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1671 = FNEG_S	----
5783	{ 1670, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1670 = FNEG_D64_MM	----
5784	{ 1669, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1669 = FNEG_D64	----
5785	{ 1668, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1668 = FNEG_D32_MM	----
5786	{ 1667, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1667 = FNEG_D32	----
5787	{ 1666, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1666 = FMUL_W	----
5788	{ 1665, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5789	{ 1664, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5790	{ 1663, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5791	{ 1662, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5792	{ 1661, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5793	{ 1660, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5794	{ 1659, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	----
5795	{ 1658, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	----
5796	{ 1657, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1657 = FMUL_D	----
5797	{ 1656, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1656 = FMSUB_W	----
5798	{ 1655, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1655 = FMSUB_D	----
5799	{ 1654, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1654 = FMOV_S_MMR6	----
5800	{ 1653, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
5801	{ 1652, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
5802	{ 1651, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1651 = FMOV_D_MMR6	----
5803	{ 1650, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1650 = FMOV_D64_MM	----
5804	{ 1649, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	----
5805	{ 1648, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1648 = FMOV_D32_MM	----
5806	{ 1647, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 750, 0\|(1ULL<	----
5807	{ 1646, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1646 = FMIN_W	----
5808	{ 1645, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1645 = FMIN_D	----
5809	{ 1644, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1644 = FMIN_A_W	----
5810	{ 1643, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1643 = FMIN_A_D	----
5811	{ 1642, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1642 = FMAX_W	----
5812	{ 1641, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1641 = FMAX_D	----
5813	{ 1640, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1640 = FMAX_A_W	----
5814	{ 1639, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1639 = FMAX_A_D	----
5815	{ 1638, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1638 = FMADD_W	----
5816	{ 1637, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1637 = FMADD_D	----
5817	{ 1636, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1636 = FLOOR_W_S_MMR6	----
5818	{ 1635, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1635 = FLOOR_W_S_MM	----
5819	{ 1634, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1634 = FLOOR_W_S	----
5820	{ 1633, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1633 = FLOOR_W_MM	----
5821	{ 1632, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1632 = FLOOR_W_D_MMR6	----
5822	{ 1631, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1631 = FLOOR_W_D64	----
5823	{ 1630, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1630 = FLOOR_W_D32	----
5824	{ 1629, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1629 = FLOOR_L_S_MMR6	----
5825	{ 1628, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1628 = FLOOR_L_S	----
5826	{ 1627, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1627 = FLOOR_L_D_MMR6	----
5827	{ 1626, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1626 = FLOOR_L_D64	----
5828	{ 1625, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1625 = FLOG2_W	----
5829	{ 1624, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1624 = FLOG2_D	----
5830	{ 1623, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1623 = FILL_W	----
5831	{ 1622, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1622 = FILL_H	----
5832	{ 1621, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1621 = FILL_D	----
5833	{ 1620, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1620 = FILL_B	----
5834	{ 1619, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1619 = FFQR_W	----
5835	{ 1618, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1618 = FFQR_D	----
5836	{ 1617, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1617 = FFQL_W	----
5837	{ 1616, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1616 = FFQL_D	----
5838	{ 1615, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1615 = FFINT_U_W	----
5839	{ 1614, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1614 = FFINT_U_D	----
5840	{ 1613, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1613 = FFINT_S_W	----
5841	{ 1612, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1612 = FFINT_S_D	----
5842	{ 1611, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1611 = FEXUPR_W	----
5843	{ 1610, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1610 = FEXUPR_D	----
5844	{ 1609, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1609 = FEXUPL_W	----
5845	{ 1608, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1608 = FEXUPL_D	----
5846	{ 1607, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1607 = FEXP2_W	----
5847	{ 1606, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1606 = FEXP2_D	----
5848	{ 1605, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1605 = FEXDO_W	----
5849	{ 1604, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1604 = FEXDO_H	----
5850	{ 1603, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1603 = FDIV_W	----
5851	{ 1602, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1602 = FDIV_S_MMR6	----
5852	{ 1601, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1601 = FDIV_S_MM	----
5853	{ 1600, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1600 = FDIV_S	----
5854	{ 1599, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1599 = FDIV_D64_MM	----
5855	{ 1598, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1598 = FDIV_D64	----
5856	{ 1597, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1597 = FDIV_D32_MM	----
5857	{ 1596, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1596 = FDIV_D32	----
5858	{ 1595, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1595 = FDIV_D	----
5859	{ 1594, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5860	{ 1593, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5861	{ 1592, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5862	{ 1591, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5863	{ 1590, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5864	{ 1589, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5865	{ 1588, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5866	{ 1587, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5867	{ 1586, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5868	{ 1585, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5869	{ 1584, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5870	{ 1583, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5871	{ 1582, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5872	{ 1581, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5873	{ 1580, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1580 = FCMP_S32_MM	----
5874	{ 1579, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1579 = FCMP_S32	----
5875	{ 1578, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 761, 0, 0x44ULL }, // Inst #1578 = FCMP_D64	----
5876	{ 1577, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1577 = FCMP_D32_MM	----
5877	{ 1576, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1576 = FCMP_D32	----
5878	{ 1575, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1575 = FCLT_W	----
5879	{ 1574, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1574 = FCLT_D	----
5880	{ 1573, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1573 = FCLE_W	----
5881	{ 1572, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1572 = FCLE_D	----
5882	{ 1571, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1571 = FCLASS_W	----
5883	{ 1570, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1570 = FCLASS_D	----
5884	{ 1569, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5885	{ 1568, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5886	{ 1567, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5887	{ 1566, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5888	{ 1565, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
5889	{ 1564, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5890	{ 1563, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5891	{ 1562, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	----
5892	{ 1561, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5893	{ 1560, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5894	{ 1559, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
5895	{ 1558, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	----
5896	{ 1557, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	----
5897	{ 1556, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
5898	{ 1555, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1555 = FABS_S_MM	----
5899	{ 1554, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1554 = FABS_S	----
5900	{ 1553, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1553 = FABS_D64_MM	----
5901	{ 1552, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1552 = FABS_D64	----
5902	{ 1551, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1551 = FABS_D32_MM	----
5903	{ 1550, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1550 = FABS_D32	----
5904	{ 1549, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1549 = EXT_MMR6	----
5905	{ 1548, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1548 = EXT_MM	----
5906	{ 1547, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	----
5907	{ 1546, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	----
5908	{ 1545, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5909	{ 1544, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5910	{ 1543, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5911	{ 1542, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5912	{ 1541, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5913	{ 1540, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5914	{ 1539, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5915	{ 1538, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	----
5916	{ 1537, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5917	{ 1536, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5918	{ 1535, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5919	{ 1534, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5920	{ 1533, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5921	{ 1532, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5922	{ 1531, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5923	{ 1530, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	----
5924	{ 1529, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	----
5925	{ 1528, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	----
5926	{ 1527, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	----
5927	{ 1526, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	----
5928	{ 1525, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	----
5929	{ 1524, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	----
5930	{ 1523, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	----
5931	{ 1522, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	----
5932	{ 1521, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1521 = EXT	----
5933	{ 1520, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5934	{ 1519, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5935	{ 1518, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5936	{ 1517, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5937	{ 1516, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5938	{ 1515, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5939	{ 1514, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5940	{ 1513, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5941	{ 1512, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5942	{ 1511, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5943	{ 1510, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5944	{ 1509, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5945	{ 1508, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5946	{ 1507, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5947	{ 1506, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
5948	{ 1505, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1505 = DivuRxRy16	----
5949	{ 1504, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1504 = DivRxRy16	----
5950	{ 1503, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5951	{ 1502, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5952	{ 1501, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
5953	{ 1500, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	----
5954	{ 1499, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
5955	{ 1498, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
5956	{ 1497, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1497 = DSRLV	----
5957	{ 1496, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
5958	{ 1495, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1495 = DSRL	----
5959	{ 1494, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1494 = DSRAV	----
5960	{ 1493, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
5961	{ 1492, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1492 = DSRA	----
5962	{ 1491, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1491 = DSLLV	----
5963	{ 1490, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	----
5964	{ 1489, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
5965	{ 1488, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1488 = DSLL	----
5966	{ 1487, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1487 = DSHD	----
5967	{ 1486, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	----
5968	{ 1485, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1485 = DSBH	----
5969	{ 1484, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1484 = DROTRV	----
5970	{ 1483, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
5971	{ 1482, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1482 = DROTR	----
5972	{ 1481, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1481 = DPS_W_PH_MMR2	----
5973	{ 1480, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1480 = DPS_W_PH	----
5974	{ 1479, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1479 = DPSX_W_PH_MMR2	----
5975	{ 1478, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1478 = DPSX_W_PH	----
5976	{ 1477, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1477 = DPSU_H_QBR_MM	----
5977	{ 1476, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1476 = DPSU_H_QBR	----
5978	{ 1475, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1475 = DPSU_H_QBL_MM	----
5979	{ 1474, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1474 = DPSU_H_QBL	----
5980	{ 1473, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1473 = DPSUB_U_W	----
5981	{ 1472, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1472 = DPSUB_U_H	----
5982	{ 1471, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1471 = DPSUB_U_D	----
5983	{ 1470, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1470 = DPSUB_S_W	----
5984	{ 1469, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1469 = DPSUB_S_H	----
5985	{ 1468, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1468 = DPSUB_S_D	----
5986	{ 1467, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5987	{ 1466, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5988	{ 1465, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5989	{ 1464, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5990	{ 1463, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5991	{ 1462, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5992	{ 1461, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5993	{ 1460, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
5994	{ 1459, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1459 = DPOP	----
5995	{ 1458, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1458 = DPA_W_PH_MMR2	----
5996	{ 1457, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1457 = DPA_W_PH	----
5997	{ 1456, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1456 = DPAX_W_PH_MMR2	----
5998	{ 1455, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1455 = DPAX_W_PH	----
5999	{ 1454, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1454 = DPAU_H_QBR_MM	----
6000	{ 1453, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1453 = DPAU_H_QBR	----
6001	{ 1452, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1452 = DPAU_H_QBL_MM	----
6002	{ 1451, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1451 = DPAU_H_QBL	----
6003	{ 1450, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6004	{ 1449, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6005	{ 1448, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6006	{ 1447, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6007	{ 1446, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6008	{ 1445, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6009	{ 1444, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6010	{ 1443, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	----
6011	{ 1442, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	----
6012	{ 1441, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	----
6013	{ 1440, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	----
6014	{ 1439, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	----
6015	{ 1438, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	----
6016	{ 1437, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	----
6017	{ 1436, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	----
6018	{ 1435, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	----
6019	{ 1434, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	----
6020	{ 1433, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	----
6021	{ 1432, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	----
6022	{ 1431, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	----
6023	{ 1430, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1430 = DMUL_R6	----
6024	{ 1429, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6025	{ 1428, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	----
6026	{ 1427, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	----
6027	{ 1426, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 219, 0\|(1ULL<	----
6028	{ 1425, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1425 = DMUHU	----
6029	{ 1424, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1424 = DMUH	----
6030	{ 1423, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	----
6031	{ 1422, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
6032	{ 1421, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 711, 0\|(1ULL<	----
6033	{ 1420, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	----
6034	{ 1419, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	----
6035	{ 1418, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6036	{ 1417, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6037	{ 1416, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6038	{ 1415, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	----
6039	{ 1414, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
6040	{ 1413, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 705, 0\|(1ULL<	----
6041	{ 1412, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 703, 0\|(1ULL<	----
6042	{ 1411, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	----
6043	{ 1410, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	----
6044	{ 1409, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0, 0x6ULL }, // Inst #1409 = DLSA	----
6045	{ 1408, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6046	{ 1407, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6047	{ 1406, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1406 = DIV_U_W	----
6048	{ 1405, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1405 = DIV_U_H	----
6049	{ 1404, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1404 = DIV_U_D	----
6050	{ 1403, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1403 = DIV_U_B	----
6051	{ 1402, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1402 = DIV_S_W	----
6052	{ 1401, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1401 = DIV_S_H	----
6053	{ 1400, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1400 = DIV_S_D	----
6054	{ 1399, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1399 = DIV_S_B	----
6055	{ 1398, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6056	{ 1397, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6057	{ 1396, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6058	{ 1395, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6059	{ 1394, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	----
6060	{ 1393, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	----
6061	{ 1392, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	----
6062	{ 1391, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6063	{ 1390, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1390 = DEXTU	----
6064	{ 1389, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1389 = DEXTM	----
6065	{ 1388, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1388 = DEXT64_32	----
6066	{ 1387, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1387 = DEXT	----
6067	{ 1386, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6068	{ 1385, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6069	{ 1384, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6070	{ 1383, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6071	{ 1382, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6072	{ 1381, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1381 = DCLZ_R6	----
6073	{ 1380, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1380 = DCLZ	----
6074	{ 1379, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1379 = DCLO_R6	----
6075	{ 1378, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1378 = DCLO	----
6076	{ 1377, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	----
6077	{ 1376, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6078	{ 1375, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	----
6079	{ 1374, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	----
6080	{ 1373, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	----
6081	{ 1372, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6082	{ 1371, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6083	{ 1370, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6084	{ 1369, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6085	{ 1368, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
6086	{ 1367, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	----
6087	{ 1366, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	----
6088	{ 1365, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6089	{ 1364, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6090	{ 1363, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6091	{ 1362, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6092	{ 1361, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6093	{ 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6094	{ 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6095	{ 1358, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6096	{ 1357, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6097	{ 1356, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6098	{ 1355, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6099	{ 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6100	{ 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6101	{ 1352, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6102	{ 1351, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6103	{ 1350, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6104	{ 1349, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6105	{ 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6106	{ 1347, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6107	{ 1346, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6108	{ 1345, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6109	{ 1344, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6110	{ 1343, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6111	{ 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6112	{ 1341, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6113	{ 1340, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6114	{ 1339, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6115	{ 1338, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6116	{ 1337, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6117	{ 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6118	{ 1335, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6119	{ 1334, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6120	{ 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6121	{ 1332, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6122	{ 1331, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6123	{ 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6124	{ 1329, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6125	{ 1328, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6126	{ 1327, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6127	{ 1326, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6128	{ 1325, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6129	{ 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6130	{ 1323, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6131	{ 1322, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6132	{ 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6133	{ 1320, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6134	{ 1319, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6135	{ 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6136	{ 1317, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6137	{ 1316, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6138	{ 1315, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6139	{ 1314, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6140	{ 1313, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6141	{ 1312, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6142	{ 1311, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6143	{ 1310, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6144	{ 1309, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6145	{ 1308, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6146	{ 1307, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6147	{ 1306, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6148	{ 1305, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6149	{ 1304, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6150	{ 1303, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6151	{ 1302, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6152	{ 1301, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6153	{ 1300, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6154	{ 1299, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6155	{ 1298, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6156	{ 1297, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6157	{ 1296, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6158	{ 1295, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6159	{ 1294, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6160	{ 1293, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6161	{ 1292, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6162	{ 1291, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6163	{ 1290, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6164	{ 1289, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6165	{ 1288, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6166	{ 1287, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6167	{ 1286, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6168	{ 1285, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6169	{ 1284, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6170	{ 1283, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6171	{ 1282, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6172	{ 1281, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6173	{ 1280, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6174	{ 1279, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6175	{ 1278, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6176	{ 1277, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6177	{ 1276, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6178	{ 1275, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6179	{ 1274, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	----
6180	{ 1273, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6181	{ 1272, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	----
6182	{ 1271, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6183	{ 1270, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	----
6184	{ 1269, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1269 = CVT_W_S_MMR6	----
6185	{ 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_W_S_MM	----
6186	{ 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_W_S	----
6187	{ 1266, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1266 = CVT_W_D64_MM	----
6188	{ 1265, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1265 = CVT_W_D64	----
6189	{ 1264, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_W_D32_MM	----
6190	{ 1263, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1263 = CVT_W_D32	----
6191	{ 1262, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1262 = CVT_S_W_MMR6	----
6192	{ 1261, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1261 = CVT_S_W_MM	----
6193	{ 1260, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1260 = CVT_S_W	----
6194	{ 1259, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1259 = CVT_S_PU64	----
6195	{ 1258, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1258 = CVT_S_PL64	----
6196	{ 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1257 = CVT_S_L_MMR6	----
6197	{ 1256, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_S_L	----
6198	{ 1255, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_S_D64_MM	----
6199	{ 1254, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_S_D64	----
6200	{ 1253, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1253 = CVT_S_D32_MM	----
6201	{ 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_S_D32	----
6202	{ 1251, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1251 = CVT_PW_PS64	----
6203	{ 1250, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 676, 0\|(1ULL<	----
6204	{ 1249, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1249 = CVT_PS_PW64	----
6205	{ 1248, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1248 = CVT_L_S_MMR6	----
6206	{ 1247, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1247 = CVT_L_S_MM	----
6207	{ 1246, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1246 = CVT_L_S	----
6208	{ 1245, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1245 = CVT_L_D_MMR6	----
6209	{ 1244, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1244 = CVT_L_D64_MM	----
6210	{ 1243, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1243 = CVT_L_D64	----
6211	{ 1242, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1242 = CVT_D_L_MMR6	----
6212	{ 1241, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1241 = CVT_D64_W_MM	----
6213	{ 1240, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1240 = CVT_D64_W	----
6214	{ 1239, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1239 = CVT_D64_S_MM	----
6215	{ 1238, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1238 = CVT_D64_S	----
6216	{ 1237, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1237 = CVT_D64_L	----
6217	{ 1236, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1236 = CVT_D32_W_MM	----
6218	{ 1235, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1235 = CVT_D32_W	----
6219	{ 1234, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1234 = CVT_D32_S_MM	----
6220	{ 1233, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1233 = CVT_D32_S	----
6221	{ 1232, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 672, 0\|(1ULL<	----
6222	{ 1231, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	----
6223	{ 1230, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	----
6224	{ 1229, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	----
6225	{ 1228, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6226	{ 1227, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6227	{ 1226, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6228	{ 1225, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6229	{ 1224, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6230	{ 1223, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6231	{ 1222, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6232	{ 1221, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6233	{ 1220, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1220 = COPY_U_W	----
6234	{ 1219, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1219 = COPY_U_H	----
6235	{ 1218, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1218 = COPY_U_B	----
6236	{ 1217, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1217 = COPY_S_W	----
6237	{ 1216, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1216 = COPY_S_H	----
6238	{ 1215, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 659, 0, 0x6ULL }, // Inst #1215 = COPY_S_D	----
6239	{ 1214, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1214 = COPY_S_B	----
6240	{ 1213, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1213 = CMP_UN_S_MMR6	----
6241	{ 1212, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1212 = CMP_UN_S	----
6242	{ 1211, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1211 = CMP_UN_D_MMR6	----
6243	{ 1210, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1210 = CMP_UN_D	----
6244	{ 1209, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1209 = CMP_ULT_S_MMR6	----
6245	{ 1208, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1208 = CMP_ULT_S	----
6246	{ 1207, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1207 = CMP_ULT_D_MMR6	----
6247	{ 1206, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1206 = CMP_ULT_D	----
6248	{ 1205, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1205 = CMP_ULE_S_MMR6	----
6249	{ 1204, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1204 = CMP_ULE_S	----
6250	{ 1203, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1203 = CMP_ULE_D_MMR6	----
6251	{ 1202, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1202 = CMP_ULE_D	----
6252	{ 1201, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1201 = CMP_UEQ_S_MMR6	----
6253	{ 1200, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1200 = CMP_UEQ_S	----
6254	{ 1199, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1199 = CMP_UEQ_D_MMR6	----
6255	{ 1198, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1198 = CMP_UEQ_D	----
6256	{ 1197, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6257	{ 1196, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6258	{ 1195, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6259	{ 1194, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6260	{ 1193, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6261	{ 1192, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6262	{ 1191, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6263	{ 1190, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6264	{ 1189, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6265	{ 1188, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6266	{ 1187, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6267	{ 1186, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6268	{ 1185, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6269	{ 1184, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6270	{ 1183, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6271	{ 1182, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6272	{ 1181, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6273	{ 1180, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6274	{ 1179, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6275	{ 1178, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6276	{ 1177, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6277	{ 1176, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6278	{ 1175, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6279	{ 1174, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6280	{ 1173, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6281	{ 1172, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6282	{ 1171, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6283	{ 1170, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6284	{ 1169, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6285	{ 1168, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6286	{ 1167, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6287	{ 1166, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6288	{ 1165, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1165 = CMP_LT_S_MMR6	----
6289	{ 1164, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1164 = CMP_LT_S	----
6290	{ 1163, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6291	{ 1162, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6292	{ 1161, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1161 = CMP_LT_D_MMR6	----
6293	{ 1160, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1160 = CMP_LT_D	----
6294	{ 1159, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1159 = CMP_LE_S_MMR6	----
6295	{ 1158, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1158 = CMP_LE_S	----
6296	{ 1157, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6297	{ 1156, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6298	{ 1155, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1155 = CMP_LE_D_MMR6	----
6299	{ 1154, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1154 = CMP_LE_D	----
6300	{ 1153, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6301	{ 1152, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6302	{ 1151, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1151 = CMP_EQ_S_MMR6	----
6303	{ 1150, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1150 = CMP_EQ_S	----
6304	{ 1149, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6305	{ 1148, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6306	{ 1147, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1147 = CMP_EQ_D_MMR6	----
6307	{ 1146, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1146 = CMP_EQ_D	----
6308	{ 1145, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	----
6309	{ 1144, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	----
6310	{ 1143, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6311	{ 1142, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6312	{ 1141, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6313	{ 1140, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6314	{ 1139, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6315	{ 1138, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	----
6316	{ 1137, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6317	{ 1136, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6318	{ 1135, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6319	{ 1134, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6320	{ 1133, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6321	{ 1132, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	----
6322	{ 1131, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6323	{ 1130, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6324	{ 1129, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6325	{ 1128, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6326	{ 1127, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6327	{ 1126, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	----
6328	{ 1125, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1125 = CLZ_R6	----
6329	{ 1124, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6330	{ 1123, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1123 = CLZ_MM	----
6331	{ 1122, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1122 = CLZ	----
6332	{ 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1121 = CLT_U_W	----
6333	{ 1120, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1120 = CLT_U_H	----
6334	{ 1119, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1119 = CLT_U_D	----
6335	{ 1118, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1118 = CLT_U_B	----
6336	{ 1117, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1117 = CLT_S_W	----
6337	{ 1116, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1116 = CLT_S_H	----
6338	{ 1115, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1115 = CLT_S_D	----
6339	{ 1114, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1114 = CLT_S_B	----
6340	{ 1113, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1113 = CLTI_U_W	----
6341	{ 1112, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1112 = CLTI_U_H	----
6342	{ 1111, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1111 = CLTI_U_D	----
6343	{ 1110, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1110 = CLTI_U_B	----
6344	{ 1109, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1109 = CLTI_S_W	----
6345	{ 1108, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1108 = CLTI_S_H	----
6346	{ 1107, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1107 = CLTI_S_D	----
6347	{ 1106, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1106 = CLTI_S_B	----
6348	{ 1105, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1105 = CLO_R6	----
6349	{ 1104, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6350	{ 1103, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1103 = CLO_MM	----
6351	{ 1102, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1102 = CLO	----
6352	{ 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1101 = CLE_U_W	----
6353	{ 1100, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1100 = CLE_U_H	----
6354	{ 1099, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1099 = CLE_U_D	----
6355	{ 1098, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1098 = CLE_U_B	----
6356	{ 1097, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1097 = CLE_S_W	----
6357	{ 1096, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1096 = CLE_S_H	----
6358	{ 1095, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1095 = CLE_S_D	----
6359	{ 1094, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1094 = CLE_S_B	----
6360	{ 1093, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1093 = CLEI_U_W	----
6361	{ 1092, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1092 = CLEI_U_H	----
6362	{ 1091, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1091 = CLEI_U_D	----
6363	{ 1090, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1090 = CLEI_U_B	----
6364	{ 1089, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1089 = CLEI_S_W	----
6365	{ 1088, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1088 = CLEI_S_H	----
6366	{ 1087, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1087 = CLEI_S_D	----
6367	{ 1086, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1086 = CLEI_S_B	----
6368	{ 1085, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
6369	{ 1084, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	----
6370	{ 1083, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	----
6371	{ 1082, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	----
6372	{ 1081, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1081 = CINS_i32	----
6373	{ 1080, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1080 = CINS64_32	----
6374	{ 1079, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1079 = CINS32	----
6375	{ 1078, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1078 = CINS	----
6376	{ 1077, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 633, 0\|(1ULL<	----
6377	{ 1076, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	----
6378	{ 1075, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	----
6379	{ 1074, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	----
6380	{ 1073, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6381	{ 1072, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6382	{ 1071, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6383	{ 1070, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6384	{ 1069, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1069 = CEQI_W	----
6385	{ 1068, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1068 = CEQI_H	----
6386	{ 1067, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1067 = CEQI_D	----
6387	{ 1066, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1066 = CEQI_B	----
6388	{ 1065, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1065 = CEIL_W_S_MMR6	----
6389	{ 1064, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1064 = CEIL_W_S_MM	----
6390	{ 1063, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1063 = CEIL_W_S	----
6391	{ 1062, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1062 = CEIL_W_MM	----
6392	{ 1061, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1061 = CEIL_W_D_MMR6	----
6393	{ 1060, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1060 = CEIL_W_D64	----
6394	{ 1059, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1059 = CEIL_W_D32	----
6395	{ 1058, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1058 = CEIL_L_S_MMR6	----
6396	{ 1057, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1057 = CEIL_L_S	----
6397	{ 1056, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1056 = CEIL_L_D_MMR6	----
6398	{ 1055, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1055 = CEIL_L_D64	----
6399	{ 1054, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6400	{ 1053, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6401	{ 1052, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6402	{ 1051, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6403	{ 1050, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6404	{ 1049, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	----
6405	{ 1048, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	----
6406	{ 1047, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	----
6407	{ 1046, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	----
6408	{ 1045, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	----
6409	{ 1044, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6410	{ 1043, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	----
6411	{ 1042, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	----
6412	{ 1041, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6413	{ 1040, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6414	{ 1039, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	----
6415	{ 1038, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	----
6416	{ 1037, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	----
6417	{ 1036, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	----
6418	{ 1035, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	----
6419	{ 1034, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	----
6420	{ 1033, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	----
6421	{ 1032, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1032 = BSET_W	----
6422	{ 1031, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1031 = BSET_H	----
6423	{ 1030, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1030 = BSET_D	----
6424	{ 1029, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1029 = BSET_B	----
6425	{ 1028, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1028 = BSETI_W	----
6426	{ 1027, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1027 = BSETI_H	----
6427	{ 1026, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1026 = BSETI_D	----
6428	{ 1025, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1025 = BSETI_B	----
6429	{ 1024, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1024 = BSEL_V	----
6430	{ 1023, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #1023 = BSELI_B	----
6431	{ 1022, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	----
6432	{ 1021, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	----
6433	{ 1020, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
6434	{ 1019, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
6435	{ 1018, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	----
6436	{ 1017, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6437	{ 1016, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6438	{ 1015, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6439	{ 1014, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6440	{ 1013, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6441	{ 1012, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	----
6442	{ 1011, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	----
6443	{ 1010, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	----
6444	{ 1009, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	----
6445	{ 1008, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	----
6446	{ 1007, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6447	{ 1006, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6448	{ 1005, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6449	{ 1004, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6450	{ 1003, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6451	{ 1002, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6452	{ 1001, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	----
6453	{ 1000, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6454	{ 999, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6455	{ 998, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6456	{ 997, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	----
6457	{ 996, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6458	{ 995, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #995 = BNEG_W	----
6459	{ 994, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #994 = BNEG_H	----
6460	{ 993, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #993 = BNEG_D	----
6461	{ 992, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #992 = BNEG_B	----
6462	{ 991, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #991 = BNEGI_W	----
6463	{ 990, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #990 = BNEGI_H	----
6464	{ 989, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #989 = BNEGI_D	----
6465	{ 988, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #988 = BNEGI_B	----
6466	{ 987, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6467	{ 986, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6468	{ 985, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6469	{ 984, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6470	{ 983, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6471	{ 982, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #982 = BMZ_V	----
6472	{ 981, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #981 = BMZI_B	----
6473	{ 980, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #980 = BMNZ_V	----
6474	{ 979, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #979 = BMNZI_B	----
6475	{ 978, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6476	{ 977, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6477	{ 976, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6478	{ 975, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6479	{ 974, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6480	{ 973, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6481	{ 972, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6482	{ 971, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6483	{ 970, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6484	{ 969, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6485	{ 968, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6486	{ 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6487	{ 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6488	{ 965, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6489	{ 964, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6490	{ 963, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6491	{ 962, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6492	{ 961, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6493	{ 960, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6494	{ 959, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6495	{ 958, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6496	{ 957, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6497	{ 956, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6498	{ 955, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6499	{ 954, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6500	{ 953, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6501	{ 952, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6502	{ 951, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6503	{ 950, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6504	{ 949, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6505	{ 948, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #948 = BITREV_MM	----
6506	{ 947, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #947 = BITREV	----
6507	{ 946, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #946 = BINSR_W	----
6508	{ 945, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #945 = BINSR_H	----
6509	{ 944, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #944 = BINSR_D	----
6510	{ 943, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #943 = BINSR_B	----
6511	{ 942, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #942 = BINSRI_W	----
6512	{ 941, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #941 = BINSRI_H	----
6513	{ 940, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #940 = BINSRI_D	----
6514	{ 939, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #939 = BINSRI_B	----
6515	{ 938, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #938 = BINSL_W	----
6516	{ 937, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #937 = BINSL_H	----
6517	{ 936, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #936 = BINSL_D	----
6518	{ 935, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #935 = BINSL_B	----
6519	{ 934, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #934 = BINSLI_W	----
6520	{ 933, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #933 = BINSLI_H	----
6521	{ 932, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #932 = BINSLI_D	----
6522	{ 931, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #931 = BINSLI_B	----
6523	{ 930, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6524	{ 929, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6525	{ 928, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6526	{ 927, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6527	{ 926, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6528	{ 925, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6529	{ 924, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6530	{ 923, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6531	{ 922, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6532	{ 921, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6533	{ 920, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6534	{ 919, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6535	{ 918, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6536	{ 917, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6537	{ 916, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6538	{ 915, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6539	{ 914, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6540	{ 913, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6541	{ 912, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6542	{ 911, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6543	{ 910, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6544	{ 909, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6545	{ 908, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6546	{ 907, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6547	{ 906, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6548	{ 905, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6549	{ 904, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6550	{ 903, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6551	{ 902, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6552	{ 901, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6553	{ 900, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6554	{ 899, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	----
6555	{ 898, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	----
6556	{ 897, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	----
6557	{ 896, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6558	{ 895, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	----
6559	{ 894, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	----
6560	{ 893, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6561	{ 892, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6562	{ 891, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6563	{ 890, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6564	{ 889, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	----
6565	{ 888, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	----
6566	{ 887, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6567	{ 886, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #886 = BCLR_W	----
6568	{ 885, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #885 = BCLR_H	----
6569	{ 884, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #884 = BCLR_D	----
6570	{ 883, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #883 = BCLR_B	----
6571	{ 882, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #882 = BCLRI_W	----
6572	{ 881, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #881 = BCLRI_H	----
6573	{ 880, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #880 = BCLRI_D	----
6574	{ 879, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #879 = BCLRI_B	----
6575	{ 878, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	----
6576	{ 877, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	----
6577	{ 876, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	----
6578	{ 875, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	----
6579	{ 874, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6580	{ 873, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6581	{ 872, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6582	{ 871, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	----
6583	{ 870, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	----
6584	{ 869, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6585	{ 868, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6586	{ 867, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	----
6587	{ 866, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	----
6588	{ 865, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	----
6589	{ 864, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	----
6590	{ 863, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
6591	{ 862, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	----
6592	{ 861, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	----
6593	{ 860, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	----
6594	{ 859, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	----
6595	{ 858, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #858 = BALIGN_MMR2	----
6596	{ 857, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #857 = BALIGN	----
6597	{ 856, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	----
6598	{ 855, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	----
6599	{ 854, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	----
6600	{ 853, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6601	{ 852, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	----
6602	{ 851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	----
6603	{ 850, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	----
6604	{ 849, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
6605	{ 848, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
6606	{ 847, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 569, 0, 0x0ULL }, // Inst #847 = AddiuRxRyOffMemX16	----
6607	{ 846, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	----
6608	{ 845, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	----
6609	{ 844, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	----
6610	{ 843, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	----
6611	{ 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6612	{ 841, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6613	{ 840, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6614	{ 839, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6615	{ 838, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6616	{ 837, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6617	{ 836, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6618	{ 835, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6619	{ 834, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6620	{ 833, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6621	{ 832, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6622	{ 831, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6623	{ 830, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6624	{ 829, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6625	{ 828, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6626	{ 827, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6627	{ 826, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6628	{ 825, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6629	{ 824, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6630	{ 823, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6631	{ 822, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #822 = ASUB_U_W	----
6632	{ 821, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #821 = ASUB_U_H	----
6633	{ 820, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #820 = ASUB_U_D	----
6634	{ 819, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #819 = ASUB_U_B	----
6635	{ 818, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #818 = ASUB_S_W	----
6636	{ 817, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #817 = ASUB_S_H	----
6637	{ 816, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #816 = ASUB_S_D	----
6638	{ 815, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #815 = ASUB_S_B	----
6639	{ 814, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #814 = APPEND_MMR2	----
6640	{ 813, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = APPEND	----
6641	{ 812, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6642	{ 811, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6643	{ 810, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6644	{ 809, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #809 = AND_V	----
6645	{ 808, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6646	{ 807, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6647	{ 806, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6648	{ 805, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #805 = ANDI_B	----
6649	{ 804, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #804 = ANDI16_MMR6	----
6650	{ 803, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #803 = ANDI16_MM	----
6651	{ 802, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
6652	{ 801, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
6653	{ 800, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	----
6654	{ 799, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6655	{ 798, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6656	{ 797, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6657	{ 796, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	----
6658	{ 795, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	----
6659	{ 794, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6660	{ 793, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6661	{ 792, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6662	{ 791, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6663	{ 790, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6664	{ 789, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6665	{ 788, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6666	{ 787, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6667	{ 786, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6668	{ 785, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6669	{ 784, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6670	{ 783, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6671	{ 782, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	----
6672	{ 781, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	----
6673	{ 780, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6674	{ 779, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6675	{ 778, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6676	{ 777, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6677	{ 776, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #776 = ADDVI_W	----
6678	{ 775, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #775 = ADDVI_H	----
6679	{ 774, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #774 = ADDVI_D	----
6680	{ 773, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #773 = ADDVI_B	----
6681	{ 772, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6682	{ 771, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6683	{ 770, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6684	{ 769, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6685	{ 768, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6686	{ 767, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6687	{ 766, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6688	{ 765, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6689	{ 764, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6690	{ 763, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6691	{ 762, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6692	{ 761, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6693	{ 760, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6694	{ 759, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	----
6695	{ 758, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	----
6696	{ 757, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6697	{ 756, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6698	{ 755, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6699	{ 754, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6700	{ 753, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6701	{ 752, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6702	{ 751, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6703	{ 750, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6704	{ 749, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6705	{ 748, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6706	{ 747, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6707	{ 746, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	----
6708	{ 745, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	----
6709	{ 744, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	----
6710	{ 743, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	----
6711	{ 742, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	----
6712	{ 741, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	----
6713	{ 740, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6714	{ 739, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6715	{ 738, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6716	{ 737, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	----
6717	{ 736, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6718	{ 735, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6719	{ 734, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6720	{ 733, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6721	{ 732, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6722	{ 731, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6723	{ 730, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6724	{ 729, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	----
6725	{ 728, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6726	{ 727, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
6727	{ 726, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #726 = ADDIUS5_MM	----
6728	{ 725, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	----
6729	{ 724, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	----
6730	{ 723, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6731	{ 722, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	----
6732	{ 721, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6733	{ 720, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6734	{ 719, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	----
6735	{ 718, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	----
6736	{ 717, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	----
6737	{ 716, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	----
6738	{ 715, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	----
6739	{ 714, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	----
6740	{ 713, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6741	{ 712, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6742	{ 711, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6743	{ 710, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6744	{ 709, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6745	{ 708, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6746	{ 707, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6747	{ 706, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6748	{ 705, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6749	{ 704, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6750	{ 703, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6751	{ 702, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6752	{ 701, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6753	{ 700, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6754	{ 699, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6755	{ 698, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	----
6756	{ 697, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	----
6757	{ 696, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6758	{ 695, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6759	{ 694, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	----
6760	{ 693, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6761	{ 692, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	----
6762	{ 691, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6763	{ 690, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6764	{ 689, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	----
6765	{ 688, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	----
6766	{ 687, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	----
6767	{ 686, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	----
6768	{ 685, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 392, 0\|(1ULL<	----
6769	{ 684, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	----
6770	{ 683, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	----
6771	{ 682, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	----
6772	{ 681, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	----
6773	{ 680, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6774	{ 679, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6775	{ 678, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6776	{ 677, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6777	{ 676, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6778	{ 675, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6779	{ 674, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6780	{ 673, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6781	{ 672, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6782	{ 671, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6783	{ 670, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	----
6784	{ 669, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	----
6785	{ 668, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	----
6786	{ 667, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	----
6787	{ 666, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
6788	{ 665, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
6789	{ 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	----
6790	{ 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	----
6791	{ 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	----
6792	{ 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	----
6793	{ 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	----
6794	{ 659, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	----
6795	{ 658, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	----
6796	{ 657, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	----
6797	{ 656, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	----
6798	{ 655, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	----
6799	{ 654, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	----
6800	{ 653, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	----
6801	{ 652, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	----
6802	{ 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6803	{ 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6804	{ 649, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	----
6805	{ 648, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	----
6806	{ 647, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	----
6807	{ 646, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	----
6808	{ 645, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	----
6809	{ 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6810	{ 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6811	{ 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6812	{ 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6813	{ 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6814	{ 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6815	{ 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6816	{ 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6817	{ 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6818	{ 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6819	{ 634, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6820	{ 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6821	{ 632, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6822	{ 631, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6823	{ 630, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6824	{ 629, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6825	{ 628, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6826	{ 627, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6827	{ 626, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6828	{ 625, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6829	{ 624, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6830	{ 623, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6831	{ 622, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0\|(1ULL<	----
6832	{ 621, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6833	{ 620, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6834	{ 619, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6835	{ 618, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	----
6836	{ 617, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6837	{ 616, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6838	{ 615, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6839	{ 614, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6840	{ 613, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6841	{ 612, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6842	{ 611, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6843	{ 610, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 485, 0\|(1ULL<	----
6844	{ 609, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 482, 0\|(1ULL<	----
6845	{ 608, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 479, 0\|(1ULL<	----
6846	{ 607, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0\|(1ULL<	----
6847	{ 606, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0\|(1ULL<	----
6848	{ 605, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0\|(1ULL<	----
6849	{ 604, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0\|(1ULL<	----
6850	{ 603, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0\|(1ULL<	----
6851	{ 602, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	----
6852	{ 601, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	----
6853	{ 600, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	----
6854	{ 599, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	----
6855	{ 598, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	----
6856	{ 597, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	----
6857	{ 596, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	----
6858	{ 595, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	----
6859	{ 594, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	----
6860	{ 593, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	----
6861	{ 592, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6862	{ 591, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
6863	{ 590, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6864	{ 589, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	----
6865	{ 588, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	----
6866	{ 587, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6867	{ 586, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6868	{ 585, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6869	{ 584, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6870	{ 583, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6871	{ 582, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	----
6872	{ 581, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	----
6873	{ 580, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	----
6874	{ 579, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6875	{ 578, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6876	{ 577, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6877	{ 576, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6878	{ 575, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	----
6879	{ 574, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	----
6880	{ 573, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	----
6881	{ 572, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	----
6882	{ 571, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	----
6883	{ 570, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	----
6884	{ 569, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6885	{ 568, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6886	{ 567, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6887	{ 566, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	----
6888	{ 565, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6889	{ 564, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
6890	{ 563, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
6891	{ 562, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6892	{ 561, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6893	{ 560, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6894	{ 559, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6895	{ 558, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
6896	{ 557, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	----
6897	{ 556, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6898	{ 555, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 414, 0\|(1ULL<	----
6899	{ 554, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 407, 0\|(1ULL<	----
6900	{ 553, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	----
6901	{ 552, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	----
6902	{ 551, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	----
6903	{ 550, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	----
6904	{ 549, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
6905	{ 548, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	----
6906	{ 547, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	----
6907	{ 546, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	----
6908	{ 545, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 398, 0\|(1ULL<	----
6909	{ 544, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6910	{ 543, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6911	{ 542, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6912	{ 541, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6913	{ 540, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6914	{ 539, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	----
6915	{ 538, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6916	{ 537, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6917	{ 536, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6918	{ 535, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
6919	{ 534, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
6920	{ 533, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
6921	{ 532, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
6922	{ 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6923	{ 530, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
6924	{ 529, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	----
6925	{ 528, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	----
6926	{ 527, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	----
6927	{ 526, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	----
6928	{ 525, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6929	{ 524, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
6930	{ 523, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6931	{ 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	----
6932	{ 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	----
6933	{ 520, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
6934	{ 519, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6935	{ 518, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6936	{ 517, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	----
6937	{ 516, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	----
6938	{ 515, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	----
6939	{ 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0\|(1ULL<	----
6940	{ 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0\|(1ULL<	----
6941	{ 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0\|(1ULL<	----
6942	{ 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0\|(1ULL<	----
6943	{ 510, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 373, 0\|(1ULL<	----
6944	{ 509, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 136, 0\|(1ULL<	----
6945	{ 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	----
6946	{ 507, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	----
6947	{ 506, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	----
6948	{ 505, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
6949	{ 504, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6950	{ 503, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	----
6951	{ 502, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	----
6952	{ 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	----
6953	{ 500, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 363, 0\|(1ULL<	----
6954	{ 499, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6955	{ 498, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0\|(1ULL<	----
6956	{ 497, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6957	{ 496, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0\|(1ULL<	----
6958	{ 495, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0\|(1ULL<	----
6959	{ 494, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
6960	{ 493, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	----
6961	{ 492, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	----
6962	{ 491, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6963	{ 490, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	----
6964	{ 489, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 348, 0\|(1ULL<	----
6965	{ 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	----
6966	{ 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0\|(1ULL<	----
6967	{ 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 341, 0\|(1ULL<	----
6968	{ 485, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 338, 0\|(1ULL<	----
6969	{ 484, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0\|(1ULL<	----
6970	{ 483, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0\|(1ULL<	----
6971	{ 482, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
6972	{ 481, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 327, 0\|(1ULL<	----
6973	{ 480, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	----
6974	{ 479, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	----
6975	{ 478, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	----
6976	{ 477, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	----
6977	{ 476, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	----
6978	{ 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	----
6979	{ 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	----
6980	{ 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	----
6981	{ 472, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
6982	{ 471, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	----
6983	{ 470, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	----
6984	{ 469, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	----
6985	{ 468, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	----
6986	{ 467, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	----
6987	{ 466, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	----
6988	{ 465, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0\|(1ULL<	----
6989	{ 464, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0\|(1ULL<	----
6990	{ 463, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0\|(1ULL<	----
6991	{ 462, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0\|(1ULL<	----
6992	{ 461, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0\|(1ULL<	----
6993	{ 460, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 278, 0\|(1ULL<	----
6994	{ 459, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 274, 0\|(1ULL<	----
6995	{ 458, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0\|(1ULL<	----
6996	{ 457, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0\|(1ULL<	----
6997	{ 456, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 262, 0\|(1ULL<	----
6998	{ 455, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0\|(1ULL<	----
6999	{ 454, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0\|(1ULL<	----
7000	{ 453, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0\|(1ULL<	----
7001	{ 452, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 246, 0\|(1ULL<	----
7002	{ 451, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 242, 0\|(1ULL<	----
7003	{ 450, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 240, 0\|(1ULL<	----
7004	{ 449, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 238, 0\|(1ULL<	----
7005	{ 448, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	----
7006	{ 447, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	----
7007	{ 446, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	----
7008	{ 445, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	----
7009	{ 444, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 231, 0\|(1ULL<	----
7010	{ 443, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 228, 0\|(1ULL<	----
7011	{ 442, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7012	{ 441, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7013	{ 440, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
7014	{ 439, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7015	{ 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
7016	{ 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7017	{ 436, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
7018	{ 435, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7019	{ 434, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
7020	{ 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
7021	{ 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
7022	{ 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	----
7023	{ 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	----
7024	{ 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7025	{ 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7026	{ 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	----
7027	{ 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	----
7028	{ 425, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7029	{ 424, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 214, 0\|(1ULL<	----
7030	{ 423, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 211, 0\|(1ULL<	----
7031	{ 422, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 208, 0\|(1ULL<	----
7032	{ 421, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	----
7033	{ 420, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 206, 0\|(1ULL<	----
7034	{ 419, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 203, 0\|(1ULL<	----
7035	{ 418, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 200, 0\|(1ULL<	----
7036	{ 417, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7037	{ 416, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7038	{ 415, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7039	{ 414, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7040	{ 413, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7041	{ 412, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7042	{ 411, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7043	{ 410, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7044	{ 409, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7045	{ 408, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7046	{ 407, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	----
7047	{ 406, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	----
7048	{ 405, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7049	{ 404, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7050	{ 403, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
7051	{ 402, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	----
7052	{ 401, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	----
7053	{ 400, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	----
7054	{ 399, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0\|(1ULL<	----
7055	{ 398, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	----
7056	{ 397, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	----
7057	{ 396, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	----
7058	{ 395, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 181, 0\|(1ULL<	----
7059	{ 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7060	{ 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7061	{ 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7062	{ 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7063	{ 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7064	{ 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7065	{ 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7066	{ 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7067	{ 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7068	{ 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7069	{ 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7070	{ 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7071	{ 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7072	{ 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7073	{ 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7074	{ 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7075	{ 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7076	{ 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7077	{ 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7078	{ 375, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7079	{ 374, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7080	{ 373, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7081	{ 372, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7082	{ 371, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7083	{ 370, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7084	{ 369, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7085	{ 368, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7086	{ 367, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7087	{ 366, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7088	{ 365, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7089	{ 364, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7090	{ 363, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7091	{ 362, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	----
7092	{ 361, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	----
7093	{ 360, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	----
7094	{ 359, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	----
7095	{ 358, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	----
7096	{ 357, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7097	{ 356, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7098	{ 355, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7099	{ 354, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7100	{ 353, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7101	{ 352, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7102	{ 351, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7103	{ 350, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7104	{ 349, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7105	{ 348, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7106	{ 347, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7107	{ 346, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7108	{ 345, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7109	{ 344, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7110	{ 343, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7111	{ 342, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7112	{ 341, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7113	{ 340, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7114	{ 339, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7115	{ 338, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7116	{ 337, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7117	{ 336, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7118	{ 335, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7119	{ 334, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7120	{ 333, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7121	{ 332, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7122	{ 331, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7123	{ 330, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7124	{ 329, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7125	{ 328, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7126	{ 327, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7127	{ 326, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7128	{ 325, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7129	{ 324, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7130	{ 323, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7131	{ 322, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7132	{ 321, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7133	{ 320, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7134	{ 319, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7135	{ 318, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7136	{ 317, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7137	{ 316, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7138	{ 315, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7139	{ 314, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7140	{ 313, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7141	{ 312, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7142	{ 311, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7143	{ 310, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7144	{ 309, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7145	{ 308, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7146	{ 307, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7147	{ 306, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7148	{ 305, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7149	{ 304, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7150	{ 303, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7151	{ 302, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7152	{ 301, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7153	{ 300, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7154	{ 299, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7155	{ 298, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7156	{ 297, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7157	{ 296, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7158	{ 295, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7159	{ 294, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7160	{ 293, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7161	{ 292, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7162	{ 291, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7163	{ 290, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7164	{ 289, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7165	{ 288, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7166	{ 287, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7167	{ 286, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7168	{ 285, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7169	{ 284, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7170	{ 283, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7171	{ 282, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7172	{ 281, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7173	{ 280, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7174	{ 279, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7175	{ 278, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7176	{ 277, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7177	{ 276, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7178	{ 275, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7179	{ 274, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	----
7180	{ 273, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7181	{ 272, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7182	{ 271, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	----
7183	{ 270, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	----
7184	{ 269, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	----
7185	{ 268, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	----
7186	{ 267, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	----
7187	{ 266, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	----
7188	{ 265, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	----
7189	{ 264, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	----
7190	{ 263, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	----
7191	{ 262, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	----
7192	{ 261, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	----
7193	{ 260, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	----
7194	{ 259, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	----
7195	{ 258, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	----
7196	{ 257, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	----
7197	{ 256, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	----
7198	{ 255, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	----
7199	{ 254, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	----
7200	{ 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7201	{ 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7202	{ 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7203	{ 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7204	{ 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7205	{ 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7206	{ 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7207	{ 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7208	{ 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7209	{ 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7210	{ 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7211	{ 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7212	{ 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7213	{ 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	----
7214	{ 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	----
7215	{ 238, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	----
7216	{ 237, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	----
7217	{ 236, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	----
7218	{ 235, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	----
7219	{ 234, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	----
7220	{ 233, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0\|(1ULL<	----
7221	{ 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7222	{ 231, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7223	{ 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7224	{ 229, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	----
7225	{ 228, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7226	{ 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7227	{ 226, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7228	{ 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7229	{ 224, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7230	{ 223, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	----
7231	{ 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7232	{ 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7233	{ 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7234	{ 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7235	{ 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7236	{ 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7237	{ 216, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7238	{ 215, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7239	{ 214, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7240	{ 213, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7241	{ 212, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7242	{ 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7243	{ 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7244	{ 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7245	{ 208, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7246	{ 207, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7247	{ 206, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7248	{ 205, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 122, 0\|(1ULL<	----
7249	{ 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	----
7250	{ 203, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0\|(1ULL<	----
7251	{ 202, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0\|(1ULL<	----
7252	{ 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7253	{ 200, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7254	{ 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7255	{ 198, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7256	{ 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7257	{ 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7258	{ 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7259	{ 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7260	{ 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7261	{ 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7262	{ 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7263	{ 190, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7264	{ 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7265	{ 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7266	{ 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7267	{ 186, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7268	{ 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7269	{ 184, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	----
7270	{ 183, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7271	{ 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7272	{ 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7273	{ 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7274	{ 179, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7275	{ 178, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7276	{ 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7277	{ 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7278	{ 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7279	{ 174, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7280	{ 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7281	{ 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7282	{ 171, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7283	{ 170, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7284	{ 169, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7285	{ 168, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7286	{ 167, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7287	{ 166, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7288	{ 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7289	{ 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7290	{ 163, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	----
7291	{ 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	----
7292	{ 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7293	{ 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7294	{ 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7295	{ 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7296	{ 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7297	{ 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7298	{ 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7299	{ 154, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7300	{ 153, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7301	{ 152, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7302	{ 151, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	----
7303	{ 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7304	{ 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7305	{ 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7306	{ 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7307	{ 146, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7308	{ 145, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7309	{ 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7310	{ 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7311	{ 142, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7312	{ 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7313	{ 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	----
7314	{ 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7315	{ 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	----
7316	{ 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7317	{ 136, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	----
7318	{ 135, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7319	{ 134, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	----
7320	{ 133, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7321	{ 132, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7322	{ 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	----
7323	{ 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	----
7324	{ 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7325	{ 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7326	{ 127, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	----
7327	{ 126, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	----
7328	{ 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7329	{ 124, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7330	{ 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	----
7331	{ 122, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7332	{ 121, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	----
7333	{ 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7334	{ 119, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	----
7335	{ 118, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	----
7336	{ 117, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7337	{ 116, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7338	{ 115, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7339	{ 114, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7340	{ 113, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7341	{ 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7342	{ 111, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7343	{ 110, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	----
7344	{ 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7345	{ 108, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	----
7346	{ 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7347	{ 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7348	{ 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7349	{ 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7350	{ 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7351	{ 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7352	{ 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7353	{ 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7354	{ 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7355	{ 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7356	{ 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7357	{ 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7358	{ 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7359	{ 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7360	{ 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7361	{ 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7362	{ 91, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	----
7363	{ 90, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	----
7364	{ 89, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0\|(1ULL<	----
7365	{ 88, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0\|(1ULL<	----
7366	{ 87, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7367	{ 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	----
7368	{ 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	----
7369	{ 84, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	----
7370	{ 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7371	{ 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7372	{ 81, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7373	{ 80, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	----
7374	{ 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7375	{ 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7376	{ 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7377	{ 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7378	{ 75, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	----
7379	{ 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7380	{ 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	----
7381	{ 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7382	{ 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7383	{ 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7384	{ 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7385	{ 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7386	{ 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7387	{ 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7388	{ 65, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0\|(1ULL<	----
7389	{ 64, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	----
7390	{ 63, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	----
7391	{ 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7392	{ 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7393	{ 60, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	----
7394	{ 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	----
7395	{ 58, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	----
7396	{ 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7397	{ 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7398	{ 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7399	{ 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	----
7400	{ 53, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	----
7401	{ 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7402	{ 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7403	{ 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7404	{ 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7405	{ 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7406	{ 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7407	{ 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	----
7408	{ 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	----
7409	{ 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	----
7410	{ 43, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	----
7411	{ 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7412	{ 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7413	{ 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0\|(1ULL<	----
7414	{ 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0\|(1ULL<	----
7415	{ 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7416	{ 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7417	{ 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7418	{ 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7419	{ 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7420	{ 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7421	{ 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0\|(1ULL<	----
7422	{ 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7423	{ 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0\|(1ULL<	----
7424	{ 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7425	{ 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0\|(1ULL<	----
7426	{ 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0\|(1ULL<	----
7427	{ 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7428	{ 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	----
7429	{ 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0\|(1ULL<	----
7430	{ 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0\|(1ULL<	----
7431	{ 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7432	{ 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7433	{ 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7434	{ 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	----
7435	{ 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	----
7436	{ 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7437	{ 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7438	{ 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7439	{ 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7440	{ 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7441	{ 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	----
7442	{ 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0\|(1ULL<	----
7443	{ 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7444	{ 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0\|(1ULL<	----
7445	{ 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	----
7446	{ 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7447	{ 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7448	{ 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7449	{ 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7450	{ 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7451	{ 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7452	{ 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	----
7453	{ 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	----
7454	}, {	----
7455	/* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7456	/* 1 */	----
7457	/* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7458	/* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7459	/* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7460	/* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7461	/* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7462	/* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7463	/* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },	----
7464	/* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7465	/* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7466	/* 29 */ { 0, 0\|(1<	----
7467	/* 30 */ { 0, 0\|(1<	----
7468	/* 33 */ { 0, 0\|(1<	----
7469	/* 35 */ { 0, 0\|(1<	----
7470	/* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	----
7471	/* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	----
7472	/* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7473	/* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7474	/* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7475	/* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7476	/* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	----
7477	/* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7478	/* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	----
7479	/* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7480	/* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7481	/* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7482	/* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7483	/* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7484	/* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7485	/* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7486	/* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7487	/* 92 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7488	/* 95 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7489	/* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7490	/* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7491	/* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	----
7492	/* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7493	/* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	----
7494	/* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	----
7495	/* 122 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7496	/* 126 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	----
7497	/* 128 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	----
7498	/* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	----
7499	/* 136 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7500	/* 138 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7501	/* 141 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7502	/* 144 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7503	/* 147 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7504	/* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7505	/* 158 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7506	/* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7507	/* 165 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7508	/* 171 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7509	/* 174 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7510	/* 175 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7511	/* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7512	/* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7513	/* 182 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7514	/* 186 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7515	/* 190 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7516	/* 194 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7517	/* 197 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7518	/* 200 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7519	/* 203 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7520	/* 206 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7521	/* 208 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7522	/* 211 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7523	/* 214 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7524	/* 216 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7525	/* 219 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7526	/* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7527	/* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7528	/* 228 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7529	/* 231 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7530	/* 234 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7531	/* 236 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7532	/* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7533	/* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7534	/* 242 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7535	/* 246 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7536	/* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7537	/* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7538	/* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7539	/* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7540	/* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7541	/* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7542	/* 274 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7543	/* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7544	/* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7545	/* 286 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7546	/* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7547	/* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7548	/* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7549	/* 302 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7550	/* 303 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7551	/* 306 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7552	/* 309 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7553	/* 312 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7554	/* 315 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7555	/* 318 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7556	/* 321 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7557	/* 324 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7558	/* 327 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7559	/* 331 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7560	/* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7561	/* 338 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7562	/* 341 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7563	/* 343 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7564	/* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	----
7565	/* 348 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7566	/* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7567	/* 352 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7568	/* 355 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7569	/* 357 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7570	/* 359 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7571	/* 361 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7572	/* 363 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7573	/* 366 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7574	/* 368 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7575	/* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7576	/* 373 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7577	/* 375 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7578	/* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7579	/* 379 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7580	/* 381 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7581	/* 383 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7582	/* 385 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7583	/* 388 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7584	/* 390 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7585	/* 392 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7586	/* 395 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7587	/* 398 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7588	/* 400 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7589	/* 402 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7590	/* 404 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7591	/* 407 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7592	/* 414 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7593	/* 421 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7594	/* 425 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7595	/* 427 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7596	/* 429 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7597	/* 432 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7598	/* 435 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7599	/* 439 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7600	/* 443 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7601	/* 447 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7602	/* 451 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7603	/* 455 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7604	/* 459 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7605	/* 463 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7606	/* 467 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7607	/* 471 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7608	/* 475 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7609	/* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7610	/* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7611	/* 485 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7612	/* 488 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7613	/* 491 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7614	/* 494 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7615	/* 496 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7616	/* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7617	/* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7618	/* 502 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7619	/* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7620	/* 511 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7621	/* 516 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7622	/* 519 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7623	/* 521 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7624	/* 523 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7625	/* 526 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7626	/* 529 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7627	/* 532 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7628	/* 535 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7629	/* 538 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7630	/* 541 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7631	/* 544 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7632	/* 547 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7633	/* 550 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7634	/* 553 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7635	/* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7636	/* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7637	/* 564 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7638	/* 566 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7639	/* 569 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7640	/* 572 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7641	/* 575 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7642	/* 578 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7643	/* 580 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7644	/* 582 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7645	/* 584 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7646	/* 586 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7647	/* 590 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7648	/* 594 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7649	/* 598 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7650	/* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7651	/* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7652	/* 608 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7653	/* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7654	/* 612 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7655	/* 614 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	----
7656	/* 616 */ { 0, 0\|(1<	----
7657	/* 619 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7658	/* 621 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7659	/* 623 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7660	/* 625 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7661	/* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7662	/* 629 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7663	/* 631 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7664	/* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7665	/* 635 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7666	/* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7667	/* 643 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7668	/* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7669	/* 650 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7670	/* 653 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7671	/* 656 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7672	/* 659 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7673	/* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7674	/* 665 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7675	/* 668 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7676	/* 670 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7677	/* 672 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7678	/* 674 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7679	/* 676 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7680	/* 679 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7681	/* 682 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7682	/* 685 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7683	/* 688 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7684	/* 691 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7685	/* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7686	/* 700 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7687	/* 703 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7688	/* 705 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7689	/* 708 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7690	/* 711 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7691	/* 714 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7692	/* 717 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7693	/* 720 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7694	/* 723 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7695	/* 727 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7696	/* 731 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7697	/* 735 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7698	/* 739 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7699	/* 742 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7700	/* 744 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7701	/* 747 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7702	/* 750 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7703	/* 752 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7704	/* 755 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7705	/* 758 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7706	/* 761 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7707	/* 764 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7708	/* 767 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7709	/* 770 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7710	/* 773 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7711	/* 775 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7712	/* 777 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7713	/* 779 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7714	/* 781 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7715	/* 783 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7716	/* 785 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7717	/* 790 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7718	/* 794 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7719	/* 798 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7720	/* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7721	/* 806 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7722	/* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7723	/* 814 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7724	/* 819 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7725	/* 824 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7726	/* 829 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7727	/* 830 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	----
7728	/* 833 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7729	/* 836 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7730	/* 839 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7731	/* 842 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },	----
7732	/* 845 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7733	/* 848 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7734	/* 850 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7735	/* 852 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7736	/* 854 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7737	/* 856 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7738	/* 860 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7739	/* 863 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7740	/* 866 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7741	/* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7742	/* 872 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7743	/* 875 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7744	/* 878 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7745	/* 881 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7746	/* 884 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7747	/* 887 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7748	/* 890 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0\|(1<	----
7749	/* 893 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7750	/* 897 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0\|(1<	----
7751	/* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7752	/* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0\|(1<	----
7753	/* 907 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	----
7754	/* 910 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7755	/* 913 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	----
7756	/* 916 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7757	/* 920 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7758	/* 924 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7759	/* 928 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7760	/* 932 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7761	/* 936 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7762	/* 938 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7763	/* 941 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7764	/* 943 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7765	/* 948 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7766	/* 952 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7767	/* 954 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7768	/* 958 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7769	/* 962 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7770	/* 966 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7771	/* 970 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7772	/* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7773	/* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7774	/* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7775	/* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7776	/* 990 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7777	/* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7778	/* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7779	/* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7780	/* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7781	/* 1010 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7782	/* 1013 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7783	/* 1016 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7784	/* 1019 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7785	/* 1021 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7786	/* 1024 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7787	/* 1026 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7788	/* 1028 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7789	/* 1030 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7790	/* 1032 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7791	/* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7792	/* 1036 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7793	/* 1039 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7794	/* 1043 */ { 0, 0\|(1<	----
7795	/* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7796	/* 1049 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7797	/* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7798	/* 1054 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7799	/* 1056 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	----
7800	/* 1059 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	----
7801	/* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	----
7802	/* 1067 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	----
7803	/* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	----
7804	/* 1075 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7805	/* 1079 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7806	/* 1082 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7807	/* 1085 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7808	/* 1088 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7809	/* 1092 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7810	/* 1096 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7811	/* 1100 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7812	/* 1104 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7813	/* 1107 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	----
7814	/* 1110 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7815	/* 1113 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7816	/* 1116 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7817	/* 1119 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	----
7818	/* 1122 */ { 0, 0\|(1<	----
7819	/* 1124 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	----
7820	}, {	----
7821	/* 0 */	----
7822	/* 0 */ Mips::SP, Mips::SP,	----
7823	/* 2 */ Mips::AT,	----
7824	/* 3 */ Mips::RA,	----
7825	/* 4 */ Mips::DSPPos,	----
7826	/* 5 */ Mips::V0, Mips::V1,	----
7827	/* 7 */ Mips::HI0, Mips::LO0,	----
7828	/* 9 */ Mips::T8,	----
7829	/* 10 */ Mips::DSPOutFlag20,	----
7830	/* 11 */ Mips::DSPCarry,	----
7831	/* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,	----
7832	/* 14 */ Mips::DSPCCond,	----
7833	/* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,	----
7834	/* 20 */ Mips::HI0_64, Mips::LO0_64,	----
7835	/* 22 */ Mips::DSPOutFlag16_19,	----
7836	/* 23 */ Mips::DSPPos, Mips::DSPEFI,	----
7837	/* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,	----
7838	/* 28 */ Mips::DSPOutFlag23,	----
7839	/* 29 */ Mips::FCC0,	----
7840	/* 30 */ Mips::DSPPos, Mips::DSPSCount,	----
7841	/* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,	----
7842	/* 36 */ Mips::AC0,	----
7843	/* 37 */ Mips::AC0_64,	----
7844	/* 38 */ Mips::HI0,	----
7845	/* 39 */ Mips::HI0_64,	----
7846	/* 40 */ Mips::LO0,	----
7847	/* 41 */ Mips::LO0_64,	----
7848	/* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,	----
7849	/* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,	----
7850	/* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	----
7851	/* 54 */ Mips::P0,	----
7852	/* 55 */ Mips::P1,	----
7853	/* 56 */ Mips::P2,	----
7854	/* 57 */ Mips::DSPOutFlag21,	----
7855	/* 58 */ Mips::DSPOutFlag22,	----
7856	/* 59 */ Mips::P0, Mips::P1, Mips::P2,	----
7857	/* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	----
7858	}	----
7859	};	----
7860		----
7861		----
7862	#ifdef __GNUC__	----
7863	#pragma GCC diagnostic push	----
7864	#pragma GCC diagnostic ignored "-Woverlength-strings"	----
7865	#endif	----
7866	extern const char MipsInstrNameData[] = {	----
7867	/* 0 */ "G_FLOG10\0"	----
7868	/* 9 */ "DMFC0\0"	----
7869	/* 15 */ "DMFGC0\0"	----
7870	/* 22 */ "MFHGC0\0"	----
7871	/* 29 */ "MTHGC0\0"	----
7872	/* 36 */ "DMTGC0\0"	----
7873	/* 43 */ "MFTC0\0"	----
7874	/* 49 */ "DMTC0\0"	----
7875	/* 55 */ "MTTC0\0"	----
7876	/* 61 */ "VMM0\0"	----
7877	/* 66 */ "MTM0\0"	----
7878	/* 71 */ "MTP0\0"	----
7879	/* 76 */ "BBIT0\0"	----
7880	/* 82 */ "LDC1\0"	----
7881	/* 87 */ "SDC1\0"	----
7882	/* 92 */ "CFC1\0"	----
7883	/* 97 */ "DMFC1\0"	----
7884	/* 103 */ "MFTHC1\0"	----
7885	/* 110 */ "MTTHC1\0"	----
7886	/* 117 */ "CTC1\0"	----
7887	/* 122 */ "CFTC1\0"	----
7888	/* 128 */ "MFTC1\0"	----
7889	/* 134 */ "DMTC1\0"	----
7890	/* 140 */ "CTTC1\0"	----
7891	/* 146 */ "MTTC1\0"	----
7892	/* 152 */ "LWC1\0"	----
7893	/* 157 */ "SWC1\0"	----
7894	/* 162 */ "LDXC1\0"	----
7895	/* 168 */ "SDXC1\0"	----
7896	/* 174 */ "LUXC1\0"	----
7897	/* 180 */ "SUXC1\0"	----
7898	/* 186 */ "LWXC1\0"	----
7899	/* 192 */ "SWXC1\0"	----
7900	/* 198 */ "MTM1\0"	----
7901	/* 203 */ "SDC1_M1\0"	----
7902	/* 211 */ "MTP1\0"	----
7903	/* 216 */ "BBIT1\0"	----
7904	/* 222 */ "BBIT032\0"	----
7905	/* 230 */ "BBIT132\0"	----
7906	/* 238 */ "DSRA32\0"	----
7907	/* 245 */ "MFHC1_D32\0"	----
7908	/* 255 */ "MTHC1_D32\0"	----
7909	/* 265 */ "FSUB_D32\0"	----
7910	/* 274 */ "NMSUB_D32\0"	----
7911	/* 284 */ "FADD_D32\0"	----
7912	/* 293 */ "NMADD_D32\0"	----
7913	/* 303 */ "C_NGE_D32\0"	----
7914	/* 313 */ "C_NGLE_D32\0"	----
7915	/* 324 */ "C_OLE_D32\0"	----
7916	/* 334 */ "C_ULE_D32\0"	----
7917	/* 344 */ "C_LE_D32\0"	----
7918	/* 353 */ "C_SF_D32\0"	----
7919	/* 362 */ "MOVF_D32\0"	----
7920	/* 371 */ "C_F_D32\0"	----
7921	/* 379 */ "PseudoSELECTFP_F_D32\0"	----
7922	/* 400 */ "FNEG_D32\0"	----
7923	/* 409 */ "MOVN_I_D32\0"	----
7924	/* 420 */ "MOVZ_I_D32\0"	----
7925	/* 431 */ "C_NGL_D32\0"	----
7926	/* 441 */ "FMUL_D32\0"	----
7927	/* 450 */ "LDC1_MM_D32\0"	----
7928	/* 462 */ "SDC1_MM_D32\0"	----
7929	/* 474 */ "C_UN_D32\0"	----
7930	/* 483 */ "RECIP_D32\0"	----
7931	/* 493 */ "FCMP_D32\0"	----
7932	/* 502 */ "C_SEQ_D32\0"	----
7933	/* 512 */ "C_UEQ_D32\0"	----
7934	/* 522 */ "C_EQ_D32\0"	----
7935	/* 531 */ "FABS_D32\0"	----
7936	/* 540 */ "CVT_S_D32\0"	----
7937	/* 550 */ "PseudoSELECT_D32\0"	----
7938	/* 567 */ "C_NGT_D32\0"	----
7939	/* 577 */ "C_OLT_D32\0"	----
7940	/* 587 */ "C_ULT_D32\0"	----
7941	/* 597 */ "C_LT_D32\0"	----
7942	/* 606 */ "FSQRT_D32\0"	----
7943	/* 616 */ "RSQRT_D32\0"	----
7944	/* 626 */ "MOVT_D32\0"	----
7945	/* 635 */ "PseudoSELECTFP_T_D32\0"	----
7946	/* 656 */ "FDIV_D32\0"	----
7947	/* 665 */ "FMOV_D32\0"	----
7948	/* 674 */ "PseudoTRUNC_W_D32\0"	----
7949	/* 692 */ "ROUND_W_D32\0"	----
7950	/* 704 */ "CEIL_W_D32\0"	----
7951	/* 715 */ "FLOOR_W_D32\0"	----
7952	/* 727 */ "CVT_W_D32\0"	----
7953	/* 737 */ "BPOSGE32\0"	----
7954	/* 746 */ "ATOMIC_LOAD_SUB_I32\0"	----
7955	/* 766 */ "ATOMIC_LOAD_ADD_I32\0"	----
7956	/* 786 */ "ATOMIC_LOAD_NAND_I32\0"	----
7957	/* 807 */ "ATOMIC_LOAD_AND_I32\0"	----
7958	/* 827 */ "ATOMIC_LOAD_UMIN_I32\0"	----
7959	/* 848 */ "ATOMIC_LOAD_MIN_I32\0"	----
7960	/* 868 */ "ATOMIC_SWAP_I32\0"	----
7961	/* 884 */ "ATOMIC_CMP_SWAP_I32\0"	----
7962	/* 904 */ "ATOMIC_LOAD_XOR_I32\0"	----
7963	/* 924 */ "ATOMIC_LOAD_OR_I32\0"	----
7964	/* 943 */ "ATOMIC_LOAD_UMAX_I32\0"	----
7965	/* 964 */ "ATOMIC_LOAD_MAX_I32\0"	----
7966	/* 984 */ "DSLL32\0"	----
7967	/* 991 */ "DSRL32\0"	----
7968	/* 998 */ "DROTR32\0"	----
7969	/* 1006 */ "CINS32\0"	----
7970	/* 1013 */ "EXTS32\0"	----
7971	/* 1020 */ "FCMP_S32\0"	----
7972	/* 1029 */ "DSLL64_32\0"	----
7973	/* 1039 */ "CINS64_32\0"	----
7974	/* 1049 */ "DEXT64_32\0"	----
7975	/* 1059 */ "LoadImmDoubleFGR_32\0"	----
7976	/* 1079 */ "LoadAddrReg32\0"	----
7977	/* 1093 */ "CINS_i32\0"	----
7978	/* 1102 */ "LoadImm32\0"	----
7979	/* 1112 */ "LoadAddrImm32\0"	----
7980	/* 1126 */ "MIPSeh_return32\0"	----
7981	/* 1142 */ "LwConstant32\0"	----
7982	/* 1155 */ "LDC2\0"	----
7983	/* 1160 */ "SDC2\0"	----
7984	/* 1165 */ "DMFC2\0"	----
7985	/* 1171 */ "DMTC2\0"	----
7986	/* 1177 */ "LWC2\0"	----
7987	/* 1182 */ "SWC2\0"	----
7988	/* 1187 */ "G_FLOG2\0"	----
7989	/* 1195 */ "MTM2\0"	----
7990	/* 1200 */ "MTP2\0"	----
7991	/* 1205 */ "G_FEXP2\0"	----
7992	/* 1213 */ "SHRA_QB_MMR2\0"	----
7993	/* 1226 */ "CMPGDU_LE_QB_MMR2\0"	----
7994	/* 1244 */ "SUBUH_QB_MMR2\0"	----
7995	/* 1258 */ "ADDUH_QB_MMR2\0"	----
7996	/* 1272 */ "CMPGDU_EQ_QB_MMR2\0"	----
7997	/* 1290 */ "SHRA_R_QB_MMR2\0"	----
7998	/* 1305 */ "SUBUH_R_QB_MMR2\0"	----
7999	/* 1321 */ "ADDUH_R_QB_MMR2\0"	----
8000	/* 1337 */ "SHRAV_R_QB_MMR2\0"	----
8001	/* 1353 */ "ABSQ_S_QB_MMR2\0"	----
8002	/* 1368 */ "CMPGDU_LT_QB_MMR2\0"	----
8003	/* 1386 */ "SHRAV_QB_MMR2\0"	----
8004	/* 1400 */ "PREPEND_MMR2\0"	----
8005	/* 1413 */ "APPEND_MMR2\0"	----
8006	/* 1425 */ "PRECR_QB_PH_MMR2\0"	----
8007	/* 1442 */ "SUBQH_PH_MMR2\0"	----
8008	/* 1456 */ "ADDQH_PH_MMR2\0"	----
8009	/* 1470 */ "SHRL_PH_MMR2\0"	----
8010	/* 1483 */ "MUL_PH_MMR2\0"	----
8011	/* 1495 */ "SUBQH_R_PH_MMR2\0"	----
8012	/* 1511 */ "ADDQH_R_PH_MMR2\0"	----
8013	/* 1527 */ "MUL_S_PH_MMR2\0"	----
8014	/* 1541 */ "MULQ_S_PH_MMR2\0"	----
8015	/* 1556 */ "SUBU_S_PH_MMR2\0"	----
8016	/* 1571 */ "ADDU_S_PH_MMR2\0"	----
8017	/* 1586 */ "SUBU_PH_MMR2\0"	----
8018	/* 1599 */ "ADDU_PH_MMR2\0"	----
8019	/* 1612 */ "SHRLV_PH_MMR2\0"	----
8020	/* 1626 */ "DPA_W_PH_MMR2\0"	----
8021	/* 1640 */ "MULSA_W_PH_MMR2\0"	----
8022	/* 1656 */ "DPAQX_SA_W_PH_MMR2\0"	----
8023	/* 1675 */ "DPSQX_SA_W_PH_MMR2\0"	----
8024	/* 1694 */ "DPS_W_PH_MMR2\0"	----
8025	/* 1708 */ "DPAQX_S_W_PH_MMR2\0"	----
8026	/* 1726 */ "DPSQX_S_W_PH_MMR2\0"	----
8027	/* 1744 */ "DPAX_W_PH_MMR2\0"	----
8028	/* 1759 */ "DPSX_W_PH_MMR2\0"	----
8029	/* 1774 */ "BALIGN_MMR2\0"	----
8030	/* 1786 */ "PRECR_SRA_PH_W_MMR2\0"	----
8031	/* 1806 */ "PRECR_SRA_R_PH_W_MMR2\0"	----
8032	/* 1828 */ "SUBQH_W_MMR2\0"	----
8033	/* 1841 */ "ADDQH_W_MMR2\0"	----
8034	/* 1854 */ "SUBQH_R_W_MMR2\0"	----
8035	/* 1869 */ "ADDQH_R_W_MMR2\0"	----
8036	/* 1884 */ "MULQ_RS_W_MMR2\0"	----
8037	/* 1899 */ "MULQ_S_W_MMR2\0"	----
8038	/* 1913 */ "LDC3\0"	----
8039	/* 1918 */ "SDC3\0"	----
8040	/* 1923 */ "LWC3\0"	----
8041	/* 1928 */ "SWC3\0"	----
8042	/* 1933 */ "BPOSGE32C_MMR3\0"	----
8043	/* 1948 */ "LDC164\0"	----
8044	/* 1955 */ "SDC164\0"	----
8045	/* 1962 */ "LDXC164\0"	----
8046	/* 1970 */ "SDXC164\0"	----
8047	/* 1978 */ "LUXC164\0"	----
8048	/* 1986 */ "SUXC164\0"	----
8049	/* 1994 */ "SEB64\0"	----
8050	/* 2000 */ "TAILCALLREGHB64\0"	----
8051	/* 2016 */ "JR_HB64\0"	----
8052	/* 2024 */ "JALR_HB64\0"	----
8053	/* 2034 */ "LB64\0"	----
8054	/* 2039 */ "SB64\0"	----
8055	/* 2044 */ "LOAD_ACC64\0"	----
8056	/* 2055 */ "STORE_ACC64\0"	----
8057	/* 2067 */ "BGEC64\0"	----
8058	/* 2074 */ "BNEC64\0"	----
8059	/* 2081 */ "JIC64\0"	----
8060	/* 2087 */ "JIALC64\0"	----
8061	/* 2095 */ "BEQC64\0"	----
8062	/* 2102 */ "SC64\0"	----
8063	/* 2107 */ "BLTC64\0"	----
8064	/* 2114 */ "BGEUC64\0"	----
8065	/* 2122 */ "BLTUC64\0"	----
8066	/* 2130 */ "BGEZC64\0"	----
8067	/* 2138 */ "BLEZC64\0"	----
8068	/* 2146 */ "BNEZC64\0"	----
8069	/* 2154 */ "BEQZC64\0"	----
8070	/* 2162 */ "BGTZC64\0"	----
8071	/* 2170 */ "BLTZC64\0"	----
8072	/* 2178 */ "AND64\0"	----
8073	/* 2184 */ "MFC1_D64\0"	----
8074	/* 2193 */ "MFHC1_D64\0"	----
8075	/* 2203 */ "MTHC1_D64\0"	----
8076	/* 2213 */ "MTC1_D64\0"	----
8077	/* 2222 */ "MOVN_I64_D64\0"	----
8078	/* 2235 */ "MOVZ_I64_D64\0"	----
8079	/* 2248 */ "FSUB_D64\0"	----
8080	/* 2257 */ "NMSUB_D64\0"	----
8081	/* 2267 */ "FADD_D64\0"	----
8082	/* 2276 */ "NMADD_D64\0"	----
8083	/* 2286 */ "C_NGE_D64\0"	----
8084	/* 2296 */ "C_NGLE_D64\0"	----
8085	/* 2307 */ "C_OLE_D64\0"	----
8086	/* 2317 */ "C_ULE_D64\0"	----
8087	/* 2327 */ "C_LE_D64\0"	----
8088	/* 2336 */ "C_SF_D64\0"	----
8089	/* 2345 */ "MOVF_D64\0"	----
8090	/* 2354 */ "C_F_D64\0"	----
8091	/* 2362 */ "PseudoSELECTFP_F_D64\0"	----
8092	/* 2383 */ "FNEG_D64\0"	----
8093	/* 2392 */ "MOVN_I_D64\0"	----
8094	/* 2403 */ "MOVZ_I_D64\0"	----
8095	/* 2414 */ "C_NGL_D64\0"	----
8096	/* 2424 */ "FMUL_D64\0"	----
8097	/* 2433 */ "TRUNC_L_D64\0"	----
8098	/* 2445 */ "ROUND_L_D64\0"	----
8099	/* 2457 */ "CEIL_L_D64\0"	----
8100	/* 2468 */ "FLOOR_L_D64\0"	----
8101	/* 2480 */ "CVT_L_D64\0"	----
8102	/* 2490 */ "LDC1_MM_D64\0"	----
8103	/* 2502 */ "SDC1_MM_D64\0"	----
8104	/* 2514 */ "C_UN_D64\0"	----
8105	/* 2523 */ "RECIP_D64\0"	----
8106	/* 2533 */ "FCMP_D64\0"	----
8107	/* 2542 */ "C_SEQ_D64\0"	----
8108	/* 2552 */ "C_UEQ_D64\0"	----
8109	/* 2562 */ "C_EQ_D64\0"	----
8110	/* 2571 */ "FABS_D64\0"	----
8111	/* 2580 */ "CVT_S_D64\0"	----
8112	/* 2590 */ "PseudoSELECT_D64\0"	----
8113	/* 2607 */ "C_NGT_D64\0"	----
8114	/* 2617 */ "C_OLT_D64\0"	----
8115	/* 2627 */ "C_ULT_D64\0"	----
8116	/* 2637 */ "C_LT_D64\0"	----
8117	/* 2646 */ "FSQRT_D64\0"	----
8118	/* 2656 */ "RSQRT_D64\0"	----
8119	/* 2666 */ "MOVT_D64\0"	----
8120	/* 2675 */ "PseudoSELECTFP_T_D64\0"	----
8121	/* 2696 */ "FDIV_D64\0"	----
8122	/* 2705 */ "FMOV_D64\0"	----
8123	/* 2714 */ "TRUNC_W_D64\0"	----
8124	/* 2726 */ "ROUND_W_D64\0"	----
8125	/* 2738 */ "CEIL_W_D64\0"	----
8126	/* 2749 */ "FLOOR_W_D64\0"	----
8127	/* 2761 */ "CVT_W_D64\0"	----
8128	/* 2771 */ "BNE64\0"	----
8129	/* 2777 */ "BuildPairF64\0"	----
8130	/* 2790 */ "ExtractElementF64\0"	----
8131	/* 2808 */ "TAILCALLREG64\0"	----
8132	/* 2822 */ "SEH64\0"	----
8133	/* 2828 */ "LH64\0"	----
8134	/* 2833 */ "SH64\0"	----
8135	/* 2838 */ "PseudoMFHI64\0"	----
8136	/* 2851 */ "PseudoMTLOHI64\0"	----
8137	/* 2866 */ "MTHI64\0"	----
8138	/* 2873 */ "MOVN_I64_I64\0"	----
8139	/* 2886 */ "MOVZ_I64_I64\0"	----
8140	/* 2899 */ "ATOMIC_LOAD_SUB_I64\0"	----
8141	/* 2919 */ "ATOMIC_LOAD_ADD_I64\0"	----
8142	/* 2939 */ "ATOMIC_LOAD_NAND_I64\0"	----
8143	/* 2960 */ "ATOMIC_LOAD_AND_I64\0"	----
8144	/* 2980 */ "MOVF_I64\0"	----
8145	/* 2989 */ "PseudoSELECTFP_F_I64\0"	----
8146	/* 3010 */ "MOVN_I_I64\0"	----
8147	/* 3021 */ "MOVZ_I_I64\0"	----
8148	/* 3032 */ "ATOMIC_LOAD_UMIN_I64\0"	----
8149	/* 3053 */ "ATOMIC_LOAD_MIN_I64\0"	----
8150	/* 3073 */ "ATOMIC_SWAP_I64\0"	----
8151	/* 3089 */ "ATOMIC_CMP_SWAP_I64\0"	----
8152	/* 3109 */ "ATOMIC_LOAD_XOR_I64\0"	----
8153	/* 3129 */ "ATOMIC_LOAD_OR_I64\0"	----
8154	/* 3148 */ "PseudoD_SELECT_I64\0"	----
8155	/* 3167 */ "PseudoSELECT_I64\0"	----
8156	/* 3184 */ "MOVT_I64\0"	----
8157	/* 3193 */ "PseudoSELECTFP_T_I64\0"	----
8158	/* 3214 */ "ATOMIC_LOAD_UMAX_I64\0"	----
8159	/* 3235 */ "ATOMIC_LOAD_MAX_I64\0"	----
8160	/* 3255 */ "LL64\0"	----
8161	/* 3260 */ "CVT_S_PL64\0"	----
8162	/* 3271 */ "LWL64\0"	----
8163	/* 3277 */ "SWL64\0"	----
8164	/* 3283 */ "PseudoMFLO64\0"	----
8165	/* 3296 */ "MTLO64\0"	----
8166	/* 3303 */ "BEQ64\0"	----
8167	/* 3309 */ "JR64\0"	----
8168	/* 3314 */ "JALR64\0"	----
8169	/* 3321 */ "NOR64\0"	----
8170	/* 3327 */ "XOR64\0"	----
8171	/* 3333 */ "RDHWR64\0"	----
8172	/* 3341 */ "LWR64\0"	----
8173	/* 3347 */ "SWR64\0"	----
8174	/* 3353 */ "FSUB_PS64\0"	----
8175	/* 3363 */ "FADD_PS64\0"	----
8176	/* 3373 */ "PLL_PS64\0"	----
8177	/* 3382 */ "FMUL_PS64\0"	----
8178	/* 3392 */ "PUL_PS64\0"	----
8179	/* 3401 */ "ADDR_PS64\0"	----
8180	/* 3411 */ "MULR_PS64\0"	----
8181	/* 3421 */ "PLU_PS64\0"	----
8182	/* 3430 */ "PUU_PS64\0"	----
8183	/* 3439 */ "CVT_PW_PS64\0"	----
8184	/* 3451 */ "CVT_PS_S64\0"	----
8185	/* 3462 */ "SLT64\0"	----
8186	/* 3468 */ "CVT_S_PU64\0"	----
8187	/* 3479 */ "LW64\0"	----
8188	/* 3484 */ "CVT_PS_PW64\0"	----
8189	/* 3496 */ "SW64\0"	----
8190	/* 3501 */ "BGEZ64\0"	----
8191	/* 3508 */ "BLEZ64\0"	----
8192	/* 3515 */ "SELNEZ64\0"	----
8193	/* 3524 */ "SELEQZ64\0"	----
8194	/* 3533 */ "BGTZ64\0"	----
8195	/* 3540 */ "BLTZ64\0"	----
8196	/* 3547 */ "BuildPairF64_64\0"	----
8197	/* 3563 */ "ExtractElementF64_64\0"	----
8198	/* 3584 */ "SLL64_64\0"	----
8199	/* 3593 */ "LONG_BRANCH_LUi2Op_64\0"	----
8200	/* 3615 */ "LoadAddrReg64\0"	----
8201	/* 3629 */ "PseudoIndirectHazardBranch64\0"	----
8202	/* 3658 */ "PseudoIndirectBranch64\0"	----
8203	/* 3681 */ "ANDi64\0"	----
8204	/* 3688 */ "XORi64\0"	----
8205	/* 3695 */ "SLTi64\0"	----
8206	/* 3702 */ "LUi64\0"	----
8207	/* 3708 */ "SGEImm64\0"	----
8208	/* 3717 */ "SLEImm64\0"	----
8209	/* 3726 */ "NORImm64\0"	----
8210	/* 3735 */ "SGTImm64\0"	----
8211	/* 3744 */ "SLTImm64\0"	----
8212	/* 3753 */ "SGEUImm64\0"	----
8213	/* 3763 */ "SLEUImm64\0"	----
8214	/* 3773 */ "SGTUImm64\0"	----
8215	/* 3783 */ "SLTUImm64\0"	----
8216	/* 3793 */ "LoadImm64\0"	----
8217	/* 3803 */ "LoadAddrImm64\0"	----
8218	/* 3817 */ "PseudoReturn64\0"	----
8219	/* 3832 */ "MIPSeh_return64\0"	----
8220	/* 3848 */ "LBu64\0"	----
8221	/* 3854 */ "LHu64\0"	----
8222	/* 3860 */ "SLTu64\0"	----
8223	/* 3867 */ "LEA_ADDiu64\0"	----
8224	/* 3879 */ "SLTiu64\0"	----
8225	/* 3887 */ "MoveR3216\0"	----
8226	/* 3897 */ "RetRA16\0"	----
8227	/* 3905 */ "JalB16\0"	----
8228	/* 3912 */ "LD_F16\0"	----
8229	/* 3919 */ "ST_F16\0"	----
8230	/* 3926 */ "ATOMIC_LOAD_SUB_I16\0"	----
8231	/* 3946 */ "ATOMIC_LOAD_ADD_I16\0"	----
8232	/* 3966 */ "ATOMIC_LOAD_NAND_I16\0"	----
8233	/* 3987 */ "ATOMIC_LOAD_AND_I16\0"	----
8234	/* 4007 */ "ATOMIC_LOAD_UMIN_I16\0"	----
8235	/* 4028 */ "ATOMIC_LOAD_MIN_I16\0"	----
8236	/* 4048 */ "ATOMIC_SWAP_I16\0"	----
8237	/* 4064 */ "ATOMIC_CMP_SWAP_I16\0"	----
8238	/* 4084 */ "ATOMIC_LOAD_XOR_I16\0"	----
8239	/* 4104 */ "ATOMIC_LOAD_OR_I16\0"	----
8240	/* 4123 */ "ATOMIC_LOAD_UMAX_I16\0"	----
8241	/* 4144 */ "ATOMIC_LOAD_MAX_I16\0"	----
8242	/* 4164 */ "Move32R16\0"	----
8243	/* 4174 */ "SraX16\0"	----
8244	/* 4181 */ "RestoreX16\0"	----
8245	/* 4192 */ "SaveX16\0"	----
8246	/* 4200 */ "BtnezT8CmpiX16\0"	----
8247	/* 4215 */ "BteqzT8CmpiX16\0"	----
8248	/* 4230 */ "BtnezT8SltiX16\0"	----
8249	/* 4245 */ "BteqzT8SltiX16\0"	----
8250	/* 4260 */ "SllX16\0"	----
8251	/* 4267 */ "SrlX16\0"	----
8252	/* 4274 */ "LbRxRyOffMemX16\0"	----
8253	/* 4290 */ "SbRxRyOffMemX16\0"	----
8254	/* 4306 */ "LhRxRyOffMemX16\0"	----
8255	/* 4322 */ "ShRxRyOffMemX16\0"	----
8256	/* 4338 */ "LbuRxRyOffMemX16\0"	----
8257	/* 4355 */ "LhuRxRyOffMemX16\0"	----
8258	/* 4372 */ "AddiuRxRyOffMemX16\0"	----
8259	/* 4391 */ "LwRxRyOffMemX16\0"	----
8260	/* 4407 */ "SwRxRyOffMemX16\0"	----
8261	/* 4423 */ "AddiuRxPcImmX16\0"	----
8262	/* 4439 */ "AddiuSpImmX16\0"	----
8263	/* 4453 */ "LwRxSpImmX16\0"	----
8264	/* 4466 */ "SwRxSpImmX16\0"	----
8265	/* 4479 */ "SltiCCRxImmX16\0"	----
8266	/* 4494 */ "SltiuCCRxImmX16\0"	----
8267	/* 4510 */ "LiRxImmX16\0"	----
8268	/* 4521 */ "CmpiRxImmX16\0"	----
8269	/* 4534 */ "SltiRxImmX16\0"	----
8270	/* 4547 */ "AddiuRxImmX16\0"	----
8271	/* 4561 */ "SltiuRxImmX16\0"	----
8272	/* 4575 */ "AddiuRxRxImmX16\0"	----
8273	/* 4591 */ "BnezRxImmX16\0"	----
8274	/* 4604 */ "BeqzRxImmX16\0"	----
8275	/* 4617 */ "BimmX16\0"	----
8276	/* 4625 */ "LiRxImmAlignX16\0"	----
8277	/* 4641 */ "LwRxPcTcpX16\0"	----
8278	/* 4654 */ "BtnezT8CmpX16\0"	----
8279	/* 4668 */ "BteqzT8CmpX16\0"	----
8280	/* 4682 */ "BtnezT8SltX16\0"	----
8281	/* 4696 */ "BteqzT8SltX16\0"	----
8282	/* 4710 */ "BtnezT8SltiuX16\0"	----
8283	/* 4726 */ "BteqzT8SltiuX16\0"	----
8284	/* 4742 */ "BtnezT8SltuX16\0"	----
8285	/* 4757 */ "BteqzT8SltuX16\0"	----
8286	/* 4772 */ "BtnezX16\0"	----
8287	/* 4781 */ "BteqzX16\0"	----
8288	/* 4790 */ "JrcRa16\0"	----
8289	/* 4798 */ "JrRa16\0"	----
8290	/* 4805 */ "Restore16\0"	----
8291	/* 4815 */ "GotPrologue16\0"	----
8292	/* 4829 */ "Save16\0"	----
8293	/* 4836 */ "JumpLinkReg16\0"	----
8294	/* 4850 */ "Mfhi16\0"	----
8295	/* 4857 */ "Break16\0"	----
8296	/* 4865 */ "Jal16\0"	----
8297	/* 4871 */ "AddiuSpImm16\0"	----
8298	/* 4884 */ "LiRxImm16\0"	----
8299	/* 4894 */ "CmpiRxImm16\0"	----
8300	/* 4906 */ "SltiRxImm16\0"	----
8301	/* 4918 */ "SltiuRxImm16\0"	----
8302	/* 4931 */ "AddiuRxRxImm16\0"	----
8303	/* 4946 */ "BnezRxImm16\0"	----
8304	/* 4958 */ "BeqzRxImm16\0"	----
8305	/* 4970 */ "Bimm16\0"	----
8306	/* 4977 */ "Mflo16\0"	----
8307	/* 4984 */ "LwRxPcTcp16\0"	----
8308	/* 4996 */ "SebRx16\0"	----
8309	/* 5004 */ "JrcRx16\0"	----
8310	/* 5012 */ "SehRx16\0"	----
8311	/* 5020 */ "SltCCRxRy16\0"	----
8312	/* 5032 */ "SltuCCRxRy16\0"	----
8313	/* 5045 */ "NegRxRy16\0"	----
8314	/* 5055 */ "CmpRxRy16\0"	----
8315	/* 5065 */ "SltRxRy16\0"	----
8316	/* 5075 */ "MultRxRy16\0"	----
8317	/* 5086 */ "NotRxRy16\0"	----
8318	/* 5096 */ "SltuRxRy16\0"	----
8319	/* 5107 */ "MultuRxRy16\0"	----
8320	/* 5119 */ "DivuRxRy16\0"	----
8321	/* 5130 */ "SravRxRy16\0"	----
8322	/* 5141 */ "DivRxRy16\0"	----
8323	/* 5151 */ "SllvRxRy16\0"	----
8324	/* 5162 */ "SrlvRxRy16\0"	----
8325	/* 5173 */ "AndRxRxRy16\0"	----
8326	/* 5185 */ "OrRxRxRy16\0"	----
8327	/* 5196 */ "XorRxRxRy16\0"	----
8328	/* 5208 */ "MultRxRyRz16\0"	----
8329	/* 5221 */ "SubuRxRyRz16\0"	----
8330	/* 5234 */ "AdduRxRyRz16\0"	----
8331	/* 5247 */ "SltuRxRyRz16\0"	----
8332	/* 5260 */ "MultuRxRyRz16\0"	----
8333	/* 5274 */ "Btnez16\0"	----
8334	/* 5282 */ "Bteqz16\0"	----
8335	/* 5290 */ "PseudoIndrectHazardBranch64R6\0"	----
8336	/* 5320 */ "PseudoIndirectBranch64R6\0"	----
8337	/* 5345 */ "MFC0_MMR6\0"	----
8338	/* 5355 */ "MFHC0_MMR6\0"	----
8339	/* 5366 */ "MTHC0_MMR6\0"	----
8340	/* 5377 */ "MTC0_MMR6\0"	----
8341	/* 5387 */ "MFC1_MMR6\0"	----
8342	/* 5397 */ "MTC1_MMR6\0"	----
8343	/* 5407 */ "LDC2_MMR6\0"	----
8344	/* 5417 */ "SDC2_MMR6\0"	----
8345	/* 5427 */ "MFC2_MMR6\0"	----
8346	/* 5437 */ "MFHC2_MMR6\0"	----
8347	/* 5448 */ "MTHC2_MMR6\0"	----
8348	/* 5459 */ "MTC2_MMR6\0"	----
8349	/* 5469 */ "LWC2_MMR6\0"	----
8350	/* 5479 */ "SWC2_MMR6\0"	----
8351	/* 5489 */ "LDC1_D64_MMR6\0"	----
8352	/* 5503 */ "SDC1_D64_MMR6\0"	----
8353	/* 5517 */ "SB16_MMR6\0"	----
8354	/* 5527 */ "BC16_MMR6\0"	----
8355	/* 5537 */ "JRC16_MMR6\0"	----
8356	/* 5548 */ "JALRC16_MMR6\0"	----
8357	/* 5561 */ "BNEZC16_MMR6\0"	----
8358	/* 5574 */ "BEQZC16_MMR6\0"	----
8359	/* 5587 */ "AND16_MMR6\0"	----
8360	/* 5598 */ "MOVE16_MMR6\0"	----
8361	/* 5610 */ "SH16_MMR6\0"	----
8362	/* 5620 */ "ANDI16_MMR6\0"	----
8363	/* 5632 */ "LI16_MMR6\0"	----
8364	/* 5642 */ "BREAK16_MMR6\0"	----
8365	/* 5655 */ "SLL16_MMR6\0"	----
8366	/* 5666 */ "SRL16_MMR6\0"	----
8367	/* 5677 */ "LWM16_MMR6\0"	----
8368	/* 5688 */ "SWM16_MMR6\0"	----
8369	/* 5699 */ "SDBBP16_MMR6\0"	----
8370	/* 5712 */ "XOR16_MMR6\0"	----
8371	/* 5723 */ "NOT16_MMR6\0"	----
8372	/* 5734 */ "SUBU16_MMR6\0"	----
8373	/* 5746 */ "ADDU16_MMR6\0"	----
8374	/* 5758 */ "SW16_MMR6\0"	----
8375	/* 5768 */ "LSA_MMR6\0"	----
8376	/* 5777 */ "EHB_MMR6\0"	----
8377	/* 5786 */ "JALRC_HB_MMR6\0"	----
8378	/* 5800 */ "LB_MMR6\0"	----
8379	/* 5808 */ "SB_MMR6\0"	----
8380	/* 5816 */ "SUB_MMR6\0"	----
8381	/* 5825 */ "BC_MMR6\0"	----
8382	/* 5833 */ "BGEC_MMR6\0"	----
8383	/* 5843 */ "BNEC_MMR6\0"	----
8384	/* 5853 */ "JIC_MMR6\0"	----
8385	/* 5862 */ "BALC_MMR6\0"	----
8386	/* 5872 */ "JIALC_MMR6\0"	----
8387	/* 5883 */ "BGEZALC_MMR6\0"	----
8388	/* 5896 */ "BLEZALC_MMR6\0"	----
8389	/* 5909 */ "BNEZALC_MMR6\0"	----
8390	/* 5922 */ "BEQZALC_MMR6\0"	----
8391	/* 5935 */ "BGTZALC_MMR6\0"	----
8392	/* 5948 */ "BLTZALC_MMR6\0"	----
8393	/* 5961 */ "ERETNC_MMR6\0"	----
8394	/* 5973 */ "SYNC_MMR6\0"	----
8395	/* 5983 */ "AUIPC_MMR6\0"	----
8396	/* 5994 */ "ALUIPC_MMR6\0"	----
8397	/* 6006 */ "ADDIUPC_MMR6\0"	----
8398	/* 6019 */ "LWPC_MMR6\0"	----
8399	/* 6029 */ "BEQC_MMR6\0"	----
8400	/* 6039 */ "JALRC_MMR6\0"	----
8401	/* 6050 */ "SC_MMR6\0"	----
8402	/* 6058 */ "BLTC_MMR6\0"	----
8403	/* 6068 */ "BGEUC_MMR6\0"	----
8404	/* 6079 */ "BLTUC_MMR6\0"	----
8405	/* 6090 */ "BNVC_MMR6\0"	----
8406	/* 6100 */ "BOVC_MMR6\0"	----
8407	/* 6110 */ "BGEZC_MMR6\0"	----
8408	/* 6121 */ "BLEZC_MMR6\0"	----
8409	/* 6132 */ "BC1NEZC_MMR6\0"	----
8410	/* 6145 */ "BC2NEZC_MMR6\0"	----
8411	/* 6158 */ "BNEZC_MMR6\0"	----
8412	/* 6169 */ "BC1EQZC_MMR6\0"	----
8413	/* 6182 */ "BC2EQZC_MMR6\0"	----
8414	/* 6195 */ "BEQZC_MMR6\0"	----
8415	/* 6206 */ "BGTZC_MMR6\0"	----
8416	/* 6217 */ "BLTZC_MMR6\0"	----
8417	/* 6228 */ "ADD_MMR6\0"	----
8418	/* 6237 */ "AND_MMR6\0"	----
8419	/* 6246 */ "MOD_MMR6\0"	----
8420	/* 6255 */ "MINA_D_MMR6\0"	----
8421	/* 6267 */ "MAXA_D_MMR6\0"	----
8422	/* 6279 */ "CMP_SLE_D_MMR6\0"	----
8423	/* 6294 */ "CMP_SULE_D_MMR6\0"	----
8424	/* 6310 */ "CMP_ULE_D_MMR6\0"	----
8425	/* 6325 */ "CMP_LE_D_MMR6\0"	----
8426	/* 6339 */ "CMP_SAF_D_MMR6\0"	----
8427	/* 6354 */ "CMP_AF_D_MMR6\0"	----
8428	/* 6368 */ "MSUBF_D_MMR6\0"	----
8429	/* 6381 */ "MADDF_D_MMR6\0"	----
8430	/* 6394 */ "SEL_D_MMR6\0"	----
8431	/* 6405 */ "TRUNC_L_D_MMR6\0"	----
8432	/* 6420 */ "ROUND_L_D_MMR6\0"	----
8433	/* 6435 */ "CEIL_L_D_MMR6\0"	----
8434	/* 6449 */ "FLOOR_L_D_MMR6\0"	----
8435	/* 6464 */ "CVT_L_D_MMR6\0"	----
8436	/* 6477 */ "MIN_D_MMR6\0"	----
8437	/* 6488 */ "CMP_SUN_D_MMR6\0"	----
8438	/* 6503 */ "CMP_UN_D_MMR6\0"	----
8439	/* 6517 */ "CMP_SEQ_D_MMR6\0"	----
8440	/* 6532 */ "CMP_SUEQ_D_MMR6\0"	----
8441	/* 6548 */ "CMP_UEQ_D_MMR6\0"	----
8442	/* 6563 */ "CMP_EQ_D_MMR6\0"	----
8443	/* 6577 */ "CLASS_D_MMR6\0"	----
8444	/* 6590 */ "CMP_SLT_D_MMR6\0"	----
8445	/* 6605 */ "CMP_SULT_D_MMR6\0"	----
8446	/* 6621 */ "CMP_ULT_D_MMR6\0"	----
8447	/* 6636 */ "CMP_LT_D_MMR6\0"	----
8448	/* 6650 */ "RINT_D_MMR6\0"	----
8449	/* 6662 */ "FMOV_D_MMR6\0"	----
8450	/* 6674 */ "TRUNC_W_D_MMR6\0"	----
8451	/* 6689 */ "ROUND_W_D_MMR6\0"	----
8452	/* 6704 */ "CEIL_W_D_MMR6\0"	----
8453	/* 6718 */ "FLOOR_W_D_MMR6\0"	----
8454	/* 6733 */ "MAX_D_MMR6\0"	----
8455	/* 6744 */ "SELNEZ_D_MMR6\0"	----
8456	/* 6758 */ "SELEQZ_D_MMR6\0"	----
8457	/* 6772 */ "CACHE_MMR6\0"	----
8458	/* 6783 */ "SIGRIE_MMR6\0"	----
8459	/* 6795 */ "PAUSE_MMR6\0"	----
8460	/* 6806 */ "PREF_MMR6\0"	----
8461	/* 6816 */ "TLBINVF_MMR6\0"	----
8462	/* 6829 */ "TAILCALLREG_MMR6\0"	----
8463	/* 6846 */ "WSBH_MMR6\0"	----
8464	/* 6856 */ "SH_MMR6\0"	----
8465	/* 6864 */ "MUH_MMR6\0"	----
8466	/* 6873 */ "SYNCI_MMR6\0"	----
8467	/* 6884 */ "ANDI_MMR6\0"	----
8468	/* 6894 */ "EI_MMR6\0"	----
8469	/* 6902 */ "XORI_MMR6\0"	----
8470	/* 6912 */ "AUI_MMR6\0"	----
8471	/* 6921 */ "LUI_MMR6\0"	----
8472	/* 6930 */ "GINVI_MMR6\0"	----
8473	/* 6941 */ "BREAK_MMR6\0"	----
8474	/* 6952 */ "JAL_MMR6\0"	----
8475	/* 6961 */ "TAILCALL_MMR6\0"	----
8476	/* 6975 */ "SLL_MMR6\0"	----
8477	/* 6984 */ "MUL_MMR6\0"	----
8478	/* 6993 */ "CVT_D_L_MMR6\0"	----
8479	/* 7006 */ "CVT_S_L_MMR6\0"	----
8480	/* 7019 */ "ALIGN_MMR6\0"	----
8481	/* 7030 */ "CLO_MMR6\0"	----
8482	/* 7039 */ "BITSWAP_MMR6\0"	----
8483	/* 7052 */ "SDBBP_MMR6\0"	----
8484	/* 7063 */ "MOVEP_MMR6\0"	----
8485	/* 7074 */ "SSNOP_MMR6\0"	----
8486	/* 7085 */ "JRCADDIUSP_MMR6\0"	----
8487	/* 7101 */ "SWSP_MMR6\0"	----
8488	/* 7111 */ "DVP_MMR6\0"	----
8489	/* 7120 */ "EVP_MMR6\0"	----
8490	/* 7129 */ "NOR_MMR6\0"	----
8491	/* 7138 */ "XOR_MMR6\0"	----
8492	/* 7147 */ "RDPGPR_MMR6\0"	----
8493	/* 7159 */ "WRPGPR_MMR6\0"	----
8494	/* 7171 */ "RDHWR_MMR6\0"	----
8495	/* 7182 */ "INS_MMR6\0"	----
8496	/* 7191 */ "MINA_S_MMR6\0"	----
8497	/* 7203 */ "MAXA_S_MMR6\0"	----
8498	/* 7215 */ "FSUB_S_MMR6\0"	----
8499	/* 7227 */ "FADD_S_MMR6\0"	----
8500	/* 7239 */ "CMP_SLE_S_MMR6\0"	----
8501	/* 7254 */ "CMP_SULE_S_MMR6\0"	----
8502	/* 7270 */ "CMP_ULE_S_MMR6\0"	----
8503	/* 7285 */ "CMP_LE_S_MMR6\0"	----
8504	/* 7299 */ "CMP_SAF_S_MMR6\0"	----
8505	/* 7314 */ "CMP_AF_S_MMR6\0"	----
8506	/* 7328 */ "MSUBF_S_MMR6\0"	----
8507	/* 7341 */ "MADDF_S_MMR6\0"	----
8508	/* 7354 */ "FNEG_S_MMR6\0"	----
8509	/* 7366 */ "SEL_S_MMR6\0"	----
8510	/* 7377 */ "FMUL_S_MMR6\0"	----
8511	/* 7389 */ "TRUNC_L_S_MMR6\0"	----
8512	/* 7404 */ "ROUND_L_S_MMR6\0"	----
8513	/* 7419 */ "CEIL_L_S_MMR6\0"	----
8514	/* 7433 */ "FLOOR_L_S_MMR6\0"	----
8515	/* 7448 */ "CVT_L_S_MMR6\0"	----
8516	/* 7461 */ "MIN_S_MMR6\0"	----
8517	/* 7472 */ "CMP_SUN_S_MMR6\0"	----
8518	/* 7487 */ "CMP_UN_S_MMR6\0"	----
8519	/* 7501 */ "CMP_SEQ_S_MMR6\0"	----
8520	/* 7516 */ "CMP_SUEQ_S_MMR6\0"	----
8521	/* 7532 */ "CMP_UEQ_S_MMR6\0"	----
8522	/* 7547 */ "CMP_EQ_S_MMR6\0"	----
8523	/* 7561 */ "CLASS_S_MMR6\0"	----
8524	/* 7574 */ "CMP_SLT_S_MMR6\0"	----
8525	/* 7589 */ "CMP_SULT_S_MMR6\0"	----
8526	/* 7605 */ "CMP_ULT_S_MMR6\0"	----
8527	/* 7620 */ "CMP_LT_S_MMR6\0"	----
8528	/* 7634 */ "RINT_S_MMR6\0"	----
8529	/* 7646 */ "FDIV_S_MMR6\0"	----
8530	/* 7658 */ "FMOV_S_MMR6\0"	----
8531	/* 7670 */ "TRUNC_W_S_MMR6\0"	----
8532	/* 7685 */ "ROUND_W_S_MMR6\0"	----
8533	/* 7700 */ "CEIL_W_S_MMR6\0"	----
8534	/* 7714 */ "FLOOR_W_S_MMR6\0"	----
8535	/* 7729 */ "CVT_W_S_MMR6\0"	----
8536	/* 7742 */ "MAX_S_MMR6\0"	----
8537	/* 7753 */ "SELNEZ_S_MMR6\0"	----
8538	/* 7767 */ "SELEQZ_S_MMR6\0"	----
8539	/* 7781 */ "DERET_MMR6\0"	----
8540	/* 7792 */ "WAIT_MMR6\0"	----
8541	/* 7802 */ "GINVT_MMR6\0"	----
8542	/* 7813 */ "EXT_MMR6\0"	----
8543	/* 7822 */ "LBU_MMR6\0"	----
8544	/* 7831 */ "SUBU_MMR6\0"	----
8545	/* 7841 */ "ADDU_MMR6\0"	----
8546	/* 7851 */ "MODU_MMR6\0"	----
8547	/* 7861 */ "MUHU_MMR6\0"	----
8548	/* 7871 */ "ADDIU_MMR6\0"	----
8549	/* 7882 */ "MULU_MMR6\0"	----
8550	/* 7892 */ "DIVU_MMR6\0"	----
8551	/* 7902 */ "DIV_MMR6\0"	----
8552	/* 7911 */ "TLBINV_MMR6\0"	----
8553	/* 7923 */ "LW_MMR6\0"	----
8554	/* 7931 */ "SW_MMR6\0"	----
8555	/* 7939 */ "CVT_S_W_MMR6\0"	----
8556	/* 7952 */ "SELNEZ_MMR6\0"	----
8557	/* 7964 */ "CLZ_MMR6\0"	----
8558	/* 7973 */ "SELEQZ_MMR6\0"	----
8559	/* 7985 */ "PseudoIndirectBranch_MMR6\0"	----
8560	/* 8011 */ "LDC2_R6\0"	----
8561	/* 8019 */ "SDC2_R6\0"	----
8562	/* 8027 */ "LWC2_R6\0"	----
8563	/* 8035 */ "SWC2_R6\0"	----
8564	/* 8043 */ "JR_HB64_R6\0"	----
8565	/* 8054 */ "SC64_R6\0"	----
8566	/* 8062 */ "LL64_R6\0"	----
8567	/* 8070 */ "DLSA_R6\0"	----
8568	/* 8078 */ "JR_HB_R6\0"	----
8569	/* 8087 */ "SC_R6\0"	----
8570	/* 8093 */ "SCD_R6\0"	----
8571	/* 8100 */ "LLD_R6\0"	----
8572	/* 8107 */ "CACHE_R6\0"	----
8573	/* 8116 */ "PREF_R6\0"	----
8574	/* 8124 */ "LL_R6\0"	----
8575	/* 8130 */ "DMUL_R6\0"	----
8576	/* 8138 */ "DCLO_R6\0"	----
8577	/* 8146 */ "SDBBP_R6\0"	----
8578	/* 8155 */ "DCLZ_R6\0"	----
8579	/* 8163 */ "PseudoIndrectHazardBranchR6\0"	----
8580	/* 8191 */ "PseudoIndirectBranchR6\0"	----
8581	/* 8214 */ "LOAD_ACC128\0"	----
8582	/* 8226 */ "STORE_ACC128\0"	----
8583	/* 8239 */ "ATOMIC_LOAD_SUB_I8\0"	----
8584	/* 8258 */ "ATOMIC_LOAD_ADD_I8\0"	----
8585	/* 8277 */ "ATOMIC_LOAD_NAND_I8\0"	----
8586	/* 8297 */ "ATOMIC_LOAD_AND_I8\0"	----
8587	/* 8316 */ "ATOMIC_LOAD_UMIN_I8\0"	----
8588	/* 8336 */ "ATOMIC_LOAD_MIN_I8\0"	----
8589	/* 8355 */ "ATOMIC_SWAP_I8\0"	----
8590	/* 8370 */ "ATOMIC_CMP_SWAP_I8\0"	----
8591	/* 8389 */ "ATOMIC_LOAD_XOR_I8\0"	----
8592	/* 8408 */ "ATOMIC_LOAD_OR_I8\0"	----
8593	/* 8426 */ "ATOMIC_LOAD_UMAX_I8\0"	----
8594	/* 8446 */ "ATOMIC_LOAD_MAX_I8\0"	----
8595	/* 8465 */ "SAA\0"	----
8596	/* 8469 */ "PRECEU_PH_QBLA\0"	----
8597	/* 8484 */ "PRECEQU_PH_QBLA\0"	----
8598	/* 8500 */ "G_FMA\0"	----
8599	/* 8506 */ "G_STRICT_FMA\0"	----
8600	/* 8519 */ "PRECEU_PH_QBRA\0"	----
8601	/* 8534 */ "PRECEQU_PH_QBRA\0"	----
8602	/* 8550 */ "DSRA\0"	----
8603	/* 8555 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"	----
8604	/* 8582 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"	----
8605	/* 8609 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"	----
8606	/* 8637 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"	----
8607	/* 8664 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"	----
8608	/* 8692 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"	----
8609	/* 8719 */ "ATOMIC_SWAP_I32_POSTRA\0"	----
8610	/* 8742 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"	----
8611	/* 8769 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"	----
8612	/* 8796 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"	----
8613	/* 8822 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"	----
8614	/* 8850 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"	----
8615	/* 8877 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"	----
8616	/* 8904 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"	----
8617	/* 8931 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"	----
8618	/* 8959 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"	----
8619	/* 8986 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"	----
8620	/* 9014 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"	----
8621	/* 9041 */ "ATOMIC_SWAP_I64_POSTRA\0"	----
8622	/* 9064 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"	----
8623	/* 9091 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"	----
8624	/* 9118 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"	----
8625	/* 9144 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"	----
8626	/* 9172 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"	----
8627	/* 9199 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"	----
8628	/* 9226 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"	----
8629	/* 9253 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"	----
8630	/* 9281 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"	----
8631	/* 9308 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"	----
8632	/* 9336 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"	----
8633	/* 9363 */ "ATOMIC_SWAP_I16_POSTRA\0"	----
8634	/* 9386 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"	----
8635	/* 9413 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"	----
8636	/* 9440 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"	----
8637	/* 9466 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"	----
8638	/* 9494 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"	----
8639	/* 9521 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"	----
8640	/* 9547 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"	----
8641	/* 9573 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"	----
8642	/* 9600 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"	----
8643	/* 9626 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"	----
8644	/* 9653 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"	----
8645	/* 9679 */ "ATOMIC_SWAP_I8_POSTRA\0"	----
8646	/* 9701 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"	----
8647	/* 9727 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"	----
8648	/* 9753 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"	----
8649	/* 9778 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"	----
8650	/* 9805 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"	----
8651	/* 9831 */ "RetRA\0"	----
8652	/* 9837 */ "DLSA\0"	----
8653	/* 9842 */ "CFCMSA\0"	----
8654	/* 9849 */ "CTCMSA\0"	----
8655	/* 9856 */ "CRC32B\0"	----
8656	/* 9863 */ "CRC32CB\0"	----
8657	/* 9871 */ "SEB\0"	----
8658	/* 9875 */ "EHB\0"	----
8659	/* 9879 */ "TAILCALLREGHB\0"	----
8660	/* 9893 */ "JR_HB\0"	----
8661	/* 9899 */ "JALR_HB\0"	----
8662	/* 9907 */ "LB\0"	----
8663	/* 9910 */ "SHRA_QB\0"	----
8664	/* 9918 */ "CMPGDU_LE_QB\0"	----
8665	/* 9931 */ "CMPGU_LE_QB\0"	----
8666	/* 9943 */ "PseudoCMPU_LE_QB\0"	----
8667	/* 9960 */ "SUBUH_QB\0"	----
8668	/* 9969 */ "ADDUH_QB\0"	----
8669	/* 9978 */ "PseudoPICK_QB\0"	----
8670	/* 9992 */ "SHLL_QB\0"	----
8671	/* 10000 */ "REPL_QB\0"	----
8672	/* 10008 */ "SHRL_QB\0"	----
8673	/* 10016 */ "CMPGDU_EQ_QB\0"	----
8674	/* 10029 */ "CMPGU_EQ_QB\0"	----
8675	/* 10041 */ "PseudoCMPU_EQ_QB\0"	----
8676	/* 10058 */ "SHRA_R_QB\0"	----
8677	/* 10068 */ "SUBUH_R_QB\0"	----
8678	/* 10079 */ "ADDUH_R_QB\0"	----
8679	/* 10090 */ "SHRAV_R_QB\0"	----
8680	/* 10101 */ "ABSQ_S_QB\0"	----
8681	/* 10111 */ "SUBU_S_QB\0"	----
8682	/* 10121 */ "ADDU_S_QB\0"	----
8683	/* 10131 */ "CMPGDU_LT_QB\0"	----
8684	/* 10144 */ "CMPGU_LT_QB\0"	----
8685	/* 10156 */ "PseudoCMPU_LT_QB\0"	----
8686	/* 10173 */ "SUBU_QB\0"	----
8687	/* 10181 */ "ADDU_QB\0"	----
8688	/* 10189 */ "SHRAV_QB\0"	----
8689	/* 10198 */ "SHLLV_QB\0"	----
8690	/* 10207 */ "REPLV_QB\0"	----
8691	/* 10216 */ "SHRLV_QB\0"	----
8692	/* 10225 */ "RADDU_W_QB\0"	----
8693	/* 10236 */ "SB\0"	----
8694	/* 10239 */ "MODSUB\0"	----
8695	/* 10246 */ "G_FSUB\0"	----
8696	/* 10253 */ "G_STRICT_FSUB\0"	----
8697	/* 10267 */ "G_ATOMICRMW_FSUB\0"	----
8698	/* 10284 */ "PseudoMSUB\0"	----
8699	/* 10295 */ "G_SUB\0"	----
8700	/* 10301 */ "G_ATOMICRMW_SUB\0"	----
8701	/* 10317 */ "SRA_B\0"	----
8702	/* 10323 */ "ADD_A_B\0"	----
8703	/* 10331 */ "MIN_A_B\0"	----
8704	/* 10339 */ "ADDS_A_B\0"	----
8705	/* 10348 */ "MAX_A_B\0"	----
8706	/* 10356 */ "NLOC_B\0"	----
8707	/* 10363 */ "NLZC_B\0"	----
8708	/* 10370 */ "SLD_B\0"	----
8709	/* 10376 */ "PCKOD_B\0"	----
8710	/* 10384 */ "ILVOD_B\0"	----
8711	/* 10392 */ "INSVE_B\0"	----
8712	/* 10400 */ "VSHF_B\0"	----
8713	/* 10407 */ "BNEG_B\0"	----
8714	/* 10414 */ "SRAI_B\0"	----
8715	/* 10421 */ "SLDI_B\0"	----
8716	/* 10428 */ "ANDI_B\0"	----
8717	/* 10435 */ "BNEGI_B\0"	----
8718	/* 10443 */ "BSELI_B\0"	----
8719	/* 10451 */ "SLLI_B\0"	----
8720	/* 10458 */ "SRLI_B\0"	----
8721	/* 10465 */ "BINSLI_B\0"	----
8722	/* 10474 */ "CEQI_B\0"	----
8723	/* 10481 */ "SRARI_B\0"	----
8724	/* 10489 */ "BCLRI_B\0"	----
8725	/* 10497 */ "SRLRI_B\0"	----
8726	/* 10505 */ "NORI_B\0"	----
8727	/* 10512 */ "XORI_B\0"	----
8728	/* 10519 */ "BINSRI_B\0"	----
8729	/* 10528 */ "SPLATI_B\0"	----
8730	/* 10537 */ "BSETI_B\0"	----
8731	/* 10545 */ "SUBVI_B\0"	----
8732	/* 10553 */ "ADDVI_B\0"	----
8733	/* 10561 */ "BMZI_B\0"	----
8734	/* 10568 */ "BMNZI_B\0"	----
8735	/* 10576 */ "FILL_B\0"	----
8736	/* 10583 */ "SLL_B\0"	----
8737	/* 10589 */ "SRL_B\0"	----
8738	/* 10595 */ "BINSL_B\0"	----
8739	/* 10603 */ "ILVL_B\0"	----
8740	/* 10610 */ "CEQ_B\0"	----
8741	/* 10616 */ "SRAR_B\0"	----
8742	/* 10623 */ "BCLR_B\0"	----
8743	/* 10630 */ "SRLR_B\0"	----
8744	/* 10637 */ "BINSR_B\0"	----
8745	/* 10645 */ "ILVR_B\0"	----
8746	/* 10652 */ "ASUB_S_B\0"	----
8747	/* 10661 */ "MOD_S_B\0"	----
8748	/* 10669 */ "CLE_S_B\0"	----
8749	/* 10677 */ "AVE_S_B\0"	----
8750	/* 10685 */ "CLEI_S_B\0"	----
8751	/* 10694 */ "MINI_S_B\0"	----
8752	/* 10703 */ "CLTI_S_B\0"	----
8753	/* 10712 */ "MAXI_S_B\0"	----
8754	/* 10721 */ "MIN_S_B\0"	----
8755	/* 10729 */ "AVER_S_B\0"	----
8756	/* 10738 */ "SUBS_S_B\0"	----
8757	/* 10747 */ "ADDS_S_B\0"	----
8758	/* 10756 */ "SAT_S_B\0"	----
8759	/* 10764 */ "CLT_S_B\0"	----
8760	/* 10772 */ "SUBSUU_S_B\0"	----
8761	/* 10783 */ "DIV_S_B\0"	----
8762	/* 10791 */ "MAX_S_B\0"	----
8763	/* 10799 */ "COPY_S_B\0"	----
8764	/* 10808 */ "SPLAT_B\0"	----
8765	/* 10816 */ "BSET_B\0"	----
8766	/* 10823 */ "PCNT_B\0"	----
8767	/* 10830 */ "INSERT_B\0"	----
8768	/* 10839 */ "ST_B\0"	----
8769	/* 10844 */ "ASUB_U_B\0"	----
8770	/* 10853 */ "MOD_U_B\0"	----
8771	/* 10861 */ "CLE_U_B\0"	----
8772	/* 10869 */ "AVE_U_B\0"	----
8773	/* 10877 */ "CLEI_U_B\0"	----
8774	/* 10886 */ "MINI_U_B\0"	----
8775	/* 10895 */ "CLTI_U_B\0"	----
8776	/* 10904 */ "MAXI_U_B\0"	----
8777	/* 10913 */ "MIN_U_B\0"	----
8778	/* 10921 */ "AVER_U_B\0"	----
8779	/* 10930 */ "SUBS_U_B\0"	----
8780	/* 10939 */ "ADDS_U_B\0"	----
8781	/* 10948 */ "SUBSUS_U_B\0"	----
8782	/* 10959 */ "SAT_U_B\0"	----
8783	/* 10967 */ "CLT_U_B\0"	----
8784	/* 10975 */ "DIV_U_B\0"	----
8785	/* 10983 */ "MAX_U_B\0"	----
8786	/* 10991 */ "COPY_U_B\0"	----
8787	/* 11000 */ "MSUBV_B\0"	----
8788	/* 11008 */ "MADDV_B\0"	----
8789	/* 11016 */ "PCKEV_B\0"	----
8790	/* 11024 */ "ILVEV_B\0"	----
8791	/* 11032 */ "MULV_B\0"	----
8792	/* 11039 */ "BZ_B\0"	----
8793	/* 11044 */ "BNZ_B\0"	----
8794	/* 11050 */ "BC\0"	----
8795	/* 11053 */ "BGEC\0"	----
8796	/* 11058 */ "BNEC\0"	----
8797	/* 11063 */ "JIC\0"	----
8798	/* 11067 */ "G_INTRINSIC\0"	----
8799	/* 11079 */ "BALC\0"	----
8800	/* 11084 */ "JIALC\0"	----
8801	/* 11090 */ "BGEZALC\0"	----
8802	/* 11098 */ "BLEZALC\0"	----
8803	/* 11106 */ "BNEZALC\0"	----
8804	/* 11114 */ "BEQZALC\0"	----
8805	/* 11122 */ "BGTZALC\0"	----
8806	/* 11130 */ "BLTZALC\0"	----
8807	/* 11138 */ "ERETNC\0"	----
8808	/* 11145 */ "G_FPTRUNC\0"	----
8809	/* 11155 */ "G_INTRINSIC_TRUNC\0"	----
8810	/* 11173 */ "G_TRUNC\0"	----
8811	/* 11181 */ "G_BUILD_VECTOR_TRUNC\0"	----
8812	/* 11202 */ "SYNC\0"	----
8813	/* 11207 */ "G_DYN_STACKALLOC\0"	----
8814	/* 11224 */ "LDPC\0"	----
8815	/* 11229 */ "AUIPC\0"	----
8816	/* 11235 */ "ALUIPC\0"	----
8817	/* 11242 */ "ADDIUPC\0"	----
8818	/* 11250 */ "LWUPC\0"	----
8819	/* 11256 */ "LWPC\0"	----
8820	/* 11261 */ "BEQC\0"	----
8821	/* 11266 */ "ADDSC\0"	----
8822	/* 11272 */ "BLTC\0"	----
8823	/* 11277 */ "BGEUC\0"	----
8824	/* 11283 */ "BLTUC\0"	----
8825	/* 11289 */ "BNVC\0"	----
8826	/* 11294 */ "BOVC\0"	----
8827	/* 11299 */ "ADDWC\0"	----
8828	/* 11305 */ "BGEZC\0"	----
8829	/* 11311 */ "BLEZC\0"	----
8830	/* 11317 */ "BNEZC\0"	----
8831	/* 11323 */ "BEQZC\0"	----
8832	/* 11329 */ "BGTZC\0"	----
8833	/* 11335 */ "BLTZC\0"	----
8834	/* 11341 */ "CRC32D\0"	----
8835	/* 11348 */ "SAAD\0"	----
8836	/* 11353 */ "G_FMAD\0"	----
8837	/* 11360 */ "G_INDEXED_SEXTLOAD\0"	----
8838	/* 11379 */ "G_SEXTLOAD\0"	----
8839	/* 11390 */ "G_INDEXED_ZEXTLOAD\0"	----
8840	/* 11409 */ "G_ZEXTLOAD\0"	----
8841	/* 11420 */ "G_INDEXED_LOAD\0"	----
8842	/* 11435 */ "G_LOAD\0"	----
8843	/* 11442 */ "CRC32CD\0"	----
8844	/* 11450 */ "SCD\0"	----
8845	/* 11454 */ "DADD\0"	----
8846	/* 11459 */ "G_VECREDUCE_FADD\0"	----
8847	/* 11476 */ "G_FADD\0"	----
8848	/* 11483 */ "G_VECREDUCE_SEQ_FADD\0"	----
8849	/* 11504 */ "G_STRICT_FADD\0"	----
8850	/* 11518 */ "G_ATOMICRMW_FADD\0"	----
8851	/* 11535 */ "PseudoMADD\0"	----
8852	/* 11546 */ "G_VECREDUCE_ADD\0"	----
8853	/* 11562 */ "G_ADD\0"	----
8854	/* 11568 */ "G_PTR_ADD\0"	----
8855	/* 11578 */ "G_ATOMICRMW_ADD\0"	----
8856	/* 11594 */ "DSHD\0"	----
8857	/* 11599 */ "YIELD\0"	----
8858	/* 11605 */ "LLD\0"	----
8859	/* 11609 */ "G_ATOMICRMW_NAND\0"	----
8860	/* 11626 */ "G_VECREDUCE_AND\0"	----
8861	/* 11642 */ "G_AND\0"	----
8862	/* 11648 */ "G_ATOMICRMW_AND\0"	----
8863	/* 11664 */ "PREPEND\0"	----
8864	/* 11672 */ "APPEND\0"	----
8865	/* 11679 */ "LIFETIME_END\0"	----
8866	/* 11692 */ "G_BRCOND\0"	----
8867	/* 11701 */ "G_LLROUND\0"	----
8868	/* 11711 */ "G_LROUND\0"	----
8869	/* 11720 */ "G_INTRINSIC_ROUND\0"	----
8870	/* 11738 */ "G_INTRINSIC_FPTRUNC_ROUND\0"	----
8871	/* 11764 */ "DMOD\0"	----
8872	/* 11769 */ "LOAD_STACK_GUARD\0"	----
8873	/* 11786 */ "SD\0"	----
8874	/* 11789 */ "FLOG2_D\0"	----
8875	/* 11797 */ "FEXP2_D\0"	----
8876	/* 11805 */ "MINA_D\0"	----
8877	/* 11812 */ "SRA_D\0"	----
8878	/* 11818 */ "MAXA_D\0"	----
8879	/* 11825 */ "ADD_A_D\0"	----
8880	/* 11833 */ "FMIN_A_D\0"	----
8881	/* 11842 */ "ADDS_A_D\0"	----
8882	/* 11851 */ "FMAX_A_D\0"	----
8883	/* 11860 */ "FSUB_D\0"	----
8884	/* 11867 */ "FMSUB_D\0"	----
8885	/* 11875 */ "NLOC_D\0"	----
8886	/* 11882 */ "NLZC_D\0"	----
8887	/* 11889 */ "FADD_D\0"	----
8888	/* 11896 */ "FMADD_D\0"	----
8889	/* 11904 */ "SLD_D\0"	----
8890	/* 11910 */ "PCKOD_D\0"	----
8891	/* 11918 */ "ILVOD_D\0"	----
8892	/* 11926 */ "FCLE_D\0"	----
8893	/* 11933 */ "FSLE_D\0"	----
8894	/* 11940 */ "CMP_SLE_D\0"	----
8895	/* 11950 */ "FCULE_D\0"	----
8896	/* 11958 */ "FSULE_D\0"	----
8897	/* 11966 */ "CMP_SULE_D\0"	----
8898	/* 11977 */ "CMP_ULE_D\0"	----
8899	/* 11987 */ "CMP_LE_D\0"	----
8900	/* 11996 */ "FCNE_D\0"	----
8901	/* 12003 */ "FSNE_D\0"	----
8902	/* 12010 */ "FCUNE_D\0"	----
8903	/* 12018 */ "FSUNE_D\0"	----
8904	/* 12026 */ "INSVE_D\0"	----
8905	/* 12034 */ "FCAF_D\0"	----
8906	/* 12041 */ "FSAF_D\0"	----
8907	/* 12048 */ "CMP_SAF_D\0"	----
8908	/* 12058 */ "MSUBF_D\0"	----
8909	/* 12066 */ "MADDF_D\0"	----
8910	/* 12074 */ "VSHF_D\0"	----
8911	/* 12081 */ "CMP_F_D\0"	----
8912	/* 12089 */ "BNEG_D\0"	----
8913	/* 12096 */ "SRAI_D\0"	----
8914	/* 12103 */ "SLDI_D\0"	----
8915	/* 12110 */ "BNEGI_D\0"	----
8916	/* 12118 */ "SLLI_D\0"	----
8917	/* 12125 */ "SRLI_D\0"	----
8918	/* 12132 */ "BINSLI_D\0"	----
8919	/* 12141 */ "CEQI_D\0"	----
8920	/* 12148 */ "SRARI_D\0"	----
8921	/* 12156 */ "BCLRI_D\0"	----
8922	/* 12164 */ "SRLRI_D\0"	----
8923	/* 12172 */ "BINSRI_D\0"	----
8924	/* 12181 */ "SPLATI_D\0"	----
8925	/* 12190 */ "BSETI_D\0"	----
8926	/* 12198 */ "SUBVI_D\0"	----
8927	/* 12206 */ "ADDVI_D\0"	----
8928	/* 12214 */ "SEL_D\0"	----
8929	/* 12220 */ "FILL_D\0"	----
8930	/* 12227 */ "SLL_D\0"	----
8931	/* 12233 */ "FEXUPL_D\0"	----
8932	/* 12242 */ "FFQL_D\0"	----
8933	/* 12249 */ "SRL_D\0"	----
8934	/* 12255 */ "BINSL_D\0"	----
8935	/* 12263 */ "FMUL_D\0"	----
8936	/* 12270 */ "ILVL_D\0"	----
8937	/* 12277 */ "FMIN_D\0"	----
8938	/* 12284 */ "FCUN_D\0"	----
8939	/* 12291 */ "FSUN_D\0"	----
8940	/* 12298 */ "CMP_SUN_D\0"	----
8941	/* 12308 */ "CMP_UN_D\0"	----
8942	/* 12317 */ "FRCP_D\0"	----
8943	/* 12324 */ "FCEQ_D\0"	----
8944	/* 12331 */ "FSEQ_D\0"	----
8945	/* 12338 */ "CMP_SEQ_D\0"	----
8946	/* 12348 */ "FCUEQ_D\0"	----
8947	/* 12356 */ "FSUEQ_D\0"	----
8948	/* 12364 */ "CMP_SUEQ_D\0"	----
8949	/* 12375 */ "CMP_UEQ_D\0"	----
8950	/* 12385 */ "CMP_EQ_D\0"	----
8951	/* 12394 */ "SRAR_D\0"	----
8952	/* 12401 */ "LDR_D\0"	----
8953	/* 12407 */ "BCLR_D\0"	----
8954	/* 12414 */ "SRLR_D\0"	----
8955	/* 12421 */ "FCOR_D\0"	----
8956	/* 12428 */ "FSOR_D\0"	----
8957	/* 12435 */ "FEXUPR_D\0"	----
8958	/* 12444 */ "FFQR_D\0"	----
8959	/* 12451 */ "BINSR_D\0"	----
8960	/* 12459 */ "STR_D\0"	----
8961	/* 12465 */ "ILVR_D\0"	----
8962	/* 12472 */ "FABS_D\0"	----
8963	/* 12479 */ "FCLASS_D\0"	----
8964	/* 12488 */ "ASUB_S_D\0"	----
8965	/* 12497 */ "HSUB_S_D\0"	----
8966	/* 12506 */ "DPSUB_S_D\0"	----
8967	/* 12516 */ "FTRUNC_S_D\0"	----
8968	/* 12527 */ "HADD_S_D\0"	----
8969	/* 12536 */ "DPADD_S_D\0"	----
8970	/* 12546 */ "MOD_S_D\0"	----
8971	/* 12554 */ "CLE_S_D\0"	----
8972	/* 12562 */ "AVE_S_D\0"	----
8973	/* 12570 */ "CLEI_S_D\0"	----
8974	/* 12579 */ "MINI_S_D\0"	----
8975	/* 12588 */ "CLTI_S_D\0"	----
8976	/* 12597 */ "MAXI_S_D\0"	----
8977	/* 12606 */ "MIN_S_D\0"	----
8978	/* 12614 */ "DOTP_S_D\0"	----
8979	/* 12623 */ "AVER_S_D\0"	----
8980	/* 12632 */ "SUBS_S_D\0"	----
8981	/* 12641 */ "ADDS_S_D\0"	----
8982	/* 12650 */ "SAT_S_D\0"	----
8983	/* 12658 */ "CLT_S_D\0"	----
8984	/* 12666 */ "FFINT_S_D\0"	----
8985	/* 12676 */ "FTINT_S_D\0"	----
8986	/* 12686 */ "SUBSUU_S_D\0"	----
8987	/* 12697 */ "DIV_S_D\0"	----
8988	/* 12705 */ "MAX_S_D\0"	----
8989	/* 12713 */ "COPY_S_D\0"	----
8990	/* 12722 */ "SPLAT_D\0"	----
8991	/* 12730 */ "BSET_D\0"	----
8992	/* 12737 */ "FCLT_D\0"	----
8993	/* 12744 */ "FSLT_D\0"	----
8994	/* 12751 */ "CMP_SLT_D\0"	----
8995	/* 12761 */ "FCULT_D\0"	----
8996	/* 12769 */ "FSULT_D\0"	----
8997	/* 12777 */ "CMP_SULT_D\0"	----
8998	/* 12788 */ "CMP_ULT_D\0"	----
8999	/* 12798 */ "CMP_LT_D\0"	----
9000	/* 12807 */ "PCNT_D\0"	----
9001	/* 12814 */ "FRINT_D\0"	----
9002	/* 12822 */ "INSERT_D\0"	----
9003	/* 12831 */ "FSQRT_D\0"	----
9004	/* 12839 */ "FRSQRT_D\0"	----
9005	/* 12848 */ "ST_D\0"	----
9006	/* 12853 */ "ASUB_U_D\0"	----
9007	/* 12862 */ "HSUB_U_D\0"	----
9008	/* 12871 */ "DPSUB_U_D\0"	----
9009	/* 12881 */ "FTRUNC_U_D\0"	----
9010	/* 12892 */ "HADD_U_D\0"	----
9011	/* 12901 */ "DPADD_U_D\0"	----
9012	/* 12911 */ "MOD_U_D\0"	----
9013	/* 12919 */ "CLE_U_D\0"	----
9014	/* 12927 */ "AVE_U_D\0"	----
9015	/* 12935 */ "CLEI_U_D\0"	----
9016	/* 12944 */ "MINI_U_D\0"	----
9017	/* 12953 */ "CLTI_U_D\0"	----
9018	/* 12962 */ "MAXI_U_D\0"	----
9019	/* 12971 */ "MIN_U_D\0"	----
9020	/* 12979 */ "DOTP_U_D\0"	----
9021	/* 12988 */ "AVER_U_D\0"	----
9022	/* 12997 */ "SUBS_U_D\0"	----
9023	/* 13006 */ "ADDS_U_D\0"	----
9024	/* 13015 */ "SUBSUS_U_D\0"	----
9025	/* 13026 */ "SAT_U_D\0"	----
9026	/* 13034 */ "CLT_U_D\0"	----
9027	/* 13042 */ "FFINT_U_D\0"	----
9028	/* 13052 */ "FTINT_U_D\0"	----
9029	/* 13062 */ "DIV_U_D\0"	----
9030	/* 13070 */ "MAX_U_D\0"	----
9031	/* 13078 */ "MSUBV_D\0"	----
9032	/* 13086 */ "MADDV_D\0"	----
9033	/* 13094 */ "PCKEV_D\0"	----
9034	/* 13102 */ "ILVEV_D\0"	----
9035	/* 13110 */ "FDIV_D\0"	----
9036	/* 13117 */ "MULV_D\0"	----
9037	/* 13124 */ "PseudoTRUNC_W_D\0"	----
9038	/* 13140 */ "FMAX_D\0"	----
9039	/* 13147 */ "BZ_D\0"	----
9040	/* 13152 */ "SELNEZ_D\0"	----
9041	/* 13161 */ "BNZ_D\0"	----
9042	/* 13167 */ "SELEQZ_D\0"	----
9043	/* 13176 */ "LBE\0"	----
9044	/* 13180 */ "PSEUDO_PROBE\0"	----
9045	/* 13193 */ "SBE\0"	----
9046	/* 13197 */ "G_SSUBE\0"	----
9047	/* 13205 */ "G_USUBE\0"	----
9048	/* 13213 */ "G_FENCE\0"	----
9049	/* 13221 */ "ARITH_FENCE\0"	----
9050	/* 13233 */ "REG_SEQUENCE\0"	----
9051	/* 13246 */ "SCE\0"	----
9052	/* 13250 */ "G_SADDE\0"	----
9053	/* 13258 */ "G_UADDE\0"	----
9054	/* 13266 */ "G_FMINNUM_IEEE\0"	----
9055	/* 13281 */ "G_FMAXNUM_IEEE\0"	----
9056	/* 13296 */ "CACHEE\0"	----
9057	/* 13303 */ "PREFE\0"	----
9058	/* 13309 */ "BGE\0"	----
9059	/* 13313 */ "SGE\0"	----
9060	/* 13317 */ "TGE\0"	----
9061	/* 13321 */ "CACHE\0"	----
9062	/* 13327 */ "LHE\0"	----
9063	/* 13331 */ "SHE\0"	----
9064	/* 13335 */ "SIGRIE\0"	----
9065	/* 13342 */ "G_JUMP_TABLE\0"	----
9066	/* 13355 */ "BUNDLE\0"	----
9067	/* 13362 */ "LLE\0"	----
9068	/* 13366 */ "SLE\0"	----
9069	/* 13370 */ "LWLE\0"	----
9070	/* 13375 */ "SWLE\0"	----
9071	/* 13380 */ "BNE\0"	----
9072	/* 13384 */ "G_MEMCPY_INLINE\0"	----
9073	/* 13400 */ "SNE\0"	----
9074	/* 13404 */ "TNE\0"	----
9075	/* 13408 */ "LOCAL_ESCAPE\0"	----
9076	/* 13421 */ "DVPE\0"	----
9077	/* 13426 */ "EVPE\0"	----
9078	/* 13431 */ "G_INDEXED_STORE\0"	----
9079	/* 13447 */ "G_STORE\0"	----
9080	/* 13455 */ "LWRE\0"	----
9081	/* 13460 */ "SWRE\0"	----
9082	/* 13465 */ "G_BITREVERSE\0"	----
9083	/* 13478 */ "PAUSE\0"	----
9084	/* 13484 */ "DBG_VALUE\0"	----
9085	/* 13494 */ "G_GLOBAL_VALUE\0"	----
9086	/* 13509 */ "G_MEMMOVE\0"	----
9087	/* 13519 */ "LWE\0"	----
9088	/* 13523 */ "SWE\0"	----
9089	/* 13527 */ "G_FREEZE\0"	----
9090	/* 13536 */ "G_FCANONICALIZE\0"	----
9091	/* 13552 */ "LBuE\0"	----
9092	/* 13557 */ "LHuE\0"	----
9093	/* 13562 */ "BC1F\0"	----
9094	/* 13567 */ "G_CTLZ_ZERO_UNDEF\0"	----
9095	/* 13585 */ "G_CTTZ_ZERO_UNDEF\0"	----
9096	/* 13603 */ "G_IMPLICIT_DEF\0"	----
9097	/* 13618 */ "PREF\0"	----
9098	/* 13623 */ "DBG_INSTR_REF\0"	----
9099	/* 13637 */ "TLBINVF\0"	----
9100	/* 13645 */ "TLBGINVF\0"	----
9101	/* 13654 */ "G_FNEG\0"	----
9102	/* 13661 */ "TAILCALLHB64R6REG\0"	----
9103	/* 13679 */ "TAILCALL64R6REG\0"	----
9104	/* 13695 */ "TAILCALLHBR6REG\0"	----
9105	/* 13711 */ "TAILCALLR6REG\0"	----
9106	/* 13725 */ "EXTRACT_SUBREG\0"	----
9107	/* 13740 */ "INSERT_SUBREG\0"	----
9108	/* 13754 */ "TAILCALLREG\0"	----
9109	/* 13766 */ "G_SEXT_INREG\0"	----
9110	/* 13779 */ "SUBREG_TO_REG\0"	----
9111	/* 13793 */ "G_ATOMIC_CMPXCHG\0"	----
9112	/* 13810 */ "G_ATOMICRMW_XCHG\0"	----
9113	/* 13827 */ "G_FLOG\0"	----
9114	/* 13834 */ "G_VAARG\0"	----
9115	/* 13842 */ "PREALLOCATED_ARG\0"	----
9116	/* 13859 */ "CRC32H\0"	----
9117	/* 13866 */ "DSBH\0"	----
9118	/* 13871 */ "WSBH\0"	----
9119	/* 13876 */ "CRC32CH\0"	----
9120	/* 13884 */ "SEH\0"	----
9121	/* 13888 */ "G_SMULH\0"	----
9122	/* 13896 */ "G_UMULH\0"	----
9123	/* 13904 */ "SHRA_PH\0"	----
9124	/* 13912 */ "PRECRQ_QB_PH\0"	----
9125	/* 13925 */ "PRECR_QB_PH\0"	----
9126	/* 13937 */ "PRECRQU_S_QB_PH\0"	----
9127	/* 13953 */ "PseudoCMP_LE_PH\0"	----
9128	/* 13969 */ "SUBQH_PH\0"	----
9129	/* 13978 */ "ADDQH_PH\0"	----
9130	/* 13987 */ "PseudoPICK_PH\0"	----
9131	/* 14001 */ "SHLL_PH\0"	----
9132	/* 14009 */ "REPL_PH\0"	----
9133	/* 14017 */ "SHRL_PH\0"	----
9134	/* 14025 */ "PACKRL_PH\0"	----
9135	/* 14035 */ "MUL_PH\0"	----
9136	/* 14042 */ "SUBQ_PH\0"	----
9137	/* 14050 */ "ADDQ_PH\0"	----
9138	/* 14058 */ "PseudoCMP_EQ_PH\0"	----
9139	/* 14074 */ "SHRA_R_PH\0"	----
9140	/* 14084 */ "SUBQH_R_PH\0"	----
9141	/* 14095 */ "ADDQH_R_PH\0"	----
9142	/* 14106 */ "SHRAV_R_PH\0"	----
9143	/* 14117 */ "MULQ_RS_PH\0"	----
9144	/* 14128 */ "SHLL_S_PH\0"	----
9145	/* 14138 */ "MUL_S_PH\0"	----
9146	/* 14147 */ "SUBQ_S_PH\0"	----
9147	/* 14157 */ "ADDQ_S_PH\0"	----
9148	/* 14167 */ "MULQ_S_PH\0"	----
9149	/* 14177 */ "ABSQ_S_PH\0"	----
9150	/* 14187 */ "SUBU_S_PH\0"	----
9151	/* 14197 */ "ADDU_S_PH\0"	----
9152	/* 14207 */ "SHLLV_S_PH\0"	----
9153	/* 14218 */ "PseudoCMP_LT_PH\0"	----
9154	/* 14234 */ "SUBU_PH\0"	----
9155	/* 14242 */ "ADDU_PH\0"	----
9156	/* 14250 */ "SHRAV_PH\0"	----
9157	/* 14259 */ "SHLLV_PH\0"	----
9158	/* 14268 */ "REPLV_PH\0"	----
9159	/* 14277 */ "SHRLV_PH\0"	----
9160	/* 14286 */ "DPA_W_PH\0"	----
9161	/* 14295 */ "MULSA_W_PH\0"	----
9162	/* 14306 */ "DPAQX_SA_W_PH\0"	----
9163	/* 14320 */ "DPSQX_SA_W_PH\0"	----
9164	/* 14334 */ "DPS_W_PH\0"	----
9165	/* 14343 */ "DPAQ_S_W_PH\0"	----
9166	/* 14355 */ "MULSAQ_S_W_PH\0"	----
9167	/* 14369 */ "DPSQ_S_W_PH\0"	----
9168	/* 14381 */ "DPAQX_S_W_PH\0"	----
9169	/* 14394 */ "DPSQX_S_W_PH\0"	----
9170	/* 14407 */ "DPAX_W_PH\0"	----
9171	/* 14417 */ "DPSX_W_PH\0"	----
9172	/* 14427 */ "SH\0"	----
9173	/* 14430 */ "DMUH\0"	----
9174	/* 14435 */ "SRA_H\0"	----
9175	/* 14441 */ "ADD_A_H\0"	----
9176	/* 14449 */ "MIN_A_H\0"	----
9177	/* 14457 */ "ADDS_A_H\0"	----
9178	/* 14466 */ "MAX_A_H\0"	----
9179	/* 14474 */ "NLOC_H\0"	----
9180	/* 14481 */ "NLZC_H\0"	----
9181	/* 14488 */ "SLD_H\0"	----
9182	/* 14494 */ "PCKOD_H\0"	----
9183	/* 14502 */ "ILVOD_H\0"	----
9184	/* 14510 */ "INSVE_H\0"	----
9185	/* 14518 */ "VSHF_H\0"	----
9186	/* 14525 */ "BNEG_H\0"	----
9187	/* 14532 */ "SRAI_H\0"	----
9188	/* 14539 */ "SLDI_H\0"	----
9189	/* 14546 */ "BNEGI_H\0"	----
9190	/* 14554 */ "SLLI_H\0"	----
9191	/* 14561 */ "SRLI_H\0"	----
9192	/* 14568 */ "BINSLI_H\0"	----
9193	/* 14577 */ "CEQI_H\0"	----
9194	/* 14584 */ "SRARI_H\0"	----
9195	/* 14592 */ "BCLRI_H\0"	----
9196	/* 14600 */ "SRLRI_H\0"	----
9197	/* 14608 */ "BINSRI_H\0"	----
9198	/* 14617 */ "SPLATI_H\0"	----
9199	/* 14626 */ "BSETI_H\0"	----
9200	/* 14634 */ "SUBVI_H\0"	----
9201	/* 14642 */ "ADDVI_H\0"	----
9202	/* 14650 */ "FILL_H\0"	----
9203	/* 14657 */ "SLL_H\0"	----
9204	/* 14663 */ "SRL_H\0"	----
9205	/* 14669 */ "BINSL_H\0"	----
9206	/* 14677 */ "ILVL_H\0"	----
9207	/* 14684 */ "FEXDO_H\0"	----
9208	/* 14692 */ "CEQ_H\0"	----
9209	/* 14698 */ "FTQ_H\0"	----
9210	/* 14704 */ "MSUB_Q_H\0"	----
9211	/* 14713 */ "MADD_Q_H\0"	----
9212	/* 14722 */ "MUL_Q_H\0"	----
9213	/* 14730 */ "MSUBR_Q_H\0"	----
9214	/* 14740 */ "MADDR_Q_H\0"	----
9215	/* 14750 */ "MULR_Q_H\0"	----
9216	/* 14759 */ "SRAR_H\0"	----
9217	/* 14766 */ "BCLR_H\0"	----
9218	/* 14773 */ "SRLR_H\0"	----
9219	/* 14780 */ "BINSR_H\0"	----
9220	/* 14788 */ "ILVR_H\0"	----
9221	/* 14795 */ "ASUB_S_H\0"	----
9222	/* 14804 */ "HSUB_S_H\0"	----
9223	/* 14813 */ "DPSUB_S_H\0"	----
9224	/* 14823 */ "HADD_S_H\0"	----
9225	/* 14832 */ "DPADD_S_H\0"	----
9226	/* 14842 */ "MOD_S_H\0"	----
9227	/* 14850 */ "CLE_S_H\0"	----
9228	/* 14858 */ "AVE_S_H\0"	----
9229	/* 14866 */ "CLEI_S_H\0"	----
9230	/* 14875 */ "MINI_S_H\0"	----
9231	/* 14884 */ "CLTI_S_H\0"	----
9232	/* 14893 */ "MAXI_S_H\0"	----
9233	/* 14902 */ "MIN_S_H\0"	----
9234	/* 14910 */ "DOTP_S_H\0"	----
9235	/* 14919 */ "AVER_S_H\0"	----
9236	/* 14928 */ "EXTR_S_H\0"	----
9237	/* 14937 */ "SUBS_S_H\0"	----
9238	/* 14946 */ "ADDS_S_H\0"	----
9239	/* 14955 */ "SAT_S_H\0"	----
9240	/* 14963 */ "CLT_S_H\0"	----
9241	/* 14971 */ "SUBSUU_S_H\0"	----
9242	/* 14982 */ "DIV_S_H\0"	----
9243	/* 14990 */ "EXTRV_S_H\0"	----
9244	/* 15000 */ "MAX_S_H\0"	----
9245	/* 15008 */ "COPY_S_H\0"	----
9246	/* 15017 */ "SPLAT_H\0"	----
9247	/* 15025 */ "BSET_H\0"	----
9248	/* 15032 */ "PCNT_H\0"	----
9249	/* 15039 */ "INSERT_H\0"	----
9250	/* 15048 */ "ST_H\0"	----
9251	/* 15053 */ "ASUB_U_H\0"	----
9252	/* 15062 */ "HSUB_U_H\0"	----
9253	/* 15071 */ "DPSUB_U_H\0"	----
9254	/* 15081 */ "HADD_U_H\0"	----
9255	/* 15090 */ "DPADD_U_H\0"	----
9256	/* 15100 */ "MOD_U_H\0"	----
9257	/* 15108 */ "CLE_U_H\0"	----
9258	/* 15116 */ "AVE_U_H\0"	----
9259	/* 15124 */ "CLEI_U_H\0"	----
9260	/* 15133 */ "MINI_U_H\0"	----
9261	/* 15142 */ "CLTI_U_H\0"	----
9262	/* 15151 */ "MAXI_U_H\0"	----
9263	/* 15160 */ "MIN_U_H\0"	----
9264	/* 15168 */ "DOTP_U_H\0"	----
9265	/* 15177 */ "AVER_U_H\0"	----
9266	/* 15186 */ "SUBS_U_H\0"	----
9267	/* 15195 */ "ADDS_U_H\0"	----
9268	/* 15204 */ "SUBSUS_U_H\0"	----
9269	/* 15215 */ "SAT_U_H\0"	----
9270	/* 15223 */ "CLT_U_H\0"	----
9271	/* 15231 */ "DIV_U_H\0"	----
9272	/* 15239 */ "MAX_U_H\0"	----
9273	/* 15247 */ "COPY_U_H\0"	----
9274	/* 15256 */ "MSUBV_H\0"	----
9275	/* 15264 */ "MADDV_H\0"	----
9276	/* 15272 */ "PCKEV_H\0"	----
9277	/* 15280 */ "ILVEV_H\0"	----
9278	/* 15288 */ "MULV_H\0"	----
9279	/* 15295 */ "BZ_H\0"	----
9280	/* 15300 */ "BNZ_H\0"	----
9281	/* 15306 */ "SYNCI\0"	----
9282	/* 15312 */ "DI\0"	----
9283	/* 15315 */ "TGEI\0"	----
9284	/* 15320 */ "TNEI\0"	----
9285	/* 15325 */ "DAHI\0"	----
9286	/* 15330 */ "PseudoMFHI\0"	----
9287	/* 15341 */ "PseudoMTLOHI\0"	----
9288	/* 15354 */ "DBG_PHI\0"	----
9289	/* 15362 */ "MFTHI\0"	----
9290	/* 15368 */ "MTHI\0"	----
9291	/* 15373 */ "MTTHI\0"	----
9292	/* 15379 */ "TEQI\0"	----
9293	/* 15384 */ "G_FPTOSI\0"	----
9294	/* 15393 */ "DATI\0"	----
9295	/* 15398 */ "TLTI\0"	----
9296	/* 15403 */ "DAUI\0"	----
9297	/* 15408 */ "G_FPTOUI\0"	----
9298	/* 15417 */ "GINVI\0"	----
9299	/* 15423 */ "TLBWI\0"	----
9300	/* 15429 */ "TLBGWI\0"	----
9301	/* 15436 */ "G_FPOWI\0"	----
9302	/* 15444 */ "MOVN_I64_I\0"	----
9303	/* 15455 */ "MOVZ_I64_I\0"	----
9304	/* 15466 */ "MOVF_I\0"	----
9305	/* 15473 */ "PseudoSELECTFP_F_I\0"	----
9306	/* 15492 */ "MOVN_I_I\0"	----
9307	/* 15501 */ "MOVZ_I_I\0"	----
9308	/* 15510 */ "PseudoD_SELECT_I\0"	----
9309	/* 15527 */ "PseudoSELECT_I\0"	----
9310	/* 15542 */ "MOVT_I\0"	----
9311	/* 15549 */ "PseudoSELECTFP_T_I\0"	----
9312	/* 15568 */ "J\0"	----
9313	/* 15570 */ "BREAK\0"	----
9314	/* 15576 */ "FORK\0"	----
9315	/* 15581 */ "G_PTRMASK\0"	----
9316	/* 15591 */ "BAL\0"	----
9317	/* 15595 */ "JAL\0"	----
9318	/* 15599 */ "BGEZAL\0"	----
9319	/* 15606 */ "BLTZAL\0"	----
9320	/* 15613 */ "MULEU_S_PH_QBL\0"	----
9321	/* 15628 */ "PRECEU_PH_QBL\0"	----
9322	/* 15642 */ "PRECEQU_PH_QBL\0"	----
9323	/* 15657 */ "DPAU_H_QBL\0"	----
9324	/* 15668 */ "DPSU_H_QBL\0"	----
9325	/* 15679 */ "LDL\0"	----
9326	/* 15683 */ "SDL\0"	----
9327	/* 15687 */ "GC_LABEL\0"	----
9328	/* 15696 */ "DBG_LABEL\0"	----
9329	/* 15706 */ "EH_LABEL\0"	----
9330	/* 15715 */ "ANNOTATION_LABEL\0"	----
9331	/* 15732 */ "BGEL\0"	----
9332	/* 15737 */ "BLEL\0"	----
9333	/* 15742 */ "BNEL\0"	----
9334	/* 15747 */ "ICALL_BRANCH_FUNNEL\0"	----
9335	/* 15767 */ "BC1FL\0"	----
9336	/* 15773 */ "MAQ_SA_W_PHL\0"	----
9337	/* 15786 */ "PRECEQ_W_PHL\0"	----
9338	/* 15799 */ "MAQ_S_W_PHL\0"	----
9339	/* 15811 */ "MULEQ_S_W_PHL\0"	----
9340	/* 15825 */ "G_FSHL\0"	----
9341	/* 15832 */ "G_SHL\0"	----
9342	/* 15838 */ "G_FCEIL\0"	----
9343	/* 15846 */ "TAILCALL\0"	----
9344	/* 15855 */ "HYPCALL\0"	----
9345	/* 15863 */ "SYSCALL\0"	----
9346	/* 15871 */ "PATCHABLE_TAIL_CALL\0"	----
9347	/* 15891 */ "PATCHABLE_TYPED_EVENT_CALL\0"	----
9348	/* 15918 */ "PATCHABLE_EVENT_CALL\0"	----
9349	/* 15939 */ "FENTRY_CALL\0"	----
9350	/* 15951 */ "BGEZALL\0"	----
9351	/* 15959 */ "BLTZALL\0"	----
9352	/* 15967 */ "KILL\0"	----
9353	/* 15972 */ "DSLL\0"	----
9354	/* 15977 */ "G_CONSTANT_POOL\0"	----
9355	/* 15993 */ "DROL\0"	----
9356	/* 15998 */ "BEQL\0"	----
9357	/* 16003 */ "DSRL\0"	----
9358	/* 16008 */ "BC1TL\0"	----
9359	/* 16014 */ "BGTL\0"	----
9360	/* 16019 */ "BLTL\0"	----
9361	/* 16024 */ "G_ROTL\0"	----
9362	/* 16031 */ "BGEUL\0"	----
9363	/* 16037 */ "BLEUL\0"	----
9364	/* 16043 */ "DMUL\0"	----
9365	/* 16048 */ "G_VECREDUCE_FMUL\0"	----
9366	/* 16065 */ "G_FMUL\0"	----
9367	/* 16072 */ "G_VECREDUCE_SEQ_FMUL\0"	----
9368	/* 16093 */ "G_STRICT_FMUL\0"	----
9369	/* 16107 */ "G_VECREDUCE_MUL\0"	----
9370	/* 16123 */ "G_MUL\0"	----
9371	/* 16129 */ "BGTUL\0"	----
9372	/* 16135 */ "BLTUL\0"	----
9373	/* 16141 */ "LWL\0"	----
9374	/* 16145 */ "SWL\0"	----
9375	/* 16149 */ "BGEZL\0"	----
9376	/* 16155 */ "BLEZL\0"	----
9377	/* 16161 */ "BGTZL\0"	----
9378	/* 16167 */ "BLTZL\0"	----
9379	/* 16173 */ "PseudoCVT_D64_L\0"	----
9380	/* 16189 */ "PseudoCVT_S_L\0"	----
9381	/* 16203 */ "G_FREM\0"	----
9382	/* 16210 */ "G_STRICT_FREM\0"	----
9383	/* 16224 */ "G_SREM\0"	----
9384	/* 16231 */ "G_UREM\0"	----
9385	/* 16238 */ "G_SDIVREM\0"	----
9386	/* 16248 */ "G_UDIVREM\0"	----
9387	/* 16258 */ "MFGC0_MM\0"	----
9388	/* 16267 */ "MFHGC0_MM\0"	----
9389	/* 16277 */ "MTHGC0_MM\0"	----
9390	/* 16287 */ "MTGC0_MM\0"	----
9391	/* 16296 */ "CFC1_MM\0"	----
9392	/* 16304 */ "MFC1_MM\0"	----
9393	/* 16312 */ "CTC1_MM\0"	----
9394	/* 16320 */ "MTC1_MM\0"	----
9395	/* 16328 */ "LWC1_MM\0"	----
9396	/* 16336 */ "SWC1_MM\0"	----
9397	/* 16344 */ "LUXC1_MM\0"	----
9398	/* 16353 */ "SUXC1_MM\0"	----
9399	/* 16362 */ "LWXC1_MM\0"	----
9400	/* 16371 */ "SWXC1_MM\0"	----
9401	/* 16380 */ "MFHC1_D32_MM\0"	----
9402	/* 16393 */ "MTHC1_D32_MM\0"	----
9403	/* 16406 */ "FSUB_D32_MM\0"	----
9404	/* 16418 */ "NMSUB_D32_MM\0"	----
9405	/* 16431 */ "FADD_D32_MM\0"	----
9406	/* 16443 */ "NMADD_D32_MM\0"	----
9407	/* 16456 */ "C_NGE_D32_MM\0"	----
9408	/* 16469 */ "C_NGLE_D32_MM\0"	----
9409	/* 16483 */ "C_OLE_D32_MM\0"	----
9410	/* 16496 */ "C_ULE_D32_MM\0"	----
9411	/* 16509 */ "C_LE_D32_MM\0"	----
9412	/* 16521 */ "C_SF_D32_MM\0"	----
9413	/* 16533 */ "MOVF_D32_MM\0"	----
9414	/* 16545 */ "C_F_D32_MM\0"	----
9415	/* 16556 */ "FNEG_D32_MM\0"	----
9416	/* 16568 */ "MOVN_I_D32_MM\0"	----
9417	/* 16582 */ "MOVZ_I_D32_MM\0"	----
9418	/* 16596 */ "C_NGL_D32_MM\0"	----
9419	/* 16609 */ "FMUL_D32_MM\0"	----
9420	/* 16621 */ "C_UN_D32_MM\0"	----
9421	/* 16633 */ "RECIP_D32_MM\0"	----
9422	/* 16646 */ "FCMP_D32_MM\0"	----
9423	/* 16658 */ "C_SEQ_D32_MM\0"	----
9424	/* 16671 */ "C_UEQ_D32_MM\0"	----
9425	/* 16684 */ "C_EQ_D32_MM\0"	----
9426	/* 16696 */ "FABS_D32_MM\0"	----
9427	/* 16708 */ "CVT_S_D32_MM\0"	----
9428	/* 16721 */ "C_NGT_D32_MM\0"	----
9429	/* 16734 */ "C_OLT_D32_MM\0"	----
9430	/* 16747 */ "C_ULT_D32_MM\0"	----
9431	/* 16760 */ "C_LT_D32_MM\0"	----
9432	/* 16772 */ "FSQRT_D32_MM\0"	----
9433	/* 16785 */ "RSQRT_D32_MM\0"	----
9434	/* 16798 */ "MOVT_D32_MM\0"	----
9435	/* 16810 */ "FDIV_D32_MM\0"	----
9436	/* 16822 */ "FMOV_D32_MM\0"	----
9437	/* 16834 */ "CVT_W_D32_MM\0"	----
9438	/* 16847 */ "BPOSGE32_MM\0"	----
9439	/* 16859 */ "LWM32_MM\0"	----
9440	/* 16868 */ "SWM32_MM\0"	----
9441	/* 16877 */ "FCMP_S32_MM\0"	----
9442	/* 16889 */ "CFC2_MM\0"	----
9443	/* 16897 */ "CTC2_MM\0"	----
9444	/* 16905 */ "ADDIUR2_MM\0"	----
9445	/* 16916 */ "MFHC1_D64_MM\0"	----
9446	/* 16929 */ "MTHC1_D64_MM\0"	----
9447	/* 16942 */ "MTC1_D64_MM\0"	----
9448	/* 16954 */ "FSUB_D64_MM\0"	----
9449	/* 16966 */ "FADD_D64_MM\0"	----
9450	/* 16978 */ "C_NGE_D64_MM\0"	----
9451	/* 16991 */ "C_NGLE_D64_MM\0"	----
9452	/* 17005 */ "C_OLE_D64_MM\0"	----
9453	/* 17018 */ "C_ULE_D64_MM\0"	----
9454	/* 17031 */ "C_LE_D64_MM\0"	----
9455	/* 17043 */ "C_SF_D64_MM\0"	----
9456	/* 17055 */ "C_F_D64_MM\0"	----
9457	/* 17066 */ "FNEG_D64_MM\0"	----
9458	/* 17078 */ "C_NGL_D64_MM\0"	----
9459	/* 17091 */ "FMUL_D64_MM\0"	----
9460	/* 17103 */ "CVT_L_D64_MM\0"	----
9461	/* 17116 */ "C_UN_D64_MM\0"	----
9462	/* 17128 */ "RECIP_D64_MM\0"	----
9463	/* 17141 */ "C_SEQ_D64_MM\0"	----
9464	/* 17154 */ "C_UEQ_D64_MM\0"	----
9465	/* 17167 */ "C_EQ_D64_MM\0"	----
9466	/* 17179 */ "FABS_D64_MM\0"	----
9467	/* 17191 */ "CVT_S_D64_MM\0"	----
9468	/* 17204 */ "C_NGT_D64_MM\0"	----
9469	/* 17217 */ "C_OLT_D64_MM\0"	----
9470	/* 17230 */ "C_ULT_D64_MM\0"	----
9471	/* 17243 */ "C_LT_D64_MM\0"	----
9472	/* 17255 */ "FSQRT_D64_MM\0"	----
9473	/* 17268 */ "RSQRT_D64_MM\0"	----
9474	/* 17281 */ "FDIV_D64_MM\0"	----
9475	/* 17293 */ "FMOV_D64_MM\0"	----
9476	/* 17305 */ "CVT_W_D64_MM\0"	----
9477	/* 17318 */ "ADDIUS5_MM\0"	----
9478	/* 17329 */ "SB16_MM\0"	----
9479	/* 17337 */ "JRC16_MM\0"	----
9480	/* 17346 */ "AND16_MM\0"	----
9481	/* 17355 */ "MOVE16_MM\0"	----
9482	/* 17365 */ "SH16_MM\0"	----
9483	/* 17373 */ "ANDI16_MM\0"	----
9484	/* 17383 */ "MFHI16_MM\0"	----
9485	/* 17393 */ "LI16_MM\0"	----
9486	/* 17401 */ "BREAK16_MM\0"	----
9487	/* 17412 */ "SLL16_MM\0"	----
9488	/* 17421 */ "SRL16_MM\0"	----
9489	/* 17430 */ "LWM16_MM\0"	----
9490	/* 17439 */ "SWM16_MM\0"	----
9491	/* 17448 */ "MFLO16_MM\0"	----
9492	/* 17458 */ "SDBBP16_MM\0"	----
9493	/* 17469 */ "JR16_MM\0"	----
9494	/* 17477 */ "JALR16_MM\0"	----
9495	/* 17487 */ "XOR16_MM\0"	----
9496	/* 17496 */ "JALRS16_MM\0"	----
9497	/* 17507 */ "NOT16_MM\0"	----
9498	/* 17516 */ "LBU16_MM\0"	----
9499	/* 17525 */ "SUBU16_MM\0"	----
9500	/* 17535 */ "ADDU16_MM\0"	----
9501	/* 17545 */ "LHU16_MM\0"	----
9502	/* 17554 */ "LW16_MM\0"	----
9503	/* 17562 */ "SW16_MM\0"	----
9504	/* 17570 */ "BNEZ16_MM\0"	----
9505	/* 17580 */ "BEQZ16_MM\0"	----
9506	/* 17590 */ "PRECEU_PH_QBLA_MM\0"	----
9507	/* 17608 */ "PRECEQU_PH_QBLA_MM\0"	----
9508	/* 17627 */ "PRECEU_PH_QBRA_MM\0"	----
9509	/* 17645 */ "PRECEQU_PH_QBRA_MM\0"	----
9510	/* 17664 */ "SRA_MM\0"	----
9511	/* 17671 */ "SEB_MM\0"	----
9512	/* 17678 */ "EHB_MM\0"	----
9513	/* 17685 */ "LB_MM\0"	----
9514	/* 17691 */ "CMPGU_LE_QB_MM\0"	----
9515	/* 17706 */ "CMPU_LE_QB_MM\0"	----
9516	/* 17720 */ "PICK_QB_MM\0"	----
9517	/* 17731 */ "SHLL_QB_MM\0"	----
9518	/* 17742 */ "REPL_QB_MM\0"	----
9519	/* 17753 */ "SHRL_QB_MM\0"	----
9520	/* 17764 */ "CMPGU_EQ_QB_MM\0"	----
9521	/* 17779 */ "CMPU_EQ_QB_MM\0"	----
9522	/* 17793 */ "SUBU_S_QB_MM\0"	----
9523	/* 17806 */ "ADDU_S_QB_MM\0"	----
9524	/* 17819 */ "CMPGU_LT_QB_MM\0"	----
9525	/* 17834 */ "CMPU_LT_QB_MM\0"	----
9526	/* 17848 */ "SUBU_QB_MM\0"	----
9527	/* 17859 */ "ADDU_QB_MM\0"	----
9528	/* 17870 */ "SHLLV_QB_MM\0"	----
9529	/* 17882 */ "REPLV_QB_MM\0"	----
9530	/* 17894 */ "SHRLV_QB_MM\0"	----
9531	/* 17906 */ "RADDU_W_QB_MM\0"	----
9532	/* 17920 */ "SB_MM\0"	----
9533	/* 17926 */ "MODSUB_MM\0"	----
9534	/* 17936 */ "PseudoMSUB_MM\0"	----
9535	/* 17950 */ "SYNC_MM\0"	----
9536	/* 17958 */ "ADDIUPC_MM\0"	----
9537	/* 17969 */ "ADDSC_MM\0"	----
9538	/* 17978 */ "ADDWC_MM\0"	----
9539	/* 17987 */ "BNEZC_MM\0"	----
9540	/* 17996 */ "BEQZC_MM\0"	----
9541	/* 18005 */ "PseudoMADD_MM\0"	----
9542	/* 18019 */ "AND_MM\0"	----
9543	/* 18026 */ "LBE_MM\0"	----
9544	/* 18033 */ "SBE_MM\0"	----
9545	/* 18040 */ "SCE_MM\0"	----
9546	/* 18047 */ "CACHEE_MM\0"	----
9547	/* 18057 */ "PREFE_MM\0"	----
9548	/* 18066 */ "TGE_MM\0"	----
9549	/* 18073 */ "CACHE_MM\0"	----
9550	/* 18082 */ "LHE_MM\0"	----
9551	/* 18089 */ "SHE_MM\0"	----
9552	/* 18096 */ "LLE_MM\0"	----
9553	/* 18103 */ "LWLE_MM\0"	----
9554	/* 18111 */ "SWLE_MM\0"	----
9555	/* 18119 */ "BNE_MM\0"	----
9556	/* 18126 */ "TNE_MM\0"	----
9557	/* 18133 */ "LWRE_MM\0"	----
9558	/* 18141 */ "SWRE_MM\0"	----
9559	/* 18149 */ "PAUSE_MM\0"	----
9560	/* 18158 */ "LWE_MM\0"	----
9561	/* 18165 */ "SWE_MM\0"	----
9562	/* 18172 */ "LBuE_MM\0"	----
9563	/* 18180 */ "LHuE_MM\0"	----
9564	/* 18188 */ "BC1F_MM\0"	----
9565	/* 18196 */ "PREF_MM\0"	----
9566	/* 18204 */ "TLBGINVF_MM\0"	----
9567	/* 18216 */ "TAILCALLREG_MM\0"	----
9568	/* 18231 */ "WSBH_MM\0"	----
9569	/* 18239 */ "SEH_MM\0"	----
9570	/* 18246 */ "LH_MM\0"	----
9571	/* 18252 */ "SHRA_PH_MM\0"	----
9572	/* 18263 */ "PRECRQ_QB_PH_MM\0"	----
9573	/* 18279 */ "PRECRQU_S_QB_PH_MM\0"	----
9574	/* 18298 */ "CMP_LE_PH_MM\0"	----
9575	/* 18311 */ "PICK_PH_MM\0"	----
9576	/* 18322 */ "SHLL_PH_MM\0"	----
9577	/* 18333 */ "REPL_PH_MM\0"	----
9578	/* 18344 */ "PACKRL_PH_MM\0"	----
9579	/* 18357 */ "SUBQ_PH_MM\0"	----
9580	/* 18368 */ "ADDQ_PH_MM\0"	----
9581	/* 18379 */ "CMP_EQ_PH_MM\0"	----
9582	/* 18392 */ "SHRA_R_PH_MM\0"	----
9583	/* 18405 */ "SHRAV_R_PH_MM\0"	----
9584	/* 18419 */ "MULQ_RS_PH_MM\0"	----
9585	/* 18433 */ "SHLL_S_PH_MM\0"	----
9586	/* 18446 */ "SUBQ_S_PH_MM\0"	----
9587	/* 18459 */ "ADDQ_S_PH_MM\0"	----
9588	/* 18472 */ "ABSQ_S_PH_MM\0"	----
9589	/* 18485 */ "SHLLV_S_PH_MM\0"	----
9590	/* 18499 */ "CMP_LT_PH_MM\0"	----
9591	/* 18512 */ "SHRAV_PH_MM\0"	----
9592	/* 18524 */ "SHLLV_PH_MM\0"	----
9593	/* 18536 */ "REPLV_PH_MM\0"	----
9594	/* 18548 */ "DPAQ_S_W_PH_MM\0"	----
9595	/* 18563 */ "MULSAQ_S_W_PH_MM\0"	----
9596	/* 18580 */ "DPSQ_S_W_PH_MM\0"	----
9597	/* 18595 */ "SH_MM\0"	----
9598	/* 18601 */ "EXTR_S_H_MM\0"	----
9599	/* 18613 */ "EXTRV_S_H_MM\0"	----
9600	/* 18626 */ "SYNCI_MM\0"	----
9601	/* 18635 */ "DI_MM\0"	----
9602	/* 18641 */ "TGEI_MM\0"	----
9603	/* 18649 */ "TNEI_MM\0"	----
9604	/* 18657 */ "PseudoMFHI_MM\0"	----
9605	/* 18671 */ "PseudoMTLOHI_MM\0"	----
9606	/* 18687 */ "MTHI_MM\0"	----
9607	/* 18695 */ "TEQI_MM\0"	----
9608	/* 18703 */ "TLTI_MM\0"	----
9609	/* 18711 */ "TLBWI_MM\0"	----
9610	/* 18720 */ "TLBGWI_MM\0"	----
9611	/* 18730 */ "MOVF_I_MM\0"	----
9612	/* 18740 */ "MOVN_I_MM\0"	----
9613	/* 18750 */ "MOVT_I_MM\0"	----
9614	/* 18760 */ "MOVZ_I_MM\0"	----
9615	/* 18770 */ "J_MM\0"	----
9616	/* 18775 */ "BREAK_MM\0"	----
9617	/* 18784 */ "JAL_MM\0"	----
9618	/* 18791 */ "BGEZAL_MM\0"	----
9619	/* 18801 */ "BLTZAL_MM\0"	----
9620	/* 18811 */ "MULEU_S_PH_QBL_MM\0"	----
9621	/* 18829 */ "PRECEU_PH_QBL_MM\0"	----
9622	/* 18846 */ "PRECEQU_PH_QBL_MM\0"	----
9623	/* 18864 */ "DPAU_H_QBL_MM\0"	----
9624	/* 18878 */ "DPSU_H_QBL_MM\0"	----
9625	/* 18892 */ "MAQ_SA_W_PHL_MM\0"	----
9626	/* 18908 */ "PRECEQ_W_PHL_MM\0"	----
9627	/* 18924 */ "MAQ_S_W_PHL_MM\0"	----
9628	/* 18939 */ "MULEQ_S_W_PHL_MM\0"	----
9629	/* 18956 */ "TAILCALL_MM\0"	----
9630	/* 18968 */ "HYPCALL_MM\0"	----
9631	/* 18979 */ "SYSCALL_MM\0"	----
9632	/* 18990 */ "SLL_MM\0"	----
9633	/* 18997 */ "SRL_MM\0"	----
9634	/* 19004 */ "MUL_MM\0"	----
9635	/* 19011 */ "LWL_MM\0"	----
9636	/* 19018 */ "SWL_MM\0"	----
9637	/* 19025 */ "LWM_MM\0"	----
9638	/* 19032 */ "SWM_MM\0"	----
9639	/* 19039 */ "CLO_MM\0"	----
9640	/* 19046 */ "PseudoMFLO_MM\0"	----
9641	/* 19060 */ "SHILO_MM\0"	----
9642	/* 19069 */ "MTLO_MM\0"	----
9643	/* 19077 */ "TRAP_MM\0"	----
9644	/* 19085 */ "SDBBP_MM\0"	----
9645	/* 19094 */ "TLBP_MM\0"	----
9646	/* 19102 */ "EXTPDP_MM\0"	----
9647	/* 19112 */ "MOVEP_MM\0"	----
9648	/* 19121 */ "TLBGP_MM\0"	----
9649	/* 19130 */ "LWGP_MM\0"	----
9650	/* 19138 */ "MTHLIP_MM\0"	----
9651	/* 19148 */ "SSNOP_MM\0"	----
9652	/* 19157 */ "ADDIUR1SP_MM\0"	----
9653	/* 19170 */ "RDDSP_MM\0"	----
9654	/* 19179 */ "WRDSP_MM\0"	----
9655	/* 19188 */ "LWDSP_MM\0"	----
9656	/* 19197 */ "SWDSP_MM\0"	----
9657	/* 19206 */ "MSUB_DSP_MM\0"	----
9658	/* 19218 */ "MADD_DSP_MM\0"	----
9659	/* 19230 */ "MFHI_DSP_MM\0"	----
9660	/* 19242 */ "MTHI_DSP_MM\0"	----
9661	/* 19254 */ "MFLO_DSP_MM\0"	----
9662	/* 19266 */ "MTLO_DSP_MM\0"	----
9663	/* 19278 */ "MULT_DSP_MM\0"	----
9664	/* 19290 */ "MSUBU_DSP_MM\0"	----
9665	/* 19303 */ "MADDU_DSP_MM\0"	----
9666	/* 19316 */ "MULTU_DSP_MM\0"	----
9667	/* 19329 */ "ADDIUSP_MM\0"	----
9668	/* 19340 */ "LWSP_MM\0"	----
9669	/* 19348 */ "SWSP_MM\0"	----
9670	/* 19356 */ "EXTP_MM\0"	----
9671	/* 19364 */ "LWP_MM\0"	----
9672	/* 19371 */ "SWP_MM\0"	----
9673	/* 19378 */ "BEQ_MM\0"	----
9674	/* 19385 */ "TEQ_MM\0"	----
9675	/* 19392 */ "TLBR_MM\0"	----
9676	/* 19400 */ "MULEU_S_PH_QBR_MM\0"	----
9677	/* 19418 */ "PRECEU_PH_QBR_MM\0"	----
9678	/* 19435 */ "PRECEQU_PH_QBR_MM\0"	----
9679	/* 19453 */ "DPAU_H_QBR_MM\0"	----
9680	/* 19467 */ "DPSU_H_QBR_MM\0"	----
9681	/* 19481 */ "BAL_BR_MM\0"	----
9682	/* 19491 */ "TLBGR_MM\0"	----
9683	/* 19500 */ "MAQ_SA_W_PHR_MM\0"	----
9684	/* 19516 */ "PRECEQ_W_PHR_MM\0"	----
9685	/* 19532 */ "MAQ_S_W_PHR_MM\0"	----
9686	/* 19547 */ "MULEQ_S_W_PHR_MM\0"	----
9687	/* 19564 */ "JR_MM\0"	----
9688	/* 19570 */ "JALR_MM\0"	----
9689	/* 19578 */ "NOR_MM\0"	----
9690	/* 19585 */ "XOR_MM\0"	----
9691	/* 19592 */ "ROTR_MM\0"	----
9692	/* 19600 */ "TLBWR_MM\0"	----
9693	/* 19609 */ "TLBGWR_MM\0"	----
9694	/* 19619 */ "RDHWR_MM\0"	----
9695	/* 19628 */ "LWR_MM\0"	----
9696	/* 19635 */ "SWR_MM\0"	----
9697	/* 19642 */ "JALS_MM\0"	----
9698	/* 19650 */ "BGEZALS_MM\0"	----
9699	/* 19661 */ "BLTZALS_MM\0"	----
9700	/* 19672 */ "INS_MM\0"	----
9701	/* 19679 */ "JALRS_MM\0"	----
9702	/* 19688 */ "LWXS_MM\0"	----
9703	/* 19696 */ "CVT_D32_S_MM\0"	----
9704	/* 19709 */ "CVT_D64_S_MM\0"	----
9705	/* 19722 */ "FSUB_S_MM\0"	----
9706	/* 19732 */ "NMSUB_S_MM\0"	----
9707	/* 19743 */ "FADD_S_MM\0"	----
9708	/* 19753 */ "NMADD_S_MM\0"	----
9709	/* 19764 */ "C_NGE_S_MM\0"	----
9710	/* 19775 */ "C_NGLE_S_MM\0"	----
9711	/* 19787 */ "C_OLE_S_MM\0"	----
9712	/* 19798 */ "C_ULE_S_MM\0"	----
9713	/* 19809 */ "C_LE_S_MM\0"	----
9714	/* 19819 */ "C_SF_S_MM\0"	----
9715	/* 19829 */ "MOVF_S_MM\0"	----
9716	/* 19839 */ "C_F_S_MM\0"	----
9717	/* 19848 */ "FNEG_S_MM\0"	----
9718	/* 19858 */ "MOVN_I_S_MM\0"	----
9719	/* 19870 */ "MOVZ_I_S_MM\0"	----
9720	/* 19882 */ "C_NGL_S_MM\0"	----
9721	/* 19893 */ "FMUL_S_MM\0"	----
9722	/* 19903 */ "CVT_L_S_MM\0"	----
9723	/* 19914 */ "C_UN_S_MM\0"	----
9724	/* 19924 */ "RECIP_S_MM\0"	----
9725	/* 19935 */ "C_SEQ_S_MM\0"	----
9726	/* 19946 */ "C_UEQ_S_MM\0"	----
9727	/* 19957 */ "C_EQ_S_MM\0"	----
9728	/* 19967 */ "FABS_S_MM\0"	----
9729	/* 19977 */ "C_NGT_S_MM\0"	----
9730	/* 19988 */ "C_OLT_S_MM\0"	----
9731	/* 19999 */ "C_ULT_S_MM\0"	----
9732	/* 20010 */ "C_LT_S_MM\0"	----
9733	/* 20020 */ "FSQRT_S_MM\0"	----
9734	/* 20031 */ "RSQRT_S_MM\0"	----
9735	/* 20042 */ "MOVT_S_MM\0"	----
9736	/* 20052 */ "FDIV_S_MM\0"	----
9737	/* 20062 */ "FMOV_S_MM\0"	----
9738	/* 20072 */ "TRUNC_W_S_MM\0"	----
9739	/* 20085 */ "ROUND_W_S_MM\0"	----
9740	/* 20098 */ "CEIL_W_S_MM\0"	----
9741	/* 20110 */ "FLOOR_W_S_MM\0"	----
9742	/* 20123 */ "CVT_W_S_MM\0"	----
9743	/* 20134 */ "BC1T_MM\0"	----
9744	/* 20142 */ "DERET_MM\0"	----
9745	/* 20151 */ "WAIT_MM\0"	----
9746	/* 20159 */ "SLT_MM\0"	----
9747	/* 20166 */ "TLT_MM\0"	----
9748	/* 20173 */ "PseudoMULT_MM\0"	----
9749	/* 20187 */ "EXT_MM\0"	----
9750	/* 20194 */ "PseudoMSUBU_MM\0"	----
9751	/* 20209 */ "PseudoMADDU_MM\0"	----
9752	/* 20224 */ "TGEU_MM\0"	----
9753	/* 20232 */ "TGEIU_MM\0"	----
9754	/* 20241 */ "TLTIU_MM\0"	----
9755	/* 20250 */ "TLTU_MM\0"	----
9756	/* 20258 */ "LWU_MM\0"	----
9757	/* 20265 */ "SRAV_MM\0"	----
9758	/* 20273 */ "BITREV_MM\0"	----
9759	/* 20283 */ "SDIV_MM\0"	----
9760	/* 20291 */ "UDIV_MM\0"	----
9761	/* 20299 */ "SLLV_MM\0"	----
9762	/* 20307 */ "SRLV_MM\0"	----
9763	/* 20315 */ "TLBGINV_MM\0"	----
9764	/* 20326 */ "SHILOV_MM\0"	----
9765	/* 20336 */ "EXTPDPV_MM\0"	----
9766	/* 20347 */ "EXTPV_MM\0"	----
9767	/* 20356 */ "ROTRV_MM\0"	----
9768	/* 20365 */ "INSV_MM\0"	----
9769	/* 20373 */ "LW_MM\0"	----
9770	/* 20379 */ "SW_MM\0"	----
9771	/* 20385 */ "CVT_D32_W_MM\0"	----
9772	/* 20398 */ "CVT_D64_W_MM\0"	----
9773	/* 20411 */ "TRUNC_W_MM\0"	----
9774	/* 20422 */ "ROUND_W_MM\0"	----
9775	/* 20433 */ "PRECRQ_PH_W_MM\0"	----
9776	/* 20448 */ "PRECRQ_RS_PH_W_MM\0"	----
9777	/* 20466 */ "CEIL_W_MM\0"	----
9778	/* 20476 */ "DPAQ_SA_L_W_MM\0"	----
9779	/* 20491 */ "DPSQ_SA_L_W_MM\0"	----
9780	/* 20506 */ "FLOOR_W_MM\0"	----
9781	/* 20517 */ "EXTR_W_MM\0"	----
9782	/* 20527 */ "SHRA_R_W_MM\0"	----
9783	/* 20539 */ "EXTR_R_W_MM\0"	----
9784	/* 20551 */ "SHRAV_R_W_MM\0"	----
9785	/* 20564 */ "EXTRV_R_W_MM\0"	----
9786	/* 20577 */ "EXTR_RS_W_MM\0"	----
9787	/* 20590 */ "EXTRV_RS_W_MM\0"	----
9788	/* 20604 */ "SHLL_S_W_MM\0"	----
9789	/* 20616 */ "SUBQ_S_W_MM\0"	----
9790	/* 20628 */ "ADDQ_S_W_MM\0"	----
9791	/* 20640 */ "ABSQ_S_W_MM\0"	----
9792	/* 20652 */ "CVT_S_W_MM\0"	----
9793	/* 20663 */ "SHLLV_S_W_MM\0"	----
9794	/* 20676 */ "EXTRV_W_MM\0"	----
9795	/* 20687 */ "PREFX_MM\0"	----
9796	/* 20696 */ "LHX_MM\0"	----
9797	/* 20703 */ "JALX_MM\0"	----
9798	/* 20711 */ "LBUX_MM\0"	----
9799	/* 20719 */ "LWX_MM\0"	----
9800	/* 20726 */ "BGEZ_MM\0"	----
9801	/* 20734 */ "BLEZ_MM\0"	----
9802	/* 20742 */ "CLZ_MM\0"	----
9803	/* 20749 */ "BGTZ_MM\0"	----
9804	/* 20757 */ "BLTZ_MM\0"	----
9805	/* 20765 */ "PseudoIndirectBranch_MM\0"	----
9806	/* 20789 */ "ADDi_MM\0"	----
9807	/* 20797 */ "ANDi_MM\0"	----
9808	/* 20805 */ "XORi_MM\0"	----
9809	/* 20813 */ "SLTi_MM\0"	----
9810	/* 20821 */ "LUi_MM\0"	----
9811	/* 20828 */ "LBu_MM\0"	----
9812	/* 20835 */ "SUBu_MM\0"	----
9813	/* 20843 */ "ADDu_MM\0"	----
9814	/* 20851 */ "LHu_MM\0"	----
9815	/* 20858 */ "SLTu_MM\0"	----
9816	/* 20866 */ "PseudoMULTu_MM\0"	----
9817	/* 20881 */ "LEA_ADDiu_MM\0"	----
9818	/* 20894 */ "SLTiu_MM\0"	----
9819	/* 20903 */ "INLINEASM\0"	----
9820	/* 20913 */ "DINSM\0"	----
9821	/* 20919 */ "DEXTM\0"	----
9822	/* 20925 */ "G_FMINIMUM\0"	----
9823	/* 20936 */ "G_FMAXIMUM\0"	----
9824	/* 20947 */ "G_FMINNUM\0"	----
9825	/* 20957 */ "G_FMAXNUM\0"	----
9826	/* 20967 */ "G_INTRINSIC_ROUNDEVEN\0"	----
9827	/* 20989 */ "BALIGN\0"	----
9828	/* 20996 */ "DALIGN\0"	----
9829	/* 21003 */ "G_ASSERT_ALIGN\0"	----
9830	/* 21018 */ "G_FCOPYSIGN\0"	----
9831	/* 21030 */ "G_VECREDUCE_FMIN\0"	----
9832	/* 21047 */ "G_ATOMICRMW_FMIN\0"	----
9833	/* 21064 */ "G_VECREDUCE_SMIN\0"	----
9834	/* 21081 */ "G_SMIN\0"	----
9835	/* 21088 */ "G_VECREDUCE_UMIN\0"	----
9836	/* 21105 */ "G_UMIN\0"	----
9837	/* 21112 */ "G_ATOMICRMW_UMIN\0"	----
9838	/* 21129 */ "G_ATOMICRMW_MIN\0"	----
9839	/* 21145 */ "G_FSIN\0"	----
9840	/* 21152 */ "DMFC2_OCTEON\0"	----
9841	/* 21165 */ "DMTC2_OCTEON\0"	----
9842	/* 21178 */ "CFI_INSTRUCTION\0"	----
9843	/* 21194 */ "ADJCALLSTACKDOWN\0"	----
9844	/* 21211 */ "G_SSUBO\0"	----
9845	/* 21219 */ "G_USUBO\0"	----
9846	/* 21227 */ "G_SADDO\0"	----
9847	/* 21235 */ "G_UADDO\0"	----
9848	/* 21243 */ "FEXP2_D_1_PSEUDO\0"	----
9849	/* 21260 */ "FEXP2_W_1_PSEUDO\0"	----
9850	/* 21277 */ "BPOSGE32_PSEUDO\0"	----
9851	/* 21293 */ "INSERT_B_VIDX64_PSEUDO\0"	----
9852	/* 21316 */ "INSERT_FD_VIDX64_PSEUDO\0"	----
9853	/* 21340 */ "INSERT_D_VIDX64_PSEUDO\0"	----
9854	/* 21363 */ "INSERT_H_VIDX64_PSEUDO\0"	----
9855	/* 21386 */ "INSERT_FW_VIDX64_PSEUDO\0"	----
9856	/* 21410 */ "INSERT_W_VIDX64_PSEUDO\0"	----
9857	/* 21433 */ "SNZ_B_PSEUDO\0"	----
9858	/* 21446 */ "SZ_B_PSEUDO\0"	----
9859	/* 21458 */ "BSEL_FD_PSEUDO\0"	----
9860	/* 21473 */ "FILL_FD_PSEUDO\0"	----
9861	/* 21488 */ "INSERT_FD_PSEUDO\0"	----
9862	/* 21505 */ "COPY_FD_PSEUDO\0"	----
9863	/* 21520 */ "MSA_FP_EXTEND_D_PSEUDO\0"	----
9864	/* 21543 */ "MSA_FP_ROUND_D_PSEUDO\0"	----
9865	/* 21565 */ "BSEL_D_PSEUDO\0"	----
9866	/* 21579 */ "AND_V_D_PSEUDO\0"	----
9867	/* 21594 */ "NOR_V_D_PSEUDO\0"	----
9868	/* 21609 */ "XOR_V_D_PSEUDO\0"	----
9869	/* 21624 */ "SNZ_D_PSEUDO\0"	----
9870	/* 21637 */ "SZ_D_PSEUDO\0"	----
9871	/* 21649 */ "BSEL_H_PSEUDO\0"	----
9872	/* 21663 */ "AND_V_H_PSEUDO\0"	----
9873	/* 21678 */ "NOR_V_H_PSEUDO\0"	----
9874	/* 21693 */ "XOR_V_H_PSEUDO\0"	----
9875	/* 21708 */ "SNZ_H_PSEUDO\0"	----
9876	/* 21721 */ "SZ_H_PSEUDO\0"	----
9877	/* 21733 */ "SNZ_V_PSEUDO\0"	----
9878	/* 21746 */ "SZ_V_PSEUDO\0"	----
9879	/* 21758 */ "BSEL_FW_PSEUDO\0"	----
9880	/* 21773 */ "FILL_FW_PSEUDO\0"	----
9881	/* 21788 */ "INSERT_FW_PSEUDO\0"	----
9882	/* 21805 */ "COPY_FW_PSEUDO\0"	----
9883	/* 21820 */ "MSA_FP_EXTEND_W_PSEUDO\0"	----
9884	/* 21843 */ "MSA_FP_ROUND_W_PSEUDO\0"	----
9885	/* 21865 */ "BSEL_W_PSEUDO\0"	----
9886	/* 21879 */ "AND_V_W_PSEUDO\0"	----
9887	/* 21894 */ "NOR_V_W_PSEUDO\0"	----
9888	/* 21909 */ "XOR_V_W_PSEUDO\0"	----
9889	/* 21924 */ "SNZ_W_PSEUDO\0"	----
9890	/* 21937 */ "SZ_W_PSEUDO\0"	----
9891	/* 21949 */ "INSERT_B_VIDX_PSEUDO\0"	----
9892	/* 21970 */ "INSERT_FD_VIDX_PSEUDO\0"	----
9893	/* 21992 */ "INSERT_D_VIDX_PSEUDO\0"	----
9894	/* 22013 */ "INSERT_H_VIDX_PSEUDO\0"	----
9895	/* 22034 */ "INSERT_FW_VIDX_PSEUDO\0"	----
9896	/* 22056 */ "INSERT_W_VIDX_PSEUDO\0"	----
9897	/* 22077 */ "DCLO\0"	----
9898	/* 22082 */ "PseudoMFLO\0"	----
9899	/* 22093 */ "SHILO\0"	----
9900	/* 22099 */ "MFTLO\0"	----
9901	/* 22105 */ "MTLO\0"	----
9902	/* 22110 */ "MTTLO\0"	----
9903	/* 22116 */ "G_SMULO\0"	----
9904	/* 22124 */ "G_UMULO\0"	----
9905	/* 22132 */ "G_BZERO\0"	----
9906	/* 22140 */ "STACKMAP\0"	----
9907	/* 22149 */ "TRAP\0"	----
9908	/* 22154 */ "G_ATOMICRMW_UDEC_WRAP\0"	----
9909	/* 22176 */ "G_ATOMICRMW_UINC_WRAP\0"	----
9910	/* 22198 */ "G_BSWAP\0"	----
9911	/* 22206 */ "DBITSWAP\0"	----
9912	/* 22215 */ "SDBBP\0"	----
9913	/* 22221 */ "TLBP\0"	----
9914	/* 22226 */ "EXTPDP\0"	----
9915	/* 22233 */ "G_SITOFP\0"	----
9916	/* 22242 */ "G_UITOFP\0"	----
9917	/* 22251 */ "TLBGP\0"	----
9918	/* 22257 */ "MTHLIP\0"	----
9919	/* 22264 */ "G_FCMP\0"	----
9920	/* 22271 */ "G_ICMP\0"	----
9921	/* 22278 */ "SSNOP\0"	----
9922	/* 22284 */ "DPOP\0"	----
9923	/* 22289 */ "G_CTPOP\0"	----
9924	/* 22297 */ "PATCHABLE_OP\0"	----
9925	/* 22310 */ "FAULTING_OP\0"	----
9926	/* 22322 */ "LOAD_ACC64DSP\0"	----
9927	/* 22336 */ "STORE_ACC64DSP\0"	----
9928	/* 22351 */ "RDDSP\0"	----
9929	/* 22357 */ "WRDSP\0"	----
9930	/* 22363 */ "MFTDSP\0"	----
9931	/* 22370 */ "MTTDSP\0"	----
9932	/* 22377 */ "LWDSP\0"	----
9933	/* 22383 */ "SWDSP\0"	----
9934	/* 22389 */ "MSUB_DSP\0"	----
9935	/* 22398 */ "MADD_DSP\0"	----
9936	/* 22407 */ "LOAD_CCOND_DSP\0"	----
9937	/* 22422 */ "STORE_CCOND_DSP\0"	----
9938	/* 22438 */ "MFHI_DSP\0"	----
9939	/* 22447 */ "PseudoMTLOHI_DSP\0"	----
9940	/* 22464 */ "MTHI_DSP\0"	----
9941	/* 22473 */ "MFLO_DSP\0"	----
9942	/* 22482 */ "MTLO_DSP\0"	----
9943	/* 22491 */ "MULT_DSP\0"	----
9944	/* 22500 */ "MSUBU_DSP\0"	----
9945	/* 22510 */ "MADDU_DSP\0"	----
9946	/* 22520 */ "MULTU_DSP\0"	----
9947	/* 22530 */ "JRADDIUSP\0"	----
9948	/* 22540 */ "EXTP\0"	----
9949	/* 22545 */ "ADJCALLSTACKUP\0"	----
9950	/* 22560 */ "PREALLOCATED_SETUP\0"	----
9951	/* 22579 */ "DVP\0"	----
9952	/* 22583 */ "EVP\0"	----
9953	/* 22587 */ "G_FLDEXP\0"	----
9954	/* 22596 */ "G_STRICT_FLDEXP\0"	----
9955	/* 22612 */ "G_FEXP\0"	----
9956	/* 22619 */ "G_FFREXP\0"	----
9957	/* 22628 */ "BEQ\0"	----
9958	/* 22632 */ "SEQ\0"	----
9959	/* 22636 */ "TEQ\0"	----
9960	/* 22640 */ "TLBR\0"	----
9961	/* 22645 */ "MULEU_S_PH_QBR\0"	----
9962	/* 22660 */ "PRECEU_PH_QBR\0"	----
9963	/* 22674 */ "PRECEQU_PH_QBR\0"	----
9964	/* 22689 */ "DPAU_H_QBR\0"	----
9965	/* 22700 */ "DPSU_H_QBR\0"	----
9966	/* 22711 */ "G_BR\0"	----
9967	/* 22716 */ "BAL_BR\0"	----
9968	/* 22723 */ "INLINEASM_BR\0"	----
9969	/* 22736 */ "G_BLOCK_ADDR\0"	----
9970	/* 22749 */ "LDR\0"	----
9971	/* 22753 */ "SDR\0"	----
9972	/* 22757 */ "MEMBARRIER\0"	----
9973	/* 22768 */ "G_CONSTANT_FOLD_BARRIER\0"	----
9974	/* 22792 */ "PATCHABLE_FUNCTION_ENTER\0"	----
9975	/* 22817 */ "G_READCYCLECOUNTER\0"	----
9976	/* 22836 */ "G_READ_REGISTER\0"	----
9977	/* 22852 */ "G_WRITE_REGISTER\0"	----
9978	/* 22869 */ "TLBGR\0"	----
9979	/* 22875 */ "LoadImmDoubleFGR\0"	----
9980	/* 22892 */ "LoadImmSingleFGR\0"	----
9981	/* 22909 */ "MAQ_SA_W_PHR\0"	----
9982	/* 22922 */ "PRECEQ_W_PHR\0"	----
9983	/* 22935 */ "MAQ_S_W_PHR\0"	----
9984	/* 22947 */ "MULEQ_S_W_PHR\0"	----
9985	/* 22961 */ "G_ASHR\0"	----
9986	/* 22968 */ "G_FSHR\0"	----
9987	/* 22975 */ "G_LSHR\0"	----
9988	/* 22982 */ "JR\0"	----
9989	/* 22985 */ "JALR\0"	----
9990	/* 22990 */ "NOR\0"	----
9991	/* 22994 */ "G_FFLOOR\0"	----
9992	/* 23003 */ "DROR\0"	----
9993	/* 23008 */ "G_BUILD_VECTOR\0"	----
9994	/* 23023 */ "G_SHUFFLE_VECTOR\0"	----
9995	/* 23040 */ "G_VECREDUCE_XOR\0"	----
9996	/* 23056 */ "G_XOR\0"	----
9997	/* 23062 */ "G_ATOMICRMW_XOR\0"	----
9998	/* 23078 */ "G_VECREDUCE_OR\0"	----
9999	/* 23093 */ "G_OR\0"	----
10000	/* 23098 */ "G_ATOMICRMW_OR\0"	----
10001	/* 23113 */ "MFTGPR\0"	----
10002	/* 23120 */ "MTTGPR\0"	----
10003	/* 23127 */ "LoadImmDoubleGPR\0"	----
10004	/* 23144 */ "LoadImmSingleGPR\0"	----
10005	/* 23161 */ "MFTR\0"	----
10006	/* 23166 */ "DROTR\0"	----
10007	/* 23172 */ "G_ROTR\0"	----
10008	/* 23179 */ "G_INTTOPTR\0"	----
10009	/* 23190 */ "MTTR\0"	----
10010	/* 23195 */ "TLBWR\0"	----
10011	/* 23201 */ "TLBGWR\0"	----
10012	/* 23208 */ "RDHWR\0"	----
10013	/* 23214 */ "LWR\0"	----
10014	/* 23218 */ "SWR\0"	----
10015	/* 23222 */ "G_FABS\0"	----
10016	/* 23229 */ "G_ABS\0"	----
10017	/* 23235 */ "G_UNMERGE_VALUES\0"	----
10018	/* 23252 */ "G_MERGE_VALUES\0"	----
10019	/* 23267 */ "CINS\0"	----
10020	/* 23272 */ "DINS\0"	----
10021	/* 23277 */ "G_FCOS\0"	----
10022	/* 23284 */ "G_CONCAT_VECTORS\0"	----
10023	/* 23301 */ "COPY_TO_REGCLASS\0"	----
10024	/* 23318 */ "G_IS_FPCLASS\0"	----
10025	/* 23331 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"	----
10026	/* 23361 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"	----
10027	/* 23388 */ "EXTS\0"	----
10028	/* 23393 */ "CVT_D32_S\0"	----
10029	/* 23403 */ "CVT_D64_S\0"	----
10030	/* 23413 */ "MOVN_I64_S\0"	----
10031	/* 23424 */ "MOVZ_I64_S\0"	----
10032	/* 23435 */ "MINA_S\0"	----
10033	/* 23442 */ "MAXA_S\0"	----
10034	/* 23449 */ "FSUB_S\0"	----
10035	/* 23456 */ "NMSUB_S\0"	----
10036	/* 23464 */ "FADD_S\0"	----
10037	/* 23471 */ "NMADD_S\0"	----
10038	/* 23479 */ "C_NGE_S\0"	----
10039	/* 23487 */ "C_NGLE_S\0"	----
10040	/* 23496 */ "C_OLE_S\0"	----
10041	/* 23504 */ "CMP_SLE_S\0"	----
10042	/* 23514 */ "CMP_SULE_S\0"	----
10043	/* 23525 */ "C_ULE_S\0"	----
10044	/* 23533 */ "CMP_ULE_S\0"	----
10045	/* 23543 */ "C_LE_S\0"	----
10046	/* 23550 */ "CMP_LE_S\0"	----
10047	/* 23559 */ "CMP_SAF_S\0"	----
10048	/* 23569 */ "MSUBF_S\0"	----
10049	/* 23577 */ "MADDF_S\0"	----
10050	/* 23585 */ "C_SF_S\0"	----
10051	/* 23592 */ "MOVF_S\0"	----
10052	/* 23599 */ "C_F_S\0"	----
10053	/* 23605 */ "PseudoSELECTFP_F_S\0"	----
10054	/* 23624 */ "CMP_F_S\0"	----
10055	/* 23632 */ "FNEG_S\0"	----
10056	/* 23639 */ "MOVN_I_S\0"	----
10057	/* 23648 */ "MOVZ_I_S\0"	----
10058	/* 23657 */ "SEL_S\0"	----
10059	/* 23663 */ "C_NGL_S\0"	----
10060	/* 23671 */ "FMUL_S\0"	----
10061	/* 23678 */ "TRUNC_L_S\0"	----
10062	/* 23688 */ "ROUND_L_S\0"	----
10063	/* 23698 */ "CEIL_L_S\0"	----
10064	/* 23707 */ "FLOOR_L_S\0"	----
10065	/* 23717 */ "CVT_L_S\0"	----
10066	/* 23725 */ "MIN_S\0"	----
10067	/* 23731 */ "CMP_SUN_S\0"	----
10068	/* 23741 */ "C_UN_S\0"	----
10069	/* 23748 */ "CMP_UN_S\0"	----
10070	/* 23757 */ "RECIP_S\0"	----
10071	/* 23765 */ "C_SEQ_S\0"	----
10072	/* 23773 */ "CMP_SEQ_S\0"	----
10073	/* 23783 */ "CMP_SUEQ_S\0"	----
10074	/* 23794 */ "C_UEQ_S\0"	----
10075	/* 23802 */ "CMP_UEQ_S\0"	----
10076	/* 23812 */ "C_EQ_S\0"	----
10077	/* 23819 */ "CMP_EQ_S\0"	----
10078	/* 23828 */ "FABS_S\0"	----
10079	/* 23835 */ "CLASS_S\0"	----
10080	/* 23843 */ "PseudoSELECT_S\0"	----
10081	/* 23858 */ "C_NGT_S\0"	----
10082	/* 23866 */ "C_OLT_S\0"	----
10083	/* 23874 */ "CMP_SLT_S\0"	----
10084	/* 23884 */ "CMP_SULT_S\0"	----
10085	/* 23895 */ "C_ULT_S\0"	----
10086	/* 23903 */ "CMP_ULT_S\0"	----
10087	/* 23913 */ "C_LT_S\0"	----
10088	/* 23920 */ "CMP_LT_S\0"	----
10089	/* 23929 */ "RINT_S\0"	----
10090	/* 23936 */ "FSQRT_S\0"	----
10091	/* 23944 */ "RSQRT_S\0"	----
10092	/* 23952 */ "MOVT_S\0"	----
10093	/* 23959 */ "PseudoSELECTFP_T_S\0"	----
10094	/* 23978 */ "FDIV_S\0"	----
10095	/* 23985 */ "FMOV_S\0"	----
10096	/* 23992 */ "PseudoTRUNC_W_S\0"	----
10097	/* 24008 */ "ROUND_W_S\0"	----
10098	/* 24018 */ "CEIL_W_S\0"	----
10099	/* 24027 */ "FLOOR_W_S\0"	----
10100	/* 24037 */ "CVT_W_S\0"	----
10101	/* 24045 */ "MAX_S\0"	----
10102	/* 24051 */ "SELNEZ_S\0"	----
10103	/* 24060 */ "SELEQZ_S\0"	----
10104	/* 24069 */ "BC1T\0"	----
10105	/* 24074 */ "G_SSUBSAT\0"	----
10106	/* 24084 */ "G_USUBSAT\0"	----
10107	/* 24094 */ "G_SADDSAT\0"	----
10108	/* 24104 */ "G_UADDSAT\0"	----
10109	/* 24114 */ "G_SSHLSAT\0"	----
10110	/* 24124 */ "G_USHLSAT\0"	----
10111	/* 24134 */ "G_SMULFIXSAT\0"	----
10112	/* 24147 */ "G_UMULFIXSAT\0"	----
10113	/* 24160 */ "G_SDIVFIXSAT\0"	----
10114	/* 24173 */ "G_UDIVFIXSAT\0"	----
10115	/* 24186 */ "G_EXTRACT\0"	----
10116	/* 24196 */ "G_SELECT\0"	----
10117	/* 24205 */ "G_BRINDIRECT\0"	----
10118	/* 24218 */ "DERET\0"	----
10119	/* 24224 */ "PATCHABLE_RET\0"	----
10120	/* 24238 */ "G_MEMSET\0"	----
10121	/* 24247 */ "BGT\0"	----
10122	/* 24251 */ "WAIT\0"	----
10123	/* 24256 */ "PATCHABLE_FUNCTION_EXIT\0"	----
10124	/* 24280 */ "G_BRJT\0"	----
10125	/* 24287 */ "BLT\0"	----
10126	/* 24291 */ "G_EXTRACT_VECTOR_ELT\0"	----
10127	/* 24312 */ "G_INSERT_VECTOR_ELT\0"	----
10128	/* 24332 */ "SLT\0"	----
10129	/* 24336 */ "TLT\0"	----
10130	/* 24340 */ "PseudoDMULT\0"	----
10131	/* 24352 */ "PseudoMULT\0"	----
10132	/* 24363 */ "DMT\0"	----
10133	/* 24367 */ "EMT\0"	----
10134	/* 24371 */ "G_FCONSTANT\0"	----
10135	/* 24383 */ "G_CONSTANT\0"	----
10136	/* 24394 */ "STATEPOINT\0"	----
10137	/* 24405 */ "PATCHPOINT\0"	----
10138	/* 24416 */ "G_PTRTOINT\0"	----
10139	/* 24427 */ "G_FRINT\0"	----
10140	/* 24435 */ "G_INTRINSIC_LRINT\0"	----
10141	/* 24453 */ "G_FNEARBYINT\0"	----
10142	/* 24466 */ "G_VASTART\0"	----
10143	/* 24476 */ "LIFETIME_START\0"	----
10144	/* 24491 */ "G_INVOKE_REGION_START\0"	----
10145	/* 24513 */ "G_INSERT\0"	----
10146	/* 24522 */ "G_FSQRT\0"	----
10147	/* 24530 */ "G_STRICT_FSQRT\0"	----
10148	/* 24545 */ "G_BITCAST\0"	----
10149	/* 24555 */ "G_ADDRSPACE_CAST\0"	----
10150	/* 24572 */ "DBG_VALUE_LIST\0"	----
10151	/* 24587 */ "GINVT\0"	----
10152	/* 24593 */ "DEXT\0"	----
10153	/* 24598 */ "G_FPEXT\0"	----
10154	/* 24606 */ "G_SEXT\0"	----
10155	/* 24613 */ "G_ASSERT_SEXT\0"	----
10156	/* 24627 */ "G_ANYEXT\0"	----
10157	/* 24636 */ "G_ZEXT\0"	----
10158	/* 24643 */ "G_ASSERT_ZEXT\0"	----
10159	/* 24657 */ "PseudoMSUBU\0"	----
10160	/* 24669 */ "PseudoMADDU\0"	----
10161	/* 24681 */ "DMODU\0"	----
10162	/* 24687 */ "BGEU\0"	----
10163	/* 24692 */ "SGEU\0"	----
10164	/* 24697 */ "TGEU\0"	----
10165	/* 24702 */ "BLEU\0"	----
10166	/* 24707 */ "SLEU\0"	----
10167	/* 24712 */ "DMUHU\0"	----
10168	/* 24718 */ "TGEIU\0"	----
10169	/* 24724 */ "TTLTIU\0"	----
10170	/* 24731 */ "V3MULU\0"	----
10171	/* 24738 */ "DMULU\0"	----
10172	/* 24744 */ "VMULU\0"	----
10173	/* 24750 */ "DINSU\0"	----
10174	/* 24756 */ "BGTU\0"	----
10175	/* 24761 */ "BLTU\0"	----
10176	/* 24766 */ "TLTU\0"	----
10177	/* 24771 */ "DEXTU\0"	----
10178	/* 24777 */ "DDIVU\0"	----
10179	/* 24783 */ "DSRAV\0"	----
10180	/* 24789 */ "BITREV\0"	----
10181	/* 24796 */ "DDIV\0"	----
10182	/* 24801 */ "G_FDIV\0"	----
10183	/* 24808 */ "G_STRICT_FDIV\0"	----
10184	/* 24822 */ "PseudoDSDIV\0"	----
10185	/* 24834 */ "G_SDIV\0"	----
10186	/* 24841 */ "PseudoSDIV\0"	----
10187	/* 24852 */ "PseudoDUDIV\0"	----
10188	/* 24864 */ "G_UDIV\0"	----
10189	/* 24871 */ "PseudoUDIV\0"	----
10190	/* 24882 */ "DSLLV\0"	----
10191	/* 24888 */ "DSRLV\0"	----
10192	/* 24894 */ "TLBINV\0"	----
10193	/* 24901 */ "TLBGINV\0"	----
10194	/* 24909 */ "SHILOV\0"	----
10195	/* 24916 */ "EXTPDPV\0"	----
10196	/* 24924 */ "EXTPV\0"	----
10197	/* 24930 */ "DROTRV\0"	----
10198	/* 24937 */ "INSV\0"	----
10199	/* 24942 */ "AND_V\0"	----
10200	/* 24948 */ "MOVE_V\0"	----
10201	/* 24955 */ "BSEL_V\0"	----
10202	/* 24962 */ "NOR_V\0"	----
10203	/* 24968 */ "XOR_V\0"	----
10204	/* 24974 */ "BZ_V\0"	----
10205	/* 24979 */ "BMZ_V\0"	----
10206	/* 24985 */ "BNZ_V\0"	----
10207	/* 24991 */ "BMNZ_V\0"	----
10208	/* 24998 */ "CRC32W\0"	----
10209	/* 25005 */ "CRC32CW\0"	----
10210	/* 25013 */ "LW\0"	----
10211	/* 25016 */ "G_FPOW\0"	----
10212	/* 25023 */ "SW\0"	----
10213	/* 25026 */ "PseudoCVT_D32_W\0"	----
10214	/* 25042 */ "FLOG2_W\0"	----
10215	/* 25050 */ "FEXP2_W\0"	----
10216	/* 25058 */ "PseudoCVT_D64_W\0"	----
10217	/* 25074 */ "SRA_W\0"	----
10218	/* 25080 */ "ADD_A_W\0"	----
10219	/* 25088 */ "FMIN_A_W\0"	----
10220	/* 25097 */ "ADDS_A_W\0"	----
10221	/* 25106 */ "FMAX_A_W\0"	----
10222	/* 25115 */ "FSUB_W\0"	----
10223	/* 25122 */ "FMSUB_W\0"	----
10224	/* 25130 */ "NLOC_W\0"	----
10225	/* 25137 */ "NLZC_W\0"	----
10226	/* 25144 */ "FADD_W\0"	----
10227	/* 25151 */ "FMADD_W\0"	----
10228	/* 25159 */ "SLD_W\0"	----
10229	/* 25165 */ "PCKOD_W\0"	----
10230	/* 25173 */ "ILVOD_W\0"	----
10231	/* 25181 */ "FCLE_W\0"	----
10232	/* 25188 */ "FSLE_W\0"	----
10233	/* 25195 */ "FCULE_W\0"	----
10234	/* 25203 */ "FSULE_W\0"	----
10235	/* 25211 */ "FCNE_W\0"	----
10236	/* 25218 */ "FSNE_W\0"	----
10237	/* 25225 */ "FCUNE_W\0"	----
10238	/* 25233 */ "FSUNE_W\0"	----
10239	/* 25241 */ "INSVE_W\0"	----
10240	/* 25249 */ "FCAF_W\0"	----
10241	/* 25256 */ "FSAF_W\0"	----
10242	/* 25263 */ "VSHF_W\0"	----
10243	/* 25270 */ "BNEG_W\0"	----
10244	/* 25277 */ "PRECR_SRA_PH_W\0"	----
10245	/* 25292 */ "PRECRQ_PH_W\0"	----
10246	/* 25304 */ "PRECR_SRA_R_PH_W\0"	----
10247	/* 25321 */ "PRECRQ_RS_PH_W\0"	----
10248	/* 25336 */ "SUBQH_W\0"	----
10249	/* 25344 */ "ADDQH_W\0"	----
10250	/* 25352 */ "SRAI_W\0"	----
10251	/* 25359 */ "SLDI_W\0"	----
10252	/* 25366 */ "BNEGI_W\0"	----
10253	/* 25374 */ "SLLI_W\0"	----
10254	/* 25381 */ "SRLI_W\0"	----
10255	/* 25388 */ "BINSLI_W\0"	----
10256	/* 25397 */ "CEQI_W\0"	----
10257	/* 25404 */ "SRARI_W\0"	----
10258	/* 25412 */ "BCLRI_W\0"	----
10259	/* 25420 */ "SRLRI_W\0"	----
10260	/* 25428 */ "BINSRI_W\0"	----
10261	/* 25437 */ "SPLATI_W\0"	----
10262	/* 25446 */ "BSETI_W\0"	----
10263	/* 25454 */ "SUBVI_W\0"	----
10264	/* 25462 */ "ADDVI_W\0"	----
10265	/* 25470 */ "FILL_W\0"	----
10266	/* 25477 */ "SLL_W\0"	----
10267	/* 25483 */ "FEXUPL_W\0"	----
10268	/* 25492 */ "FFQL_W\0"	----
10269	/* 25499 */ "SRL_W\0"	----
10270	/* 25505 */ "BINSL_W\0"	----
10271	/* 25513 */ "FMUL_W\0"	----
10272	/* 25520 */ "ILVL_W\0"	----
10273	/* 25527 */ "DPAQ_SA_L_W\0"	----
10274	/* 25539 */ "DPSQ_SA_L_W\0"	----
10275	/* 25551 */ "FMIN_W\0"	----
10276	/* 25558 */ "FCUN_W\0"	----
10277	/* 25565 */ "FSUN_W\0"	----
10278	/* 25572 */ "FEXDO_W\0"	----
10279	/* 25580 */ "FRCP_W\0"	----
10280	/* 25587 */ "FCEQ_W\0"	----
10281	/* 25594 */ "FSEQ_W\0"	----
10282	/* 25601 */ "FCUEQ_W\0"	----
10283	/* 25609 */ "FSUEQ_W\0"	----
10284	/* 25617 */ "FTQ_W\0"	----
10285	/* 25623 */ "MSUB_Q_W\0"	----
10286	/* 25632 */ "MADD_Q_W\0"	----
10287	/* 25641 */ "MUL_Q_W\0"	----
10288	/* 25649 */ "MSUBR_Q_W\0"	----
10289	/* 25659 */ "MADDR_Q_W\0"	----
10290	/* 25669 */ "MULR_Q_W\0"	----
10291	/* 25678 */ "SRAR_W\0"	----
10292	/* 25685 */ "LDR_W\0"	----
10293	/* 25691 */ "BCLR_W\0"	----
10294	/* 25698 */ "SRLR_W\0"	----
10295	/* 25705 */ "FCOR_W\0"	----
10296	/* 25712 */ "FSOR_W\0"	----
10297	/* 25719 */ "FEXUPR_W\0"	----
10298	/* 25728 */ "FFQR_W\0"	----
10299	/* 25735 */ "BINSR_W\0"	----
10300	/* 25743 */ "STR_W\0"	----
10301	/* 25749 */ "EXTR_W\0"	----
10302	/* 25756 */ "ILVR_W\0"	----
10303	/* 25763 */ "SHRA_R_W\0"	----
10304	/* 25772 */ "SUBQH_R_W\0"	----
10305	/* 25782 */ "ADDQH_R_W\0"	----
10306	/* 25792 */ "EXTR_R_W\0"	----
10307	/* 25801 */ "SHRAV_R_W\0"	----
10308	/* 25811 */ "EXTRV_R_W\0"	----
10309	/* 25821 */ "FABS_W\0"	----
10310	/* 25828 */ "MULQ_RS_W\0"	----
10311	/* 25838 */ "EXTR_RS_W\0"	----
10312	/* 25848 */ "EXTRV_RS_W\0"	----
10313	/* 25859 */ "FCLASS_W\0"	----
10314	/* 25868 */ "ASUB_S_W\0"	----
10315	/* 25877 */ "HSUB_S_W\0"	----
10316	/* 25886 */ "DPSUB_S_W\0"	----
10317	/* 25896 */ "FTRUNC_S_W\0"	----
10318	/* 25907 */ "HADD_S_W\0"	----
10319	/* 25916 */ "DPADD_S_W\0"	----
10320	/* 25926 */ "MOD_S_W\0"	----
10321	/* 25934 */ "CLE_S_W\0"	----
10322	/* 25942 */ "AVE_S_W\0"	----
10323	/* 25950 */ "CLEI_S_W\0"	----
10324	/* 25959 */ "MINI_S_W\0"	----
10325	/* 25968 */ "CLTI_S_W\0"	----
10326	/* 25977 */ "MAXI_S_W\0"	----
10327	/* 25986 */ "SHLL_S_W\0"	----
10328	/* 25995 */ "MIN_S_W\0"	----
10329	/* 26003 */ "DOTP_S_W\0"	----
10330	/* 26012 */ "SUBQ_S_W\0"	----
10331	/* 26021 */ "ADDQ_S_W\0"	----
10332	/* 26030 */ "MULQ_S_W\0"	----
10333	/* 26039 */ "ABSQ_S_W\0"	----
10334	/* 26048 */ "AVER_S_W\0"	----
10335	/* 26057 */ "SUBS_S_W\0"	----
10336	/* 26066 */ "ADDS_S_W\0"	----
10337	/* 26075 */ "SAT_S_W\0"	----
10338	/* 26083 */ "CLT_S_W\0"	----
10339	/* 26091 */ "FFINT_S_W\0"	----
10340	/* 26101 */ "FTINT_S_W\0"	----
10341	/* 26111 */ "PseudoCVT_S_W\0"	----
10342	/* 26125 */ "SUBSUU_S_W\0"	----
10343	/* 26136 */ "DIV_S_W\0"	----
10344	/* 26144 */ "SHLLV_S_W\0"	----
10345	/* 26154 */ "MAX_S_W\0"	----
10346	/* 26162 */ "COPY_S_W\0"	----
10347	/* 26171 */ "SPLAT_W\0"	----
10348	/* 26179 */ "BSET_W\0"	----
10349	/* 26186 */ "FCLT_W\0"	----
10350	/* 26193 */ "FSLT_W\0"	----
10351	/* 26200 */ "FCULT_W\0"	----
10352	/* 26208 */ "FSULT_W\0"	----
10353	/* 26216 */ "PCNT_W\0"	----
10354	/* 26223 */ "FRINT_W\0"	----
10355	/* 26231 */ "INSERT_W\0"	----
10356	/* 26240 */ "FSQRT_W\0"	----
10357	/* 26248 */ "FRSQRT_W\0"	----
10358	/* 26257 */ "ST_W\0"	----
10359	/* 26262 */ "ASUB_U_W\0"	----
10360	/* 26271 */ "HSUB_U_W\0"	----
10361	/* 26280 */ "DPSUB_U_W\0"	----
10362	/* 26290 */ "FTRUNC_U_W\0"	----
10363	/* 26301 */ "HADD_U_W\0"	----
10364	/* 26310 */ "DPADD_U_W\0"	----
10365	/* 26320 */ "MOD_U_W\0"	----
10366	/* 26328 */ "CLE_U_W\0"	----
10367	/* 26336 */ "AVE_U_W\0"	----
10368	/* 26344 */ "CLEI_U_W\0"	----
10369	/* 26353 */ "MINI_U_W\0"	----
10370	/* 26362 */ "CLTI_U_W\0"	----
10371	/* 26371 */ "MAXI_U_W\0"	----
10372	/* 26380 */ "MIN_U_W\0"	----
10373	/* 26388 */ "DOTP_U_W\0"	----
10374	/* 26397 */ "AVER_U_W\0"	----
10375	/* 26406 */ "SUBS_U_W\0"	----
10376	/* 26415 */ "ADDS_U_W\0"	----
10377	/* 26424 */ "SUBSUS_U_W\0"	----
10378	/* 26435 */ "SAT_U_W\0"	----
10379	/* 26443 */ "CLT_U_W\0"	----
10380	/* 26451 */ "FFINT_U_W\0"	----
10381	/* 26461 */ "FTINT_U_W\0"	----
10382	/* 26471 */ "DIV_U_W\0"	----
10383	/* 26479 */ "MAX_U_W\0"	----
10384	/* 26487 */ "COPY_U_W\0"	----
10385	/* 26496 */ "MSUBV_W\0"	----
10386	/* 26504 */ "MADDV_W\0"	----
10387	/* 26512 */ "PCKEV_W\0"	----
10388	/* 26520 */ "ILVEV_W\0"	----
10389	/* 26528 */ "FDIV_W\0"	----
10390	/* 26535 */ "MULV_W\0"	----
10391	/* 26542 */ "EXTRV_W\0"	----
10392	/* 26550 */ "FMAX_W\0"	----
10393	/* 26557 */ "BZ_W\0"	----
10394	/* 26562 */ "BNZ_W\0"	----
10395	/* 26568 */ "G_VECREDUCE_FMAX\0"	----
10396	/* 26585 */ "G_ATOMICRMW_FMAX\0"	----
10397	/* 26602 */ "G_VECREDUCE_SMAX\0"	----
10398	/* 26619 */ "G_SMAX\0"	----
10399	/* 26626 */ "G_VECREDUCE_UMAX\0"	----
10400	/* 26643 */ "G_UMAX\0"	----
10401	/* 26650 */ "G_ATOMICRMW_UMAX\0"	----
10402	/* 26667 */ "G_ATOMICRMW_MAX\0"	----
10403	/* 26683 */ "MFTACX\0"	----
10404	/* 26690 */ "MTTACX\0"	----
10405	/* 26697 */ "G_FRAME_INDEX\0"	----
10406	/* 26711 */ "G_SBFX\0"	----
10407	/* 26718 */ "G_UBFX\0"	----
10408	/* 26725 */ "LHX\0"	----
10409	/* 26729 */ "G_SMULFIX\0"	----
10410	/* 26739 */ "G_UMULFIX\0"	----
10411	/* 26749 */ "G_SDIVFIX\0"	----
10412	/* 26759 */ "G_UDIVFIX\0"	----
10413	/* 26769 */ "JALX\0"	----
10414	/* 26774 */ "LBUX\0"	----
10415	/* 26779 */ "LWX\0"	----
10416	/* 26783 */ "G_MEMCPY\0"	----
10417	/* 26792 */ "COPY\0"	----
10418	/* 26797 */ "CONSTPOOL_ENTRY\0"	----
10419	/* 26813 */ "BGEZ\0"	----
10420	/* 26818 */ "BLEZ\0"	----
10421	/* 26823 */ "BC1NEZ\0"	----
10422	/* 26830 */ "BC2NEZ\0"	----
10423	/* 26837 */ "SELNEZ\0"	----
10424	/* 26844 */ "DCLZ\0"	----
10425	/* 26849 */ "G_CTLZ\0"	----
10426	/* 26856 */ "BC1EQZ\0"	----
10427	/* 26863 */ "BC2EQZ\0"	----
10428	/* 26870 */ "SELEQZ\0"	----
10429	/* 26877 */ "BGTZ\0"	----
10430	/* 26882 */ "BLTZ\0"	----
10431	/* 26887 */ "G_CTTZ\0"	----
10432	/* 26894 */ "SelBneZ\0"	----
10433	/* 26902 */ "SelBeqZ\0"	----
10434	/* 26910 */ "JalOneReg\0"	----
10435	/* 26920 */ "JalTwoReg\0"	----
10436	/* 26930 */ "PseudoIndirectHazardBranch\0"	----
10437	/* 26957 */ "PseudoIndirectBranch\0"	----
10438	/* 26978 */ "Ulh\0"	----
10439	/* 26982 */ "Ush\0"	----
10440	/* 26986 */ "DADDi\0"	----
10441	/* 26992 */ "ANDi\0"	----
10442	/* 26997 */ "SNEi\0"	----
10443	/* 27002 */ "SEQi\0"	----
10444	/* 27007 */ "XORi\0"	----
10445	/* 27012 */ "SLTi\0"	----
10446	/* 27017 */ "LONG_BRANCH_LUi\0"	----
10447	/* 27033 */ "SelTBtneZCmpi\0"	----
10448	/* 27047 */ "SelTBteqZCmpi\0"	----
10449	/* 27061 */ "SelTBtneZSlti\0"	----
10450	/* 27075 */ "SelTBteqZSlti\0"	----
10451	/* 27089 */ "SGEImm\0"	----
10452	/* 27096 */ "SLEImm\0"	----
10453	/* 27103 */ "DROLImm\0"	----
10454	/* 27111 */ "NORImm\0"	----
10455	/* 27118 */ "DRORImm\0"	----
10456	/* 27126 */ "SGTImm\0"	----
10457	/* 27133 */ "SGEUImm\0"	----
10458	/* 27141 */ "SLEUImm\0"	----
10459	/* 27149 */ "SGTUImm\0"	----
10460	/* 27157 */ "BneImm\0"	----
10461	/* 27164 */ "BeqImm\0"	----
10462	/* 27171 */ "PseudoReturn\0"	----
10463	/* 27184 */ "JALRHB64Pseudo\0"	----
10464	/* 27199 */ "JALR64Pseudo\0"	----
10465	/* 27212 */ "JALRHBPseudo\0"	----
10466	/* 27225 */ "JALRPseudo\0"	----
10467	/* 27236 */ "B_MMR6_Pseudo\0"	----
10468	/* 27250 */ "B_MM_Pseudo\0"	----
10469	/* 27262 */ "SDIV_MM_Pseudo\0"	----
10470	/* 27277 */ "UDIV_MM_Pseudo\0"	----
10471	/* 27292 */ "LDMacro\0"	----
10472	/* 27300 */ "SDMacro\0"	----
10473	/* 27308 */ "SNEMacro\0"	----
10474	/* 27317 */ "SNEIMacro\0"	----
10475	/* 27327 */ "SEQIMacro\0"	----
10476	/* 27337 */ "DSRemIMacro\0"	----
10477	/* 27349 */ "DURemIMacro\0"	----
10478	/* 27361 */ "DSDivIMacro\0"	----
10479	/* 27373 */ "DUDivIMacro\0"	----
10480	/* 27385 */ "DMULMacro\0"	----
10481	/* 27395 */ "DMULOMacro\0"	----
10482	/* 27406 */ "SEQMacro\0"	----
10483	/* 27415 */ "ABSMacro\0"	----
10484	/* 27424 */ "DMULOUMacro\0"	----
10485	/* 27436 */ "DSRemMacro\0"	----
10486	/* 27447 */ "DURemMacro\0"	----
10487	/* 27458 */ "BGEImmMacro\0"	----
10488	/* 27470 */ "BLEImmMacro\0"	----
10489	/* 27482 */ "BGELImmMacro\0"	----
10490	/* 27495 */ "BLELImmMacro\0"	----
10491	/* 27508 */ "BNELImmMacro\0"	----
10492	/* 27521 */ "BEQLImmMacro\0"	----
10493	/* 27534 */ "BGTLImmMacro\0"	----
10494	/* 27547 */ "BLTLImmMacro\0"	----
10495	/* 27560 */ "BGEULImmMacro\0"	----
10496	/* 27574 */ "BLEULImmMacro\0"	----
10497	/* 27588 */ "DMULImmMacro\0"	----
10498	/* 27601 */ "BGTULImmMacro\0"	----
10499	/* 27615 */ "BLTULImmMacro\0"	----
10500	/* 27629 */ "BGTImmMacro\0"	----
10501	/* 27641 */ "BLTImmMacro\0"	----
10502	/* 27653 */ "BGEUImmMacro\0"	----
10503	/* 27666 */ "BLEUImmMacro\0"	----
10504	/* 27679 */ "BGTUImmMacro\0"	----
10505	/* 27692 */ "BLTUImmMacro\0"	----
10506	/* 27705 */ "DSDivMacro\0"	----
10507	/* 27716 */ "DUDivMacro\0"	----
10508	/* 27727 */ "LONG_BRANCH_LUi2Op\0"	----
10509	/* 27746 */ "LONG_BRANCH_DADDiu2Op\0"	----
10510	/* 27768 */ "LONG_BRANCH_ADDiu2Op\0"	----
10511	/* 27789 */ "SelTBtneZCmp\0"	----
10512	/* 27802 */ "SelTBteqZCmp\0"	----
10513	/* 27815 */ "SaaAddr\0"	----
10514	/* 27823 */ "SaadAddr\0"	----
10515	/* 27832 */ "ERet\0"	----
10516	/* 27837 */ "SelTBtneZSlt\0"	----
10517	/* 27850 */ "SelTBteqZSlt\0"	----
10518	/* 27863 */ "LBu\0"	----
10519	/* 27867 */ "DSUBu\0"	----
10520	/* 27873 */ "BADDu\0"	----
10521	/* 27879 */ "DADDu\0"	----
10522	/* 27885 */ "LHu\0"	----
10523	/* 27889 */ "SLTu\0"	----
10524	/* 27894 */ "PseudoDMULTu\0"	----
10525	/* 27907 */ "PseudoMULTu\0"	----
10526	/* 27919 */ "LWu\0"	----
10527	/* 27923 */ "Ulhu\0"	----
10528	/* 27928 */ "LONG_BRANCH_DADDiu\0"	----
10529	/* 27947 */ "LEA_ADDiu\0"	----
10530	/* 27957 */ "LONG_BRANCH_ADDiu\0"	----
10531	/* 27975 */ "SLTiu\0"	----
10532	/* 27981 */ "SelTBtneZSltiu\0"	----
10533	/* 27996 */ "SelTBteqZSltiu\0"	----
10534	/* 28011 */ "SelTBtneZSltu\0"	----
10535	/* 28025 */ "SelTBteqZSltu\0"	----
10536	/* 28039 */ "Ulw\0"	----
10537	/* 28043 */ "Usw\0"	----
10538	};	----
10539	#ifdef __GNUC__	----
10540	#pragma GCC diagnostic pop	----
10541	#endif	----
10542		----
10543	extern const unsigned MipsInstrNameIndices[] = {	----
10544	15358U, 20903U, 22723U, 21178U, 15706U, 15687U, 15715U, 15967U,	----
10545	13725U, 13740U, 13605U, 13779U, 23301U, 13484U, 24572U, 13623U,	----
10546	15354U, 15696U, 13233U, 26792U, 13355U, 24476U, 11679U, 13180U,	----
10547	13221U, 22140U, 15939U, 24405U, 11769U, 22560U, 13842U, 24394U,	----
10548	13408U, 22310U, 22297U, 22792U, 24224U, 24256U, 15871U, 15918U,	----
10549	15891U, 15747U, 22757U, 24613U, 24643U, 21003U, 11562U, 10295U,	----
10550	16123U, 24834U, 24864U, 16224U, 16231U, 16238U, 16248U, 11642U,	----
10551	23093U, 23056U, 13603U, 15356U, 26697U, 13494U, 15977U, 24186U,	----
10552	23235U, 24513U, 23252U, 23008U, 11181U, 23284U, 24416U, 23179U,	----
10553	24545U, 13527U, 22768U, 11738U, 11155U, 11720U, 24435U, 20967U,	----
10554	22817U, 11435U, 11379U, 11409U, 11420U, 11360U, 11390U, 13447U,	----
10555	13431U, 23331U, 13793U, 13810U, 11578U, 10301U, 11648U, 11609U,	----
10556	23098U, 23062U, 26667U, 21129U, 26650U, 21112U, 11518U, 10267U,	----
10557	26585U, 21047U, 22176U, 22154U, 13213U, 11692U, 24205U, 24491U,	----
10558	11067U, 23361U, 24627U, 11173U, 24383U, 24371U, 24466U, 13834U,	----
10559	24606U, 13766U, 24636U, 15832U, 22975U, 22961U, 15825U, 22968U,	----
10560	23172U, 16024U, 22271U, 22264U, 24196U, 21235U, 13258U, 21219U,	----
10561	13205U, 21227U, 13250U, 21211U, 13197U, 22124U, 22116U, 13896U,	----
10562	13888U, 24104U, 24094U, 24084U, 24074U, 24124U, 24114U, 26729U,	----
10563	26739U, 24134U, 24147U, 26749U, 26759U, 24160U, 24173U, 11476U,	----
10564	10246U, 16065U, 8500U, 11353U, 24801U, 16203U, 25016U, 15436U,	----
10565	22612U, 1205U, 13827U, 1187U, 0U, 22587U, 22619U, 13654U,	----
10566	24598U, 11145U, 15384U, 15408U, 22233U, 22242U, 23222U, 21018U,	----
10567	23318U, 13536U, 20947U, 20957U, 13266U, 13281U, 20925U, 20936U,	----
10568	11568U, 15581U, 21081U, 26619U, 21105U, 26643U, 23229U, 11711U,	----
10569	11701U, 22711U, 24280U, 24312U, 24291U, 23023U, 26887U, 13585U,	----
10570	26849U, 13567U, 22289U, 22198U, 13465U, 15838U, 23277U, 21145U,	----
10571	24522U, 22994U, 24427U, 24453U, 24555U, 22736U, 13342U, 11207U,	----
10572	11504U, 10253U, 16093U, 24808U, 16210U, 8506U, 24530U, 22596U,	----
10573	22836U, 22852U, 26783U, 13384U, 13509U, 24238U, 22132U, 11483U,	----
10574	16072U, 11459U, 16048U, 26568U, 21030U, 11546U, 16107U, 11626U,	----
10575	23078U, 23040U, 26602U, 21064U, 26626U, 21088U, 26711U, 26718U,	----
10576	27415U, 21194U, 22545U, 21579U, 21663U, 21879U, 4064U, 9386U,	----
10577	884U, 8742U, 3089U, 9064U, 8370U, 9701U, 3946U, 9226U,	----
10578	766U, 8582U, 2919U, 8904U, 8258U, 9547U, 3987U, 9281U,	----
10579	807U, 8637U, 2960U, 8959U, 8297U, 9600U, 4144U, 9494U,	----
10580	964U, 8850U, 3235U, 9172U, 8446U, 9805U, 4028U, 9336U,	----
10581	848U, 8692U, 3053U, 9014U, 8336U, 9653U, 3966U, 9253U,	----
10582	786U, 8609U, 2939U, 8931U, 8277U, 9573U, 4104U, 9440U,	----
10583	924U, 8796U, 3129U, 9118U, 8408U, 9753U, 3926U, 9199U,	----
10584	746U, 8555U, 2899U, 8877U, 8239U, 9521U, 4123U, 9466U,	----
10585	943U, 8822U, 3214U, 9144U, 8426U, 9778U, 4007U, 9308U,	----
10586	827U, 8664U, 3032U, 8986U, 8316U, 9626U, 4084U, 9413U,	----
10587	904U, 8769U, 3109U, 9091U, 8389U, 9727U, 4048U, 9363U,	----
10588	868U, 8719U, 3073U, 9041U, 8355U, 9679U, 9861U, 22716U,	----
10589	19481U, 27521U, 13309U, 27458U, 15732U, 27482U, 24687U, 27653U,	----
10590	16031U, 27560U, 24247U, 27629U, 16014U, 27534U, 24756U, 27679U,	----
10591	16129U, 27601U, 13351U, 27470U, 15737U, 27495U, 24702U, 27666U,	----
10592	16037U, 27574U, 24287U, 27641U, 16019U, 27547U, 24761U, 27692U,	----
10593	16135U, 27615U, 27508U, 21277U, 21565U, 21458U, 21758U, 21649U,	----
10594	21865U, 17673U, 27236U, 27250U, 27164U, 27157U, 4668U, 4215U,	----
10595	4696U, 4245U, 4726U, 4757U, 4654U, 4200U, 4682U, 4230U,	----
10596	4710U, 4742U, 2777U, 3547U, 122U, 26797U, 21505U, 21805U,	----
10597	140U, 1144U, 27588U, 27385U, 27395U, 27424U, 15993U, 27103U,	----
10598	23003U, 27118U, 27361U, 27705U, 27337U, 27436U, 27373U, 27716U,	----
10599	27349U, 27447U, 27832U, 2790U, 3563U, 12472U, 25821U, 21243U,	----
10600	21260U, 21473U, 21773U, 4815U, 21293U, 21949U, 21340U, 21992U,	----
10601	21488U, 21316U, 21970U, 21788U, 21386U, 22034U, 21363U, 22013U,	----
10602	21410U, 22056U, 27199U, 27184U, 27212U, 27225U, 6952U, 26910U,	----
10603	26920U, 27292U, 12401U, 25685U, 3912U, 8214U, 2044U, 22322U,	----
10604	22407U, 27957U, 27768U, 27928U, 27746U, 27017U, 27727U, 3593U,	----
10605	19025U, 1112U, 3803U, 1079U, 3615U, 1102U, 3793U, 22875U,	----
10606	1059U, 23127U, 22892U, 23144U, 1142U, 26683U, 43U, 128U,	----
10607	22363U, 23113U, 103U, 15362U, 22099U, 1126U, 3832U, 21520U,	----
10608	21820U, 21543U, 21843U, 26690U, 55U, 146U, 22370U, 23120U,	----
10609	110U, 15373U, 22110U, 27589U, 27396U, 27425U, 5075U, 5208U,	----
10610	5107U, 5260U, 22280U, 27111U, 3726U, 21594U, 21678U, 21894U,	----
10611	21595U, 21679U, 21895U, 10041U, 9943U, 10156U, 14058U, 13953U,	----
10612	14218U, 25026U, 16173U, 25058U, 16189U, 26111U, 24340U, 27894U,	----
10613	24822U, 24852U, 15510U, 3148U, 26957U, 3658U, 5320U, 8191U,	----
10614	20765U, 7985U, 26930U, 3629U, 5290U, 8163U, 11535U, 24669U,	----
10615	20209U, 18005U, 15330U, 2838U, 18657U, 22082U, 3283U, 19046U,	----
10616	10284U, 24657U, 20194U, 17936U, 15341U, 2851U, 22447U, 18671U,	----
10617	24352U, 20173U, 27907U, 20866U, 13987U, 9978U, 27171U, 3817U,	----
10618	24841U, 379U, 2362U, 15473U, 2989U, 23605U, 635U, 2675U,	----
10619	15549U, 3193U, 23959U, 550U, 2590U, 15527U, 3167U, 23843U,	----
10620	13124U, 674U, 23992U, 24871U, 15994U, 27104U, 23004U, 27119U,	----
10621	9831U, 3897U, 203U, 27262U, 27300U, 27362U, 27706U, 27327U,	----
10622	27406U, 13313U, 27089U, 3708U, 24692U, 27133U, 3753U, 27126U,	----
10623	3735U, 27149U, 3773U, 13366U, 27096U, 3717U, 24707U, 27141U,	----
10624	3763U, 3744U, 3783U, 27317U, 27308U, 21433U, 21624U, 21708U,	----
10625	21733U, 21924U, 27338U, 27437U, 8226U, 2055U, 22336U, 22422U,	----
10626	12459U, 25743U, 3919U, 19032U, 21446U, 21637U, 21721U, 21746U,	----
10627	21937U, 27815U, 27823U, 26902U, 26894U, 27802U, 27047U, 27850U,	----
10628	27075U, 27996U, 28025U, 27789U, 27033U, 27837U, 27061U, 27981U,	----
10629	28011U, 5020U, 4479U, 4494U, 5032U, 5247U, 15846U, 13679U,	----
10630	13661U, 13695U, 13711U, 13754U, 2808U, 9879U, 2000U, 18216U,	----
10631	6829U, 18956U, 6961U, 22149U, 19077U, 27277U, 27374U, 27717U,	----
10632	27350U, 27448U, 26978U, 27923U, 28039U, 26982U, 28043U, 21609U,	----
10633	21693U, 21909U, 14177U, 18472U, 10101U, 1353U, 26039U, 20640U,	----
10634	11455U, 11242U, 17958U, 6006U, 19157U, 16905U, 17318U, 19329U,	----
10635	7871U, 13978U, 1456U, 14095U, 1511U, 25782U, 1869U, 25344U,	----
10636	1841U, 14050U, 18368U, 14157U, 18459U, 26021U, 20628U, 3401U,	----
10637	11266U, 17969U, 10339U, 11842U, 14457U, 25097U, 10747U, 12641U,	----
10638	14946U, 26066U, 10939U, 13006U, 15195U, 26415U, 17535U, 5746U,	----
10639	9969U, 1258U, 10079U, 1321U, 7841U, 14242U, 1599U, 10181U,	----
10640	17859U, 14197U, 1571U, 10121U, 17806U, 10553U, 12206U, 14642U,	----
10641	25462U, 11009U, 13087U, 15265U, 26505U, 11299U, 17978U, 10323U,	----
10642	11825U, 14441U, 25080U, 18012U, 6228U, 26987U, 20789U, 27941U,	----
10643	20885U, 27874U, 20843U, 20990U, 7019U, 11235U, 5994U, 11622U,	----
10644	17346U, 5587U, 2178U, 17373U, 5620U, 10428U, 6884U, 18019U,	----
10645	6237U, 24942U, 26992U, 3681U, 20797U, 11672U, 1413U, 10652U,	----
10646	12488U, 14795U, 25868U, 10844U, 12853U, 15053U, 26262U, 15404U,	----
10647	11229U, 5983U, 6912U, 10729U, 12623U, 14919U, 26048U, 10921U,	----
10648	12988U, 15177U, 26397U, 10677U, 12562U, 14858U, 25942U, 10869U,	----
10649	12927U, 15116U, 26336U, 4547U, 4423U, 4931U, 4575U, 4372U,	----
10650	4871U, 4439U, 5234U, 5173U, 17330U, 27873U, 15591U, 11079U,	----
10651	5862U, 20989U, 1774U, 76U, 222U, 216U, 230U, 11050U,	----
10652	5527U, 26856U, 6169U, 13562U, 15767U, 18188U, 26823U, 6132U,	----
10653	24069U, 16008U, 20134U, 26863U, 6182U, 26830U, 6145U, 10489U,	----
10654	12156U, 14592U, 25412U, 10623U, 12407U, 14766U, 25691U, 5825U,	----
10655	22628U, 3303U, 11261U, 2095U, 6029U, 15998U, 17580U, 11114U,	----
10656	5922U, 11323U, 5574U, 2154U, 17996U, 6195U, 19378U, 11053U,	----
10657	2067U, 5833U, 11277U, 2114U, 6068U, 26813U, 3501U, 15599U,	----
10658	11090U, 5883U, 15951U, 19650U, 18791U, 11305U, 2130U, 6110U,	----
10659	16149U, 20726U, 26877U, 3533U, 11122U, 5935U, 11329U, 2162U,	----
10660	6206U, 16161U, 20749U, 10465U, 12132U, 14568U, 25388U, 10595U,	----
10661	12255U, 14669U, 25505U, 10519U, 12172U, 14608U, 25428U, 10637U,	----
10662	12451U, 14780U, 25735U, 24789U, 20273U, 22207U, 7039U, 26818U,	----
10663	3508U, 11098U, 5896U, 11311U, 2138U, 6121U, 16155U, 20734U,	----
10664	11272U, 2107U, 6058U, 11283U, 2122U, 6079U, 26882U, 3540U,	----
10665	15606U, 11130U, 5948U, 15959U, 19661U, 18801U, 11335U, 2170U,	----
10666	6217U, 16167U, 20757U, 10568U, 24991U, 10561U, 24979U, 13380U,	----
10667	2771U, 11058U, 2074U, 5843U, 10435U, 12110U, 14546U, 25366U,	----
10668	10407U, 12089U, 14525U, 25270U, 15742U, 17570U, 11106U, 5909U,	----
10669	11317U, 5561U, 2146U, 17987U, 6158U, 18119U, 11289U, 6090U,	----
10670	11044U, 13161U, 15300U, 24985U, 26562U, 11294U, 6100U, 737U,	----
10671	1933U, 16847U, 15570U, 17401U, 5642U, 18775U, 6941U, 10443U,	----
10672	24955U, 10537U, 12190U, 14626U, 25446U, 10816U, 12730U, 15025U,	----
10673	26179U, 11039U, 13147U, 15295U, 24974U, 26557U, 4958U, 4604U,	----
10674	4970U, 4617U, 4946U, 4591U, 4857U, 5282U, 4781U, 5274U,	----
10675	4772U, 13321U, 13296U, 18047U, 18073U, 6772U, 8107U, 2457U,	----
10676	6435U, 23698U, 7419U, 704U, 2738U, 6704U, 20466U, 24018U,	----
10677	20098U, 7700U, 10474U, 12141U, 14577U, 25397U, 10610U, 12325U,	----
10678	14692U, 25588U, 92U, 16296U, 16889U, 9842U, 23267U, 1006U,	----
10679	1039U, 1093U, 12480U, 6577U, 23835U, 7561U, 10685U, 12570U,	----
10680	14866U, 25950U, 10877U, 12935U, 15124U, 26344U, 10669U, 12554U,	----
10681	14850U, 25934U, 10861U, 12919U, 15108U, 26328U, 22078U, 19039U,	----
10682	7030U, 8139U, 10703U, 12588U, 14884U, 25968U, 10895U, 12953U,	----
10683	15142U, 26362U, 10764U, 12658U, 14963U, 26083U, 10967U, 13034U,	----
10684	15223U, 26443U, 26845U, 20742U, 7964U, 8156U, 10016U, 1272U,	----
10685	9918U, 1226U, 10131U, 1368U, 10029U, 17764U, 9931U, 17691U,	----
10686	10144U, 17819U, 10047U, 17779U, 9949U, 17706U, 10162U, 17834U,	----
10687	6354U, 7314U, 12385U, 6563U, 14064U, 18379U, 23819U, 7547U,	----
10688	12081U, 23624U, 11987U, 6325U, 13959U, 18298U, 23550U, 7285U,	----
10689	12798U, 6636U, 14224U, 18499U, 23920U, 7620U, 12048U, 6339U,	----
10690	23559U, 7299U, 12338U, 6517U, 23773U, 7501U, 11940U, 6279U,	----
10691	23504U, 7239U, 12751U, 6590U, 23874U, 7574U, 12364U, 6532U,	----
10692	23783U, 7516U, 11966U, 6294U, 23514U, 7254U, 12777U, 6605U,	----
10693	23884U, 7589U, 12298U, 6488U, 23731U, 7472U, 12375U, 6548U,	----
10694	23802U, 7532U, 11977U, 6310U, 23533U, 7270U, 12788U, 6621U,	----
10695	23903U, 7605U, 12308U, 6503U, 23748U, 7487U, 10799U, 12713U,	----
10696	15008U, 26162U, 10991U, 15247U, 26487U, 9856U, 9863U, 11442U,	----
10697	13876U, 25005U, 11341U, 13859U, 24998U, 117U, 16312U, 16897U,	----
10698	9849U, 23393U, 19696U, 25032U, 20385U, 16179U, 23403U, 19709U,	----
10699	25064U, 20398U, 6993U, 2480U, 17103U, 6464U, 23717U, 19903U,	----
10700	7448U, 3484U, 3451U, 3439U, 540U, 16708U, 2580U, 17191U,	----
10701	16195U, 7006U, 3260U, 3468U, 26117U, 20652U, 7939U, 727U,	----
10702	16834U, 2761U, 17305U, 24037U, 20123U, 7729U, 522U, 16684U,	----
10703	2562U, 17167U, 23812U, 19957U, 371U, 16545U, 2354U, 17055U,	----
10704	23599U, 19839U, 344U, 16509U, 2327U, 17031U, 23543U, 19809U,	----
10705	597U, 16760U, 2637U, 17243U, 23913U, 20010U, 303U, 16456U,	----
10706	2286U, 16978U, 23479U, 19764U, 313U, 16469U, 2296U, 16991U,	----
10707	23487U, 19775U, 431U, 16596U, 2414U, 17078U, 23663U, 19882U,	----
10708	567U, 16721U, 2607U, 17204U, 23858U, 19977U, 324U, 16483U,	----
10709	2307U, 17005U, 23496U, 19787U, 577U, 16734U, 2617U, 17217U,	----
10710	23866U, 19988U, 502U, 16658U, 2542U, 17141U, 23765U, 19935U,	----
10711	353U, 16521U, 2336U, 17043U, 23585U, 19819U, 512U, 16671U,	----
10712	2552U, 17154U, 23794U, 19946U, 334U, 16496U, 2317U, 17018U,	----
10713	23525U, 19798U, 587U, 16747U, 2627U, 17230U, 23895U, 19999U,	----
10714	474U, 16621U, 2514U, 17116U, 23741U, 19914U, 5055U, 4894U,	----
10715	4521U, 11454U, 26986U, 27940U, 27879U, 15325U, 20996U, 15393U,	----
10716	15403U, 22206U, 22077U, 8138U, 26844U, 8155U, 24796U, 24777U,	----
10717	24218U, 20142U, 7781U, 24593U, 1049U, 20919U, 24771U, 15312U,	----
10718	23272U, 20913U, 24750U, 24797U, 24778U, 7892U, 7902U, 10783U,	----
10719	12697U, 14982U, 26136U, 10975U, 13062U, 15231U, 26471U, 18635U,	----
10720	6886U, 9837U, 8070U, 9U, 97U, 1165U, 21152U, 15U,	----
10721	11764U, 24681U, 24363U, 49U, 134U, 1171U, 21165U, 36U,	----
10722	14430U, 24712U, 16043U, 24346U, 27900U, 24738U, 8130U, 12614U,	----
10723	14910U, 26003U, 12979U, 15168U, 26388U, 12536U, 14832U, 25916U,	----
10724	12901U, 15090U, 26310U, 14306U, 1656U, 14381U, 1708U, 25527U,	----
10725	20476U, 14343U, 18548U, 15657U, 18864U, 22689U, 19453U, 14407U,	----
10726	1744U, 14286U, 1626U, 22284U, 14320U, 1675U, 14394U, 1726U,	----
10727	25539U, 20491U, 14369U, 18580U, 12506U, 14813U, 25886U, 12871U,	----
10728	15071U, 26280U, 15668U, 18878U, 22700U, 19467U, 14417U, 1759U,	----
10729	14334U, 1694U, 23166U, 998U, 24930U, 13866U, 24828U, 11594U,	----
10730	15972U, 984U, 1029U, 24882U, 8550U, 238U, 24783U, 16003U,	----
10731	991U, 24888U, 10241U, 27867U, 24858U, 22579U, 13421U, 7111U,	----
10732	5141U, 5119U, 9875U, 17678U, 5777U, 15317U, 18643U, 6894U,	----
10733	24367U, 24219U, 11138U, 5961U, 20143U, 7782U, 22583U, 13426U,	----
10734	7120U, 24594U, 22540U, 22226U, 24916U, 20336U, 19102U, 24924U,	----
10735	20347U, 19356U, 25848U, 20590U, 25811U, 20564U, 14990U, 18613U,	----
10736	26542U, 20676U, 25838U, 20577U, 25792U, 20539U, 14928U, 18601U,	----
10737	25749U, 20517U, 23388U, 1013U, 20187U, 7813U, 531U, 16696U,	----
10738	2571U, 17179U, 23828U, 19967U, 11889U, 284U, 16431U, 2267U,	----
10739	16966U, 3363U, 23464U, 19743U, 7227U, 25144U, 12034U, 25249U,	----
10740	12324U, 25587U, 12479U, 25859U, 11926U, 25181U, 12737U, 26186U,	----
10741	493U, 16646U, 2533U, 1020U, 16877U, 11996U, 25211U, 12421U,	----
10742	25705U, 12348U, 25601U, 11950U, 25195U, 12761U, 26200U, 12010U,	----
10743	25225U, 12284U, 25558U, 13110U, 656U, 16810U, 2696U, 17281U,	----
10744	23978U, 20052U, 7646U, 26528U, 14684U, 25572U, 11797U, 25050U,	----
10745	12233U, 25483U, 12435U, 25719U, 12666U, 26091U, 13042U, 26451U,	----
10746	12242U, 25492U, 12444U, 25728U, 10576U, 12220U, 14650U, 25470U,	----
10747	11789U, 25042U, 2468U, 6449U, 23707U, 7433U, 715U, 2749U,	----
10748	6718U, 20506U, 24027U, 20110U, 7714U, 11896U, 25151U, 11851U,	----
10749	25106U, 13140U, 26550U, 11833U, 25088U, 12277U, 25551U, 665U,	----
10750	16822U, 2705U, 17293U, 6662U, 23985U, 20062U, 7658U, 11867U,	----
10751	25122U, 12263U, 441U, 16609U, 2424U, 17091U, 3382U, 23671U,	----
10752	19893U, 7377U, 25513U, 400U, 16556U, 2383U, 17066U, 23632U,	----
10753	19848U, 7354U, 15576U, 12317U, 25580U, 12814U, 26223U, 12839U,	----
10754	26248U, 12041U, 25256U, 12331U, 25594U, 11933U, 25188U, 12744U,	----
10755	26193U, 12003U, 25218U, 12428U, 25712U, 12831U, 606U, 16772U,	----
10756	2646U, 17255U, 23936U, 20020U, 26240U, 11860U, 265U, 16406U,	----
10757	2248U, 16954U, 3353U, 23449U, 19722U, 7215U, 25115U, 12356U,	----
10758	25609U, 11958U, 25203U, 12769U, 26208U, 12018U, 25233U, 12291U,	----
10759	25565U, 12676U, 26101U, 13052U, 26461U, 14698U, 25617U, 12516U,	----
10760	25896U, 12881U, 26290U, 15417U, 6930U, 24587U, 7802U, 12527U,	----
10761	14823U, 25907U, 12892U, 15081U, 26301U, 12497U, 14804U, 25877U,	----
10762	12862U, 15062U, 26271U, 15855U, 18968U, 11024U, 13102U, 15280U,	----
10763	26520U, 10603U, 12270U, 14677U, 25520U, 10384U, 11918U, 14502U,	----
10764	25173U, 10645U, 12465U, 14788U, 25756U, 23268U, 10830U, 12822U,	----
10765	15039U, 26231U, 24937U, 10392U, 12026U, 14510U, 25241U, 20365U,	----
10766	19672U, 7182U, 15568U, 15595U, 22985U, 17477U, 3314U, 5548U,	----
10767	5786U, 6039U, 17496U, 19679U, 9899U, 2024U, 19570U, 19642U,	----
10768	26769U, 20703U, 18784U, 11084U, 2087U, 5872U, 11063U, 2081U,	----
10769	5853U, 22982U, 17469U, 3309U, 22530U, 17337U, 5537U, 7085U,	----
10770	9893U, 2016U, 8043U, 8078U, 19564U, 18770U, 4865U, 3905U,	----
10771	4798U, 4790U, 5004U, 4836U, 9907U, 2034U, 13176U, 18026U,	----
10772	17516U, 26774U, 20711U, 7822U, 17685U, 5800U, 27863U, 3848U,	----
10773	13552U, 18172U, 20828U, 11602U, 82U, 1948U, 5489U, 450U,	----
10774	2490U, 1155U, 5407U, 8011U, 1913U, 10422U, 12104U, 14540U,	----
10775	25360U, 15679U, 11224U, 22749U, 162U, 1962U, 10371U, 11905U,	----
10776	14489U, 25160U, 27947U, 3867U, 20881U, 13893U, 2828U, 13327U,	----
10777	18082U, 17545U, 26725U, 20696U, 18246U, 27885U, 3854U, 13557U,	----
10778	18180U, 20851U, 17393U, 5632U, 15852U, 3255U, 8062U, 11605U,	----
10779	8100U, 13362U, 18096U, 18962U, 6967U, 8124U, 9838U, 5768U,	----
10780	8071U, 6921U, 174U, 1978U, 16344U, 27029U, 3702U, 20821U,	----
10781	25013U, 17554U, 3479U, 152U, 16328U, 1177U, 5469U, 8027U,	----
10782	1923U, 22377U, 19188U, 13519U, 18158U, 19130U, 16141U, 3271U,	----
10783	13370U, 18103U, 19011U, 17430U, 5677U, 16859U, 11256U, 6019U,	----
10784	19364U, 23214U, 3341U, 13455U, 18133U, 19628U, 19340U, 11250U,	----
10785	20258U, 26779U, 186U, 16362U, 19688U, 20719U, 20373U, 7923U,	----
10786	27919U, 4274U, 4338U, 4306U, 4355U, 4884U, 4625U, 4510U,	----
10787	4984U, 4641U, 4391U, 4453U, 11541U, 12066U, 6381U, 23577U,	----
10788	7341U, 14740U, 25659U, 24675U, 22510U, 19303U, 20215U, 11008U,	----
10789	13086U, 15264U, 26504U, 294U, 16444U, 2277U, 22398U, 19218U,	----
10790	18011U, 14713U, 25632U, 23472U, 19754U, 15773U, 18892U, 22909U,	----
10791	19500U, 15799U, 18924U, 22935U, 19532U, 11818U, 6267U, 23442U,	----
10792	7203U, 10712U, 12597U, 14893U, 25977U, 10904U, 12962U, 15151U,	----
10793	26371U, 10348U, 11852U, 14466U, 25107U, 13141U, 6733U, 24045U,	----
10794	10791U, 12705U, 15000U, 7742U, 26154U, 10983U, 13070U, 15239U,	----
10795	26479U, 10U, 5345U, 98U, 2184U, 16304U, 5387U, 1166U,	----
10796	5427U, 16U, 16258U, 5355U, 245U, 16380U, 2193U, 16916U,	----
10797	5437U, 22U, 16267U, 15336U, 17383U, 2844U, 22438U, 19230U,	----
10798	18663U, 22088U, 17448U, 3289U, 22473U, 19254U, 19052U, 23161U,	----
10799	11805U, 6255U, 23435U, 7191U, 10694U, 12579U, 14875U, 25959U,	----
10800	10886U, 12944U, 15133U, 26353U, 10331U, 11834U, 14449U, 25089U,	----
10801	12278U, 6477U, 23725U, 10721U, 12606U, 14902U, 7461U, 25995U,	----
10802	10913U, 12971U, 15160U, 26380U, 11765U, 10239U, 17926U, 24682U,	----
10803	7851U, 6246U, 10661U, 12546U, 14842U, 25926U, 10853U, 12911U,	----
10804	15100U, 26320U, 17355U, 5598U, 19112U, 7063U, 24948U, 362U,	----
10805	16533U, 2345U, 15466U, 2980U, 18730U, 23592U, 19829U, 2222U,	----
10806	15444U, 2873U, 23413U, 409U, 16568U, 2392U, 15492U, 3010U,	----
10807	18740U, 23639U, 19858U, 626U, 16798U, 2666U, 15542U, 3184U,	----
10808	18750U, 23952U, 20042U, 2235U, 15455U, 2886U, 23424U, 420U,	----
10809	16582U, 2403U, 15501U, 3021U, 18760U, 23648U, 19870U, 10290U,	----
10810	12058U, 6368U, 23569U, 7328U, 14730U, 25649U, 24663U, 22500U,	----
10811	19290U, 20200U, 11000U, 13078U, 15256U, 26496U, 275U, 16419U,	----
10812	2258U, 22389U, 19206U, 17942U, 14704U, 25623U, 23457U, 19733U,	----
10813	50U, 5377U, 135U, 2213U, 16942U, 16320U, 5397U, 1172U,	----
10814	5459U, 37U, 16287U, 5366U, 255U, 16393U, 2203U, 16929U,	----
10815	5448U, 29U, 16277U, 15368U, 2866U, 22464U, 19242U, 18687U,	----
10816	22257U, 19138U, 22105U, 3296U, 22482U, 19266U, 19069U, 66U,	----
10817	198U, 1195U, 71U, 211U, 1200U, 23190U, 14431U, 24713U,	----
10818	7861U, 6864U, 16044U, 15811U, 18939U, 22947U, 19547U, 15613U,	----
10819	18811U, 22645U, 19400U, 14117U, 18419U, 25828U, 1884U, 14167U,	----
10820	1541U, 26030U, 1899U, 3411U, 14750U, 25669U, 14355U, 18563U,	----
10821	14295U, 1640U, 24347U, 22520U, 19316U, 22491U, 19278U, 20179U,	----
10822	27901U, 20872U, 24733U, 7882U, 11032U, 13117U, 15288U, 26535U,	----
10823	19004U, 6984U, 14035U, 1483U, 14722U, 25641U, 8131U, 14138U,	----
10824	1527U, 4850U, 4977U, 4164U, 3887U, 10356U, 11875U, 14474U,	----
10825	25130U, 10363U, 11882U, 14481U, 25137U, 293U, 16443U, 2276U,	----
10826	23471U, 19753U, 274U, 16418U, 2257U, 23456U, 19732U, 22990U,	----
10827	3321U, 10505U, 19578U, 7129U, 24962U, 17507U, 5723U, 5045U,	----
10828	5086U, 22991U, 17488U, 5713U, 3322U, 10506U, 6903U, 19579U,	----
10829	7130U, 24963U, 27008U, 3689U, 20806U, 5185U, 14025U, 18344U,	----
10830	13478U, 18149U, 6795U, 11016U, 13094U, 15272U, 26512U, 10376U,	----
10831	11910U, 14494U, 25165U, 10823U, 12807U, 15032U, 26216U, 13993U,	----
10832	18311U, 9984U, 17720U, 3373U, 3421U, 22285U, 15642U, 8484U,	----
10833	17608U, 18846U, 22674U, 8534U, 17645U, 19435U, 15786U, 18908U,	----
10834	22922U, 19516U, 15628U, 8469U, 17590U, 18829U, 22660U, 8519U,	----
10835	17627U, 19418U, 13937U, 18279U, 25292U, 20433U, 13912U, 18263U,	----
10836	25321U, 20448U, 13925U, 1425U, 25277U, 1786U, 25304U, 1806U,	----
10837	13618U, 13303U, 18057U, 20687U, 18196U, 6806U, 8116U, 11664U,	----
10838	1400U, 3392U, 3430U, 10225U, 17906U, 22351U, 19170U, 23208U,	----
10839	3333U, 19619U, 7171U, 7147U, 483U, 16633U, 2523U, 17128U,	----
10840	23757U, 19924U, 14268U, 18536U, 10207U, 17882U, 14009U, 18333U,	----
10841	10000U, 17742U, 12815U, 6650U, 23929U, 7634U, 23167U, 24931U,	----
10842	20356U, 19592U, 2445U, 6420U, 23688U, 7404U, 692U, 2726U,	----
10843	6689U, 20422U, 24008U, 20085U, 7685U, 616U, 16785U, 2656U,	----
10844	17268U, 23944U, 20031U, 4805U, 4181U, 8465U, 11348U, 10756U,	----
10845	12650U, 14955U, 26075U, 10959U, 13026U, 15215U, 26435U, 10236U,	----
10846	17329U, 5517U, 2039U, 13193U, 18033U, 17920U, 5808U, 11269U,	----
10847	2102U, 8054U, 11450U, 8093U, 13246U, 18040U, 17972U, 6050U,	----
10848	8087U, 11786U, 22215U, 17458U, 5699U, 19085U, 7052U, 8146U,	----
10849	87U, 1955U, 5503U, 462U, 2502U, 1160U, 5417U, 8019U,	----
10850	1918U, 24829U, 20283U, 15683U, 22753U, 168U, 1970U, 9871U,	----
10851	1994U, 17671U, 13884U, 2822U, 18239U, 26870U, 3524U, 13167U,	----
10852	6758U, 7973U, 24060U, 7767U, 26837U, 3515U, 13152U, 6744U,	----
10853	7952U, 24051U, 7753U, 12214U, 6394U, 23657U, 7366U, 22632U,	----
10854	27002U, 14427U, 17365U, 5610U, 2833U, 13331U, 18089U, 10401U,	----
10855	14519U, 25264U, 22093U, 24909U, 20326U, 19060U, 14259U, 18524U,	----
10856	10198U, 17870U, 14207U, 18485U, 26144U, 20663U, 14001U, 18322U,	----
10857	9992U, 17731U, 14128U, 18433U, 25986U, 20604U, 14250U, 18512U,	----
10858	10189U, 1386U, 14106U, 18405U, 10090U, 1337U, 25801U, 20551U,	----
10859	13904U, 18252U, 9910U, 1213U, 14074U, 18392U, 10058U, 1290U,	----
10860	25763U, 20527U, 14277U, 1612U, 10216U, 17894U, 14017U, 1470U,	----
10861	10008U, 17753U, 18595U, 6856U, 13335U, 6783U, 10421U, 12103U,	----
10862	14539U, 25359U, 10370U, 11904U, 14488U, 25159U, 15973U, 17412U,	----
10863	5655U, 1030U, 3584U, 10451U, 12118U, 14554U, 25374U, 24883U,	----
10864	20299U, 10583U, 12227U, 14657U, 18990U, 6975U, 25477U, 24332U,	----
10865	3462U, 20159U, 27012U, 3695U, 20813U, 27975U, 3879U, 20894U,	----
10866	27889U, 3860U, 20858U, 13400U, 26997U, 10528U, 12181U, 14617U,	----
10867	25437U, 10808U, 12722U, 15017U, 26171U, 8551U, 10414U, 12096U,	----
10868	14532U, 25352U, 10481U, 12148U, 14584U, 25404U, 10616U, 12394U,	----
10869	14759U, 25678U, 24784U, 20265U, 10317U, 11812U, 14435U, 17664U,	----
10870	25074U, 16004U, 17421U, 5666U, 10458U, 12125U, 14561U, 25381U,	----
10871	10497U, 12164U, 14600U, 25420U, 10630U, 12414U, 14773U, 25698U,	----
10872	24889U, 20307U, 10589U, 12249U, 14663U, 18997U, 25499U, 22278U,	----
10873	19148U, 7074U, 10839U, 12848U, 15048U, 26257U, 10242U, 13969U,	----
10874	1442U, 14084U, 1495U, 25772U, 1854U, 25336U, 1828U, 14042U,	----
10875	18357U, 14147U, 18446U, 26012U, 20616U, 10948U, 13015U, 15204U,	----
10876	26424U, 10772U, 12686U, 14971U, 26125U, 10738U, 12632U, 14937U,	----
10877	26057U, 10930U, 12997U, 15186U, 26406U, 17525U, 5734U, 9960U,	----
10878	1244U, 10068U, 1305U, 7831U, 14234U, 1586U, 10173U, 17848U,	----
10879	14187U, 1556U, 10111U, 17793U, 10545U, 12198U, 14634U, 25454U,	----
10880	11001U, 13079U, 15257U, 26497U, 17929U, 5816U, 27868U, 20835U,	----
10881	180U, 1986U, 16353U, 25023U, 17562U, 5758U, 3496U, 157U,	----
10882	16336U, 1182U, 5479U, 8035U, 1928U, 22383U, 19197U, 13523U,	----
10883	18165U, 16145U, 3277U, 13375U, 18111U, 19018U, 17439U, 5688U,	----
10884	16868U, 19371U, 23218U, 3347U, 13460U, 18141U, 19635U, 19348U,	----
10885	7101U, 192U, 16371U, 20379U, 7931U, 11202U, 15306U, 18626U,	----
10886	6873U, 17950U, 5973U, 15863U, 18979U, 4829U, 4192U, 4290U,	----
10887	4996U, 5012U, 4322U, 4260U, 5151U, 5065U, 4906U, 4534U,	----
10888	4918U, 4561U, 5096U, 4174U, 5130U, 4267U, 5162U, 5221U,	----
10889	4407U, 4466U, 22636U, 15379U, 18695U, 19385U, 13317U, 15315U,	----
10890	24718U, 20232U, 18641U, 24697U, 20224U, 18066U, 24901U, 13645U,	----
10891	18204U, 20315U, 22251U, 19121U, 22869U, 19491U, 15429U, 18720U,	----
10892	23201U, 19609U, 24894U, 13637U, 6816U, 7911U, 22221U, 19094U,	----
10893	22640U, 19392U, 15423U, 18711U, 23195U, 19600U, 24336U, 15398U,	----
10894	20241U, 18703U, 24766U, 20250U, 20166U, 13404U, 15320U, 18649U,	----
10895	18126U, 2433U, 6405U, 23678U, 7389U, 680U, 2714U, 6674U,	----
10896	20411U, 23998U, 20072U, 7670U, 24724U, 24859U, 20291U, 24731U,	----
10897	61U, 24744U, 10400U, 12074U, 14518U, 25263U, 24251U, 20151U,	----
10898	7792U, 22357U, 19179U, 7159U, 13871U, 18231U, 6846U, 23052U,	----
10899	17487U, 5712U, 3327U, 10512U, 6902U, 19585U, 7138U, 24968U,	----
10900	27007U, 3688U, 20805U, 5196U, 11599U,	----
10901	};	----
10902		----
10903	static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10904	II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10905	}	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10906		----
10907	} // end namespace llvm	----
10908	#endif // GET_INSTRINFO_MC_DESC	----
10909		----
10910	#ifdef GET_INSTRINFO_HEADER	----
10911	#undef GET_INSTRINFO_HEADER	----
10912	namespace llvm {	----
10913	struct MipsGenInstrInfo : public TargetInstrInfo {	----
10914	explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);	----
10915	~MipsGenInstrInfo() override = default;	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10916		----
10917	};	----
10918	} // end namespace llvm	----
10919	#endif // GET_INSTRINFO_HEADER	----
10920		----
10921	#ifdef GET_INSTRINFO_HELPER_DECLS	----
10922	#undef GET_INSTRINFO_HELPER_DECLS	----
10923		----
10924		----
10925	#endif // GET_INSTRINFO_HELPER_DECLS	----
10926		----
10927	#ifdef GET_INSTRINFO_HELPERS	----
10928	#undef GET_INSTRINFO_HELPERS	----
10929		----
10930	#endif // GET_INSTRINFO_HELPERS	----
10931		----
10932	#ifdef GET_INSTRINFO_CTOR_DTOR	----
10933	#undef GET_INSTRINFO_CTOR_DTOR	----
10934	namespace llvm {	----
10935	extern const MipsInstrTable MipsDescs;	----
10936	extern const unsigned MipsInstrNameIndices[];	----
10937	extern const char MipsInstrNameData[];	----
10938	MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10939	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10940	InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10941	}	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
10942	} // end namespace llvm	----
10943	#endif // GET_INSTRINFO_CTOR_DTOR	----
10944		----
10945	#ifdef GET_INSTRINFO_OPERAND_ENUM	----
10946	#undef GET_INSTRINFO_OPERAND_ENUM	----
10947	namespace llvm {	----
10948	namespace Mips {	----
10949	namespace OpName {	----
10950	enum {	----
10951	OPERAND_LAST	----
10952	};	----
10953	} // end namespace OpName	----
10954	} // end namespace Mips	----
10955	} // end namespace llvm	----
10956	#endif //GET_INSTRINFO_OPERAND_ENUM	----
10957		----
10958	#ifdef GET_INSTRINFO_NAMED_OPS	----
10959	#undef GET_INSTRINFO_NAMED_OPS	----
10960	namespace llvm {	----
10961	namespace Mips {	----
10962	LLVM_READONLY	----
10963	int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {	----
10964	return -1;	----
10965	}	----
10966	} // end namespace Mips	----
10967	} // end namespace llvm	----
10968	#endif //GET_INSTRINFO_NAMED_OPS	----
10969		----
10970	#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM	----
10971	#undef GET_INSTRINFO_OPERAND_TYPES_ENUM	----
10972	namespace llvm {	----
10973	namespace Mips {	----
10974	namespace OpTypes {	----
10975	enum OperandType {	----
10976	InvertedImOperand = 0,	----
10977	InvertedImOperand64 = 1,	----
10978	PtrRC = 2,	----
10979	brtarget = 3,	----
10980	brtarget1SImm16 = 4,	----
10981	brtarget7_mm = 5,	----
10982	brtarget10_mm = 6,	----
10983	brtarget21 = 7,	----
10984	brtarget21_mm = 8,	----
10985	brtarget26 = 9,	----
10986	brtarget26_mm = 10,	----
10987	brtarget_lsl2_mm = 11,	----
10988	brtarget_mm = 12,	----
10989	brtargetr6 = 13,	----
10990	calloffset16 = 14,	----
10991	calltarget = 15,	----
10992	calltarget_mm = 16,	----
10993	condcode = 17,	----
10994	cpinst_operand = 18,	----
10995	f32imm = 19,	----
10996	f64imm = 20,	----
10997	i1imm = 21,	----
10998	i8imm = 22,	----
10999	i16imm = 23,	----
11000	i32imm = 24,	----
11001	i64imm = 25,	----
11002	imm64 = 26,	----
11003	jmpoffset16 = 27,	----
11004	jmptarget = 28,	----
11005	jmptarget_mm = 29,	----
11006	li16_imm = 30,	----
11007	mem = 31,	----
11008	mem16 = 32,	----
11009	mem16_ea = 33,	----
11010	mem16sp = 34,	----
11011	mem_ea = 35,	----
11012	mem_mm_4 = 36,	----
11013	mem_mm_4_lsl1 = 37,	----
11014	mem_mm_4_lsl2 = 38,	----
11015	mem_mm_4sp = 39,	----
11016	mem_mm_9 = 40,	----
11017	mem_mm_11 = 41,	----
11018	mem_mm_12 = 42,	----
11019	mem_mm_16 = 43,	----
11020	mem_mm_gp_simm7_lsl2 = 44,	----
11021	mem_mm_sp_imm5_lsl2 = 45,	----
11022	mem_msa = 46,	----
11023	mem_simm9 = 47,	----
11024	mem_simm9_exp = 48,	----
11025	mem_simm10 = 49,	----
11026	mem_simm10_lsl1 = 50,	----
11027	mem_simm10_lsl2 = 51,	----
11028	mem_simm10_lsl3 = 52,	----
11029	mem_simm11 = 53,	----
11030	mem_simm12 = 54,	----
11031	mem_simm16 = 55,	----
11032	mem_simmptr = 56,	----
11033	pcrel16 = 57,	----
11034	ptype0 = 58,	----
11035	ptype1 = 59,	----
11036	ptype2 = 60,	----
11037	ptype3 = 61,	----
11038	ptype4 = 62,	----
11039	ptype5 = 63,	----
11040	reglist = 64,	----
11041	reglist16 = 65,	----
11042	simm3_lsa2 = 66,	----
11043	simm4 = 67,	----
11044	simm5 = 68,	----
11045	simm6 = 69,	----
11046	simm7_lsl2 = 70,	----
11047	simm9 = 71,	----
11048	simm9_addiusp = 72,	----
11049	simm10 = 73,	----
11050	simm10_64 = 74,	----
11051	simm10_lsl1 = 75,	----
11052	simm10_lsl2 = 76,	----
11053	simm10_lsl3 = 77,	----
11054	simm11 = 78,	----
11055	simm12 = 79,	----
11056	simm16 = 80,	----
11057	simm16_64 = 81,	----
11058	simm16_relaxed = 82,	----
11059	simm18_lsl3 = 83,	----
11060	simm19_lsl2 = 84,	----
11061	simm23_lsl2 = 85,	----
11062	simm32 = 86,	----
11063	simm32_relaxed = 87,	----
11064	size_ins = 88,	----
11065	type0 = 89,	----
11066	type1 = 90,	----
11067	type2 = 91,	----
11068	type3 = 92,	----
11069	type4 = 93,	----
11070	type5 = 94,	----
11071	uimm1 = 95,	----
11072	uimm1_ptr = 96,	----
11073	uimm2 = 97,	----
11074	uimm2_plus1 = 98,	----
11075	uimm2_ptr = 99,	----
11076	uimm3 = 100,	----
11077	uimm3_ptr = 101,	----
11078	uimm3_shift = 102,	----
11079	uimm4 = 103,	----
11080	uimm4_andi = 104,	----
11081	uimm4_ptr = 105,	----
11082	uimm5 = 106,	----
11083	uimm5_64 = 107,	----
11084	uimm5_64_report_uimm6 = 108,	----
11085	uimm5_inssize_plus1 = 109,	----
11086	uimm5_lsl2 = 110,	----
11087	uimm5_plus1 = 111,	----
11088	uimm5_plus1_report_uimm6 = 112,	----
11089	uimm5_plus32 = 113,	----
11090	uimm5_plus32_normalize = 114,	----
11091	uimm5_plus32_normalize_64 = 115,	----
11092	uimm5_plus33 = 116,	----
11093	uimm5_report_uimm6 = 117,	----
11094	uimm6 = 118,	----
11095	uimm6_lsl2 = 119,	----
11096	uimm7 = 120,	----
11097	uimm8 = 121,	----
11098	uimm10 = 122,	----
11099	uimm16 = 123,	----
11100	uimm16_64 = 124,	----
11101	uimm16_64_relaxed = 125,	----
11102	uimm16_altrelaxed = 126,	----
11103	uimm16_relaxed = 127,	----
11104	uimm20 = 128,	----
11105	uimm26 = 129,	----
11106	uimm32_coerced = 130,	----
11107	uimm_range_2_64 = 131,	----
11108	uimmz = 132,	----
11109	untyped_imm_0 = 133,	----
11110	vsplat_simm5 = 134,	----
11111	vsplat_simm10 = 135,	----
11112	vsplat_uimm1 = 136,	----
11113	vsplat_uimm2 = 137,	----
11114	vsplat_uimm3 = 138,	----
11115	vsplat_uimm4 = 139,	----
11116	vsplat_uimm5 = 140,	----
11117	vsplat_uimm6 = 141,	----
11118	vsplat_uimm8 = 142,	----
11119	ACC64DSPOpnd = 143,	----
11120	AFGR64Opnd = 144,	----
11121	CCROpnd = 145,	----
11122	COP0Opnd = 146,	----
11123	COP2Opnd = 147,	----
11124	COP3Opnd = 148,	----
11125	DSPROpnd = 149,	----
11126	FCCRegsOpnd = 150,	----
11127	FGR32Opnd = 151,	----
11128	FGR64Opnd = 152,	----
11129	FGRCCOpnd = 153,	----
11130	GPR32NonZeroOpnd = 154,	----
11131	GPR32Opnd = 155,	----
11132	GPR32ZeroOpnd = 156,	----
11133	GPR64Opnd = 157,	----
11134	GPRMM16Opnd = 158,	----
11135	GPRMM16OpndMoveP = 159,	----
11136	GPRMM16OpndMovePPairFirst = 160,	----
11137	GPRMM16OpndMovePPairSecond = 161,	----
11138	GPRMM16OpndZero = 162,	----
11139	HI32DSPOpnd = 163,	----
11140	HWRegsOpnd = 164,	----
11141	LO32DSPOpnd = 165,	----
11142	MSA128BOpnd = 166,	----
11143	MSA128CROpnd = 167,	----
11144	MSA128DOpnd = 168,	----
11145	MSA128F16Opnd = 169,	----
11146	MSA128HOpnd = 170,	----
11147	MSA128WOpnd = 171,	----
11148	StrictlyAFGR64Opnd = 172,	----
11149	StrictlyFGR32Opnd = 173,	----
11150	StrictlyFGR64Opnd = 174,	----
11151	ACC64 = 175,	----
11152	ACC64DSP = 176,	----
11153	ACC128 = 177,	----
11154	AFGR64 = 178,	----
11155	CCR = 179,	----
11156	COP0 = 180,	----
11157	COP2 = 181,	----
11158	COP3 = 182,	----
11159	CPU16Regs = 183,	----
11160	CPU16RegsPlusSP = 184,	----
11161	CPURAReg = 185,	----
11162	CPUSPReg = 186,	----
11163	DSPCC = 187,	----
11164	DSPR = 188,	----
11165	FCC = 189,	----
11166	FGR32 = 190,	----
11167	FGR64 = 191,	----
11168	FGRCC = 192,	----
11169	GP32 = 193,	----
11170	GP64 = 194,	----
11171	GPR32 = 195,	----
11172	GPR32NONZERO = 196,	----
11173	GPR32ZERO = 197,	----
11174	GPR64 = 198,	----
11175	GPRMM16 = 199,	----
11176	GPRMM16MoveP = 200,	----
11177	GPRMM16MovePPairFirst = 201,	----
11178	GPRMM16MovePPairSecond = 202,	----
11179	GPRMM16Zero = 203,	----
11180	HI32 = 204,	----
11181	HI32DSP = 205,	----
11182	HI64 = 206,	----
11183	HWRegs = 207,	----
11184	LO32 = 208,	----
11185	LO32DSP = 209,	----
11186	LO64 = 210,	----
11187	MSA128B = 211,	----
11188	MSA128D = 212,	----
11189	MSA128F16 = 213,	----
11190	MSA128H = 214,	----
11191	MSA128W = 215,	----
11192	MSA128WEvens = 216,	----
11193	MSACtrl = 217,	----
11194	OCTEON_MPL = 218,	----
11195	OCTEON_P = 219,	----
11196	SP32 = 220,	----
11197	SP64 = 221,	----
11198	OPERAND_TYPE_LIST_END	----
11199	};	----
11200	} // end namespace OpTypes	----
11201	} // end namespace Mips	----
11202	} // end namespace llvm	----
11203	#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM	----
11204		----
11205	#ifdef GET_INSTRINFO_OPERAND_TYPE	----
11206	#undef GET_INSTRINFO_OPERAND_TYPE	----
11207	namespace llvm {	----
11208	namespace Mips {	----
11209	LLVM_READONLY	----
11210	static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {	----
11211	static const uint16_t Offsets[] = {	----
11212	/* PHI */	----
11213	0,	----
11214	/* INLINEASM */	----
11215	1,	----
11216	/* INLINEASM_BR */	----
11217	1,	----
11218	/* CFI_INSTRUCTION */	----
11219	1,	----
11220	/* EH_LABEL */	----
11221	2,	----
11222	/* GC_LABEL */	----
11223	3,	----
11224	/* ANNOTATION_LABEL */	----
11225	4,	----
11226	/* KILL */	----
11227	5,	----
11228	/* EXTRACT_SUBREG */	----
11229	5,	----
11230	/* INSERT_SUBREG */	----
11231	8,	----
11232	/* IMPLICIT_DEF */	----
11233	12,	----
11234	/* SUBREG_TO_REG */	----
11235	13,	----
11236	/* COPY_TO_REGCLASS */	----
11237	17,	----
11238	/* DBG_VALUE */	----
11239	20,	----
11240	/* DBG_VALUE_LIST */	----
11241	20,	----
11242	/* DBG_INSTR_REF */	----
11243	20,	----
11244	/* DBG_PHI */	----
11245	20,	----
11246	/* DBG_LABEL */	----
11247	20,	----
11248	/* REG_SEQUENCE */	----
11249	21,	----
11250	/* COPY */	----
11251	23,	----
11252	/* BUNDLE */	----
11253	25,	----
11254	/* LIFETIME_START */	----
11255	25,	----
11256	/* LIFETIME_END */	----
11257	26,	----
11258	/* PSEUDO_PROBE */	----
11259	27,	----
11260	/* ARITH_FENCE */	----
11261	31,	----
11262	/* STACKMAP */	----
11263	33,	----
11264	/* FENTRY_CALL */	----
11265	35,	----
11266	/* PATCHPOINT */	----
11267	35,	----
11268	/* LOAD_STACK_GUARD */	----
11269	41,	----
11270	/* PREALLOCATED_SETUP */	----
11271	42,	----
11272	/* PREALLOCATED_ARG */	----
11273	43,	----
11274	/* STATEPOINT */	----
11275	46,	----
11276	/* LOCAL_ESCAPE */	----
11277	46,	----
11278	/* FAULTING_OP */	----
11279	48,	----
11280	/* PATCHABLE_OP */	----
11281	49,	----
11282	/* PATCHABLE_FUNCTION_ENTER */	----
11283	49,	----
11284	/* PATCHABLE_RET */	----
11285	49,	----
11286	/* PATCHABLE_FUNCTION_EXIT */	----
11287	49,	----
11288	/* PATCHABLE_TAIL_CALL */	----
11289	49,	----
11290	/* PATCHABLE_EVENT_CALL */	----
11291	49,	----
11292	/* PATCHABLE_TYPED_EVENT_CALL */	----
11293	51,	----
11294	/* ICALL_BRANCH_FUNNEL */	----
11295	54,	----
11296	/* MEMBARRIER */	----
11297	54,	----
11298	/* G_ASSERT_SEXT */	----
11299	54,	----
11300	/* G_ASSERT_ZEXT */	----
11301	57,	----
11302	/* G_ASSERT_ALIGN */	----
11303	60,	----
11304	/* G_ADD */	----
11305	63,	----
11306	/* G_SUB */	----
11307	66,	----
11308	/* G_MUL */	----
11309	69,	----
11310	/* G_SDIV */	----
11311	72,	----
11312	/* G_UDIV */	----
11313	75,	----
11314	/* G_SREM */	----
11315	78,	----
11316	/* G_UREM */	----
11317	81,	----
11318	/* G_SDIVREM */	----
11319	84,	----
11320	/* G_UDIVREM */	----
11321	88,	----
11322	/* G_AND */	----
11323	92,	----
11324	/* G_OR */	----
11325	95,	----
11326	/* G_XOR */	----
11327	98,	----
11328	/* G_IMPLICIT_DEF */	----
11329	101,	----
11330	/* G_PHI */	----
11331	102,	----
11332	/* G_FRAME_INDEX */	----
11333	103,	----
11334	/* G_GLOBAL_VALUE */	----
11335	105,	----
11336	/* G_CONSTANT_POOL */	----
11337	107,	----
11338	/* G_EXTRACT */	----
11339	109,	----
11340	/* G_UNMERGE_VALUES */	----
11341	112,	----
11342	/* G_INSERT */	----
11343	114,	----
11344	/* G_MERGE_VALUES */	----
11345	118,	----
11346	/* G_BUILD_VECTOR */	----
11347	120,	----
11348	/* G_BUILD_VECTOR_TRUNC */	----
11349	122,	----
11350	/* G_CONCAT_VECTORS */	----
11351	124,	----
11352	/* G_PTRTOINT */	----
11353	126,	----
11354	/* G_INTTOPTR */	----
11355	128,	----
11356	/* G_BITCAST */	----
11357	130,	----
11358	/* G_FREEZE */	----
11359	132,	----
11360	/* G_CONSTANT_FOLD_BARRIER */	----
11361	134,	----
11362	/* G_INTRINSIC_FPTRUNC_ROUND */	----
11363	136,	----
11364	/* G_INTRINSIC_TRUNC */	----
11365	139,	----
11366	/* G_INTRINSIC_ROUND */	----
11367	141,	----
11368	/* G_INTRINSIC_LRINT */	----
11369	143,	----
11370	/* G_INTRINSIC_ROUNDEVEN */	----
11371	145,	----
11372	/* G_READCYCLECOUNTER */	----
11373	147,	----
11374	/* G_LOAD */	----
11375	148,	----
11376	/* G_SEXTLOAD */	----
11377	150,	----
11378	/* G_ZEXTLOAD */	----
11379	152,	----
11380	/* G_INDEXED_LOAD */	----
11381	154,	----
11382	/* G_INDEXED_SEXTLOAD */	----
11383	159,	----
11384	/* G_INDEXED_ZEXTLOAD */	----
11385	164,	----
11386	/* G_STORE */	----
11387	169,	----
11388	/* G_INDEXED_STORE */	----
11389	171,	----
11390	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	----
11391	176,	----
11392	/* G_ATOMIC_CMPXCHG */	----
11393	181,	----
11394	/* G_ATOMICRMW_XCHG */	----
11395	185,	----
11396	/* G_ATOMICRMW_ADD */	----
11397	188,	----
11398	/* G_ATOMICRMW_SUB */	----
11399	191,	----
11400	/* G_ATOMICRMW_AND */	----
11401	194,	----
11402	/* G_ATOMICRMW_NAND */	----
11403	197,	----
11404	/* G_ATOMICRMW_OR */	----
11405	200,	----
11406	/* G_ATOMICRMW_XOR */	----
11407	203,	----
11408	/* G_ATOMICRMW_MAX */	----
11409	206,	----
11410	/* G_ATOMICRMW_MIN */	----
11411	209,	----
11412	/* G_ATOMICRMW_UMAX */	----
11413	212,	----
11414	/* G_ATOMICRMW_UMIN */	----
11415	215,	----
11416	/* G_ATOMICRMW_FADD */	----
11417	218,	----
11418	/* G_ATOMICRMW_FSUB */	----
11419	221,	----
11420	/* G_ATOMICRMW_FMAX */	----
11421	224,	----
11422	/* G_ATOMICRMW_FMIN */	----
11423	227,	----
11424	/* G_ATOMICRMW_UINC_WRAP */	----
11425	230,	----
11426	/* G_ATOMICRMW_UDEC_WRAP */	----
11427	233,	----
11428	/* G_FENCE */	----
11429	236,	----
11430	/* G_BRCOND */	----
11431	238,	----
11432	/* G_BRINDIRECT */	----
11433	240,	----
11434	/* G_INVOKE_REGION_START */	----
11435	241,	----
11436	/* G_INTRINSIC */	----
11437	241,	----
11438	/* G_INTRINSIC_W_SIDE_EFFECTS */	----
11439	242,	----
11440	/* G_ANYEXT */	----
11441	243,	----
11442	/* G_TRUNC */	----
11443	245,	----
11444	/* G_CONSTANT */	----
11445	247,	----
11446	/* G_FCONSTANT */	----
11447	249,	----
11448	/* G_VASTART */	----
11449	251,	----
11450	/* G_VAARG */	----
11451	252,	----
11452	/* G_SEXT */	----
11453	255,	----
11454	/* G_SEXT_INREG */	----
11455	257,	----
11456	/* G_ZEXT */	----
11457	260,	----
11458	/* G_SHL */	----
11459	262,	----
11460	/* G_LSHR */	----
11461	265,	----
11462	/* G_ASHR */	----
11463	268,	----
11464	/* G_FSHL */	----
11465	271,	----
11466	/* G_FSHR */	----
11467	275,	----
11468	/* G_ROTR */	----
11469	279,	----
11470	/* G_ROTL */	----
11471	282,	----
11472	/* G_ICMP */	----
11473	285,	----
11474	/* G_FCMP */	----
11475	289,	----
11476	/* G_SELECT */	----
11477	293,	----
11478	/* G_UADDO */	----
11479	297,	----
11480	/* G_UADDE */	----
11481	301,	----
11482	/* G_USUBO */	----
11483	306,	----
11484	/* G_USUBE */	----
11485	310,	----
11486	/* G_SADDO */	----
11487	315,	----
11488	/* G_SADDE */	----
11489	319,	----
11490	/* G_SSUBO */	----
11491	324,	----
11492	/* G_SSUBE */	----
11493	328,	----
11494	/* G_UMULO */	----
11495	333,	----
11496	/* G_SMULO */	----
11497	337,	----
11498	/* G_UMULH */	----
11499	341,	----
11500	/* G_SMULH */	----
11501	344,	----
11502	/* G_UADDSAT */	----
11503	347,	----
11504	/* G_SADDSAT */	----
11505	350,	----
11506	/* G_USUBSAT */	----
11507	353,	----
11508	/* G_SSUBSAT */	----
11509	356,	----
11510	/* G_USHLSAT */	----
11511	359,	----
11512	/* G_SSHLSAT */	----
11513	362,	----
11514	/* G_SMULFIX */	----
11515	365,	----
11516	/* G_UMULFIX */	----
11517	369,	----
11518	/* G_SMULFIXSAT */	----
11519	373,	----
11520	/* G_UMULFIXSAT */	----
11521	377,	----
11522	/* G_SDIVFIX */	----
11523	381,	----
11524	/* G_UDIVFIX */	----
11525	385,	----
11526	/* G_SDIVFIXSAT */	----
11527	389,	----
11528	/* G_UDIVFIXSAT */	----
11529	393,	----
11530	/* G_FADD */	----
11531	397,	----
11532	/* G_FSUB */	----
11533	400,	----
11534	/* G_FMUL */	----
11535	403,	----
11536	/* G_FMA */	----
11537	406,	----
11538	/* G_FMAD */	----
11539	410,	----
11540	/* G_FDIV */	----
11541	414,	----
11542	/* G_FREM */	----
11543	417,	----
11544	/* G_FPOW */	----
11545	420,	----
11546	/* G_FPOWI */	----
11547	423,	----
11548	/* G_FEXP */	----
11549	426,	----
11550	/* G_FEXP2 */	----
11551	428,	----
11552	/* G_FLOG */	----
11553	430,	----
11554	/* G_FLOG2 */	----
11555	432,	----
11556	/* G_FLOG10 */	----
11557	434,	----
11558	/* G_FLDEXP */	----
11559	436,	----
11560	/* G_FFREXP */	----
11561	439,	----
11562	/* G_FNEG */	----
11563	442,	----
11564	/* G_FPEXT */	----
11565	444,	----
11566	/* G_FPTRUNC */	----
11567	446,	----
11568	/* G_FPTOSI */	----
11569	448,	----
11570	/* G_FPTOUI */	----
11571	450,	----
11572	/* G_SITOFP */	----
11573	452,	----
11574	/* G_UITOFP */	----
11575	454,	----
11576	/* G_FABS */	----
11577	456,	----
11578	/* G_FCOPYSIGN */	----
11579	458,	----
11580	/* G_IS_FPCLASS */	----
11581	461,	----
11582	/* G_FCANONICALIZE */	----
11583	464,	----
11584	/* G_FMINNUM */	----
11585	466,	----
11586	/* G_FMAXNUM */	----
11587	469,	----
11588	/* G_FMINNUM_IEEE */	----
11589	472,	----
11590	/* G_FMAXNUM_IEEE */	----
11591	475,	----
11592	/* G_FMINIMUM */	----
11593	478,	----
11594	/* G_FMAXIMUM */	----
11595	481,	----
11596	/* G_PTR_ADD */	----
11597	484,	----
11598	/* G_PTRMASK */	----
11599	487,	----
11600	/* G_SMIN */	----
11601	490,	----
11602	/* G_SMAX */	----
11603	493,	----
11604	/* G_UMIN */	----
11605	496,	----
11606	/* G_UMAX */	----
11607	499,	----
11608	/* G_ABS */	----
11609	502,	----
11610	/* G_LROUND */	----
11611	504,	----
11612	/* G_LLROUND */	----
11613	506,	----
11614	/* G_BR */	----
11615	508,	----
11616	/* G_BRJT */	----
11617	509,	----
11618	/* G_INSERT_VECTOR_ELT */	----
11619	512,	----
11620	/* G_EXTRACT_VECTOR_ELT */	----
11621	516,	----
11622	/* G_SHUFFLE_VECTOR */	----
11623	519,	----
11624	/* G_CTTZ */	----
11625	523,	----
11626	/* G_CTTZ_ZERO_UNDEF */	----
11627	525,	----
11628	/* G_CTLZ */	----
11629	527,	----
11630	/* G_CTLZ_ZERO_UNDEF */	----
11631	529,	----
11632	/* G_CTPOP */	----
11633	531,	----
11634	/* G_BSWAP */	----
11635	533,	----
11636	/* G_BITREVERSE */	----
11637	535,	----
11638	/* G_FCEIL */	----
11639	537,	----
11640	/* G_FCOS */	----
11641	539,	----
11642	/* G_FSIN */	----
11643	541,	----
11644	/* G_FSQRT */	----
11645	543,	----
11646	/* G_FFLOOR */	----
11647	545,	----
11648	/* G_FRINT */	----
11649	547,	----
11650	/* G_FNEARBYINT */	----
11651	549,	----
11652	/* G_ADDRSPACE_CAST */	----
11653	551,	----
11654	/* G_BLOCK_ADDR */	----
11655	553,	----
11656	/* G_JUMP_TABLE */	----
11657	555,	----
11658	/* G_DYN_STACKALLOC */	----
11659	557,	----
11660	/* G_STRICT_FADD */	----
11661	560,	----
11662	/* G_STRICT_FSUB */	----
11663	563,	----
11664	/* G_STRICT_FMUL */	----
11665	566,	----
11666	/* G_STRICT_FDIV */	----
11667	569,	----
11668	/* G_STRICT_FREM */	----
11669	572,	----
11670	/* G_STRICT_FMA */	----
11671	575,	----
11672	/* G_STRICT_FSQRT */	----
11673	579,	----
11674	/* G_STRICT_FLDEXP */	----
11675	581,	----
11676	/* G_READ_REGISTER */	----
11677	584,	----
11678	/* G_WRITE_REGISTER */	----
11679	586,	----
11680	/* G_MEMCPY */	----
11681	588,	----
11682	/* G_MEMCPY_INLINE */	----
11683	592,	----
11684	/* G_MEMMOVE */	----
11685	595,	----
11686	/* G_MEMSET */	----
11687	599,	----
11688	/* G_BZERO */	----
11689	603,	----
11690	/* G_VECREDUCE_SEQ_FADD */	----
11691	606,	----
11692	/* G_VECREDUCE_SEQ_FMUL */	----
11693	609,	----
11694	/* G_VECREDUCE_FADD */	----
11695	612,	----
11696	/* G_VECREDUCE_FMUL */	----
11697	614,	----
11698	/* G_VECREDUCE_FMAX */	----
11699	616,	----
11700	/* G_VECREDUCE_FMIN */	----
11701	618,	----
11702	/* G_VECREDUCE_ADD */	----
11703	620,	----
11704	/* G_VECREDUCE_MUL */	----
11705	622,	----
11706	/* G_VECREDUCE_AND */	----
11707	624,	----
11708	/* G_VECREDUCE_OR */	----
11709	626,	----
11710	/* G_VECREDUCE_XOR */	----
11711	628,	----
11712	/* G_VECREDUCE_SMAX */	----
11713	630,	----
11714	/* G_VECREDUCE_SMIN */	----
11715	632,	----
11716	/* G_VECREDUCE_UMAX */	----
11717	634,	----
11718	/* G_VECREDUCE_UMIN */	----
11719	636,	----
11720	/* G_SBFX */	----
11721	638,	----
11722	/* G_UBFX */	----
11723	642,	----
11724	/* ABSMacro */	----
11725	646,	----
11726	/* ADJCALLSTACKDOWN */	----
11727	648,	----
11728	/* ADJCALLSTACKUP */	----
11729	650,	----
11730	/* AND_V_D_PSEUDO */	----
11731	652,	----
11732	/* AND_V_H_PSEUDO */	----
11733	655,	----
11734	/* AND_V_W_PSEUDO */	----
11735	658,	----
11736	/* ATOMIC_CMP_SWAP_I16 */	----
11737	661,	----
11738	/* ATOMIC_CMP_SWAP_I16_POSTRA */	----
11739	665,	----
11740	/* ATOMIC_CMP_SWAP_I32 */	----
11741	672,	----
11742	/* ATOMIC_CMP_SWAP_I32_POSTRA */	----
11743	676,	----
11744	/* ATOMIC_CMP_SWAP_I64 */	----
11745	680,	----
11746	/* ATOMIC_CMP_SWAP_I64_POSTRA */	----
11747	684,	----
11748	/* ATOMIC_CMP_SWAP_I8 */	----
11749	688,	----
11750	/* ATOMIC_CMP_SWAP_I8_POSTRA */	----
11751	692,	----
11752	/* ATOMIC_LOAD_ADD_I16 */	----
11753	699,	----
11754	/* ATOMIC_LOAD_ADD_I16_POSTRA */	----
11755	702,	----
11756	/* ATOMIC_LOAD_ADD_I32 */	----
11757	708,	----
11758	/* ATOMIC_LOAD_ADD_I32_POSTRA */	----
11759	711,	----
11760	/* ATOMIC_LOAD_ADD_I64 */	----
11761	714,	----
11762	/* ATOMIC_LOAD_ADD_I64_POSTRA */	----
11763	717,	----
11764	/* ATOMIC_LOAD_ADD_I8 */	----
11765	720,	----
11766	/* ATOMIC_LOAD_ADD_I8_POSTRA */	----
11767	723,	----
11768	/* ATOMIC_LOAD_AND_I16 */	----
11769	729,	----
11770	/* ATOMIC_LOAD_AND_I16_POSTRA */	----
11771	732,	----
11772	/* ATOMIC_LOAD_AND_I32 */	----
11773	738,	----
11774	/* ATOMIC_LOAD_AND_I32_POSTRA */	----
11775	741,	----
11776	/* ATOMIC_LOAD_AND_I64 */	----
11777	744,	----
11778	/* ATOMIC_LOAD_AND_I64_POSTRA */	----
11779	747,	----
11780	/* ATOMIC_LOAD_AND_I8 */	----
11781	750,	----
11782	/* ATOMIC_LOAD_AND_I8_POSTRA */	----
11783	753,	----
11784	/* ATOMIC_LOAD_MAX_I16 */	----
11785	759,	----
11786	/* ATOMIC_LOAD_MAX_I16_POSTRA */	----
11787	762,	----
11788	/* ATOMIC_LOAD_MAX_I32 */	----
11789	768,	----
11790	/* ATOMIC_LOAD_MAX_I32_POSTRA */	----
11791	771,	----
11792	/* ATOMIC_LOAD_MAX_I64 */	----
11793	774,	----
11794	/* ATOMIC_LOAD_MAX_I64_POSTRA */	----
11795	777,	----
11796	/* ATOMIC_LOAD_MAX_I8 */	----
11797	780,	----
11798	/* ATOMIC_LOAD_MAX_I8_POSTRA */	----
11799	783,	----
11800	/* ATOMIC_LOAD_MIN_I16 */	----
11801	789,	----
11802	/* ATOMIC_LOAD_MIN_I16_POSTRA */	----
11803	792,	----
11804	/* ATOMIC_LOAD_MIN_I32 */	----
11805	798,	----
11806	/* ATOMIC_LOAD_MIN_I32_POSTRA */	----
11807	801,	----
11808	/* ATOMIC_LOAD_MIN_I64 */	----
11809	804,	----
11810	/* ATOMIC_LOAD_MIN_I64_POSTRA */	----
11811	807,	----
11812	/* ATOMIC_LOAD_MIN_I8 */	----
11813	810,	----
11814	/* ATOMIC_LOAD_MIN_I8_POSTRA */	----
11815	813,	----
11816	/* ATOMIC_LOAD_NAND_I16 */	----
11817	819,	----
11818	/* ATOMIC_LOAD_NAND_I16_POSTRA */	----
11819	822,	----
11820	/* ATOMIC_LOAD_NAND_I32 */	----
11821	828,	----
11822	/* ATOMIC_LOAD_NAND_I32_POSTRA */	----
11823	831,	----
11824	/* ATOMIC_LOAD_NAND_I64 */	----
11825	834,	----
11826	/* ATOMIC_LOAD_NAND_I64_POSTRA */	----
11827	837,	----
11828	/* ATOMIC_LOAD_NAND_I8 */	----
11829	840,	----
11830	/* ATOMIC_LOAD_NAND_I8_POSTRA */	----
11831	843,	----
11832	/* ATOMIC_LOAD_OR_I16 */	----
11833	849,	----
11834	/* ATOMIC_LOAD_OR_I16_POSTRA */	----
11835	852,	----
11836	/* ATOMIC_LOAD_OR_I32 */	----
11837	858,	----
11838	/* ATOMIC_LOAD_OR_I32_POSTRA */	----
11839	861,	----
11840	/* ATOMIC_LOAD_OR_I64 */	----
11841	864,	----
11842	/* ATOMIC_LOAD_OR_I64_POSTRA */	----
11843	867,	----
11844	/* ATOMIC_LOAD_OR_I8 */	----
11845	870,	----
11846	/* ATOMIC_LOAD_OR_I8_POSTRA */	----
11847	873,	----
11848	/* ATOMIC_LOAD_SUB_I16 */	----
11849	879,	----
11850	/* ATOMIC_LOAD_SUB_I16_POSTRA */	----
11851	882,	----
11852	/* ATOMIC_LOAD_SUB_I32 */	----
11853	888,	----
11854	/* ATOMIC_LOAD_SUB_I32_POSTRA */	----
11855	891,	----
11856	/* ATOMIC_LOAD_SUB_I64 */	----
11857	894,	----
11858	/* ATOMIC_LOAD_SUB_I64_POSTRA */	----
11859	897,	----
11860	/* ATOMIC_LOAD_SUB_I8 */	----
11861	900,	----
11862	/* ATOMIC_LOAD_SUB_I8_POSTRA */	----
11863	903,	----
11864	/* ATOMIC_LOAD_UMAX_I16 */	----
11865	909,	----
11866	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	----
11867	912,	----
11868	/* ATOMIC_LOAD_UMAX_I32 */	----
11869	918,	----
11870	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	----
11871	921,	----
11872	/* ATOMIC_LOAD_UMAX_I64 */	----
11873	924,	----
11874	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	----
11875	927,	----
11876	/* ATOMIC_LOAD_UMAX_I8 */	----
11877	930,	----
11878	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	----
11879	933,	----
11880	/* ATOMIC_LOAD_UMIN_I16 */	----
11881	939,	----
11882	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	----
11883	942,	----
11884	/* ATOMIC_LOAD_UMIN_I32 */	----
11885	948,	----
11886	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	----
11887	951,	----
11888	/* ATOMIC_LOAD_UMIN_I64 */	----
11889	954,	----
11890	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	----
11891	957,	----
11892	/* ATOMIC_LOAD_UMIN_I8 */	----
11893	960,	----
11894	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	----
11895	963,	----
11896	/* ATOMIC_LOAD_XOR_I16 */	----
11897	969,	----
11898	/* ATOMIC_LOAD_XOR_I16_POSTRA */	----
11899	972,	----
11900	/* ATOMIC_LOAD_XOR_I32 */	----
11901	978,	----
11902	/* ATOMIC_LOAD_XOR_I32_POSTRA */	----
11903	981,	----
11904	/* ATOMIC_LOAD_XOR_I64 */	----
11905	984,	----
11906	/* ATOMIC_LOAD_XOR_I64_POSTRA */	----
11907	987,	----
11908	/* ATOMIC_LOAD_XOR_I8 */	----
11909	990,	----
11910	/* ATOMIC_LOAD_XOR_I8_POSTRA */	----
11911	993,	----
11912	/* ATOMIC_SWAP_I16 */	----
11913	999,	----
11914	/* ATOMIC_SWAP_I16_POSTRA */	----
11915	1002,	----
11916	/* ATOMIC_SWAP_I32 */	----
11917	1008,	----
11918	/* ATOMIC_SWAP_I32_POSTRA */	----
11919	1011,	----
11920	/* ATOMIC_SWAP_I64 */	----
11921	1014,	----
11922	/* ATOMIC_SWAP_I64_POSTRA */	----
11923	1017,	----
11924	/* ATOMIC_SWAP_I8 */	----
11925	1020,	----
11926	/* ATOMIC_SWAP_I8_POSTRA */	----
11927	1023,	----
11928	/* B */	----
11929	1029,	----
11930	/* BAL_BR */	----
11931	1030,	----
11932	/* BAL_BR_MM */	----
11933	1031,	----
11934	/* BEQLImmMacro */	----
11935	1032,	----
11936	/* BGE */	----
11937	1035,	----
11938	/* BGEImmMacro */	----
11939	1038,	----
11940	/* BGEL */	----
11941	1041,	----
11942	/* BGELImmMacro */	----
11943	1044,	----
11944	/* BGEU */	----
11945	1047,	----
11946	/* BGEUImmMacro */	----
11947	1050,	----
11948	/* BGEUL */	----
11949	1053,	----
11950	/* BGEULImmMacro */	----
11951	1056,	----
11952	/* BGT */	----
11953	1059,	----
11954	/* BGTImmMacro */	----
11955	1062,	----
11956	/* BGTL */	----
11957	1065,	----
11958	/* BGTLImmMacro */	----
11959	1068,	----
11960	/* BGTU */	----
11961	1071,	----
11962	/* BGTUImmMacro */	----
11963	1074,	----
11964	/* BGTUL */	----
11965	1077,	----
11966	/* BGTULImmMacro */	----
11967	1080,	----
11968	/* BLE */	----
11969	1083,	----
11970	/* BLEImmMacro */	----
11971	1086,	----
11972	/* BLEL */	----
11973	1089,	----
11974	/* BLELImmMacro */	----
11975	1092,	----
11976	/* BLEU */	----
11977	1095,	----
11978	/* BLEUImmMacro */	----
11979	1098,	----
11980	/* BLEUL */	----
11981	1101,	----
11982	/* BLEULImmMacro */	----
11983	1104,	----
11984	/* BLT */	----
11985	1107,	----
11986	/* BLTImmMacro */	----
11987	1110,	----
11988	/* BLTL */	----
11989	1113,	----
11990	/* BLTLImmMacro */	----
11991	1116,	----
11992	/* BLTU */	----
11993	1119,	----
11994	/* BLTUImmMacro */	----
11995	1122,	----
11996	/* BLTUL */	----
11997	1125,	----
11998	/* BLTULImmMacro */	----
11999	1128,	----
12000	/* BNELImmMacro */	----
12001	1131,	----
12002	/* BPOSGE32_PSEUDO */	----
12003	1134,	----
12004	/* BSEL_D_PSEUDO */	----
12005	1135,	----
12006	/* BSEL_FD_PSEUDO */	----
12007	1139,	----
12008	/* BSEL_FW_PSEUDO */	----
12009	1143,	----
12010	/* BSEL_H_PSEUDO */	----
12011	1147,	----
12012	/* BSEL_W_PSEUDO */	----
12013	1151,	----
12014	/* B_MM */	----
12015	1155,	----
12016	/* B_MMR6_Pseudo */	----
12017	1156,	----
12018	/* B_MM_Pseudo */	----
12019	1157,	----
12020	/* BeqImm */	----
12021	1158,	----
12022	/* BneImm */	----
12023	1161,	----
12024	/* BteqzT8CmpX16 */	----
12025	1164,	----
12026	/* BteqzT8CmpiX16 */	----
12027	1167,	----
12028	/* BteqzT8SltX16 */	----
12029	1170,	----
12030	/* BteqzT8SltiX16 */	----
12031	1173,	----
12032	/* BteqzT8SltiuX16 */	----
12033	1176,	----
12034	/* BteqzT8SltuX16 */	----
12035	1179,	----
12036	/* BtnezT8CmpX16 */	----
12037	1182,	----
12038	/* BtnezT8CmpiX16 */	----
12039	1185,	----
12040	/* BtnezT8SltX16 */	----
12041	1188,	----
12042	/* BtnezT8SltiX16 */	----
12043	1191,	----
12044	/* BtnezT8SltiuX16 */	----
12045	1194,	----
12046	/* BtnezT8SltuX16 */	----
12047	1197,	----
12048	/* BuildPairF64 */	----
12049	1200,	----
12050	/* BuildPairF64_64 */	----
12051	1203,	----
12052	/* CFTC1 */	----
12053	1206,	----
12054	/* CONSTPOOL_ENTRY */	----
12055	1208,	----
12056	/* COPY_FD_PSEUDO */	----
12057	1211,	----
12058	/* COPY_FW_PSEUDO */	----
12059	1214,	----
12060	/* CTTC1 */	----
12061	1217,	----
12062	/* Constant32 */	----
12063	1219,	----
12064	/* DMULImmMacro */	----
12065	1220,	----
12066	/* DMULMacro */	----
12067	1223,	----
12068	/* DMULOMacro */	----
12069	1226,	----
12070	/* DMULOUMacro */	----
12071	1229,	----
12072	/* DROL */	----
12073	1232,	----
12074	/* DROLImm */	----
12075	1235,	----
12076	/* DROR */	----
12077	1238,	----
12078	/* DRORImm */	----
12079	1241,	----
12080	/* DSDivIMacro */	----
12081	1244,	----
12082	/* DSDivMacro */	----
12083	1247,	----
12084	/* DSRemIMacro */	----
12085	1250,	----
12086	/* DSRemMacro */	----
12087	1253,	----
12088	/* DUDivIMacro */	----
12089	1256,	----
12090	/* DUDivMacro */	----
12091	1259,	----
12092	/* DURemIMacro */	----
12093	1262,	----
12094	/* DURemMacro */	----
12095	1265,	----
12096	/* ERet */	----
12097	1268,	----
12098	/* ExtractElementF64 */	----
12099	1268,	----
12100	/* ExtractElementF64_64 */	----
12101	1271,	----
12102	/* FABS_D */	----
12103	1274,	----
12104	/* FABS_W */	----
12105	1276,	----
12106	/* FEXP2_D_1_PSEUDO */	----
12107	1278,	----
12108	/* FEXP2_W_1_PSEUDO */	----
12109	1280,	----
12110	/* FILL_FD_PSEUDO */	----
12111	1282,	----
12112	/* FILL_FW_PSEUDO */	----
12113	1284,	----
12114	/* GotPrologue16 */	----
12115	1286,	----
12116	/* INSERT_B_VIDX64_PSEUDO */	----
12117	1290,	----
12118	/* INSERT_B_VIDX_PSEUDO */	----
12119	1294,	----
12120	/* INSERT_D_VIDX64_PSEUDO */	----
12121	1298,	----
12122	/* INSERT_D_VIDX_PSEUDO */	----
12123	1302,	----
12124	/* INSERT_FD_PSEUDO */	----
12125	1306,	----
12126	/* INSERT_FD_VIDX64_PSEUDO */	----
12127	1310,	----
12128	/* INSERT_FD_VIDX_PSEUDO */	----
12129	1314,	----
12130	/* INSERT_FW_PSEUDO */	----
12131	1318,	----
12132	/* INSERT_FW_VIDX64_PSEUDO */	----
12133	1322,	----
12134	/* INSERT_FW_VIDX_PSEUDO */	----
12135	1326,	----
12136	/* INSERT_H_VIDX64_PSEUDO */	----
12137	1330,	----
12138	/* INSERT_H_VIDX_PSEUDO */	----
12139	1334,	----
12140	/* INSERT_W_VIDX64_PSEUDO */	----
12141	1338,	----
12142	/* INSERT_W_VIDX_PSEUDO */	----
12143	1342,	----
12144	/* JALR64Pseudo */	----
12145	1346,	----
12146	/* JALRHB64Pseudo */	----
12147	1347,	----
12148	/* JALRHBPseudo */	----
12149	1348,	----
12150	/* JALRPseudo */	----
12151	1349,	----
12152	/* JAL_MMR6 */	----
12153	1350,	----
12154	/* JalOneReg */	----
12155	1351,	----
12156	/* JalTwoReg */	----
12157	1352,	----
12158	/* LDMacro */	----
12159	1354,	----
12160	/* LDR_D */	----
12161	1357,	----
12162	/* LDR_W */	----
12163	1360,	----
12164	/* LD_F16 */	----
12165	1363,	----
12166	/* LOAD_ACC128 */	----
12167	1366,	----
12168	/* LOAD_ACC64 */	----
12169	1369,	----
12170	/* LOAD_ACC64DSP */	----
12171	1372,	----
12172	/* LOAD_CCOND_DSP */	----
12173	1375,	----
12174	/* LONG_BRANCH_ADDiu */	----
12175	1378,	----
12176	/* LONG_BRANCH_ADDiu2Op */	----
12177	1382,	----
12178	/* LONG_BRANCH_DADDiu */	----
12179	1385,	----
12180	/* LONG_BRANCH_DADDiu2Op */	----
12181	1389,	----
12182	/* LONG_BRANCH_LUi */	----
12183	1392,	----
12184	/* LONG_BRANCH_LUi2Op */	----
12185	1395,	----
12186	/* LONG_BRANCH_LUi2Op_64 */	----
12187	1397,	----
12188	/* LWM_MM */	----
12189	1399,	----
12190	/* LoadAddrImm32 */	----
12191	1402,	----
12192	/* LoadAddrImm64 */	----
12193	1404,	----
12194	/* LoadAddrReg32 */	----
12195	1406,	----
12196	/* LoadAddrReg64 */	----
12197	1409,	----
12198	/* LoadImm32 */	----
12199	1412,	----
12200	/* LoadImm64 */	----
12201	1414,	----
12202	/* LoadImmDoubleFGR */	----
12203	1416,	----
12204	/* LoadImmDoubleFGR_32 */	----
12205	1418,	----
12206	/* LoadImmDoubleGPR */	----
12207	1420,	----
12208	/* LoadImmSingleFGR */	----
12209	1422,	----
12210	/* LoadImmSingleGPR */	----
12211	1424,	----
12212	/* LwConstant32 */	----
12213	1426,	----
12214	/* MFTACX */	----
12215	1429,	----
12216	/* MFTC0 */	----
12217	1431,	----
12218	/* MFTC1 */	----
12219	1434,	----
12220	/* MFTDSP */	----
12221	1436,	----
12222	/* MFTGPR */	----
12223	1437,	----
12224	/* MFTHC1 */	----
12225	1440,	----
12226	/* MFTHI */	----
12227	1442,	----
12228	/* MFTLO */	----
12229	1444,	----
12230	/* MIPSeh_return32 */	----
12231	1446,	----
12232	/* MIPSeh_return64 */	----
12233	1448,	----
12234	/* MSA_FP_EXTEND_D_PSEUDO */	----
12235	1450,	----
12236	/* MSA_FP_EXTEND_W_PSEUDO */	----
12237	1452,	----
12238	/* MSA_FP_ROUND_D_PSEUDO */	----
12239	1454,	----
12240	/* MSA_FP_ROUND_W_PSEUDO */	----
12241	1456,	----
12242	/* MTTACX */	----
12243	1458,	----
12244	/* MTTC0 */	----
12245	1460,	----
12246	/* MTTC1 */	----
12247	1463,	----
12248	/* MTTDSP */	----
12249	1465,	----
12250	/* MTTGPR */	----
12251	1466,	----
12252	/* MTTHC1 */	----
12253	1468,	----
12254	/* MTTHI */	----
12255	1470,	----
12256	/* MTTLO */	----
12257	1472,	----
12258	/* MULImmMacro */	----
12259	1474,	----
12260	/* MULOMacro */	----
12261	1477,	----
12262	/* MULOUMacro */	----
12263	1480,	----
12264	/* MultRxRy16 */	----
12265	1483,	----
12266	/* MultRxRyRz16 */	----
12267	1485,	----
12268	/* MultuRxRy16 */	----
12269	1488,	----
12270	/* MultuRxRyRz16 */	----
12271	1490,	----
12272	/* NOP */	----
12273	1493,	----
12274	/* NORImm */	----
12275	1493,	----
12276	/* NORImm64 */	----
12277	1496,	----
12278	/* NOR_V_D_PSEUDO */	----
12279	1499,	----
12280	/* NOR_V_H_PSEUDO */	----
12281	1502,	----
12282	/* NOR_V_W_PSEUDO */	----
12283	1505,	----
12284	/* OR_V_D_PSEUDO */	----
12285	1508,	----
12286	/* OR_V_H_PSEUDO */	----
12287	1511,	----
12288	/* OR_V_W_PSEUDO */	----
12289	1514,	----
12290	/* PseudoCMPU_EQ_QB */	----
12291	1517,	----
12292	/* PseudoCMPU_LE_QB */	----
12293	1520,	----
12294	/* PseudoCMPU_LT_QB */	----
12295	1523,	----
12296	/* PseudoCMP_EQ_PH */	----
12297	1526,	----
12298	/* PseudoCMP_LE_PH */	----
12299	1529,	----
12300	/* PseudoCMP_LT_PH */	----
12301	1532,	----
12302	/* PseudoCVT_D32_W */	----
12303	1535,	----
12304	/* PseudoCVT_D64_L */	----
12305	1537,	----
12306	/* PseudoCVT_D64_W */	----
12307	1539,	----
12308	/* PseudoCVT_S_L */	----
12309	1541,	----
12310	/* PseudoCVT_S_W */	----
12311	1543,	----
12312	/* PseudoDMULT */	----
12313	1545,	----
12314	/* PseudoDMULTu */	----
12315	1548,	----
12316	/* PseudoDSDIV */	----
12317	1551,	----
12318	/* PseudoDUDIV */	----
12319	1554,	----
12320	/* PseudoD_SELECT_I */	----
12321	1557,	----
12322	/* PseudoD_SELECT_I64 */	----
12323	1564,	----
12324	/* PseudoIndirectBranch */	----
12325	1571,	----
12326	/* PseudoIndirectBranch64 */	----
12327	1572,	----
12328	/* PseudoIndirectBranch64R6 */	----
12329	1573,	----
12330	/* PseudoIndirectBranchR6 */	----
12331	1574,	----
12332	/* PseudoIndirectBranch_MM */	----
12333	1575,	----
12334	/* PseudoIndirectBranch_MMR6 */	----
12335	1576,	----
12336	/* PseudoIndirectHazardBranch */	----
12337	1577,	----
12338	/* PseudoIndirectHazardBranch64 */	----
12339	1578,	----
12340	/* PseudoIndrectHazardBranch64R6 */	----
12341	1579,	----
12342	/* PseudoIndrectHazardBranchR6 */	----
12343	1580,	----
12344	/* PseudoMADD */	----
12345	1581,	----
12346	/* PseudoMADDU */	----
12347	1585,	----
12348	/* PseudoMADDU_MM */	----
12349	1589,	----
12350	/* PseudoMADD_MM */	----
12351	1593,	----
12352	/* PseudoMFHI */	----
12353	1597,	----
12354	/* PseudoMFHI64 */	----
12355	1599,	----
12356	/* PseudoMFHI_MM */	----
12357	1601,	----
12358	/* PseudoMFLO */	----
12359	1603,	----
12360	/* PseudoMFLO64 */	----
12361	1605,	----
12362	/* PseudoMFLO_MM */	----
12363	1607,	----
12364	/* PseudoMSUB */	----
12365	1609,	----
12366	/* PseudoMSUBU */	----
12367	1613,	----
12368	/* PseudoMSUBU_MM */	----
12369	1617,	----
12370	/* PseudoMSUB_MM */	----
12371	1621,	----
12372	/* PseudoMTLOHI */	----
12373	1625,	----
12374	/* PseudoMTLOHI64 */	----
12375	1628,	----
12376	/* PseudoMTLOHI_DSP */	----
12377	1631,	----
12378	/* PseudoMTLOHI_MM */	----
12379	1634,	----
12380	/* PseudoMULT */	----
12381	1637,	----
12382	/* PseudoMULT_MM */	----
12383	1640,	----
12384	/* PseudoMULTu */	----
12385	1643,	----
12386	/* PseudoMULTu_MM */	----
12387	1646,	----
12388	/* PseudoPICK_PH */	----
12389	1649,	----
12390	/* PseudoPICK_QB */	----
12391	1653,	----
12392	/* PseudoReturn */	----
12393	1657,	----
12394	/* PseudoReturn64 */	----
12395	1658,	----
12396	/* PseudoSDIV */	----
12397	1659,	----
12398	/* PseudoSELECTFP_F_D32 */	----
12399	1662,	----
12400	/* PseudoSELECTFP_F_D64 */	----
12401	1666,	----
12402	/* PseudoSELECTFP_F_I */	----
12403	1670,	----
12404	/* PseudoSELECTFP_F_I64 */	----
12405	1674,	----
12406	/* PseudoSELECTFP_F_S */	----
12407	1678,	----
12408	/* PseudoSELECTFP_T_D32 */	----
12409	1682,	----
12410	/* PseudoSELECTFP_T_D64 */	----
12411	1686,	----
12412	/* PseudoSELECTFP_T_I */	----
12413	1690,	----
12414	/* PseudoSELECTFP_T_I64 */	----
12415	1694,	----
12416	/* PseudoSELECTFP_T_S */	----
12417	1698,	----
12418	/* PseudoSELECT_D32 */	----
12419	1702,	----
12420	/* PseudoSELECT_D64 */	----
12421	1706,	----
12422	/* PseudoSELECT_I */	----
12423	1710,	----
12424	/* PseudoSELECT_I64 */	----
12425	1714,	----
12426	/* PseudoSELECT_S */	----
12427	1718,	----
12428	/* PseudoTRUNC_W_D */	----
12429	1722,	----
12430	/* PseudoTRUNC_W_D32 */	----
12431	1725,	----
12432	/* PseudoTRUNC_W_S */	----
12433	1728,	----
12434	/* PseudoUDIV */	----
12435	1731,	----
12436	/* ROL */	----
12437	1734,	----
12438	/* ROLImm */	----
12439	1737,	----
12440	/* ROR */	----
12441	1740,	----
12442	/* RORImm */	----
12443	1743,	----
12444	/* RetRA */	----
12445	1746,	----
12446	/* RetRA16 */	----
12447	1746,	----
12448	/* SDC1_M1 */	----
12449	1746,	----
12450	/* SDIV_MM_Pseudo */	----
12451	1749,	----
12452	/* SDMacro */	----
12453	1752,	----
12454	/* SDivIMacro */	----
12455	1755,	----
12456	/* SDivMacro */	----
12457	1758,	----
12458	/* SEQIMacro */	----
12459	1761,	----
12460	/* SEQMacro */	----
12461	1764,	----
12462	/* SGE */	----
12463	1767,	----
12464	/* SGEImm */	----
12465	1770,	----
12466	/* SGEImm64 */	----
12467	1773,	----
12468	/* SGEU */	----
12469	1776,	----
12470	/* SGEUImm */	----
12471	1779,	----
12472	/* SGEUImm64 */	----
12473	1782,	----
12474	/* SGTImm */	----
12475	1785,	----
12476	/* SGTImm64 */	----
12477	1788,	----
12478	/* SGTUImm */	----
12479	1791,	----
12480	/* SGTUImm64 */	----
12481	1794,	----
12482	/* SLE */	----
12483	1797,	----
12484	/* SLEImm */	----
12485	1800,	----
12486	/* SLEImm64 */	----
12487	1803,	----
12488	/* SLEU */	----
12489	1806,	----
12490	/* SLEUImm */	----
12491	1809,	----
12492	/* SLEUImm64 */	----
12493	1812,	----
12494	/* SLTImm64 */	----
12495	1815,	----
12496	/* SLTUImm64 */	----
12497	1818,	----
12498	/* SNEIMacro */	----
12499	1821,	----
12500	/* SNEMacro */	----
12501	1824,	----
12502	/* SNZ_B_PSEUDO */	----
12503	1827,	----
12504	/* SNZ_D_PSEUDO */	----
12505	1829,	----
12506	/* SNZ_H_PSEUDO */	----
12507	1831,	----
12508	/* SNZ_V_PSEUDO */	----
12509	1833,	----
12510	/* SNZ_W_PSEUDO */	----
12511	1835,	----
12512	/* SRemIMacro */	----
12513	1837,	----
12514	/* SRemMacro */	----
12515	1840,	----
12516	/* STORE_ACC128 */	----
12517	1843,	----
12518	/* STORE_ACC64 */	----
12519	1846,	----
12520	/* STORE_ACC64DSP */	----
12521	1849,	----
12522	/* STORE_CCOND_DSP */	----
12523	1852,	----
12524	/* STR_D */	----
12525	1855,	----
12526	/* STR_W */	----
12527	1858,	----
12528	/* ST_F16 */	----
12529	1861,	----
12530	/* SWM_MM */	----
12531	1864,	----
12532	/* SZ_B_PSEUDO */	----
12533	1867,	----
12534	/* SZ_D_PSEUDO */	----
12535	1869,	----
12536	/* SZ_H_PSEUDO */	----
12537	1871,	----
12538	/* SZ_V_PSEUDO */	----
12539	1873,	----
12540	/* SZ_W_PSEUDO */	----
12541	1875,	----
12542	/* SaaAddr */	----
12543	1877,	----
12544	/* SaadAddr */	----
12545	1880,	----
12546	/* SelBeqZ */	----
12547	1883,	----
12548	/* SelBneZ */	----
12549	1887,	----
12550	/* SelTBteqZCmp */	----
12551	1891,	----
12552	/* SelTBteqZCmpi */	----
12553	1896,	----
12554	/* SelTBteqZSlt */	----
12555	1901,	----
12556	/* SelTBteqZSlti */	----
12557	1906,	----
12558	/* SelTBteqZSltiu */	----
12559	1911,	----
12560	/* SelTBteqZSltu */	----
12561	1916,	----
12562	/* SelTBtneZCmp */	----
12563	1921,	----
12564	/* SelTBtneZCmpi */	----
12565	1926,	----
12566	/* SelTBtneZSlt */	----
12567	1931,	----
12568	/* SelTBtneZSlti */	----
12569	1936,	----
12570	/* SelTBtneZSltiu */	----
12571	1941,	----
12572	/* SelTBtneZSltu */	----
12573	1946,	----
12574	/* SltCCRxRy16 */	----
12575	1951,	----
12576	/* SltiCCRxImmX16 */	----
12577	1954,	----
12578	/* SltiuCCRxImmX16 */	----
12579	1957,	----
12580	/* SltuCCRxRy16 */	----
12581	1960,	----
12582	/* SltuRxRyRz16 */	----
12583	1963,	----
12584	/* TAILCALL */	----
12585	1966,	----
12586	/* TAILCALL64R6REG */	----
12587	1967,	----
12588	/* TAILCALLHB64R6REG */	----
12589	1968,	----
12590	/* TAILCALLHBR6REG */	----
12591	1969,	----
12592	/* TAILCALLR6REG */	----
12593	1970,	----
12594	/* TAILCALLREG */	----
12595	1971,	----
12596	/* TAILCALLREG64 */	----
12597	1972,	----
12598	/* TAILCALLREGHB */	----
12599	1973,	----
12600	/* TAILCALLREGHB64 */	----
12601	1974,	----
12602	/* TAILCALLREG_MM */	----
12603	1975,	----
12604	/* TAILCALLREG_MMR6 */	----
12605	1976,	----
12606	/* TAILCALL_MM */	----
12607	1977,	----
12608	/* TAILCALL_MMR6 */	----
12609	1978,	----
12610	/* TRAP */	----
12611	1979,	----
12612	/* TRAP_MM */	----
12613	1979,	----
12614	/* UDIV_MM_Pseudo */	----
12615	1979,	----
12616	/* UDivIMacro */	----
12617	1982,	----
12618	/* UDivMacro */	----
12619	1985,	----
12620	/* URemIMacro */	----
12621	1988,	----
12622	/* URemMacro */	----
12623	1991,	----
12624	/* Ulh */	----
12625	1994,	----
12626	/* Ulhu */	----
12627	1997,	----
12628	/* Ulw */	----
12629	2000,	----
12630	/* Ush */	----
12631	2003,	----
12632	/* Usw */	----
12633	2006,	----
12634	/* XOR_V_D_PSEUDO */	----
12635	2009,	----
12636	/* XOR_V_H_PSEUDO */	----
12637	2012,	----
12638	/* XOR_V_W_PSEUDO */	----
12639	2015,	----
12640	/* ABSQ_S_PH */	----
12641	2018,	----
12642	/* ABSQ_S_PH_MM */	----
12643	2020,	----
12644	/* ABSQ_S_QB */	----
12645	2022,	----
12646	/* ABSQ_S_QB_MMR2 */	----
12647	2024,	----
12648	/* ABSQ_S_W */	----
12649	2026,	----
12650	/* ABSQ_S_W_MM */	----
12651	2028,	----
12652	/* ADD */	----
12653	2030,	----
12654	/* ADDIUPC */	----
12655	2033,	----
12656	/* ADDIUPC_MM */	----
12657	2035,	----
12658	/* ADDIUPC_MMR6 */	----
12659	2037,	----
12660	/* ADDIUR1SP_MM */	----
12661	2039,	----
12662	/* ADDIUR2_MM */	----
12663	2041,	----
12664	/* ADDIUS5_MM */	----
12665	2044,	----
12666	/* ADDIUSP_MM */	----
12667	2047,	----
12668	/* ADDIU_MMR6 */	----
12669	2048,	----
12670	/* ADDQH_PH */	----
12671	2051,	----
12672	/* ADDQH_PH_MMR2 */	----
12673	2054,	----
12674	/* ADDQH_R_PH */	----
12675	2057,	----
12676	/* ADDQH_R_PH_MMR2 */	----
12677	2060,	----
12678	/* ADDQH_R_W */	----
12679	2063,	----
12680	/* ADDQH_R_W_MMR2 */	----
12681	2066,	----
12682	/* ADDQH_W */	----
12683	2069,	----
12684	/* ADDQH_W_MMR2 */	----
12685	2072,	----
12686	/* ADDQ_PH */	----
12687	2075,	----
12688	/* ADDQ_PH_MM */	----
12689	2078,	----
12690	/* ADDQ_S_PH */	----
12691	2081,	----
12692	/* ADDQ_S_PH_MM */	----
12693	2084,	----
12694	/* ADDQ_S_W */	----
12695	2087,	----
12696	/* ADDQ_S_W_MM */	----
12697	2090,	----
12698	/* ADDR_PS64 */	----
12699	2093,	----
12700	/* ADDSC */	----
12701	2096,	----
12702	/* ADDSC_MM */	----
12703	2099,	----
12704	/* ADDS_A_B */	----
12705	2102,	----
12706	/* ADDS_A_D */	----
12707	2105,	----
12708	/* ADDS_A_H */	----
12709	2108,	----
12710	/* ADDS_A_W */	----
12711	2111,	----
12712	/* ADDS_S_B */	----
12713	2114,	----
12714	/* ADDS_S_D */	----
12715	2117,	----
12716	/* ADDS_S_H */	----
12717	2120,	----
12718	/* ADDS_S_W */	----
12719	2123,	----
12720	/* ADDS_U_B */	----
12721	2126,	----
12722	/* ADDS_U_D */	----
12723	2129,	----
12724	/* ADDS_U_H */	----
12725	2132,	----
12726	/* ADDS_U_W */	----
12727	2135,	----
12728	/* ADDU16_MM */	----
12729	2138,	----
12730	/* ADDU16_MMR6 */	----
12731	2141,	----
12732	/* ADDUH_QB */	----
12733	2144,	----
12734	/* ADDUH_QB_MMR2 */	----
12735	2147,	----
12736	/* ADDUH_R_QB */	----
12737	2150,	----
12738	/* ADDUH_R_QB_MMR2 */	----
12739	2153,	----
12740	/* ADDU_MMR6 */	----
12741	2156,	----
12742	/* ADDU_PH */	----
12743	2159,	----
12744	/* ADDU_PH_MMR2 */	----
12745	2162,	----
12746	/* ADDU_QB */	----
12747	2165,	----
12748	/* ADDU_QB_MM */	----
12749	2168,	----
12750	/* ADDU_S_PH */	----
12751	2171,	----
12752	/* ADDU_S_PH_MMR2 */	----
12753	2174,	----
12754	/* ADDU_S_QB */	----
12755	2177,	----
12756	/* ADDU_S_QB_MM */	----
12757	2180,	----
12758	/* ADDVI_B */	----
12759	2183,	----
12760	/* ADDVI_D */	----
12761	2186,	----
12762	/* ADDVI_H */	----
12763	2189,	----
12764	/* ADDVI_W */	----
12765	2192,	----
12766	/* ADDV_B */	----
12767	2195,	----
12768	/* ADDV_D */	----
12769	2198,	----
12770	/* ADDV_H */	----
12771	2201,	----
12772	/* ADDV_W */	----
12773	2204,	----
12774	/* ADDWC */	----
12775	2207,	----
12776	/* ADDWC_MM */	----
12777	2210,	----
12778	/* ADD_A_B */	----
12779	2213,	----
12780	/* ADD_A_D */	----
12781	2216,	----
12782	/* ADD_A_H */	----
12783	2219,	----
12784	/* ADD_A_W */	----
12785	2222,	----
12786	/* ADD_MM */	----
12787	2225,	----
12788	/* ADD_MMR6 */	----
12789	2228,	----
12790	/* ADDi */	----
12791	2231,	----
12792	/* ADDi_MM */	----
12793	2234,	----
12794	/* ADDiu */	----
12795	2237,	----
12796	/* ADDiu_MM */	----
12797	2240,	----
12798	/* ADDu */	----
12799	2243,	----
12800	/* ADDu_MM */	----
12801	2246,	----
12802	/* ALIGN */	----
12803	2249,	----
12804	/* ALIGN_MMR6 */	----
12805	2253,	----
12806	/* ALUIPC */	----
12807	2257,	----
12808	/* ALUIPC_MMR6 */	----
12809	2259,	----
12810	/* AND */	----
12811	2261,	----
12812	/* AND16_MM */	----
12813	2264,	----
12814	/* AND16_MMR6 */	----
12815	2267,	----
12816	/* AND64 */	----
12817	2270,	----
12818	/* ANDI16_MM */	----
12819	2273,	----
12820	/* ANDI16_MMR6 */	----
12821	2276,	----
12822	/* ANDI_B */	----
12823	2279,	----
12824	/* ANDI_MMR6 */	----
12825	2282,	----
12826	/* AND_MM */	----
12827	2285,	----
12828	/* AND_MMR6 */	----
12829	2288,	----
12830	/* AND_V */	----
12831	2291,	----
12832	/* ANDi */	----
12833	2294,	----
12834	/* ANDi64 */	----
12835	2297,	----
12836	/* ANDi_MM */	----
12837	2300,	----
12838	/* APPEND */	----
12839	2303,	----
12840	/* APPEND_MMR2 */	----
12841	2307,	----
12842	/* ASUB_S_B */	----
12843	2311,	----
12844	/* ASUB_S_D */	----
12845	2314,	----
12846	/* ASUB_S_H */	----
12847	2317,	----
12848	/* ASUB_S_W */	----
12849	2320,	----
12850	/* ASUB_U_B */	----
12851	2323,	----
12852	/* ASUB_U_D */	----
12853	2326,	----
12854	/* ASUB_U_H */	----
12855	2329,	----
12856	/* ASUB_U_W */	----
12857	2332,	----
12858	/* AUI */	----
12859	2335,	----
12860	/* AUIPC */	----
12861	2338,	----
12862	/* AUIPC_MMR6 */	----
12863	2340,	----
12864	/* AUI_MMR6 */	----
12865	2342,	----
12866	/* AVER_S_B */	----
12867	2345,	----
12868	/* AVER_S_D */	----
12869	2348,	----
12870	/* AVER_S_H */	----
12871	2351,	----
12872	/* AVER_S_W */	----
12873	2354,	----
12874	/* AVER_U_B */	----
12875	2357,	----
12876	/* AVER_U_D */	----
12877	2360,	----
12878	/* AVER_U_H */	----
12879	2363,	----
12880	/* AVER_U_W */	----
12881	2366,	----
12882	/* AVE_S_B */	----
12883	2369,	----
12884	/* AVE_S_D */	----
12885	2372,	----
12886	/* AVE_S_H */	----
12887	2375,	----
12888	/* AVE_S_W */	----
12889	2378,	----
12890	/* AVE_U_B */	----
12891	2381,	----
12892	/* AVE_U_D */	----
12893	2384,	----
12894	/* AVE_U_H */	----
12895	2387,	----
12896	/* AVE_U_W */	----
12897	2390,	----
12898	/* AddiuRxImmX16 */	----
12899	2393,	----
12900	/* AddiuRxPcImmX16 */	----
12901	2395,	----
12902	/* AddiuRxRxImm16 */	----
12903	2397,	----
12904	/* AddiuRxRxImmX16 */	----
12905	2400,	----
12906	/* AddiuRxRyOffMemX16 */	----
12907	2403,	----
12908	/* AddiuSpImm16 */	----
12909	2406,	----
12910	/* AddiuSpImmX16 */	----
12911	2407,	----
12912	/* AdduRxRyRz16 */	----
12913	2408,	----
12914	/* AndRxRxRy16 */	----
12915	2411,	----
12916	/* B16_MM */	----
12917	2414,	----
12918	/* BADDu */	----
12919	2415,	----
12920	/* BAL */	----
12921	2418,	----
12922	/* BALC */	----
12923	2419,	----
12924	/* BALC_MMR6 */	----
12925	2420,	----
12926	/* BALIGN */	----
12927	2421,	----
12928	/* BALIGN_MMR2 */	----
12929	2425,	----
12930	/* BBIT0 */	----
12931	2429,	----
12932	/* BBIT032 */	----
12933	2432,	----
12934	/* BBIT1 */	----
12935	2435,	----
12936	/* BBIT132 */	----
12937	2438,	----
12938	/* BC */	----
12939	2441,	----
12940	/* BC16_MMR6 */	----
12941	2442,	----
12942	/* BC1EQZ */	----
12943	2443,	----
12944	/* BC1EQZC_MMR6 */	----
12945	2445,	----
12946	/* BC1F */	----
12947	2447,	----
12948	/* BC1FL */	----
12949	2449,	----
12950	/* BC1F_MM */	----
12951	2451,	----
12952	/* BC1NEZ */	----
12953	2453,	----
12954	/* BC1NEZC_MMR6 */	----
12955	2455,	----
12956	/* BC1T */	----
12957	2457,	----
12958	/* BC1TL */	----
12959	2459,	----
12960	/* BC1T_MM */	----
12961	2461,	----
12962	/* BC2EQZ */	----
12963	2463,	----
12964	/* BC2EQZC_MMR6 */	----
12965	2465,	----
12966	/* BC2NEZ */	----
12967	2467,	----
12968	/* BC2NEZC_MMR6 */	----
12969	2469,	----
12970	/* BCLRI_B */	----
12971	2471,	----
12972	/* BCLRI_D */	----
12973	2474,	----
12974	/* BCLRI_H */	----
12975	2477,	----
12976	/* BCLRI_W */	----
12977	2480,	----
12978	/* BCLR_B */	----
12979	2483,	----
12980	/* BCLR_D */	----
12981	2486,	----
12982	/* BCLR_H */	----
12983	2489,	----
12984	/* BCLR_W */	----
12985	2492,	----
12986	/* BC_MMR6 */	----
12987	2495,	----
12988	/* BEQ */	----
12989	2496,	----
12990	/* BEQ64 */	----
12991	2499,	----
12992	/* BEQC */	----
12993	2502,	----
12994	/* BEQC64 */	----
12995	2505,	----
12996	/* BEQC_MMR6 */	----
12997	2508,	----
12998	/* BEQL */	----
12999	2511,	----
13000	/* BEQZ16_MM */	----
13001	2514,	----
13002	/* BEQZALC */	----
13003	2516,	----
13004	/* BEQZALC_MMR6 */	----
13005	2518,	----
13006	/* BEQZC */	----
13007	2520,	----
13008	/* BEQZC16_MMR6 */	----
13009	2522,	----
13010	/* BEQZC64 */	----
13011	2524,	----
13012	/* BEQZC_MM */	----
13013	2526,	----
13014	/* BEQZC_MMR6 */	----
13015	2528,	----
13016	/* BEQ_MM */	----
13017	2530,	----
13018	/* BGEC */	----
13019	2533,	----
13020	/* BGEC64 */	----
13021	2536,	----
13022	/* BGEC_MMR6 */	----
13023	2539,	----
13024	/* BGEUC */	----
13025	2542,	----
13026	/* BGEUC64 */	----
13027	2545,	----
13028	/* BGEUC_MMR6 */	----
13029	2548,	----
13030	/* BGEZ */	----
13031	2551,	----
13032	/* BGEZ64 */	----
13033	2553,	----
13034	/* BGEZAL */	----
13035	2555,	----
13036	/* BGEZALC */	----
13037	2557,	----
13038	/* BGEZALC_MMR6 */	----
13039	2559,	----
13040	/* BGEZALL */	----
13041	2561,	----
13042	/* BGEZALS_MM */	----
13043	2563,	----
13044	/* BGEZAL_MM */	----
13045	2565,	----
13046	/* BGEZC */	----
13047	2567,	----
13048	/* BGEZC64 */	----
13049	2569,	----
13050	/* BGEZC_MMR6 */	----
13051	2571,	----
13052	/* BGEZL */	----
13053	2573,	----
13054	/* BGEZ_MM */	----
13055	2575,	----
13056	/* BGTZ */	----
13057	2577,	----
13058	/* BGTZ64 */	----
13059	2579,	----
13060	/* BGTZALC */	----
13061	2581,	----
13062	/* BGTZALC_MMR6 */	----
13063	2583,	----
13064	/* BGTZC */	----
13065	2585,	----
13066	/* BGTZC64 */	----
13067	2587,	----
13068	/* BGTZC_MMR6 */	----
13069	2589,	----
13070	/* BGTZL */	----
13071	2591,	----
13072	/* BGTZ_MM */	----
13073	2593,	----
13074	/* BINSLI_B */	----
13075	2595,	----
13076	/* BINSLI_D */	----
13077	2599,	----
13078	/* BINSLI_H */	----
13079	2603,	----
13080	/* BINSLI_W */	----
13081	2607,	----
13082	/* BINSL_B */	----
13083	2611,	----
13084	/* BINSL_D */	----
13085	2615,	----
13086	/* BINSL_H */	----
13087	2619,	----
13088	/* BINSL_W */	----
13089	2623,	----
13090	/* BINSRI_B */	----
13091	2627,	----
13092	/* BINSRI_D */	----
13093	2631,	----
13094	/* BINSRI_H */	----
13095	2635,	----
13096	/* BINSRI_W */	----
13097	2639,	----
13098	/* BINSR_B */	----
13099	2643,	----
13100	/* BINSR_D */	----
13101	2647,	----
13102	/* BINSR_H */	----
13103	2651,	----
13104	/* BINSR_W */	----
13105	2655,	----
13106	/* BITREV */	----
13107	2659,	----
13108	/* BITREV_MM */	----
13109	2661,	----
13110	/* BITSWAP */	----
13111	2663,	----
13112	/* BITSWAP_MMR6 */	----
13113	2665,	----
13114	/* BLEZ */	----
13115	2667,	----
13116	/* BLEZ64 */	----
13117	2669,	----
13118	/* BLEZALC */	----
13119	2671,	----
13120	/* BLEZALC_MMR6 */	----
13121	2673,	----
13122	/* BLEZC */	----
13123	2675,	----
13124	/* BLEZC64 */	----
13125	2677,	----
13126	/* BLEZC_MMR6 */	----
13127	2679,	----
13128	/* BLEZL */	----
13129	2681,	----
13130	/* BLEZ_MM */	----
13131	2683,	----
13132	/* BLTC */	----
13133	2685,	----
13134	/* BLTC64 */	----
13135	2688,	----
13136	/* BLTC_MMR6 */	----
13137	2691,	----
13138	/* BLTUC */	----
13139	2694,	----
13140	/* BLTUC64 */	----
13141	2697,	----
13142	/* BLTUC_MMR6 */	----
13143	2700,	----
13144	/* BLTZ */	----
13145	2703,	----
13146	/* BLTZ64 */	----
13147	2705,	----
13148	/* BLTZAL */	----
13149	2707,	----
13150	/* BLTZALC */	----
13151	2709,	----
13152	/* BLTZALC_MMR6 */	----
13153	2711,	----
13154	/* BLTZALL */	----
13155	2713,	----
13156	/* BLTZALS_MM */	----
13157	2715,	----
13158	/* BLTZAL_MM */	----
13159	2717,	----
13160	/* BLTZC */	----
13161	2719,	----
13162	/* BLTZC64 */	----
13163	2721,	----
13164	/* BLTZC_MMR6 */	----
13165	2723,	----
13166	/* BLTZL */	----
13167	2725,	----
13168	/* BLTZ_MM */	----
13169	2727,	----
13170	/* BMNZI_B */	----
13171	2729,	----
13172	/* BMNZ_V */	----
13173	2733,	----
13174	/* BMZI_B */	----
13175	2737,	----
13176	/* BMZ_V */	----
13177	2741,	----
13178	/* BNE */	----
13179	2745,	----
13180	/* BNE64 */	----
13181	2748,	----
13182	/* BNEC */	----
13183	2751,	----
13184	/* BNEC64 */	----
13185	2754,	----
13186	/* BNEC_MMR6 */	----
13187	2757,	----
13188	/* BNEGI_B */	----
13189	2760,	----
13190	/* BNEGI_D */	----
13191	2763,	----
13192	/* BNEGI_H */	----
13193	2766,	----
13194	/* BNEGI_W */	----
13195	2769,	----
13196	/* BNEG_B */	----
13197	2772,	----
13198	/* BNEG_D */	----
13199	2775,	----
13200	/* BNEG_H */	----
13201	2778,	----
13202	/* BNEG_W */	----
13203	2781,	----
13204	/* BNEL */	----
13205	2784,	----
13206	/* BNEZ16_MM */	----
13207	2787,	----
13208	/* BNEZALC */	----
13209	2789,	----
13210	/* BNEZALC_MMR6 */	----
13211	2791,	----
13212	/* BNEZC */	----
13213	2793,	----
13214	/* BNEZC16_MMR6 */	----
13215	2795,	----
13216	/* BNEZC64 */	----
13217	2797,	----
13218	/* BNEZC_MM */	----
13219	2799,	----
13220	/* BNEZC_MMR6 */	----
13221	2801,	----
13222	/* BNE_MM */	----
13223	2803,	----
13224	/* BNVC */	----
13225	2806,	----
13226	/* BNVC_MMR6 */	----
13227	2809,	----
13228	/* BNZ_B */	----
13229	2812,	----
13230	/* BNZ_D */	----
13231	2814,	----
13232	/* BNZ_H */	----
13233	2816,	----
13234	/* BNZ_V */	----
13235	2818,	----
13236	/* BNZ_W */	----
13237	2820,	----
13238	/* BOVC */	----
13239	2822,	----
13240	/* BOVC_MMR6 */	----
13241	2825,	----
13242	/* BPOSGE32 */	----
13243	2828,	----
13244	/* BPOSGE32C_MMR3 */	----
13245	2829,	----
13246	/* BPOSGE32_MM */	----
13247	2830,	----
13248	/* BREAK */	----
13249	2831,	----
13250	/* BREAK16_MM */	----
13251	2833,	----
13252	/* BREAK16_MMR6 */	----
13253	2834,	----
13254	/* BREAK_MM */	----
13255	2835,	----
13256	/* BREAK_MMR6 */	----
13257	2837,	----
13258	/* BSELI_B */	----
13259	2839,	----
13260	/* BSEL_V */	----
13261	2843,	----
13262	/* BSETI_B */	----
13263	2847,	----
13264	/* BSETI_D */	----
13265	2850,	----
13266	/* BSETI_H */	----
13267	2853,	----
13268	/* BSETI_W */	----
13269	2856,	----
13270	/* BSET_B */	----
13271	2859,	----
13272	/* BSET_D */	----
13273	2862,	----
13274	/* BSET_H */	----
13275	2865,	----
13276	/* BSET_W */	----
13277	2868,	----
13278	/* BZ_B */	----
13279	2871,	----
13280	/* BZ_D */	----
13281	2873,	----
13282	/* BZ_H */	----
13283	2875,	----
13284	/* BZ_V */	----
13285	2877,	----
13286	/* BZ_W */	----
13287	2879,	----
13288	/* BeqzRxImm16 */	----
13289	2881,	----
13290	/* BeqzRxImmX16 */	----
13291	2883,	----
13292	/* Bimm16 */	----
13293	2885,	----
13294	/* BimmX16 */	----
13295	2886,	----
13296	/* BnezRxImm16 */	----
13297	2887,	----
13298	/* BnezRxImmX16 */	----
13299	2889,	----
13300	/* Break16 */	----
13301	2891,	----
13302	/* Bteqz16 */	----
13303	2891,	----
13304	/* BteqzX16 */	----
13305	2892,	----
13306	/* Btnez16 */	----
13307	2893,	----
13308	/* BtnezX16 */	----
13309	2894,	----
13310	/* CACHE */	----
13311	2895,	----
13312	/* CACHEE */	----
13313	2898,	----
13314	/* CACHEE_MM */	----
13315	2901,	----
13316	/* CACHE_MM */	----
13317	2904,	----
13318	/* CACHE_MMR6 */	----
13319	2907,	----
13320	/* CACHE_R6 */	----
13321	2910,	----
13322	/* CEIL_L_D64 */	----
13323	2913,	----
13324	/* CEIL_L_D_MMR6 */	----
13325	2915,	----
13326	/* CEIL_L_S */	----
13327	2917,	----
13328	/* CEIL_L_S_MMR6 */	----
13329	2919,	----
13330	/* CEIL_W_D32 */	----
13331	2921,	----
13332	/* CEIL_W_D64 */	----
13333	2923,	----
13334	/* CEIL_W_D_MMR6 */	----
13335	2925,	----
13336	/* CEIL_W_MM */	----
13337	2927,	----
13338	/* CEIL_W_S */	----
13339	2929,	----
13340	/* CEIL_W_S_MM */	----
13341	2931,	----
13342	/* CEIL_W_S_MMR6 */	----
13343	2933,	----
13344	/* CEQI_B */	----
13345	2935,	----
13346	/* CEQI_D */	----
13347	2938,	----
13348	/* CEQI_H */	----
13349	2941,	----
13350	/* CEQI_W */	----
13351	2944,	----
13352	/* CEQ_B */	----
13353	2947,	----
13354	/* CEQ_D */	----
13355	2950,	----
13356	/* CEQ_H */	----
13357	2953,	----
13358	/* CEQ_W */	----
13359	2956,	----
13360	/* CFC1 */	----
13361	2959,	----
13362	/* CFC1_MM */	----
13363	2961,	----
13364	/* CFC2_MM */	----
13365	2963,	----
13366	/* CFCMSA */	----
13367	2965,	----
13368	/* CINS */	----
13369	2967,	----
13370	/* CINS32 */	----
13371	2971,	----
13372	/* CINS64_32 */	----
13373	2975,	----
13374	/* CINS_i32 */	----
13375	2979,	----
13376	/* CLASS_D */	----
13377	2983,	----
13378	/* CLASS_D_MMR6 */	----
13379	2985,	----
13380	/* CLASS_S */	----
13381	2987,	----
13382	/* CLASS_S_MMR6 */	----
13383	2989,	----
13384	/* CLEI_S_B */	----
13385	2991,	----
13386	/* CLEI_S_D */	----
13387	2994,	----
13388	/* CLEI_S_H */	----
13389	2997,	----
13390	/* CLEI_S_W */	----
13391	3000,	----
13392	/* CLEI_U_B */	----
13393	3003,	----
13394	/* CLEI_U_D */	----
13395	3006,	----
13396	/* CLEI_U_H */	----
13397	3009,	----
13398	/* CLEI_U_W */	----
13399	3012,	----
13400	/* CLE_S_B */	----
13401	3015,	----
13402	/* CLE_S_D */	----
13403	3018,	----
13404	/* CLE_S_H */	----
13405	3021,	----
13406	/* CLE_S_W */	----
13407	3024,	----
13408	/* CLE_U_B */	----
13409	3027,	----
13410	/* CLE_U_D */	----
13411	3030,	----
13412	/* CLE_U_H */	----
13413	3033,	----
13414	/* CLE_U_W */	----
13415	3036,	----
13416	/* CLO */	----
13417	3039,	----
13418	/* CLO_MM */	----
13419	3041,	----
13420	/* CLO_MMR6 */	----
13421	3043,	----
13422	/* CLO_R6 */	----
13423	3045,	----
13424	/* CLTI_S_B */	----
13425	3047,	----
13426	/* CLTI_S_D */	----
13427	3050,	----
13428	/* CLTI_S_H */	----
13429	3053,	----
13430	/* CLTI_S_W */	----
13431	3056,	----
13432	/* CLTI_U_B */	----
13433	3059,	----
13434	/* CLTI_U_D */	----
13435	3062,	----
13436	/* CLTI_U_H */	----
13437	3065,	----
13438	/* CLTI_U_W */	----
13439	3068,	----
13440	/* CLT_S_B */	----
13441	3071,	----
13442	/* CLT_S_D */	----
13443	3074,	----
13444	/* CLT_S_H */	----
13445	3077,	----
13446	/* CLT_S_W */	----
13447	3080,	----
13448	/* CLT_U_B */	----
13449	3083,	----
13450	/* CLT_U_D */	----
13451	3086,	----
13452	/* CLT_U_H */	----
13453	3089,	----
13454	/* CLT_U_W */	----
13455	3092,	----
13456	/* CLZ */	----
13457	3095,	----
13458	/* CLZ_MM */	----
13459	3097,	----
13460	/* CLZ_MMR6 */	----
13461	3099,	----
13462	/* CLZ_R6 */	----
13463	3101,	----
13464	/* CMPGDU_EQ_QB */	----
13465	3103,	----
13466	/* CMPGDU_EQ_QB_MMR2 */	----
13467	3106,	----
13468	/* CMPGDU_LE_QB */	----
13469	3109,	----
13470	/* CMPGDU_LE_QB_MMR2 */	----
13471	3112,	----
13472	/* CMPGDU_LT_QB */	----
13473	3115,	----
13474	/* CMPGDU_LT_QB_MMR2 */	----
13475	3118,	----
13476	/* CMPGU_EQ_QB */	----
13477	3121,	----
13478	/* CMPGU_EQ_QB_MM */	----
13479	3124,	----
13480	/* CMPGU_LE_QB */	----
13481	3127,	----
13482	/* CMPGU_LE_QB_MM */	----
13483	3130,	----
13484	/* CMPGU_LT_QB */	----
13485	3133,	----
13486	/* CMPGU_LT_QB_MM */	----
13487	3136,	----
13488	/* CMPU_EQ_QB */	----
13489	3139,	----
13490	/* CMPU_EQ_QB_MM */	----
13491	3141,	----
13492	/* CMPU_LE_QB */	----
13493	3143,	----
13494	/* CMPU_LE_QB_MM */	----
13495	3145,	----
13496	/* CMPU_LT_QB */	----
13497	3147,	----
13498	/* CMPU_LT_QB_MM */	----
13499	3149,	----
13500	/* CMP_AF_D_MMR6 */	----
13501	3151,	----
13502	/* CMP_AF_S_MMR6 */	----
13503	3154,	----
13504	/* CMP_EQ_D */	----
13505	3157,	----
13506	/* CMP_EQ_D_MMR6 */	----
13507	3160,	----
13508	/* CMP_EQ_PH */	----
13509	3163,	----
13510	/* CMP_EQ_PH_MM */	----
13511	3165,	----
13512	/* CMP_EQ_S */	----
13513	3167,	----
13514	/* CMP_EQ_S_MMR6 */	----
13515	3170,	----
13516	/* CMP_F_D */	----
13517	3173,	----
13518	/* CMP_F_S */	----
13519	3176,	----
13520	/* CMP_LE_D */	----
13521	3179,	----
13522	/* CMP_LE_D_MMR6 */	----
13523	3182,	----
13524	/* CMP_LE_PH */	----
13525	3185,	----
13526	/* CMP_LE_PH_MM */	----
13527	3187,	----
13528	/* CMP_LE_S */	----
13529	3189,	----
13530	/* CMP_LE_S_MMR6 */	----
13531	3192,	----
13532	/* CMP_LT_D */	----
13533	3195,	----
13534	/* CMP_LT_D_MMR6 */	----
13535	3198,	----
13536	/* CMP_LT_PH */	----
13537	3201,	----
13538	/* CMP_LT_PH_MM */	----
13539	3203,	----
13540	/* CMP_LT_S */	----
13541	3205,	----
13542	/* CMP_LT_S_MMR6 */	----
13543	3208,	----
13544	/* CMP_SAF_D */	----
13545	3211,	----
13546	/* CMP_SAF_D_MMR6 */	----
13547	3214,	----
13548	/* CMP_SAF_S */	----
13549	3217,	----
13550	/* CMP_SAF_S_MMR6 */	----
13551	3220,	----
13552	/* CMP_SEQ_D */	----
13553	3223,	----
13554	/* CMP_SEQ_D_MMR6 */	----
13555	3226,	----
13556	/* CMP_SEQ_S */	----
13557	3229,	----
13558	/* CMP_SEQ_S_MMR6 */	----
13559	3232,	----
13560	/* CMP_SLE_D */	----
13561	3235,	----
13562	/* CMP_SLE_D_MMR6 */	----
13563	3238,	----
13564	/* CMP_SLE_S */	----
13565	3241,	----
13566	/* CMP_SLE_S_MMR6 */	----
13567	3244,	----
13568	/* CMP_SLT_D */	----
13569	3247,	----
13570	/* CMP_SLT_D_MMR6 */	----
13571	3250,	----
13572	/* CMP_SLT_S */	----
13573	3253,	----
13574	/* CMP_SLT_S_MMR6 */	----
13575	3256,	----
13576	/* CMP_SUEQ_D */	----
13577	3259,	----
13578	/* CMP_SUEQ_D_MMR6 */	----
13579	3262,	----
13580	/* CMP_SUEQ_S */	----
13581	3265,	----
13582	/* CMP_SUEQ_S_MMR6 */	----
13583	3268,	----
13584	/* CMP_SULE_D */	----
13585	3271,	----
13586	/* CMP_SULE_D_MMR6 */	----
13587	3274,	----
13588	/* CMP_SULE_S */	----
13589	3277,	----
13590	/* CMP_SULE_S_MMR6 */	----
13591	3280,	----
13592	/* CMP_SULT_D */	----
13593	3283,	----
13594	/* CMP_SULT_D_MMR6 */	----
13595	3286,	----
13596	/* CMP_SULT_S */	----
13597	3289,	----
13598	/* CMP_SULT_S_MMR6 */	----
13599	3292,	----
13600	/* CMP_SUN_D */	----
13601	3295,	----
13602	/* CMP_SUN_D_MMR6 */	----
13603	3298,	----
13604	/* CMP_SUN_S */	----
13605	3301,	----
13606	/* CMP_SUN_S_MMR6 */	----
13607	3304,	----
13608	/* CMP_UEQ_D */	----
13609	3307,	----
13610	/* CMP_UEQ_D_MMR6 */	----
13611	3310,	----
13612	/* CMP_UEQ_S */	----
13613	3313,	----
13614	/* CMP_UEQ_S_MMR6 */	----
13615	3316,	----
13616	/* CMP_ULE_D */	----
13617	3319,	----
13618	/* CMP_ULE_D_MMR6 */	----
13619	3322,	----
13620	/* CMP_ULE_S */	----
13621	3325,	----
13622	/* CMP_ULE_S_MMR6 */	----
13623	3328,	----
13624	/* CMP_ULT_D */	----
13625	3331,	----
13626	/* CMP_ULT_D_MMR6 */	----
13627	3334,	----
13628	/* CMP_ULT_S */	----
13629	3337,	----
13630	/* CMP_ULT_S_MMR6 */	----
13631	3340,	----
13632	/* CMP_UN_D */	----
13633	3343,	----
13634	/* CMP_UN_D_MMR6 */	----
13635	3346,	----
13636	/* CMP_UN_S */	----
13637	3349,	----
13638	/* CMP_UN_S_MMR6 */	----
13639	3352,	----
13640	/* COPY_S_B */	----
13641	3355,	----
13642	/* COPY_S_D */	----
13643	3358,	----
13644	/* COPY_S_H */	----
13645	3361,	----
13646	/* COPY_S_W */	----
13647	3364,	----
13648	/* COPY_U_B */	----
13649	3367,	----
13650	/* COPY_U_H */	----
13651	3370,	----
13652	/* COPY_U_W */	----
13653	3373,	----
13654	/* CRC32B */	----
13655	3376,	----
13656	/* CRC32CB */	----
13657	3379,	----
13658	/* CRC32CD */	----
13659	3382,	----
13660	/* CRC32CH */	----
13661	3385,	----
13662	/* CRC32CW */	----
13663	3388,	----
13664	/* CRC32D */	----
13665	3391,	----
13666	/* CRC32H */	----
13667	3394,	----
13668	/* CRC32W */	----
13669	3397,	----
13670	/* CTC1 */	----
13671	3400,	----
13672	/* CTC1_MM */	----
13673	3402,	----
13674	/* CTC2_MM */	----
13675	3404,	----
13676	/* CTCMSA */	----
13677	3406,	----
13678	/* CVT_D32_S */	----
13679	3408,	----
13680	/* CVT_D32_S_MM */	----
13681	3410,	----
13682	/* CVT_D32_W */	----
13683	3412,	----
13684	/* CVT_D32_W_MM */	----
13685	3414,	----
13686	/* CVT_D64_L */	----
13687	3416,	----
13688	/* CVT_D64_S */	----
13689	3418,	----
13690	/* CVT_D64_S_MM */	----
13691	3420,	----
13692	/* CVT_D64_W */	----
13693	3422,	----
13694	/* CVT_D64_W_MM */	----
13695	3424,	----
13696	/* CVT_D_L_MMR6 */	----
13697	3426,	----
13698	/* CVT_L_D64 */	----
13699	3428,	----
13700	/* CVT_L_D64_MM */	----
13701	3430,	----
13702	/* CVT_L_D_MMR6 */	----
13703	3432,	----
13704	/* CVT_L_S */	----
13705	3434,	----
13706	/* CVT_L_S_MM */	----
13707	3436,	----
13708	/* CVT_L_S_MMR6 */	----
13709	3438,	----
13710	/* CVT_PS_PW64 */	----
13711	3440,	----
13712	/* CVT_PS_S64 */	----
13713	3442,	----
13714	/* CVT_PW_PS64 */	----
13715	3445,	----
13716	/* CVT_S_D32 */	----
13717	3447,	----
13718	/* CVT_S_D32_MM */	----
13719	3449,	----
13720	/* CVT_S_D64 */	----
13721	3451,	----
13722	/* CVT_S_D64_MM */	----
13723	3453,	----
13724	/* CVT_S_L */	----
13725	3455,	----
13726	/* CVT_S_L_MMR6 */	----
13727	3457,	----
13728	/* CVT_S_PL64 */	----
13729	3459,	----
13730	/* CVT_S_PU64 */	----
13731	3461,	----
13732	/* CVT_S_W */	----
13733	3463,	----
13734	/* CVT_S_W_MM */	----
13735	3465,	----
13736	/* CVT_S_W_MMR6 */	----
13737	3467,	----
13738	/* CVT_W_D32 */	----
13739	3469,	----
13740	/* CVT_W_D32_MM */	----
13741	3471,	----
13742	/* CVT_W_D64 */	----
13743	3473,	----
13744	/* CVT_W_D64_MM */	----
13745	3475,	----
13746	/* CVT_W_S */	----
13747	3477,	----
13748	/* CVT_W_S_MM */	----
13749	3479,	----
13750	/* CVT_W_S_MMR6 */	----
13751	3481,	----
13752	/* C_EQ_D32 */	----
13753	3483,	----
13754	/* C_EQ_D32_MM */	----
13755	3486,	----
13756	/* C_EQ_D64 */	----
13757	3489,	----
13758	/* C_EQ_D64_MM */	----
13759	3492,	----
13760	/* C_EQ_S */	----
13761	3495,	----
13762	/* C_EQ_S_MM */	----
13763	3498,	----
13764	/* C_F_D32 */	----
13765	3501,	----
13766	/* C_F_D32_MM */	----
13767	3504,	----
13768	/* C_F_D64 */	----
13769	3507,	----
13770	/* C_F_D64_MM */	----
13771	3510,	----
13772	/* C_F_S */	----
13773	3513,	----
13774	/* C_F_S_MM */	----
13775	3516,	----
13776	/* C_LE_D32 */	----
13777	3519,	----
13778	/* C_LE_D32_MM */	----
13779	3522,	----
13780	/* C_LE_D64 */	----
13781	3525,	----
13782	/* C_LE_D64_MM */	----
13783	3528,	----
13784	/* C_LE_S */	----
13785	3531,	----
13786	/* C_LE_S_MM */	----
13787	3534,	----
13788	/* C_LT_D32 */	----
13789	3537,	----
13790	/* C_LT_D32_MM */	----
13791	3540,	----
13792	/* C_LT_D64 */	----
13793	3543,	----
13794	/* C_LT_D64_MM */	----
13795	3546,	----
13796	/* C_LT_S */	----
13797	3549,	----
13798	/* C_LT_S_MM */	----
13799	3552,	----
13800	/* C_NGE_D32 */	----
13801	3555,	----
13802	/* C_NGE_D32_MM */	----
13803	3558,	----
13804	/* C_NGE_D64 */	----
13805	3561,	----
13806	/* C_NGE_D64_MM */	----
13807	3564,	----
13808	/* C_NGE_S */	----
13809	3567,	----
13810	/* C_NGE_S_MM */	----
13811	3570,	----
13812	/* C_NGLE_D32 */	----
13813	3573,	----
13814	/* C_NGLE_D32_MM */	----
13815	3576,	----
13816	/* C_NGLE_D64 */	----
13817	3579,	----
13818	/* C_NGLE_D64_MM */	----
13819	3582,	----
13820	/* C_NGLE_S */	----
13821	3585,	----
13822	/* C_NGLE_S_MM */	----
13823	3588,	----
13824	/* C_NGL_D32 */	----
13825	3591,	----
13826	/* C_NGL_D32_MM */	----
13827	3594,	----
13828	/* C_NGL_D64 */	----
13829	3597,	----
13830	/* C_NGL_D64_MM */	----
13831	3600,	----
13832	/* C_NGL_S */	----
13833	3603,	----
13834	/* C_NGL_S_MM */	----
13835	3606,	----
13836	/* C_NGT_D32 */	----
13837	3609,	----
13838	/* C_NGT_D32_MM */	----
13839	3612,	----
13840	/* C_NGT_D64 */	----
13841	3615,	----
13842	/* C_NGT_D64_MM */	----
13843	3618,	----
13844	/* C_NGT_S */	----
13845	3621,	----
13846	/* C_NGT_S_MM */	----
13847	3624,	----
13848	/* C_OLE_D32 */	----
13849	3627,	----
13850	/* C_OLE_D32_MM */	----
13851	3630,	----
13852	/* C_OLE_D64 */	----
13853	3633,	----
13854	/* C_OLE_D64_MM */	----
13855	3636,	----
13856	/* C_OLE_S */	----
13857	3639,	----
13858	/* C_OLE_S_MM */	----
13859	3642,	----
13860	/* C_OLT_D32 */	----
13861	3645,	----
13862	/* C_OLT_D32_MM */	----
13863	3648,	----
13864	/* C_OLT_D64 */	----
13865	3651,	----
13866	/* C_OLT_D64_MM */	----
13867	3654,	----
13868	/* C_OLT_S */	----
13869	3657,	----
13870	/* C_OLT_S_MM */	----
13871	3660,	----
13872	/* C_SEQ_D32 */	----
13873	3663,	----
13874	/* C_SEQ_D32_MM */	----
13875	3666,	----
13876	/* C_SEQ_D64 */	----
13877	3669,	----
13878	/* C_SEQ_D64_MM */	----
13879	3672,	----
13880	/* C_SEQ_S */	----
13881	3675,	----
13882	/* C_SEQ_S_MM */	----
13883	3678,	----
13884	/* C_SF_D32 */	----
13885	3681,	----
13886	/* C_SF_D32_MM */	----
13887	3684,	----
13888	/* C_SF_D64 */	----
13889	3687,	----
13890	/* C_SF_D64_MM */	----
13891	3690,	----
13892	/* C_SF_S */	----
13893	3693,	----
13894	/* C_SF_S_MM */	----
13895	3696,	----
13896	/* C_UEQ_D32 */	----
13897	3699,	----
13898	/* C_UEQ_D32_MM */	----
13899	3702,	----
13900	/* C_UEQ_D64 */	----
13901	3705,	----
13902	/* C_UEQ_D64_MM */	----
13903	3708,	----
13904	/* C_UEQ_S */	----
13905	3711,	----
13906	/* C_UEQ_S_MM */	----
13907	3714,	----
13908	/* C_ULE_D32 */	----
13909	3717,	----
13910	/* C_ULE_D32_MM */	----
13911	3720,	----
13912	/* C_ULE_D64 */	----
13913	3723,	----
13914	/* C_ULE_D64_MM */	----
13915	3726,	----
13916	/* C_ULE_S */	----
13917	3729,	----
13918	/* C_ULE_S_MM */	----
13919	3732,	----
13920	/* C_ULT_D32 */	----
13921	3735,	----
13922	/* C_ULT_D32_MM */	----
13923	3738,	----
13924	/* C_ULT_D64 */	----
13925	3741,	----
13926	/* C_ULT_D64_MM */	----
13927	3744,	----
13928	/* C_ULT_S */	----
13929	3747,	----
13930	/* C_ULT_S_MM */	----
13931	3750,	----
13932	/* C_UN_D32 */	----
13933	3753,	----
13934	/* C_UN_D32_MM */	----
13935	3756,	----
13936	/* C_UN_D64 */	----
13937	3759,	----
13938	/* C_UN_D64_MM */	----
13939	3762,	----
13940	/* C_UN_S */	----
13941	3765,	----
13942	/* C_UN_S_MM */	----
13943	3768,	----
13944	/* CmpRxRy16 */	----
13945	3771,	----
13946	/* CmpiRxImm16 */	----
13947	3773,	----
13948	/* CmpiRxImmX16 */	----
13949	3775,	----
13950	/* DADD */	----
13951	3777,	----
13952	/* DADDi */	----
13953	3780,	----
13954	/* DADDiu */	----
13955	3783,	----
13956	/* DADDu */	----
13957	3786,	----
13958	/* DAHI */	----
13959	3789,	----
13960	/* DALIGN */	----
13961	3792,	----
13962	/* DATI */	----
13963	3796,	----
13964	/* DAUI */	----
13965	3799,	----
13966	/* DBITSWAP */	----
13967	3802,	----
13968	/* DCLO */	----
13969	3804,	----
13970	/* DCLO_R6 */	----
13971	3806,	----
13972	/* DCLZ */	----
13973	3808,	----
13974	/* DCLZ_R6 */	----
13975	3810,	----
13976	/* DDIV */	----
13977	3812,	----
13978	/* DDIVU */	----
13979	3815,	----
13980	/* DERET */	----
13981	3818,	----
13982	/* DERET_MM */	----
13983	3818,	----
13984	/* DERET_MMR6 */	----
13985	3818,	----
13986	/* DEXT */	----
13987	3818,	----
13988	/* DEXT64_32 */	----
13989	3822,	----
13990	/* DEXTM */	----
13991	3826,	----
13992	/* DEXTU */	----
13993	3830,	----
13994	/* DI */	----
13995	3834,	----
13996	/* DINS */	----
13997	3835,	----
13998	/* DINSM */	----
13999	3840,	----
14000	/* DINSU */	----
14001	3845,	----
14002	/* DIV */	----
14003	3850,	----
14004	/* DIVU */	----
14005	3853,	----
14006	/* DIVU_MMR6 */	----
14007	3856,	----
14008	/* DIV_MMR6 */	----
14009	3859,	----
14010	/* DIV_S_B */	----
14011	3862,	----
14012	/* DIV_S_D */	----
14013	3865,	----
14014	/* DIV_S_H */	----
14015	3868,	----
14016	/* DIV_S_W */	----
14017	3871,	----
14018	/* DIV_U_B */	----
14019	3874,	----
14020	/* DIV_U_D */	----
14021	3877,	----
14022	/* DIV_U_H */	----
14023	3880,	----
14024	/* DIV_U_W */	----
14025	3883,	----
14026	/* DI_MM */	----
14027	3886,	----
14028	/* DI_MMR6 */	----
14029	3887,	----
14030	/* DLSA */	----
14031	3888,	----
14032	/* DLSA_R6 */	----
14033	3892,	----
14034	/* DMFC0 */	----
14035	3896,	----
14036	/* DMFC1 */	----
14037	3899,	----
14038	/* DMFC2 */	----
14039	3901,	----
14040	/* DMFC2_OCTEON */	----
14041	3904,	----
14042	/* DMFGC0 */	----
14043	3906,	----
14044	/* DMOD */	----
14045	3909,	----
14046	/* DMODU */	----
14047	3912,	----
14048	/* DMT */	----
14049	3915,	----
14050	/* DMTC0 */	----
14051	3916,	----
14052	/* DMTC1 */	----
14053	3919,	----
14054	/* DMTC2 */	----
14055	3921,	----
14056	/* DMTC2_OCTEON */	----
14057	3924,	----
14058	/* DMTGC0 */	----
14059	3926,	----
14060	/* DMUH */	----
14061	3929,	----
14062	/* DMUHU */	----
14063	3932,	----
14064	/* DMUL */	----
14065	3935,	----
14066	/* DMULT */	----
14067	3938,	----
14068	/* DMULTu */	----
14069	3940,	----
14070	/* DMULU */	----
14071	3942,	----
14072	/* DMUL_R6 */	----
14073	3945,	----
14074	/* DOTP_S_D */	----
14075	3948,	----
14076	/* DOTP_S_H */	----
14077	3951,	----
14078	/* DOTP_S_W */	----
14079	3954,	----
14080	/* DOTP_U_D */	----
14081	3957,	----
14082	/* DOTP_U_H */	----
14083	3960,	----
14084	/* DOTP_U_W */	----
14085	3963,	----
14086	/* DPADD_S_D */	----
14087	3966,	----
14088	/* DPADD_S_H */	----
14089	3970,	----
14090	/* DPADD_S_W */	----
14091	3974,	----
14092	/* DPADD_U_D */	----
14093	3978,	----
14094	/* DPADD_U_H */	----
14095	3982,	----
14096	/* DPADD_U_W */	----
14097	3986,	----
14098	/* DPAQX_SA_W_PH */	----
14099	3990,	----
14100	/* DPAQX_SA_W_PH_MMR2 */	----
14101	3994,	----
14102	/* DPAQX_S_W_PH */	----
14103	3998,	----
14104	/* DPAQX_S_W_PH_MMR2 */	----
14105	4002,	----
14106	/* DPAQ_SA_L_W */	----
14107	4006,	----
14108	/* DPAQ_SA_L_W_MM */	----
14109	4010,	----
14110	/* DPAQ_S_W_PH */	----
14111	4014,	----
14112	/* DPAQ_S_W_PH_MM */	----
14113	4018,	----
14114	/* DPAU_H_QBL */	----
14115	4022,	----
14116	/* DPAU_H_QBL_MM */	----
14117	4026,	----
14118	/* DPAU_H_QBR */	----
14119	4030,	----
14120	/* DPAU_H_QBR_MM */	----
14121	4034,	----
14122	/* DPAX_W_PH */	----
14123	4038,	----
14124	/* DPAX_W_PH_MMR2 */	----
14125	4042,	----
14126	/* DPA_W_PH */	----
14127	4046,	----
14128	/* DPA_W_PH_MMR2 */	----
14129	4050,	----
14130	/* DPOP */	----
14131	4054,	----
14132	/* DPSQX_SA_W_PH */	----
14133	4056,	----
14134	/* DPSQX_SA_W_PH_MMR2 */	----
14135	4060,	----
14136	/* DPSQX_S_W_PH */	----
14137	4064,	----
14138	/* DPSQX_S_W_PH_MMR2 */	----
14139	4068,	----
14140	/* DPSQ_SA_L_W */	----
14141	4072,	----
14142	/* DPSQ_SA_L_W_MM */	----
14143	4076,	----
14144	/* DPSQ_S_W_PH */	----
14145	4080,	----
14146	/* DPSQ_S_W_PH_MM */	----
14147	4084,	----
14148	/* DPSUB_S_D */	----
14149	4088,	----
14150	/* DPSUB_S_H */	----
14151	4092,	----
14152	/* DPSUB_S_W */	----
14153	4096,	----
14154	/* DPSUB_U_D */	----
14155	4100,	----
14156	/* DPSUB_U_H */	----
14157	4104,	----
14158	/* DPSUB_U_W */	----
14159	4108,	----
14160	/* DPSU_H_QBL */	----
14161	4112,	----
14162	/* DPSU_H_QBL_MM */	----
14163	4116,	----
14164	/* DPSU_H_QBR */	----
14165	4120,	----
14166	/* DPSU_H_QBR_MM */	----
14167	4124,	----
14168	/* DPSX_W_PH */	----
14169	4128,	----
14170	/* DPSX_W_PH_MMR2 */	----
14171	4132,	----
14172	/* DPS_W_PH */	----
14173	4136,	----
14174	/* DPS_W_PH_MMR2 */	----
14175	4140,	----
14176	/* DROTR */	----
14177	4144,	----
14178	/* DROTR32 */	----
14179	4147,	----
14180	/* DROTRV */	----
14181	4150,	----
14182	/* DSBH */	----
14183	4153,	----
14184	/* DSDIV */	----
14185	4155,	----
14186	/* DSHD */	----
14187	4157,	----
14188	/* DSLL */	----
14189	4159,	----
14190	/* DSLL32 */	----
14191	4162,	----
14192	/* DSLL64_32 */	----
14193	4165,	----
14194	/* DSLLV */	----
14195	4167,	----
14196	/* DSRA */	----
14197	4170,	----
14198	/* DSRA32 */	----
14199	4173,	----
14200	/* DSRAV */	----
14201	4176,	----
14202	/* DSRL */	----
14203	4179,	----
14204	/* DSRL32 */	----
14205	4182,	----
14206	/* DSRLV */	----
14207	4185,	----
14208	/* DSUB */	----
14209	4188,	----
14210	/* DSUBu */	----
14211	4191,	----
14212	/* DUDIV */	----
14213	4194,	----
14214	/* DVP */	----
14215	4196,	----
14216	/* DVPE */	----
14217	4197,	----
14218	/* DVP_MMR6 */	----
14219	4198,	----
14220	/* DivRxRy16 */	----
14221	4199,	----
14222	/* DivuRxRy16 */	----
14223	4201,	----
14224	/* EHB */	----
14225	4203,	----
14226	/* EHB_MM */	----
14227	4203,	----
14228	/* EHB_MMR6 */	----
14229	4203,	----
14230	/* EI */	----
14231	4203,	----
14232	/* EI_MM */	----
14233	4204,	----
14234	/* EI_MMR6 */	----
14235	4205,	----
14236	/* EMT */	----
14237	4206,	----
14238	/* ERET */	----
14239	4207,	----
14240	/* ERETNC */	----
14241	4207,	----
14242	/* ERETNC_MMR6 */	----
14243	4207,	----
14244	/* ERET_MM */	----
14245	4207,	----
14246	/* ERET_MMR6 */	----
14247	4207,	----
14248	/* EVP */	----
14249	4207,	----
14250	/* EVPE */	----
14251	4208,	----
14252	/* EVP_MMR6 */	----
14253	4209,	----
14254	/* EXT */	----
14255	4210,	----
14256	/* EXTP */	----
14257	4214,	----
14258	/* EXTPDP */	----
14259	4217,	----
14260	/* EXTPDPV */	----
14261	4220,	----
14262	/* EXTPDPV_MM */	----
14263	4223,	----
14264	/* EXTPDP_MM */	----
14265	4226,	----
14266	/* EXTPV */	----
14267	4229,	----
14268	/* EXTPV_MM */	----
14269	4232,	----
14270	/* EXTP_MM */	----
14271	4235,	----
14272	/* EXTRV_RS_W */	----
14273	4238,	----
14274	/* EXTRV_RS_W_MM */	----
14275	4241,	----
14276	/* EXTRV_R_W */	----
14277	4244,	----
14278	/* EXTRV_R_W_MM */	----
14279	4247,	----
14280	/* EXTRV_S_H */	----
14281	4250,	----
14282	/* EXTRV_S_H_MM */	----
14283	4253,	----
14284	/* EXTRV_W */	----
14285	4256,	----
14286	/* EXTRV_W_MM */	----
14287	4259,	----
14288	/* EXTR_RS_W */	----
14289	4262,	----
14290	/* EXTR_RS_W_MM */	----
14291	4265,	----
14292	/* EXTR_R_W */	----
14293	4268,	----
14294	/* EXTR_R_W_MM */	----
14295	4271,	----
14296	/* EXTR_S_H */	----
14297	4274,	----
14298	/* EXTR_S_H_MM */	----
14299	4277,	----
14300	/* EXTR_W */	----
14301	4280,	----
14302	/* EXTR_W_MM */	----
14303	4283,	----
14304	/* EXTS */	----
14305	4286,	----
14306	/* EXTS32 */	----
14307	4290,	----
14308	/* EXT_MM */	----
14309	4294,	----
14310	/* EXT_MMR6 */	----
14311	4298,	----
14312	/* FABS_D32 */	----
14313	4302,	----
14314	/* FABS_D32_MM */	----
14315	4304,	----
14316	/* FABS_D64 */	----
14317	4306,	----
14318	/* FABS_D64_MM */	----
14319	4308,	----
14320	/* FABS_S */	----
14321	4310,	----
14322	/* FABS_S_MM */	----
14323	4312,	----
14324	/* FADD_D */	----
14325	4314,	----
14326	/* FADD_D32 */	----
14327	4317,	----
14328	/* FADD_D32_MM */	----
14329	4320,	----
14330	/* FADD_D64 */	----
14331	4323,	----
14332	/* FADD_D64_MM */	----
14333	4326,	----
14334	/* FADD_PS64 */	----
14335	4329,	----
14336	/* FADD_S */	----
14337	4332,	----
14338	/* FADD_S_MM */	----
14339	4335,	----
14340	/* FADD_S_MMR6 */	----
14341	4338,	----
14342	/* FADD_W */	----
14343	4341,	----
14344	/* FCAF_D */	----
14345	4344,	----
14346	/* FCAF_W */	----
14347	4347,	----
14348	/* FCEQ_D */	----
14349	4350,	----
14350	/* FCEQ_W */	----
14351	4353,	----
14352	/* FCLASS_D */	----
14353	4356,	----
14354	/* FCLASS_W */	----
14355	4358,	----
14356	/* FCLE_D */	----
14357	4360,	----
14358	/* FCLE_W */	----
14359	4363,	----
14360	/* FCLT_D */	----
14361	4366,	----
14362	/* FCLT_W */	----
14363	4369,	----
14364	/* FCMP_D32 */	----
14365	4372,	----
14366	/* FCMP_D32_MM */	----
14367	4375,	----
14368	/* FCMP_D64 */	----
14369	4378,	----
14370	/* FCMP_S32 */	----
14371	4381,	----
14372	/* FCMP_S32_MM */	----
14373	4384,	----
14374	/* FCNE_D */	----
14375	4387,	----
14376	/* FCNE_W */	----
14377	4390,	----
14378	/* FCOR_D */	----
14379	4393,	----
14380	/* FCOR_W */	----
14381	4396,	----
14382	/* FCUEQ_D */	----
14383	4399,	----
14384	/* FCUEQ_W */	----
14385	4402,	----
14386	/* FCULE_D */	----
14387	4405,	----
14388	/* FCULE_W */	----
14389	4408,	----
14390	/* FCULT_D */	----
14391	4411,	----
14392	/* FCULT_W */	----
14393	4414,	----
14394	/* FCUNE_D */	----
14395	4417,	----
14396	/* FCUNE_W */	----
14397	4420,	----
14398	/* FCUN_D */	----
14399	4423,	----
14400	/* FCUN_W */	----
14401	4426,	----
14402	/* FDIV_D */	----
14403	4429,	----
14404	/* FDIV_D32 */	----
14405	4432,	----
14406	/* FDIV_D32_MM */	----
14407	4435,	----
14408	/* FDIV_D64 */	----
14409	4438,	----
14410	/* FDIV_D64_MM */	----
14411	4441,	----
14412	/* FDIV_S */	----
14413	4444,	----
14414	/* FDIV_S_MM */	----
14415	4447,	----
14416	/* FDIV_S_MMR6 */	----
14417	4450,	----
14418	/* FDIV_W */	----
14419	4453,	----
14420	/* FEXDO_H */	----
14421	4456,	----
14422	/* FEXDO_W */	----
14423	4459,	----
14424	/* FEXP2_D */	----
14425	4462,	----
14426	/* FEXP2_W */	----
14427	4465,	----
14428	/* FEXUPL_D */	----
14429	4468,	----
14430	/* FEXUPL_W */	----
14431	4470,	----
14432	/* FEXUPR_D */	----
14433	4472,	----
14434	/* FEXUPR_W */	----
14435	4474,	----
14436	/* FFINT_S_D */	----
14437	4476,	----
14438	/* FFINT_S_W */	----
14439	4478,	----
14440	/* FFINT_U_D */	----
14441	4480,	----
14442	/* FFINT_U_W */	----
14443	4482,	----
14444	/* FFQL_D */	----
14445	4484,	----
14446	/* FFQL_W */	----
14447	4486,	----
14448	/* FFQR_D */	----
14449	4488,	----
14450	/* FFQR_W */	----
14451	4490,	----
14452	/* FILL_B */	----
14453	4492,	----
14454	/* FILL_D */	----
14455	4494,	----
14456	/* FILL_H */	----
14457	4496,	----
14458	/* FILL_W */	----
14459	4498,	----
14460	/* FLOG2_D */	----
14461	4500,	----
14462	/* FLOG2_W */	----
14463	4502,	----
14464	/* FLOOR_L_D64 */	----
14465	4504,	----
14466	/* FLOOR_L_D_MMR6 */	----
14467	4506,	----
14468	/* FLOOR_L_S */	----
14469	4508,	----
14470	/* FLOOR_L_S_MMR6 */	----
14471	4510,	----
14472	/* FLOOR_W_D32 */	----
14473	4512,	----
14474	/* FLOOR_W_D64 */	----
14475	4514,	----
14476	/* FLOOR_W_D_MMR6 */	----
14477	4516,	----
14478	/* FLOOR_W_MM */	----
14479	4518,	----
14480	/* FLOOR_W_S */	----
14481	4520,	----
14482	/* FLOOR_W_S_MM */	----
14483	4522,	----
14484	/* FLOOR_W_S_MMR6 */	----
14485	4524,	----
14486	/* FMADD_D */	----
14487	4526,	----
14488	/* FMADD_W */	----
14489	4530,	----
14490	/* FMAX_A_D */	----
14491	4534,	----
14492	/* FMAX_A_W */	----
14493	4537,	----
14494	/* FMAX_D */	----
14495	4540,	----
14496	/* FMAX_W */	----
14497	4543,	----
14498	/* FMIN_A_D */	----
14499	4546,	----
14500	/* FMIN_A_W */	----
14501	4549,	----
14502	/* FMIN_D */	----
14503	4552,	----
14504	/* FMIN_W */	----
14505	4555,	----
14506	/* FMOV_D32 */	----
14507	4558,	----
14508	/* FMOV_D32_MM */	----
14509	4560,	----
14510	/* FMOV_D64 */	----
14511	4562,	----
14512	/* FMOV_D64_MM */	----
14513	4564,	----
14514	/* FMOV_D_MMR6 */	----
14515	4566,	----
14516	/* FMOV_S */	----
14517	4568,	----
14518	/* FMOV_S_MM */	----
14519	4570,	----
14520	/* FMOV_S_MMR6 */	----
14521	4572,	----
14522	/* FMSUB_D */	----
14523	4574,	----
14524	/* FMSUB_W */	----
14525	4578,	----
14526	/* FMUL_D */	----
14527	4582,	----
14528	/* FMUL_D32 */	----
14529	4585,	----
14530	/* FMUL_D32_MM */	----
14531	4588,	----
14532	/* FMUL_D64 */	----
14533	4591,	----
14534	/* FMUL_D64_MM */	----
14535	4594,	----
14536	/* FMUL_PS64 */	----
14537	4597,	----
14538	/* FMUL_S */	----
14539	4600,	----
14540	/* FMUL_S_MM */	----
14541	4603,	----
14542	/* FMUL_S_MMR6 */	----
14543	4606,	----
14544	/* FMUL_W */	----
14545	4609,	----
14546	/* FNEG_D32 */	----
14547	4612,	----
14548	/* FNEG_D32_MM */	----
14549	4614,	----
14550	/* FNEG_D64 */	----
14551	4616,	----
14552	/* FNEG_D64_MM */	----
14553	4618,	----
14554	/* FNEG_S */	----
14555	4620,	----
14556	/* FNEG_S_MM */	----
14557	4622,	----
14558	/* FNEG_S_MMR6 */	----
14559	4624,	----
14560	/* FORK */	----
14561	4626,	----
14562	/* FRCP_D */	----
14563	4629,	----
14564	/* FRCP_W */	----
14565	4631,	----
14566	/* FRINT_D */	----
14567	4633,	----
14568	/* FRINT_W */	----
14569	4635,	----
14570	/* FRSQRT_D */	----
14571	4637,	----
14572	/* FRSQRT_W */	----
14573	4639,	----
14574	/* FSAF_D */	----
14575	4641,	----
14576	/* FSAF_W */	----
14577	4644,	----
14578	/* FSEQ_D */	----
14579	4647,	----
14580	/* FSEQ_W */	----
14581	4650,	----
14582	/* FSLE_D */	----
14583	4653,	----
14584	/* FSLE_W */	----
14585	4656,	----
14586	/* FSLT_D */	----
14587	4659,	----
14588	/* FSLT_W */	----
14589	4662,	----
14590	/* FSNE_D */	----
14591	4665,	----
14592	/* FSNE_W */	----
14593	4668,	----
14594	/* FSOR_D */	----
14595	4671,	----
14596	/* FSOR_W */	----
14597	4674,	----
14598	/* FSQRT_D */	----
14599	4677,	----
14600	/* FSQRT_D32 */	----
14601	4679,	----
14602	/* FSQRT_D32_MM */	----
14603	4681,	----
14604	/* FSQRT_D64 */	----
14605	4683,	----
14606	/* FSQRT_D64_MM */	----
14607	4685,	----
14608	/* FSQRT_S */	----
14609	4687,	----
14610	/* FSQRT_S_MM */	----
14611	4689,	----
14612	/* FSQRT_W */	----
14613	4691,	----
14614	/* FSUB_D */	----
14615	4693,	----
14616	/* FSUB_D32 */	----
14617	4696,	----
14618	/* FSUB_D32_MM */	----
14619	4699,	----
14620	/* FSUB_D64 */	----
14621	4702,	----
14622	/* FSUB_D64_MM */	----
14623	4705,	----
14624	/* FSUB_PS64 */	----
14625	4708,	----
14626	/* FSUB_S */	----
14627	4711,	----
14628	/* FSUB_S_MM */	----
14629	4714,	----
14630	/* FSUB_S_MMR6 */	----
14631	4717,	----
14632	/* FSUB_W */	----
14633	4720,	----
14634	/* FSUEQ_D */	----
14635	4723,	----
14636	/* FSUEQ_W */	----
14637	4726,	----
14638	/* FSULE_D */	----
14639	4729,	----
14640	/* FSULE_W */	----
14641	4732,	----
14642	/* FSULT_D */	----
14643	4735,	----
14644	/* FSULT_W */	----
14645	4738,	----
14646	/* FSUNE_D */	----
14647	4741,	----
14648	/* FSUNE_W */	----
14649	4744,	----
14650	/* FSUN_D */	----
14651	4747,	----
14652	/* FSUN_W */	----
14653	4750,	----
14654	/* FTINT_S_D */	----
14655	4753,	----
14656	/* FTINT_S_W */	----
14657	4755,	----
14658	/* FTINT_U_D */	----
14659	4757,	----
14660	/* FTINT_U_W */	----
14661	4759,	----
14662	/* FTQ_H */	----
14663	4761,	----
14664	/* FTQ_W */	----
14665	4764,	----
14666	/* FTRUNC_S_D */	----
14667	4767,	----
14668	/* FTRUNC_S_W */	----
14669	4769,	----
14670	/* FTRUNC_U_D */	----
14671	4771,	----
14672	/* FTRUNC_U_W */	----
14673	4773,	----
14674	/* GINVI */	----
14675	4775,	----
14676	/* GINVI_MMR6 */	----
14677	4776,	----
14678	/* GINVT */	----
14679	4777,	----
14680	/* GINVT_MMR6 */	----
14681	4779,	----
14682	/* HADD_S_D */	----
14683	4781,	----
14684	/* HADD_S_H */	----
14685	4784,	----
14686	/* HADD_S_W */	----
14687	4787,	----
14688	/* HADD_U_D */	----
14689	4790,	----
14690	/* HADD_U_H */	----
14691	4793,	----
14692	/* HADD_U_W */	----
14693	4796,	----
14694	/* HSUB_S_D */	----
14695	4799,	----
14696	/* HSUB_S_H */	----
14697	4802,	----
14698	/* HSUB_S_W */	----
14699	4805,	----
14700	/* HSUB_U_D */	----
14701	4808,	----
14702	/* HSUB_U_H */	----
14703	4811,	----
14704	/* HSUB_U_W */	----
14705	4814,	----
14706	/* HYPCALL */	----
14707	4817,	----
14708	/* HYPCALL_MM */	----
14709	4818,	----
14710	/* ILVEV_B */	----
14711	4819,	----
14712	/* ILVEV_D */	----
14713	4822,	----
14714	/* ILVEV_H */	----
14715	4825,	----
14716	/* ILVEV_W */	----
14717	4828,	----
14718	/* ILVL_B */	----
14719	4831,	----
14720	/* ILVL_D */	----
14721	4834,	----
14722	/* ILVL_H */	----
14723	4837,	----
14724	/* ILVL_W */	----
14725	4840,	----
14726	/* ILVOD_B */	----
14727	4843,	----
14728	/* ILVOD_D */	----
14729	4846,	----
14730	/* ILVOD_H */	----
14731	4849,	----
14732	/* ILVOD_W */	----
14733	4852,	----
14734	/* ILVR_B */	----
14735	4855,	----
14736	/* ILVR_D */	----
14737	4858,	----
14738	/* ILVR_H */	----
14739	4861,	----
14740	/* ILVR_W */	----
14741	4864,	----
14742	/* INS */	----
14743	4867,	----
14744	/* INSERT_B */	----
14745	4872,	----
14746	/* INSERT_D */	----
14747	4876,	----
14748	/* INSERT_H */	----
14749	4880,	----
14750	/* INSERT_W */	----
14751	4884,	----
14752	/* INSV */	----
14753	4888,	----
14754	/* INSVE_B */	----
14755	4891,	----
14756	/* INSVE_D */	----
14757	4896,	----
14758	/* INSVE_H */	----
14759	4901,	----
14760	/* INSVE_W */	----
14761	4906,	----
14762	/* INSV_MM */	----
14763	4911,	----
14764	/* INS_MM */	----
14765	4914,	----
14766	/* INS_MMR6 */	----
14767	4919,	----
14768	/* J */	----
14769	4924,	----
14770	/* JAL */	----
14771	4925,	----
14772	/* JALR */	----
14773	4926,	----
14774	/* JALR16_MM */	----
14775	4928,	----
14776	/* JALR64 */	----
14777	4929,	----
14778	/* JALRC16_MMR6 */	----
14779	4931,	----
14780	/* JALRC_HB_MMR6 */	----
14781	4932,	----
14782	/* JALRC_MMR6 */	----
14783	4934,	----
14784	/* JALRS16_MM */	----
14785	4936,	----
14786	/* JALRS_MM */	----
14787	4937,	----
14788	/* JALR_HB */	----
14789	4939,	----
14790	/* JALR_HB64 */	----
14791	4941,	----
14792	/* JALR_MM */	----
14793	4943,	----
14794	/* JALS_MM */	----
14795	4945,	----
14796	/* JALX */	----
14797	4946,	----
14798	/* JALX_MM */	----
14799	4947,	----
14800	/* JAL_MM */	----
14801	4948,	----
14802	/* JIALC */	----
14803	4949,	----
14804	/* JIALC64 */	----
14805	4951,	----
14806	/* JIALC_MMR6 */	----
14807	4953,	----
14808	/* JIC */	----
14809	4955,	----
14810	/* JIC64 */	----
14811	4957,	----
14812	/* JIC_MMR6 */	----
14813	4959,	----
14814	/* JR */	----
14815	4961,	----
14816	/* JR16_MM */	----
14817	4962,	----
14818	/* JR64 */	----
14819	4963,	----
14820	/* JRADDIUSP */	----
14821	4964,	----
14822	/* JRC16_MM */	----
14823	4965,	----
14824	/* JRC16_MMR6 */	----
14825	4966,	----
14826	/* JRCADDIUSP_MMR6 */	----
14827	4967,	----
14828	/* JR_HB */	----
14829	4968,	----
14830	/* JR_HB64 */	----
14831	4969,	----
14832	/* JR_HB64_R6 */	----
14833	4970,	----
14834	/* JR_HB_R6 */	----
14835	4971,	----
14836	/* JR_MM */	----
14837	4972,	----
14838	/* J_MM */	----
14839	4973,	----
14840	/* Jal16 */	----
14841	4974,	----
14842	/* JalB16 */	----
14843	4975,	----
14844	/* JrRa16 */	----
14845	4976,	----
14846	/* JrcRa16 */	----
14847	4976,	----
14848	/* JrcRx16 */	----
14849	4976,	----
14850	/* JumpLinkReg16 */	----
14851	4977,	----
14852	/* LB */	----
14853	4978,	----
14854	/* LB64 */	----
14855	4981,	----
14856	/* LBE */	----
14857	4984,	----
14858	/* LBE_MM */	----
14859	4987,	----
14860	/* LBU16_MM */	----
14861	4990,	----
14862	/* LBUX */	----
14863	4993,	----
14864	/* LBUX_MM */	----
14865	4996,	----
14866	/* LBU_MMR6 */	----
14867	4999,	----
14868	/* LB_MM */	----
14869	5002,	----
14870	/* LB_MMR6 */	----
14871	5005,	----
14872	/* LBu */	----
14873	5008,	----
14874	/* LBu64 */	----
14875	5011,	----
14876	/* LBuE */	----
14877	5014,	----
14878	/* LBuE_MM */	----
14879	5017,	----
14880	/* LBu_MM */	----
14881	5020,	----
14882	/* LD */	----
14883	5023,	----
14884	/* LDC1 */	----
14885	5026,	----
14886	/* LDC164 */	----
14887	5029,	----
14888	/* LDC1_D64_MMR6 */	----
14889	5032,	----
14890	/* LDC1_MM_D32 */	----
14891	5035,	----
14892	/* LDC1_MM_D64 */	----
14893	5038,	----
14894	/* LDC2 */	----
14895	5041,	----
14896	/* LDC2_MMR6 */	----
14897	5044,	----
14898	/* LDC2_R6 */	----
14899	5047,	----
14900	/* LDC3 */	----
14901	5050,	----
14902	/* LDI_B */	----
14903	5053,	----
14904	/* LDI_D */	----
14905	5055,	----
14906	/* LDI_H */	----
14907	5057,	----
14908	/* LDI_W */	----
14909	5059,	----
14910	/* LDL */	----
14911	5061,	----
14912	/* LDPC */	----
14913	5065,	----
14914	/* LDR */	----
14915	5067,	----
14916	/* LDXC1 */	----
14917	5071,	----
14918	/* LDXC164 */	----
14919	5074,	----
14920	/* LD_B */	----
14921	5077,	----
14922	/* LD_D */	----
14923	5080,	----
14924	/* LD_H */	----
14925	5083,	----
14926	/* LD_W */	----
14927	5086,	----
14928	/* LEA_ADDiu */	----
14929	5089,	----
14930	/* LEA_ADDiu64 */	----
14931	5092,	----
14932	/* LEA_ADDiu_MM */	----
14933	5095,	----
14934	/* LH */	----
14935	5098,	----
14936	/* LH64 */	----
14937	5101,	----
14938	/* LHE */	----
14939	5104,	----
14940	/* LHE_MM */	----
14941	5107,	----
14942	/* LHU16_MM */	----
14943	5110,	----
14944	/* LHX */	----
14945	5113,	----
14946	/* LHX_MM */	----
14947	5116,	----
14948	/* LH_MM */	----
14949	5119,	----
14950	/* LHu */	----
14951	5122,	----
14952	/* LHu64 */	----
14953	5125,	----
14954	/* LHuE */	----
14955	5128,	----
14956	/* LHuE_MM */	----
14957	5131,	----
14958	/* LHu_MM */	----
14959	5134,	----
14960	/* LI16_MM */	----
14961	5137,	----
14962	/* LI16_MMR6 */	----
14963	5139,	----
14964	/* LL */	----
14965	5141,	----
14966	/* LL64 */	----
14967	5144,	----
14968	/* LL64_R6 */	----
14969	5147,	----
14970	/* LLD */	----
14971	5150,	----
14972	/* LLD_R6 */	----
14973	5153,	----
14974	/* LLE */	----
14975	5156,	----
14976	/* LLE_MM */	----
14977	5159,	----
14978	/* LL_MM */	----
14979	5162,	----
14980	/* LL_MMR6 */	----
14981	5165,	----
14982	/* LL_R6 */	----
14983	5168,	----
14984	/* LSA */	----
14985	5171,	----
14986	/* LSA_MMR6 */	----
14987	5175,	----
14988	/* LSA_R6 */	----
14989	5179,	----
14990	/* LUI_MMR6 */	----
14991	5183,	----
14992	/* LUXC1 */	----
14993	5185,	----
14994	/* LUXC164 */	----
14995	5188,	----
14996	/* LUXC1_MM */	----
14997	5191,	----
14998	/* LUi */	----
14999	5194,	----
15000	/* LUi64 */	----
15001	5196,	----
15002	/* LUi_MM */	----
15003	5198,	----
15004	/* LW */	----
15005	5200,	----
15006	/* LW16_MM */	----
15007	5203,	----
15008	/* LW64 */	----
15009	5206,	----
15010	/* LWC1 */	----
15011	5209,	----
15012	/* LWC1_MM */	----
15013	5212,	----
15014	/* LWC2 */	----
15015	5215,	----
15016	/* LWC2_MMR6 */	----
15017	5218,	----
15018	/* LWC2_R6 */	----
15019	5221,	----
15020	/* LWC3 */	----
15021	5224,	----
15022	/* LWDSP */	----
15023	5227,	----
15024	/* LWDSP_MM */	----
15025	5230,	----
15026	/* LWE */	----
15027	5233,	----
15028	/* LWE_MM */	----
15029	5236,	----
15030	/* LWGP_MM */	----
15031	5239,	----
15032	/* LWL */	----
15033	5242,	----
15034	/* LWL64 */	----
15035	5246,	----
15036	/* LWLE */	----
15037	5250,	----
15038	/* LWLE_MM */	----
15039	5254,	----
15040	/* LWL_MM */	----
15041	5258,	----
15042	/* LWM16_MM */	----
15043	5262,	----
15044	/* LWM16_MMR6 */	----
15045	5265,	----
15046	/* LWM32_MM */	----
15047	5268,	----
15048	/* LWPC */	----
15049	5271,	----
15050	/* LWPC_MMR6 */	----
15051	5273,	----
15052	/* LWP_MM */	----
15053	5275,	----
15054	/* LWR */	----
15055	5279,	----
15056	/* LWR64 */	----
15057	5283,	----
15058	/* LWRE */	----
15059	5287,	----
15060	/* LWRE_MM */	----
15061	5291,	----
15062	/* LWR_MM */	----
15063	5295,	----
15064	/* LWSP_MM */	----
15065	5299,	----
15066	/* LWUPC */	----
15067	5302,	----
15068	/* LWU_MM */	----
15069	5304,	----
15070	/* LWX */	----
15071	5307,	----
15072	/* LWXC1 */	----
15073	5310,	----
15074	/* LWXC1_MM */	----
15075	5313,	----
15076	/* LWXS_MM */	----
15077	5316,	----
15078	/* LWX_MM */	----
15079	5319,	----
15080	/* LW_MM */	----
15081	5322,	----
15082	/* LW_MMR6 */	----
15083	5325,	----
15084	/* LWu */	----
15085	5328,	----
15086	/* LbRxRyOffMemX16 */	----
15087	5331,	----
15088	/* LbuRxRyOffMemX16 */	----
15089	5334,	----
15090	/* LhRxRyOffMemX16 */	----
15091	5337,	----
15092	/* LhuRxRyOffMemX16 */	----
15093	5340,	----
15094	/* LiRxImm16 */	----
15095	5343,	----
15096	/* LiRxImmAlignX16 */	----
15097	5345,	----
15098	/* LiRxImmX16 */	----
15099	5347,	----
15100	/* LwRxPcTcp16 */	----
15101	5349,	----
15102	/* LwRxPcTcpX16 */	----
15103	5352,	----
15104	/* LwRxRyOffMemX16 */	----
15105	5355,	----
15106	/* LwRxSpImmX16 */	----
15107	5358,	----
15108	/* MADD */	----
15109	5361,	----
15110	/* MADDF_D */	----
15111	5363,	----
15112	/* MADDF_D_MMR6 */	----
15113	5367,	----
15114	/* MADDF_S */	----
15115	5371,	----
15116	/* MADDF_S_MMR6 */	----
15117	5375,	----
15118	/* MADDR_Q_H */	----
15119	5379,	----
15120	/* MADDR_Q_W */	----
15121	5383,	----
15122	/* MADDU */	----
15123	5387,	----
15124	/* MADDU_DSP */	----
15125	5389,	----
15126	/* MADDU_DSP_MM */	----
15127	5393,	----
15128	/* MADDU_MM */	----
15129	5397,	----
15130	/* MADDV_B */	----
15131	5399,	----
15132	/* MADDV_D */	----
15133	5403,	----
15134	/* MADDV_H */	----
15135	5407,	----
15136	/* MADDV_W */	----
15137	5411,	----
15138	/* MADD_D32 */	----
15139	5415,	----
15140	/* MADD_D32_MM */	----
15141	5419,	----
15142	/* MADD_D64 */	----
15143	5423,	----
15144	/* MADD_DSP */	----
15145	5427,	----
15146	/* MADD_DSP_MM */	----
15147	5431,	----
15148	/* MADD_MM */	----
15149	5435,	----
15150	/* MADD_Q_H */	----
15151	5437,	----
15152	/* MADD_Q_W */	----
15153	5441,	----
15154	/* MADD_S */	----
15155	5445,	----
15156	/* MADD_S_MM */	----
15157	5449,	----
15158	/* MAQ_SA_W_PHL */	----
15159	5453,	----
15160	/* MAQ_SA_W_PHL_MM */	----
15161	5457,	----
15162	/* MAQ_SA_W_PHR */	----
15163	5461,	----
15164	/* MAQ_SA_W_PHR_MM */	----
15165	5465,	----
15166	/* MAQ_S_W_PHL */	----
15167	5469,	----
15168	/* MAQ_S_W_PHL_MM */	----
15169	5473,	----
15170	/* MAQ_S_W_PHR */	----
15171	5477,	----
15172	/* MAQ_S_W_PHR_MM */	----
15173	5481,	----
15174	/* MAXA_D */	----
15175	5485,	----
15176	/* MAXA_D_MMR6 */	----
15177	5488,	----
15178	/* MAXA_S */	----
15179	5491,	----
15180	/* MAXA_S_MMR6 */	----
15181	5494,	----
15182	/* MAXI_S_B */	----
15183	5497,	----
15184	/* MAXI_S_D */	----
15185	5500,	----
15186	/* MAXI_S_H */	----
15187	5503,	----
15188	/* MAXI_S_W */	----
15189	5506,	----
15190	/* MAXI_U_B */	----
15191	5509,	----
15192	/* MAXI_U_D */	----
15193	5512,	----
15194	/* MAXI_U_H */	----
15195	5515,	----
15196	/* MAXI_U_W */	----
15197	5518,	----
15198	/* MAX_A_B */	----
15199	5521,	----
15200	/* MAX_A_D */	----
15201	5524,	----
15202	/* MAX_A_H */	----
15203	5527,	----
15204	/* MAX_A_W */	----
15205	5530,	----
15206	/* MAX_D */	----
15207	5533,	----
15208	/* MAX_D_MMR6 */	----
15209	5536,	----
15210	/* MAX_S */	----
15211	5539,	----
15212	/* MAX_S_B */	----
15213	5542,	----
15214	/* MAX_S_D */	----
15215	5545,	----
15216	/* MAX_S_H */	----
15217	5548,	----
15218	/* MAX_S_MMR6 */	----
15219	5551,	----
15220	/* MAX_S_W */	----
15221	5554,	----
15222	/* MAX_U_B */	----
15223	5557,	----
15224	/* MAX_U_D */	----
15225	5560,	----
15226	/* MAX_U_H */	----
15227	5563,	----
15228	/* MAX_U_W */	----
15229	5566,	----
15230	/* MFC0 */	----
15231	5569,	----
15232	/* MFC0_MMR6 */	----
15233	5572,	----
15234	/* MFC1 */	----
15235	5575,	----
15236	/* MFC1_D64 */	----
15237	5577,	----
15238	/* MFC1_MM */	----
15239	5579,	----
15240	/* MFC1_MMR6 */	----
15241	5581,	----
15242	/* MFC2 */	----
15243	5583,	----
15244	/* MFC2_MMR6 */	----
15245	5586,	----
15246	/* MFGC0 */	----
15247	5588,	----
15248	/* MFGC0_MM */	----
15249	5591,	----
15250	/* MFHC0_MMR6 */	----
15251	5594,	----
15252	/* MFHC1_D32 */	----
15253	5597,	----
15254	/* MFHC1_D32_MM */	----
15255	5599,	----
15256	/* MFHC1_D64 */	----
15257	5601,	----
15258	/* MFHC1_D64_MM */	----
15259	5603,	----
15260	/* MFHC2_MMR6 */	----
15261	5605,	----
15262	/* MFHGC0 */	----
15263	5607,	----
15264	/* MFHGC0_MM */	----
15265	5610,	----
15266	/* MFHI */	----
15267	5613,	----
15268	/* MFHI16_MM */	----
15269	5614,	----
15270	/* MFHI64 */	----
15271	5615,	----
15272	/* MFHI_DSP */	----
15273	5616,	----
15274	/* MFHI_DSP_MM */	----
15275	5618,	----
15276	/* MFHI_MM */	----
15277	5620,	----
15278	/* MFLO */	----
15279	5621,	----
15280	/* MFLO16_MM */	----
15281	5622,	----
15282	/* MFLO64 */	----
15283	5623,	----
15284	/* MFLO_DSP */	----
15285	5624,	----
15286	/* MFLO_DSP_MM */	----
15287	5626,	----
15288	/* MFLO_MM */	----
15289	5628,	----
15290	/* MFTR */	----
15291	5629,	----
15292	/* MINA_D */	----
15293	5634,	----
15294	/* MINA_D_MMR6 */	----
15295	5637,	----
15296	/* MINA_S */	----
15297	5640,	----
15298	/* MINA_S_MMR6 */	----
15299	5643,	----
15300	/* MINI_S_B */	----
15301	5646,	----
15302	/* MINI_S_D */	----
15303	5649,	----
15304	/* MINI_S_H */	----
15305	5652,	----
15306	/* MINI_S_W */	----
15307	5655,	----
15308	/* MINI_U_B */	----
15309	5658,	----
15310	/* MINI_U_D */	----
15311	5661,	----
15312	/* MINI_U_H */	----
15313	5664,	----
15314	/* MINI_U_W */	----
15315	5667,	----
15316	/* MIN_A_B */	----
15317	5670,	----
15318	/* MIN_A_D */	----
15319	5673,	----
15320	/* MIN_A_H */	----
15321	5676,	----
15322	/* MIN_A_W */	----
15323	5679,	----
15324	/* MIN_D */	----
15325	5682,	----
15326	/* MIN_D_MMR6 */	----
15327	5685,	----
15328	/* MIN_S */	----
15329	5688,	----
15330	/* MIN_S_B */	----
15331	5691,	----
15332	/* MIN_S_D */	----
15333	5694,	----
15334	/* MIN_S_H */	----
15335	5697,	----
15336	/* MIN_S_MMR6 */	----
15337	5700,	----
15338	/* MIN_S_W */	----
15339	5703,	----
15340	/* MIN_U_B */	----
15341	5706,	----
15342	/* MIN_U_D */	----
15343	5709,	----
15344	/* MIN_U_H */	----
15345	5712,	----
15346	/* MIN_U_W */	----
15347	5715,	----
15348	/* MOD */	----
15349	5718,	----
15350	/* MODSUB */	----
15351	5721,	----
15352	/* MODSUB_MM */	----
15353	5724,	----
15354	/* MODU */	----
15355	5727,	----
15356	/* MODU_MMR6 */	----
15357	5730,	----
15358	/* MOD_MMR6 */	----
15359	5733,	----
15360	/* MOD_S_B */	----
15361	5736,	----
15362	/* MOD_S_D */	----
15363	5739,	----
15364	/* MOD_S_H */	----
15365	5742,	----
15366	/* MOD_S_W */	----
15367	5745,	----
15368	/* MOD_U_B */	----
15369	5748,	----
15370	/* MOD_U_D */	----
15371	5751,	----
15372	/* MOD_U_H */	----
15373	5754,	----
15374	/* MOD_U_W */	----
15375	5757,	----
15376	/* MOVE16_MM */	----
15377	5760,	----
15378	/* MOVE16_MMR6 */	----
15379	5762,	----
15380	/* MOVEP_MM */	----
15381	5764,	----
15382	/* MOVEP_MMR6 */	----
15383	5768,	----
15384	/* MOVE_V */	----
15385	5772,	----
15386	/* MOVF_D32 */	----
15387	5774,	----
15388	/* MOVF_D32_MM */	----
15389	5778,	----
15390	/* MOVF_D64 */	----
15391	5782,	----
15392	/* MOVF_I */	----
15393	5786,	----
15394	/* MOVF_I64 */	----
15395	5790,	----
15396	/* MOVF_I_MM */	----
15397	5794,	----
15398	/* MOVF_S */	----
15399	5798,	----
15400	/* MOVF_S_MM */	----
15401	5802,	----
15402	/* MOVN_I64_D64 */	----
15403	5806,	----
15404	/* MOVN_I64_I */	----
15405	5810,	----
15406	/* MOVN_I64_I64 */	----
15407	5814,	----
15408	/* MOVN_I64_S */	----
15409	5818,	----
15410	/* MOVN_I_D32 */	----
15411	5822,	----
15412	/* MOVN_I_D32_MM */	----
15413	5826,	----
15414	/* MOVN_I_D64 */	----
15415	5830,	----
15416	/* MOVN_I_I */	----
15417	5834,	----
15418	/* MOVN_I_I64 */	----
15419	5838,	----
15420	/* MOVN_I_MM */	----
15421	5842,	----
15422	/* MOVN_I_S */	----
15423	5846,	----
15424	/* MOVN_I_S_MM */	----
15425	5850,	----
15426	/* MOVT_D32 */	----
15427	5854,	----
15428	/* MOVT_D32_MM */	----
15429	5858,	----
15430	/* MOVT_D64 */	----
15431	5862,	----
15432	/* MOVT_I */	----
15433	5866,	----
15434	/* MOVT_I64 */	----
15435	5870,	----
15436	/* MOVT_I_MM */	----
15437	5874,	----
15438	/* MOVT_S */	----
15439	5878,	----
15440	/* MOVT_S_MM */	----
15441	5882,	----
15442	/* MOVZ_I64_D64 */	----
15443	5886,	----
15444	/* MOVZ_I64_I */	----
15445	5890,	----
15446	/* MOVZ_I64_I64 */	----
15447	5894,	----
15448	/* MOVZ_I64_S */	----
15449	5898,	----
15450	/* MOVZ_I_D32 */	----
15451	5902,	----
15452	/* MOVZ_I_D32_MM */	----
15453	5906,	----
15454	/* MOVZ_I_D64 */	----
15455	5910,	----
15456	/* MOVZ_I_I */	----
15457	5914,	----
15458	/* MOVZ_I_I64 */	----
15459	5918,	----
15460	/* MOVZ_I_MM */	----
15461	5922,	----
15462	/* MOVZ_I_S */	----
15463	5926,	----
15464	/* MOVZ_I_S_MM */	----
15465	5930,	----
15466	/* MSUB */	----
15467	5934,	----
15468	/* MSUBF_D */	----
15469	5936,	----
15470	/* MSUBF_D_MMR6 */	----
15471	5940,	----
15472	/* MSUBF_S */	----
15473	5944,	----
15474	/* MSUBF_S_MMR6 */	----
15475	5948,	----
15476	/* MSUBR_Q_H */	----
15477	5952,	----
15478	/* MSUBR_Q_W */	----
15479	5956,	----
15480	/* MSUBU */	----
15481	5960,	----
15482	/* MSUBU_DSP */	----
15483	5962,	----
15484	/* MSUBU_DSP_MM */	----
15485	5966,	----
15486	/* MSUBU_MM */	----
15487	5970,	----
15488	/* MSUBV_B */	----
15489	5972,	----
15490	/* MSUBV_D */	----
15491	5976,	----
15492	/* MSUBV_H */	----
15493	5980,	----
15494	/* MSUBV_W */	----
15495	5984,	----
15496	/* MSUB_D32 */	----
15497	5988,	----
15498	/* MSUB_D32_MM */	----
15499	5992,	----
15500	/* MSUB_D64 */	----
15501	5996,	----
15502	/* MSUB_DSP */	----
15503	6000,	----
15504	/* MSUB_DSP_MM */	----
15505	6004,	----
15506	/* MSUB_MM */	----
15507	6008,	----
15508	/* MSUB_Q_H */	----
15509	6010,	----
15510	/* MSUB_Q_W */	----
15511	6014,	----
15512	/* MSUB_S */	----
15513	6018,	----
15514	/* MSUB_S_MM */	----
15515	6022,	----
15516	/* MTC0 */	----
15517	6026,	----
15518	/* MTC0_MMR6 */	----
15519	6029,	----
15520	/* MTC1 */	----
15521	6032,	----
15522	/* MTC1_D64 */	----
15523	6034,	----
15524	/* MTC1_D64_MM */	----
15525	6036,	----
15526	/* MTC1_MM */	----
15527	6038,	----
15528	/* MTC1_MMR6 */	----
15529	6040,	----
15530	/* MTC2 */	----
15531	6042,	----
15532	/* MTC2_MMR6 */	----
15533	6045,	----
15534	/* MTGC0 */	----
15535	6047,	----
15536	/* MTGC0_MM */	----
15537	6050,	----
15538	/* MTHC0_MMR6 */	----
15539	6053,	----
15540	/* MTHC1_D32 */	----
15541	6056,	----
15542	/* MTHC1_D32_MM */	----
15543	6059,	----
15544	/* MTHC1_D64 */	----
15545	6062,	----
15546	/* MTHC1_D64_MM */	----
15547	6065,	----
15548	/* MTHC2_MMR6 */	----
15549	6068,	----
15550	/* MTHGC0 */	----
15551	6070,	----
15552	/* MTHGC0_MM */	----
15553	6073,	----
15554	/* MTHI */	----
15555	6076,	----
15556	/* MTHI64 */	----
15557	6077,	----
15558	/* MTHI_DSP */	----
15559	6078,	----
15560	/* MTHI_DSP_MM */	----
15561	6080,	----
15562	/* MTHI_MM */	----
15563	6082,	----
15564	/* MTHLIP */	----
15565	6083,	----
15566	/* MTHLIP_MM */	----
15567	6086,	----
15568	/* MTLO */	----
15569	6089,	----
15570	/* MTLO64 */	----
15571	6090,	----
15572	/* MTLO_DSP */	----
15573	6091,	----
15574	/* MTLO_DSP_MM */	----
15575	6093,	----
15576	/* MTLO_MM */	----
15577	6095,	----
15578	/* MTM0 */	----
15579	6096,	----
15580	/* MTM1 */	----
15581	6097,	----
15582	/* MTM2 */	----
15583	6098,	----
15584	/* MTP0 */	----
15585	6099,	----
15586	/* MTP1 */	----
15587	6100,	----
15588	/* MTP2 */	----
15589	6101,	----
15590	/* MTTR */	----
15591	6102,	----
15592	/* MUH */	----
15593	6107,	----
15594	/* MUHU */	----
15595	6110,	----
15596	/* MUHU_MMR6 */	----
15597	6113,	----
15598	/* MUH_MMR6 */	----
15599	6116,	----
15600	/* MUL */	----
15601	6119,	----
15602	/* MULEQ_S_W_PHL */	----
15603	6122,	----
15604	/* MULEQ_S_W_PHL_MM */	----
15605	6125,	----
15606	/* MULEQ_S_W_PHR */	----
15607	6128,	----
15608	/* MULEQ_S_W_PHR_MM */	----
15609	6131,	----
15610	/* MULEU_S_PH_QBL */	----
15611	6134,	----
15612	/* MULEU_S_PH_QBL_MM */	----
15613	6137,	----
15614	/* MULEU_S_PH_QBR */	----
15615	6140,	----
15616	/* MULEU_S_PH_QBR_MM */	----
15617	6143,	----
15618	/* MULQ_RS_PH */	----
15619	6146,	----
15620	/* MULQ_RS_PH_MM */	----
15621	6149,	----
15622	/* MULQ_RS_W */	----
15623	6152,	----
15624	/* MULQ_RS_W_MMR2 */	----
15625	6155,	----
15626	/* MULQ_S_PH */	----
15627	6158,	----
15628	/* MULQ_S_PH_MMR2 */	----
15629	6161,	----
15630	/* MULQ_S_W */	----
15631	6164,	----
15632	/* MULQ_S_W_MMR2 */	----
15633	6167,	----
15634	/* MULR_PS64 */	----
15635	6170,	----
15636	/* MULR_Q_H */	----
15637	6173,	----
15638	/* MULR_Q_W */	----
15639	6176,	----
15640	/* MULSAQ_S_W_PH */	----
15641	6179,	----
15642	/* MULSAQ_S_W_PH_MM */	----
15643	6183,	----
15644	/* MULSA_W_PH */	----
15645	6187,	----
15646	/* MULSA_W_PH_MMR2 */	----
15647	6191,	----
15648	/* MULT */	----
15649	6195,	----
15650	/* MULTU_DSP */	----
15651	6197,	----
15652	/* MULTU_DSP_MM */	----
15653	6200,	----
15654	/* MULT_DSP */	----
15655	6203,	----
15656	/* MULT_DSP_MM */	----
15657	6206,	----
15658	/* MULT_MM */	----
15659	6209,	----
15660	/* MULTu */	----
15661	6211,	----
15662	/* MULTu_MM */	----
15663	6213,	----
15664	/* MULU */	----
15665	6215,	----
15666	/* MULU_MMR6 */	----
15667	6218,	----
15668	/* MULV_B */	----
15669	6221,	----
15670	/* MULV_D */	----
15671	6224,	----
15672	/* MULV_H */	----
15673	6227,	----
15674	/* MULV_W */	----
15675	6230,	----
15676	/* MUL_MM */	----
15677	6233,	----
15678	/* MUL_MMR6 */	----
15679	6236,	----
15680	/* MUL_PH */	----
15681	6239,	----
15682	/* MUL_PH_MMR2 */	----
15683	6242,	----
15684	/* MUL_Q_H */	----
15685	6245,	----
15686	/* MUL_Q_W */	----
15687	6248,	----
15688	/* MUL_R6 */	----
15689	6251,	----
15690	/* MUL_S_PH */	----
15691	6254,	----
15692	/* MUL_S_PH_MMR2 */	----
15693	6257,	----
15694	/* Mfhi16 */	----
15695	6260,	----
15696	/* Mflo16 */	----
15697	6261,	----
15698	/* Move32R16 */	----
15699	6262,	----
15700	/* MoveR3216 */	----
15701	6264,	----
15702	/* NLOC_B */	----
15703	6266,	----
15704	/* NLOC_D */	----
15705	6268,	----
15706	/* NLOC_H */	----
15707	6270,	----
15708	/* NLOC_W */	----
15709	6272,	----
15710	/* NLZC_B */	----
15711	6274,	----
15712	/* NLZC_D */	----
15713	6276,	----
15714	/* NLZC_H */	----
15715	6278,	----
15716	/* NLZC_W */	----
15717	6280,	----
15718	/* NMADD_D32 */	----
15719	6282,	----
15720	/* NMADD_D32_MM */	----
15721	6286,	----
15722	/* NMADD_D64 */	----
15723	6290,	----
15724	/* NMADD_S */	----
15725	6294,	----
15726	/* NMADD_S_MM */	----
15727	6298,	----
15728	/* NMSUB_D32 */	----
15729	6302,	----
15730	/* NMSUB_D32_MM */	----
15731	6306,	----
15732	/* NMSUB_D64 */	----
15733	6310,	----
15734	/* NMSUB_S */	----
15735	6314,	----
15736	/* NMSUB_S_MM */	----
15737	6318,	----
15738	/* NOR */	----
15739	6322,	----
15740	/* NOR64 */	----
15741	6325,	----
15742	/* NORI_B */	----
15743	6328,	----
15744	/* NOR_MM */	----
15745	6331,	----
15746	/* NOR_MMR6 */	----
15747	6334,	----
15748	/* NOR_V */	----
15749	6337,	----
15750	/* NOT16_MM */	----
15751	6340,	----
15752	/* NOT16_MMR6 */	----
15753	6342,	----
15754	/* NegRxRy16 */	----
15755	6344,	----
15756	/* NotRxRy16 */	----
15757	6346,	----
15758	/* OR */	----
15759	6348,	----
15760	/* OR16_MM */	----
15761	6351,	----
15762	/* OR16_MMR6 */	----
15763	6354,	----
15764	/* OR64 */	----
15765	6357,	----
15766	/* ORI_B */	----
15767	6360,	----
15768	/* ORI_MMR6 */	----
15769	6363,	----
15770	/* OR_MM */	----
15771	6366,	----
15772	/* OR_MMR6 */	----
15773	6369,	----
15774	/* OR_V */	----
15775	6372,	----
15776	/* ORi */	----
15777	6375,	----
15778	/* ORi64 */	----
15779	6378,	----
15780	/* ORi_MM */	----
15781	6381,	----
15782	/* OrRxRxRy16 */	----
15783	6384,	----
15784	/* PACKRL_PH */	----
15785	6387,	----
15786	/* PACKRL_PH_MM */	----
15787	6390,	----
15788	/* PAUSE */	----
15789	6393,	----
15790	/* PAUSE_MM */	----
15791	6393,	----
15792	/* PAUSE_MMR6 */	----
15793	6393,	----
15794	/* PCKEV_B */	----
15795	6393,	----
15796	/* PCKEV_D */	----
15797	6396,	----
15798	/* PCKEV_H */	----
15799	6399,	----
15800	/* PCKEV_W */	----
15801	6402,	----
15802	/* PCKOD_B */	----
15803	6405,	----
15804	/* PCKOD_D */	----
15805	6408,	----
15806	/* PCKOD_H */	----
15807	6411,	----
15808	/* PCKOD_W */	----
15809	6414,	----
15810	/* PCNT_B */	----
15811	6417,	----
15812	/* PCNT_D */	----
15813	6419,	----
15814	/* PCNT_H */	----
15815	6421,	----
15816	/* PCNT_W */	----
15817	6423,	----
15818	/* PICK_PH */	----
15819	6425,	----
15820	/* PICK_PH_MM */	----
15821	6428,	----
15822	/* PICK_QB */	----
15823	6431,	----
15824	/* PICK_QB_MM */	----
15825	6434,	----
15826	/* PLL_PS64 */	----
15827	6437,	----
15828	/* PLU_PS64 */	----
15829	6440,	----
15830	/* POP */	----
15831	6443,	----
15832	/* PRECEQU_PH_QBL */	----
15833	6445,	----
15834	/* PRECEQU_PH_QBLA */	----
15835	6447,	----
15836	/* PRECEQU_PH_QBLA_MM */	----
15837	6449,	----
15838	/* PRECEQU_PH_QBL_MM */	----
15839	6451,	----
15840	/* PRECEQU_PH_QBR */	----
15841	6453,	----
15842	/* PRECEQU_PH_QBRA */	----
15843	6455,	----
15844	/* PRECEQU_PH_QBRA_MM */	----
15845	6457,	----
15846	/* PRECEQU_PH_QBR_MM */	----
15847	6459,	----
15848	/* PRECEQ_W_PHL */	----
15849	6461,	----
15850	/* PRECEQ_W_PHL_MM */	----
15851	6463,	----
15852	/* PRECEQ_W_PHR */	----
15853	6465,	----
15854	/* PRECEQ_W_PHR_MM */	----
15855	6467,	----
15856	/* PRECEU_PH_QBL */	----
15857	6469,	----
15858	/* PRECEU_PH_QBLA */	----
15859	6471,	----
15860	/* PRECEU_PH_QBLA_MM */	----
15861	6473,	----
15862	/* PRECEU_PH_QBL_MM */	----
15863	6475,	----
15864	/* PRECEU_PH_QBR */	----
15865	6477,	----
15866	/* PRECEU_PH_QBRA */	----
15867	6479,	----
15868	/* PRECEU_PH_QBRA_MM */	----
15869	6481,	----
15870	/* PRECEU_PH_QBR_MM */	----
15871	6483,	----
15872	/* PRECRQU_S_QB_PH */	----
15873	6485,	----
15874	/* PRECRQU_S_QB_PH_MM */	----
15875	6488,	----
15876	/* PRECRQ_PH_W */	----
15877	6491,	----
15878	/* PRECRQ_PH_W_MM */	----
15879	6494,	----
15880	/* PRECRQ_QB_PH */	----
15881	6497,	----
15882	/* PRECRQ_QB_PH_MM */	----
15883	6500,	----
15884	/* PRECRQ_RS_PH_W */	----
15885	6503,	----
15886	/* PRECRQ_RS_PH_W_MM */	----
15887	6506,	----
15888	/* PRECR_QB_PH */	----
15889	6509,	----
15890	/* PRECR_QB_PH_MMR2 */	----
15891	6512,	----
15892	/* PRECR_SRA_PH_W */	----
15893	6515,	----
15894	/* PRECR_SRA_PH_W_MMR2 */	----
15895	6519,	----
15896	/* PRECR_SRA_R_PH_W */	----
15897	6523,	----
15898	/* PRECR_SRA_R_PH_W_MMR2 */	----
15899	6527,	----
15900	/* PREF */	----
15901	6531,	----
15902	/* PREFE */	----
15903	6534,	----
15904	/* PREFE_MM */	----
15905	6537,	----
15906	/* PREFX_MM */	----
15907	6540,	----
15908	/* PREF_MM */	----
15909	6543,	----
15910	/* PREF_MMR6 */	----
15911	6546,	----
15912	/* PREF_R6 */	----
15913	6549,	----
15914	/* PREPEND */	----
15915	6552,	----
15916	/* PREPEND_MMR2 */	----
15917	6556,	----
15918	/* PUL_PS64 */	----
15919	6560,	----
15920	/* PUU_PS64 */	----
15921	6563,	----
15922	/* RADDU_W_QB */	----
15923	6566,	----
15924	/* RADDU_W_QB_MM */	----
15925	6568,	----
15926	/* RDDSP */	----
15927	6570,	----
15928	/* RDDSP_MM */	----
15929	6572,	----
15930	/* RDHWR */	----
15931	6574,	----
15932	/* RDHWR64 */	----
15933	6577,	----
15934	/* RDHWR_MM */	----
15935	6580,	----
15936	/* RDHWR_MMR6 */	----
15937	6583,	----
15938	/* RDPGPR_MMR6 */	----
15939	6586,	----
15940	/* RECIP_D32 */	----
15941	6588,	----
15942	/* RECIP_D32_MM */	----
15943	6590,	----
15944	/* RECIP_D64 */	----
15945	6592,	----
15946	/* RECIP_D64_MM */	----
15947	6594,	----
15948	/* RECIP_S */	----
15949	6596,	----
15950	/* RECIP_S_MM */	----
15951	6598,	----
15952	/* REPLV_PH */	----
15953	6600,	----
15954	/* REPLV_PH_MM */	----
15955	6602,	----
15956	/* REPLV_QB */	----
15957	6604,	----
15958	/* REPLV_QB_MM */	----
15959	6606,	----
15960	/* REPL_PH */	----
15961	6608,	----
15962	/* REPL_PH_MM */	----
15963	6610,	----
15964	/* REPL_QB */	----
15965	6612,	----
15966	/* REPL_QB_MM */	----
15967	6614,	----
15968	/* RINT_D */	----
15969	6616,	----
15970	/* RINT_D_MMR6 */	----
15971	6618,	----
15972	/* RINT_S */	----
15973	6620,	----
15974	/* RINT_S_MMR6 */	----
15975	6622,	----
15976	/* ROTR */	----
15977	6624,	----
15978	/* ROTRV */	----
15979	6627,	----
15980	/* ROTRV_MM */	----
15981	6630,	----
15982	/* ROTR_MM */	----
15983	6633,	----
15984	/* ROUND_L_D64 */	----
15985	6636,	----
15986	/* ROUND_L_D_MMR6 */	----
15987	6638,	----
15988	/* ROUND_L_S */	----
15989	6640,	----
15990	/* ROUND_L_S_MMR6 */	----
15991	6642,	----
15992	/* ROUND_W_D32 */	----
15993	6644,	----
15994	/* ROUND_W_D64 */	----
15995	6646,	----
15996	/* ROUND_W_D_MMR6 */	----
15997	6648,	----
15998	/* ROUND_W_MM */	----
15999	6650,	----
16000	/* ROUND_W_S */	----
16001	6652,	----
16002	/* ROUND_W_S_MM */	----
16003	6654,	----
16004	/* ROUND_W_S_MMR6 */	----
16005	6656,	----
16006	/* RSQRT_D32 */	----
16007	6658,	----
16008	/* RSQRT_D32_MM */	----
16009	6660,	----
16010	/* RSQRT_D64 */	----
16011	6662,	----
16012	/* RSQRT_D64_MM */	----
16013	6664,	----
16014	/* RSQRT_S */	----
16015	6666,	----
16016	/* RSQRT_S_MM */	----
16017	6668,	----
16018	/* Restore16 */	----
16019	6670,	----
16020	/* RestoreX16 */	----
16021	6670,	----
16022	/* SAA */	----
16023	6670,	----
16024	/* SAAD */	----
16025	6672,	----
16026	/* SAT_S_B */	----
16027	6674,	----
16028	/* SAT_S_D */	----
16029	6677,	----
16030	/* SAT_S_H */	----
16031	6680,	----
16032	/* SAT_S_W */	----
16033	6683,	----
16034	/* SAT_U_B */	----
16035	6686,	----
16036	/* SAT_U_D */	----
16037	6689,	----
16038	/* SAT_U_H */	----
16039	6692,	----
16040	/* SAT_U_W */	----
16041	6695,	----
16042	/* SB */	----
16043	6698,	----
16044	/* SB16_MM */	----
16045	6701,	----
16046	/* SB16_MMR6 */	----
16047	6704,	----
16048	/* SB64 */	----
16049	6707,	----
16050	/* SBE */	----
16051	6710,	----
16052	/* SBE_MM */	----
16053	6713,	----
16054	/* SB_MM */	----
16055	6716,	----
16056	/* SB_MMR6 */	----
16057	6719,	----
16058	/* SC */	----
16059	6722,	----
16060	/* SC64 */	----
16061	6726,	----
16062	/* SC64_R6 */	----
16063	6730,	----
16064	/* SCD */	----
16065	6734,	----
16066	/* SCD_R6 */	----
16067	6738,	----
16068	/* SCE */	----
16069	6742,	----
16070	/* SCE_MM */	----
16071	6746,	----
16072	/* SC_MM */	----
16073	6750,	----
16074	/* SC_MMR6 */	----
16075	6754,	----
16076	/* SC_R6 */	----
16077	6758,	----
16078	/* SD */	----
16079	6762,	----
16080	/* SDBBP */	----
16081	6765,	----
16082	/* SDBBP16_MM */	----
16083	6766,	----
16084	/* SDBBP16_MMR6 */	----
16085	6767,	----
16086	/* SDBBP_MM */	----
16087	6768,	----
16088	/* SDBBP_MMR6 */	----
16089	6769,	----
16090	/* SDBBP_R6 */	----
16091	6770,	----
16092	/* SDC1 */	----
16093	6771,	----
16094	/* SDC164 */	----
16095	6774,	----
16096	/* SDC1_D64_MMR6 */	----
16097	6777,	----
16098	/* SDC1_MM_D32 */	----
16099	6780,	----
16100	/* SDC1_MM_D64 */	----
16101	6783,	----
16102	/* SDC2 */	----
16103	6786,	----
16104	/* SDC2_MMR6 */	----
16105	6789,	----
16106	/* SDC2_R6 */	----
16107	6792,	----
16108	/* SDC3 */	----
16109	6795,	----
16110	/* SDIV */	----
16111	6798,	----
16112	/* SDIV_MM */	----
16113	6800,	----
16114	/* SDL */	----
16115	6802,	----
16116	/* SDR */	----
16117	6805,	----
16118	/* SDXC1 */	----
16119	6808,	----
16120	/* SDXC164 */	----
16121	6811,	----
16122	/* SEB */	----
16123	6814,	----
16124	/* SEB64 */	----
16125	6816,	----
16126	/* SEB_MM */	----
16127	6818,	----
16128	/* SEH */	----
16129	6820,	----
16130	/* SEH64 */	----
16131	6822,	----
16132	/* SEH_MM */	----
16133	6824,	----
16134	/* SELEQZ */	----
16135	6826,	----
16136	/* SELEQZ64 */	----
16137	6829,	----
16138	/* SELEQZ_D */	----
16139	6832,	----
16140	/* SELEQZ_D_MMR6 */	----
16141	6835,	----
16142	/* SELEQZ_MMR6 */	----
16143	6838,	----
16144	/* SELEQZ_S */	----
16145	6841,	----
16146	/* SELEQZ_S_MMR6 */	----
16147	6844,	----
16148	/* SELNEZ */	----
16149	6847,	----
16150	/* SELNEZ64 */	----
16151	6850,	----
16152	/* SELNEZ_D */	----
16153	6853,	----
16154	/* SELNEZ_D_MMR6 */	----
16155	6856,	----
16156	/* SELNEZ_MMR6 */	----
16157	6859,	----
16158	/* SELNEZ_S */	----
16159	6862,	----
16160	/* SELNEZ_S_MMR6 */	----
16161	6865,	----
16162	/* SEL_D */	----
16163	6868,	----
16164	/* SEL_D_MMR6 */	----
16165	6872,	----
16166	/* SEL_S */	----
16167	6876,	----
16168	/* SEL_S_MMR6 */	----
16169	6880,	----
16170	/* SEQ */	----
16171	6884,	----
16172	/* SEQi */	----
16173	6887,	----
16174	/* SH */	----
16175	6890,	----
16176	/* SH16_MM */	----
16177	6893,	----
16178	/* SH16_MMR6 */	----
16179	6896,	----
16180	/* SH64 */	----
16181	6899,	----
16182	/* SHE */	----
16183	6902,	----
16184	/* SHE_MM */	----
16185	6905,	----
16186	/* SHF_B */	----
16187	6908,	----
16188	/* SHF_H */	----
16189	6911,	----
16190	/* SHF_W */	----
16191	6914,	----
16192	/* SHILO */	----
16193	6917,	----
16194	/* SHILOV */	----
16195	6920,	----
16196	/* SHILOV_MM */	----
16197	6923,	----
16198	/* SHILO_MM */	----
16199	6926,	----
16200	/* SHLLV_PH */	----
16201	6929,	----
16202	/* SHLLV_PH_MM */	----
16203	6932,	----
16204	/* SHLLV_QB */	----
16205	6935,	----
16206	/* SHLLV_QB_MM */	----
16207	6938,	----
16208	/* SHLLV_S_PH */	----
16209	6941,	----
16210	/* SHLLV_S_PH_MM */	----
16211	6944,	----
16212	/* SHLLV_S_W */	----
16213	6947,	----
16214	/* SHLLV_S_W_MM */	----
16215	6950,	----
16216	/* SHLL_PH */	----
16217	6953,	----
16218	/* SHLL_PH_MM */	----
16219	6956,	----
16220	/* SHLL_QB */	----
16221	6959,	----
16222	/* SHLL_QB_MM */	----
16223	6962,	----
16224	/* SHLL_S_PH */	----
16225	6965,	----
16226	/* SHLL_S_PH_MM */	----
16227	6968,	----
16228	/* SHLL_S_W */	----
16229	6971,	----
16230	/* SHLL_S_W_MM */	----
16231	6974,	----
16232	/* SHRAV_PH */	----
16233	6977,	----
16234	/* SHRAV_PH_MM */	----
16235	6980,	----
16236	/* SHRAV_QB */	----
16237	6983,	----
16238	/* SHRAV_QB_MMR2 */	----
16239	6986,	----
16240	/* SHRAV_R_PH */	----
16241	6989,	----
16242	/* SHRAV_R_PH_MM */	----
16243	6992,	----
16244	/* SHRAV_R_QB */	----
16245	6995,	----
16246	/* SHRAV_R_QB_MMR2 */	----
16247	6998,	----
16248	/* SHRAV_R_W */	----
16249	7001,	----
16250	/* SHRAV_R_W_MM */	----
16251	7004,	----
16252	/* SHRA_PH */	----
16253	7007,	----
16254	/* SHRA_PH_MM */	----
16255	7010,	----
16256	/* SHRA_QB */	----
16257	7013,	----
16258	/* SHRA_QB_MMR2 */	----
16259	7016,	----
16260	/* SHRA_R_PH */	----
16261	7019,	----
16262	/* SHRA_R_PH_MM */	----
16263	7022,	----
16264	/* SHRA_R_QB */	----
16265	7025,	----
16266	/* SHRA_R_QB_MMR2 */	----
16267	7028,	----
16268	/* SHRA_R_W */	----
16269	7031,	----
16270	/* SHRA_R_W_MM */	----
16271	7034,	----
16272	/* SHRLV_PH */	----
16273	7037,	----
16274	/* SHRLV_PH_MMR2 */	----
16275	7040,	----
16276	/* SHRLV_QB */	----
16277	7043,	----
16278	/* SHRLV_QB_MM */	----
16279	7046,	----
16280	/* SHRL_PH */	----
16281	7049,	----
16282	/* SHRL_PH_MMR2 */	----
16283	7052,	----
16284	/* SHRL_QB */	----
16285	7055,	----
16286	/* SHRL_QB_MM */	----
16287	7058,	----
16288	/* SH_MM */	----
16289	7061,	----
16290	/* SH_MMR6 */	----
16291	7064,	----
16292	/* SIGRIE */	----
16293	7067,	----
16294	/* SIGRIE_MMR6 */	----
16295	7068,	----
16296	/* SLDI_B */	----
16297	7069,	----
16298	/* SLDI_D */	----
16299	7073,	----
16300	/* SLDI_H */	----
16301	7077,	----
16302	/* SLDI_W */	----
16303	7081,	----
16304	/* SLD_B */	----
16305	7085,	----
16306	/* SLD_D */	----
16307	7089,	----
16308	/* SLD_H */	----
16309	7093,	----
16310	/* SLD_W */	----
16311	7097,	----
16312	/* SLL */	----
16313	7101,	----
16314	/* SLL16_MM */	----
16315	7104,	----
16316	/* SLL16_MMR6 */	----
16317	7107,	----
16318	/* SLL64_32 */	----
16319	7110,	----
16320	/* SLL64_64 */	----
16321	7112,	----
16322	/* SLLI_B */	----
16323	7114,	----
16324	/* SLLI_D */	----
16325	7117,	----
16326	/* SLLI_H */	----
16327	7120,	----
16328	/* SLLI_W */	----
16329	7123,	----
16330	/* SLLV */	----
16331	7126,	----
16332	/* SLLV_MM */	----
16333	7129,	----
16334	/* SLL_B */	----
16335	7132,	----
16336	/* SLL_D */	----
16337	7135,	----
16338	/* SLL_H */	----
16339	7138,	----
16340	/* SLL_MM */	----
16341	7141,	----
16342	/* SLL_MMR6 */	----
16343	7144,	----
16344	/* SLL_W */	----
16345	7147,	----
16346	/* SLT */	----
16347	7150,	----
16348	/* SLT64 */	----
16349	7153,	----
16350	/* SLT_MM */	----
16351	7156,	----
16352	/* SLTi */	----
16353	7159,	----
16354	/* SLTi64 */	----
16355	7162,	----
16356	/* SLTi_MM */	----
16357	7165,	----
16358	/* SLTiu */	----
16359	7168,	----
16360	/* SLTiu64 */	----
16361	7171,	----
16362	/* SLTiu_MM */	----
16363	7174,	----
16364	/* SLTu */	----
16365	7177,	----
16366	/* SLTu64 */	----
16367	7180,	----
16368	/* SLTu_MM */	----
16369	7183,	----
16370	/* SNE */	----
16371	7186,	----
16372	/* SNEi */	----
16373	7189,	----
16374	/* SPLATI_B */	----
16375	7192,	----
16376	/* SPLATI_D */	----
16377	7195,	----
16378	/* SPLATI_H */	----
16379	7198,	----
16380	/* SPLATI_W */	----
16381	7201,	----
16382	/* SPLAT_B */	----
16383	7204,	----
16384	/* SPLAT_D */	----
16385	7207,	----
16386	/* SPLAT_H */	----
16387	7210,	----
16388	/* SPLAT_W */	----
16389	7213,	----
16390	/* SRA */	----
16391	7216,	----
16392	/* SRAI_B */	----
16393	7219,	----
16394	/* SRAI_D */	----
16395	7222,	----
16396	/* SRAI_H */	----
16397	7225,	----
16398	/* SRAI_W */	----
16399	7228,	----
16400	/* SRARI_B */	----
16401	7231,	----
16402	/* SRARI_D */	----
16403	7234,	----
16404	/* SRARI_H */	----
16405	7237,	----
16406	/* SRARI_W */	----
16407	7240,	----
16408	/* SRAR_B */	----
16409	7243,	----
16410	/* SRAR_D */	----
16411	7246,	----
16412	/* SRAR_H */	----
16413	7249,	----
16414	/* SRAR_W */	----
16415	7252,	----
16416	/* SRAV */	----
16417	7255,	----
16418	/* SRAV_MM */	----
16419	7258,	----
16420	/* SRA_B */	----
16421	7261,	----
16422	/* SRA_D */	----
16423	7264,	----
16424	/* SRA_H */	----
16425	7267,	----
16426	/* SRA_MM */	----
16427	7270,	----
16428	/* SRA_W */	----
16429	7273,	----
16430	/* SRL */	----
16431	7276,	----
16432	/* SRL16_MM */	----
16433	7279,	----
16434	/* SRL16_MMR6 */	----
16435	7282,	----
16436	/* SRLI_B */	----
16437	7285,	----
16438	/* SRLI_D */	----
16439	7288,	----
16440	/* SRLI_H */	----
16441	7291,	----
16442	/* SRLI_W */	----
16443	7294,	----
16444	/* SRLRI_B */	----
16445	7297,	----
16446	/* SRLRI_D */	----
16447	7300,	----
16448	/* SRLRI_H */	----
16449	7303,	----
16450	/* SRLRI_W */	----
16451	7306,	----
16452	/* SRLR_B */	----
16453	7309,	----
16454	/* SRLR_D */	----
16455	7312,	----
16456	/* SRLR_H */	----
16457	7315,	----
16458	/* SRLR_W */	----
16459	7318,	----
16460	/* SRLV */	----
16461	7321,	----
16462	/* SRLV_MM */	----
16463	7324,	----
16464	/* SRL_B */	----
16465	7327,	----
16466	/* SRL_D */	----
16467	7330,	----
16468	/* SRL_H */	----
16469	7333,	----
16470	/* SRL_MM */	----
16471	7336,	----
16472	/* SRL_W */	----
16473	7339,	----
16474	/* SSNOP */	----
16475	7342,	----
16476	/* SSNOP_MM */	----
16477	7342,	----
16478	/* SSNOP_MMR6 */	----
16479	7342,	----
16480	/* ST_B */	----
16481	7342,	----
16482	/* ST_D */	----
16483	7345,	----
16484	/* ST_H */	----
16485	7348,	----
16486	/* ST_W */	----
16487	7351,	----
16488	/* SUB */	----
16489	7354,	----
16490	/* SUBQH_PH */	----
16491	7357,	----
16492	/* SUBQH_PH_MMR2 */	----
16493	7360,	----
16494	/* SUBQH_R_PH */	----
16495	7363,	----
16496	/* SUBQH_R_PH_MMR2 */	----
16497	7366,	----
16498	/* SUBQH_R_W */	----
16499	7369,	----
16500	/* SUBQH_R_W_MMR2 */	----
16501	7372,	----
16502	/* SUBQH_W */	----
16503	7375,	----
16504	/* SUBQH_W_MMR2 */	----
16505	7378,	----
16506	/* SUBQ_PH */	----
16507	7381,	----
16508	/* SUBQ_PH_MM */	----
16509	7384,	----
16510	/* SUBQ_S_PH */	----
16511	7387,	----
16512	/* SUBQ_S_PH_MM */	----
16513	7390,	----
16514	/* SUBQ_S_W */	----
16515	7393,	----
16516	/* SUBQ_S_W_MM */	----
16517	7396,	----
16518	/* SUBSUS_U_B */	----
16519	7399,	----
16520	/* SUBSUS_U_D */	----
16521	7402,	----
16522	/* SUBSUS_U_H */	----
16523	7405,	----
16524	/* SUBSUS_U_W */	----
16525	7408,	----
16526	/* SUBSUU_S_B */	----
16527	7411,	----
16528	/* SUBSUU_S_D */	----
16529	7414,	----
16530	/* SUBSUU_S_H */	----
16531	7417,	----
16532	/* SUBSUU_S_W */	----
16533	7420,	----
16534	/* SUBS_S_B */	----
16535	7423,	----
16536	/* SUBS_S_D */	----
16537	7426,	----
16538	/* SUBS_S_H */	----
16539	7429,	----
16540	/* SUBS_S_W */	----
16541	7432,	----
16542	/* SUBS_U_B */	----
16543	7435,	----
16544	/* SUBS_U_D */	----
16545	7438,	----
16546	/* SUBS_U_H */	----
16547	7441,	----
16548	/* SUBS_U_W */	----
16549	7444,	----
16550	/* SUBU16_MM */	----
16551	7447,	----
16552	/* SUBU16_MMR6 */	----
16553	7450,	----
16554	/* SUBUH_QB */	----
16555	7453,	----
16556	/* SUBUH_QB_MMR2 */	----
16557	7456,	----
16558	/* SUBUH_R_QB */	----
16559	7459,	----
16560	/* SUBUH_R_QB_MMR2 */	----
16561	7462,	----
16562	/* SUBU_MMR6 */	----
16563	7465,	----
16564	/* SUBU_PH */	----
16565	7468,	----
16566	/* SUBU_PH_MMR2 */	----
16567	7471,	----
16568	/* SUBU_QB */	----
16569	7474,	----
16570	/* SUBU_QB_MM */	----
16571	7477,	----
16572	/* SUBU_S_PH */	----
16573	7480,	----
16574	/* SUBU_S_PH_MMR2 */	----
16575	7483,	----
16576	/* SUBU_S_QB */	----
16577	7486,	----
16578	/* SUBU_S_QB_MM */	----
16579	7489,	----
16580	/* SUBVI_B */	----
16581	7492,	----
16582	/* SUBVI_D */	----
16583	7495,	----
16584	/* SUBVI_H */	----
16585	7498,	----
16586	/* SUBVI_W */	----
16587	7501,	----
16588	/* SUBV_B */	----
16589	7504,	----
16590	/* SUBV_D */	----
16591	7507,	----
16592	/* SUBV_H */	----
16593	7510,	----
16594	/* SUBV_W */	----
16595	7513,	----
16596	/* SUB_MM */	----
16597	7516,	----
16598	/* SUB_MMR6 */	----
16599	7519,	----
16600	/* SUBu */	----
16601	7522,	----
16602	/* SUBu_MM */	----
16603	7525,	----
16604	/* SUXC1 */	----
16605	7528,	----
16606	/* SUXC164 */	----
16607	7531,	----
16608	/* SUXC1_MM */	----
16609	7534,	----
16610	/* SW */	----
16611	7537,	----
16612	/* SW16_MM */	----
16613	7540,	----
16614	/* SW16_MMR6 */	----
16615	7543,	----
16616	/* SW64 */	----
16617	7546,	----
16618	/* SWC1 */	----
16619	7549,	----
16620	/* SWC1_MM */	----
16621	7552,	----
16622	/* SWC2 */	----
16623	7555,	----
16624	/* SWC2_MMR6 */	----
16625	7558,	----
16626	/* SWC2_R6 */	----
16627	7561,	----
16628	/* SWC3 */	----
16629	7564,	----
16630	/* SWDSP */	----
16631	7567,	----
16632	/* SWDSP_MM */	----
16633	7570,	----
16634	/* SWE */	----
16635	7573,	----
16636	/* SWE_MM */	----
16637	7576,	----
16638	/* SWL */	----
16639	7579,	----
16640	/* SWL64 */	----
16641	7582,	----
16642	/* SWLE */	----
16643	7585,	----
16644	/* SWLE_MM */	----
16645	7588,	----
16646	/* SWL_MM */	----
16647	7591,	----
16648	/* SWM16_MM */	----
16649	7594,	----
16650	/* SWM16_MMR6 */	----
16651	7597,	----
16652	/* SWM32_MM */	----
16653	7600,	----
16654	/* SWP_MM */	----
16655	7603,	----
16656	/* SWR */	----
16657	7607,	----
16658	/* SWR64 */	----
16659	7610,	----
16660	/* SWRE */	----
16661	7613,	----
16662	/* SWRE_MM */	----
16663	7616,	----
16664	/* SWR_MM */	----
16665	7619,	----
16666	/* SWSP_MM */	----
16667	7622,	----
16668	/* SWSP_MMR6 */	----
16669	7625,	----
16670	/* SWXC1 */	----
16671	7628,	----
16672	/* SWXC1_MM */	----
16673	7631,	----
16674	/* SW_MM */	----
16675	7634,	----
16676	/* SW_MMR6 */	----
16677	7637,	----
16678	/* SYNC */	----
16679	7640,	----
16680	/* SYNCI */	----
16681	7641,	----
16682	/* SYNCI_MM */	----
16683	7643,	----
16684	/* SYNCI_MMR6 */	----
16685	7645,	----
16686	/* SYNC_MM */	----
16687	7647,	----
16688	/* SYNC_MMR6 */	----
16689	7648,	----
16690	/* SYSCALL */	----
16691	7649,	----
16692	/* SYSCALL_MM */	----
16693	7650,	----
16694	/* Save16 */	----
16695	7651,	----
16696	/* SaveX16 */	----
16697	7651,	----
16698	/* SbRxRyOffMemX16 */	----
16699	7651,	----
16700	/* SebRx16 */	----
16701	7654,	----
16702	/* SehRx16 */	----
16703	7656,	----
16704	/* ShRxRyOffMemX16 */	----
16705	7658,	----
16706	/* SllX16 */	----
16707	7661,	----
16708	/* SllvRxRy16 */	----
16709	7664,	----
16710	/* SltRxRy16 */	----
16711	7667,	----
16712	/* SltiRxImm16 */	----
16713	7669,	----
16714	/* SltiRxImmX16 */	----
16715	7671,	----
16716	/* SltiuRxImm16 */	----
16717	7673,	----
16718	/* SltiuRxImmX16 */	----
16719	7675,	----
16720	/* SltuRxRy16 */	----
16721	7677,	----
16722	/* SraX16 */	----
16723	7679,	----
16724	/* SravRxRy16 */	----
16725	7682,	----
16726	/* SrlX16 */	----
16727	7685,	----
16728	/* SrlvRxRy16 */	----
16729	7688,	----
16730	/* SubuRxRyRz16 */	----
16731	7691,	----
16732	/* SwRxRyOffMemX16 */	----
16733	7694,	----
16734	/* SwRxSpImmX16 */	----
16735	7697,	----
16736	/* TEQ */	----
16737	7700,	----
16738	/* TEQI */	----
16739	7703,	----
16740	/* TEQI_MM */	----
16741	7705,	----
16742	/* TEQ_MM */	----
16743	7707,	----
16744	/* TGE */	----
16745	7710,	----
16746	/* TGEI */	----
16747	7713,	----
16748	/* TGEIU */	----
16749	7715,	----
16750	/* TGEIU_MM */	----
16751	7717,	----
16752	/* TGEI_MM */	----
16753	7719,	----
16754	/* TGEU */	----
16755	7721,	----
16756	/* TGEU_MM */	----
16757	7724,	----
16758	/* TGE_MM */	----
16759	7727,	----
16760	/* TLBGINV */	----
16761	7730,	----
16762	/* TLBGINVF */	----
16763	7730,	----
16764	/* TLBGINVF_MM */	----
16765	7730,	----
16766	/* TLBGINV_MM */	----
16767	7730,	----
16768	/* TLBGP */	----
16769	7730,	----
16770	/* TLBGP_MM */	----
16771	7730,	----
16772	/* TLBGR */	----
16773	7730,	----
16774	/* TLBGR_MM */	----
16775	7730,	----
16776	/* TLBGWI */	----
16777	7730,	----
16778	/* TLBGWI_MM */	----
16779	7730,	----
16780	/* TLBGWR */	----
16781	7730,	----
16782	/* TLBGWR_MM */	----
16783	7730,	----
16784	/* TLBINV */	----
16785	7730,	----
16786	/* TLBINVF */	----
16787	7730,	----
16788	/* TLBINVF_MMR6 */	----
16789	7730,	----
16790	/* TLBINV_MMR6 */	----
16791	7730,	----
16792	/* TLBP */	----
16793	7730,	----
16794	/* TLBP_MM */	----
16795	7730,	----
16796	/* TLBR */	----
16797	7730,	----
16798	/* TLBR_MM */	----
16799	7730,	----
16800	/* TLBWI */	----
16801	7730,	----
16802	/* TLBWI_MM */	----
16803	7730,	----
16804	/* TLBWR */	----
16805	7730,	----
16806	/* TLBWR_MM */	----
16807	7730,	----
16808	/* TLT */	----
16809	7730,	----
16810	/* TLTI */	----
16811	7733,	----
16812	/* TLTIU_MM */	----
16813	7735,	----
16814	/* TLTI_MM */	----
16815	7737,	----
16816	/* TLTU */	----
16817	7739,	----
16818	/* TLTU_MM */	----
16819	7742,	----
16820	/* TLT_MM */	----
16821	7745,	----
16822	/* TNE */	----
16823	7748,	----
16824	/* TNEI */	----
16825	7751,	----
16826	/* TNEI_MM */	----
16827	7753,	----
16828	/* TNE_MM */	----
16829	7755,	----
16830	/* TRUNC_L_D64 */	----
16831	7758,	----
16832	/* TRUNC_L_D_MMR6 */	----
16833	7760,	----
16834	/* TRUNC_L_S */	----
16835	7762,	----
16836	/* TRUNC_L_S_MMR6 */	----
16837	7764,	----
16838	/* TRUNC_W_D32 */	----
16839	7766,	----
16840	/* TRUNC_W_D64 */	----
16841	7768,	----
16842	/* TRUNC_W_D_MMR6 */	----
16843	7770,	----
16844	/* TRUNC_W_MM */	----
16845	7772,	----
16846	/* TRUNC_W_S */	----
16847	7774,	----
16848	/* TRUNC_W_S_MM */	----
16849	7776,	----
16850	/* TRUNC_W_S_MMR6 */	----
16851	7778,	----
16852	/* TTLTIU */	----
16853	7780,	----
16854	/* UDIV */	----
16855	7782,	----
16856	/* UDIV_MM */	----
16857	7784,	----
16858	/* V3MULU */	----
16859	7786,	----
16860	/* VMM0 */	----
16861	7789,	----
16862	/* VMULU */	----
16863	7792,	----
16864	/* VSHF_B */	----
16865	7795,	----
16866	/* VSHF_D */	----
16867	7799,	----
16868	/* VSHF_H */	----
16869	7803,	----
16870	/* VSHF_W */	----
16871	7807,	----
16872	/* WAIT */	----
16873	7811,	----
16874	/* WAIT_MM */	----
16875	7811,	----
16876	/* WAIT_MMR6 */	----
16877	7812,	----
16878	/* WRDSP */	----
16879	7813,	----
16880	/* WRDSP_MM */	----
16881	7815,	----
16882	/* WRPGPR_MMR6 */	----
16883	7817,	----
16884	/* WSBH */	----
16885	7819,	----
16886	/* WSBH_MM */	----
16887	7821,	----
16888	/* WSBH_MMR6 */	----
16889	7823,	----
16890	/* XOR */	----
16891	7825,	----
16892	/* XOR16_MM */	----
16893	7828,	----
16894	/* XOR16_MMR6 */	----
16895	7831,	----
16896	/* XOR64 */	----
16897	7834,	----
16898	/* XORI_B */	----
16899	7837,	----
16900	/* XORI_MMR6 */	----
16901	7840,	----
16902	/* XOR_MM */	----
16903	7843,	----
16904	/* XOR_MMR6 */	----
16905	7846,	----
16906	/* XOR_V */	----
16907	7849,	----
16908	/* XORi */	----
16909	7852,	----
16910	/* XORi64 */	----
16911	7855,	----
16912	/* XORi_MM */	----
16913	7858,	----
16914	/* XorRxRxRy16 */	----
16915	7861,	----
16916	/* YIELD */	----
16917	7864,	----
16918	};	----
16919		----
16920	using namespace OpTypes;	----
16921	static const int16_t OpcodeOperandTypes[] = {	----
16922		----
16923	/* PHI */	----
16924	-1,	----
16925	/* INLINEASM */	----
16926	/* INLINEASM_BR */	----
16927	/* CFI_INSTRUCTION */	----
16928	i32imm,	----
16929	/* EH_LABEL */	----
16930	i32imm,	----
16931	/* GC_LABEL */	----
16932	i32imm,	----
16933	/* ANNOTATION_LABEL */	----
16934	i32imm,	----
16935	/* KILL */	----
16936	/* EXTRACT_SUBREG */	----
16937	-1, -1, i32imm,	----
16938	/* INSERT_SUBREG */	----
16939	-1, -1, -1, i32imm,	----
16940	/* IMPLICIT_DEF */	----
16941	-1,	----
16942	/* SUBREG_TO_REG */	----
16943	-1, -1, -1, i32imm,	----
16944	/* COPY_TO_REGCLASS */	----
16945	-1, -1, i32imm,	----
16946	/* DBG_VALUE */	----
16947	/* DBG_VALUE_LIST */	----
16948	/* DBG_INSTR_REF */	----
16949	/* DBG_PHI */	----
16950	/* DBG_LABEL */	----
16951	-1,	----
16952	/* REG_SEQUENCE */	----
16953	-1, -1,	----
16954	/* COPY */	----
16955	-1, -1,	----
16956	/* BUNDLE */	----
16957	/* LIFETIME_START */	----
16958	i32imm,	----
16959	/* LIFETIME_END */	----
16960	i32imm,	----
16961	/* PSEUDO_PROBE */	----
16962	i64imm, i64imm, i8imm, i32imm,	----
16963	/* ARITH_FENCE */	----
16964	-1, -1,	----
16965	/* STACKMAP */	----
16966	i64imm, i32imm,	----
16967	/* FENTRY_CALL */	----
16968	/* PATCHPOINT */	----
16969	-1, i64imm, i32imm, -1, i32imm, i32imm,	----
16970	/* LOAD_STACK_GUARD */	----
16971	-1,	----
16972	/* PREALLOCATED_SETUP */	----
16973	i32imm,	----
16974	/* PREALLOCATED_ARG */	----
16975	-1, i32imm, i32imm,	----
16976	/* STATEPOINT */	----
16977	/* LOCAL_ESCAPE */	----
16978	-1, i32imm,	----
16979	/* FAULTING_OP */	----
16980	-1,	----
16981	/* PATCHABLE_OP */	----
16982	/* PATCHABLE_FUNCTION_ENTER */	----
16983	/* PATCHABLE_RET */	----
16984	/* PATCHABLE_FUNCTION_EXIT */	----
16985	/* PATCHABLE_TAIL_CALL */	----
16986	/* PATCHABLE_EVENT_CALL */	----
16987	-1, -1,	----
16988	/* PATCHABLE_TYPED_EVENT_CALL */	----
16989	-1, -1, -1,	----
16990	/* ICALL_BRANCH_FUNNEL */	----
16991	/* MEMBARRIER */	----
16992	/* G_ASSERT_SEXT */	----
16993	type0, type0, untyped_imm_0,	----
16994	/* G_ASSERT_ZEXT */	----
16995	type0, type0, untyped_imm_0,	----
16996	/* G_ASSERT_ALIGN */	----
16997	type0, type0, untyped_imm_0,	----
16998	/* G_ADD */	----
16999	type0, type0, type0,	----
17000	/* G_SUB */	----
17001	type0, type0, type0,	----
17002	/* G_MUL */	----
17003	type0, type0, type0,	----
17004	/* G_SDIV */	----
17005	type0, type0, type0,	----
17006	/* G_UDIV */	----
17007	type0, type0, type0,	----
17008	/* G_SREM */	----
17009	type0, type0, type0,	----
17010	/* G_UREM */	----
17011	type0, type0, type0,	----
17012	/* G_SDIVREM */	----
17013	type0, type0, type0, type0,	----
17014	/* G_UDIVREM */	----
17015	type0, type0, type0, type0,	----
17016	/* G_AND */	----
17017	type0, type0, type0,	----
17018	/* G_OR */	----
17019	type0, type0, type0,	----
17020	/* G_XOR */	----
17021	type0, type0, type0,	----
17022	/* G_IMPLICIT_DEF */	----
17023	type0,	----
17024	/* G_PHI */	----
17025	type0,	----
17026	/* G_FRAME_INDEX */	----
17027	type0, -1,	----
17028	/* G_GLOBAL_VALUE */	----
17029	type0, -1,	----
17030	/* G_CONSTANT_POOL */	----
17031	type0, -1,	----
17032	/* G_EXTRACT */	----
17033	type0, type1, untyped_imm_0,	----
17034	/* G_UNMERGE_VALUES */	----
17035	type0, type1,	----
17036	/* G_INSERT */	----
17037	type0, type0, type1, untyped_imm_0,	----
17038	/* G_MERGE_VALUES */	----
17039	type0, type1,	----
17040	/* G_BUILD_VECTOR */	----
17041	type0, type1,	----
17042	/* G_BUILD_VECTOR_TRUNC */	----
17043	type0, type1,	----
17044	/* G_CONCAT_VECTORS */	----
17045	type0, type1,	----
17046	/* G_PTRTOINT */	----
17047	type0, type1,	----
17048	/* G_INTTOPTR */	----
17049	type0, type1,	----
17050	/* G_BITCAST */	----
17051	type0, type1,	----
17052	/* G_FREEZE */	----
17053	type0, type0,	----
17054	/* G_CONSTANT_FOLD_BARRIER */	----
17055	type0, type0,	----
17056	/* G_INTRINSIC_FPTRUNC_ROUND */	----
17057	type0, type1, i32imm,	----
17058	/* G_INTRINSIC_TRUNC */	----
17059	type0, type0,	----
17060	/* G_INTRINSIC_ROUND */	----
17061	type0, type0,	----
17062	/* G_INTRINSIC_LRINT */	----
17063	type0, type1,	----
17064	/* G_INTRINSIC_ROUNDEVEN */	----
17065	type0, type0,	----
17066	/* G_READCYCLECOUNTER */	----
17067	type0,	----
17068	/* G_LOAD */	----
17069	type0, ptype1,	----
17070	/* G_SEXTLOAD */	----
17071	type0, ptype1,	----
17072	/* G_ZEXTLOAD */	----
17073	type0, ptype1,	----
17074	/* G_INDEXED_LOAD */	----
17075	type0, ptype1, ptype1, type2, -1,	----
17076	/* G_INDEXED_SEXTLOAD */	----
17077	type0, ptype1, ptype1, type2, -1,	----
17078	/* G_INDEXED_ZEXTLOAD */	----
17079	type0, ptype1, ptype1, type2, -1,	----
17080	/* G_STORE */	----
17081	type0, ptype1,	----
17082	/* G_INDEXED_STORE */	----
17083	ptype0, type1, ptype0, ptype2, -1,	----
17084	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	----
17085	type0, type1, type2, type0, type0,	----
17086	/* G_ATOMIC_CMPXCHG */	----
17087	type0, ptype1, type0, type0,	----
17088	/* G_ATOMICRMW_XCHG */	----
17089	type0, ptype1, type0,	----
17090	/* G_ATOMICRMW_ADD */	----
17091	type0, ptype1, type0,	----
17092	/* G_ATOMICRMW_SUB */	----
17093	type0, ptype1, type0,	----
17094	/* G_ATOMICRMW_AND */	----
17095	type0, ptype1, type0,	----
17096	/* G_ATOMICRMW_NAND */	----
17097	type0, ptype1, type0,	----
17098	/* G_ATOMICRMW_OR */	----
17099	type0, ptype1, type0,	----
17100	/* G_ATOMICRMW_XOR */	----
17101	type0, ptype1, type0,	----
17102	/* G_ATOMICRMW_MAX */	----
17103	type0, ptype1, type0,	----
17104	/* G_ATOMICRMW_MIN */	----
17105	type0, ptype1, type0,	----
17106	/* G_ATOMICRMW_UMAX */	----
17107	type0, ptype1, type0,	----
17108	/* G_ATOMICRMW_UMIN */	----
17109	type0, ptype1, type0,	----
17110	/* G_ATOMICRMW_FADD */	----
17111	type0, ptype1, type0,	----
17112	/* G_ATOMICRMW_FSUB */	----
17113	type0, ptype1, type0,	----
17114	/* G_ATOMICRMW_FMAX */	----
17115	type0, ptype1, type0,	----
17116	/* G_ATOMICRMW_FMIN */	----
17117	type0, ptype1, type0,	----
17118	/* G_ATOMICRMW_UINC_WRAP */	----
17119	type0, ptype1, type0,	----
17120	/* G_ATOMICRMW_UDEC_WRAP */	----
17121	type0, ptype1, type0,	----
17122	/* G_FENCE */	----
17123	i32imm, i32imm,	----
17124	/* G_BRCOND */	----
17125	type0, -1,	----
17126	/* G_BRINDIRECT */	----
17127	type0,	----
17128	/* G_INVOKE_REGION_START */	----
17129	/* G_INTRINSIC */	----
17130	-1,	----
17131	/* G_INTRINSIC_W_SIDE_EFFECTS */	----
17132	-1,	----
17133	/* G_ANYEXT */	----
17134	type0, type1,	----
17135	/* G_TRUNC */	----
17136	type0, type1,	----
17137	/* G_CONSTANT */	----
17138	type0, -1,	----
17139	/* G_FCONSTANT */	----
17140	type0, -1,	----
17141	/* G_VASTART */	----
17142	type0,	----
17143	/* G_VAARG */	----
17144	type0, type1, -1,	----
17145	/* G_SEXT */	----
17146	type0, type1,	----
17147	/* G_SEXT_INREG */	----
17148	type0, type0, untyped_imm_0,	----
17149	/* G_ZEXT */	----
17150	type0, type1,	----
17151	/* G_SHL */	----
17152	type0, type0, type1,	----
17153	/* G_LSHR */	----
17154	type0, type0, type1,	----
17155	/* G_ASHR */	----
17156	type0, type0, type1,	----
17157	/* G_FSHL */	----
17158	type0, type0, type0, type1,	----
17159	/* G_FSHR */	----
17160	type0, type0, type0, type1,	----
17161	/* G_ROTR */	----
17162	type0, type0, type1,	----
17163	/* G_ROTL */	----
17164	type0, type0, type1,	----
17165	/* G_ICMP */	----
17166	type0, -1, type1, type1,	----
17167	/* G_FCMP */	----
17168	type0, -1, type1, type1,	----
17169	/* G_SELECT */	----
17170	type0, type1, type0, type0,	----
17171	/* G_UADDO */	----
17172	type0, type1, type0, type0,	----
17173	/* G_UADDE */	----
17174	type0, type1, type0, type0, type1,	----
17175	/* G_USUBO */	----
17176	type0, type1, type0, type0,	----
17177	/* G_USUBE */	----
17178	type0, type1, type0, type0, type1,	----
17179	/* G_SADDO */	----
17180	type0, type1, type0, type0,	----
17181	/* G_SADDE */	----
17182	type0, type1, type0, type0, type1,	----
17183	/* G_SSUBO */	----
17184	type0, type1, type0, type0,	----
17185	/* G_SSUBE */	----
17186	type0, type1, type0, type0, type1,	----
17187	/* G_UMULO */	----
17188	type0, type1, type0, type0,	----
17189	/* G_SMULO */	----
17190	type0, type1, type0, type0,	----
17191	/* G_UMULH */	----
17192	type0, type0, type0,	----
17193	/* G_SMULH */	----
17194	type0, type0, type0,	----
17195	/* G_UADDSAT */	----
17196	type0, type0, type0,	----
17197	/* G_SADDSAT */	----
17198	type0, type0, type0,	----
17199	/* G_USUBSAT */	----
17200	type0, type0, type0,	----
17201	/* G_SSUBSAT */	----
17202	type0, type0, type0,	----
17203	/* G_USHLSAT */	----
17204	type0, type0, type1,	----
17205	/* G_SSHLSAT */	----
17206	type0, type0, type1,	----
17207	/* G_SMULFIX */	----
17208	type0, type0, type0, untyped_imm_0,	----
17209	/* G_UMULFIX */	----
17210	type0, type0, type0, untyped_imm_0,	----
17211	/* G_SMULFIXSAT */	----
17212	type0, type0, type0, untyped_imm_0,	----
17213	/* G_UMULFIXSAT */	----
17214	type0, type0, type0, untyped_imm_0,	----
17215	/* G_SDIVFIX */	----
17216	type0, type0, type0, untyped_imm_0,	----
17217	/* G_UDIVFIX */	----
17218	type0, type0, type0, untyped_imm_0,	----
17219	/* G_SDIVFIXSAT */	----
17220	type0, type0, type0, untyped_imm_0,	----
17221	/* G_UDIVFIXSAT */	----
17222	type0, type0, type0, untyped_imm_0,	----
17223	/* G_FADD */	----
17224	type0, type0, type0,	----
17225	/* G_FSUB */	----
17226	type0, type0, type0,	----
17227	/* G_FMUL */	----
17228	type0, type0, type0,	----
17229	/* G_FMA */	----
17230	type0, type0, type0, type0,	----
17231	/* G_FMAD */	----
17232	type0, type0, type0, type0,	----
17233	/* G_FDIV */	----
17234	type0, type0, type0,	----
17235	/* G_FREM */	----
17236	type0, type0, type0,	----
17237	/* G_FPOW */	----
17238	type0, type0, type0,	----
17239	/* G_FPOWI */	----
17240	type0, type0, type1,	----
17241	/* G_FEXP */	----
17242	type0, type0,	----
17243	/* G_FEXP2 */	----
17244	type0, type0,	----
17245	/* G_FLOG */	----
17246	type0, type0,	----
17247	/* G_FLOG2 */	----
17248	type0, type0,	----
17249	/* G_FLOG10 */	----
17250	type0, type0,	----
17251	/* G_FLDEXP */	----
17252	type0, type0, type1,	----
17253	/* G_FFREXP */	----
17254	type0, type1, type0,	----
17255	/* G_FNEG */	----
17256	type0, type0,	----
17257	/* G_FPEXT */	----
17258	type0, type1,	----
17259	/* G_FPTRUNC */	----
17260	type0, type1,	----
17261	/* G_FPTOSI */	----
17262	type0, type1,	----
17263	/* G_FPTOUI */	----
17264	type0, type1,	----
17265	/* G_SITOFP */	----
17266	type0, type1,	----
17267	/* G_UITOFP */	----
17268	type0, type1,	----
17269	/* G_FABS */	----
17270	type0, type0,	----
17271	/* G_FCOPYSIGN */	----
17272	type0, type0, type1,	----
17273	/* G_IS_FPCLASS */	----
17274	type0, type1, -1,	----
17275	/* G_FCANONICALIZE */	----
17276	type0, type0,	----
17277	/* G_FMINNUM */	----
17278	type0, type0, type0,	----
17279	/* G_FMAXNUM */	----
17280	type0, type0, type0,	----
17281	/* G_FMINNUM_IEEE */	----
17282	type0, type0, type0,	----
17283	/* G_FMAXNUM_IEEE */	----
17284	type0, type0, type0,	----
17285	/* G_FMINIMUM */	----
17286	type0, type0, type0,	----
17287	/* G_FMAXIMUM */	----
17288	type0, type0, type0,	----
17289	/* G_PTR_ADD */	----
17290	ptype0, ptype0, type1,	----
17291	/* G_PTRMASK */	----
17292	ptype0, ptype0, type1,	----
17293	/* G_SMIN */	----
17294	type0, type0, type0,	----
17295	/* G_SMAX */	----
17296	type0, type0, type0,	----
17297	/* G_UMIN */	----
17298	type0, type0, type0,	----
17299	/* G_UMAX */	----
17300	type0, type0, type0,	----
17301	/* G_ABS */	----
17302	type0, type0,	----
17303	/* G_LROUND */	----
17304	type0, type1,	----
17305	/* G_LLROUND */	----
17306	type0, type1,	----
17307	/* G_BR */	----
17308	-1,	----
17309	/* G_BRJT */	----
17310	ptype0, -1, type1,	----
17311	/* G_INSERT_VECTOR_ELT */	----
17312	type0, type0, type1, type2,	----
17313	/* G_EXTRACT_VECTOR_ELT */	----
17314	type0, type1, type2,	----
17315	/* G_SHUFFLE_VECTOR */	----
17316	type0, type1, type1, -1,	----
17317	/* G_CTTZ */	----
17318	type0, type1,	----
17319	/* G_CTTZ_ZERO_UNDEF */	----
17320	type0, type1,	----
17321	/* G_CTLZ */	----
17322	type0, type1,	----
17323	/* G_CTLZ_ZERO_UNDEF */	----
17324	type0, type1,	----
17325	/* G_CTPOP */	----
17326	type0, type1,	----
17327	/* G_BSWAP */	----
17328	type0, type0,	----
17329	/* G_BITREVERSE */	----
17330	type0, type0,	----
17331	/* G_FCEIL */	----
17332	type0, type0,	----
17333	/* G_FCOS */	----
17334	type0, type0,	----
17335	/* G_FSIN */	----
17336	type0, type0,	----
17337	/* G_FSQRT */	----
17338	type0, type0,	----
17339	/* G_FFLOOR */	----
17340	type0, type0,	----
17341	/* G_FRINT */	----
17342	type0, type0,	----
17343	/* G_FNEARBYINT */	----
17344	type0, type0,	----
17345	/* G_ADDRSPACE_CAST */	----
17346	type0, type1,	----
17347	/* G_BLOCK_ADDR */	----
17348	type0, -1,	----
17349	/* G_JUMP_TABLE */	----
17350	type0, -1,	----
17351	/* G_DYN_STACKALLOC */	----
17352	ptype0, type1, i32imm,	----
17353	/* G_STRICT_FADD */	----
17354	type0, type0, type0,	----
17355	/* G_STRICT_FSUB */	----
17356	type0, type0, type0,	----
17357	/* G_STRICT_FMUL */	----
17358	type0, type0, type0,	----
17359	/* G_STRICT_FDIV */	----
17360	type0, type0, type0,	----
17361	/* G_STRICT_FREM */	----
17362	type0, type0, type0,	----
17363	/* G_STRICT_FMA */	----
17364	type0, type0, type0, type0,	----
17365	/* G_STRICT_FSQRT */	----
17366	type0, type0,	----
17367	/* G_STRICT_FLDEXP */	----
17368	type0, type0, type1,	----
17369	/* G_READ_REGISTER */	----
17370	type0, -1,	----
17371	/* G_WRITE_REGISTER */	----
17372	-1, type0,	----
17373	/* G_MEMCPY */	----
17374	ptype0, ptype1, type2, untyped_imm_0,	----
17375	/* G_MEMCPY_INLINE */	----
17376	ptype0, ptype1, type2,	----
17377	/* G_MEMMOVE */	----
17378	ptype0, ptype1, type2, untyped_imm_0,	----
17379	/* G_MEMSET */	----
17380	ptype0, type1, type2, untyped_imm_0,	----
17381	/* G_BZERO */	----
17382	ptype0, type1, untyped_imm_0,	----
17383	/* G_VECREDUCE_SEQ_FADD */	----
17384	type0, type1, type2,	----
17385	/* G_VECREDUCE_SEQ_FMUL */	----
17386	type0, type1, type2,	----
17387	/* G_VECREDUCE_FADD */	----
17388	type0, type1,	----
17389	/* G_VECREDUCE_FMUL */	----
17390	type0, type1,	----
17391	/* G_VECREDUCE_FMAX */	----
17392	type0, type1,	----
17393	/* G_VECREDUCE_FMIN */	----
17394	type0, type1,	----
17395	/* G_VECREDUCE_ADD */	----
17396	type0, type1,	----
17397	/* G_VECREDUCE_MUL */	----
17398	type0, type1,	----
17399	/* G_VECREDUCE_AND */	----
17400	type0, type1,	----
17401	/* G_VECREDUCE_OR */	----
17402	type0, type1,	----
17403	/* G_VECREDUCE_XOR */	----
17404	type0, type1,	----
17405	/* G_VECREDUCE_SMAX */	----
17406	type0, type1,	----
17407	/* G_VECREDUCE_SMIN */	----
17408	type0, type1,	----
17409	/* G_VECREDUCE_UMAX */	----
17410	type0, type1,	----
17411	/* G_VECREDUCE_UMIN */	----
17412	type0, type1,	----
17413	/* G_SBFX */	----
17414	type0, type0, type1, type1,	----
17415	/* G_UBFX */	----
17416	type0, type0, type1, type1,	----
17417	/* ABSMacro */	----
17418	GPR32Opnd, GPR32Opnd,	----
17419	/* ADJCALLSTACKDOWN */	----
17420	i32imm, i32imm,	----
17421	/* ADJCALLSTACKUP */	----
17422	i32imm, i32imm,	----
17423	/* AND_V_D_PSEUDO */	----
17424	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
17425	/* AND_V_H_PSEUDO */	----
17426	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
17427	/* AND_V_W_PSEUDO */	----
17428	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
17429	/* ATOMIC_CMP_SWAP_I16 */	----
17430	GPR32, -1, GPR32, GPR32,	----
17431	/* ATOMIC_CMP_SWAP_I16_POSTRA */	----
17432	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	----
17433	/* ATOMIC_CMP_SWAP_I32 */	----
17434	GPR32, -1, GPR32, GPR32,	----
17435	/* ATOMIC_CMP_SWAP_I32_POSTRA */	----
17436	GPR32, -1, GPR32, GPR32,	----
17437	/* ATOMIC_CMP_SWAP_I64 */	----
17438	GPR64, -1, GPR64, GPR64,	----
17439	/* ATOMIC_CMP_SWAP_I64_POSTRA */	----
17440	GPR64, -1, GPR64, GPR64,	----
17441	/* ATOMIC_CMP_SWAP_I8 */	----
17442	GPR32, -1, GPR32, GPR32,	----
17443	/* ATOMIC_CMP_SWAP_I8_POSTRA */	----
17444	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	----
17445	/* ATOMIC_LOAD_ADD_I16 */	----
17446	GPR32, -1, GPR32,	----
17447	/* ATOMIC_LOAD_ADD_I16_POSTRA */	----
17448	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17449	/* ATOMIC_LOAD_ADD_I32 */	----
17450	GPR32, -1, GPR32,	----
17451	/* ATOMIC_LOAD_ADD_I32_POSTRA */	----
17452	GPR32, -1, GPR32,	----
17453	/* ATOMIC_LOAD_ADD_I64 */	----
17454	GPR64, -1, GPR64,	----
17455	/* ATOMIC_LOAD_ADD_I64_POSTRA */	----
17456	GPR64, -1, GPR64,	----
17457	/* ATOMIC_LOAD_ADD_I8 */	----
17458	GPR32, -1, GPR32,	----
17459	/* ATOMIC_LOAD_ADD_I8_POSTRA */	----
17460	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17461	/* ATOMIC_LOAD_AND_I16 */	----
17462	GPR32, -1, GPR32,	----
17463	/* ATOMIC_LOAD_AND_I16_POSTRA */	----
17464	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17465	/* ATOMIC_LOAD_AND_I32 */	----
17466	GPR32, -1, GPR32,	----
17467	/* ATOMIC_LOAD_AND_I32_POSTRA */	----
17468	GPR32, -1, GPR32,	----
17469	/* ATOMIC_LOAD_AND_I64 */	----
17470	GPR64, -1, GPR64,	----
17471	/* ATOMIC_LOAD_AND_I64_POSTRA */	----
17472	GPR64, -1, GPR64,	----
17473	/* ATOMIC_LOAD_AND_I8 */	----
17474	GPR32, -1, GPR32,	----
17475	/* ATOMIC_LOAD_AND_I8_POSTRA */	----
17476	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17477	/* ATOMIC_LOAD_MAX_I16 */	----
17478	GPR32, -1, GPR32,	----
17479	/* ATOMIC_LOAD_MAX_I16_POSTRA */	----
17480	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17481	/* ATOMIC_LOAD_MAX_I32 */	----
17482	GPR32, -1, GPR32,	----
17483	/* ATOMIC_LOAD_MAX_I32_POSTRA */	----
17484	GPR32, -1, GPR32,	----
17485	/* ATOMIC_LOAD_MAX_I64 */	----
17486	GPR64, -1, GPR64,	----
17487	/* ATOMIC_LOAD_MAX_I64_POSTRA */	----
17488	GPR64, -1, GPR64,	----
17489	/* ATOMIC_LOAD_MAX_I8 */	----
17490	GPR32, -1, GPR32,	----
17491	/* ATOMIC_LOAD_MAX_I8_POSTRA */	----
17492	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17493	/* ATOMIC_LOAD_MIN_I16 */	----
17494	GPR32, -1, GPR32,	----
17495	/* ATOMIC_LOAD_MIN_I16_POSTRA */	----
17496	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17497	/* ATOMIC_LOAD_MIN_I32 */	----
17498	GPR32, -1, GPR32,	----
17499	/* ATOMIC_LOAD_MIN_I32_POSTRA */	----
17500	GPR32, -1, GPR32,	----
17501	/* ATOMIC_LOAD_MIN_I64 */	----
17502	GPR64, -1, GPR64,	----
17503	/* ATOMIC_LOAD_MIN_I64_POSTRA */	----
17504	GPR64, -1, GPR64,	----
17505	/* ATOMIC_LOAD_MIN_I8 */	----
17506	GPR32, -1, GPR32,	----
17507	/* ATOMIC_LOAD_MIN_I8_POSTRA */	----
17508	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17509	/* ATOMIC_LOAD_NAND_I16 */	----
17510	GPR32, -1, GPR32,	----
17511	/* ATOMIC_LOAD_NAND_I16_POSTRA */	----
17512	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17513	/* ATOMIC_LOAD_NAND_I32 */	----
17514	GPR32, -1, GPR32,	----
17515	/* ATOMIC_LOAD_NAND_I32_POSTRA */	----
17516	GPR32, -1, GPR32,	----
17517	/* ATOMIC_LOAD_NAND_I64 */	----
17518	GPR64, -1, GPR64,	----
17519	/* ATOMIC_LOAD_NAND_I64_POSTRA */	----
17520	GPR64, -1, GPR64,	----
17521	/* ATOMIC_LOAD_NAND_I8 */	----
17522	GPR32, -1, GPR32,	----
17523	/* ATOMIC_LOAD_NAND_I8_POSTRA */	----
17524	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17525	/* ATOMIC_LOAD_OR_I16 */	----
17526	GPR32, -1, GPR32,	----
17527	/* ATOMIC_LOAD_OR_I16_POSTRA */	----
17528	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17529	/* ATOMIC_LOAD_OR_I32 */	----
17530	GPR32, -1, GPR32,	----
17531	/* ATOMIC_LOAD_OR_I32_POSTRA */	----
17532	GPR32, -1, GPR32,	----
17533	/* ATOMIC_LOAD_OR_I64 */	----
17534	GPR64, -1, GPR64,	----
17535	/* ATOMIC_LOAD_OR_I64_POSTRA */	----
17536	GPR64, -1, GPR64,	----
17537	/* ATOMIC_LOAD_OR_I8 */	----
17538	GPR32, -1, GPR32,	----
17539	/* ATOMIC_LOAD_OR_I8_POSTRA */	----
17540	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17541	/* ATOMIC_LOAD_SUB_I16 */	----
17542	GPR32, -1, GPR32,	----
17543	/* ATOMIC_LOAD_SUB_I16_POSTRA */	----
17544	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17545	/* ATOMIC_LOAD_SUB_I32 */	----
17546	GPR32, -1, GPR32,	----
17547	/* ATOMIC_LOAD_SUB_I32_POSTRA */	----
17548	GPR32, -1, GPR32,	----
17549	/* ATOMIC_LOAD_SUB_I64 */	----
17550	GPR64, -1, GPR64,	----
17551	/* ATOMIC_LOAD_SUB_I64_POSTRA */	----
17552	GPR64, -1, GPR64,	----
17553	/* ATOMIC_LOAD_SUB_I8 */	----
17554	GPR32, -1, GPR32,	----
17555	/* ATOMIC_LOAD_SUB_I8_POSTRA */	----
17556	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17557	/* ATOMIC_LOAD_UMAX_I16 */	----
17558	GPR32, -1, GPR32,	----
17559	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	----
17560	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17561	/* ATOMIC_LOAD_UMAX_I32 */	----
17562	GPR32, -1, GPR32,	----
17563	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	----
17564	GPR32, -1, GPR32,	----
17565	/* ATOMIC_LOAD_UMAX_I64 */	----
17566	GPR64, -1, GPR64,	----
17567	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	----
17568	GPR64, -1, GPR64,	----
17569	/* ATOMIC_LOAD_UMAX_I8 */	----
17570	GPR32, -1, GPR32,	----
17571	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	----
17572	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17573	/* ATOMIC_LOAD_UMIN_I16 */	----
17574	GPR32, -1, GPR32,	----
17575	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	----
17576	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17577	/* ATOMIC_LOAD_UMIN_I32 */	----
17578	GPR32, -1, GPR32,	----
17579	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	----
17580	GPR32, -1, GPR32,	----
17581	/* ATOMIC_LOAD_UMIN_I64 */	----
17582	GPR64, -1, GPR64,	----
17583	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	----
17584	GPR64, -1, GPR64,	----
17585	/* ATOMIC_LOAD_UMIN_I8 */	----
17586	GPR32, -1, GPR32,	----
17587	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	----
17588	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17589	/* ATOMIC_LOAD_XOR_I16 */	----
17590	GPR32, -1, GPR32,	----
17591	/* ATOMIC_LOAD_XOR_I16_POSTRA */	----
17592	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17593	/* ATOMIC_LOAD_XOR_I32 */	----
17594	GPR32, -1, GPR32,	----
17595	/* ATOMIC_LOAD_XOR_I32_POSTRA */	----
17596	GPR32, -1, GPR32,	----
17597	/* ATOMIC_LOAD_XOR_I64 */	----
17598	GPR64, -1, GPR64,	----
17599	/* ATOMIC_LOAD_XOR_I64_POSTRA */	----
17600	GPR64, -1, GPR64,	----
17601	/* ATOMIC_LOAD_XOR_I8 */	----
17602	GPR32, -1, GPR32,	----
17603	/* ATOMIC_LOAD_XOR_I8_POSTRA */	----
17604	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17605	/* ATOMIC_SWAP_I16 */	----
17606	GPR32, -1, GPR32,	----
17607	/* ATOMIC_SWAP_I16_POSTRA */	----
17608	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17609	/* ATOMIC_SWAP_I32 */	----
17610	GPR32, -1, GPR32,	----
17611	/* ATOMIC_SWAP_I32_POSTRA */	----
17612	GPR32, -1, GPR32,	----
17613	/* ATOMIC_SWAP_I64 */	----
17614	GPR64, -1, GPR64,	----
17615	/* ATOMIC_SWAP_I64_POSTRA */	----
17616	GPR64, -1, GPR64,	----
17617	/* ATOMIC_SWAP_I8 */	----
17618	GPR32, -1, GPR32,	----
17619	/* ATOMIC_SWAP_I8_POSTRA */	----
17620	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	----
17621	/* B */	----
17622	brtarget,	----
17623	/* BAL_BR */	----
17624	brtarget,	----
17625	/* BAL_BR_MM */	----
17626	brtarget_mm,	----
17627	/* BEQLImmMacro */	----
17628	GPR32Opnd, imm64, brtarget,	----
17629	/* BGE */	----
17630	GPR32Opnd, GPR32Opnd, brtarget,	----
17631	/* BGEImmMacro */	----
17632	GPR32Opnd, imm64, brtarget,	----
17633	/* BGEL */	----
17634	GPR32Opnd, GPR32Opnd, brtarget,	----
17635	/* BGELImmMacro */	----
17636	GPR32Opnd, imm64, brtarget,	----
17637	/* BGEU */	----
17638	GPR32Opnd, GPR32Opnd, brtarget,	----
17639	/* BGEUImmMacro */	----
17640	GPR32Opnd, imm64, brtarget,	----
17641	/* BGEUL */	----
17642	GPR32Opnd, GPR32Opnd, brtarget,	----
17643	/* BGEULImmMacro */	----
17644	GPR32Opnd, imm64, brtarget,	----
17645	/* BGT */	----
17646	GPR32Opnd, GPR32Opnd, brtarget,	----
17647	/* BGTImmMacro */	----
17648	GPR32Opnd, imm64, brtarget,	----
17649	/* BGTL */	----
17650	GPR32Opnd, GPR32Opnd, brtarget,	----
17651	/* BGTLImmMacro */	----
17652	GPR32Opnd, imm64, brtarget,	----
17653	/* BGTU */	----
17654	GPR32Opnd, GPR32Opnd, brtarget,	----
17655	/* BGTUImmMacro */	----
17656	GPR32Opnd, imm64, brtarget,	----
17657	/* BGTUL */	----
17658	GPR32Opnd, GPR32Opnd, brtarget,	----
17659	/* BGTULImmMacro */	----
17660	GPR32Opnd, imm64, brtarget,	----
17661	/* BLE */	----
17662	GPR32Opnd, GPR32Opnd, brtarget,	----
17663	/* BLEImmMacro */	----
17664	GPR32Opnd, imm64, brtarget,	----
17665	/* BLEL */	----
17666	GPR32Opnd, GPR32Opnd, brtarget,	----
17667	/* BLELImmMacro */	----
17668	GPR32Opnd, imm64, brtarget,	----
17669	/* BLEU */	----
17670	GPR32Opnd, GPR32Opnd, brtarget,	----
17671	/* BLEUImmMacro */	----
17672	GPR32Opnd, imm64, brtarget,	----
17673	/* BLEUL */	----
17674	GPR32Opnd, GPR32Opnd, brtarget,	----
17675	/* BLEULImmMacro */	----
17676	GPR32Opnd, imm64, brtarget,	----
17677	/* BLT */	----
17678	GPR32Opnd, GPR32Opnd, brtarget,	----
17679	/* BLTImmMacro */	----
17680	GPR32Opnd, imm64, brtarget,	----
17681	/* BLTL */	----
17682	GPR32Opnd, GPR32Opnd, brtarget,	----
17683	/* BLTLImmMacro */	----
17684	GPR32Opnd, imm64, brtarget,	----
17685	/* BLTU */	----
17686	GPR32Opnd, GPR32Opnd, brtarget,	----
17687	/* BLTUImmMacro */	----
17688	GPR32Opnd, imm64, brtarget,	----
17689	/* BLTUL */	----
17690	GPR32Opnd, GPR32Opnd, brtarget,	----
17691	/* BLTULImmMacro */	----
17692	GPR32Opnd, imm64, brtarget,	----
17693	/* BNELImmMacro */	----
17694	GPR32Opnd, imm64, brtarget,	----
17695	/* BPOSGE32_PSEUDO */	----
17696	GPR32Opnd,	----
17697	/* BSEL_D_PSEUDO */	----
17698	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
17699	/* BSEL_FD_PSEUDO */	----
17700	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
17701	/* BSEL_FW_PSEUDO */	----
17702	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
17703	/* BSEL_H_PSEUDO */	----
17704	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
17705	/* BSEL_W_PSEUDO */	----
17706	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
17707	/* B_MM */	----
17708	brtarget,	----
17709	/* B_MMR6_Pseudo */	----
17710	brtarget_mm,	----
17711	/* B_MM_Pseudo */	----
17712	brtarget_mm,	----
17713	/* BeqImm */	----
17714	GPR32Opnd, imm64, brtarget,	----
17715	/* BneImm */	----
17716	GPR32Opnd, imm64, brtarget,	----
17717	/* BteqzT8CmpX16 */	----
17718	CPU16Regs, CPU16Regs, brtarget,	----
17719	/* BteqzT8CmpiX16 */	----
17720	CPU16Regs, simm16, brtarget,	----
17721	/* BteqzT8SltX16 */	----
17722	CPU16Regs, CPU16Regs, brtarget,	----
17723	/* BteqzT8SltiX16 */	----
17724	CPU16Regs, simm16, brtarget,	----
17725	/* BteqzT8SltiuX16 */	----
17726	CPU16Regs, simm16, brtarget,	----
17727	/* BteqzT8SltuX16 */	----
17728	CPU16Regs, CPU16Regs, brtarget,	----
17729	/* BtnezT8CmpX16 */	----
17730	CPU16Regs, CPU16Regs, brtarget,	----
17731	/* BtnezT8CmpiX16 */	----
17732	CPU16Regs, simm16, brtarget,	----
17733	/* BtnezT8SltX16 */	----
17734	CPU16Regs, CPU16Regs, brtarget,	----
17735	/* BtnezT8SltiX16 */	----
17736	CPU16Regs, simm16, brtarget,	----
17737	/* BtnezT8SltiuX16 */	----
17738	CPU16Regs, simm16, brtarget,	----
17739	/* BtnezT8SltuX16 */	----
17740	CPU16Regs, CPU16Regs, brtarget,	----
17741	/* BuildPairF64 */	----
17742	AFGR64Opnd, GPR32Opnd, GPR32Opnd,	----
17743	/* BuildPairF64_64 */	----
17744	FGR64Opnd, GPR32Opnd, GPR32Opnd,	----
17745	/* CFTC1 */	----
17746	GPR32Opnd, FGRCCOpnd,	----
17747	/* CONSTPOOL_ENTRY */	----
17748	cpinst_operand, cpinst_operand, i32imm,	----
17749	/* COPY_FD_PSEUDO */	----
17750	FGR64, MSA128D, uimm1_ptr,	----
17751	/* COPY_FW_PSEUDO */	----
17752	FGR32, MSA128W, uimm2_ptr,	----
17753	/* CTTC1 */	----
17754	FGRCCOpnd, GPR32Opnd,	----
17755	/* Constant32 */	----
17756	simm32,	----
17757	/* DMULImmMacro */	----
17758	GPR64Opnd, GPR64Opnd, simm32_relaxed,	----
17759	/* DMULMacro */	----
17760	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17761	/* DMULOMacro */	----
17762	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17763	/* DMULOUMacro */	----
17764	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17765	/* DROL */	----
17766	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
17767	/* DROLImm */	----
17768	GPR32Opnd, GPR32Opnd, simm16,	----
17769	/* DROR */	----
17770	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
17771	/* DRORImm */	----
17772	GPR32Opnd, GPR32Opnd, simm16,	----
17773	/* DSDivIMacro */	----
17774	GPR64Opnd, GPR64Opnd, imm64,	----
17775	/* DSDivMacro */	----
17776	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17777	/* DSRemIMacro */	----
17778	GPR64Opnd, GPR64Opnd, simm32_relaxed,	----
17779	/* DSRemMacro */	----
17780	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17781	/* DUDivIMacro */	----
17782	GPR64Opnd, GPR64Opnd, imm64,	----
17783	/* DUDivMacro */	----
17784	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17785	/* DURemIMacro */	----
17786	GPR64Opnd, GPR64Opnd, simm32_relaxed,	----
17787	/* DURemMacro */	----
17788	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
17789	/* ERet */	----
17790	/* ExtractElementF64 */	----
17791	GPR32Opnd, AFGR64Opnd, i32imm,	----
17792	/* ExtractElementF64_64 */	----
17793	GPR32Opnd, FGR64Opnd, i32imm,	----
17794	/* FABS_D */	----
17795	MSA128DOpnd, MSA128DOpnd,	----
17796	/* FABS_W */	----
17797	MSA128WOpnd, MSA128WOpnd,	----
17798	/* FEXP2_D_1_PSEUDO */	----
17799	MSA128D, MSA128D,	----
17800	/* FEXP2_W_1_PSEUDO */	----
17801	MSA128W, MSA128W,	----
17802	/* FILL_FD_PSEUDO */	----
17803	MSA128D, FGR64,	----
17804	/* FILL_FW_PSEUDO */	----
17805	MSA128W, FGR32,	----
17806	/* GotPrologue16 */	----
17807	CPU16Regs, CPU16Regs, simm16, simm16,	----
17808	/* INSERT_B_VIDX64_PSEUDO */	----
17809	MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,	----
17810	/* INSERT_B_VIDX_PSEUDO */	----
17811	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,	----
17812	/* INSERT_D_VIDX64_PSEUDO */	----
17813	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,	----
17814	/* INSERT_D_VIDX_PSEUDO */	----
17815	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,	----
17816	/* INSERT_FD_PSEUDO */	----
17817	MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,	----
17818	/* INSERT_FD_VIDX64_PSEUDO */	----
17819	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,	----
17820	/* INSERT_FD_VIDX_PSEUDO */	----
17821	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,	----
17822	/* INSERT_FW_PSEUDO */	----
17823	MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,	----
17824	/* INSERT_FW_VIDX64_PSEUDO */	----
17825	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,	----
17826	/* INSERT_FW_VIDX_PSEUDO */	----
17827	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,	----
17828	/* INSERT_H_VIDX64_PSEUDO */	----
17829	MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,	----
17830	/* INSERT_H_VIDX_PSEUDO */	----
17831	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,	----
17832	/* INSERT_W_VIDX64_PSEUDO */	----
17833	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,	----
17834	/* INSERT_W_VIDX_PSEUDO */	----
17835	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,	----
17836	/* JALR64Pseudo */	----
17837	GPR64Opnd,	----
17838	/* JALRHB64Pseudo */	----
17839	GPR64Opnd,	----
17840	/* JALRHBPseudo */	----
17841	GPR32Opnd,	----
17842	/* JALRPseudo */	----
17843	GPR32Opnd,	----
17844	/* JAL_MMR6 */	----
17845	calltarget,	----
17846	/* JalOneReg */	----
17847	GPR32Opnd,	----
17848	/* JalTwoReg */	----
17849	GPR32Opnd, GPR32Opnd,	----
17850	/* LDMacro */	----
17851	GPR32Opnd, -1, simm16,	----
17852	/* LDR_D */	----
17853	MSA128DOpnd, -1, GPR32,	----
17854	/* LDR_W */	----
17855	MSA128WOpnd, -1, GPR32,	----
17856	/* LD_F16 */	----
17857	MSA128F16, -1, simm10,	----
17858	/* LOAD_ACC128 */	----
17859	ACC128, -1, simm16,	----
17860	/* LOAD_ACC64 */	----
17861	ACC64, -1, simm16,	----
17862	/* LOAD_ACC64DSP */	----
17863	ACC64DSPOpnd, -1, simm16,	----
17864	/* LOAD_CCOND_DSP */	----
17865	DSPCC, -1, simm16,	----
17866	/* LONG_BRANCH_ADDiu */	----
17867	GPR32Opnd, GPR32Opnd, brtarget, brtarget,	----
17868	/* LONG_BRANCH_ADDiu2Op */	----
17869	GPR32Opnd, GPR32Opnd, brtarget,	----
17870	/* LONG_BRANCH_DADDiu */	----
17871	GPR64Opnd, GPR64Opnd, brtarget, brtarget,	----
17872	/* LONG_BRANCH_DADDiu2Op */	----
17873	GPR64Opnd, GPR64Opnd, brtarget,	----
17874	/* LONG_BRANCH_LUi */	----
17875	GPR32Opnd, brtarget, brtarget,	----
17876	/* LONG_BRANCH_LUi2Op */	----
17877	GPR32Opnd, brtarget,	----
17878	/* LONG_BRANCH_LUi2Op_64 */	----
17879	GPR64Opnd, brtarget,	----
17880	/* LWM_MM */	----
17881	reglist, -1, simm12,	----
17882	/* LoadAddrImm32 */	----
17883	GPR32Opnd, i32imm,	----
17884	/* LoadAddrImm64 */	----
17885	GPR64Opnd, imm64,	----
17886	/* LoadAddrReg32 */	----
17887	GPR32Opnd, -1, simm16,	----
17888	/* LoadAddrReg64 */	----
17889	GPR64Opnd, -1, simm16,	----
17890	/* LoadImm32 */	----
17891	GPR32Opnd, uimm32_coerced,	----
17892	/* LoadImm64 */	----
17893	GPR64Opnd, imm64,	----
17894	/* LoadImmDoubleFGR */	----
17895	StrictlyFGR64Opnd, imm64,	----
17896	/* LoadImmDoubleFGR_32 */	----
17897	StrictlyAFGR64Opnd, imm64,	----
17898	/* LoadImmDoubleGPR */	----
17899	GPR32Opnd, imm64,	----
17900	/* LoadImmSingleFGR */	----
17901	StrictlyFGR32Opnd, imm64,	----
17902	/* LoadImmSingleGPR */	----
17903	GPR32Opnd, imm64,	----
17904	/* LwConstant32 */	----
17905	CPU16Regs, simm32, simm32,	----
17906	/* MFTACX */	----
17907	GPR32Opnd, ACC64DSPOpnd,	----
17908	/* MFTC0 */	----
17909	GPR32Opnd, COP0Opnd, uimm3,	----
17910	/* MFTC1 */	----
17911	GPR32Opnd, FGR32Opnd,	----
17912	/* MFTDSP */	----
17913	GPR32Opnd,	----
17914	/* MFTGPR */	----
17915	GPR32Opnd, GPR32Opnd, uimm3,	----
17916	/* MFTHC1 */	----
17917	GPR32Opnd, FGR32Opnd,	----
17918	/* MFTHI */	----
17919	GPR32Opnd, ACC64DSPOpnd,	----
17920	/* MFTLO */	----
17921	GPR32Opnd, ACC64DSPOpnd,	----
17922	/* MIPSeh_return32 */	----
17923	GPR32, GPR32,	----
17924	/* MIPSeh_return64 */	----
17925	GPR64, GPR64,	----
17926	/* MSA_FP_EXTEND_D_PSEUDO */	----
17927	FGR64Opnd, MSA128F16,	----
17928	/* MSA_FP_EXTEND_W_PSEUDO */	----
17929	FGR32Opnd, MSA128F16,	----
17930	/* MSA_FP_ROUND_D_PSEUDO */	----
17931	MSA128F16, FGR64Opnd,	----
17932	/* MSA_FP_ROUND_W_PSEUDO */	----
17933	MSA128F16, FGR32Opnd,	----
17934	/* MTTACX */	----
17935	ACC64DSPOpnd, GPR32Opnd,	----
17936	/* MTTC0 */	----
17937	COP0Opnd, GPR32Opnd, uimm3,	----
17938	/* MTTC1 */	----
17939	FGR32Opnd, GPR32Opnd,	----
17940	/* MTTDSP */	----
17941	GPR32Opnd,	----
17942	/* MTTGPR */	----
17943	GPR32Opnd, GPR32Opnd,	----
17944	/* MTTHC1 */	----
17945	FGR32Opnd, GPR32Opnd,	----
17946	/* MTTHI */	----
17947	ACC64DSPOpnd, GPR32Opnd,	----
17948	/* MTTLO */	----
17949	ACC64DSPOpnd, GPR32Opnd,	----
17950	/* MULImmMacro */	----
17951	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
17952	/* MULOMacro */	----
17953	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
17954	/* MULOUMacro */	----
17955	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
17956	/* MultRxRy16 */	----
17957	CPU16Regs, CPU16Regs,	----
17958	/* MultRxRyRz16 */	----
17959	CPU16Regs, CPU16Regs, CPU16Regs,	----
17960	/* MultuRxRy16 */	----
17961	CPU16Regs, CPU16Regs,	----
17962	/* MultuRxRyRz16 */	----
17963	CPU16Regs, CPU16Regs, CPU16Regs,	----
17964	/* NOP */	----
17965	/* NORImm */	----
17966	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
17967	/* NORImm64 */	----
17968	GPR64Opnd, GPR64Opnd, imm64,	----
17969	/* NOR_V_D_PSEUDO */	----
17970	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
17971	/* NOR_V_H_PSEUDO */	----
17972	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
17973	/* NOR_V_W_PSEUDO */	----
17974	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
17975	/* OR_V_D_PSEUDO */	----
17976	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
17977	/* OR_V_H_PSEUDO */	----
17978	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
17979	/* OR_V_W_PSEUDO */	----
17980	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
17981	/* PseudoCMPU_EQ_QB */	----
17982	DSPCC, DSPROpnd, DSPROpnd,	----
17983	/* PseudoCMPU_LE_QB */	----
17984	DSPCC, DSPROpnd, DSPROpnd,	----
17985	/* PseudoCMPU_LT_QB */	----
17986	DSPCC, DSPROpnd, DSPROpnd,	----
17987	/* PseudoCMP_EQ_PH */	----
17988	DSPCC, DSPROpnd, DSPROpnd,	----
17989	/* PseudoCMP_LE_PH */	----
17990	DSPCC, DSPROpnd, DSPROpnd,	----
17991	/* PseudoCMP_LT_PH */	----
17992	DSPCC, DSPROpnd, DSPROpnd,	----
17993	/* PseudoCVT_D32_W */	----
17994	AFGR64Opnd, GPR32Opnd,	----
17995	/* PseudoCVT_D64_L */	----
17996	FGR64Opnd, GPR64Opnd,	----
17997	/* PseudoCVT_D64_W */	----
17998	FGR64Opnd, GPR32Opnd,	----
17999	/* PseudoCVT_S_L */	----
18000	FGR64Opnd, GPR64Opnd,	----
18001	/* PseudoCVT_S_W */	----
18002	FGR32Opnd, GPR32Opnd,	----
18003	/* PseudoDMULT */	----
18004	ACC128, GPR64Opnd, GPR64Opnd,	----
18005	/* PseudoDMULTu */	----
18006	ACC128, GPR64Opnd, GPR64Opnd,	----
18007	/* PseudoDSDIV */	----
18008	ACC128, GPR64Opnd, GPR64Opnd,	----
18009	/* PseudoDUDIV */	----
18010	ACC128, GPR64Opnd, GPR64Opnd,	----
18011	/* PseudoD_SELECT_I */	----
18012	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18013	/* PseudoD_SELECT_I64 */	----
18014	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
18015	/* PseudoIndirectBranch */	----
18016	GPR32Opnd,	----
18017	/* PseudoIndirectBranch64 */	----
18018	GPR64Opnd,	----
18019	/* PseudoIndirectBranch64R6 */	----
18020	GPR64Opnd,	----
18021	/* PseudoIndirectBranchR6 */	----
18022	GPR32Opnd,	----
18023	/* PseudoIndirectBranch_MM */	----
18024	GPR32Opnd,	----
18025	/* PseudoIndirectBranch_MMR6 */	----
18026	GPR32Opnd,	----
18027	/* PseudoIndirectHazardBranch */	----
18028	GPR32Opnd,	----
18029	/* PseudoIndirectHazardBranch64 */	----
18030	GPR64Opnd,	----
18031	/* PseudoIndrectHazardBranch64R6 */	----
18032	GPR64Opnd,	----
18033	/* PseudoIndrectHazardBranchR6 */	----
18034	GPR32Opnd,	----
18035	/* PseudoMADD */	----
18036	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18037	/* PseudoMADDU */	----
18038	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18039	/* PseudoMADDU_MM */	----
18040	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18041	/* PseudoMADD_MM */	----
18042	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18043	/* PseudoMFHI */	----
18044	GPR32, ACC64,	----
18045	/* PseudoMFHI64 */	----
18046	GPR64, ACC128,	----
18047	/* PseudoMFHI_MM */	----
18048	GPR32, ACC64,	----
18049	/* PseudoMFLO */	----
18050	GPR32, ACC64,	----
18051	/* PseudoMFLO64 */	----
18052	GPR64, ACC128,	----
18053	/* PseudoMFLO_MM */	----
18054	GPR32, ACC64,	----
18055	/* PseudoMSUB */	----
18056	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18057	/* PseudoMSUBU */	----
18058	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18059	/* PseudoMSUBU_MM */	----
18060	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18061	/* PseudoMSUB_MM */	----
18062	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	----
18063	/* PseudoMTLOHI */	----
18064	ACC64, GPR32, GPR32,	----
18065	/* PseudoMTLOHI64 */	----
18066	ACC128, GPR64, GPR64,	----
18067	/* PseudoMTLOHI_DSP */	----
18068	ACC64DSP, GPR32, GPR32,	----
18069	/* PseudoMTLOHI_MM */	----
18070	ACC64, GPR32, GPR32,	----
18071	/* PseudoMULT */	----
18072	ACC64, GPR32Opnd, GPR32Opnd,	----
18073	/* PseudoMULT_MM */	----
18074	ACC64, GPR32Opnd, GPR32Opnd,	----
18075	/* PseudoMULTu */	----
18076	ACC64, GPR32Opnd, GPR32Opnd,	----
18077	/* PseudoMULTu_MM */	----
18078	ACC64, GPR32Opnd, GPR32Opnd,	----
18079	/* PseudoPICK_PH */	----
18080	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	----
18081	/* PseudoPICK_QB */	----
18082	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	----
18083	/* PseudoReturn */	----
18084	GPR32Opnd,	----
18085	/* PseudoReturn64 */	----
18086	GPR64Opnd,	----
18087	/* PseudoSDIV */	----
18088	ACC64, GPR32Opnd, GPR32Opnd,	----
18089	/* PseudoSELECTFP_F_D32 */	----
18090	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
18091	/* PseudoSELECTFP_F_D64 */	----
18092	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
18093	/* PseudoSELECTFP_F_I */	----
18094	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	----
18095	/* PseudoSELECTFP_F_I64 */	----
18096	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	----
18097	/* PseudoSELECTFP_F_S */	----
18098	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
18099	/* PseudoSELECTFP_T_D32 */	----
18100	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
18101	/* PseudoSELECTFP_T_D64 */	----
18102	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
18103	/* PseudoSELECTFP_T_I */	----
18104	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	----
18105	/* PseudoSELECTFP_T_I64 */	----
18106	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	----
18107	/* PseudoSELECTFP_T_S */	----
18108	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
18109	/* PseudoSELECT_D32 */	----
18110	AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,	----
18111	/* PseudoSELECT_D64 */	----
18112	FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,	----
18113	/* PseudoSELECT_I */	----
18114	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18115	/* PseudoSELECT_I64 */	----
18116	GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,	----
18117	/* PseudoSELECT_S */	----
18118	FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,	----
18119	/* PseudoTRUNC_W_D */	----
18120	FGR32Opnd, FGR64Opnd, GPR32Opnd,	----
18121	/* PseudoTRUNC_W_D32 */	----
18122	FGR32Opnd, AFGR64Opnd, GPR32Opnd,	----
18123	/* PseudoTRUNC_W_S */	----
18124	FGR32Opnd, FGR32Opnd, GPR32Opnd,	----
18125	/* PseudoUDIV */	----
18126	ACC64, GPR32Opnd, GPR32Opnd,	----
18127	/* ROL */	----
18128	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18129	/* ROLImm */	----
18130	GPR32Opnd, GPR32Opnd, simm16,	----
18131	/* ROR */	----
18132	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18133	/* RORImm */	----
18134	GPR32Opnd, GPR32Opnd, simm16,	----
18135	/* RetRA */	----
18136	/* RetRA16 */	----
18137	/* SDC1_M1 */	----
18138	AFGR64Opnd, -1, simm16,	----
18139	/* SDIV_MM_Pseudo */	----
18140	ACC64, GPR32Opnd, GPR32Opnd,	----
18141	/* SDMacro */	----
18142	GPR32Opnd, -1, simm16,	----
18143	/* SDivIMacro */	----
18144	GPR32Opnd, GPR32Opnd, simm32,	----
18145	/* SDivMacro */	----
18146	GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,	----
18147	/* SEQIMacro */	----
18148	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
18149	/* SEQMacro */	----
18150	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18151	/* SGE */	----
18152	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18153	/* SGEImm */	----
18154	GPR32Opnd, GPR32Opnd, simm32,	----
18155	/* SGEImm64 */	----
18156	GPR64Opnd, GPR64Opnd, imm64,	----
18157	/* SGEU */	----
18158	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18159	/* SGEUImm */	----
18160	GPR32Opnd, GPR32Opnd, uimm32_coerced,	----
18161	/* SGEUImm64 */	----
18162	GPR64Opnd, GPR64Opnd, imm64,	----
18163	/* SGTImm */	----
18164	GPR32Opnd, GPR32Opnd, simm32,	----
18165	/* SGTImm64 */	----
18166	GPR64Opnd, GPR64Opnd, imm64,	----
18167	/* SGTUImm */	----
18168	GPR32Opnd, GPR32Opnd, uimm32_coerced,	----
18169	/* SGTUImm64 */	----
18170	GPR64Opnd, GPR64Opnd, imm64,	----
18171	/* SLE */	----
18172	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18173	/* SLEImm */	----
18174	GPR32Opnd, GPR32Opnd, simm32,	----
18175	/* SLEImm64 */	----
18176	GPR64Opnd, GPR64Opnd, imm64,	----
18177	/* SLEU */	----
18178	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18179	/* SLEUImm */	----
18180	GPR32Opnd, GPR32Opnd, uimm32_coerced,	----
18181	/* SLEUImm64 */	----
18182	GPR64Opnd, GPR64Opnd, imm64,	----
18183	/* SLTImm64 */	----
18184	GPR64Opnd, GPR64Opnd, imm64,	----
18185	/* SLTUImm64 */	----
18186	GPR64Opnd, GPR64Opnd, imm64,	----
18187	/* SNEIMacro */	----
18188	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
18189	/* SNEMacro */	----
18190	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18191	/* SNZ_B_PSEUDO */	----
18192	GPR32, MSA128B,	----
18193	/* SNZ_D_PSEUDO */	----
18194	GPR32, MSA128D,	----
18195	/* SNZ_H_PSEUDO */	----
18196	GPR32, MSA128H,	----
18197	/* SNZ_V_PSEUDO */	----
18198	GPR32, MSA128B,	----
18199	/* SNZ_W_PSEUDO */	----
18200	GPR32, MSA128W,	----
18201	/* SRemIMacro */	----
18202	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
18203	/* SRemMacro */	----
18204	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18205	/* STORE_ACC128 */	----
18206	ACC128, -1, simm16,	----
18207	/* STORE_ACC64 */	----
18208	ACC64, -1, simm16,	----
18209	/* STORE_ACC64DSP */	----
18210	ACC64DSPOpnd, -1, simm16,	----
18211	/* STORE_CCOND_DSP */	----
18212	DSPCC, -1, simm16,	----
18213	/* STR_D */	----
18214	MSA128DOpnd, -1, GPR32,	----
18215	/* STR_W */	----
18216	MSA128WOpnd, -1, GPR32,	----
18217	/* ST_F16 */	----
18218	MSA128F16, -1, simm10,	----
18219	/* SWM_MM */	----
18220	reglist, -1, simm12,	----
18221	/* SZ_B_PSEUDO */	----
18222	GPR32, MSA128B,	----
18223	/* SZ_D_PSEUDO */	----
18224	GPR32, MSA128D,	----
18225	/* SZ_H_PSEUDO */	----
18226	GPR32, MSA128H,	----
18227	/* SZ_V_PSEUDO */	----
18228	GPR32, MSA128B,	----
18229	/* SZ_W_PSEUDO */	----
18230	GPR32, MSA128W,	----
18231	/* SaaAddr */	----
18232	GPR64Opnd, -1, simm16,	----
18233	/* SaadAddr */	----
18234	GPR64Opnd, -1, simm16,	----
18235	/* SelBeqZ */	----
18236	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18237	/* SelBneZ */	----
18238	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18239	/* SelTBteqZCmp */	----
18240	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18241	/* SelTBteqZCmpi */	----
18242	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18243	/* SelTBteqZSlt */	----
18244	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18245	/* SelTBteqZSlti */	----
18246	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18247	/* SelTBteqZSltiu */	----
18248	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18249	/* SelTBteqZSltu */	----
18250	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18251	/* SelTBtneZCmp */	----
18252	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18253	/* SelTBtneZCmpi */	----
18254	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18255	/* SelTBtneZSlt */	----
18256	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18257	/* SelTBtneZSlti */	----
18258	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18259	/* SelTBtneZSltiu */	----
18260	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	----
18261	/* SelTBtneZSltu */	----
18262	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	----
18263	/* SltCCRxRy16 */	----
18264	CPU16Regs, CPU16Regs, CPU16Regs,	----
18265	/* SltiCCRxImmX16 */	----
18266	CPU16Regs, CPU16Regs, simm16,	----
18267	/* SltiuCCRxImmX16 */	----
18268	CPU16Regs, CPU16Regs, simm16,	----
18269	/* SltuCCRxRy16 */	----
18270	CPU16Regs, CPU16Regs, CPU16Regs,	----
18271	/* SltuRxRyRz16 */	----
18272	CPU16Regs, CPU16Regs, CPU16Regs,	----
18273	/* TAILCALL */	----
18274	calltarget,	----
18275	/* TAILCALL64R6REG */	----
18276	GPR64Opnd,	----
18277	/* TAILCALLHB64R6REG */	----
18278	GPR64Opnd,	----
18279	/* TAILCALLHBR6REG */	----
18280	GPR32Opnd,	----
18281	/* TAILCALLR6REG */	----
18282	GPR32Opnd,	----
18283	/* TAILCALLREG */	----
18284	GPR32Opnd,	----
18285	/* TAILCALLREG64 */	----
18286	GPR64Opnd,	----
18287	/* TAILCALLREGHB */	----
18288	GPR32Opnd,	----
18289	/* TAILCALLREGHB64 */	----
18290	GPR64Opnd,	----
18291	/* TAILCALLREG_MM */	----
18292	GPR32Opnd,	----
18293	/* TAILCALLREG_MMR6 */	----
18294	GPR32Opnd,	----
18295	/* TAILCALL_MM */	----
18296	calltarget,	----
18297	/* TAILCALL_MMR6 */	----
18298	calltarget,	----
18299	/* TRAP */	----
18300	/* TRAP_MM */	----
18301	/* UDIV_MM_Pseudo */	----
18302	ACC64, GPR32Opnd, GPR32Opnd,	----
18303	/* UDivIMacro */	----
18304	GPR32Opnd, GPR32Opnd, simm32,	----
18305	/* UDivMacro */	----
18306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18307	/* URemIMacro */	----
18308	GPR32Opnd, GPR32Opnd, simm32_relaxed,	----
18309	/* URemMacro */	----
18310	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18311	/* Ulh */	----
18312	GPR32Opnd, -1, simm16,	----
18313	/* Ulhu */	----
18314	GPR32Opnd, -1, simm16,	----
18315	/* Ulw */	----
18316	GPR32Opnd, -1, simm16,	----
18317	/* Ush */	----
18318	GPR32Opnd, -1, simm16,	----
18319	/* Usw */	----
18320	GPR32Opnd, -1, simm16,	----
18321	/* XOR_V_D_PSEUDO */	----
18322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18323	/* XOR_V_H_PSEUDO */	----
18324	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18325	/* XOR_V_W_PSEUDO */	----
18326	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18327	/* ABSQ_S_PH */	----
18328	DSPROpnd, DSPROpnd,	----
18329	/* ABSQ_S_PH_MM */	----
18330	DSPROpnd, DSPROpnd,	----
18331	/* ABSQ_S_QB */	----
18332	DSPROpnd, DSPROpnd,	----
18333	/* ABSQ_S_QB_MMR2 */	----
18334	DSPROpnd, DSPROpnd,	----
18335	/* ABSQ_S_W */	----
18336	GPR32Opnd, GPR32Opnd,	----
18337	/* ABSQ_S_W_MM */	----
18338	GPR32Opnd, GPR32Opnd,	----
18339	/* ADD */	----
18340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18341	/* ADDIUPC */	----
18342	GPR32Opnd, simm19_lsl2,	----
18343	/* ADDIUPC_MM */	----
18344	GPRMM16Opnd, simm23_lsl2,	----
18345	/* ADDIUPC_MMR6 */	----
18346	GPR32Opnd, simm19_lsl2,	----
18347	/* ADDIUR1SP_MM */	----
18348	GPRMM16Opnd, uimm6_lsl2,	----
18349	/* ADDIUR2_MM */	----
18350	GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,	----
18351	/* ADDIUS5_MM */	----
18352	GPR32Opnd, GPR32Opnd, simm4,	----
18353	/* ADDIUSP_MM */	----
18354	simm9_addiusp,	----
18355	/* ADDIU_MMR6 */	----
18356	GPR32Opnd, GPR32Opnd, simm16,	----
18357	/* ADDQH_PH */	----
18358	DSPROpnd, DSPROpnd, DSPROpnd,	----
18359	/* ADDQH_PH_MMR2 */	----
18360	DSPROpnd, DSPROpnd, DSPROpnd,	----
18361	/* ADDQH_R_PH */	----
18362	DSPROpnd, DSPROpnd, DSPROpnd,	----
18363	/* ADDQH_R_PH_MMR2 */	----
18364	DSPROpnd, DSPROpnd, DSPROpnd,	----
18365	/* ADDQH_R_W */	----
18366	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18367	/* ADDQH_R_W_MMR2 */	----
18368	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18369	/* ADDQH_W */	----
18370	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18371	/* ADDQH_W_MMR2 */	----
18372	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18373	/* ADDQ_PH */	----
18374	DSPROpnd, DSPROpnd, DSPROpnd,	----
18375	/* ADDQ_PH_MM */	----
18376	DSPROpnd, DSPROpnd, DSPROpnd,	----
18377	/* ADDQ_S_PH */	----
18378	DSPROpnd, DSPROpnd, DSPROpnd,	----
18379	/* ADDQ_S_PH_MM */	----
18380	DSPROpnd, DSPROpnd, DSPROpnd,	----
18381	/* ADDQ_S_W */	----
18382	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18383	/* ADDQ_S_W_MM */	----
18384	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18385	/* ADDR_PS64 */	----
18386	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
18387	/* ADDSC */	----
18388	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18389	/* ADDSC_MM */	----
18390	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18391	/* ADDS_A_B */	----
18392	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18393	/* ADDS_A_D */	----
18394	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18395	/* ADDS_A_H */	----
18396	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18397	/* ADDS_A_W */	----
18398	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18399	/* ADDS_S_B */	----
18400	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18401	/* ADDS_S_D */	----
18402	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18403	/* ADDS_S_H */	----
18404	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18405	/* ADDS_S_W */	----
18406	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18407	/* ADDS_U_B */	----
18408	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18409	/* ADDS_U_D */	----
18410	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18411	/* ADDS_U_H */	----
18412	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18413	/* ADDS_U_W */	----
18414	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18415	/* ADDU16_MM */	----
18416	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
18417	/* ADDU16_MMR6 */	----
18418	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
18419	/* ADDUH_QB */	----
18420	DSPROpnd, DSPROpnd, DSPROpnd,	----
18421	/* ADDUH_QB_MMR2 */	----
18422	DSPROpnd, DSPROpnd, DSPROpnd,	----
18423	/* ADDUH_R_QB */	----
18424	DSPROpnd, DSPROpnd, DSPROpnd,	----
18425	/* ADDUH_R_QB_MMR2 */	----
18426	DSPROpnd, DSPROpnd, DSPROpnd,	----
18427	/* ADDU_MMR6 */	----
18428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18429	/* ADDU_PH */	----
18430	DSPROpnd, DSPROpnd, DSPROpnd,	----
18431	/* ADDU_PH_MMR2 */	----
18432	DSPROpnd, DSPROpnd, DSPROpnd,	----
18433	/* ADDU_QB */	----
18434	DSPROpnd, DSPROpnd, DSPROpnd,	----
18435	/* ADDU_QB_MM */	----
18436	DSPROpnd, DSPROpnd, DSPROpnd,	----
18437	/* ADDU_S_PH */	----
18438	DSPROpnd, DSPROpnd, DSPROpnd,	----
18439	/* ADDU_S_PH_MMR2 */	----
18440	DSPROpnd, DSPROpnd, DSPROpnd,	----
18441	/* ADDU_S_QB */	----
18442	DSPROpnd, DSPROpnd, DSPROpnd,	----
18443	/* ADDU_S_QB_MM */	----
18444	DSPROpnd, DSPROpnd, DSPROpnd,	----
18445	/* ADDVI_B */	----
18446	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
18447	/* ADDVI_D */	----
18448	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
18449	/* ADDVI_H */	----
18450	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
18451	/* ADDVI_W */	----
18452	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18453	/* ADDV_B */	----
18454	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18455	/* ADDV_D */	----
18456	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18457	/* ADDV_H */	----
18458	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18459	/* ADDV_W */	----
18460	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18461	/* ADDWC */	----
18462	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18463	/* ADDWC_MM */	----
18464	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18465	/* ADD_A_B */	----
18466	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18467	/* ADD_A_D */	----
18468	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18469	/* ADD_A_H */	----
18470	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18471	/* ADD_A_W */	----
18472	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18473	/* ADD_MM */	----
18474	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18475	/* ADD_MMR6 */	----
18476	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18477	/* ADDi */	----
18478	GPR32Opnd, GPR32Opnd, simm16_relaxed,	----
18479	/* ADDi_MM */	----
18480	GPR32Opnd, GPR32Opnd, simm16,	----
18481	/* ADDiu */	----
18482	GPR32Opnd, GPR32Opnd, simm16_relaxed,	----
18483	/* ADDiu_MM */	----
18484	GPR32Opnd, GPR32Opnd, simm16,	----
18485	/* ADDu */	----
18486	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18487	/* ADDu_MM */	----
18488	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18489	/* ALIGN */	----
18490	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	----
18491	/* ALIGN_MMR6 */	----
18492	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	----
18493	/* ALUIPC */	----
18494	GPR32Opnd, simm16,	----
18495	/* ALUIPC_MMR6 */	----
18496	GPR32Opnd, simm16,	----
18497	/* AND */	----
18498	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18499	/* AND16_MM */	----
18500	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
18501	/* AND16_MMR6 */	----
18502	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
18503	/* AND64 */	----
18504	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
18505	/* ANDI16_MM */	----
18506	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	----
18507	/* ANDI16_MMR6 */	----
18508	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	----
18509	/* ANDI_B */	----
18510	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
18511	/* ANDI_MMR6 */	----
18512	GPR32Opnd, GPR32Opnd, uimm16,	----
18513	/* AND_MM */	----
18514	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18515	/* AND_MMR6 */	----
18516	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
18517	/* AND_V */	----
18518	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18519	/* ANDi */	----
18520	GPR32Opnd, GPR32Opnd, uimm16,	----
18521	/* ANDi64 */	----
18522	GPR64Opnd, GPR64Opnd, uimm16_64,	----
18523	/* ANDi_MM */	----
18524	GPR32Opnd, GPR32Opnd, uimm16,	----
18525	/* APPEND */	----
18526	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	----
18527	/* APPEND_MMR2 */	----
18528	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	----
18529	/* ASUB_S_B */	----
18530	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18531	/* ASUB_S_D */	----
18532	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18533	/* ASUB_S_H */	----
18534	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18535	/* ASUB_S_W */	----
18536	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18537	/* ASUB_U_B */	----
18538	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18539	/* ASUB_U_D */	----
18540	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18541	/* ASUB_U_H */	----
18542	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18543	/* ASUB_U_W */	----
18544	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18545	/* AUI */	----
18546	GPR32Opnd, GPR32Opnd, uimm16,	----
18547	/* AUIPC */	----
18548	GPR32Opnd, simm16,	----
18549	/* AUIPC_MMR6 */	----
18550	GPR32Opnd, simm16,	----
18551	/* AUI_MMR6 */	----
18552	GPR32Opnd, GPR32Opnd, uimm16,	----
18553	/* AVER_S_B */	----
18554	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18555	/* AVER_S_D */	----
18556	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18557	/* AVER_S_H */	----
18558	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18559	/* AVER_S_W */	----
18560	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18561	/* AVER_U_B */	----
18562	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18563	/* AVER_U_D */	----
18564	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18565	/* AVER_U_H */	----
18566	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18567	/* AVER_U_W */	----
18568	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18569	/* AVE_S_B */	----
18570	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18571	/* AVE_S_D */	----
18572	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18573	/* AVE_S_H */	----
18574	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18575	/* AVE_S_W */	----
18576	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18577	/* AVE_U_B */	----
18578	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18579	/* AVE_U_D */	----
18580	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18581	/* AVE_U_H */	----
18582	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18583	/* AVE_U_W */	----
18584	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18585	/* AddiuRxImmX16 */	----
18586	CPU16Regs, simm16,	----
18587	/* AddiuRxPcImmX16 */	----
18588	CPU16Regs, simm16,	----
18589	/* AddiuRxRxImm16 */	----
18590	CPU16Regs, CPU16Regs, simm16,	----
18591	/* AddiuRxRxImmX16 */	----
18592	CPU16Regs, CPU16Regs, simm16,	----
18593	/* AddiuRxRyOffMemX16 */	----
18594	CPU16Regs, CPU16RegsPlusSP, simm16,	----
18595	/* AddiuSpImm16 */	----
18596	simm16,	----
18597	/* AddiuSpImmX16 */	----
18598	simm16,	----
18599	/* AdduRxRyRz16 */	----
18600	CPU16Regs, CPU16Regs, CPU16Regs,	----
18601	/* AndRxRxRy16 */	----
18602	CPU16Regs, CPU16Regs, CPU16Regs,	----
18603	/* B16_MM */	----
18604	brtarget10_mm,	----
18605	/* BADDu */	----
18606	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
18607	/* BAL */	----
18608	brtarget,	----
18609	/* BALC */	----
18610	brtarget26,	----
18611	/* BALC_MMR6 */	----
18612	brtarget26_mm,	----
18613	/* BALIGN */	----
18614	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	----
18615	/* BALIGN_MMR2 */	----
18616	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	----
18617	/* BBIT0 */	----
18618	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	----
18619	/* BBIT032 */	----
18620	GPR64Opnd, uimm5_64, brtarget,	----
18621	/* BBIT1 */	----
18622	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	----
18623	/* BBIT132 */	----
18624	GPR64Opnd, uimm5_64, brtarget,	----
18625	/* BC */	----
18626	brtarget26,	----
18627	/* BC16_MMR6 */	----
18628	brtarget10_mm,	----
18629	/* BC1EQZ */	----
18630	FGR64Opnd, brtarget,	----
18631	/* BC1EQZC_MMR6 */	----
18632	FGR64Opnd, brtarget_mm,	----
18633	/* BC1F */	----
18634	FCCRegsOpnd, brtarget,	----
18635	/* BC1FL */	----
18636	FCCRegsOpnd, brtarget,	----
18637	/* BC1F_MM */	----
18638	FCCRegsOpnd, brtarget_mm,	----
18639	/* BC1NEZ */	----
18640	FGR64Opnd, brtarget,	----
18641	/* BC1NEZC_MMR6 */	----
18642	FGR64Opnd, brtarget_mm,	----
18643	/* BC1T */	----
18644	FCCRegsOpnd, brtarget,	----
18645	/* BC1TL */	----
18646	FCCRegsOpnd, brtarget,	----
18647	/* BC1T_MM */	----
18648	FCCRegsOpnd, brtarget_mm,	----
18649	/* BC2EQZ */	----
18650	COP2Opnd, brtarget,	----
18651	/* BC2EQZC_MMR6 */	----
18652	COP2Opnd, brtarget_mm,	----
18653	/* BC2NEZ */	----
18654	COP2Opnd, brtarget,	----
18655	/* BC2NEZC_MMR6 */	----
18656	COP2Opnd, brtarget_mm,	----
18657	/* BCLRI_B */	----
18658	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
18659	/* BCLRI_D */	----
18660	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
18661	/* BCLRI_H */	----
18662	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
18663	/* BCLRI_W */	----
18664	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18665	/* BCLR_B */	----
18666	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18667	/* BCLR_D */	----
18668	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18669	/* BCLR_H */	----
18670	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18671	/* BCLR_W */	----
18672	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18673	/* BC_MMR6 */	----
18674	brtarget26_mm,	----
18675	/* BEQ */	----
18676	GPR32Opnd, GPR32Opnd, brtarget,	----
18677	/* BEQ64 */	----
18678	GPR64Opnd, GPR64Opnd, brtarget,	----
18679	/* BEQC */	----
18680	GPR32Opnd, GPR32Opnd, brtarget,	----
18681	/* BEQC64 */	----
18682	GPR64Opnd, GPR64Opnd, brtarget,	----
18683	/* BEQC_MMR6 */	----
18684	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18685	/* BEQL */	----
18686	GPR32Opnd, GPR32Opnd, brtarget,	----
18687	/* BEQZ16_MM */	----
18688	GPRMM16Opnd, brtarget7_mm,	----
18689	/* BEQZALC */	----
18690	GPR32Opnd, brtarget,	----
18691	/* BEQZALC_MMR6 */	----
18692	GPR32Opnd, brtarget_mm,	----
18693	/* BEQZC */	----
18694	GPR32Opnd, brtarget21,	----
18695	/* BEQZC16_MMR6 */	----
18696	GPRMM16Opnd, brtarget7_mm,	----
18697	/* BEQZC64 */	----
18698	GPR64Opnd, brtarget21,	----
18699	/* BEQZC_MM */	----
18700	GPR32Opnd, brtarget_mm,	----
18701	/* BEQZC_MMR6 */	----
18702	GPR32Opnd, brtarget21_mm,	----
18703	/* BEQ_MM */	----
18704	GPR32Opnd, GPR32Opnd, brtarget_mm,	----
18705	/* BGEC */	----
18706	GPR32Opnd, GPR32Opnd, brtarget,	----
18707	/* BGEC64 */	----
18708	GPR64Opnd, GPR64Opnd, brtarget,	----
18709	/* BGEC_MMR6 */	----
18710	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18711	/* BGEUC */	----
18712	GPR32Opnd, GPR32Opnd, brtarget,	----
18713	/* BGEUC64 */	----
18714	GPR64Opnd, GPR64Opnd, brtarget,	----
18715	/* BGEUC_MMR6 */	----
18716	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18717	/* BGEZ */	----
18718	GPR32Opnd, brtarget,	----
18719	/* BGEZ64 */	----
18720	GPR64Opnd, brtarget,	----
18721	/* BGEZAL */	----
18722	GPR32Opnd, brtarget,	----
18723	/* BGEZALC */	----
18724	GPR32Opnd, brtarget,	----
18725	/* BGEZALC_MMR6 */	----
18726	GPR32Opnd, brtarget_mm,	----
18727	/* BGEZALL */	----
18728	GPR32Opnd, brtarget,	----
18729	/* BGEZALS_MM */	----
18730	GPR32Opnd, brtarget_mm,	----
18731	/* BGEZAL_MM */	----
18732	GPR32Opnd, brtarget_mm,	----
18733	/* BGEZC */	----
18734	GPR32Opnd, brtarget,	----
18735	/* BGEZC64 */	----
18736	GPR64Opnd, brtarget,	----
18737	/* BGEZC_MMR6 */	----
18738	GPR32Opnd, brtarget_lsl2_mm,	----
18739	/* BGEZL */	----
18740	GPR32Opnd, brtarget,	----
18741	/* BGEZ_MM */	----
18742	GPR32Opnd, brtarget_mm,	----
18743	/* BGTZ */	----
18744	GPR32Opnd, brtarget,	----
18745	/* BGTZ64 */	----
18746	GPR64Opnd, brtarget,	----
18747	/* BGTZALC */	----
18748	GPR32Opnd, brtarget,	----
18749	/* BGTZALC_MMR6 */	----
18750	GPR32Opnd, brtarget_mm,	----
18751	/* BGTZC */	----
18752	GPR32Opnd, brtarget,	----
18753	/* BGTZC64 */	----
18754	GPR64Opnd, brtarget,	----
18755	/* BGTZC_MMR6 */	----
18756	GPR32Opnd, brtarget_lsl2_mm,	----
18757	/* BGTZL */	----
18758	GPR32Opnd, brtarget,	----
18759	/* BGTZ_MM */	----
18760	GPR32Opnd, brtarget_mm,	----
18761	/* BINSLI_B */	----
18762	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
18763	/* BINSLI_D */	----
18764	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
18765	/* BINSLI_H */	----
18766	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
18767	/* BINSLI_W */	----
18768	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18769	/* BINSL_B */	----
18770	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18771	/* BINSL_D */	----
18772	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18773	/* BINSL_H */	----
18774	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18775	/* BINSL_W */	----
18776	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18777	/* BINSRI_B */	----
18778	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
18779	/* BINSRI_D */	----
18780	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
18781	/* BINSRI_H */	----
18782	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
18783	/* BINSRI_W */	----
18784	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18785	/* BINSR_B */	----
18786	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18787	/* BINSR_D */	----
18788	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18789	/* BINSR_H */	----
18790	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18791	/* BINSR_W */	----
18792	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18793	/* BITREV */	----
18794	GPR32Opnd, GPR32Opnd,	----
18795	/* BITREV_MM */	----
18796	GPR32Opnd, GPR32Opnd,	----
18797	/* BITSWAP */	----
18798	GPR32Opnd, GPR32Opnd,	----
18799	/* BITSWAP_MMR6 */	----
18800	GPR32Opnd, GPR32Opnd,	----
18801	/* BLEZ */	----
18802	GPR32Opnd, brtarget,	----
18803	/* BLEZ64 */	----
18804	GPR64Opnd, brtarget,	----
18805	/* BLEZALC */	----
18806	GPR32Opnd, brtarget,	----
18807	/* BLEZALC_MMR6 */	----
18808	GPR32Opnd, brtarget_mm,	----
18809	/* BLEZC */	----
18810	GPR32Opnd, brtarget,	----
18811	/* BLEZC64 */	----
18812	GPR64Opnd, brtarget,	----
18813	/* BLEZC_MMR6 */	----
18814	GPR32Opnd, brtarget_lsl2_mm,	----
18815	/* BLEZL */	----
18816	GPR32Opnd, brtarget,	----
18817	/* BLEZ_MM */	----
18818	GPR32Opnd, brtarget_mm,	----
18819	/* BLTC */	----
18820	GPR32Opnd, GPR32Opnd, brtarget,	----
18821	/* BLTC64 */	----
18822	GPR64Opnd, GPR64Opnd, brtarget,	----
18823	/* BLTC_MMR6 */	----
18824	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18825	/* BLTUC */	----
18826	GPR32Opnd, GPR32Opnd, brtarget,	----
18827	/* BLTUC64 */	----
18828	GPR64Opnd, GPR64Opnd, brtarget,	----
18829	/* BLTUC_MMR6 */	----
18830	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18831	/* BLTZ */	----
18832	GPR32Opnd, brtarget,	----
18833	/* BLTZ64 */	----
18834	GPR64Opnd, brtarget,	----
18835	/* BLTZAL */	----
18836	GPR32Opnd, brtarget,	----
18837	/* BLTZALC */	----
18838	GPR32Opnd, brtarget,	----
18839	/* BLTZALC_MMR6 */	----
18840	GPR32Opnd, brtarget_mm,	----
18841	/* BLTZALL */	----
18842	GPR32Opnd, brtarget,	----
18843	/* BLTZALS_MM */	----
18844	GPR32Opnd, brtarget_mm,	----
18845	/* BLTZAL_MM */	----
18846	GPR32Opnd, brtarget_mm,	----
18847	/* BLTZC */	----
18848	GPR32Opnd, brtarget,	----
18849	/* BLTZC64 */	----
18850	GPR64Opnd, brtarget,	----
18851	/* BLTZC_MMR6 */	----
18852	GPR32Opnd, brtarget_lsl2_mm,	----
18853	/* BLTZL */	----
18854	GPR32Opnd, brtarget,	----
18855	/* BLTZ_MM */	----
18856	GPR32Opnd, brtarget_mm,	----
18857	/* BMNZI_B */	----
18858	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
18859	/* BMNZ_V */	----
18860	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18861	/* BMZI_B */	----
18862	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
18863	/* BMZ_V */	----
18864	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18865	/* BNE */	----
18866	GPR32Opnd, GPR32Opnd, brtarget,	----
18867	/* BNE64 */	----
18868	GPR64Opnd, GPR64Opnd, brtarget,	----
18869	/* BNEC */	----
18870	GPR32Opnd, GPR32Opnd, brtarget,	----
18871	/* BNEC64 */	----
18872	GPR64Opnd, GPR64Opnd, brtarget,	----
18873	/* BNEC_MMR6 */	----
18874	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	----
18875	/* BNEGI_B */	----
18876	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
18877	/* BNEGI_D */	----
18878	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
18879	/* BNEGI_H */	----
18880	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
18881	/* BNEGI_W */	----
18882	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18883	/* BNEG_B */	----
18884	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18885	/* BNEG_D */	----
18886	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18887	/* BNEG_H */	----
18888	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18889	/* BNEG_W */	----
18890	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18891	/* BNEL */	----
18892	GPR32Opnd, GPR32Opnd, brtarget,	----
18893	/* BNEZ16_MM */	----
18894	GPRMM16Opnd, brtarget7_mm,	----
18895	/* BNEZALC */	----
18896	GPR32Opnd, brtarget,	----
18897	/* BNEZALC_MMR6 */	----
18898	GPR32Opnd, brtarget_mm,	----
18899	/* BNEZC */	----
18900	GPR32Opnd, brtarget21,	----
18901	/* BNEZC16_MMR6 */	----
18902	GPRMM16Opnd, brtarget7_mm,	----
18903	/* BNEZC64 */	----
18904	GPR64Opnd, brtarget21,	----
18905	/* BNEZC_MM */	----
18906	GPR32Opnd, brtarget_mm,	----
18907	/* BNEZC_MMR6 */	----
18908	GPR32Opnd, brtarget21_mm,	----
18909	/* BNE_MM */	----
18910	GPR32Opnd, GPR32Opnd, brtarget_mm,	----
18911	/* BNVC */	----
18912	GPR32Opnd, GPR32Opnd, brtarget,	----
18913	/* BNVC_MMR6 */	----
18914	GPR32Opnd, GPR32Opnd, brtargetr6,	----
18915	/* BNZ_B */	----
18916	MSA128BOpnd, brtarget,	----
18917	/* BNZ_D */	----
18918	MSA128DOpnd, brtarget,	----
18919	/* BNZ_H */	----
18920	MSA128HOpnd, brtarget,	----
18921	/* BNZ_V */	----
18922	MSA128BOpnd, brtarget,	----
18923	/* BNZ_W */	----
18924	MSA128WOpnd, brtarget,	----
18925	/* BOVC */	----
18926	GPR32Opnd, GPR32Opnd, brtarget,	----
18927	/* BOVC_MMR6 */	----
18928	GPR32Opnd, GPR32Opnd, brtargetr6,	----
18929	/* BPOSGE32 */	----
18930	brtarget,	----
18931	/* BPOSGE32C_MMR3 */	----
18932	brtarget1SImm16,	----
18933	/* BPOSGE32_MM */	----
18934	brtarget_mm,	----
18935	/* BREAK */	----
18936	uimm10, uimm10,	----
18937	/* BREAK16_MM */	----
18938	uimm4,	----
18939	/* BREAK16_MMR6 */	----
18940	uimm4,	----
18941	/* BREAK_MM */	----
18942	uimm10, uimm10,	----
18943	/* BREAK_MMR6 */	----
18944	uimm10, uimm10,	----
18945	/* BSELI_B */	----
18946	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
18947	/* BSEL_V */	----
18948	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18949	/* BSETI_B */	----
18950	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
18951	/* BSETI_D */	----
18952	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
18953	/* BSETI_H */	----
18954	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
18955	/* BSETI_W */	----
18956	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
18957	/* BSET_B */	----
18958	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
18959	/* BSET_D */	----
18960	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
18961	/* BSET_H */	----
18962	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
18963	/* BSET_W */	----
18964	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
18965	/* BZ_B */	----
18966	MSA128BOpnd, brtarget,	----
18967	/* BZ_D */	----
18968	MSA128DOpnd, brtarget,	----
18969	/* BZ_H */	----
18970	MSA128HOpnd, brtarget,	----
18971	/* BZ_V */	----
18972	MSA128BOpnd, brtarget,	----
18973	/* BZ_W */	----
18974	MSA128WOpnd, brtarget,	----
18975	/* BeqzRxImm16 */	----
18976	CPU16Regs, brtarget,	----
18977	/* BeqzRxImmX16 */	----
18978	CPU16Regs, brtarget,	----
18979	/* Bimm16 */	----
18980	brtarget,	----
18981	/* BimmX16 */	----
18982	brtarget,	----
18983	/* BnezRxImm16 */	----
18984	CPU16Regs, brtarget,	----
18985	/* BnezRxImmX16 */	----
18986	CPU16Regs, brtarget,	----
18987	/* Break16 */	----
18988	/* Bteqz16 */	----
18989	simm16,	----
18990	/* BteqzX16 */	----
18991	simm16,	----
18992	/* Btnez16 */	----
18993	simm16,	----
18994	/* BtnezX16 */	----
18995	simm16,	----
18996	/* CACHE */	----
18997	-1, simm16, uimm5,	----
18998	/* CACHEE */	----
18999	-1, simm9, uimm5,	----
19000	/* CACHEE_MM */	----
19001	-1, simm9, uimm5,	----
19002	/* CACHE_MM */	----
19003	-1, simm12, uimm5,	----
19004	/* CACHE_MMR6 */	----
19005	-1, simm12, uimm5,	----
19006	/* CACHE_R6 */	----
19007	-1, simm9, uimm5,	----
19008	/* CEIL_L_D64 */	----
19009	FGR64Opnd, FGR64Opnd,	----
19010	/* CEIL_L_D_MMR6 */	----
19011	FGR64Opnd, FGR64Opnd,	----
19012	/* CEIL_L_S */	----
19013	FGR64Opnd, FGR32Opnd,	----
19014	/* CEIL_L_S_MMR6 */	----
19015	FGR64Opnd, FGR32Opnd,	----
19016	/* CEIL_W_D32 */	----
19017	FGR32Opnd, AFGR64Opnd,	----
19018	/* CEIL_W_D64 */	----
19019	FGR32Opnd, FGR64Opnd,	----
19020	/* CEIL_W_D_MMR6 */	----
19021	FGR32Opnd, AFGR64Opnd,	----
19022	/* CEIL_W_MM */	----
19023	FGR32Opnd, AFGR64Opnd,	----
19024	/* CEIL_W_S */	----
19025	FGR32Opnd, FGR32Opnd,	----
19026	/* CEIL_W_S_MM */	----
19027	FGR32Opnd, FGR32Opnd,	----
19028	/* CEIL_W_S_MMR6 */	----
19029	FGR32Opnd, FGR32Opnd,	----
19030	/* CEQI_B */	----
19031	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	----
19032	/* CEQI_D */	----
19033	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	----
19034	/* CEQI_H */	----
19035	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	----
19036	/* CEQI_W */	----
19037	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	----
19038	/* CEQ_B */	----
19039	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19040	/* CEQ_D */	----
19041	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19042	/* CEQ_H */	----
19043	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19044	/* CEQ_W */	----
19045	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19046	/* CFC1 */	----
19047	GPR32Opnd, CCROpnd,	----
19048	/* CFC1_MM */	----
19049	GPR32Opnd, CCROpnd,	----
19050	/* CFC2_MM */	----
19051	GPR32Opnd, COP2Opnd,	----
19052	/* CFCMSA */	----
19053	GPR32Opnd, MSA128CROpnd,	----
19054	/* CINS */	----
19055	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	----
19056	/* CINS32 */	----
19057	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	----
19058	/* CINS64_32 */	----
19059	GPR64Opnd, GPR32Opnd, uimm5, uimm5,	----
19060	/* CINS_i32 */	----
19061	GPR32Opnd, GPR32Opnd, uimm5, uimm5,	----
19062	/* CLASS_D */	----
19063	FGR64Opnd, FGR64Opnd,	----
19064	/* CLASS_D_MMR6 */	----
19065	FGR64Opnd, FGR64Opnd,	----
19066	/* CLASS_S */	----
19067	FGR32Opnd, FGR32Opnd,	----
19068	/* CLASS_S_MMR6 */	----
19069	FGR32Opnd, FGR32Opnd,	----
19070	/* CLEI_S_B */	----
19071	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	----
19072	/* CLEI_S_D */	----
19073	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	----
19074	/* CLEI_S_H */	----
19075	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	----
19076	/* CLEI_S_W */	----
19077	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	----
19078	/* CLEI_U_B */	----
19079	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
19080	/* CLEI_U_D */	----
19081	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
19082	/* CLEI_U_H */	----
19083	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
19084	/* CLEI_U_W */	----
19085	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
19086	/* CLE_S_B */	----
19087	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19088	/* CLE_S_D */	----
19089	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19090	/* CLE_S_H */	----
19091	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19092	/* CLE_S_W */	----
19093	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19094	/* CLE_U_B */	----
19095	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19096	/* CLE_U_D */	----
19097	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19098	/* CLE_U_H */	----
19099	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19100	/* CLE_U_W */	----
19101	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19102	/* CLO */	----
19103	GPR32Opnd, GPR32Opnd,	----
19104	/* CLO_MM */	----
19105	GPR32Opnd, GPR32Opnd,	----
19106	/* CLO_MMR6 */	----
19107	GPR32Opnd, GPR32Opnd,	----
19108	/* CLO_R6 */	----
19109	GPR32Opnd, GPR32Opnd,	----
19110	/* CLTI_S_B */	----
19111	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	----
19112	/* CLTI_S_D */	----
19113	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	----
19114	/* CLTI_S_H */	----
19115	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	----
19116	/* CLTI_S_W */	----
19117	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	----
19118	/* CLTI_U_B */	----
19119	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
19120	/* CLTI_U_D */	----
19121	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
19122	/* CLTI_U_H */	----
19123	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
19124	/* CLTI_U_W */	----
19125	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
19126	/* CLT_S_B */	----
19127	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19128	/* CLT_S_D */	----
19129	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19130	/* CLT_S_H */	----
19131	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19132	/* CLT_S_W */	----
19133	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19134	/* CLT_U_B */	----
19135	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19136	/* CLT_U_D */	----
19137	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19138	/* CLT_U_H */	----
19139	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19140	/* CLT_U_W */	----
19141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19142	/* CLZ */	----
19143	GPR32Opnd, GPR32Opnd,	----
19144	/* CLZ_MM */	----
19145	GPR32Opnd, GPR32Opnd,	----
19146	/* CLZ_MMR6 */	----
19147	GPR32Opnd, GPR32Opnd,	----
19148	/* CLZ_R6 */	----
19149	GPR32Opnd, GPR32Opnd,	----
19150	/* CMPGDU_EQ_QB */	----
19151	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19152	/* CMPGDU_EQ_QB_MMR2 */	----
19153	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19154	/* CMPGDU_LE_QB */	----
19155	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19156	/* CMPGDU_LE_QB_MMR2 */	----
19157	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19158	/* CMPGDU_LT_QB */	----
19159	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19160	/* CMPGDU_LT_QB_MMR2 */	----
19161	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19162	/* CMPGU_EQ_QB */	----
19163	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19164	/* CMPGU_EQ_QB_MM */	----
19165	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19166	/* CMPGU_LE_QB */	----
19167	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19168	/* CMPGU_LE_QB_MM */	----
19169	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19170	/* CMPGU_LT_QB */	----
19171	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19172	/* CMPGU_LT_QB_MM */	----
19173	GPR32Opnd, DSPROpnd, DSPROpnd,	----
19174	/* CMPU_EQ_QB */	----
19175	DSPROpnd, DSPROpnd,	----
19176	/* CMPU_EQ_QB_MM */	----
19177	DSPROpnd, DSPROpnd,	----
19178	/* CMPU_LE_QB */	----
19179	DSPROpnd, DSPROpnd,	----
19180	/* CMPU_LE_QB_MM */	----
19181	DSPROpnd, DSPROpnd,	----
19182	/* CMPU_LT_QB */	----
19183	DSPROpnd, DSPROpnd,	----
19184	/* CMPU_LT_QB_MM */	----
19185	DSPROpnd, DSPROpnd,	----
19186	/* CMP_AF_D_MMR6 */	----
19187	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19188	/* CMP_AF_S_MMR6 */	----
19189	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19190	/* CMP_EQ_D */	----
19191	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19192	/* CMP_EQ_D_MMR6 */	----
19193	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19194	/* CMP_EQ_PH */	----
19195	DSPROpnd, DSPROpnd,	----
19196	/* CMP_EQ_PH_MM */	----
19197	DSPROpnd, DSPROpnd,	----
19198	/* CMP_EQ_S */	----
19199	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19200	/* CMP_EQ_S_MMR6 */	----
19201	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19202	/* CMP_F_D */	----
19203	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19204	/* CMP_F_S */	----
19205	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19206	/* CMP_LE_D */	----
19207	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19208	/* CMP_LE_D_MMR6 */	----
19209	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19210	/* CMP_LE_PH */	----
19211	DSPROpnd, DSPROpnd,	----
19212	/* CMP_LE_PH_MM */	----
19213	DSPROpnd, DSPROpnd,	----
19214	/* CMP_LE_S */	----
19215	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19216	/* CMP_LE_S_MMR6 */	----
19217	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19218	/* CMP_LT_D */	----
19219	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19220	/* CMP_LT_D_MMR6 */	----
19221	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19222	/* CMP_LT_PH */	----
19223	DSPROpnd, DSPROpnd,	----
19224	/* CMP_LT_PH_MM */	----
19225	DSPROpnd, DSPROpnd,	----
19226	/* CMP_LT_S */	----
19227	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19228	/* CMP_LT_S_MMR6 */	----
19229	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19230	/* CMP_SAF_D */	----
19231	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19232	/* CMP_SAF_D_MMR6 */	----
19233	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19234	/* CMP_SAF_S */	----
19235	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19236	/* CMP_SAF_S_MMR6 */	----
19237	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19238	/* CMP_SEQ_D */	----
19239	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19240	/* CMP_SEQ_D_MMR6 */	----
19241	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19242	/* CMP_SEQ_S */	----
19243	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19244	/* CMP_SEQ_S_MMR6 */	----
19245	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19246	/* CMP_SLE_D */	----
19247	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19248	/* CMP_SLE_D_MMR6 */	----
19249	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19250	/* CMP_SLE_S */	----
19251	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19252	/* CMP_SLE_S_MMR6 */	----
19253	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19254	/* CMP_SLT_D */	----
19255	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19256	/* CMP_SLT_D_MMR6 */	----
19257	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19258	/* CMP_SLT_S */	----
19259	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19260	/* CMP_SLT_S_MMR6 */	----
19261	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19262	/* CMP_SUEQ_D */	----
19263	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19264	/* CMP_SUEQ_D_MMR6 */	----
19265	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19266	/* CMP_SUEQ_S */	----
19267	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19268	/* CMP_SUEQ_S_MMR6 */	----
19269	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19270	/* CMP_SULE_D */	----
19271	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19272	/* CMP_SULE_D_MMR6 */	----
19273	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19274	/* CMP_SULE_S */	----
19275	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19276	/* CMP_SULE_S_MMR6 */	----
19277	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19278	/* CMP_SULT_D */	----
19279	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19280	/* CMP_SULT_D_MMR6 */	----
19281	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19282	/* CMP_SULT_S */	----
19283	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19284	/* CMP_SULT_S_MMR6 */	----
19285	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19286	/* CMP_SUN_D */	----
19287	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19288	/* CMP_SUN_D_MMR6 */	----
19289	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19290	/* CMP_SUN_S */	----
19291	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19292	/* CMP_SUN_S_MMR6 */	----
19293	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19294	/* CMP_UEQ_D */	----
19295	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19296	/* CMP_UEQ_D_MMR6 */	----
19297	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19298	/* CMP_UEQ_S */	----
19299	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19300	/* CMP_UEQ_S_MMR6 */	----
19301	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19302	/* CMP_ULE_D */	----
19303	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19304	/* CMP_ULE_D_MMR6 */	----
19305	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19306	/* CMP_ULE_S */	----
19307	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19308	/* CMP_ULE_S_MMR6 */	----
19309	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19310	/* CMP_ULT_D */	----
19311	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19312	/* CMP_ULT_D_MMR6 */	----
19313	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19314	/* CMP_ULT_S */	----
19315	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19316	/* CMP_ULT_S_MMR6 */	----
19317	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19318	/* CMP_UN_D */	----
19319	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19320	/* CMP_UN_D_MMR6 */	----
19321	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	----
19322	/* CMP_UN_S */	----
19323	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19324	/* CMP_UN_S_MMR6 */	----
19325	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
19326	/* COPY_S_B */	----
19327	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	----
19328	/* COPY_S_D */	----
19329	GPR64Opnd, MSA128DOpnd, uimm1_ptr,	----
19330	/* COPY_S_H */	----
19331	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	----
19332	/* COPY_S_W */	----
19333	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	----
19334	/* COPY_U_B */	----
19335	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	----
19336	/* COPY_U_H */	----
19337	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	----
19338	/* COPY_U_W */	----
19339	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	----
19340	/* CRC32B */	----
19341	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19342	/* CRC32CB */	----
19343	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19344	/* CRC32CD */	----
19345	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19346	/* CRC32CH */	----
19347	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19348	/* CRC32CW */	----
19349	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19350	/* CRC32D */	----
19351	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19352	/* CRC32H */	----
19353	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19354	/* CRC32W */	----
19355	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19356	/* CTC1 */	----
19357	CCROpnd, GPR32Opnd,	----
19358	/* CTC1_MM */	----
19359	CCROpnd, GPR32Opnd,	----
19360	/* CTC2_MM */	----
19361	COP2Opnd, GPR32Opnd,	----
19362	/* CTCMSA */	----
19363	MSA128CROpnd, GPR32Opnd,	----
19364	/* CVT_D32_S */	----
19365	AFGR64Opnd, FGR32Opnd,	----
19366	/* CVT_D32_S_MM */	----
19367	AFGR64Opnd, FGR32Opnd,	----
19368	/* CVT_D32_W */	----
19369	AFGR64Opnd, FGR32Opnd,	----
19370	/* CVT_D32_W_MM */	----
19371	AFGR64Opnd, FGR32Opnd,	----
19372	/* CVT_D64_L */	----
19373	FGR64Opnd, FGR64Opnd,	----
19374	/* CVT_D64_S */	----
19375	FGR64Opnd, FGR32Opnd,	----
19376	/* CVT_D64_S_MM */	----
19377	FGR64Opnd, FGR32Opnd,	----
19378	/* CVT_D64_W */	----
19379	FGR64Opnd, FGR32Opnd,	----
19380	/* CVT_D64_W_MM */	----
19381	FGR64Opnd, FGR32Opnd,	----
19382	/* CVT_D_L_MMR6 */	----
19383	FGR64Opnd, FGR64Opnd,	----
19384	/* CVT_L_D64 */	----
19385	FGR64Opnd, FGR64Opnd,	----
19386	/* CVT_L_D64_MM */	----
19387	FGR64Opnd, FGR64Opnd,	----
19388	/* CVT_L_D_MMR6 */	----
19389	FGR64Opnd, FGR64Opnd,	----
19390	/* CVT_L_S */	----
19391	FGR64Opnd, FGR32Opnd,	----
19392	/* CVT_L_S_MM */	----
19393	FGR64Opnd, FGR32Opnd,	----
19394	/* CVT_L_S_MMR6 */	----
19395	FGR64Opnd, FGR32Opnd,	----
19396	/* CVT_PS_PW64 */	----
19397	FGR64Opnd, FGR64Opnd,	----
19398	/* CVT_PS_S64 */	----
19399	FGR64Opnd, FGR32Opnd, FGR32Opnd,	----
19400	/* CVT_PW_PS64 */	----
19401	FGR64Opnd, FGR64Opnd,	----
19402	/* CVT_S_D32 */	----
19403	FGR32Opnd, AFGR64Opnd,	----
19404	/* CVT_S_D32_MM */	----
19405	FGR32Opnd, AFGR64Opnd,	----
19406	/* CVT_S_D64 */	----
19407	FGR32Opnd, FGR64Opnd,	----
19408	/* CVT_S_D64_MM */	----
19409	FGR32Opnd, FGR64Opnd,	----
19410	/* CVT_S_L */	----
19411	FGR32Opnd, FGR64Opnd,	----
19412	/* CVT_S_L_MMR6 */	----
19413	FGR64Opnd, FGR32Opnd,	----
19414	/* CVT_S_PL64 */	----
19415	FGR32Opnd, FGR64Opnd,	----
19416	/* CVT_S_PU64 */	----
19417	FGR32Opnd, FGR64Opnd,	----
19418	/* CVT_S_W */	----
19419	FGR32Opnd, FGR32Opnd,	----
19420	/* CVT_S_W_MM */	----
19421	FGR32Opnd, FGR32Opnd,	----
19422	/* CVT_S_W_MMR6 */	----
19423	FGR32Opnd, FGR32Opnd,	----
19424	/* CVT_W_D32 */	----
19425	FGR32Opnd, AFGR64Opnd,	----
19426	/* CVT_W_D32_MM */	----
19427	FGR32Opnd, AFGR64Opnd,	----
19428	/* CVT_W_D64 */	----
19429	FGR32Opnd, FGR64Opnd,	----
19430	/* CVT_W_D64_MM */	----
19431	FGR32Opnd, FGR64Opnd,	----
19432	/* CVT_W_S */	----
19433	FGR32Opnd, FGR32Opnd,	----
19434	/* CVT_W_S_MM */	----
19435	FGR32Opnd, FGR32Opnd,	----
19436	/* CVT_W_S_MMR6 */	----
19437	FGR32Opnd, FGR32Opnd,	----
19438	/* C_EQ_D32 */	----
19439	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19440	/* C_EQ_D32_MM */	----
19441	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19442	/* C_EQ_D64 */	----
19443	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19444	/* C_EQ_D64_MM */	----
19445	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19446	/* C_EQ_S */	----
19447	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19448	/* C_EQ_S_MM */	----
19449	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19450	/* C_F_D32 */	----
19451	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19452	/* C_F_D32_MM */	----
19453	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19454	/* C_F_D64 */	----
19455	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19456	/* C_F_D64_MM */	----
19457	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19458	/* C_F_S */	----
19459	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19460	/* C_F_S_MM */	----
19461	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19462	/* C_LE_D32 */	----
19463	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19464	/* C_LE_D32_MM */	----
19465	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19466	/* C_LE_D64 */	----
19467	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19468	/* C_LE_D64_MM */	----
19469	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19470	/* C_LE_S */	----
19471	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19472	/* C_LE_S_MM */	----
19473	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19474	/* C_LT_D32 */	----
19475	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19476	/* C_LT_D32_MM */	----
19477	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19478	/* C_LT_D64 */	----
19479	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19480	/* C_LT_D64_MM */	----
19481	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19482	/* C_LT_S */	----
19483	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19484	/* C_LT_S_MM */	----
19485	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19486	/* C_NGE_D32 */	----
19487	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19488	/* C_NGE_D32_MM */	----
19489	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19490	/* C_NGE_D64 */	----
19491	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19492	/* C_NGE_D64_MM */	----
19493	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19494	/* C_NGE_S */	----
19495	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19496	/* C_NGE_S_MM */	----
19497	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19498	/* C_NGLE_D32 */	----
19499	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19500	/* C_NGLE_D32_MM */	----
19501	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19502	/* C_NGLE_D64 */	----
19503	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19504	/* C_NGLE_D64_MM */	----
19505	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19506	/* C_NGLE_S */	----
19507	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19508	/* C_NGLE_S_MM */	----
19509	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19510	/* C_NGL_D32 */	----
19511	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19512	/* C_NGL_D32_MM */	----
19513	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19514	/* C_NGL_D64 */	----
19515	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19516	/* C_NGL_D64_MM */	----
19517	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19518	/* C_NGL_S */	----
19519	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19520	/* C_NGL_S_MM */	----
19521	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19522	/* C_NGT_D32 */	----
19523	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19524	/* C_NGT_D32_MM */	----
19525	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19526	/* C_NGT_D64 */	----
19527	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19528	/* C_NGT_D64_MM */	----
19529	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19530	/* C_NGT_S */	----
19531	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19532	/* C_NGT_S_MM */	----
19533	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19534	/* C_OLE_D32 */	----
19535	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19536	/* C_OLE_D32_MM */	----
19537	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19538	/* C_OLE_D64 */	----
19539	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19540	/* C_OLE_D64_MM */	----
19541	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19542	/* C_OLE_S */	----
19543	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19544	/* C_OLE_S_MM */	----
19545	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19546	/* C_OLT_D32 */	----
19547	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19548	/* C_OLT_D32_MM */	----
19549	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19550	/* C_OLT_D64 */	----
19551	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19552	/* C_OLT_D64_MM */	----
19553	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19554	/* C_OLT_S */	----
19555	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19556	/* C_OLT_S_MM */	----
19557	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19558	/* C_SEQ_D32 */	----
19559	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19560	/* C_SEQ_D32_MM */	----
19561	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19562	/* C_SEQ_D64 */	----
19563	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19564	/* C_SEQ_D64_MM */	----
19565	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19566	/* C_SEQ_S */	----
19567	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19568	/* C_SEQ_S_MM */	----
19569	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19570	/* C_SF_D32 */	----
19571	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19572	/* C_SF_D32_MM */	----
19573	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19574	/* C_SF_D64 */	----
19575	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19576	/* C_SF_D64_MM */	----
19577	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19578	/* C_SF_S */	----
19579	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19580	/* C_SF_S_MM */	----
19581	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19582	/* C_UEQ_D32 */	----
19583	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19584	/* C_UEQ_D32_MM */	----
19585	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19586	/* C_UEQ_D64 */	----
19587	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19588	/* C_UEQ_D64_MM */	----
19589	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19590	/* C_UEQ_S */	----
19591	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19592	/* C_UEQ_S_MM */	----
19593	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19594	/* C_ULE_D32 */	----
19595	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19596	/* C_ULE_D32_MM */	----
19597	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19598	/* C_ULE_D64 */	----
19599	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19600	/* C_ULE_D64_MM */	----
19601	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19602	/* C_ULE_S */	----
19603	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19604	/* C_ULE_S_MM */	----
19605	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19606	/* C_ULT_D32 */	----
19607	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19608	/* C_ULT_D32_MM */	----
19609	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19610	/* C_ULT_D64 */	----
19611	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19612	/* C_ULT_D64_MM */	----
19613	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19614	/* C_ULT_S */	----
19615	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19616	/* C_ULT_S_MM */	----
19617	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19618	/* C_UN_D32 */	----
19619	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19620	/* C_UN_D32_MM */	----
19621	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	----
19622	/* C_UN_D64 */	----
19623	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19624	/* C_UN_D64_MM */	----
19625	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	----
19626	/* C_UN_S */	----
19627	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19628	/* C_UN_S_MM */	----
19629	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	----
19630	/* CmpRxRy16 */	----
19631	CPU16Regs, CPU16Regs,	----
19632	/* CmpiRxImm16 */	----
19633	CPU16Regs, simm16,	----
19634	/* CmpiRxImmX16 */	----
19635	CPU16Regs, simm16,	----
19636	/* DADD */	----
19637	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19638	/* DADDi */	----
19639	GPR64Opnd, GPR64Opnd, simm16_64,	----
19640	/* DADDiu */	----
19641	GPR64Opnd, GPR64Opnd, simm16_64,	----
19642	/* DADDu */	----
19643	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19644	/* DAHI */	----
19645	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	----
19646	/* DALIGN */	----
19647	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,	----
19648	/* DATI */	----
19649	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	----
19650	/* DAUI */	----
19651	GPR64Opnd, GPR64Opnd, uimm16,	----
19652	/* DBITSWAP */	----
19653	GPR64Opnd, GPR64Opnd,	----
19654	/* DCLO */	----
19655	GPR64Opnd, GPR64Opnd,	----
19656	/* DCLO_R6 */	----
19657	GPR64Opnd, GPR64Opnd,	----
19658	/* DCLZ */	----
19659	GPR64Opnd, GPR64Opnd,	----
19660	/* DCLZ_R6 */	----
19661	GPR64Opnd, GPR64Opnd,	----
19662	/* DDIV */	----
19663	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19664	/* DDIVU */	----
19665	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19666	/* DERET */	----
19667	/* DERET_MM */	----
19668	/* DERET_MMR6 */	----
19669	/* DEXT */	----
19670	GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,	----
19671	/* DEXT64_32 */	----
19672	GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,	----
19673	/* DEXTM */	----
19674	GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,	----
19675	/* DEXTU */	----
19676	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,	----
19677	/* DI */	----
19678	GPR32Opnd,	----
19679	/* DINS */	----
19680	GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,	----
19681	/* DINSM */	----
19682	GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,	----
19683	/* DINSU */	----
19684	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,	----
19685	/* DIV */	----
19686	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19687	/* DIVU */	----
19688	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19689	/* DIVU_MMR6 */	----
19690	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19691	/* DIV_MMR6 */	----
19692	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
19693	/* DIV_S_B */	----
19694	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19695	/* DIV_S_D */	----
19696	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19697	/* DIV_S_H */	----
19698	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19699	/* DIV_S_W */	----
19700	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19701	/* DIV_U_B */	----
19702	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
19703	/* DIV_U_D */	----
19704	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
19705	/* DIV_U_H */	----
19706	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
19707	/* DIV_U_W */	----
19708	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
19709	/* DI_MM */	----
19710	GPR32Opnd,	----
19711	/* DI_MMR6 */	----
19712	GPR32Opnd,	----
19713	/* DLSA */	----
19714	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	----
19715	/* DLSA_R6 */	----
19716	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	----
19717	/* DMFC0 */	----
19718	GPR64Opnd, COP0Opnd, uimm3,	----
19719	/* DMFC1 */	----
19720	GPR64Opnd, FGR64Opnd,	----
19721	/* DMFC2 */	----
19722	GPR64Opnd, COP2Opnd, uimm3,	----
19723	/* DMFC2_OCTEON */	----
19724	GPR64Opnd, uimm16,	----
19725	/* DMFGC0 */	----
19726	GPR64Opnd, COP0Opnd, uimm3,	----
19727	/* DMOD */	----
19728	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19729	/* DMODU */	----
19730	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19731	/* DMT */	----
19732	GPR32Opnd,	----
19733	/* DMTC0 */	----
19734	COP0Opnd, GPR64Opnd, uimm3,	----
19735	/* DMTC1 */	----
19736	FGR64Opnd, GPR64Opnd,	----
19737	/* DMTC2 */	----
19738	COP2Opnd, GPR64Opnd, uimm3,	----
19739	/* DMTC2_OCTEON */	----
19740	GPR64Opnd, uimm16,	----
19741	/* DMTGC0 */	----
19742	COP0Opnd, GPR64Opnd, uimm3,	----
19743	/* DMUH */	----
19744	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19745	/* DMUHU */	----
19746	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19747	/* DMUL */	----
19748	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19749	/* DMULT */	----
19750	GPR64Opnd, GPR64Opnd,	----
19751	/* DMULTu */	----
19752	GPR64Opnd, GPR64Opnd,	----
19753	/* DMULU */	----
19754	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19755	/* DMUL_R6 */	----
19756	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19757	/* DOTP_S_D */	----
19758	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19759	/* DOTP_S_H */	----
19760	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19761	/* DOTP_S_W */	----
19762	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19763	/* DOTP_U_D */	----
19764	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19765	/* DOTP_U_H */	----
19766	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19767	/* DOTP_U_W */	----
19768	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19769	/* DPADD_S_D */	----
19770	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19771	/* DPADD_S_H */	----
19772	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19773	/* DPADD_S_W */	----
19774	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19775	/* DPADD_U_D */	----
19776	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19777	/* DPADD_U_H */	----
19778	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19779	/* DPADD_U_W */	----
19780	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19781	/* DPAQX_SA_W_PH */	----
19782	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19783	/* DPAQX_SA_W_PH_MMR2 */	----
19784	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19785	/* DPAQX_S_W_PH */	----
19786	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19787	/* DPAQX_S_W_PH_MMR2 */	----
19788	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19789	/* DPAQ_SA_L_W */	----
19790	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19791	/* DPAQ_SA_L_W_MM */	----
19792	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19793	/* DPAQ_S_W_PH */	----
19794	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19795	/* DPAQ_S_W_PH_MM */	----
19796	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19797	/* DPAU_H_QBL */	----
19798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19799	/* DPAU_H_QBL_MM */	----
19800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19801	/* DPAU_H_QBR */	----
19802	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19803	/* DPAU_H_QBR_MM */	----
19804	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19805	/* DPAX_W_PH */	----
19806	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19807	/* DPAX_W_PH_MMR2 */	----
19808	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19809	/* DPA_W_PH */	----
19810	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19811	/* DPA_W_PH_MMR2 */	----
19812	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19813	/* DPOP */	----
19814	GPR64Opnd, GPR64Opnd,	----
19815	/* DPSQX_SA_W_PH */	----
19816	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19817	/* DPSQX_SA_W_PH_MMR2 */	----
19818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19819	/* DPSQX_S_W_PH */	----
19820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19821	/* DPSQX_S_W_PH_MMR2 */	----
19822	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19823	/* DPSQ_SA_L_W */	----
19824	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19825	/* DPSQ_SA_L_W_MM */	----
19826	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19827	/* DPSQ_S_W_PH */	----
19828	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19829	/* DPSQ_S_W_PH_MM */	----
19830	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19831	/* DPSUB_S_D */	----
19832	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19833	/* DPSUB_S_H */	----
19834	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19835	/* DPSUB_S_W */	----
19836	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19837	/* DPSUB_U_D */	----
19838	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
19839	/* DPSUB_U_H */	----
19840	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
19841	/* DPSUB_U_W */	----
19842	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
19843	/* DPSU_H_QBL */	----
19844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19845	/* DPSU_H_QBL_MM */	----
19846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19847	/* DPSU_H_QBR */	----
19848	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19849	/* DPSU_H_QBR_MM */	----
19850	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19851	/* DPSX_W_PH */	----
19852	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19853	/* DPSX_W_PH_MMR2 */	----
19854	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19855	/* DPS_W_PH */	----
19856	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19857	/* DPS_W_PH_MMR2 */	----
19858	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
19859	/* DROTR */	----
19860	GPR64Opnd, GPR64Opnd, uimm6,	----
19861	/* DROTR32 */	----
19862	GPR64Opnd, GPR64Opnd, uimm5,	----
19863	/* DROTRV */	----
19864	GPR64Opnd, GPR64Opnd, GPR32Opnd,	----
19865	/* DSBH */	----
19866	GPR64Opnd, GPR64Opnd,	----
19867	/* DSDIV */	----
19868	GPR64Opnd, GPR64Opnd,	----
19869	/* DSHD */	----
19870	GPR64Opnd, GPR64Opnd,	----
19871	/* DSLL */	----
19872	GPR64Opnd, GPR64Opnd, uimm6,	----
19873	/* DSLL32 */	----
19874	GPR64Opnd, GPR64Opnd, uimm5,	----
19875	/* DSLL64_32 */	----
19876	GPR64, GPR32,	----
19877	/* DSLLV */	----
19878	GPR64Opnd, GPR64Opnd, GPR32Opnd,	----
19879	/* DSRA */	----
19880	GPR64Opnd, GPR64Opnd, uimm6,	----
19881	/* DSRA32 */	----
19882	GPR64Opnd, GPR64Opnd, uimm5,	----
19883	/* DSRAV */	----
19884	GPR64Opnd, GPR64Opnd, GPR32Opnd,	----
19885	/* DSRL */	----
19886	GPR64Opnd, GPR64Opnd, uimm6,	----
19887	/* DSRL32 */	----
19888	GPR64Opnd, GPR64Opnd, uimm5,	----
19889	/* DSRLV */	----
19890	GPR64Opnd, GPR64Opnd, GPR32Opnd,	----
19891	/* DSUB */	----
19892	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19893	/* DSUBu */	----
19894	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
19895	/* DUDIV */	----
19896	GPR64Opnd, GPR64Opnd,	----
19897	/* DVP */	----
19898	GPR32Opnd,	----
19899	/* DVPE */	----
19900	GPR32Opnd,	----
19901	/* DVP_MMR6 */	----
19902	GPR32Opnd,	----
19903	/* DivRxRy16 */	----
19904	CPU16Regs, CPU16Regs,	----
19905	/* DivuRxRy16 */	----
19906	CPU16Regs, CPU16Regs,	----
19907	/* EHB */	----
19908	/* EHB_MM */	----
19909	/* EHB_MMR6 */	----
19910	/* EI */	----
19911	GPR32Opnd,	----
19912	/* EI_MM */	----
19913	GPR32Opnd,	----
19914	/* EI_MMR6 */	----
19915	GPR32Opnd,	----
19916	/* EMT */	----
19917	GPR32Opnd,	----
19918	/* ERET */	----
19919	/* ERETNC */	----
19920	/* ERETNC_MMR6 */	----
19921	/* ERET_MM */	----
19922	/* ERET_MMR6 */	----
19923	/* EVP */	----
19924	GPR32Opnd,	----
19925	/* EVPE */	----
19926	GPR32Opnd,	----
19927	/* EVP_MMR6 */	----
19928	GPR32Opnd,	----
19929	/* EXT */	----
19930	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	----
19931	/* EXTP */	----
19932	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19933	/* EXTPDP */	----
19934	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19935	/* EXTPDPV */	----
19936	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19937	/* EXTPDPV_MM */	----
19938	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19939	/* EXTPDP_MM */	----
19940	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19941	/* EXTPV */	----
19942	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19943	/* EXTPV_MM */	----
19944	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19945	/* EXTP_MM */	----
19946	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19947	/* EXTRV_RS_W */	----
19948	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19949	/* EXTRV_RS_W_MM */	----
19950	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19951	/* EXTRV_R_W */	----
19952	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19953	/* EXTRV_R_W_MM */	----
19954	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19955	/* EXTRV_S_H */	----
19956	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19957	/* EXTRV_S_H_MM */	----
19958	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19959	/* EXTRV_W */	----
19960	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19961	/* EXTRV_W_MM */	----
19962	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	----
19963	/* EXTR_RS_W */	----
19964	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19965	/* EXTR_RS_W_MM */	----
19966	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19967	/* EXTR_R_W */	----
19968	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19969	/* EXTR_R_W_MM */	----
19970	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19971	/* EXTR_S_H */	----
19972	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19973	/* EXTR_S_H_MM */	----
19974	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19975	/* EXTR_W */	----
19976	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19977	/* EXTR_W_MM */	----
19978	GPR32Opnd, ACC64DSPOpnd, uimm5,	----
19979	/* EXTS */	----
19980	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	----
19981	/* EXTS32 */	----
19982	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	----
19983	/* EXT_MM */	----
19984	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	----
19985	/* EXT_MMR6 */	----
19986	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	----
19987	/* FABS_D32 */	----
19988	AFGR64Opnd, AFGR64Opnd,	----
19989	/* FABS_D32_MM */	----
19990	AFGR64Opnd, AFGR64Opnd,	----
19991	/* FABS_D64 */	----
19992	FGR64Opnd, FGR64Opnd,	----
19993	/* FABS_D64_MM */	----
19994	FGR64Opnd, FGR64Opnd,	----
19995	/* FABS_S */	----
19996	FGR32Opnd, FGR32Opnd,	----
19997	/* FABS_S_MM */	----
19998	FGR32Opnd, FGR32Opnd,	----
19999	/* FADD_D */	----
20000	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20001	/* FADD_D32 */	----
20002	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20003	/* FADD_D32_MM */	----
20004	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20005	/* FADD_D64 */	----
20006	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20007	/* FADD_D64_MM */	----
20008	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20009	/* FADD_PS64 */	----
20010	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20011	/* FADD_S */	----
20012	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20013	/* FADD_S_MM */	----
20014	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20015	/* FADD_S_MMR6 */	----
20016	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20017	/* FADD_W */	----
20018	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20019	/* FCAF_D */	----
20020	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20021	/* FCAF_W */	----
20022	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20023	/* FCEQ_D */	----
20024	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20025	/* FCEQ_W */	----
20026	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20027	/* FCLASS_D */	----
20028	MSA128DOpnd, MSA128DOpnd,	----
20029	/* FCLASS_W */	----
20030	MSA128WOpnd, MSA128WOpnd,	----
20031	/* FCLE_D */	----
20032	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20033	/* FCLE_W */	----
20034	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20035	/* FCLT_D */	----
20036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20037	/* FCLT_W */	----
20038	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20039	/* FCMP_D32 */	----
20040	AFGR64, AFGR64, condcode,	----
20041	/* FCMP_D32_MM */	----
20042	AFGR64, AFGR64, condcode,	----
20043	/* FCMP_D64 */	----
20044	FGR64, FGR64, condcode,	----
20045	/* FCMP_S32 */	----
20046	FGR32, FGR32, condcode,	----
20047	/* FCMP_S32_MM */	----
20048	FGR32, FGR32, condcode,	----
20049	/* FCNE_D */	----
20050	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20051	/* FCNE_W */	----
20052	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20053	/* FCOR_D */	----
20054	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20055	/* FCOR_W */	----
20056	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20057	/* FCUEQ_D */	----
20058	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20059	/* FCUEQ_W */	----
20060	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20061	/* FCULE_D */	----
20062	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20063	/* FCULE_W */	----
20064	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20065	/* FCULT_D */	----
20066	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20067	/* FCULT_W */	----
20068	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20069	/* FCUNE_D */	----
20070	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20071	/* FCUNE_W */	----
20072	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20073	/* FCUN_D */	----
20074	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20075	/* FCUN_W */	----
20076	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20077	/* FDIV_D */	----
20078	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20079	/* FDIV_D32 */	----
20080	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20081	/* FDIV_D32_MM */	----
20082	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20083	/* FDIV_D64 */	----
20084	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20085	/* FDIV_D64_MM */	----
20086	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20087	/* FDIV_S */	----
20088	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20089	/* FDIV_S_MM */	----
20090	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20091	/* FDIV_S_MMR6 */	----
20092	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20093	/* FDIV_W */	----
20094	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20095	/* FEXDO_H */	----
20096	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	----
20097	/* FEXDO_W */	----
20098	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	----
20099	/* FEXP2_D */	----
20100	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20101	/* FEXP2_W */	----
20102	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20103	/* FEXUPL_D */	----
20104	MSA128DOpnd, MSA128WOpnd,	----
20105	/* FEXUPL_W */	----
20106	MSA128WOpnd, MSA128HOpnd,	----
20107	/* FEXUPR_D */	----
20108	MSA128DOpnd, MSA128WOpnd,	----
20109	/* FEXUPR_W */	----
20110	MSA128WOpnd, MSA128HOpnd,	----
20111	/* FFINT_S_D */	----
20112	MSA128DOpnd, MSA128DOpnd,	----
20113	/* FFINT_S_W */	----
20114	MSA128WOpnd, MSA128WOpnd,	----
20115	/* FFINT_U_D */	----
20116	MSA128DOpnd, MSA128DOpnd,	----
20117	/* FFINT_U_W */	----
20118	MSA128WOpnd, MSA128WOpnd,	----
20119	/* FFQL_D */	----
20120	MSA128DOpnd, MSA128WOpnd,	----
20121	/* FFQL_W */	----
20122	MSA128WOpnd, MSA128HOpnd,	----
20123	/* FFQR_D */	----
20124	MSA128DOpnd, MSA128WOpnd,	----
20125	/* FFQR_W */	----
20126	MSA128WOpnd, MSA128HOpnd,	----
20127	/* FILL_B */	----
20128	MSA128BOpnd, GPR32Opnd,	----
20129	/* FILL_D */	----
20130	MSA128DOpnd, GPR64Opnd,	----
20131	/* FILL_H */	----
20132	MSA128HOpnd, GPR32Opnd,	----
20133	/* FILL_W */	----
20134	MSA128WOpnd, GPR32Opnd,	----
20135	/* FLOG2_D */	----
20136	MSA128DOpnd, MSA128DOpnd,	----
20137	/* FLOG2_W */	----
20138	MSA128WOpnd, MSA128WOpnd,	----
20139	/* FLOOR_L_D64 */	----
20140	FGR64Opnd, FGR64Opnd,	----
20141	/* FLOOR_L_D_MMR6 */	----
20142	FGR64Opnd, FGR64Opnd,	----
20143	/* FLOOR_L_S */	----
20144	FGR64Opnd, FGR32Opnd,	----
20145	/* FLOOR_L_S_MMR6 */	----
20146	FGR64Opnd, FGR32Opnd,	----
20147	/* FLOOR_W_D32 */	----
20148	FGR32Opnd, AFGR64Opnd,	----
20149	/* FLOOR_W_D64 */	----
20150	FGR32Opnd, FGR64Opnd,	----
20151	/* FLOOR_W_D_MMR6 */	----
20152	FGR32Opnd, AFGR64Opnd,	----
20153	/* FLOOR_W_MM */	----
20154	FGR32Opnd, AFGR64Opnd,	----
20155	/* FLOOR_W_S */	----
20156	FGR32Opnd, FGR32Opnd,	----
20157	/* FLOOR_W_S_MM */	----
20158	FGR32Opnd, FGR32Opnd,	----
20159	/* FLOOR_W_S_MMR6 */	----
20160	FGR32Opnd, FGR32Opnd,	----
20161	/* FMADD_D */	----
20162	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20163	/* FMADD_W */	----
20164	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20165	/* FMAX_A_D */	----
20166	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20167	/* FMAX_A_W */	----
20168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20169	/* FMAX_D */	----
20170	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20171	/* FMAX_W */	----
20172	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20173	/* FMIN_A_D */	----
20174	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20175	/* FMIN_A_W */	----
20176	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20177	/* FMIN_D */	----
20178	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20179	/* FMIN_W */	----
20180	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20181	/* FMOV_D32 */	----
20182	AFGR64Opnd, AFGR64Opnd,	----
20183	/* FMOV_D32_MM */	----
20184	AFGR64Opnd, AFGR64Opnd,	----
20185	/* FMOV_D64 */	----
20186	FGR64Opnd, FGR64Opnd,	----
20187	/* FMOV_D64_MM */	----
20188	FGR64Opnd, FGR64Opnd,	----
20189	/* FMOV_D_MMR6 */	----
20190	FGR64Opnd, FGR64Opnd,	----
20191	/* FMOV_S */	----
20192	FGR32Opnd, FGR32Opnd,	----
20193	/* FMOV_S_MM */	----
20194	FGR32Opnd, FGR32Opnd,	----
20195	/* FMOV_S_MMR6 */	----
20196	FGR32Opnd, FGR32Opnd,	----
20197	/* FMSUB_D */	----
20198	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20199	/* FMSUB_W */	----
20200	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20201	/* FMUL_D */	----
20202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20203	/* FMUL_D32 */	----
20204	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20205	/* FMUL_D32_MM */	----
20206	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20207	/* FMUL_D64 */	----
20208	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20209	/* FMUL_D64_MM */	----
20210	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20211	/* FMUL_PS64 */	----
20212	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20213	/* FMUL_S */	----
20214	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20215	/* FMUL_S_MM */	----
20216	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20217	/* FMUL_S_MMR6 */	----
20218	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20219	/* FMUL_W */	----
20220	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20221	/* FNEG_D32 */	----
20222	AFGR64Opnd, AFGR64Opnd,	----
20223	/* FNEG_D32_MM */	----
20224	AFGR64Opnd, AFGR64Opnd,	----
20225	/* FNEG_D64 */	----
20226	FGR64Opnd, FGR64Opnd,	----
20227	/* FNEG_D64_MM */	----
20228	FGR64Opnd, FGR64Opnd,	----
20229	/* FNEG_S */	----
20230	FGR32Opnd, FGR32Opnd,	----
20231	/* FNEG_S_MM */	----
20232	FGR32Opnd, FGR32Opnd,	----
20233	/* FNEG_S_MMR6 */	----
20234	FGR32Opnd, FGR32Opnd,	----
20235	/* FORK */	----
20236	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
20237	/* FRCP_D */	----
20238	MSA128DOpnd, MSA128DOpnd,	----
20239	/* FRCP_W */	----
20240	MSA128WOpnd, MSA128WOpnd,	----
20241	/* FRINT_D */	----
20242	MSA128DOpnd, MSA128DOpnd,	----
20243	/* FRINT_W */	----
20244	MSA128WOpnd, MSA128WOpnd,	----
20245	/* FRSQRT_D */	----
20246	MSA128DOpnd, MSA128DOpnd,	----
20247	/* FRSQRT_W */	----
20248	MSA128WOpnd, MSA128WOpnd,	----
20249	/* FSAF_D */	----
20250	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20251	/* FSAF_W */	----
20252	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20253	/* FSEQ_D */	----
20254	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20255	/* FSEQ_W */	----
20256	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20257	/* FSLE_D */	----
20258	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20259	/* FSLE_W */	----
20260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20261	/* FSLT_D */	----
20262	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20263	/* FSLT_W */	----
20264	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20265	/* FSNE_D */	----
20266	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20267	/* FSNE_W */	----
20268	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20269	/* FSOR_D */	----
20270	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20271	/* FSOR_W */	----
20272	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20273	/* FSQRT_D */	----
20274	MSA128DOpnd, MSA128DOpnd,	----
20275	/* FSQRT_D32 */	----
20276	AFGR64Opnd, AFGR64Opnd,	----
20277	/* FSQRT_D32_MM */	----
20278	AFGR64Opnd, AFGR64Opnd,	----
20279	/* FSQRT_D64 */	----
20280	FGR64Opnd, FGR64Opnd,	----
20281	/* FSQRT_D64_MM */	----
20282	FGR64Opnd, FGR64Opnd,	----
20283	/* FSQRT_S */	----
20284	FGR32Opnd, FGR32Opnd,	----
20285	/* FSQRT_S_MM */	----
20286	FGR32Opnd, FGR32Opnd,	----
20287	/* FSQRT_W */	----
20288	MSA128WOpnd, MSA128WOpnd,	----
20289	/* FSUB_D */	----
20290	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20291	/* FSUB_D32 */	----
20292	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20293	/* FSUB_D32_MM */	----
20294	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20295	/* FSUB_D64 */	----
20296	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20297	/* FSUB_D64_MM */	----
20298	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20299	/* FSUB_PS64 */	----
20300	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20301	/* FSUB_S */	----
20302	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20303	/* FSUB_S_MM */	----
20304	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20305	/* FSUB_S_MMR6 */	----
20306	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20307	/* FSUB_W */	----
20308	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20309	/* FSUEQ_D */	----
20310	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20311	/* FSUEQ_W */	----
20312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20313	/* FSULE_D */	----
20314	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20315	/* FSULE_W */	----
20316	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20317	/* FSULT_D */	----
20318	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20319	/* FSULT_W */	----
20320	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20321	/* FSUNE_D */	----
20322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20323	/* FSUNE_W */	----
20324	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20325	/* FSUN_D */	----
20326	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20327	/* FSUN_W */	----
20328	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20329	/* FTINT_S_D */	----
20330	MSA128DOpnd, MSA128DOpnd,	----
20331	/* FTINT_S_W */	----
20332	MSA128WOpnd, MSA128WOpnd,	----
20333	/* FTINT_U_D */	----
20334	MSA128DOpnd, MSA128DOpnd,	----
20335	/* FTINT_U_W */	----
20336	MSA128WOpnd, MSA128WOpnd,	----
20337	/* FTQ_H */	----
20338	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	----
20339	/* FTQ_W */	----
20340	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	----
20341	/* FTRUNC_S_D */	----
20342	MSA128DOpnd, MSA128DOpnd,	----
20343	/* FTRUNC_S_W */	----
20344	MSA128WOpnd, MSA128WOpnd,	----
20345	/* FTRUNC_U_D */	----
20346	MSA128DOpnd, MSA128DOpnd,	----
20347	/* FTRUNC_U_W */	----
20348	MSA128WOpnd, MSA128WOpnd,	----
20349	/* GINVI */	----
20350	GPR32Opnd,	----
20351	/* GINVI_MMR6 */	----
20352	GPR32Opnd,	----
20353	/* GINVT */	----
20354	GPR32Opnd, uimm2,	----
20355	/* GINVT_MMR6 */	----
20356	GPR32Opnd, uimm2,	----
20357	/* HADD_S_D */	----
20358	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
20359	/* HADD_S_H */	----
20360	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
20361	/* HADD_S_W */	----
20362	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
20363	/* HADD_U_D */	----
20364	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
20365	/* HADD_U_H */	----
20366	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
20367	/* HADD_U_W */	----
20368	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
20369	/* HSUB_S_D */	----
20370	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
20371	/* HSUB_S_H */	----
20372	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
20373	/* HSUB_S_W */	----
20374	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
20375	/* HSUB_U_D */	----
20376	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	----
20377	/* HSUB_U_H */	----
20378	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	----
20379	/* HSUB_U_W */	----
20380	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	----
20381	/* HYPCALL */	----
20382	uimm10,	----
20383	/* HYPCALL_MM */	----
20384	uimm10,	----
20385	/* ILVEV_B */	----
20386	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20387	/* ILVEV_D */	----
20388	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20389	/* ILVEV_H */	----
20390	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20391	/* ILVEV_W */	----
20392	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20393	/* ILVL_B */	----
20394	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20395	/* ILVL_D */	----
20396	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20397	/* ILVL_H */	----
20398	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20399	/* ILVL_W */	----
20400	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20401	/* ILVOD_B */	----
20402	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20403	/* ILVOD_D */	----
20404	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20405	/* ILVOD_H */	----
20406	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20407	/* ILVOD_W */	----
20408	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20409	/* ILVR_B */	----
20410	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20411	/* ILVR_D */	----
20412	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20413	/* ILVR_H */	----
20414	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20415	/* ILVR_W */	----
20416	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20417	/* INS */	----
20418	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	----
20419	/* INSERT_B */	----
20420	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,	----
20421	/* INSERT_D */	----
20422	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,	----
20423	/* INSERT_H */	----
20424	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,	----
20425	/* INSERT_W */	----
20426	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,	----
20427	/* INSV */	----
20428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
20429	/* INSVE_B */	----
20430	MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,	----
20431	/* INSVE_D */	----
20432	MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,	----
20433	/* INSVE_H */	----
20434	MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,	----
20435	/* INSVE_W */	----
20436	MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,	----
20437	/* INSV_MM */	----
20438	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
20439	/* INS_MM */	----
20440	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	----
20441	/* INS_MMR6 */	----
20442	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	----
20443	/* J */	----
20444	jmptarget,	----
20445	/* JAL */	----
20446	calltarget,	----
20447	/* JALR */	----
20448	GPR32Opnd, GPR32Opnd,	----
20449	/* JALR16_MM */	----
20450	GPR32Opnd,	----
20451	/* JALR64 */	----
20452	GPR64Opnd, GPR64Opnd,	----
20453	/* JALRC16_MMR6 */	----
20454	GPR32Opnd,	----
20455	/* JALRC_HB_MMR6 */	----
20456	GPR32Opnd, GPR32Opnd,	----
20457	/* JALRC_MMR6 */	----
20458	GPR32Opnd, GPR32Opnd,	----
20459	/* JALRS16_MM */	----
20460	GPR32Opnd,	----
20461	/* JALRS_MM */	----
20462	GPR32Opnd, GPR32Opnd,	----
20463	/* JALR_HB */	----
20464	GPR32Opnd, GPR32Opnd,	----
20465	/* JALR_HB64 */	----
20466	GPR64Opnd, GPR64Opnd,	----
20467	/* JALR_MM */	----
20468	GPR32Opnd, GPR32Opnd,	----
20469	/* JALS_MM */	----
20470	calltarget_mm,	----
20471	/* JALX */	----
20472	calltarget,	----
20473	/* JALX_MM */	----
20474	calltarget,	----
20475	/* JAL_MM */	----
20476	calltarget_mm,	----
20477	/* JIALC */	----
20478	GPR32Opnd, calloffset16,	----
20479	/* JIALC64 */	----
20480	GPR64Opnd, calloffset16,	----
20481	/* JIALC_MMR6 */	----
20482	GPR32Opnd, calloffset16,	----
20483	/* JIC */	----
20484	GPR32Opnd, jmpoffset16,	----
20485	/* JIC64 */	----
20486	GPR64Opnd, jmpoffset16,	----
20487	/* JIC_MMR6 */	----
20488	GPR32Opnd, jmpoffset16,	----
20489	/* JR */	----
20490	GPR32Opnd,	----
20491	/* JR16_MM */	----
20492	GPR32Opnd,	----
20493	/* JR64 */	----
20494	GPR64Opnd,	----
20495	/* JRADDIUSP */	----
20496	uimm5_lsl2,	----
20497	/* JRC16_MM */	----
20498	GPR32Opnd,	----
20499	/* JRC16_MMR6 */	----
20500	GPR32Opnd,	----
20501	/* JRCADDIUSP_MMR6 */	----
20502	uimm5_lsl2,	----
20503	/* JR_HB */	----
20504	GPR32Opnd,	----
20505	/* JR_HB64 */	----
20506	GPR64Opnd,	----
20507	/* JR_HB64_R6 */	----
20508	GPR64Opnd,	----
20509	/* JR_HB_R6 */	----
20510	GPR32Opnd,	----
20511	/* JR_MM */	----
20512	GPR32Opnd,	----
20513	/* J_MM */	----
20514	jmptarget_mm,	----
20515	/* Jal16 */	----
20516	uimm26,	----
20517	/* JalB16 */	----
20518	uimm26,	----
20519	/* JrRa16 */	----
20520	/* JrcRa16 */	----
20521	/* JrcRx16 */	----
20522	CPU16Regs,	----
20523	/* JumpLinkReg16 */	----
20524	CPU16Regs,	----
20525	/* LB */	----
20526	GPR32Opnd, -1, simm16,	----
20527	/* LB64 */	----
20528	GPR64Opnd, -1, simm16,	----
20529	/* LBE */	----
20530	GPR32Opnd, -1, simm9,	----
20531	/* LBE_MM */	----
20532	GPR32Opnd, -1, simm16,	----
20533	/* LBU16_MM */	----
20534	GPRMM16Opnd, -1, simm4,	----
20535	/* LBUX */	----
20536	GPR32Opnd, -1, -1,	----
20537	/* LBUX_MM */	----
20538	GPR32Opnd, -1, -1,	----
20539	/* LBU_MMR6 */	----
20540	GPR32Opnd, -1, simm16,	----
20541	/* LB_MM */	----
20542	GPR32Opnd, -1, simm16,	----
20543	/* LB_MMR6 */	----
20544	GPR32Opnd, -1, simm16,	----
20545	/* LBu */	----
20546	GPR32Opnd, -1, simm16,	----
20547	/* LBu64 */	----
20548	GPR64Opnd, -1, simm16,	----
20549	/* LBuE */	----
20550	GPR32Opnd, -1, simm9,	----
20551	/* LBuE_MM */	----
20552	GPR32Opnd, -1, simm16,	----
20553	/* LBu_MM */	----
20554	GPR32Opnd, -1, simm16,	----
20555	/* LD */	----
20556	GPR64Opnd, -1, simm16,	----
20557	/* LDC1 */	----
20558	AFGR64Opnd, -1, simm16,	----
20559	/* LDC164 */	----
20560	FGR64Opnd, -1, simm16,	----
20561	/* LDC1_D64_MMR6 */	----
20562	FGR64Opnd, -1, simm16,	----
20563	/* LDC1_MM_D32 */	----
20564	AFGR64Opnd, -1, simm16,	----
20565	/* LDC1_MM_D64 */	----
20566	FGR64Opnd, -1, simm16,	----
20567	/* LDC2 */	----
20568	COP2Opnd, -1, simm16,	----
20569	/* LDC2_MMR6 */	----
20570	COP2Opnd, GPR32, simm11,	----
20571	/* LDC2_R6 */	----
20572	COP2Opnd, -1, simm11,	----
20573	/* LDC3 */	----
20574	COP3Opnd, -1, simm16,	----
20575	/* LDI_B */	----
20576	MSA128BOpnd, vsplat_simm10,	----
20577	/* LDI_D */	----
20578	MSA128DOpnd, vsplat_simm10,	----
20579	/* LDI_H */	----
20580	MSA128HOpnd, vsplat_simm10,	----
20581	/* LDI_W */	----
20582	MSA128WOpnd, vsplat_simm10,	----
20583	/* LDL */	----
20584	GPR64Opnd, -1, simm16, GPR64Opnd,	----
20585	/* LDPC */	----
20586	GPR64Opnd, simm18_lsl3,	----
20587	/* LDR */	----
20588	GPR64Opnd, -1, simm16, GPR64Opnd,	----
20589	/* LDXC1 */	----
20590	AFGR64Opnd, -1, -1,	----
20591	/* LDXC164 */	----
20592	FGR64Opnd, -1, -1,	----
20593	/* LD_B */	----
20594	MSA128BOpnd, -1, simm10,	----
20595	/* LD_D */	----
20596	MSA128DOpnd, -1, simm10_lsl3,	----
20597	/* LD_H */	----
20598	MSA128HOpnd, -1, simm10_lsl1,	----
20599	/* LD_W */	----
20600	MSA128WOpnd, -1, simm10_lsl2,	----
20601	/* LEA_ADDiu */	----
20602	GPR32Opnd, -1, simm16,	----
20603	/* LEA_ADDiu64 */	----
20604	GPR64Opnd, -1, simm16,	----
20605	/* LEA_ADDiu_MM */	----
20606	GPR32Opnd, -1, simm16,	----
20607	/* LH */	----
20608	GPR32Opnd, -1, simm16,	----
20609	/* LH64 */	----
20610	GPR64Opnd, -1, simm16,	----
20611	/* LHE */	----
20612	GPR32Opnd, -1, simm9,	----
20613	/* LHE_MM */	----
20614	GPR32Opnd, -1, simm9,	----
20615	/* LHU16_MM */	----
20616	GPRMM16Opnd, -1, simm4,	----
20617	/* LHX */	----
20618	GPR32Opnd, -1, -1,	----
20619	/* LHX_MM */	----
20620	GPR32Opnd, -1, -1,	----
20621	/* LH_MM */	----
20622	GPR32Opnd, -1, simm16,	----
20623	/* LHu */	----
20624	GPR32Opnd, -1, simm16,	----
20625	/* LHu64 */	----
20626	GPR64Opnd, -1, simm16,	----
20627	/* LHuE */	----
20628	GPR32Opnd, -1, simm9,	----
20629	/* LHuE_MM */	----
20630	GPR32Opnd, -1, simm9,	----
20631	/* LHu_MM */	----
20632	GPR32Opnd, -1, simm16,	----
20633	/* LI16_MM */	----
20634	GPRMM16Opnd, li16_imm,	----
20635	/* LI16_MMR6 */	----
20636	GPRMM16Opnd, li16_imm,	----
20637	/* LL */	----
20638	GPR32Opnd, -1, simm16,	----
20639	/* LL64 */	----
20640	GPR32Opnd, -1, simm16,	----
20641	/* LL64_R6 */	----
20642	GPR32Opnd, -1, simm9,	----
20643	/* LLD */	----
20644	GPR64Opnd, -1, simm16,	----
20645	/* LLD_R6 */	----
20646	GPR64Opnd, -1, simm9,	----
20647	/* LLE */	----
20648	GPR32Opnd, -1, simm9,	----
20649	/* LLE_MM */	----
20650	GPR32Opnd, -1, simm9,	----
20651	/* LL_MM */	----
20652	GPR32Opnd, -1, simm12,	----
20653	/* LL_MMR6 */	----
20654	GPR32Opnd, -1, simm9,	----
20655	/* LL_R6 */	----
20656	GPR32Opnd, -1, simm9,	----
20657	/* LSA */	----
20658	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	----
20659	/* LSA_MMR6 */	----
20660	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	----
20661	/* LSA_R6 */	----
20662	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	----
20663	/* LUI_MMR6 */	----
20664	GPR32Opnd, uimm16,	----
20665	/* LUXC1 */	----
20666	AFGR64Opnd, -1, -1,	----
20667	/* LUXC164 */	----
20668	FGR64Opnd, -1, -1,	----
20669	/* LUXC1_MM */	----
20670	FGR64Opnd, -1, -1,	----
20671	/* LUi */	----
20672	GPR32Opnd, uimm16_relaxed,	----
20673	/* LUi64 */	----
20674	GPR64Opnd, uimm16_64_relaxed,	----
20675	/* LUi_MM */	----
20676	GPR32Opnd, uimm16_relaxed,	----
20677	/* LW */	----
20678	GPR32Opnd, -1, simm16,	----
20679	/* LW16_MM */	----
20680	GPRMM16Opnd, -1, simm4,	----
20681	/* LW64 */	----
20682	GPR64Opnd, -1, simm16,	----
20683	/* LWC1 */	----
20684	FGR32Opnd, -1, simm16,	----
20685	/* LWC1_MM */	----
20686	FGR32Opnd, -1, simm16,	----
20687	/* LWC2 */	----
20688	COP2Opnd, -1, simm16,	----
20689	/* LWC2_MMR6 */	----
20690	COP2Opnd, GPR32, simm11,	----
20691	/* LWC2_R6 */	----
20692	COP2Opnd, -1, simm11,	----
20693	/* LWC3 */	----
20694	COP3Opnd, -1, simm16,	----
20695	/* LWDSP */	----
20696	DSPROpnd, -1, simm16,	----
20697	/* LWDSP_MM */	----
20698	DSPROpnd, -1, simm16,	----
20699	/* LWE */	----
20700	GPR32Opnd, -1, simm9,	----
20701	/* LWE_MM */	----
20702	GPR32Opnd, -1, simm9,	----
20703	/* LWGP_MM */	----
20704	GPRMM16Opnd, -1, simm7_lsl2,	----
20705	/* LWL */	----
20706	GPR32Opnd, -1, simm16, GPR32Opnd,	----
20707	/* LWL64 */	----
20708	GPR64Opnd, -1, simm16, GPR64Opnd,	----
20709	/* LWLE */	----
20710	GPR32Opnd, -1, simm9, GPR32Opnd,	----
20711	/* LWLE_MM */	----
20712	GPR32Opnd, -1, simm9, GPR32Opnd,	----
20713	/* LWL_MM */	----
20714	GPR32Opnd, -1, simm12, GPR32Opnd,	----
20715	/* LWM16_MM */	----
20716	reglist16, -1, uimm8,	----
20717	/* LWM16_MMR6 */	----
20718	reglist16, -1, uimm8,	----
20719	/* LWM32_MM */	----
20720	reglist, -1, simm12,	----
20721	/* LWPC */	----
20722	GPR32Opnd, simm19_lsl2,	----
20723	/* LWPC_MMR6 */	----
20724	GPR32Opnd, simm19_lsl2,	----
20725	/* LWP_MM */	----
20726	GPR32Opnd, GPR32Opnd, -1, simm12,	----
20727	/* LWR */	----
20728	GPR32Opnd, -1, simm16, GPR32Opnd,	----
20729	/* LWR64 */	----
20730	GPR64Opnd, -1, simm16, GPR64Opnd,	----
20731	/* LWRE */	----
20732	GPR32Opnd, -1, simm9, GPR32Opnd,	----
20733	/* LWRE_MM */	----
20734	GPR32Opnd, -1, simm9, GPR32Opnd,	----
20735	/* LWR_MM */	----
20736	GPR32Opnd, -1, simm12, GPR32Opnd,	----
20737	/* LWSP_MM */	----
20738	GPR32Opnd, -1, simm5,	----
20739	/* LWUPC */	----
20740	GPR32Opnd, simm19_lsl2,	----
20741	/* LWU_MM */	----
20742	GPR32Opnd, -1, simm12,	----
20743	/* LWX */	----
20744	GPR32Opnd, -1, -1,	----
20745	/* LWXC1 */	----
20746	FGR32Opnd, -1, -1,	----
20747	/* LWXC1_MM */	----
20748	FGR32Opnd, -1, -1,	----
20749	/* LWXS_MM */	----
20750	GPR32Opnd, -1, -1,	----
20751	/* LWX_MM */	----
20752	GPR32Opnd, -1, -1,	----
20753	/* LW_MM */	----
20754	GPR32Opnd, -1, simm16,	----
20755	/* LW_MMR6 */	----
20756	GPR32Opnd, -1, simm16,	----
20757	/* LWu */	----
20758	GPR64Opnd, -1, simm16,	----
20759	/* LbRxRyOffMemX16 */	----
20760	CPU16Regs, CPU16Regs, simm16,	----
20761	/* LbuRxRyOffMemX16 */	----
20762	CPU16Regs, CPU16Regs, simm16,	----
20763	/* LhRxRyOffMemX16 */	----
20764	CPU16Regs, CPU16Regs, simm16,	----
20765	/* LhuRxRyOffMemX16 */	----
20766	CPU16Regs, CPU16Regs, simm16,	----
20767	/* LiRxImm16 */	----
20768	CPU16Regs, simm16,	----
20769	/* LiRxImmAlignX16 */	----
20770	CPU16Regs, simm16,	----
20771	/* LiRxImmX16 */	----
20772	CPU16Regs, simm16,	----
20773	/* LwRxPcTcp16 */	----
20774	CPU16Regs, pcrel16, i32imm,	----
20775	/* LwRxPcTcpX16 */	----
20776	CPU16Regs, pcrel16, i32imm,	----
20777	/* LwRxRyOffMemX16 */	----
20778	CPU16Regs, CPU16Regs, simm16,	----
20779	/* LwRxSpImmX16 */	----
20780	CPU16Regs, CPU16RegsPlusSP, simm16,	----
20781	/* MADD */	----
20782	GPR32Opnd, GPR32Opnd,	----
20783	/* MADDF_D */	----
20784	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20785	/* MADDF_D_MMR6 */	----
20786	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20787	/* MADDF_S */	----
20788	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20789	/* MADDF_S_MMR6 */	----
20790	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20791	/* MADDR_Q_H */	----
20792	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20793	/* MADDR_Q_W */	----
20794	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20795	/* MADDU */	----
20796	GPR32Opnd, GPR32Opnd,	----
20797	/* MADDU_DSP */	----
20798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20799	/* MADDU_DSP_MM */	----
20800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20801	/* MADDU_MM */	----
20802	GPR32Opnd, GPR32Opnd,	----
20803	/* MADDV_B */	----
20804	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20805	/* MADDV_D */	----
20806	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20807	/* MADDV_H */	----
20808	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20809	/* MADDV_W */	----
20810	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20811	/* MADD_D32 */	----
20812	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20813	/* MADD_D32_MM */	----
20814	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
20815	/* MADD_D64 */	----
20816	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20817	/* MADD_DSP */	----
20818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20819	/* MADD_DSP_MM */	----
20820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20821	/* MADD_MM */	----
20822	GPR32Opnd, GPR32Opnd,	----
20823	/* MADD_Q_H */	----
20824	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20825	/* MADD_Q_W */	----
20826	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20827	/* MADD_S */	----
20828	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20829	/* MADD_S_MM */	----
20830	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20831	/* MAQ_SA_W_PHL */	----
20832	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20833	/* MAQ_SA_W_PHL_MM */	----
20834	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20835	/* MAQ_SA_W_PHR */	----
20836	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20837	/* MAQ_SA_W_PHR_MM */	----
20838	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20839	/* MAQ_S_W_PHL */	----
20840	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20841	/* MAQ_S_W_PHL_MM */	----
20842	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20843	/* MAQ_S_W_PHR */	----
20844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20845	/* MAQ_S_W_PHR_MM */	----
20846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
20847	/* MAXA_D */	----
20848	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20849	/* MAXA_D_MMR6 */	----
20850	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20851	/* MAXA_S */	----
20852	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20853	/* MAXA_S_MMR6 */	----
20854	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20855	/* MAXI_S_B */	----
20856	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	----
20857	/* MAXI_S_D */	----
20858	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	----
20859	/* MAXI_S_H */	----
20860	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	----
20861	/* MAXI_S_W */	----
20862	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	----
20863	/* MAXI_U_B */	----
20864	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
20865	/* MAXI_U_D */	----
20866	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
20867	/* MAXI_U_H */	----
20868	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
20869	/* MAXI_U_W */	----
20870	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
20871	/* MAX_A_B */	----
20872	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20873	/* MAX_A_D */	----
20874	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20875	/* MAX_A_H */	----
20876	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20877	/* MAX_A_W */	----
20878	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20879	/* MAX_D */	----
20880	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20881	/* MAX_D_MMR6 */	----
20882	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20883	/* MAX_S */	----
20884	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20885	/* MAX_S_B */	----
20886	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20887	/* MAX_S_D */	----
20888	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20889	/* MAX_S_H */	----
20890	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20891	/* MAX_S_MMR6 */	----
20892	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20893	/* MAX_S_W */	----
20894	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20895	/* MAX_U_B */	----
20896	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20897	/* MAX_U_D */	----
20898	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20899	/* MAX_U_H */	----
20900	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20901	/* MAX_U_W */	----
20902	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20903	/* MFC0 */	----
20904	GPR32Opnd, COP0Opnd, uimm3,	----
20905	/* MFC0_MMR6 */	----
20906	GPR32Opnd, COP0Opnd, uimm3,	----
20907	/* MFC1 */	----
20908	GPR32Opnd, FGR32Opnd,	----
20909	/* MFC1_D64 */	----
20910	GPR32Opnd, FGR64Opnd,	----
20911	/* MFC1_MM */	----
20912	GPR32Opnd, FGR32Opnd,	----
20913	/* MFC1_MMR6 */	----
20914	GPR32Opnd, FGR32Opnd,	----
20915	/* MFC2 */	----
20916	GPR32Opnd, COP2Opnd, uimm3,	----
20917	/* MFC2_MMR6 */	----
20918	GPR32Opnd, COP2Opnd,	----
20919	/* MFGC0 */	----
20920	GPR32Opnd, COP0Opnd, uimm3,	----
20921	/* MFGC0_MM */	----
20922	GPR32Opnd, COP0Opnd, uimm3,	----
20923	/* MFHC0_MMR6 */	----
20924	GPR32Opnd, COP0Opnd, uimm3,	----
20925	/* MFHC1_D32 */	----
20926	GPR32Opnd, AFGR64Opnd,	----
20927	/* MFHC1_D32_MM */	----
20928	GPR32Opnd, AFGR64Opnd,	----
20929	/* MFHC1_D64 */	----
20930	GPR32Opnd, FGR64Opnd,	----
20931	/* MFHC1_D64_MM */	----
20932	GPR32Opnd, FGR64Opnd,	----
20933	/* MFHC2_MMR6 */	----
20934	GPR32Opnd, COP2Opnd,	----
20935	/* MFHGC0 */	----
20936	GPR32Opnd, COP0Opnd, uimm3,	----
20937	/* MFHGC0_MM */	----
20938	GPR32Opnd, COP0Opnd, uimm3,	----
20939	/* MFHI */	----
20940	GPR32Opnd,	----
20941	/* MFHI16_MM */	----
20942	GPR32Opnd,	----
20943	/* MFHI64 */	----
20944	GPR64Opnd,	----
20945	/* MFHI_DSP */	----
20946	GPR32Opnd, ACC64DSPOpnd,	----
20947	/* MFHI_DSP_MM */	----
20948	GPR32Opnd, ACC64DSPOpnd,	----
20949	/* MFHI_MM */	----
20950	GPR32Opnd,	----
20951	/* MFLO */	----
20952	GPR32Opnd,	----
20953	/* MFLO16_MM */	----
20954	GPR32Opnd,	----
20955	/* MFLO64 */	----
20956	GPR64Opnd,	----
20957	/* MFLO_DSP */	----
20958	GPR32Opnd, ACC64DSPOpnd,	----
20959	/* MFLO_DSP_MM */	----
20960	GPR32Opnd, ACC64DSPOpnd,	----
20961	/* MFLO_MM */	----
20962	GPR32Opnd,	----
20963	/* MFTR */	----
20964	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	----
20965	/* MINA_D */	----
20966	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20967	/* MINA_D_MMR6 */	----
20968	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20969	/* MINA_S */	----
20970	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20971	/* MINA_S_MMR6 */	----
20972	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
20973	/* MINI_S_B */	----
20974	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	----
20975	/* MINI_S_D */	----
20976	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	----
20977	/* MINI_S_H */	----
20978	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	----
20979	/* MINI_S_W */	----
20980	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	----
20981	/* MINI_U_B */	----
20982	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
20983	/* MINI_U_D */	----
20984	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
20985	/* MINI_U_H */	----
20986	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
20987	/* MINI_U_W */	----
20988	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
20989	/* MIN_A_B */	----
20990	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
20991	/* MIN_A_D */	----
20992	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
20993	/* MIN_A_H */	----
20994	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
20995	/* MIN_A_W */	----
20996	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
20997	/* MIN_D */	----
20998	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
20999	/* MIN_D_MMR6 */	----
21000	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21001	/* MIN_S */	----
21002	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21003	/* MIN_S_B */	----
21004	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21005	/* MIN_S_D */	----
21006	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21007	/* MIN_S_H */	----
21008	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21009	/* MIN_S_MMR6 */	----
21010	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21011	/* MIN_S_W */	----
21012	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21013	/* MIN_U_B */	----
21014	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21015	/* MIN_U_D */	----
21016	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21017	/* MIN_U_H */	----
21018	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21019	/* MIN_U_W */	----
21020	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21021	/* MOD */	----
21022	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21023	/* MODSUB */	----
21024	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21025	/* MODSUB_MM */	----
21026	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21027	/* MODU */	----
21028	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21029	/* MODU_MMR6 */	----
21030	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21031	/* MOD_MMR6 */	----
21032	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21033	/* MOD_S_B */	----
21034	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21035	/* MOD_S_D */	----
21036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21037	/* MOD_S_H */	----
21038	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21039	/* MOD_S_W */	----
21040	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21041	/* MOD_U_B */	----
21042	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21043	/* MOD_U_D */	----
21044	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21045	/* MOD_U_H */	----
21046	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21047	/* MOD_U_W */	----
21048	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21049	/* MOVE16_MM */	----
21050	GPR32Opnd, GPR32Opnd,	----
21051	/* MOVE16_MMR6 */	----
21052	GPR32Opnd, GPR32Opnd,	----
21053	/* MOVEP_MM */	----
21054	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	----
21055	/* MOVEP_MMR6 */	----
21056	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	----
21057	/* MOVE_V */	----
21058	MSA128BOpnd, MSA128BOpnd,	----
21059	/* MOVF_D32 */	----
21060	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	----
21061	/* MOVF_D32_MM */	----
21062	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	----
21063	/* MOVF_D64 */	----
21064	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	----
21065	/* MOVF_I */	----
21066	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	----
21067	/* MOVF_I64 */	----
21068	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	----
21069	/* MOVF_I_MM */	----
21070	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	----
21071	/* MOVF_S */	----
21072	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	----
21073	/* MOVF_S_MM */	----
21074	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	----
21075	/* MOVN_I64_D64 */	----
21076	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	----
21077	/* MOVN_I64_I */	----
21078	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	----
21079	/* MOVN_I64_I64 */	----
21080	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21081	/* MOVN_I64_S */	----
21082	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	----
21083	/* MOVN_I_D32 */	----
21084	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	----
21085	/* MOVN_I_D32_MM */	----
21086	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	----
21087	/* MOVN_I_D64 */	----
21088	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	----
21089	/* MOVN_I_I */	----
21090	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21091	/* MOVN_I_I64 */	----
21092	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	----
21093	/* MOVN_I_MM */	----
21094	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21095	/* MOVN_I_S */	----
21096	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	----
21097	/* MOVN_I_S_MM */	----
21098	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	----
21099	/* MOVT_D32 */	----
21100	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	----
21101	/* MOVT_D32_MM */	----
21102	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	----
21103	/* MOVT_D64 */	----
21104	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	----
21105	/* MOVT_I */	----
21106	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	----
21107	/* MOVT_I64 */	----
21108	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	----
21109	/* MOVT_I_MM */	----
21110	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	----
21111	/* MOVT_S */	----
21112	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	----
21113	/* MOVT_S_MM */	----
21114	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	----
21115	/* MOVZ_I64_D64 */	----
21116	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	----
21117	/* MOVZ_I64_I */	----
21118	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	----
21119	/* MOVZ_I64_I64 */	----
21120	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21121	/* MOVZ_I64_S */	----
21122	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	----
21123	/* MOVZ_I_D32 */	----
21124	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	----
21125	/* MOVZ_I_D32_MM */	----
21126	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	----
21127	/* MOVZ_I_D64 */	----
21128	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	----
21129	/* MOVZ_I_I */	----
21130	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21131	/* MOVZ_I_I64 */	----
21132	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	----
21133	/* MOVZ_I_MM */	----
21134	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21135	/* MOVZ_I_S */	----
21136	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	----
21137	/* MOVZ_I_S_MM */	----
21138	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	----
21139	/* MSUB */	----
21140	GPR32Opnd, GPR32Opnd,	----
21141	/* MSUBF_D */	----
21142	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21143	/* MSUBF_D_MMR6 */	----
21144	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21145	/* MSUBF_S */	----
21146	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21147	/* MSUBF_S_MMR6 */	----
21148	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21149	/* MSUBR_Q_H */	----
21150	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21151	/* MSUBR_Q_W */	----
21152	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21153	/* MSUBU */	----
21154	GPR32Opnd, GPR32Opnd,	----
21155	/* MSUBU_DSP */	----
21156	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21157	/* MSUBU_DSP_MM */	----
21158	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21159	/* MSUBU_MM */	----
21160	GPR32Opnd, GPR32Opnd,	----
21161	/* MSUBV_B */	----
21162	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21163	/* MSUBV_D */	----
21164	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21165	/* MSUBV_H */	----
21166	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21167	/* MSUBV_W */	----
21168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21169	/* MSUB_D32 */	----
21170	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21171	/* MSUB_D32_MM */	----
21172	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21173	/* MSUB_D64 */	----
21174	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21175	/* MSUB_DSP */	----
21176	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21177	/* MSUB_DSP_MM */	----
21178	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21179	/* MSUB_MM */	----
21180	GPR32Opnd, GPR32Opnd,	----
21181	/* MSUB_Q_H */	----
21182	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21183	/* MSUB_Q_W */	----
21184	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21185	/* MSUB_S */	----
21186	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21187	/* MSUB_S_MM */	----
21188	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21189	/* MTC0 */	----
21190	COP0Opnd, GPR32Opnd, uimm3,	----
21191	/* MTC0_MMR6 */	----
21192	COP0Opnd, GPR32Opnd, uimm3,	----
21193	/* MTC1 */	----
21194	FGR32Opnd, GPR32Opnd,	----
21195	/* MTC1_D64 */	----
21196	FGR64Opnd, GPR32Opnd,	----
21197	/* MTC1_D64_MM */	----
21198	FGR64Opnd, GPR32Opnd,	----
21199	/* MTC1_MM */	----
21200	FGR32Opnd, GPR32Opnd,	----
21201	/* MTC1_MMR6 */	----
21202	FGR32Opnd, GPR32Opnd,	----
21203	/* MTC2 */	----
21204	COP2Opnd, GPR32Opnd, uimm3,	----
21205	/* MTC2_MMR6 */	----
21206	COP2Opnd, GPR32Opnd,	----
21207	/* MTGC0 */	----
21208	COP0Opnd, GPR32Opnd, uimm3,	----
21209	/* MTGC0_MM */	----
21210	COP0Opnd, GPR32Opnd, uimm3,	----
21211	/* MTHC0_MMR6 */	----
21212	COP0Opnd, GPR32Opnd, uimm3,	----
21213	/* MTHC1_D32 */	----
21214	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	----
21215	/* MTHC1_D32_MM */	----
21216	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	----
21217	/* MTHC1_D64 */	----
21218	FGR64Opnd, FGR64Opnd, GPR32Opnd,	----
21219	/* MTHC1_D64_MM */	----
21220	FGR64Opnd, FGR64Opnd, GPR32Opnd,	----
21221	/* MTHC2_MMR6 */	----
21222	COP2Opnd, GPR32Opnd,	----
21223	/* MTHGC0 */	----
21224	COP0Opnd, GPR32Opnd, uimm3,	----
21225	/* MTHGC0_MM */	----
21226	COP0Opnd, GPR32Opnd, uimm3,	----
21227	/* MTHI */	----
21228	GPR32Opnd,	----
21229	/* MTHI64 */	----
21230	GPR64Opnd,	----
21231	/* MTHI_DSP */	----
21232	HI32DSPOpnd, GPR32Opnd,	----
21233	/* MTHI_DSP_MM */	----
21234	HI32DSPOpnd, GPR32Opnd,	----
21235	/* MTHI_MM */	----
21236	GPR32Opnd,	----
21237	/* MTHLIP */	----
21238	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	----
21239	/* MTHLIP_MM */	----
21240	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	----
21241	/* MTLO */	----
21242	GPR32Opnd,	----
21243	/* MTLO64 */	----
21244	GPR64Opnd,	----
21245	/* MTLO_DSP */	----
21246	LO32DSPOpnd, GPR32Opnd,	----
21247	/* MTLO_DSP_MM */	----
21248	LO32DSPOpnd, GPR32Opnd,	----
21249	/* MTLO_MM */	----
21250	GPR32Opnd,	----
21251	/* MTM0 */	----
21252	GPR64Opnd,	----
21253	/* MTM1 */	----
21254	GPR64Opnd,	----
21255	/* MTM2 */	----
21256	GPR64Opnd,	----
21257	/* MTP0 */	----
21258	GPR64Opnd,	----
21259	/* MTP1 */	----
21260	GPR64Opnd,	----
21261	/* MTP2 */	----
21262	GPR64Opnd,	----
21263	/* MTTR */	----
21264	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	----
21265	/* MUH */	----
21266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21267	/* MUHU */	----
21268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21269	/* MUHU_MMR6 */	----
21270	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21271	/* MUH_MMR6 */	----
21272	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21273	/* MUL */	----
21274	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21275	/* MULEQ_S_W_PHL */	----
21276	GPR32Opnd, DSPROpnd, DSPROpnd,	----
21277	/* MULEQ_S_W_PHL_MM */	----
21278	GPR32Opnd, DSPROpnd, DSPROpnd,	----
21279	/* MULEQ_S_W_PHR */	----
21280	GPR32Opnd, DSPROpnd, DSPROpnd,	----
21281	/* MULEQ_S_W_PHR_MM */	----
21282	GPR32Opnd, DSPROpnd, DSPROpnd,	----
21283	/* MULEU_S_PH_QBL */	----
21284	DSPROpnd, DSPROpnd, DSPROpnd,	----
21285	/* MULEU_S_PH_QBL_MM */	----
21286	DSPROpnd, DSPROpnd, DSPROpnd,	----
21287	/* MULEU_S_PH_QBR */	----
21288	DSPROpnd, DSPROpnd, DSPROpnd,	----
21289	/* MULEU_S_PH_QBR_MM */	----
21290	DSPROpnd, DSPROpnd, DSPROpnd,	----
21291	/* MULQ_RS_PH */	----
21292	DSPROpnd, DSPROpnd, DSPROpnd,	----
21293	/* MULQ_RS_PH_MM */	----
21294	DSPROpnd, DSPROpnd, DSPROpnd,	----
21295	/* MULQ_RS_W */	----
21296	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21297	/* MULQ_RS_W_MMR2 */	----
21298	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21299	/* MULQ_S_PH */	----
21300	DSPROpnd, DSPROpnd, DSPROpnd,	----
21301	/* MULQ_S_PH_MMR2 */	----
21302	DSPROpnd, DSPROpnd, DSPROpnd,	----
21303	/* MULQ_S_W */	----
21304	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21305	/* MULQ_S_W_MMR2 */	----
21306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21307	/* MULR_PS64 */	----
21308	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21309	/* MULR_Q_H */	----
21310	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21311	/* MULR_Q_W */	----
21312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21313	/* MULSAQ_S_W_PH */	----
21314	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21315	/* MULSAQ_S_W_PH_MM */	----
21316	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21317	/* MULSA_W_PH */	----
21318	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21319	/* MULSA_W_PH_MMR2 */	----
21320	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	----
21321	/* MULT */	----
21322	GPR32Opnd, GPR32Opnd,	----
21323	/* MULTU_DSP */	----
21324	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	----
21325	/* MULTU_DSP_MM */	----
21326	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	----
21327	/* MULT_DSP */	----
21328	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	----
21329	/* MULT_DSP_MM */	----
21330	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	----
21331	/* MULT_MM */	----
21332	GPR32Opnd, GPR32Opnd,	----
21333	/* MULTu */	----
21334	GPR32Opnd, GPR32Opnd,	----
21335	/* MULTu_MM */	----
21336	GPR32Opnd, GPR32Opnd,	----
21337	/* MULU */	----
21338	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21339	/* MULU_MMR6 */	----
21340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21341	/* MULV_B */	----
21342	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21343	/* MULV_D */	----
21344	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21345	/* MULV_H */	----
21346	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21347	/* MULV_W */	----
21348	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21349	/* MUL_MM */	----
21350	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21351	/* MUL_MMR6 */	----
21352	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21353	/* MUL_PH */	----
21354	DSPROpnd, DSPROpnd, DSPROpnd,	----
21355	/* MUL_PH_MMR2 */	----
21356	DSPROpnd, DSPROpnd, DSPROpnd,	----
21357	/* MUL_Q_H */	----
21358	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21359	/* MUL_Q_W */	----
21360	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21361	/* MUL_R6 */	----
21362	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21363	/* MUL_S_PH */	----
21364	DSPROpnd, DSPROpnd, DSPROpnd,	----
21365	/* MUL_S_PH_MMR2 */	----
21366	DSPROpnd, DSPROpnd, DSPROpnd,	----
21367	/* Mfhi16 */	----
21368	CPU16Regs,	----
21369	/* Mflo16 */	----
21370	CPU16Regs,	----
21371	/* Move32R16 */	----
21372	GPR32, CPU16Regs,	----
21373	/* MoveR3216 */	----
21374	CPU16Regs, GPR32,	----
21375	/* NLOC_B */	----
21376	MSA128BOpnd, MSA128BOpnd,	----
21377	/* NLOC_D */	----
21378	MSA128DOpnd, MSA128DOpnd,	----
21379	/* NLOC_H */	----
21380	MSA128HOpnd, MSA128HOpnd,	----
21381	/* NLOC_W */	----
21382	MSA128WOpnd, MSA128WOpnd,	----
21383	/* NLZC_B */	----
21384	MSA128BOpnd, MSA128BOpnd,	----
21385	/* NLZC_D */	----
21386	MSA128DOpnd, MSA128DOpnd,	----
21387	/* NLZC_H */	----
21388	MSA128HOpnd, MSA128HOpnd,	----
21389	/* NLZC_W */	----
21390	MSA128WOpnd, MSA128WOpnd,	----
21391	/* NMADD_D32 */	----
21392	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21393	/* NMADD_D32_MM */	----
21394	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21395	/* NMADD_D64 */	----
21396	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21397	/* NMADD_S */	----
21398	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21399	/* NMADD_S_MM */	----
21400	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21401	/* NMSUB_D32 */	----
21402	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21403	/* NMSUB_D32_MM */	----
21404	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	----
21405	/* NMSUB_D64 */	----
21406	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21407	/* NMSUB_S */	----
21408	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21409	/* NMSUB_S_MM */	----
21410	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21411	/* NOR */	----
21412	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21413	/* NOR64 */	----
21414	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21415	/* NORI_B */	----
21416	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
21417	/* NOR_MM */	----
21418	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21419	/* NOR_MMR6 */	----
21420	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21421	/* NOR_V */	----
21422	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21423	/* NOT16_MM */	----
21424	GPRMM16Opnd, GPRMM16Opnd,	----
21425	/* NOT16_MMR6 */	----
21426	GPRMM16Opnd, GPRMM16Opnd,	----
21427	/* NegRxRy16 */	----
21428	CPU16Regs, CPU16Regs,	----
21429	/* NotRxRy16 */	----
21430	CPU16Regs, CPU16Regs,	----
21431	/* OR */	----
21432	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21433	/* OR16_MM */	----
21434	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
21435	/* OR16_MMR6 */	----
21436	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
21437	/* OR64 */	----
21438	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21439	/* ORI_B */	----
21440	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
21441	/* ORI_MMR6 */	----
21442	GPR32Opnd, GPR32Opnd, uimm16,	----
21443	/* OR_MM */	----
21444	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21445	/* OR_MMR6 */	----
21446	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21447	/* OR_V */	----
21448	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21449	/* ORi */	----
21450	GPR32Opnd, GPR32Opnd, uimm16,	----
21451	/* ORi64 */	----
21452	GPR64Opnd, GPR64Opnd, uimm16_64,	----
21453	/* ORi_MM */	----
21454	GPR32Opnd, GPR32Opnd, uimm16,	----
21455	/* OrRxRxRy16 */	----
21456	CPU16Regs, CPU16Regs, CPU16Regs,	----
21457	/* PACKRL_PH */	----
21458	DSPROpnd, DSPROpnd, DSPROpnd,	----
21459	/* PACKRL_PH_MM */	----
21460	DSPROpnd, DSPROpnd, DSPROpnd,	----
21461	/* PAUSE */	----
21462	/* PAUSE_MM */	----
21463	/* PAUSE_MMR6 */	----
21464	/* PCKEV_B */	----
21465	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21466	/* PCKEV_D */	----
21467	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21468	/* PCKEV_H */	----
21469	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21470	/* PCKEV_W */	----
21471	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21472	/* PCKOD_B */	----
21473	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
21474	/* PCKOD_D */	----
21475	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
21476	/* PCKOD_H */	----
21477	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
21478	/* PCKOD_W */	----
21479	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
21480	/* PCNT_B */	----
21481	MSA128BOpnd, MSA128BOpnd,	----
21482	/* PCNT_D */	----
21483	MSA128DOpnd, MSA128DOpnd,	----
21484	/* PCNT_H */	----
21485	MSA128HOpnd, MSA128HOpnd,	----
21486	/* PCNT_W */	----
21487	MSA128WOpnd, MSA128WOpnd,	----
21488	/* PICK_PH */	----
21489	DSPROpnd, DSPROpnd, DSPROpnd,	----
21490	/* PICK_PH_MM */	----
21491	DSPROpnd, DSPROpnd, DSPROpnd,	----
21492	/* PICK_QB */	----
21493	DSPROpnd, DSPROpnd, DSPROpnd,	----
21494	/* PICK_QB_MM */	----
21495	DSPROpnd, DSPROpnd, DSPROpnd,	----
21496	/* PLL_PS64 */	----
21497	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21498	/* PLU_PS64 */	----
21499	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21500	/* POP */	----
21501	GPR32Opnd, GPR32Opnd,	----
21502	/* PRECEQU_PH_QBL */	----
21503	DSPROpnd, DSPROpnd,	----
21504	/* PRECEQU_PH_QBLA */	----
21505	DSPROpnd, DSPROpnd,	----
21506	/* PRECEQU_PH_QBLA_MM */	----
21507	DSPROpnd, DSPROpnd,	----
21508	/* PRECEQU_PH_QBL_MM */	----
21509	DSPROpnd, DSPROpnd,	----
21510	/* PRECEQU_PH_QBR */	----
21511	DSPROpnd, DSPROpnd,	----
21512	/* PRECEQU_PH_QBRA */	----
21513	DSPROpnd, DSPROpnd,	----
21514	/* PRECEQU_PH_QBRA_MM */	----
21515	DSPROpnd, DSPROpnd,	----
21516	/* PRECEQU_PH_QBR_MM */	----
21517	DSPROpnd, DSPROpnd,	----
21518	/* PRECEQ_W_PHL */	----
21519	GPR32Opnd, DSPROpnd,	----
21520	/* PRECEQ_W_PHL_MM */	----
21521	GPR32Opnd, DSPROpnd,	----
21522	/* PRECEQ_W_PHR */	----
21523	GPR32Opnd, DSPROpnd,	----
21524	/* PRECEQ_W_PHR_MM */	----
21525	GPR32Opnd, DSPROpnd,	----
21526	/* PRECEU_PH_QBL */	----
21527	DSPROpnd, DSPROpnd,	----
21528	/* PRECEU_PH_QBLA */	----
21529	DSPROpnd, DSPROpnd,	----
21530	/* PRECEU_PH_QBLA_MM */	----
21531	DSPROpnd, DSPROpnd,	----
21532	/* PRECEU_PH_QBL_MM */	----
21533	DSPROpnd, DSPROpnd,	----
21534	/* PRECEU_PH_QBR */	----
21535	DSPROpnd, DSPROpnd,	----
21536	/* PRECEU_PH_QBRA */	----
21537	DSPROpnd, DSPROpnd,	----
21538	/* PRECEU_PH_QBRA_MM */	----
21539	DSPROpnd, DSPROpnd,	----
21540	/* PRECEU_PH_QBR_MM */	----
21541	DSPROpnd, DSPROpnd,	----
21542	/* PRECRQU_S_QB_PH */	----
21543	DSPROpnd, DSPROpnd, DSPROpnd,	----
21544	/* PRECRQU_S_QB_PH_MM */	----
21545	DSPROpnd, DSPROpnd, DSPROpnd,	----
21546	/* PRECRQ_PH_W */	----
21547	DSPROpnd, GPR32Opnd, GPR32Opnd,	----
21548	/* PRECRQ_PH_W_MM */	----
21549	DSPROpnd, GPR32Opnd, GPR32Opnd,	----
21550	/* PRECRQ_QB_PH */	----
21551	DSPROpnd, DSPROpnd, DSPROpnd,	----
21552	/* PRECRQ_QB_PH_MM */	----
21553	DSPROpnd, DSPROpnd, DSPROpnd,	----
21554	/* PRECRQ_RS_PH_W */	----
21555	DSPROpnd, GPR32Opnd, GPR32Opnd,	----
21556	/* PRECRQ_RS_PH_W_MM */	----
21557	DSPROpnd, GPR32Opnd, GPR32Opnd,	----
21558	/* PRECR_QB_PH */	----
21559	DSPROpnd, DSPROpnd, DSPROpnd,	----
21560	/* PRECR_QB_PH_MMR2 */	----
21561	DSPROpnd, DSPROpnd, DSPROpnd,	----
21562	/* PRECR_SRA_PH_W */	----
21563	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21564	/* PRECR_SRA_PH_W_MMR2 */	----
21565	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21566	/* PRECR_SRA_R_PH_W */	----
21567	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21568	/* PRECR_SRA_R_PH_W_MMR2 */	----
21569	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21570	/* PREF */	----
21571	-1, simm16, uimm5,	----
21572	/* PREFE */	----
21573	-1, simm9, uimm5,	----
21574	/* PREFE_MM */	----
21575	-1, simm9, uimm5,	----
21576	/* PREFX_MM */	----
21577	-1, -1, uimm5,	----
21578	/* PREF_MM */	----
21579	-1, simm12, uimm5,	----
21580	/* PREF_MMR6 */	----
21581	-1, simm12, uimm5,	----
21582	/* PREF_R6 */	----
21583	-1, simm9, uimm5,	----
21584	/* PREPEND */	----
21585	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21586	/* PREPEND_MMR2 */	----
21587	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	----
21588	/* PUL_PS64 */	----
21589	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21590	/* PUU_PS64 */	----
21591	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21592	/* RADDU_W_QB */	----
21593	GPR32Opnd, DSPROpnd,	----
21594	/* RADDU_W_QB_MM */	----
21595	GPR32Opnd, DSPROpnd,	----
21596	/* RDDSP */	----
21597	GPR32Opnd, uimm10,	----
21598	/* RDDSP_MM */	----
21599	GPR32Opnd, uimm7,	----
21600	/* RDHWR */	----
21601	GPR32Opnd, HWRegsOpnd, uimm8,	----
21602	/* RDHWR64 */	----
21603	GPR64Opnd, HWRegsOpnd, uimm8,	----
21604	/* RDHWR_MM */	----
21605	GPR32Opnd, HWRegsOpnd, uimm8,	----
21606	/* RDHWR_MMR6 */	----
21607	GPR32Opnd, HWRegsOpnd, uimm3,	----
21608	/* RDPGPR_MMR6 */	----
21609	GPR32Opnd, GPR32Opnd,	----
21610	/* RECIP_D32 */	----
21611	AFGR64Opnd, AFGR64Opnd,	----
21612	/* RECIP_D32_MM */	----
21613	AFGR64Opnd, AFGR64Opnd,	----
21614	/* RECIP_D64 */	----
21615	FGR64Opnd, FGR64Opnd,	----
21616	/* RECIP_D64_MM */	----
21617	FGR64Opnd, FGR64Opnd,	----
21618	/* RECIP_S */	----
21619	FGR32Opnd, FGR32Opnd,	----
21620	/* RECIP_S_MM */	----
21621	FGR32Opnd, FGR32Opnd,	----
21622	/* REPLV_PH */	----
21623	DSPROpnd, GPR32Opnd,	----
21624	/* REPLV_PH_MM */	----
21625	DSPROpnd, GPR32Opnd,	----
21626	/* REPLV_QB */	----
21627	DSPROpnd, GPR32Opnd,	----
21628	/* REPLV_QB_MM */	----
21629	DSPROpnd, GPR32Opnd,	----
21630	/* REPL_PH */	----
21631	DSPROpnd, simm10,	----
21632	/* REPL_PH_MM */	----
21633	DSPROpnd, simm10,	----
21634	/* REPL_QB */	----
21635	DSPROpnd, uimm8,	----
21636	/* REPL_QB_MM */	----
21637	DSPROpnd, uimm8,	----
21638	/* RINT_D */	----
21639	FGR64Opnd, FGR64Opnd,	----
21640	/* RINT_D_MMR6 */	----
21641	FGR64Opnd, FGR64Opnd,	----
21642	/* RINT_S */	----
21643	FGR32Opnd, FGR32Opnd,	----
21644	/* RINT_S_MMR6 */	----
21645	FGR32Opnd, FGR32Opnd,	----
21646	/* ROTR */	----
21647	GPR32Opnd, GPR32Opnd, uimm5,	----
21648	/* ROTRV */	----
21649	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21650	/* ROTRV_MM */	----
21651	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21652	/* ROTR_MM */	----
21653	GPR32Opnd, GPR32Opnd, uimm5,	----
21654	/* ROUND_L_D64 */	----
21655	FGR64Opnd, FGR64Opnd,	----
21656	/* ROUND_L_D_MMR6 */	----
21657	FGR64Opnd, FGR64Opnd,	----
21658	/* ROUND_L_S */	----
21659	FGR64Opnd, FGR32Opnd,	----
21660	/* ROUND_L_S_MMR6 */	----
21661	FGR64Opnd, FGR32Opnd,	----
21662	/* ROUND_W_D32 */	----
21663	FGR32Opnd, AFGR64Opnd,	----
21664	/* ROUND_W_D64 */	----
21665	FGR32Opnd, FGR64Opnd,	----
21666	/* ROUND_W_D_MMR6 */	----
21667	FGR64Opnd, FGR64Opnd,	----
21668	/* ROUND_W_MM */	----
21669	FGR32Opnd, AFGR64Opnd,	----
21670	/* ROUND_W_S */	----
21671	FGR32Opnd, FGR32Opnd,	----
21672	/* ROUND_W_S_MM */	----
21673	FGR32Opnd, FGR32Opnd,	----
21674	/* ROUND_W_S_MMR6 */	----
21675	FGR32Opnd, FGR32Opnd,	----
21676	/* RSQRT_D32 */	----
21677	AFGR64Opnd, AFGR64Opnd,	----
21678	/* RSQRT_D32_MM */	----
21679	AFGR64Opnd, AFGR64Opnd,	----
21680	/* RSQRT_D64 */	----
21681	FGR64Opnd, FGR64Opnd,	----
21682	/* RSQRT_D64_MM */	----
21683	FGR64Opnd, FGR64Opnd,	----
21684	/* RSQRT_S */	----
21685	FGR32Opnd, FGR32Opnd,	----
21686	/* RSQRT_S_MM */	----
21687	FGR32Opnd, FGR32Opnd,	----
21688	/* Restore16 */	----
21689	/* RestoreX16 */	----
21690	/* SAA */	----
21691	GPR64Opnd, GPR64Opnd,	----
21692	/* SAAD */	----
21693	GPR64Opnd, GPR64Opnd,	----
21694	/* SAT_S_B */	----
21695	MSA128BOpnd, MSA128BOpnd, uimm3,	----
21696	/* SAT_S_D */	----
21697	MSA128DOpnd, MSA128DOpnd, uimm6,	----
21698	/* SAT_S_H */	----
21699	MSA128HOpnd, MSA128HOpnd, uimm4,	----
21700	/* SAT_S_W */	----
21701	MSA128WOpnd, MSA128WOpnd, uimm5,	----
21702	/* SAT_U_B */	----
21703	MSA128BOpnd, MSA128BOpnd, uimm3,	----
21704	/* SAT_U_D */	----
21705	MSA128DOpnd, MSA128DOpnd, uimm6,	----
21706	/* SAT_U_H */	----
21707	MSA128HOpnd, MSA128HOpnd, uimm4,	----
21708	/* SAT_U_W */	----
21709	MSA128WOpnd, MSA128WOpnd, uimm5,	----
21710	/* SB */	----
21711	GPR32Opnd, -1, simm16,	----
21712	/* SB16_MM */	----
21713	GPRMM16OpndZero, -1, simm4,	----
21714	/* SB16_MMR6 */	----
21715	GPRMM16OpndZero, -1, simm4,	----
21716	/* SB64 */	----
21717	GPR64Opnd, -1, simm16,	----
21718	/* SBE */	----
21719	GPR32Opnd, -1, simm9,	----
21720	/* SBE_MM */	----
21721	GPR32Opnd, -1, simm9,	----
21722	/* SB_MM */	----
21723	GPR32Opnd, -1, simm16,	----
21724	/* SB_MMR6 */	----
21725	GPR32Opnd, -1, simm16,	----
21726	/* SC */	----
21727	GPR32Opnd, GPR32Opnd, -1, simm16,	----
21728	/* SC64 */	----
21729	GPR32Opnd, GPR32Opnd, -1, simm16,	----
21730	/* SC64_R6 */	----
21731	GPR32Opnd, GPR32Opnd, -1, simm9,	----
21732	/* SCD */	----
21733	GPR64Opnd, GPR64Opnd, -1, simm16,	----
21734	/* SCD_R6 */	----
21735	GPR64Opnd, GPR64Opnd, -1, simm9,	----
21736	/* SCE */	----
21737	GPR32Opnd, GPR32Opnd, -1, simm9,	----
21738	/* SCE_MM */	----
21739	GPR32Opnd, GPR32Opnd, -1, simm9,	----
21740	/* SC_MM */	----
21741	GPR32Opnd, GPR32Opnd, -1, simm12,	----
21742	/* SC_MMR6 */	----
21743	GPR32Opnd, GPR32Opnd, -1, simm9,	----
21744	/* SC_R6 */	----
21745	GPR32Opnd, GPR32Opnd, -1, simm9,	----
21746	/* SD */	----
21747	GPR64Opnd, -1, simm16,	----
21748	/* SDBBP */	----
21749	uimm20,	----
21750	/* SDBBP16_MM */	----
21751	uimm4,	----
21752	/* SDBBP16_MMR6 */	----
21753	uimm4,	----
21754	/* SDBBP_MM */	----
21755	uimm10,	----
21756	/* SDBBP_MMR6 */	----
21757	uimm20,	----
21758	/* SDBBP_R6 */	----
21759	uimm20,	----
21760	/* SDC1 */	----
21761	AFGR64Opnd, -1, simm16,	----
21762	/* SDC164 */	----
21763	FGR64Opnd, -1, simm16,	----
21764	/* SDC1_D64_MMR6 */	----
21765	FGR64Opnd, -1, simm16,	----
21766	/* SDC1_MM_D32 */	----
21767	AFGR64Opnd, -1, simm16,	----
21768	/* SDC1_MM_D64 */	----
21769	FGR64Opnd, -1, simm16,	----
21770	/* SDC2 */	----
21771	COP2Opnd, -1, simm16,	----
21772	/* SDC2_MMR6 */	----
21773	COP2Opnd, GPR32, simm11,	----
21774	/* SDC2_R6 */	----
21775	COP2Opnd, -1, simm11,	----
21776	/* SDC3 */	----
21777	COP3Opnd, -1, simm16,	----
21778	/* SDIV */	----
21779	GPR32Opnd, GPR32Opnd,	----
21780	/* SDIV_MM */	----
21781	GPR32Opnd, GPR32Opnd,	----
21782	/* SDL */	----
21783	GPR64Opnd, -1, simm16,	----
21784	/* SDR */	----
21785	GPR64Opnd, -1, simm16,	----
21786	/* SDXC1 */	----
21787	AFGR64Opnd, -1, -1,	----
21788	/* SDXC164 */	----
21789	FGR64Opnd, -1, -1,	----
21790	/* SEB */	----
21791	GPR32Opnd, GPR32Opnd,	----
21792	/* SEB64 */	----
21793	GPR64Opnd, GPR64Opnd,	----
21794	/* SEB_MM */	----
21795	GPR32Opnd, GPR32Opnd,	----
21796	/* SEH */	----
21797	GPR32Opnd, GPR32Opnd,	----
21798	/* SEH64 */	----
21799	GPR64Opnd, GPR64Opnd,	----
21800	/* SEH_MM */	----
21801	GPR32Opnd, GPR32Opnd,	----
21802	/* SELEQZ */	----
21803	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21804	/* SELEQZ64 */	----
21805	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21806	/* SELEQZ_D */	----
21807	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21808	/* SELEQZ_D_MMR6 */	----
21809	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21810	/* SELEQZ_MMR6 */	----
21811	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21812	/* SELEQZ_S */	----
21813	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21814	/* SELEQZ_S_MMR6 */	----
21815	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21816	/* SELNEZ */	----
21817	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21818	/* SELNEZ64 */	----
21819	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21820	/* SELNEZ_D */	----
21821	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21822	/* SELNEZ_D_MMR6 */	----
21823	FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21824	/* SELNEZ_MMR6 */	----
21825	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21826	/* SELNEZ_S */	----
21827	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21828	/* SELNEZ_S_MMR6 */	----
21829	FGR32Opnd, FGR32Opnd, FGR32Opnd,	----
21830	/* SEL_D */	----
21831	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21832	/* SEL_D_MMR6 */	----
21833	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	----
21834	/* SEL_S */	----
21835	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
21836	/* SEL_S_MMR6 */	----
21837	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	----
21838	/* SEQ */	----
21839	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
21840	/* SEQi */	----
21841	GPR64Opnd, GPR64Opnd, simm10_64,	----
21842	/* SH */	----
21843	GPR32Opnd, -1, simm16,	----
21844	/* SH16_MM */	----
21845	GPRMM16OpndZero, -1, simm4,	----
21846	/* SH16_MMR6 */	----
21847	GPRMM16OpndZero, -1, simm4,	----
21848	/* SH64 */	----
21849	GPR64Opnd, -1, simm16,	----
21850	/* SHE */	----
21851	GPR32Opnd, -1, simm9,	----
21852	/* SHE_MM */	----
21853	GPR32Opnd, -1, simm9,	----
21854	/* SHF_B */	----
21855	MSA128BOpnd, MSA128BOpnd, uimm8,	----
21856	/* SHF_H */	----
21857	MSA128HOpnd, MSA128HOpnd, uimm8,	----
21858	/* SHF_W */	----
21859	MSA128WOpnd, MSA128WOpnd, uimm8,	----
21860	/* SHILO */	----
21861	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	----
21862	/* SHILOV */	----
21863	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	----
21864	/* SHILOV_MM */	----
21865	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	----
21866	/* SHILO_MM */	----
21867	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	----
21868	/* SHLLV_PH */	----
21869	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21870	/* SHLLV_PH_MM */	----
21871	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21872	/* SHLLV_QB */	----
21873	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21874	/* SHLLV_QB_MM */	----
21875	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21876	/* SHLLV_S_PH */	----
21877	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21878	/* SHLLV_S_PH_MM */	----
21879	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21880	/* SHLLV_S_W */	----
21881	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21882	/* SHLLV_S_W_MM */	----
21883	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21884	/* SHLL_PH */	----
21885	DSPROpnd, DSPROpnd, uimm4,	----
21886	/* SHLL_PH_MM */	----
21887	DSPROpnd, DSPROpnd, uimm4,	----
21888	/* SHLL_QB */	----
21889	DSPROpnd, DSPROpnd, uimm3,	----
21890	/* SHLL_QB_MM */	----
21891	DSPROpnd, DSPROpnd, uimm3,	----
21892	/* SHLL_S_PH */	----
21893	DSPROpnd, DSPROpnd, uimm4,	----
21894	/* SHLL_S_PH_MM */	----
21895	DSPROpnd, DSPROpnd, uimm4,	----
21896	/* SHLL_S_W */	----
21897	GPR32Opnd, GPR32Opnd, uimm5,	----
21898	/* SHLL_S_W_MM */	----
21899	GPR32Opnd, GPR32Opnd, uimm5,	----
21900	/* SHRAV_PH */	----
21901	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21902	/* SHRAV_PH_MM */	----
21903	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21904	/* SHRAV_QB */	----
21905	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21906	/* SHRAV_QB_MMR2 */	----
21907	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21908	/* SHRAV_R_PH */	----
21909	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21910	/* SHRAV_R_PH_MM */	----
21911	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21912	/* SHRAV_R_QB */	----
21913	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21914	/* SHRAV_R_QB_MMR2 */	----
21915	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21916	/* SHRAV_R_W */	----
21917	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21918	/* SHRAV_R_W_MM */	----
21919	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
21920	/* SHRA_PH */	----
21921	DSPROpnd, DSPROpnd, uimm4,	----
21922	/* SHRA_PH_MM */	----
21923	DSPROpnd, DSPROpnd, uimm4,	----
21924	/* SHRA_QB */	----
21925	DSPROpnd, DSPROpnd, uimm3,	----
21926	/* SHRA_QB_MMR2 */	----
21927	DSPROpnd, DSPROpnd, uimm3,	----
21928	/* SHRA_R_PH */	----
21929	DSPROpnd, DSPROpnd, uimm4,	----
21930	/* SHRA_R_PH_MM */	----
21931	DSPROpnd, DSPROpnd, uimm4,	----
21932	/* SHRA_R_QB */	----
21933	DSPROpnd, DSPROpnd, uimm3,	----
21934	/* SHRA_R_QB_MMR2 */	----
21935	DSPROpnd, DSPROpnd, uimm3,	----
21936	/* SHRA_R_W */	----
21937	GPR32Opnd, GPR32Opnd, uimm5,	----
21938	/* SHRA_R_W_MM */	----
21939	GPR32Opnd, GPR32Opnd, uimm5,	----
21940	/* SHRLV_PH */	----
21941	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21942	/* SHRLV_PH_MMR2 */	----
21943	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21944	/* SHRLV_QB */	----
21945	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21946	/* SHRLV_QB_MM */	----
21947	DSPROpnd, DSPROpnd, GPR32Opnd,	----
21948	/* SHRL_PH */	----
21949	DSPROpnd, DSPROpnd, uimm4,	----
21950	/* SHRL_PH_MMR2 */	----
21951	DSPROpnd, DSPROpnd, uimm4,	----
21952	/* SHRL_QB */	----
21953	DSPROpnd, DSPROpnd, uimm3,	----
21954	/* SHRL_QB_MM */	----
21955	DSPROpnd, DSPROpnd, uimm3,	----
21956	/* SH_MM */	----
21957	GPR32Opnd, -1, simm16,	----
21958	/* SH_MMR6 */	----
21959	GPR32Opnd, -1, simm16,	----
21960	/* SIGRIE */	----
21961	uimm16,	----
21962	/* SIGRIE_MMR6 */	----
21963	uimm16,	----
21964	/* SLDI_B */	----
21965	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,	----
21966	/* SLDI_D */	----
21967	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,	----
21968	/* SLDI_H */	----
21969	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,	----
21970	/* SLDI_W */	----
21971	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,	----
21972	/* SLD_B */	----
21973	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	----
21974	/* SLD_D */	----
21975	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	----
21976	/* SLD_H */	----
21977	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	----
21978	/* SLD_W */	----
21979	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	----
21980	/* SLL */	----
21981	GPR32Opnd, GPR32Opnd, uimm5,	----
21982	/* SLL16_MM */	----
21983	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	----
21984	/* SLL16_MMR6 */	----
21985	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	----
21986	/* SLL64_32 */	----
21987	GPR64, GPR32,	----
21988	/* SLL64_64 */	----
21989	GPR64, GPR64,	----
21990	/* SLLI_B */	----
21991	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
21992	/* SLLI_D */	----
21993	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
21994	/* SLLI_H */	----
21995	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
21996	/* SLLI_W */	----
21997	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
21998	/* SLLV */	----
21999	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22000	/* SLLV_MM */	----
22001	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22002	/* SLL_B */	----
22003	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22004	/* SLL_D */	----
22005	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22006	/* SLL_H */	----
22007	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22008	/* SLL_MM */	----
22009	GPR32Opnd, GPR32Opnd, uimm5,	----
22010	/* SLL_MMR6 */	----
22011	GPR32Opnd, GPR32Opnd, uimm5,	----
22012	/* SLL_W */	----
22013	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22014	/* SLT */	----
22015	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22016	/* SLT64 */	----
22017	GPR32Opnd, GPR64Opnd, GPR64Opnd,	----
22018	/* SLT_MM */	----
22019	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22020	/* SLTi */	----
22021	GPR32Opnd, GPR32Opnd, simm16,	----
22022	/* SLTi64 */	----
22023	GPR32Opnd, GPR64Opnd, simm16_64,	----
22024	/* SLTi_MM */	----
22025	GPR32Opnd, GPR32Opnd, simm16,	----
22026	/* SLTiu */	----
22027	GPR32Opnd, GPR32Opnd, simm16,	----
22028	/* SLTiu64 */	----
22029	GPR32Opnd, GPR64Opnd, simm16_64,	----
22030	/* SLTiu_MM */	----
22031	GPR32Opnd, GPR32Opnd, simm16,	----
22032	/* SLTu */	----
22033	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22034	/* SLTu64 */	----
22035	GPR32Opnd, GPR64Opnd, GPR64Opnd,	----
22036	/* SLTu_MM */	----
22037	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22038	/* SNE */	----
22039	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
22040	/* SNEi */	----
22041	GPR64Opnd, GPR64Opnd, simm10_64,	----
22042	/* SPLATI_B */	----
22043	MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,	----
22044	/* SPLATI_D */	----
22045	MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,	----
22046	/* SPLATI_H */	----
22047	MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,	----
22048	/* SPLATI_W */	----
22049	MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,	----
22050	/* SPLAT_B */	----
22051	MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	----
22052	/* SPLAT_D */	----
22053	MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	----
22054	/* SPLAT_H */	----
22055	MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	----
22056	/* SPLAT_W */	----
22057	MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	----
22058	/* SRA */	----
22059	GPR32Opnd, GPR32Opnd, uimm5,	----
22060	/* SRAI_B */	----
22061	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
22062	/* SRAI_D */	----
22063	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
22064	/* SRAI_H */	----
22065	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
22066	/* SRAI_W */	----
22067	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
22068	/* SRARI_B */	----
22069	MSA128BOpnd, MSA128BOpnd, uimm3,	----
22070	/* SRARI_D */	----
22071	MSA128DOpnd, MSA128DOpnd, uimm6,	----
22072	/* SRARI_H */	----
22073	MSA128HOpnd, MSA128HOpnd, uimm4,	----
22074	/* SRARI_W */	----
22075	MSA128WOpnd, MSA128WOpnd, uimm5,	----
22076	/* SRAR_B */	----
22077	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22078	/* SRAR_D */	----
22079	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22080	/* SRAR_H */	----
22081	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22082	/* SRAR_W */	----
22083	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22084	/* SRAV */	----
22085	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22086	/* SRAV_MM */	----
22087	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22088	/* SRA_B */	----
22089	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22090	/* SRA_D */	----
22091	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22092	/* SRA_H */	----
22093	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22094	/* SRA_MM */	----
22095	GPR32Opnd, GPR32Opnd, uimm5,	----
22096	/* SRA_W */	----
22097	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22098	/* SRL */	----
22099	GPR32Opnd, GPR32Opnd, uimm5,	----
22100	/* SRL16_MM */	----
22101	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	----
22102	/* SRL16_MMR6 */	----
22103	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	----
22104	/* SRLI_B */	----
22105	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	----
22106	/* SRLI_D */	----
22107	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	----
22108	/* SRLI_H */	----
22109	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	----
22110	/* SRLI_W */	----
22111	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
22112	/* SRLRI_B */	----
22113	MSA128BOpnd, MSA128BOpnd, uimm3,	----
22114	/* SRLRI_D */	----
22115	MSA128DOpnd, MSA128DOpnd, uimm6,	----
22116	/* SRLRI_H */	----
22117	MSA128HOpnd, MSA128HOpnd, uimm4,	----
22118	/* SRLRI_W */	----
22119	MSA128WOpnd, MSA128WOpnd, uimm5,	----
22120	/* SRLR_B */	----
22121	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22122	/* SRLR_D */	----
22123	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22124	/* SRLR_H */	----
22125	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22126	/* SRLR_W */	----
22127	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22128	/* SRLV */	----
22129	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22130	/* SRLV_MM */	----
22131	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22132	/* SRL_B */	----
22133	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22134	/* SRL_D */	----
22135	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22136	/* SRL_H */	----
22137	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22138	/* SRL_MM */	----
22139	GPR32Opnd, GPR32Opnd, uimm5,	----
22140	/* SRL_W */	----
22141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22142	/* SSNOP */	----
22143	/* SSNOP_MM */	----
22144	/* SSNOP_MMR6 */	----
22145	/* ST_B */	----
22146	MSA128BOpnd, -1, simm10,	----
22147	/* ST_D */	----
22148	MSA128DOpnd, -1, simm10_lsl3,	----
22149	/* ST_H */	----
22150	MSA128HOpnd, -1, simm10_lsl1,	----
22151	/* ST_W */	----
22152	MSA128WOpnd, -1, simm10_lsl2,	----
22153	/* SUB */	----
22154	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22155	/* SUBQH_PH */	----
22156	DSPROpnd, DSPROpnd, DSPROpnd,	----
22157	/* SUBQH_PH_MMR2 */	----
22158	DSPROpnd, DSPROpnd, DSPROpnd,	----
22159	/* SUBQH_R_PH */	----
22160	DSPROpnd, DSPROpnd, DSPROpnd,	----
22161	/* SUBQH_R_PH_MMR2 */	----
22162	DSPROpnd, DSPROpnd, DSPROpnd,	----
22163	/* SUBQH_R_W */	----
22164	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22165	/* SUBQH_R_W_MMR2 */	----
22166	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22167	/* SUBQH_W */	----
22168	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22169	/* SUBQH_W_MMR2 */	----
22170	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22171	/* SUBQ_PH */	----
22172	DSPROpnd, DSPROpnd, DSPROpnd,	----
22173	/* SUBQ_PH_MM */	----
22174	DSPROpnd, DSPROpnd, DSPROpnd,	----
22175	/* SUBQ_S_PH */	----
22176	DSPROpnd, DSPROpnd, DSPROpnd,	----
22177	/* SUBQ_S_PH_MM */	----
22178	DSPROpnd, DSPROpnd, DSPROpnd,	----
22179	/* SUBQ_S_W */	----
22180	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22181	/* SUBQ_S_W_MM */	----
22182	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22183	/* SUBSUS_U_B */	----
22184	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22185	/* SUBSUS_U_D */	----
22186	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22187	/* SUBSUS_U_H */	----
22188	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22189	/* SUBSUS_U_W */	----
22190	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22191	/* SUBSUU_S_B */	----
22192	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22193	/* SUBSUU_S_D */	----
22194	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22195	/* SUBSUU_S_H */	----
22196	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22197	/* SUBSUU_S_W */	----
22198	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22199	/* SUBS_S_B */	----
22200	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22201	/* SUBS_S_D */	----
22202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22203	/* SUBS_S_H */	----
22204	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22205	/* SUBS_S_W */	----
22206	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22207	/* SUBS_U_B */	----
22208	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22209	/* SUBS_U_D */	----
22210	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22211	/* SUBS_U_H */	----
22212	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22213	/* SUBS_U_W */	----
22214	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22215	/* SUBU16_MM */	----
22216	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
22217	/* SUBU16_MMR6 */	----
22218	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
22219	/* SUBUH_QB */	----
22220	DSPROpnd, DSPROpnd, DSPROpnd,	----
22221	/* SUBUH_QB_MMR2 */	----
22222	DSPROpnd, DSPROpnd, DSPROpnd,	----
22223	/* SUBUH_R_QB */	----
22224	DSPROpnd, DSPROpnd, DSPROpnd,	----
22225	/* SUBUH_R_QB_MMR2 */	----
22226	DSPROpnd, DSPROpnd, DSPROpnd,	----
22227	/* SUBU_MMR6 */	----
22228	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22229	/* SUBU_PH */	----
22230	DSPROpnd, DSPROpnd, DSPROpnd,	----
22231	/* SUBU_PH_MMR2 */	----
22232	DSPROpnd, DSPROpnd, DSPROpnd,	----
22233	/* SUBU_QB */	----
22234	DSPROpnd, DSPROpnd, DSPROpnd,	----
22235	/* SUBU_QB_MM */	----
22236	DSPROpnd, DSPROpnd, DSPROpnd,	----
22237	/* SUBU_S_PH */	----
22238	DSPROpnd, DSPROpnd, DSPROpnd,	----
22239	/* SUBU_S_PH_MMR2 */	----
22240	DSPROpnd, DSPROpnd, DSPROpnd,	----
22241	/* SUBU_S_QB */	----
22242	DSPROpnd, DSPROpnd, DSPROpnd,	----
22243	/* SUBU_S_QB_MM */	----
22244	DSPROpnd, DSPROpnd, DSPROpnd,	----
22245	/* SUBVI_B */	----
22246	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	----
22247	/* SUBVI_D */	----
22248	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	----
22249	/* SUBVI_H */	----
22250	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	----
22251	/* SUBVI_W */	----
22252	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	----
22253	/* SUBV_B */	----
22254	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22255	/* SUBV_D */	----
22256	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22257	/* SUBV_H */	----
22258	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22259	/* SUBV_W */	----
22260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22261	/* SUB_MM */	----
22262	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22263	/* SUB_MMR6 */	----
22264	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22265	/* SUBu */	----
22266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22267	/* SUBu_MM */	----
22268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22269	/* SUXC1 */	----
22270	AFGR64Opnd, -1, -1,	----
22271	/* SUXC164 */	----
22272	FGR64Opnd, -1, -1,	----
22273	/* SUXC1_MM */	----
22274	FGR64Opnd, -1, -1,	----
22275	/* SW */	----
22276	GPR32Opnd, -1, simm16,	----
22277	/* SW16_MM */	----
22278	GPRMM16OpndZero, -1, simm4,	----
22279	/* SW16_MMR6 */	----
22280	GPRMM16OpndZero, -1, simm4,	----
22281	/* SW64 */	----
22282	GPR64Opnd, -1, simm16,	----
22283	/* SWC1 */	----
22284	FGR32Opnd, -1, simm16,	----
22285	/* SWC1_MM */	----
22286	FGR32Opnd, -1, simm16,	----
22287	/* SWC2 */	----
22288	COP2Opnd, -1, simm16,	----
22289	/* SWC2_MMR6 */	----
22290	COP2Opnd, GPR32, simm11,	----
22291	/* SWC2_R6 */	----
22292	COP2Opnd, -1, simm11,	----
22293	/* SWC3 */	----
22294	COP3Opnd, -1, simm16,	----
22295	/* SWDSP */	----
22296	DSPROpnd, -1, simm16,	----
22297	/* SWDSP_MM */	----
22298	DSPROpnd, -1, simm16,	----
22299	/* SWE */	----
22300	GPR32Opnd, -1, simm9,	----
22301	/* SWE_MM */	----
22302	GPR32Opnd, -1, simm9,	----
22303	/* SWL */	----
22304	GPR32Opnd, -1, simm16,	----
22305	/* SWL64 */	----
22306	GPR64Opnd, -1, simm16,	----
22307	/* SWLE */	----
22308	GPR32Opnd, -1, simm9,	----
22309	/* SWLE_MM */	----
22310	GPR32Opnd, -1, simm9,	----
22311	/* SWL_MM */	----
22312	GPR32Opnd, -1, simm12,	----
22313	/* SWM16_MM */	----
22314	reglist16, -1, uimm8,	----
22315	/* SWM16_MMR6 */	----
22316	reglist16, -1, uimm8,	----
22317	/* SWM32_MM */	----
22318	reglist, -1, simm12,	----
22319	/* SWP_MM */	----
22320	GPR32Opnd, GPR32Opnd, -1, simm12,	----
22321	/* SWR */	----
22322	GPR32Opnd, -1, simm16,	----
22323	/* SWR64 */	----
22324	GPR64Opnd, -1, simm16,	----
22325	/* SWRE */	----
22326	GPR32Opnd, -1, simm9,	----
22327	/* SWRE_MM */	----
22328	GPR32Opnd, -1, simm9,	----
22329	/* SWR_MM */	----
22330	GPR32Opnd, -1, simm12,	----
22331	/* SWSP_MM */	----
22332	GPR32Opnd, -1, simm5,	----
22333	/* SWSP_MMR6 */	----
22334	GPR32Opnd, -1, simm5,	----
22335	/* SWXC1 */	----
22336	FGR32Opnd, -1, -1,	----
22337	/* SWXC1_MM */	----
22338	FGR32Opnd, -1, -1,	----
22339	/* SW_MM */	----
22340	GPR32Opnd, -1, simm16,	----
22341	/* SW_MMR6 */	----
22342	GPR32Opnd, -1, simm16,	----
22343	/* SYNC */	----
22344	uimm5,	----
22345	/* SYNCI */	----
22346	-1, simm16,	----
22347	/* SYNCI_MM */	----
22348	-1, simm16,	----
22349	/* SYNCI_MMR6 */	----
22350	-1, simm16,	----
22351	/* SYNC_MM */	----
22352	uimm5,	----
22353	/* SYNC_MMR6 */	----
22354	uimm5,	----
22355	/* SYSCALL */	----
22356	uimm20,	----
22357	/* SYSCALL_MM */	----
22358	uimm10,	----
22359	/* Save16 */	----
22360	/* SaveX16 */	----
22361	/* SbRxRyOffMemX16 */	----
22362	CPU16Regs, CPU16Regs, simm16,	----
22363	/* SebRx16 */	----
22364	CPU16Regs, CPU16Regs,	----
22365	/* SehRx16 */	----
22366	CPU16Regs, CPU16Regs,	----
22367	/* ShRxRyOffMemX16 */	----
22368	CPU16Regs, CPU16Regs, simm16,	----
22369	/* SllX16 */	----
22370	CPU16Regs, CPU16Regs, uimm5,	----
22371	/* SllvRxRy16 */	----
22372	CPU16Regs, CPU16Regs, CPU16Regs,	----
22373	/* SltRxRy16 */	----
22374	CPU16Regs, CPU16Regs,	----
22375	/* SltiRxImm16 */	----
22376	CPU16Regs, simm16,	----
22377	/* SltiRxImmX16 */	----
22378	CPU16Regs, simm16,	----
22379	/* SltiuRxImm16 */	----
22380	CPU16Regs, simm16,	----
22381	/* SltiuRxImmX16 */	----
22382	CPU16Regs, simm16,	----
22383	/* SltuRxRy16 */	----
22384	CPU16Regs, CPU16Regs,	----
22385	/* SraX16 */	----
22386	CPU16Regs, CPU16Regs, uimm5,	----
22387	/* SravRxRy16 */	----
22388	CPU16Regs, CPU16Regs, CPU16Regs,	----
22389	/* SrlX16 */	----
22390	CPU16Regs, CPU16Regs, uimm5,	----
22391	/* SrlvRxRy16 */	----
22392	CPU16Regs, CPU16Regs, CPU16Regs,	----
22393	/* SubuRxRyRz16 */	----
22394	CPU16Regs, CPU16Regs, CPU16Regs,	----
22395	/* SwRxRyOffMemX16 */	----
22396	CPU16Regs, CPU16Regs, simm16,	----
22397	/* SwRxSpImmX16 */	----
22398	CPU16Regs, CPU16RegsPlusSP, simm16,	----
22399	/* TEQ */	----
22400	GPR32Opnd, GPR32Opnd, uimm10,	----
22401	/* TEQI */	----
22402	GPR32Opnd, simm16,	----
22403	/* TEQI_MM */	----
22404	GPR32Opnd, simm16,	----
22405	/* TEQ_MM */	----
22406	GPR32Opnd, GPR32Opnd, uimm4,	----
22407	/* TGE */	----
22408	GPR32Opnd, GPR32Opnd, uimm10,	----
22409	/* TGEI */	----
22410	GPR32Opnd, simm16,	----
22411	/* TGEIU */	----
22412	GPR32Opnd, simm16,	----
22413	/* TGEIU_MM */	----
22414	GPR32Opnd, simm16,	----
22415	/* TGEI_MM */	----
22416	GPR32Opnd, simm16,	----
22417	/* TGEU */	----
22418	GPR32Opnd, GPR32Opnd, uimm10,	----
22419	/* TGEU_MM */	----
22420	GPR32Opnd, GPR32Opnd, uimm4,	----
22421	/* TGE_MM */	----
22422	GPR32Opnd, GPR32Opnd, uimm4,	----
22423	/* TLBGINV */	----
22424	/* TLBGINVF */	----
22425	/* TLBGINVF_MM */	----
22426	/* TLBGINV_MM */	----
22427	/* TLBGP */	----
22428	/* TLBGP_MM */	----
22429	/* TLBGR */	----
22430	/* TLBGR_MM */	----
22431	/* TLBGWI */	----
22432	/* TLBGWI_MM */	----
22433	/* TLBGWR */	----
22434	/* TLBGWR_MM */	----
22435	/* TLBINV */	----
22436	/* TLBINVF */	----
22437	/* TLBINVF_MMR6 */	----
22438	/* TLBINV_MMR6 */	----
22439	/* TLBP */	----
22440	/* TLBP_MM */	----
22441	/* TLBR */	----
22442	/* TLBR_MM */	----
22443	/* TLBWI */	----
22444	/* TLBWI_MM */	----
22445	/* TLBWR */	----
22446	/* TLBWR_MM */	----
22447	/* TLT */	----
22448	GPR32Opnd, GPR32Opnd, uimm10,	----
22449	/* TLTI */	----
22450	GPR32Opnd, simm16,	----
22451	/* TLTIU_MM */	----
22452	GPR32Opnd, simm16,	----
22453	/* TLTI_MM */	----
22454	GPR32Opnd, simm16,	----
22455	/* TLTU */	----
22456	GPR32Opnd, GPR32Opnd, uimm10,	----
22457	/* TLTU_MM */	----
22458	GPR32Opnd, GPR32Opnd, uimm4,	----
22459	/* TLT_MM */	----
22460	GPR32Opnd, GPR32Opnd, uimm4,	----
22461	/* TNE */	----
22462	GPR32Opnd, GPR32Opnd, uimm10,	----
22463	/* TNEI */	----
22464	GPR32Opnd, simm16,	----
22465	/* TNEI_MM */	----
22466	GPR32Opnd, simm16,	----
22467	/* TNE_MM */	----
22468	GPR32Opnd, GPR32Opnd, uimm4,	----
22469	/* TRUNC_L_D64 */	----
22470	FGR64Opnd, FGR64Opnd,	----
22471	/* TRUNC_L_D_MMR6 */	----
22472	FGR64Opnd, FGR64Opnd,	----
22473	/* TRUNC_L_S */	----
22474	FGR64Opnd, FGR32Opnd,	----
22475	/* TRUNC_L_S_MMR6 */	----
22476	FGR64Opnd, FGR32Opnd,	----
22477	/* TRUNC_W_D32 */	----
22478	FGR32Opnd, AFGR64Opnd,	----
22479	/* TRUNC_W_D64 */	----
22480	FGR32Opnd, FGR64Opnd,	----
22481	/* TRUNC_W_D_MMR6 */	----
22482	FGR32Opnd, FGR64Opnd,	----
22483	/* TRUNC_W_MM */	----
22484	FGR32Opnd, AFGR64Opnd,	----
22485	/* TRUNC_W_S */	----
22486	FGR32Opnd, FGR32Opnd,	----
22487	/* TRUNC_W_S_MM */	----
22488	FGR32Opnd, FGR32Opnd,	----
22489	/* TRUNC_W_S_MMR6 */	----
22490	FGR32Opnd, FGR32Opnd,	----
22491	/* TTLTIU */	----
22492	GPR32Opnd, simm16,	----
22493	/* UDIV */	----
22494	GPR32Opnd, GPR32Opnd,	----
22495	/* UDIV_MM */	----
22496	GPR32Opnd, GPR32Opnd,	----
22497	/* V3MULU */	----
22498	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
22499	/* VMM0 */	----
22500	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
22501	/* VMULU */	----
22502	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
22503	/* VSHF_B */	----
22504	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22505	/* VSHF_D */	----
22506	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	----
22507	/* VSHF_H */	----
22508	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	----
22509	/* VSHF_W */	----
22510	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	----
22511	/* WAIT */	----
22512	/* WAIT_MM */	----
22513	uimm10,	----
22514	/* WAIT_MMR6 */	----
22515	uimm10,	----
22516	/* WRDSP */	----
22517	GPR32Opnd, uimm10,	----
22518	/* WRDSP_MM */	----
22519	GPR32Opnd, uimm7,	----
22520	/* WRPGPR_MMR6 */	----
22521	GPR32Opnd, GPR32Opnd,	----
22522	/* WSBH */	----
22523	GPR32Opnd, GPR32Opnd,	----
22524	/* WSBH_MM */	----
22525	GPR32Opnd, GPR32Opnd,	----
22526	/* WSBH_MMR6 */	----
22527	GPR32Opnd, GPR32Opnd,	----
22528	/* XOR */	----
22529	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22530	/* XOR16_MM */	----
22531	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
22532	/* XOR16_MMR6 */	----
22533	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	----
22534	/* XOR64 */	----
22535	GPR64Opnd, GPR64Opnd, GPR64Opnd,	----
22536	/* XORI_B */	----
22537	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	----
22538	/* XORI_MMR6 */	----
22539	GPR32Opnd, GPR32Opnd, uimm16,	----
22540	/* XOR_MM */	----
22541	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22542	/* XOR_MMR6 */	----
22543	GPR32Opnd, GPR32Opnd, GPR32Opnd,	----
22544	/* XOR_V */	----
22545	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	----
22546	/* XORi */	----
22547	GPR32Opnd, GPR32Opnd, uimm16,	----
22548	/* XORi64 */	----
22549	GPR64Opnd, GPR64Opnd, uimm16_64,	----
22550	/* XORi_MM */	----
22551	GPR32Opnd, GPR32Opnd, uimm16,	----
22552	/* XorRxRxRy16 */	----
22553	CPU16Regs, CPU16Regs, CPU16Regs,	----
22554	/* YIELD */	----
22555	GPR32Opnd, GPR32Opnd,	----
22556	};	----
22557	return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];	----
22558	}	----
22559	} // end namespace Mips	----
22560	} // end namespace llvm	----
22561	#endif // GET_INSTRINFO_OPERAND_TYPE	----
22562		----
22563	#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE	----
22564	#undef GET_INSTRINFO_MEM_OPERAND_SIZE	----
22565	namespace llvm {	----
22566	namespace Mips {	----
22567	LLVM_READONLY	----
22568	static int getMemOperandSize(int OpType) {	----
22569	switch (OpType) {	----
22570	default: return 0;	----
22571	}	----
22572	}	----
22573	} // end namespace Mips	----
22574	} // end namespace llvm	----
22575	#endif // GET_INSTRINFO_MEM_OPERAND_SIZE	----
22576		----
22577	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	----
22578	#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	----
22579	namespace llvm {	----
22580	namespace Mips {	----
22581	LLVM_READONLY static unsigned	----
22582	getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {	----
22583	return LogicalOpIdx;	----
22584	}	----
22585	LLVM_READONLY static inline unsigned	----
22586	getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {	----
22587	auto S = 0U;	----
22588	for (auto i = 0U; i < LogicalOpIdx; ++i)	----
22589	S += getLogicalOperandSize(Opcode, i);	----
22590	return S;	----
22591	}	----
22592	} // end namespace Mips	----
22593	} // end namespace llvm	----
22594	#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	----
22595		----
22596	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	----
22597	#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	----
22598	namespace llvm {	----
22599	namespace Mips {	----
22600	LLVM_READONLY static int	----
22601	getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {	----
22602	return -1;	----
22603	}	----
22604	} // end namespace Mips	----
22605	} // end namespace llvm	----
22606	#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	----
22607		----
22608	#ifdef GET_INSTRINFO_MC_HELPER_DECLS	----
22609	#undef GET_INSTRINFO_MC_HELPER_DECLS	----
22610		----
22611	namespace llvm {	----
22612	class MCInst;	----
22613	class FeatureBitset;	----
22614		----
22615	namespace Mips_MC {	----
22616		----
22617	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);	----
22618		----
22619	} // end namespace Mips_MC	----
22620	} // end namespace llvm	----
22621		----
22622	#endif // GET_INSTRINFO_MC_HELPER_DECLS	----
22623		----
22624	#ifdef GET_INSTRINFO_MC_HELPERS	----
22625	#undef GET_INSTRINFO_MC_HELPERS	----
22626		----
22627	namespace llvm {	----
22628	namespace Mips_MC {	----
22629		----
22630	} // end namespace Mips_MC	----
22631	} // end namespace llvm	----
22632		----
22633	#endif // GET_GENISTRINFO_MC_HELPERS	----
22634		----
22635	#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)	----
22636	#define GET_COMPUTE_FEATURES	----
22637	#endif	----
22638	#ifdef GET_COMPUTE_FEATURES	----
22639	#undef GET_COMPUTE_FEATURES	----
22640	namespace llvm {	----
22641	namespace Mips_MC {	----
22642		----
22643	// Bits for subtarget features that participate in instruction matching.	----
22644	enum SubtargetFeatureBits : uint8_t {	----
22645	Feature_HasMips2Bit = 11,	----
22646	Feature_HasMips3_32Bit = 14,	----
22647	Feature_HasMips3_32r2Bit = 15,	----
22648	Feature_HasMips3Bit = 12,	----
22649	Feature_NotMips3Bit = 47,	----
22650	Feature_HasMips4_32Bit = 16,	----
22651	Feature_NotMips4_32Bit = 48,	----
22652	Feature_HasMips4_32r2Bit = 17,	----
22653	Feature_HasMips5_32r2Bit = 18,	----
22654	Feature_HasMips32Bit = 19,	----
22655	Feature_HasMips32r2Bit = 20,	----
22656	Feature_HasMips32r5Bit = 21,	----
22657	Feature_HasMips32r6Bit = 22,	----
22658	Feature_NotMips32r6Bit = 49,	----
22659	Feature_IsGP64bitBit = 33,	----
22660	Feature_IsGP32bitBit = 32,	----
22661	Feature_IsPTR64bitBit = 37,	----
22662	Feature_IsPTR32bitBit = 36,	----
22663	Feature_HasMips64Bit = 23,	----
22664	Feature_NotMips64Bit = 50,	----
22665	Feature_HasMips64r2Bit = 24,	----
22666	Feature_HasMips64r5Bit = 25,	----
22667	Feature_HasMips64r6Bit = 26,	----
22668	Feature_NotMips64r6Bit = 51,	----
22669	Feature_InMips16ModeBit = 30,	----
22670	Feature_NotInMips16ModeBit = 46,	----
22671	Feature_HasCnMipsBit = 1,	----
22672	Feature_NotCnMipsBit = 42,	----
22673	Feature_HasCnMipsPBit = 2,	----
22674	Feature_NotCnMipsPBit = 43,	----
22675	Feature_IsSym32Bit = 39,	----
22676	Feature_IsSym64Bit = 40,	----
22677	Feature_HasStdEncBit = 27,	----
22678	Feature_InMicroMipsBit = 29,	----
22679	Feature_NotInMicroMipsBit = 45,	----
22680	Feature_HasEVABit = 6,	----
22681	Feature_HasMSABit = 8,	----
22682	Feature_HasMadd4Bit = 10,	----
22683	Feature_HasMTBit = 9,	----
22684	Feature_UseIndirectJumpsHazardBit = 52,	----
22685	Feature_NoIndirectJumpGuardsBit = 41,	----
22686	Feature_HasCRCBit = 0,	----
22687	Feature_HasVirtBit = 28,	----
22688	Feature_HasGINVBit = 7,	----
22689	Feature_IsFP64bitBit = 31,	----
22690	Feature_NotFP64bitBit = 44,	----
22691	Feature_IsSingleFloatBit = 38,	----
22692	Feature_IsNotSingleFloatBit = 34,	----
22693	Feature_IsNotSoftFloatBit = 35,	----
22694	Feature_HasMips3DBit = 13,	----
22695	Feature_HasDSPBit = 3,	----
22696	Feature_HasDSPR2Bit = 4,	----
22697	Feature_HasDSPR3Bit = 5,	----
22698	};	----
22699		----
22700	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {	0
22701	FeatureBitset Features;	0
22702	if (FB[Mips::FeatureMips2])	0
22703	Features.set(Feature_HasMips2Bit);	0
22704	if (FB[Mips::FeatureMips3_32])	0
22705	Features.set(Feature_HasMips3_32Bit);	0
22706	if (FB[Mips::FeatureMips3_32r2])	0
22707	Features.set(Feature_HasMips3_32r2Bit);	0
22708	if (FB[Mips::FeatureMips3])	0
22709	Features.set(Feature_HasMips3Bit);	0
22710	if (!FB[Mips::FeatureMips3])	0
22711	Features.set(Feature_NotMips3Bit);	0
22712	if (FB[Mips::FeatureMips4_32])	0
22713	Features.set(Feature_HasMips4_32Bit);	0
22714	if (!FB[Mips::FeatureMips4_32])	0
22715	Features.set(Feature_NotMips4_32Bit);	0
22716	if (FB[Mips::FeatureMips4_32r2])	0
22717	Features.set(Feature_HasMips4_32r2Bit);	0
22718	if (FB[Mips::FeatureMips5_32r2])	0
22719	Features.set(Feature_HasMips5_32r2Bit);	0
22720	if (FB[Mips::FeatureMips32])	0
22721	Features.set(Feature_HasMips32Bit);	0
22722	if (FB[Mips::FeatureMips32r2])	0
22723	Features.set(Feature_HasMips32r2Bit);	0
22724	if (FB[Mips::FeatureMips32r5])	0
22725	Features.set(Feature_HasMips32r5Bit);	0
22726	if (FB[Mips::FeatureMips32r6])	0
22727	Features.set(Feature_HasMips32r6Bit);	0
22728	if (!FB[Mips::FeatureMips32r6])	0
22729	Features.set(Feature_NotMips32r6Bit);	0
22730	if (FB[Mips::FeatureGP64Bit])	0
22731	Features.set(Feature_IsGP64bitBit);	0
22732	if (!FB[Mips::FeatureGP64Bit])	0
22733	Features.set(Feature_IsGP32bitBit);	0
22734	if (FB[Mips::FeaturePTR64Bit])	0
22735	Features.set(Feature_IsPTR64bitBit);	0
22736	if (!FB[Mips::FeaturePTR64Bit])	0
22737	Features.set(Feature_IsPTR32bitBit);	0
22738	if (FB[Mips::FeatureMips64])	0
22739	Features.set(Feature_HasMips64Bit);	0
22740	if (!FB[Mips::FeatureMips64])	0
22741	Features.set(Feature_NotMips64Bit);	0
22742	if (FB[Mips::FeatureMips64r2])	0
22743	Features.set(Feature_HasMips64r2Bit);	0
22744	if (FB[Mips::FeatureMips64r5])	0
22745	Features.set(Feature_HasMips64r5Bit);	0
22746	if (FB[Mips::FeatureMips64r6])	0
22747	Features.set(Feature_HasMips64r6Bit);	0
22748	if (!FB[Mips::FeatureMips64r6])	0
22749	Features.set(Feature_NotMips64r6Bit);	0
22750	if (FB[Mips::FeatureMips16])	0
22751	Features.set(Feature_InMips16ModeBit);	0
22752	if (!FB[Mips::FeatureMips16])	0
22753	Features.set(Feature_NotInMips16ModeBit);	0
22754	if (FB[Mips::FeatureCnMips])	0
22755	Features.set(Feature_HasCnMipsBit);	0
22756	if (!FB[Mips::FeatureCnMips])	0
22757	Features.set(Feature_NotCnMipsBit);	0
22758	if (FB[Mips::FeatureCnMipsP])	0
22759	Features.set(Feature_HasCnMipsPBit);	0
22760	if (!FB[Mips::FeatureCnMipsP])	0
22761	Features.set(Feature_NotCnMipsPBit);	0
22762	if (FB[Mips::FeatureSym32])	0
22763	Features.set(Feature_IsSym32Bit);	0
22764	if (!FB[Mips::FeatureSym32])	0
22765	Features.set(Feature_IsSym64Bit);	0
22766	if (!FB[Mips::FeatureMips16])	0
22767	Features.set(Feature_HasStdEncBit);	0
22768	if (FB[Mips::FeatureMicroMips])	0
22769	Features.set(Feature_InMicroMipsBit);	0
22770	if (!FB[Mips::FeatureMicroMips])	0
22771	Features.set(Feature_NotInMicroMipsBit);	0
22772	if (FB[Mips::FeatureEVA])	0
22773	Features.set(Feature_HasEVABit);	0
22774	if (FB[Mips::FeatureMSA])	0
22775	Features.set(Feature_HasMSABit);	0
22776	if (!FB[Mips::FeatureNoMadd4])	0
22777	Features.set(Feature_HasMadd4Bit);	0
22778	if (FB[Mips::FeatureMT])	0
22779	Features.set(Feature_HasMTBit);	0
22780	if (FB[Mips::FeatureUseIndirectJumpsHazard])	0
22781	Features.set(Feature_UseIndirectJumpsHazardBit);	0
22782	if (!FB[Mips::FeatureUseIndirectJumpsHazard])	0
22783	Features.set(Feature_NoIndirectJumpGuardsBit);	0
22784	if (FB[Mips::FeatureCRC])	0
22785	Features.set(Feature_HasCRCBit);	0
22786	if (FB[Mips::FeatureVirt])	0
22787	Features.set(Feature_HasVirtBit);	0
22788	if (FB[Mips::FeatureGINV])	0
22789	Features.set(Feature_HasGINVBit);	0
22790	if (FB[Mips::FeatureFP64Bit])	0
22791	Features.set(Feature_IsFP64bitBit);	0
22792	if (!FB[Mips::FeatureFP64Bit])	0
22793	Features.set(Feature_NotFP64bitBit);	0
22794	if (FB[Mips::FeatureSingleFloat])	0
22795	Features.set(Feature_IsSingleFloatBit);	0
22796	if (!FB[Mips::FeatureSingleFloat])	0
22797	Features.set(Feature_IsNotSingleFloatBit);	0
22798	if (!FB[Mips::FeatureSoftFloat])	0
22799	Features.set(Feature_IsNotSoftFloatBit);	0
22800	if (FB[Mips::FeatureMips3D])	0
22801	Features.set(Feature_HasMips3DBit);	0
22802	if (FB[Mips::FeatureDSP])	0
22803	Features.set(Feature_HasDSPBit);	0
22804	if (FB[Mips::FeatureDSPR2])	0
22805	Features.set(Feature_HasDSPR2Bit);	0
22806	if (FB[Mips::FeatureDSPR3])	0
22807	Features.set(Feature_HasDSPR3Bit);	0
22808	return Features;	0
22809	}	----
22810		----
22811	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {	0
22812	enum : uint8_t {	----
22813	CEFBS_None,	----
22814	CEFBS_HasCnMips,	----
22815	CEFBS_HasCnMipsP,	----
22816	CEFBS_HasDSP,	----
22817	CEFBS_HasDSPR2,	----
22818	CEFBS_HasMSA,	----
22819	CEFBS_HasMT,	----
22820	CEFBS_InMicroMips,	----
22821	CEFBS_InMips16Mode,	----
22822	CEFBS_IsGP32bit,	----
22823	CEFBS_IsGP64bit,	----
22824	CEFBS_IsNotSoftFloat,	----
22825	CEFBS_NotCnMips,	----
22826	CEFBS_NotInMips16Mode,	----
22827	CEFBS_HasDSP_NotInMicroMips,	----
22828	CEFBS_HasStdEnc_HasMSA,	----
22829	CEFBS_HasStdEnc_HasMips32,	----
22830	CEFBS_HasStdEnc_HasMips32r6,	----
22831	CEFBS_HasStdEnc_HasMips64,	----
22832	CEFBS_HasStdEnc_HasMips64r6,	----
22833	CEFBS_HasStdEnc_IsNotSoftFloat,	----
22834	CEFBS_HasStdEnc_NotInMicroMips,	----
22835	CEFBS_HasStdEnc_NotMips3,	----
22836	CEFBS_HasStdEnc_NotMips4_32,	----
22837	CEFBS_InMicroMips_HasDSP,	----
22838	CEFBS_InMicroMips_HasDSPR2,	----
22839	CEFBS_InMicroMips_HasDSPR3,	----
22840	CEFBS_InMicroMips_HasEVA,	----
22841	CEFBS_InMicroMips_HasMips32r6,	----
22842	CEFBS_InMicroMips_IsNotSoftFloat,	----
22843	CEFBS_InMicroMips_NotMips32r6,	----
22844	CEFBS_IsFP64bit_IsNotSoftFloat,	----
22845	CEFBS_IsGP32bit_NotInMicroMips,	----
22846	CEFBS_NotFP64bit_IsNotSoftFloat,	----
22847	CEFBS_NotInMips16Mode_HasDSP,	----
22848	CEFBS_NotInMips16Mode_IsGP64bit,	----
22849	CEFBS_NotInMips16Mode_IsNotSoftFloat,	----
22850	CEFBS_NotInMips16Mode_IsPTR64bit,	----
22851	CEFBS_HasMips3_NotMips64r6_NotCnMips,	----
22852	CEFBS_HasMips64_HasCnMips_NotInMicroMips,	----
22853	CEFBS_HasStdEnc_HasMSA_HasMips64,	----
22854	CEFBS_HasStdEnc_HasMT_NotInMicroMips,	----
22855	CEFBS_HasStdEnc_HasMips2_NotInMicroMips,	----
22856	CEFBS_HasStdEnc_HasMips3_NotInMicroMips,	----
22857	CEFBS_HasStdEnc_HasMips32_NotInMicroMips,	----
22858	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,	----
22859	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,	----
22860	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,	----
22861	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,	----
22862	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,	----
22863	CEFBS_HasStdEnc_HasMips64r5_HasVirt,	----
22864	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,	----
22865	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,	----
22866	CEFBS_HasStdEnc_IsGP64bit_HasMips3,	----
22867	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,	----
22868	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,	----
22869	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,	----
22870	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,	----
22871	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,	----
22872	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,	----
22873	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,	----
22874	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,	----
22875	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,	----
22876	CEFBS_InMicroMips_HasMips32r5_HasVirt,	----
22877	CEFBS_InMicroMips_HasMips32r6_HasGINV,	----
22878	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,	----
22879	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,	----
22880	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,	----
22881	CEFBS_InMicroMips_NotMips32r6_HasDSP,	----
22882	CEFBS_InMicroMips_NotMips32r6_HasEVA,	----
22883	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,	----
22884	CEFBS_InMicroMips_NotMips32r6_NotMips64r6,	----
22885	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,	----
22886	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,	----
22887	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,	----
22888	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,	----
22889	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,	----
22890	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,	----
22891	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22892	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,	----
22893	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,	----
22894	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,	----
22895	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,	----
22896	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,	----
22897	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,	----
22898	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,	----
22899	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,	----
22900	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,	----
22901	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,	----
22902	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,	----
22903	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,	----
22904	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	----
22905	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	----
22906	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,	----
22907	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,	----
22908	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,	----
22909	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,	----
22910	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,	----
22911	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,	----
22912	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,	----
22913	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22914	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,	----
22915	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,	----
22916	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,	----
22917	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,	----
22918	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22919	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22920	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22921	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	----
22922	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22923	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22924	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22925	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	----
22926	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	----
22927	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22928	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	----
22929	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	----
22930	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,	----
22931	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	----
22932	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	----
22933	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,	----
22934	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,	----
22935	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	----
22936	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	----
22937	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	----
22938	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22939	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,	----
22940	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,	----
22941	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,	----
22943	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22944	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	----
22945	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22946	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22947	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22948	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	----
22949	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22950	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	----
22951	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	----
22952	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22953	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22954	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	----
22955	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	----
22956	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,	----
22957	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22958	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22959	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22960	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22961	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22962	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22963	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22964	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	----
22965	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	----
22966	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	----
22967	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	----
22968	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	----
22969	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	----
22970	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	----
22971	};	----
22972		----
22973	static constexpr FeatureBitset FeatureBitsets[] = {	----
22974	{}, // CEFBS_None	----
22975	{Feature_HasCnMipsBit, },	----
22976	{Feature_HasCnMipsPBit, },	----
22977	{Feature_HasDSPBit, },	----
22978	{Feature_HasDSPR2Bit, },	----
22979	{Feature_HasMSABit, },	----
22980	{Feature_HasMTBit, },	----
22981	{Feature_InMicroMipsBit, },	----
22982	{Feature_InMips16ModeBit, },	----
22983	{Feature_IsGP32bitBit, },	----
22984	{Feature_IsGP64bitBit, },	----
22985	{Feature_IsNotSoftFloatBit, },	----
22986	{Feature_NotCnMipsBit, },	----
22987	{Feature_NotInMips16ModeBit, },	----
22988	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },	----
22989	{Feature_HasStdEncBit, Feature_HasMSABit, },	----
22990	{Feature_HasStdEncBit, Feature_HasMips32Bit, },	----
22991	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, },	----
22992	{Feature_HasStdEncBit, Feature_HasMips64Bit, },	----
22993	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, },	----
22994	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },	----
22995	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },	----
22996	{Feature_HasStdEncBit, Feature_NotMips3Bit, },	----
22997	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },	----
22998	{Feature_InMicroMipsBit, Feature_HasDSPBit, },	----
22999	{Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },	----
23000	{Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },	----
23001	{Feature_InMicroMipsBit, Feature_HasEVABit, },	----
23002	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },	----
23003	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },	----
23004	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },	----
23005	{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23006	{Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },	----
23007	{Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23008	{Feature_NotInMips16ModeBit, Feature_HasDSPBit, },	----
23009	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },	----
23010	{Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },	----
23011	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },	----
23012	{Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },	----
23013	{Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },	----
23014	{Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },	----
23015	{Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },	----
23016	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },	----
23017	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },	----
23018	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },	----
23019	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },	----
23020	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },	----
23021	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	----
23022	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },	----
23023	{Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },	----
23024	{Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },	----
23025	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23026	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },	----
23027	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },	----
23028	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },	----
23029	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },	----
23030	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },	----
23031	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23032	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23033	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },	----
23034	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23035	{Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },	----
23036	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23037	{Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },	----
23038	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },	----
23039	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	----
23040	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23041	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23042	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },	----
23043	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },	----
23044	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	----
23045	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23046	{Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23047	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },	----
23048	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },	----
23049	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },	----
23050	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },	----
23051	{Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	----
23052	{Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23053	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23054	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	----
23055	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23056	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23057	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23058	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23059	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	----
23060	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	----
23061	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },	----
23062	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	----
23063	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },	----
23064	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23065	{Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23066	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23067	{Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23068	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	----
23069	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23070	{Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	----
23071	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	----
23072	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23073	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23074	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23075	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	----
23076	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	----
23077	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	----
23078	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	----
23079	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23080	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23081	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23082	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23083	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23084	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23085	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23086	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	----
23087	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23088	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23089	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23090	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23091	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23092	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23093	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23094	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	----
23095	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23096	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23097	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23098	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23099	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23100	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	----
23101	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	----
23102	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23103	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	----
23104	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23105	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	----
23106	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23107	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23108	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23109	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	----
23110	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23111	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23112	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23113	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23114	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23115	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	----
23116	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	----
23117	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },	----
23118	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23119	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23120	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23121	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23122	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23123	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23124	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23125	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	----
23126	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	----
23127	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	----
23128	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	----
23129	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	----
23130	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	----
23131	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	----
23132	};	----
23133	static uint8_t RequiredFeaturesRefs[] = {	----
23134	CEFBS_None, // PHI = 0	----
23135	CEFBS_None, // INLINEASM = 1	----
23136	CEFBS_None, // INLINEASM_BR = 2	----
23137	CEFBS_None, // CFI_INSTRUCTION = 3	----
23138	CEFBS_None, // EH_LABEL = 4	----
23139	CEFBS_None, // GC_LABEL = 5	----
23140	CEFBS_None, // ANNOTATION_LABEL = 6	----
23141	CEFBS_None, // KILL = 7	----
23142	CEFBS_None, // EXTRACT_SUBREG = 8	----
23143	CEFBS_None, // INSERT_SUBREG = 9	----
23144	CEFBS_None, // IMPLICIT_DEF = 10	----
23145	CEFBS_None, // SUBREG_TO_REG = 11	----
23146	CEFBS_None, // COPY_TO_REGCLASS = 12	----
23147	CEFBS_None, // DBG_VALUE = 13	----
23148	CEFBS_None, // DBG_VALUE_LIST = 14	----
23149	CEFBS_None, // DBG_INSTR_REF = 15	----
23150	CEFBS_None, // DBG_PHI = 16	----
23151	CEFBS_None, // DBG_LABEL = 17	----
23152	CEFBS_None, // REG_SEQUENCE = 18	----
23153	CEFBS_None, // COPY = 19	----
23154	CEFBS_None, // BUNDLE = 20	----
23155	CEFBS_None, // LIFETIME_START = 21	----
23156	CEFBS_None, // LIFETIME_END = 22	----
23157	CEFBS_None, // PSEUDO_PROBE = 23	----
23158	CEFBS_None, // ARITH_FENCE = 24	----
23159	CEFBS_None, // STACKMAP = 25	----
23160	CEFBS_None, // FENTRY_CALL = 26	----
23161	CEFBS_None, // PATCHPOINT = 27	----
23162	CEFBS_None, // LOAD_STACK_GUARD = 28	----
23163	CEFBS_None, // PREALLOCATED_SETUP = 29	----
23164	CEFBS_None, // PREALLOCATED_ARG = 30	----
23165	CEFBS_None, // STATEPOINT = 31	----
23166	CEFBS_None, // LOCAL_ESCAPE = 32	----
23167	CEFBS_None, // FAULTING_OP = 33	----
23168	CEFBS_None, // PATCHABLE_OP = 34	----
23169	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35	----
23170	CEFBS_None, // PATCHABLE_RET = 36	----
23171	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37	----
23172	CEFBS_None, // PATCHABLE_TAIL_CALL = 38	----
23173	CEFBS_None, // PATCHABLE_EVENT_CALL = 39	----
23174	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40	----
23175	CEFBS_None, // ICALL_BRANCH_FUNNEL = 41	----
23176	CEFBS_None, // MEMBARRIER = 42	----
23177	CEFBS_None, // G_ASSERT_SEXT = 43	----
23178	CEFBS_None, // G_ASSERT_ZEXT = 44	----
23179	CEFBS_None, // G_ASSERT_ALIGN = 45	----
23180	CEFBS_None, // G_ADD = 46	----
23181	CEFBS_None, // G_SUB = 47	----
23182	CEFBS_None, // G_MUL = 48	----
23183	CEFBS_None, // G_SDIV = 49	----
23184	CEFBS_None, // G_UDIV = 50	----
23185	CEFBS_None, // G_SREM = 51	----
23186	CEFBS_None, // G_UREM = 52	----
23187	CEFBS_None, // G_SDIVREM = 53	----
23188	CEFBS_None, // G_UDIVREM = 54	----
23189	CEFBS_None, // G_AND = 55	----
23190	CEFBS_None, // G_OR = 56	----
23191	CEFBS_None, // G_XOR = 57	----
23192	CEFBS_None, // G_IMPLICIT_DEF = 58	----
23193	CEFBS_None, // G_PHI = 59	----
23194	CEFBS_None, // G_FRAME_INDEX = 60	----
23195	CEFBS_None, // G_GLOBAL_VALUE = 61	----
23196	CEFBS_None, // G_CONSTANT_POOL = 62	----
23197	CEFBS_None, // G_EXTRACT = 63	----
23198	CEFBS_None, // G_UNMERGE_VALUES = 64	----
23199	CEFBS_None, // G_INSERT = 65	----
23200	CEFBS_None, // G_MERGE_VALUES = 66	----
23201	CEFBS_None, // G_BUILD_VECTOR = 67	----
23202	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 68	----
23203	CEFBS_None, // G_CONCAT_VECTORS = 69	----
23204	CEFBS_None, // G_PTRTOINT = 70	----
23205	CEFBS_None, // G_INTTOPTR = 71	----
23206	CEFBS_None, // G_BITCAST = 72	----
23207	CEFBS_None, // G_FREEZE = 73	----
23208	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 74	----
23209	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 75	----
23210	CEFBS_None, // G_INTRINSIC_TRUNC = 76	----
23211	CEFBS_None, // G_INTRINSIC_ROUND = 77	----
23212	CEFBS_None, // G_INTRINSIC_LRINT = 78	----
23213	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 79	----
23214	CEFBS_None, // G_READCYCLECOUNTER = 80	----
23215	CEFBS_None, // G_LOAD = 81	----
23216	CEFBS_None, // G_SEXTLOAD = 82	----
23217	CEFBS_None, // G_ZEXTLOAD = 83	----
23218	CEFBS_None, // G_INDEXED_LOAD = 84	----
23219	CEFBS_None, // G_INDEXED_SEXTLOAD = 85	----
23220	CEFBS_None, // G_INDEXED_ZEXTLOAD = 86	----
23221	CEFBS_None, // G_STORE = 87	----
23222	CEFBS_None, // G_INDEXED_STORE = 88	----
23223	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89	----
23224	CEFBS_None, // G_ATOMIC_CMPXCHG = 90	----
23225	CEFBS_None, // G_ATOMICRMW_XCHG = 91	----
23226	CEFBS_None, // G_ATOMICRMW_ADD = 92	----
23227	CEFBS_None, // G_ATOMICRMW_SUB = 93	----
23228	CEFBS_None, // G_ATOMICRMW_AND = 94	----
23229	CEFBS_None, // G_ATOMICRMW_NAND = 95	----
23230	CEFBS_None, // G_ATOMICRMW_OR = 96	----
23231	CEFBS_None, // G_ATOMICRMW_XOR = 97	----
23232	CEFBS_None, // G_ATOMICRMW_MAX = 98	----
23233	CEFBS_None, // G_ATOMICRMW_MIN = 99	----
23234	CEFBS_None, // G_ATOMICRMW_UMAX = 100	----
23235	CEFBS_None, // G_ATOMICRMW_UMIN = 101	----
23236	CEFBS_None, // G_ATOMICRMW_FADD = 102	----
23237	CEFBS_None, // G_ATOMICRMW_FSUB = 103	----
23238	CEFBS_None, // G_ATOMICRMW_FMAX = 104	----
23239	CEFBS_None, // G_ATOMICRMW_FMIN = 105	----
23240	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 106	----
23241	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 107	----
23242	CEFBS_None, // G_FENCE = 108	----
23243	CEFBS_None, // G_BRCOND = 109	----
23244	CEFBS_None, // G_BRINDIRECT = 110	----
23245	CEFBS_None, // G_INVOKE_REGION_START = 111	----
23246	CEFBS_None, // G_INTRINSIC = 112	----
23247	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 113	----
23248	CEFBS_None, // G_ANYEXT = 114	----
23249	CEFBS_None, // G_TRUNC = 115	----
23250	CEFBS_None, // G_CONSTANT = 116	----
23251	CEFBS_None, // G_FCONSTANT = 117	----
23252	CEFBS_None, // G_VASTART = 118	----
23253	CEFBS_None, // G_VAARG = 119	----
23254	CEFBS_None, // G_SEXT = 120	----
23255	CEFBS_None, // G_SEXT_INREG = 121	----
23256	CEFBS_None, // G_ZEXT = 122	----
23257	CEFBS_None, // G_SHL = 123	----
23258	CEFBS_None, // G_LSHR = 124	----
23259	CEFBS_None, // G_ASHR = 125	----
23260	CEFBS_None, // G_FSHL = 126	----
23261	CEFBS_None, // G_FSHR = 127	----
23262	CEFBS_None, // G_ROTR = 128	----
23263	CEFBS_None, // G_ROTL = 129	----
23264	CEFBS_None, // G_ICMP = 130	----
23265	CEFBS_None, // G_FCMP = 131	----
23266	CEFBS_None, // G_SELECT = 132	----
23267	CEFBS_None, // G_UADDO = 133	----
23268	CEFBS_None, // G_UADDE = 134	----
23269	CEFBS_None, // G_USUBO = 135	----
23270	CEFBS_None, // G_USUBE = 136	----
23271	CEFBS_None, // G_SADDO = 137	----
23272	CEFBS_None, // G_SADDE = 138	----
23273	CEFBS_None, // G_SSUBO = 139	----
23274	CEFBS_None, // G_SSUBE = 140	----
23275	CEFBS_None, // G_UMULO = 141	----
23276	CEFBS_None, // G_SMULO = 142	----
23277	CEFBS_None, // G_UMULH = 143	----
23278	CEFBS_None, // G_SMULH = 144	----
23279	CEFBS_None, // G_UADDSAT = 145	----
23280	CEFBS_None, // G_SADDSAT = 146	----
23281	CEFBS_None, // G_USUBSAT = 147	----
23282	CEFBS_None, // G_SSUBSAT = 148	----
23283	CEFBS_None, // G_USHLSAT = 149	----
23284	CEFBS_None, // G_SSHLSAT = 150	----
23285	CEFBS_None, // G_SMULFIX = 151	----
23286	CEFBS_None, // G_UMULFIX = 152	----
23287	CEFBS_None, // G_SMULFIXSAT = 153	----
23288	CEFBS_None, // G_UMULFIXSAT = 154	----
23289	CEFBS_None, // G_SDIVFIX = 155	----
23290	CEFBS_None, // G_UDIVFIX = 156	----
23291	CEFBS_None, // G_SDIVFIXSAT = 157	----
23292	CEFBS_None, // G_UDIVFIXSAT = 158	----
23293	CEFBS_None, // G_FADD = 159	----
23294	CEFBS_None, // G_FSUB = 160	----
23295	CEFBS_None, // G_FMUL = 161	----
23296	CEFBS_None, // G_FMA = 162	----
23297	CEFBS_None, // G_FMAD = 163	----
23298	CEFBS_None, // G_FDIV = 164	----
23299	CEFBS_None, // G_FREM = 165	----
23300	CEFBS_None, // G_FPOW = 166	----
23301	CEFBS_None, // G_FPOWI = 167	----
23302	CEFBS_None, // G_FEXP = 168	----
23303	CEFBS_None, // G_FEXP2 = 169	----
23304	CEFBS_None, // G_FLOG = 170	----
23305	CEFBS_None, // G_FLOG2 = 171	----
23306	CEFBS_None, // G_FLOG10 = 172	----
23307	CEFBS_None, // G_FLDEXP = 173	----
23308	CEFBS_None, // G_FFREXP = 174	----
23309	CEFBS_None, // G_FNEG = 175	----
23310	CEFBS_None, // G_FPEXT = 176	----
23311	CEFBS_None, // G_FPTRUNC = 177	----
23312	CEFBS_None, // G_FPTOSI = 178	----
23313	CEFBS_None, // G_FPTOUI = 179	----
23314	CEFBS_None, // G_SITOFP = 180	----
23315	CEFBS_None, // G_UITOFP = 181	----
23316	CEFBS_None, // G_FABS = 182	----
23317	CEFBS_None, // G_FCOPYSIGN = 183	----
23318	CEFBS_None, // G_IS_FPCLASS = 184	----
23319	CEFBS_None, // G_FCANONICALIZE = 185	----
23320	CEFBS_None, // G_FMINNUM = 186	----
23321	CEFBS_None, // G_FMAXNUM = 187	----
23322	CEFBS_None, // G_FMINNUM_IEEE = 188	----
23323	CEFBS_None, // G_FMAXNUM_IEEE = 189	----
23324	CEFBS_None, // G_FMINIMUM = 190	----
23325	CEFBS_None, // G_FMAXIMUM = 191	----
23326	CEFBS_None, // G_PTR_ADD = 192	----
23327	CEFBS_None, // G_PTRMASK = 193	----
23328	CEFBS_None, // G_SMIN = 194	----
23329	CEFBS_None, // G_SMAX = 195	----
23330	CEFBS_None, // G_UMIN = 196	----
23331	CEFBS_None, // G_UMAX = 197	----
23332	CEFBS_None, // G_ABS = 198	----
23333	CEFBS_None, // G_LROUND = 199	----
23334	CEFBS_None, // G_LLROUND = 200	----
23335	CEFBS_None, // G_BR = 201	----
23336	CEFBS_None, // G_BRJT = 202	----
23337	CEFBS_None, // G_INSERT_VECTOR_ELT = 203	----
23338	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 204	----
23339	CEFBS_None, // G_SHUFFLE_VECTOR = 205	----
23340	CEFBS_None, // G_CTTZ = 206	----
23341	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 207	----
23342	CEFBS_None, // G_CTLZ = 208	----
23343	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 209	----
23344	CEFBS_None, // G_CTPOP = 210	----
23345	CEFBS_None, // G_BSWAP = 211	----
23346	CEFBS_None, // G_BITREVERSE = 212	----
23347	CEFBS_None, // G_FCEIL = 213	----
23348	CEFBS_None, // G_FCOS = 214	----
23349	CEFBS_None, // G_FSIN = 215	----
23350	CEFBS_None, // G_FSQRT = 216	----
23351	CEFBS_None, // G_FFLOOR = 217	----
23352	CEFBS_None, // G_FRINT = 218	----
23353	CEFBS_None, // G_FNEARBYINT = 219	----
23354	CEFBS_None, // G_ADDRSPACE_CAST = 220	----
23355	CEFBS_None, // G_BLOCK_ADDR = 221	----
23356	CEFBS_None, // G_JUMP_TABLE = 222	----
23357	CEFBS_None, // G_DYN_STACKALLOC = 223	----
23358	CEFBS_None, // G_STRICT_FADD = 224	----
23359	CEFBS_None, // G_STRICT_FSUB = 225	----
23360	CEFBS_None, // G_STRICT_FMUL = 226	----
23361	CEFBS_None, // G_STRICT_FDIV = 227	----
23362	CEFBS_None, // G_STRICT_FREM = 228	----
23363	CEFBS_None, // G_STRICT_FMA = 229	----
23364	CEFBS_None, // G_STRICT_FSQRT = 230	----
23365	CEFBS_None, // G_STRICT_FLDEXP = 231	----
23366	CEFBS_None, // G_READ_REGISTER = 232	----
23367	CEFBS_None, // G_WRITE_REGISTER = 233	----
23368	CEFBS_None, // G_MEMCPY = 234	----
23369	CEFBS_None, // G_MEMCPY_INLINE = 235	----
23370	CEFBS_None, // G_MEMMOVE = 236	----
23371	CEFBS_None, // G_MEMSET = 237	----
23372	CEFBS_None, // G_BZERO = 238	----
23373	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 239	----
23374	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 240	----
23375	CEFBS_None, // G_VECREDUCE_FADD = 241	----
23376	CEFBS_None, // G_VECREDUCE_FMUL = 242	----
23377	CEFBS_None, // G_VECREDUCE_FMAX = 243	----
23378	CEFBS_None, // G_VECREDUCE_FMIN = 244	----
23379	CEFBS_None, // G_VECREDUCE_ADD = 245	----
23380	CEFBS_None, // G_VECREDUCE_MUL = 246	----
23381	CEFBS_None, // G_VECREDUCE_AND = 247	----
23382	CEFBS_None, // G_VECREDUCE_OR = 248	----
23383	CEFBS_None, // G_VECREDUCE_XOR = 249	----
23384	CEFBS_None, // G_VECREDUCE_SMAX = 250	----
23385	CEFBS_None, // G_VECREDUCE_SMIN = 251	----
23386	CEFBS_None, // G_VECREDUCE_UMAX = 252	----
23387	CEFBS_None, // G_VECREDUCE_UMIN = 253	----
23388	CEFBS_None, // G_SBFX = 254	----
23389	CEFBS_None, // G_UBFX = 255	----
23390	CEFBS_None, // ABSMacro = 256	----
23391	CEFBS_None, // ADJCALLSTACKDOWN = 257	----
23392	CEFBS_None, // ADJCALLSTACKUP = 258	----
23393	CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 259	----
23394	CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 260	----
23395	CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 261	----
23396	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 262	----
23397	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 263	----
23398	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 264	----
23399	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 265	----
23400	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 266	----
23401	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 267	----
23402	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 268	----
23403	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 269	----
23404	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 270	----
23405	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 271	----
23406	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 272	----
23407	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 273	----
23408	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 274	----
23409	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 275	----
23410	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 276	----
23411	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 277	----
23412	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 278	----
23413	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 279	----
23414	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 280	----
23415	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 281	----
23416	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 282	----
23417	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 283	----
23418	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 284	----
23419	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 285	----
23420	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 286	----
23421	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 287	----
23422	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 288	----
23423	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 289	----
23424	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 290	----
23425	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 291	----
23426	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 292	----
23427	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 293	----
23428	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 294	----
23429	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 295	----
23430	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 296	----
23431	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 297	----
23432	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 298	----
23433	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 299	----
23434	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 300	----
23435	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 301	----
23436	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 302	----
23437	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 303	----
23438	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 304	----
23439	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 305	----
23440	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 306	----
23441	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 307	----
23442	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 308	----
23443	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 309	----
23444	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 310	----
23445	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 311	----
23446	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 312	----
23447	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 313	----
23448	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 314	----
23449	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 315	----
23450	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 316	----
23451	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 317	----
23452	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 318	----
23453	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 319	----
23454	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 320	----
23455	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 321	----
23456	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 322	----
23457	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 323	----
23458	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 324	----
23459	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 325	----
23460	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 326	----
23461	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 327	----
23462	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 328	----
23463	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 329	----
23464	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 330	----
23465	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 331	----
23466	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 332	----
23467	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 333	----
23468	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 334	----
23469	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 335	----
23470	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 336	----
23471	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 337	----
23472	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 338	----
23473	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 339	----
23474	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 340	----
23475	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 341	----
23476	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 342	----
23477	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 343	----
23478	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 344	----
23479	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 345	----
23480	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 346	----
23481	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 347	----
23482	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 348	----
23483	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 349	----
23484	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 350	----
23485	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 351	----
23486	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 352	----
23487	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 353	----
23488	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 354	----
23489	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 355	----
23490	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 356	----
23491	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 357	----
23492	CEFBS_HasStdEnc_NotInMicroMips, // B = 358	----
23493	CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 359	----
23494	CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 360	----
23495	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 361	----
23496	CEFBS_None, // BGE = 362	----
23497	CEFBS_None, // BGEImmMacro = 363	----
23498	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 364	----
23499	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 365	----
23500	CEFBS_None, // BGEU = 366	----
23501	CEFBS_None, // BGEUImmMacro = 367	----
23502	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 368	----
23503	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 369	----
23504	CEFBS_None, // BGT = 370	----
23505	CEFBS_None, // BGTImmMacro = 371	----
23506	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 372	----
23507	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 373	----
23508	CEFBS_None, // BGTU = 374	----
23509	CEFBS_None, // BGTUImmMacro = 375	----
23510	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 376	----
23511	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 377	----
23512	CEFBS_None, // BLE = 378	----
23513	CEFBS_None, // BLEImmMacro = 379	----
23514	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 380	----
23515	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 381	----
23516	CEFBS_None, // BLEU = 382	----
23517	CEFBS_None, // BLEUImmMacro = 383	----
23518	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 384	----
23519	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 385	----
23520	CEFBS_None, // BLT = 386	----
23521	CEFBS_None, // BLTImmMacro = 387	----
23522	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 388	----
23523	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 389	----
23524	CEFBS_None, // BLTU = 390	----
23525	CEFBS_None, // BLTUImmMacro = 391	----
23526	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 392	----
23527	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 393	----
23528	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 394	----
23529	CEFBS_None, // BPOSGE32_PSEUDO = 395	----
23530	CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 396	----
23531	CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 397	----
23532	CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 398	----
23533	CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 399	----
23534	CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 400	----
23535	CEFBS_InMicroMips_NotMips32r6, // B_MM = 401	----
23536	CEFBS_None, // B_MMR6_Pseudo = 402	----
23537	CEFBS_InMicroMips, // B_MM_Pseudo = 403	----
23538	CEFBS_None, // BeqImm = 404	----
23539	CEFBS_None, // BneImm = 405	----
23540	CEFBS_InMips16Mode, // BteqzT8CmpX16 = 406	----
23541	CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 407	----
23542	CEFBS_InMips16Mode, // BteqzT8SltX16 = 408	----
23543	CEFBS_InMips16Mode, // BteqzT8SltiX16 = 409	----
23544	CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 410	----
23545	CEFBS_InMips16Mode, // BteqzT8SltuX16 = 411	----
23546	CEFBS_InMips16Mode, // BtnezT8CmpX16 = 412	----
23547	CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 413	----
23548	CEFBS_InMips16Mode, // BtnezT8SltX16 = 414	----
23549	CEFBS_InMips16Mode, // BtnezT8SltiX16 = 415	----
23550	CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 416	----
23551	CEFBS_InMips16Mode, // BtnezT8SltuX16 = 417	----
23552	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 418	----
23553	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 419	----
23554	CEFBS_HasMT, // CFTC1 = 420	----
23555	CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 421	----
23556	CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 422	----
23557	CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 423	----
23558	CEFBS_HasMT, // CTTC1 = 424	----
23559	CEFBS_InMips16Mode, // Constant32 = 425	----
23560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 426	----
23561	CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 427	----
23562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 428	----
23563	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 429	----
23564	CEFBS_HasStdEnc_HasMips64, // DROL = 430	----
23565	CEFBS_HasStdEnc_HasMips64, // DROLImm = 431	----
23566	CEFBS_HasStdEnc_HasMips64, // DROR = 432	----
23567	CEFBS_HasStdEnc_HasMips64, // DRORImm = 433	----
23568	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 434	----
23569	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 435	----
23570	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 436	----
23571	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 437	----
23572	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 438	----
23573	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 439	----
23574	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 440	----
23575	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 441	----
23576	CEFBS_NotInMips16Mode, // ERet = 442	----
23577	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 443	----
23578	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 444	----
23579	CEFBS_HasStdEnc_HasMSA, // FABS_D = 445	----
23580	CEFBS_HasStdEnc_HasMSA, // FABS_W = 446	----
23581	CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 447	----
23582	CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 448	----
23583	CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 449	----
23584	CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 450	----
23585	CEFBS_InMips16Mode, // GotPrologue16 = 451	----
23586	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 452	----
23587	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 453	----
23588	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 454	----
23589	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 455	----
23590	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 456	----
23591	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 457	----
23592	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 458	----
23593	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 459	----
23594	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 460	----
23595	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 461	----
23596	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 462	----
23597	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 463	----
23598	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 464	----
23599	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 465	----
23600	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 466	----
23601	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 467	----
23602	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 468	----
23603	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 469	----
23604	CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 470	----
23605	CEFBS_None, // JalOneReg = 471	----
23606	CEFBS_None, // JalTwoReg = 472	----
23607	CEFBS_HasStdEnc_NotMips3, // LDMacro = 473	----
23608	CEFBS_NotInMips16Mode, // LDR_D = 474	----
23609	CEFBS_NotInMips16Mode, // LDR_W = 475	----
23610	CEFBS_HasMSA, // LD_F16 = 476	----
23611	CEFBS_NotInMips16Mode, // LOAD_ACC128 = 477	----
23612	CEFBS_NotInMips16Mode, // LOAD_ACC64 = 478	----
23613	CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 479	----
23614	CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 480	----
23615	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 481	----
23616	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 482	----
23617	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 483	----
23618	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 484	----
23619	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 485	----
23620	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 486	----
23621	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 487	----
23622	CEFBS_InMicroMips, // LWM_MM = 488	----
23623	CEFBS_None, // LoadAddrImm32 = 489	----
23624	CEFBS_None, // LoadAddrImm64 = 490	----
23625	CEFBS_None, // LoadAddrReg32 = 491	----
23626	CEFBS_None, // LoadAddrReg64 = 492	----
23627	CEFBS_None, // LoadImm32 = 493	----
23628	CEFBS_None, // LoadImm64 = 494	----
23629	CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 495	----
23630	CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 496	----
23631	CEFBS_None, // LoadImmDoubleGPR = 497	----
23632	CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 498	----
23633	CEFBS_None, // LoadImmSingleGPR = 499	----
23634	CEFBS_InMips16Mode, // LwConstant32 = 500	----
23635	CEFBS_HasMT, // MFTACX = 501	----
23636	CEFBS_HasMT, // MFTC0 = 502	----
23637	CEFBS_HasMT, // MFTC1 = 503	----
23638	CEFBS_HasMT, // MFTDSP = 504	----
23639	CEFBS_HasMT, // MFTGPR = 505	----
23640	CEFBS_HasMT, // MFTHC1 = 506	----
23641	CEFBS_HasMT, // MFTHI = 507	----
23642	CEFBS_HasMT, // MFTLO = 508	----
23643	CEFBS_None, // MIPSeh_return32 = 509	----
23644	CEFBS_None, // MIPSeh_return64 = 510	----
23645	CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 511	----
23646	CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 512	----
23647	CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 513	----
23648	CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 514	----
23649	CEFBS_HasMT, // MTTACX = 515	----
23650	CEFBS_HasMT, // MTTC0 = 516	----
23651	CEFBS_HasMT, // MTTC1 = 517	----
23652	CEFBS_HasMT, // MTTDSP = 518	----
23653	CEFBS_HasMT, // MTTGPR = 519	----
23654	CEFBS_HasMT, // MTTHC1 = 520	----
23655	CEFBS_HasMT, // MTTHI = 521	----
23656	CEFBS_HasMT, // MTTLO = 522	----
23657	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 523	----
23658	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 524	----
23659	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 525	----
23660	CEFBS_InMips16Mode, // MultRxRy16 = 526	----
23661	CEFBS_InMips16Mode, // MultRxRyRz16 = 527	----
23662	CEFBS_InMips16Mode, // MultuRxRy16 = 528	----
23663	CEFBS_InMips16Mode, // MultuRxRyRz16 = 529	----
23664	CEFBS_HasStdEnc_NotInMicroMips, // NOP = 530	----
23665	CEFBS_IsGP32bit, // NORImm = 531	----
23666	CEFBS_IsGP64bit, // NORImm64 = 532	----
23667	CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 533	----
23668	CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 534	----
23669	CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 535	----
23670	CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 536	----
23671	CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 537	----
23672	CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 538	----
23673	CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 539	----
23674	CEFBS_HasDSP, // PseudoCMPU_LE_QB = 540	----
23675	CEFBS_HasDSP, // PseudoCMPU_LT_QB = 541	----
23676	CEFBS_HasDSP, // PseudoCMP_EQ_PH = 542	----
23677	CEFBS_HasDSP, // PseudoCMP_LE_PH = 543	----
23678	CEFBS_HasDSP, // PseudoCMP_LT_PH = 544	----
23679	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 545	----
23680	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 546	----
23681	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 547	----
23682	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 548	----
23683	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 549	----
23684	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 550	----
23685	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 551	----
23686	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 552	----
23687	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 553	----
23688	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 554	----
23689	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 555	----
23690	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 556	----
23691	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 557	----
23692	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 558	----
23693	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 559	----
23694	CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 560	----
23695	CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 561	----
23696	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 562	----
23697	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 563	----
23698	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 564	----
23699	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 565	----
23700	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 566	----
23701	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 567	----
23702	CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 568	----
23703	CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 569	----
23704	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 570	----
23705	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 571	----
23706	CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 572	----
23707	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 573	----
23708	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 574	----
23709	CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 575	----
23710	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 576	----
23711	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 577	----
23712	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 578	----
23713	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 579	----
23714	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 580	----
23715	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 581	----
23716	CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 582	----
23717	CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 583	----
23718	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 584	----
23719	CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 585	----
23720	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 586	----
23721	CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 587	----
23722	CEFBS_HasDSP, // PseudoPICK_PH = 588	----
23723	CEFBS_HasDSP, // PseudoPICK_QB = 589	----
23724	CEFBS_None, // PseudoReturn = 590	----
23725	CEFBS_IsGP64bit, // PseudoReturn64 = 591	----
23726	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 592	----
23727	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 593	----
23728	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 594	----
23729	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 595	----
23730	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 596	----
23731	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 597	----
23732	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 598	----
23733	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 599	----
23734	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 600	----
23735	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 601	----
23736	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 602	----
23737	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 603	----
23738	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 604	----
23739	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 605	----
23740	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 606	----
23741	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 607	----
23742	CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 608	----
23743	CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 609	----
23744	CEFBS_None, // PseudoTRUNC_W_S = 610	----
23745	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 611	----
23746	CEFBS_None, // ROL = 612	----
23747	CEFBS_None, // ROLImm = 613	----
23748	CEFBS_None, // ROR = 614	----
23749	CEFBS_None, // RORImm = 615	----
23750	CEFBS_NotInMips16Mode, // RetRA = 616	----
23751	CEFBS_InMips16Mode, // RetRA16 = 617	----
23752	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 618	----
23753	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 619	----
23754	CEFBS_HasStdEnc_NotMips3, // SDMacro = 620	----
23755	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 621	----
23756	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 622	----
23757	CEFBS_NotCnMips, // SEQIMacro = 623	----
23758	CEFBS_NotCnMips, // SEQMacro = 624	----
23759	CEFBS_HasStdEnc_NotInMicroMips, // SGE = 625	----
23760	CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 626	----
23761	CEFBS_IsGP64bit, // SGEImm64 = 627	----
23762	CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 628	----
23763	CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 629	----
23764	CEFBS_IsGP64bit, // SGEUImm64 = 630	----
23765	CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 631	----
23766	CEFBS_IsGP64bit, // SGTImm64 = 632	----
23767	CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 633	----
23768	CEFBS_IsGP64bit, // SGTUImm64 = 634	----
23769	CEFBS_HasStdEnc_NotInMicroMips, // SLE = 635	----
23770	CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 636	----
23771	CEFBS_IsGP64bit, // SLEImm64 = 637	----
23772	CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 638	----
23773	CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 639	----
23774	CEFBS_IsGP64bit, // SLEUImm64 = 640	----
23775	CEFBS_IsGP64bit, // SLTImm64 = 641	----
23776	CEFBS_IsGP64bit, // SLTUImm64 = 642	----
23777	CEFBS_NotCnMips, // SNEIMacro = 643	----
23778	CEFBS_NotCnMips, // SNEMacro = 644	----
23779	CEFBS_None, // SNZ_B_PSEUDO = 645	----
23780	CEFBS_None, // SNZ_D_PSEUDO = 646	----
23781	CEFBS_None, // SNZ_H_PSEUDO = 647	----
23782	CEFBS_None, // SNZ_V_PSEUDO = 648	----
23783	CEFBS_None, // SNZ_W_PSEUDO = 649	----
23784	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 650	----
23785	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 651	----
23786	CEFBS_NotInMips16Mode, // STORE_ACC128 = 652	----
23787	CEFBS_NotInMips16Mode, // STORE_ACC64 = 653	----
23788	CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 654	----
23789	CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 655	----
23790	CEFBS_NotInMips16Mode, // STR_D = 656	----
23791	CEFBS_NotInMips16Mode, // STR_W = 657	----
23792	CEFBS_HasMSA, // ST_F16 = 658	----
23793	CEFBS_InMicroMips, // SWM_MM = 659	----
23794	CEFBS_None, // SZ_B_PSEUDO = 660	----
23795	CEFBS_None, // SZ_D_PSEUDO = 661	----
23796	CEFBS_None, // SZ_H_PSEUDO = 662	----
23797	CEFBS_None, // SZ_V_PSEUDO = 663	----
23798	CEFBS_None, // SZ_W_PSEUDO = 664	----
23799	CEFBS_HasCnMipsP, // SaaAddr = 665	----
23800	CEFBS_HasCnMipsP, // SaadAddr = 666	----
23801	CEFBS_InMips16Mode, // SelBeqZ = 667	----
23802	CEFBS_InMips16Mode, // SelBneZ = 668	----
23803	CEFBS_InMips16Mode, // SelTBteqZCmp = 669	----
23804	CEFBS_InMips16Mode, // SelTBteqZCmpi = 670	----
23805	CEFBS_InMips16Mode, // SelTBteqZSlt = 671	----
23806	CEFBS_InMips16Mode, // SelTBteqZSlti = 672	----
23807	CEFBS_InMips16Mode, // SelTBteqZSltiu = 673	----
23808	CEFBS_InMips16Mode, // SelTBteqZSltu = 674	----
23809	CEFBS_InMips16Mode, // SelTBtneZCmp = 675	----
23810	CEFBS_InMips16Mode, // SelTBtneZCmpi = 676	----
23811	CEFBS_InMips16Mode, // SelTBtneZSlt = 677	----
23812	CEFBS_InMips16Mode, // SelTBtneZSlti = 678	----
23813	CEFBS_InMips16Mode, // SelTBtneZSltiu = 679	----
23814	CEFBS_InMips16Mode, // SelTBtneZSltu = 680	----
23815	CEFBS_InMips16Mode, // SltCCRxRy16 = 681	----
23816	CEFBS_InMips16Mode, // SltiCCRxImmX16 = 682	----
23817	CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 683	----
23818	CEFBS_InMips16Mode, // SltuCCRxRy16 = 684	----
23819	CEFBS_InMips16Mode, // SltuRxRyRz16 = 685	----
23820	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 686	----
23821	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 687	----
23822	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 688	----
23823	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 689	----
23824	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 690	----
23825	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 691	----
23826	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 692	----
23827	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 693	----
23828	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 694	----
23829	CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 695	----
23830	CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 696	----
23831	CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 697	----
23832	CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 698	----
23833	CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 699	----
23834	CEFBS_InMicroMips, // TRAP_MM = 700	----
23835	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 701	----
23836	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 702	----
23837	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 703	----
23838	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 704	----
23839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 705	----
23840	CEFBS_None, // Ulh = 706	----
23841	CEFBS_None, // Ulhu = 707	----
23842	CEFBS_None, // Ulw = 708	----
23843	CEFBS_None, // Ush = 709	----
23844	CEFBS_None, // Usw = 710	----
23845	CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 711	----
23846	CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 712	----
23847	CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 713	----
23848	CEFBS_HasDSP, // ABSQ_S_PH = 714	----
23849	CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 715	----
23850	CEFBS_HasDSPR2, // ABSQ_S_QB = 716	----
23851	CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 717	----
23852	CEFBS_HasDSP, // ABSQ_S_W = 718	----
23853	CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 719	----
23854	CEFBS_HasStdEnc_NotInMicroMips, // ADD = 720	----
23855	CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 721	----
23856	CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 722	----
23857	CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 723	----
23858	CEFBS_InMicroMips, // ADDIUR1SP_MM = 724	----
23859	CEFBS_InMicroMips, // ADDIUR2_MM = 725	----
23860	CEFBS_InMicroMips, // ADDIUS5_MM = 726	----
23861	CEFBS_InMicroMips, // ADDIUSP_MM = 727	----
23862	CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 728	----
23863	CEFBS_HasDSPR2, // ADDQH_PH = 729	----
23864	CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 730	----
23865	CEFBS_HasDSPR2, // ADDQH_R_PH = 731	----
23866	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 732	----
23867	CEFBS_HasDSPR2, // ADDQH_R_W = 733	----
23868	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 734	----
23869	CEFBS_HasDSPR2, // ADDQH_W = 735	----
23870	CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 736	----
23871	CEFBS_HasDSP, // ADDQ_PH = 737	----
23872	CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 738	----
23873	CEFBS_HasDSP, // ADDQ_S_PH = 739	----
23874	CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 740	----
23875	CEFBS_HasDSP, // ADDQ_S_W = 741	----
23876	CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 742	----
23877	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 743	----
23878	CEFBS_HasDSP, // ADDSC = 744	----
23879	CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 745	----
23880	CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 746	----
23881	CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 747	----
23882	CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 748	----
23883	CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 749	----
23884	CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 750	----
23885	CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 751	----
23886	CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 752	----
23887	CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 753	----
23888	CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 754	----
23889	CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 755	----
23890	CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 756	----
23891	CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 757	----
23892	CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 758	----
23893	CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 759	----
23894	CEFBS_HasDSPR2, // ADDUH_QB = 760	----
23895	CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 761	----
23896	CEFBS_HasDSPR2, // ADDUH_R_QB = 762	----
23897	CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 763	----
23898	CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 764	----
23899	CEFBS_HasDSPR2, // ADDU_PH = 765	----
23900	CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 766	----
23901	CEFBS_HasDSP, // ADDU_QB = 767	----
23902	CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 768	----
23903	CEFBS_HasDSPR2, // ADDU_S_PH = 769	----
23904	CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 770	----
23905	CEFBS_HasDSP, // ADDU_S_QB = 771	----
23906	CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 772	----
23907	CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 773	----
23908	CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 774	----
23909	CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 775	----
23910	CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 776	----
23911	CEFBS_HasStdEnc_HasMSA, // ADDV_B = 777	----
23912	CEFBS_HasStdEnc_HasMSA, // ADDV_D = 778	----
23913	CEFBS_HasStdEnc_HasMSA, // ADDV_H = 779	----
23914	CEFBS_HasStdEnc_HasMSA, // ADDV_W = 780	----
23915	CEFBS_HasDSP, // ADDWC = 781	----
23916	CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 782	----
23917	CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 783	----
23918	CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 784	----
23919	CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 785	----
23920	CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 786	----
23921	CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 787	----
23922	CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 788	----
23923	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 789	----
23924	CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 790	----
23925	CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 791	----
23926	CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 792	----
23927	CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 793	----
23928	CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 794	----
23929	CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 795	----
23930	CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 796	----
23931	CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 797	----
23932	CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 798	----
23933	CEFBS_HasStdEnc_NotInMicroMips, // AND = 799	----
23934	CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 800	----
23935	CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 801	----
23936	CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 802	----
23937	CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 803	----
23938	CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 804	----
23939	CEFBS_HasStdEnc_HasMSA, // ANDI_B = 805	----
23940	CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 806	----
23941	CEFBS_InMicroMips_NotMips32r6, // AND_MM = 807	----
23942	CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 808	----
23943	CEFBS_HasStdEnc_HasMSA, // AND_V = 809	----
23944	CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 810	----
23945	CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 811	----
23946	CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 812	----
23947	CEFBS_HasDSPR2, // APPEND = 813	----
23948	CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 814	----
23949	CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 815	----
23950	CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 816	----
23951	CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 817	----
23952	CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 818	----
23953	CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 819	----
23954	CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 820	----
23955	CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 821	----
23956	CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 822	----
23957	CEFBS_HasStdEnc_HasMips32r6, // AUI = 823	----
23958	CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 824	----
23959	CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 825	----
23960	CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 826	----
23961	CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 827	----
23962	CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 828	----
23963	CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 829	----
23964	CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 830	----
23965	CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 831	----
23966	CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 832	----
23967	CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 833	----
23968	CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 834	----
23969	CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 835	----
23970	CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 836	----
23971	CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 837	----
23972	CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 838	----
23973	CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 839	----
23974	CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 840	----
23975	CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 841	----
23976	CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 842	----
23977	CEFBS_InMips16Mode, // AddiuRxImmX16 = 843	----
23978	CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 844	----
23979	CEFBS_InMips16Mode, // AddiuRxRxImm16 = 845	----
23980	CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 846	----
23981	CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 847	----
23982	CEFBS_InMips16Mode, // AddiuSpImm16 = 848	----
23983	CEFBS_InMips16Mode, // AddiuSpImmX16 = 849	----
23984	CEFBS_InMips16Mode, // AdduRxRyRz16 = 850	----
23985	CEFBS_InMips16Mode, // AndRxRxRy16 = 851	----
23986	CEFBS_InMicroMips, // B16_MM = 852	----
23987	CEFBS_HasCnMips, // BADDu = 853	----
23988	CEFBS_HasStdEnc_HasMips32r6, // BAL = 854	----
23989	CEFBS_HasStdEnc_HasMips32r6, // BALC = 855	----
23990	CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 856	----
23991	CEFBS_HasDSPR2, // BALIGN = 857	----
23992	CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 858	----
23993	CEFBS_HasCnMips, // BBIT0 = 859	----
23994	CEFBS_HasCnMips, // BBIT032 = 860	----
23995	CEFBS_HasCnMips, // BBIT1 = 861	----
23996	CEFBS_HasCnMips, // BBIT132 = 862	----
23997	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 863	----
23998	CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 864	----
23999	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 865	----
24000	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 866	----
24001	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 867	----
24002	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 868	----
24003	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 869	----
24004	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 870	----
24005	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 871	----
24006	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 872	----
24007	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 873	----
24008	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 874	----
24009	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 875	----
24010	CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 876	----
24011	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 877	----
24012	CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 878	----
24013	CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 879	----
24014	CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 880	----
24015	CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 881	----
24016	CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 882	----
24017	CEFBS_HasStdEnc_HasMSA, // BCLR_B = 883	----
24018	CEFBS_HasStdEnc_HasMSA, // BCLR_D = 884	----
24019	CEFBS_HasStdEnc_HasMSA, // BCLR_H = 885	----
24020	CEFBS_HasStdEnc_HasMSA, // BCLR_W = 886	----
24021	CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 887	----
24022	CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 888	----
24023	CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 889	----
24024	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 890	----
24025	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 891	----
24026	CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 892	----
24027	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 893	----
24028	CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 894	----
24029	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 895	----
24030	CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 896	----
24031	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 897	----
24032	CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 898	----
24033	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 899	----
24034	CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 900	----
24035	CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 901	----
24036	CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 902	----
24037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 903	----
24038	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 904	----
24039	CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 905	----
24040	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 906	----
24041	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 907	----
24042	CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 908	----
24043	CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 909	----
24044	CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 910	----
24045	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 911	----
24046	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 912	----
24047	CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 913	----
24048	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 914	----
24049	CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 915	----
24050	CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 916	----
24051	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 917	----
24052	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 918	----
24053	CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 919	----
24054	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 920	----
24055	CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 921	----
24056	CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 922	----
24057	CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 923	----
24058	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 924	----
24059	CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 925	----
24060	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 926	----
24061	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 927	----
24062	CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 928	----
24063	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 929	----
24064	CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 930	----
24065	CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 931	----
24066	CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 932	----
24067	CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 933	----
24068	CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 934	----
24069	CEFBS_HasStdEnc_HasMSA, // BINSL_B = 935	----
24070	CEFBS_HasStdEnc_HasMSA, // BINSL_D = 936	----
24071	CEFBS_HasStdEnc_HasMSA, // BINSL_H = 937	----
24072	CEFBS_HasStdEnc_HasMSA, // BINSL_W = 938	----
24073	CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 939	----
24074	CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 940	----
24075	CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 941	----
24076	CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 942	----
24077	CEFBS_HasStdEnc_HasMSA, // BINSR_B = 943	----
24078	CEFBS_HasStdEnc_HasMSA, // BINSR_D = 944	----
24079	CEFBS_HasStdEnc_HasMSA, // BINSR_H = 945	----
24080	CEFBS_HasStdEnc_HasMSA, // BINSR_W = 946	----
24081	CEFBS_HasDSP, // BITREV = 947	----
24082	CEFBS_InMicroMips_HasDSP, // BITREV_MM = 948	----
24083	CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 949	----
24084	CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 950	----
24085	CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 951	----
24086	CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 952	----
24087	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 953	----
24088	CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 954	----
24089	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 955	----
24090	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 956	----
24091	CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 957	----
24092	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 958	----
24093	CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 959	----
24094	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 960	----
24095	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 961	----
24096	CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 962	----
24097	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 963	----
24098	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 964	----
24099	CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 965	----
24100	CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 966	----
24101	CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 967	----
24102	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 968	----
24103	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 969	----
24104	CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 970	----
24105	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 971	----
24106	CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 972	----
24107	CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 973	----
24108	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 974	----
24109	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 975	----
24110	CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 976	----
24111	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 977	----
24112	CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 978	----
24113	CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 979	----
24114	CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 980	----
24115	CEFBS_HasStdEnc_HasMSA, // BMZI_B = 981	----
24116	CEFBS_HasStdEnc_HasMSA, // BMZ_V = 982	----
24117	CEFBS_HasStdEnc_NotInMicroMips, // BNE = 983	----
24118	CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 984	----
24119	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 985	----
24120	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 986	----
24121	CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 987	----
24122	CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 988	----
24123	CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 989	----
24124	CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 990	----
24125	CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 991	----
24126	CEFBS_HasStdEnc_HasMSA, // BNEG_B = 992	----
24127	CEFBS_HasStdEnc_HasMSA, // BNEG_D = 993	----
24128	CEFBS_HasStdEnc_HasMSA, // BNEG_H = 994	----
24129	CEFBS_HasStdEnc_HasMSA, // BNEG_W = 995	----
24130	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 996	----
24131	CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 997	----
24132	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 998	----
24133	CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 999	----
24134	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1000	----
24135	CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1001	----
24136	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1002	----
24137	CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1003	----
24138	CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1004	----
24139	CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1005	----
24140	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1006	----
24141	CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1007	----
24142	CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1008	----
24143	CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1009	----
24144	CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1010	----
24145	CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1011	----
24146	CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1012	----
24147	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1013	----
24148	CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1014	----
24149	CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1015	----
24150	CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1016	----
24151	CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1017	----
24152	CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1018	----
24153	CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1019	----
24154	CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1020	----
24155	CEFBS_InMicroMips, // BREAK_MM = 1021	----
24156	CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1022	----
24157	CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1023	----
24158	CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1024	----
24159	CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1025	----
24160	CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1026	----
24161	CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1027	----
24162	CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1028	----
24163	CEFBS_HasStdEnc_HasMSA, // BSET_B = 1029	----
24164	CEFBS_HasStdEnc_HasMSA, // BSET_D = 1030	----
24165	CEFBS_HasStdEnc_HasMSA, // BSET_H = 1031	----
24166	CEFBS_HasStdEnc_HasMSA, // BSET_W = 1032	----
24167	CEFBS_HasStdEnc_HasMSA, // BZ_B = 1033	----
24168	CEFBS_HasStdEnc_HasMSA, // BZ_D = 1034	----
24169	CEFBS_HasStdEnc_HasMSA, // BZ_H = 1035	----
24170	CEFBS_HasStdEnc_HasMSA, // BZ_V = 1036	----
24171	CEFBS_HasStdEnc_HasMSA, // BZ_W = 1037	----
24172	CEFBS_InMips16Mode, // BeqzRxImm16 = 1038	----
24173	CEFBS_InMips16Mode, // BeqzRxImmX16 = 1039	----
24174	CEFBS_InMips16Mode, // Bimm16 = 1040	----
24175	CEFBS_InMips16Mode, // BimmX16 = 1041	----
24176	CEFBS_InMips16Mode, // BnezRxImm16 = 1042	----
24177	CEFBS_InMips16Mode, // BnezRxImmX16 = 1043	----
24178	CEFBS_InMips16Mode, // Break16 = 1044	----
24179	CEFBS_InMips16Mode, // Bteqz16 = 1045	----
24180	CEFBS_InMips16Mode, // BteqzX16 = 1046	----
24181	CEFBS_InMips16Mode, // Btnez16 = 1047	----
24182	CEFBS_InMips16Mode, // BtnezX16 = 1048	----
24183	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1049	----
24184	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1050	----
24185	CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1051	----
24186	CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1052	----
24187	CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1053	----
24188	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1054	----
24189	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1055	----
24190	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1056	----
24191	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1057	----
24192	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1058	----
24193	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1059	----
24194	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1060	----
24195	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1061	----
24196	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1062	----
24197	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1063	----
24198	CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1064	----
24199	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1065	----
24200	CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1066	----
24201	CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1067	----
24202	CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1068	----
24203	CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1069	----
24204	CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1070	----
24205	CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1071	----
24206	CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1072	----
24207	CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1073	----
24208	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1074	----
24209	CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1075	----
24210	CEFBS_InMicroMips, // CFC2_MM = 1076	----
24211	CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1077	----
24212	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1078	----
24213	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1079	----
24214	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1080	----
24215	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1081	----
24216	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1082	----
24217	CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1083	----
24218	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1084	----
24219	CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1085	----
24220	CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1086	----
24221	CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1087	----
24222	CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1088	----
24223	CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1089	----
24224	CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1090	----
24225	CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1091	----
24226	CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1092	----
24227	CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1093	----
24228	CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1094	----
24229	CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1095	----
24230	CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1096	----
24231	CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1097	----
24232	CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1098	----
24233	CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1099	----
24234	CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1100	----
24235	CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1101	----
24236	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1102	----
24237	CEFBS_InMicroMips, // CLO_MM = 1103	----
24238	CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1104	----
24239	CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1105	----
24240	CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1106	----
24241	CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1107	----
24242	CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1108	----
24243	CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1109	----
24244	CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1110	----
24245	CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1111	----
24246	CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1112	----
24247	CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1113	----
24248	CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1114	----
24249	CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1115	----
24250	CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1116	----
24251	CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1117	----
24252	CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1118	----
24253	CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1119	----
24254	CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1120	----
24255	CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1121	----
24256	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1122	----
24257	CEFBS_InMicroMips, // CLZ_MM = 1123	----
24258	CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1124	----
24259	CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1125	----
24260	CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1126	----
24261	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1127	----
24262	CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1128	----
24263	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1129	----
24264	CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1130	----
24265	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1131	----
24266	CEFBS_HasDSP, // CMPGU_EQ_QB = 1132	----
24267	CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1133	----
24268	CEFBS_HasDSP, // CMPGU_LE_QB = 1134	----
24269	CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1135	----
24270	CEFBS_HasDSP, // CMPGU_LT_QB = 1136	----
24271	CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1137	----
24272	CEFBS_HasDSP, // CMPU_EQ_QB = 1138	----
24273	CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1139	----
24274	CEFBS_HasDSP, // CMPU_LE_QB = 1140	----
24275	CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1141	----
24276	CEFBS_HasDSP, // CMPU_LT_QB = 1142	----
24277	CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1143	----
24278	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1144	----
24279	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1145	----
24280	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1146	----
24281	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1147	----
24282	CEFBS_HasDSP, // CMP_EQ_PH = 1148	----
24283	CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1149	----
24284	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1150	----
24285	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1151	----
24286	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1152	----
24287	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1153	----
24288	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1154	----
24289	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1155	----
24290	CEFBS_HasDSP, // CMP_LE_PH = 1156	----
24291	CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1157	----
24292	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1158	----
24293	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1159	----
24294	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1160	----
24295	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1161	----
24296	CEFBS_HasDSP, // CMP_LT_PH = 1162	----
24297	CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1163	----
24298	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1164	----
24299	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1165	----
24300	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1166	----
24301	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1167	----
24302	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1168	----
24303	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1169	----
24304	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1170	----
24305	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1171	----
24306	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1172	----
24307	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1173	----
24308	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1174	----
24309	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1175	----
24310	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1176	----
24311	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1177	----
24312	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1178	----
24313	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1179	----
24314	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1180	----
24315	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1181	----
24316	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1182	----
24317	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1183	----
24318	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1184	----
24319	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1185	----
24320	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1186	----
24321	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1187	----
24322	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1188	----
24323	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1189	----
24324	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1190	----
24325	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1191	----
24326	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1192	----
24327	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1193	----
24328	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1194	----
24329	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1195	----
24330	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1196	----
24331	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1197	----
24332	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1198	----
24333	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1199	----
24334	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1200	----
24335	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1201	----
24336	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1202	----
24337	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1203	----
24338	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1204	----
24339	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1205	----
24340	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1206	----
24341	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1207	----
24342	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1208	----
24343	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1209	----
24344	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1210	----
24345	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1211	----
24346	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1212	----
24347	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1213	----
24348	CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1214	----
24349	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1215	----
24350	CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1216	----
24351	CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1217	----
24352	CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1218	----
24353	CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1219	----
24354	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1220	----
24355	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1221	----
24356	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1222	----
24357	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1223	----
24358	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1224	----
24359	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1225	----
24360	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1226	----
24361	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1227	----
24362	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1228	----
24363	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1229	----
24364	CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1230	----
24365	CEFBS_InMicroMips, // CTC2_MM = 1231	----
24366	CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1232	----
24367	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1233	----
24368	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1234	----
24369	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1235	----
24370	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1236	----
24371	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1237	----
24372	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1238	----
24373	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1239	----
24374	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1240	----
24375	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1241	----
24376	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1242	----
24377	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1243	----
24378	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1244	----
24379	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1245	----
24380	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1246	----
24381	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1247	----
24382	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1248	----
24383	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1249	----
24384	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1250	----
24385	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1251	----
24386	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1252	----
24387	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1253	----
24388	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1254	----
24389	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1255	----
24390	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1256	----
24391	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1257	----
24392	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1258	----
24393	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1259	----
24394	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1260	----
24395	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1261	----
24396	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1262	----
24397	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1263	----
24398	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1264	----
24399	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1265	----
24400	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1266	----
24401	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1267	----
24402	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1268	----
24403	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1269	----
24404	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1270	----
24405	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1271	----
24406	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1272	----
24407	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1273	----
24408	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1274	----
24409	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1275	----
24410	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1276	----
24411	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1277	----
24412	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1278	----
24413	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1279	----
24414	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1280	----
24415	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1281	----
24416	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1282	----
24417	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1283	----
24418	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1284	----
24419	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1285	----
24420	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1286	----
24421	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1287	----
24422	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1288	----
24423	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1289	----
24424	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1290	----
24425	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1291	----
24426	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1292	----
24427	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1293	----
24428	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1294	----
24429	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1295	----
24430	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1296	----
24431	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1297	----
24432	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1298	----
24433	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1299	----
24434	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1300	----
24435	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1301	----
24436	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1302	----
24437	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1303	----
24438	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1304	----
24439	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1305	----
24440	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1306	----
24441	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1307	----
24442	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1308	----
24443	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1309	----
24444	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1310	----
24445	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1311	----
24446	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1312	----
24447	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1313	----
24448	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1314	----
24449	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1315	----
24450	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1316	----
24451	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1317	----
24452	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1318	----
24453	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1319	----
24454	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1320	----
24455	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1321	----
24456	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1322	----
24457	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1323	----
24458	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1324	----
24459	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1325	----
24460	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1326	----
24461	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1327	----
24462	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1328	----
24463	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1329	----
24464	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1330	----
24465	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1331	----
24466	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1332	----
24467	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1333	----
24468	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1334	----
24469	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1335	----
24470	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1336	----
24471	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1337	----
24472	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1338	----
24473	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1339	----
24474	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1340	----
24475	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1341	----
24476	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1342	----
24477	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1343	----
24478	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1344	----
24479	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1345	----
24480	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1346	----
24481	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1347	----
24482	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1348	----
24483	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1349	----
24484	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1350	----
24485	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1351	----
24486	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1352	----
24487	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1353	----
24488	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1354	----
24489	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1355	----
24490	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1356	----
24491	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1357	----
24492	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1358	----
24493	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1359	----
24494	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1360	----
24495	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1361	----
24496	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1362	----
24497	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1363	----
24498	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1364	----
24499	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1365	----
24500	CEFBS_InMips16Mode, // CmpRxRy16 = 1366	----
24501	CEFBS_InMips16Mode, // CmpiRxImm16 = 1367	----
24502	CEFBS_InMips16Mode, // CmpiRxImmX16 = 1368	----
24503	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1369	----
24504	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1370	----
24505	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1371	----
24506	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1372	----
24507	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1373	----
24508	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1374	----
24509	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1375	----
24510	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1376	----
24511	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1377	----
24512	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1378	----
24513	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1379	----
24514	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1380	----
24515	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1381	----
24516	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1382	----
24517	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1383	----
24518	CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1384	----
24519	CEFBS_InMicroMips, // DERET_MM = 1385	----
24520	CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1386	----
24521	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1387	----
24522	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1388	----
24523	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1389	----
24524	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1390	----
24525	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1391	----
24526	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1392	----
24527	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1393	----
24528	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1394	----
24529	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1395	----
24530	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1396	----
24531	CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1397	----
24532	CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1398	----
24533	CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1399	----
24534	CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1400	----
24535	CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1401	----
24536	CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1402	----
24537	CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1403	----
24538	CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1404	----
24539	CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1405	----
24540	CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1406	----
24541	CEFBS_InMicroMips, // DI_MM = 1407	----
24542	CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1408	----
24543	CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1409	----
24544	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1410	----
24545	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1411	----
24546	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1412	----
24547	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1413	----
24548	CEFBS_HasCnMips, // DMFC2_OCTEON = 1414	----
24549	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1415	----
24550	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1416	----
24551	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1417	----
24552	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1418	----
24553	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1419	----
24554	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1420	----
24555	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1421	----
24556	CEFBS_HasCnMips, // DMTC2_OCTEON = 1422	----
24557	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1423	----
24558	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1424	----
24559	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1425	----
24560	CEFBS_HasCnMips, // DMUL = 1426	----
24561	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1427	----
24562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1428	----
24563	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1429	----
24564	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1430	----
24565	CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1431	----
24566	CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1432	----
24567	CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1433	----
24568	CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1434	----
24569	CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1435	----
24570	CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1436	----
24571	CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1437	----
24572	CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1438	----
24573	CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1439	----
24574	CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1440	----
24575	CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1441	----
24576	CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1442	----
24577	CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1443	----
24578	CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1444	----
24579	CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1445	----
24580	CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1446	----
24581	CEFBS_HasDSP, // DPAQ_SA_L_W = 1447	----
24582	CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1448	----
24583	CEFBS_HasDSP, // DPAQ_S_W_PH = 1449	----
24584	CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1450	----
24585	CEFBS_HasDSP, // DPAU_H_QBL = 1451	----
24586	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1452	----
24587	CEFBS_HasDSP, // DPAU_H_QBR = 1453	----
24588	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1454	----
24589	CEFBS_HasDSPR2, // DPAX_W_PH = 1455	----
24590	CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1456	----
24591	CEFBS_HasDSPR2, // DPA_W_PH = 1457	----
24592	CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1458	----
24593	CEFBS_HasCnMips, // DPOP = 1459	----
24594	CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1460	----
24595	CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1461	----
24596	CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1462	----
24597	CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1463	----
24598	CEFBS_HasDSP, // DPSQ_SA_L_W = 1464	----
24599	CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1465	----
24600	CEFBS_HasDSP, // DPSQ_S_W_PH = 1466	----
24601	CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1467	----
24602	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1468	----
24603	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1469	----
24604	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1470	----
24605	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1471	----
24606	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1472	----
24607	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1473	----
24608	CEFBS_HasDSP, // DPSU_H_QBL = 1474	----
24609	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1475	----
24610	CEFBS_HasDSP, // DPSU_H_QBR = 1476	----
24611	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1477	----
24612	CEFBS_HasDSPR2, // DPSX_W_PH = 1478	----
24613	CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1479	----
24614	CEFBS_HasDSPR2, // DPS_W_PH = 1480	----
24615	CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1481	----
24616	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1482	----
24617	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1483	----
24618	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1484	----
24619	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1485	----
24620	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1486	----
24621	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1487	----
24622	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1488	----
24623	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1489	----
24624	CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1490	----
24625	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1491	----
24626	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1492	----
24627	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1493	----
24628	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1494	----
24629	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1495	----
24630	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1496	----
24631	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1497	----
24632	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1498	----
24633	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1499	----
24634	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1500	----
24635	CEFBS_HasStdEnc_HasMips32r6, // DVP = 1501	----
24636	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1502	----
24637	CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1503	----
24638	CEFBS_InMips16Mode, // DivRxRy16 = 1504	----
24639	CEFBS_InMips16Mode, // DivuRxRy16 = 1505	----
24640	CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1506	----
24641	CEFBS_InMicroMips, // EHB_MM = 1507	----
24642	CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1508	----
24643	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1509	----
24644	CEFBS_InMicroMips, // EI_MM = 1510	----
24645	CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1511	----
24646	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1512	----
24647	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1513	----
24648	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1514	----
24649	CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1515	----
24650	CEFBS_InMicroMips, // ERET_MM = 1516	----
24651	CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1517	----
24652	CEFBS_HasStdEnc_HasMips32r6, // EVP = 1518	----
24653	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1519	----
24654	CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1520	----
24655	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1521	----
24656	CEFBS_HasDSP, // EXTP = 1522	----
24657	CEFBS_HasDSP, // EXTPDP = 1523	----
24658	CEFBS_HasDSP, // EXTPDPV = 1524	----
24659	CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1525	----
24660	CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1526	----
24661	CEFBS_HasDSP, // EXTPV = 1527	----
24662	CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1528	----
24663	CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1529	----
24664	CEFBS_HasDSP, // EXTRV_RS_W = 1530	----
24665	CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1531	----
24666	CEFBS_HasDSP, // EXTRV_R_W = 1532	----
24667	CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1533	----
24668	CEFBS_HasDSP, // EXTRV_S_H = 1534	----
24669	CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1535	----
24670	CEFBS_HasDSP, // EXTRV_W = 1536	----
24671	CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1537	----
24672	CEFBS_HasDSP, // EXTR_RS_W = 1538	----
24673	CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1539	----
24674	CEFBS_HasDSP, // EXTR_R_W = 1540	----
24675	CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1541	----
24676	CEFBS_HasDSP, // EXTR_S_H = 1542	----
24677	CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1543	----
24678	CEFBS_HasDSP, // EXTR_W = 1544	----
24679	CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1545	----
24680	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1546	----
24681	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1547	----
24682	CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1548	----
24683	CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1549	----
24684	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1550	----
24685	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1551	----
24686	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1552	----
24687	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1553	----
24688	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1554	----
24689	CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1555	----
24690	CEFBS_HasStdEnc_HasMSA, // FADD_D = 1556	----
24691	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1557	----
24692	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1558	----
24693	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1559	----
24694	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1560	----
24695	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1561	----
24696	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1562	----
24697	CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1563	----
24698	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1564	----
24699	CEFBS_HasStdEnc_HasMSA, // FADD_W = 1565	----
24700	CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1566	----
24701	CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1567	----
24702	CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1568	----
24703	CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1569	----
24704	CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1570	----
24705	CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1571	----
24706	CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1572	----
24707	CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1573	----
24708	CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1574	----
24709	CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1575	----
24710	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1576	----
24711	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1577	----
24712	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1578	----
24713	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1579	----
24714	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1580	----
24715	CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1581	----
24716	CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1582	----
24717	CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1583	----
24718	CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1584	----
24719	CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1585	----
24720	CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1586	----
24721	CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1587	----
24722	CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1588	----
24723	CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1589	----
24724	CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1590	----
24725	CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1591	----
24726	CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1592	----
24727	CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1593	----
24728	CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1594	----
24729	CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1595	----
24730	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1596	----
24731	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1597	----
24732	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1598	----
24733	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1599	----
24734	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1600	----
24735	CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1601	----
24736	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1602	----
24737	CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1603	----
24738	CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1604	----
24739	CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1605	----
24740	CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1606	----
24741	CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1607	----
24742	CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1608	----
24743	CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1609	----
24744	CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1610	----
24745	CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1611	----
24746	CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1612	----
24747	CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1613	----
24748	CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1614	----
24749	CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1615	----
24750	CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1616	----
24751	CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1617	----
24752	CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1618	----
24753	CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1619	----
24754	CEFBS_HasStdEnc_HasMSA, // FILL_B = 1620	----
24755	CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1621	----
24756	CEFBS_HasStdEnc_HasMSA, // FILL_H = 1622	----
24757	CEFBS_HasStdEnc_HasMSA, // FILL_W = 1623	----
24758	CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1624	----
24759	CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1625	----
24760	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1626	----
24761	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1627	----
24762	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1628	----
24763	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1629	----
24764	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1630	----
24765	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1631	----
24766	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1632	----
24767	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1633	----
24768	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1634	----
24769	CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1635	----
24770	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1636	----
24771	CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1637	----
24772	CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1638	----
24773	CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1639	----
24774	CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1640	----
24775	CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1641	----
24776	CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1642	----
24777	CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1643	----
24778	CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1644	----
24779	CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1645	----
24780	CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1646	----
24781	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1647	----
24782	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1648	----
24783	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1649	----
24784	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1650	----
24785	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1651	----
24786	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1652	----
24787	CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1653	----
24788	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1654	----
24789	CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1655	----
24790	CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1656	----
24791	CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1657	----
24792	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1658	----
24793	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1659	----
24794	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1660	----
24795	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1661	----
24796	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1662	----
24797	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1663	----
24798	CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1664	----
24799	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1665	----
24800	CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1666	----
24801	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1667	----
24802	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1668	----
24803	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1669	----
24804	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1670	----
24805	CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1671	----
24806	CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1672	----
24807	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1673	----
24808	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1674	----
24809	CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1675	----
24810	CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1676	----
24811	CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1677	----
24812	CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1678	----
24813	CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1679	----
24814	CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1680	----
24815	CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1681	----
24816	CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1682	----
24817	CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1683	----
24818	CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1684	----
24819	CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1685	----
24820	CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1686	----
24821	CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1687	----
24822	CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1688	----
24823	CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1689	----
24824	CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1690	----
24825	CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1691	----
24826	CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1692	----
24827	CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1693	----
24828	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1694	----
24829	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1695	----
24830	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1696	----
24831	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1697	----
24832	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1698	----
24833	CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1699	----
24834	CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1700	----
24835	CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1701	----
24836	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1702	----
24837	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1703	----
24838	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1704	----
24839	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1705	----
24840	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1706	----
24841	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1707	----
24842	CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1708	----
24843	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1709	----
24844	CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1710	----
24845	CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1711	----
24846	CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1712	----
24847	CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1713	----
24848	CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1714	----
24849	CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1715	----
24850	CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1716	----
24851	CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1717	----
24852	CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1718	----
24853	CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1719	----
24854	CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1720	----
24855	CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1721	----
24856	CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1722	----
24857	CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1723	----
24858	CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1724	----
24859	CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1725	----
24860	CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1726	----
24861	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1727	----
24862	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1728	----
24863	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1729	----
24864	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1730	----
24865	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1731	----
24866	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1732	----
24867	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1733	----
24868	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1734	----
24869	CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1735	----
24870	CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1736	----
24871	CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1737	----
24872	CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1738	----
24873	CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1739	----
24874	CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1740	----
24875	CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1741	----
24876	CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1742	----
24877	CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1743	----
24878	CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1744	----
24879	CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1745	----
24880	CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1746	----
24881	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1747	----
24882	CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1748	----
24883	CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1749	----
24884	CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1750	----
24885	CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1751	----
24886	CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1752	----
24887	CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1753	----
24888	CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1754	----
24889	CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1755	----
24890	CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1756	----
24891	CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1757	----
24892	CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1758	----
24893	CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1759	----
24894	CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1760	----
24895	CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1761	----
24896	CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1762	----
24897	CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1763	----
24898	CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1764	----
24899	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1765	----
24900	CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1766	----
24901	CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1767	----
24902	CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1768	----
24903	CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1769	----
24904	CEFBS_HasDSP, // INSV = 1770	----
24905	CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1771	----
24906	CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1772	----
24907	CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1773	----
24908	CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1774	----
24909	CEFBS_InMicroMips_HasDSP, // INSV_MM = 1775	----
24910	CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1776	----
24911	CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1777	----
24912	CEFBS_HasStdEnc_NotInMicroMips, // J = 1778	----
24913	CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1779	----
24914	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1780	----
24915	CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1781	----
24916	CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1782	----
24917	CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1783	----
24918	CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1784	----
24919	CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1785	----
24920	CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1786	----
24921	CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1787	----
24922	CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1788	----
24923	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1789	----
24924	CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1790	----
24925	CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1791	----
24926	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1792	----
24927	CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1793	----
24928	CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1794	----
24929	CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1795	----
24930	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1796	----
24931	CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1797	----
24932	CEFBS_HasStdEnc_HasMips32r6, // JIC = 1798	----
24933	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1799	----
24934	CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1800	----
24935	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1801	----
24936	CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1802	----
24937	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1803	----
24938	CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1804	----
24939	CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1805	----
24940	CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1806	----
24941	CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1807	----
24942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1808	----
24943	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1809	----
24944	CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1810	----
24945	CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1811	----
24946	CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1812	----
24947	CEFBS_InMicroMips_NotMips32r6, // J_MM = 1813	----
24948	CEFBS_InMips16Mode, // Jal16 = 1814	----
24949	CEFBS_InMips16Mode, // JalB16 = 1815	----
24950	CEFBS_InMips16Mode, // JrRa16 = 1816	----
24951	CEFBS_InMips16Mode, // JrcRa16 = 1817	----
24952	CEFBS_InMips16Mode, // JrcRx16 = 1818	----
24953	CEFBS_InMips16Mode, // JumpLinkReg16 = 1819	----
24954	CEFBS_HasStdEnc_NotInMicroMips, // LB = 1820	----
24955	CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1821	----
24956	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1822	----
24957	CEFBS_InMicroMips_HasEVA, // LBE_MM = 1823	----
24958	CEFBS_InMicroMips, // LBU16_MM = 1824	----
24959	CEFBS_HasDSP, // LBUX = 1825	----
24960	CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1826	----
24961	CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1827	----
24962	CEFBS_InMicroMips, // LB_MM = 1828	----
24963	CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1829	----
24964	CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1830	----
24965	CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1831	----
24966	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1832	----
24967	CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1833	----
24968	CEFBS_InMicroMips, // LBu_MM = 1834	----
24969	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1835	----
24970	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1836	----
24971	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1837	----
24972	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1838	----
24973	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1839	----
24974	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1840	----
24975	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1841	----
24976	CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1842	----
24977	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1843	----
24978	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1844	----
24979	CEFBS_HasStdEnc_HasMSA, // LDI_B = 1845	----
24980	CEFBS_HasStdEnc_HasMSA, // LDI_D = 1846	----
24981	CEFBS_HasStdEnc_HasMSA, // LDI_H = 1847	----
24982	CEFBS_HasStdEnc_HasMSA, // LDI_W = 1848	----
24983	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1849	----
24984	CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1850	----
24985	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1851	----
24986	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1852	----
24987	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1853	----
24988	CEFBS_HasStdEnc_HasMSA, // LD_B = 1854	----
24989	CEFBS_HasStdEnc_HasMSA, // LD_D = 1855	----
24990	CEFBS_HasStdEnc_HasMSA, // LD_H = 1856	----
24991	CEFBS_HasStdEnc_HasMSA, // LD_W = 1857	----
24992	CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1858	----
24993	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1859	----
24994	CEFBS_InMicroMips, // LEA_ADDiu_MM = 1860	----
24995	CEFBS_HasStdEnc_NotInMicroMips, // LH = 1861	----
24996	CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1862	----
24997	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1863	----
24998	CEFBS_InMicroMips_HasEVA, // LHE_MM = 1864	----
24999	CEFBS_InMicroMips, // LHU16_MM = 1865	----
25000	CEFBS_HasDSP, // LHX = 1866	----
25001	CEFBS_InMicroMips_HasDSP, // LHX_MM = 1867	----
25002	CEFBS_InMicroMips, // LH_MM = 1868	----
25003	CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1869	----
25004	CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1870	----
25005	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1871	----
25006	CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1872	----
25007	CEFBS_InMicroMips, // LHu_MM = 1873	----
25008	CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1874	----
25009	CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1875	----
25010	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1876	----
25011	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1877	----
25012	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1878	----
25013	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1879	----
25014	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1880	----
25015	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1881	----
25016	CEFBS_InMicroMips_HasEVA, // LLE_MM = 1882	----
25017	CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1883	----
25018	CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1884	----
25019	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1885	----
25020	CEFBS_HasStdEnc_HasMSA, // LSA = 1886	----
25021	CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1887	----
25022	CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1888	----
25023	CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1889	----
25024	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1890	----
25025	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1891	----
25026	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1892	----
25027	CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1893	----
25028	CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1894	----
25029	CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1895	----
25030	CEFBS_HasStdEnc_NotInMicroMips, // LW = 1896	----
25031	CEFBS_InMicroMips, // LW16_MM = 1897	----
25032	CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1898	----
25033	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1899	----
25034	CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1900	----
25035	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1901	----
25036	CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1902	----
25037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1903	----
25038	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1904	----
25039	CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1905	----
25040	CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1906	----
25041	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1907	----
25042	CEFBS_InMicroMips_HasEVA, // LWE_MM = 1908	----
25043	CEFBS_InMicroMips, // LWGP_MM = 1909	----
25044	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1910	----
25045	CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1911	----
25046	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1912	----
25047	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1913	----
25048	CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1914	----
25049	CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1915	----
25050	CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1916	----
25051	CEFBS_InMicroMips, // LWM32_MM = 1917	----
25052	CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1918	----
25053	CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1919	----
25054	CEFBS_InMicroMips, // LWP_MM = 1920	----
25055	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1921	----
25056	CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1922	----
25057	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1923	----
25058	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1924	----
25059	CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1925	----
25060	CEFBS_InMicroMips, // LWSP_MM = 1926	----
25061	CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1927	----
25062	CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1928	----
25063	CEFBS_HasDSP, // LWX = 1929	----
25064	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1930	----
25065	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1931	----
25066	CEFBS_InMicroMips, // LWXS_MM = 1932	----
25067	CEFBS_InMicroMips_HasDSP, // LWX_MM = 1933	----
25068	CEFBS_InMicroMips, // LW_MM = 1934	----
25069	CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1935	----
25070	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1936	----
25071	CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1937	----
25072	CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1938	----
25073	CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1939	----
25074	CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1940	----
25075	CEFBS_InMips16Mode, // LiRxImm16 = 1941	----
25076	CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1942	----
25077	CEFBS_InMips16Mode, // LiRxImmX16 = 1943	----
25078	CEFBS_InMips16Mode, // LwRxPcTcp16 = 1944	----
25079	CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1945	----
25080	CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1946	----
25081	CEFBS_InMips16Mode, // LwRxSpImmX16 = 1947	----
25082	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1948	----
25083	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1949	----
25084	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1950	----
25085	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1951	----
25086	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1952	----
25087	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1953	----
25088	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1954	----
25089	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1955	----
25090	CEFBS_HasDSP, // MADDU_DSP = 1956	----
25091	CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1957	----
25092	CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1958	----
25093	CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1959	----
25094	CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1960	----
25095	CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1961	----
25096	CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1962	----
25097	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1963	----
25098	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1964	----
25099	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1965	----
25100	CEFBS_HasDSP, // MADD_DSP = 1966	----
25101	CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1967	----
25102	CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1968	----
25103	CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1969	----
25104	CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1970	----
25105	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1971	----
25106	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1972	----
25107	CEFBS_HasDSP, // MAQ_SA_W_PHL = 1973	----
25108	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1974	----
25109	CEFBS_HasDSP, // MAQ_SA_W_PHR = 1975	----
25110	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1976	----
25111	CEFBS_HasDSP, // MAQ_S_W_PHL = 1977	----
25112	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1978	----
25113	CEFBS_HasDSP, // MAQ_S_W_PHR = 1979	----
25114	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1980	----
25115	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1981	----
25116	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1982	----
25117	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1983	----
25118	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1984	----
25119	CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1985	----
25120	CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1986	----
25121	CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1987	----
25122	CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1988	----
25123	CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1989	----
25124	CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1990	----
25125	CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1991	----
25126	CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1992	----
25127	CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1993	----
25128	CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1994	----
25129	CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1995	----
25130	CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1996	----
25131	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1997	----
25132	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1998	----
25133	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1999	----
25134	CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2000	----
25135	CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2001	----
25136	CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2002	----
25137	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2003	----
25138	CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2004	----
25139	CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2005	----
25140	CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2006	----
25141	CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2007	----
25142	CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2008	----
25143	CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2009	----
25144	CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2010	----
25145	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2011	----
25146	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2012	----
25147	CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2013	----
25148	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2014	----
25149	CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2015	----
25150	CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2016	----
25151	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2017	----
25152	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2018	----
25153	CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2019	----
25154	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2020	----
25155	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2021	----
25156	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2022	----
25157	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2023	----
25158	CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2024	----
25159	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2025	----
25160	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2026	----
25161	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2027	----
25162	CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2028	----
25163	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2029	----
25164	CEFBS_HasDSP, // MFHI_DSP = 2030	----
25165	CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2031	----
25166	CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2032	----
25167	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2033	----
25168	CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2034	----
25169	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2035	----
25170	CEFBS_HasDSP, // MFLO_DSP = 2036	----
25171	CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2037	----
25172	CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2038	----
25173	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2039	----
25174	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2040	----
25175	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2041	----
25176	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2042	----
25177	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2043	----
25178	CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2044	----
25179	CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2045	----
25180	CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2046	----
25181	CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2047	----
25182	CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2048	----
25183	CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2049	----
25184	CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2050	----
25185	CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2051	----
25186	CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2052	----
25187	CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2053	----
25188	CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2054	----
25189	CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2055	----
25190	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2056	----
25191	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2057	----
25192	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2058	----
25193	CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2059	----
25194	CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2060	----
25195	CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2061	----
25196	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2062	----
25197	CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2063	----
25198	CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2064	----
25199	CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2065	----
25200	CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2066	----
25201	CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2067	----
25202	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2068	----
25203	CEFBS_HasDSP, // MODSUB = 2069	----
25204	CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2070	----
25205	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2071	----
25206	CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2072	----
25207	CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2073	----
25208	CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2074	----
25209	CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2075	----
25210	CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2076	----
25211	CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2077	----
25212	CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2078	----
25213	CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2079	----
25214	CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2080	----
25215	CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2081	----
25216	CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2082	----
25217	CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2083	----
25218	CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2084	----
25219	CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2085	----
25220	CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2086	----
25221	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2087	----
25222	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2088	----
25223	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2089	----
25224	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2090	----
25225	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2091	----
25226	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2092	----
25227	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2093	----
25228	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2094	----
25229	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2095	----
25230	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2096	----
25231	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2097	----
25232	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2098	----
25233	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2099	----
25234	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2100	----
25235	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2101	----
25236	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2102	----
25237	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2103	----
25238	CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2104	----
25239	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2105	----
25240	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2106	----
25241	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2107	----
25242	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2108	----
25243	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2109	----
25244	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2110	----
25245	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2111	----
25246	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2112	----
25247	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2113	----
25248	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2114	----
25249	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2115	----
25250	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2116	----
25251	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2117	----
25252	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2118	----
25253	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2119	----
25254	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2120	----
25255	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2121	----
25256	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2122	----
25257	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2123	----
25258	CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2124	----
25259	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2125	----
25260	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2126	----
25261	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2127	----
25262	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2128	----
25263	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2129	----
25264	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2130	----
25265	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2131	----
25266	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2132	----
25267	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2133	----
25268	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2134	----
25269	CEFBS_HasDSP, // MSUBU_DSP = 2135	----
25270	CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2136	----
25271	CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2137	----
25272	CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2138	----
25273	CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2139	----
25274	CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2140	----
25275	CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2141	----
25276	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2142	----
25277	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2143	----
25278	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2144	----
25279	CEFBS_HasDSP, // MSUB_DSP = 2145	----
25280	CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2146	----
25281	CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2147	----
25282	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2148	----
25283	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2149	----
25284	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2150	----
25285	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2151	----
25286	CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2152	----
25287	CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2153	----
25288	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2154	----
25289	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2155	----
25290	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2156	----
25291	CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2157	----
25292	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2158	----
25293	CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2159	----
25294	CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2160	----
25295	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2161	----
25296	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2162	----
25297	CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2163	----
25298	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2164	----
25299	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2165	----
25300	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2166	----
25301	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2167	----
25302	CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2168	----
25303	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2169	----
25304	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2170	----
25305	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2171	----
25306	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2172	----
25307	CEFBS_HasDSP, // MTHI_DSP = 2173	----
25308	CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2174	----
25309	CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2175	----
25310	CEFBS_HasDSP, // MTHLIP = 2176	----
25311	CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2177	----
25312	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2178	----
25313	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2179	----
25314	CEFBS_HasDSP, // MTLO_DSP = 2180	----
25315	CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2181	----
25316	CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2182	----
25317	CEFBS_HasCnMips, // MTM0 = 2183	----
25318	CEFBS_HasCnMips, // MTM1 = 2184	----
25319	CEFBS_HasCnMips, // MTM2 = 2185	----
25320	CEFBS_HasCnMips, // MTP0 = 2186	----
25321	CEFBS_HasCnMips, // MTP1 = 2187	----
25322	CEFBS_HasCnMips, // MTP2 = 2188	----
25323	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2189	----
25324	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2190	----
25325	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2191	----
25326	CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2192	----
25327	CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2193	----
25328	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2194	----
25329	CEFBS_HasDSP, // MULEQ_S_W_PHL = 2195	----
25330	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2196	----
25331	CEFBS_HasDSP, // MULEQ_S_W_PHR = 2197	----
25332	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2198	----
25333	CEFBS_HasDSP, // MULEU_S_PH_QBL = 2199	----
25334	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2200	----
25335	CEFBS_HasDSP, // MULEU_S_PH_QBR = 2201	----
25336	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2202	----
25337	CEFBS_HasDSP, // MULQ_RS_PH = 2203	----
25338	CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2204	----
25339	CEFBS_HasDSPR2, // MULQ_RS_W = 2205	----
25340	CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2206	----
25341	CEFBS_HasDSPR2, // MULQ_S_PH = 2207	----
25342	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2208	----
25343	CEFBS_HasDSPR2, // MULQ_S_W = 2209	----
25344	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2210	----
25345	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2211	----
25346	CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2212	----
25347	CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2213	----
25348	CEFBS_HasDSP, // MULSAQ_S_W_PH = 2214	----
25349	CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2215	----
25350	CEFBS_HasDSPR2, // MULSA_W_PH = 2216	----
25351	CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2217	----
25352	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2218	----
25353	CEFBS_HasDSP, // MULTU_DSP = 2219	----
25354	CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2220	----
25355	CEFBS_HasDSP, // MULT_DSP = 2221	----
25356	CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2222	----
25357	CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2223	----
25358	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2224	----
25359	CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2225	----
25360	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2226	----
25361	CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2227	----
25362	CEFBS_HasStdEnc_HasMSA, // MULV_B = 2228	----
25363	CEFBS_HasStdEnc_HasMSA, // MULV_D = 2229	----
25364	CEFBS_HasStdEnc_HasMSA, // MULV_H = 2230	----
25365	CEFBS_HasStdEnc_HasMSA, // MULV_W = 2231	----
25366	CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2232	----
25367	CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2233	----
25368	CEFBS_HasDSPR2, // MUL_PH = 2234	----
25369	CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2235	----
25370	CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2236	----
25371	CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2237	----
25372	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2238	----
25373	CEFBS_HasDSPR2, // MUL_S_PH = 2239	----
25374	CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2240	----
25375	CEFBS_InMips16Mode, // Mfhi16 = 2241	----
25376	CEFBS_InMips16Mode, // Mflo16 = 2242	----
25377	CEFBS_InMips16Mode, // Move32R16 = 2243	----
25378	CEFBS_InMips16Mode, // MoveR3216 = 2244	----
25379	CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2245	----
25380	CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2246	----
25381	CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2247	----
25382	CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2248	----
25383	CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2249	----
25384	CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2250	----
25385	CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2251	----
25386	CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2252	----
25387	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2253	----
25388	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2254	----
25389	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2255	----
25390	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2256	----
25391	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2257	----
25392	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2258	----
25393	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2259	----
25394	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2260	----
25395	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2261	----
25396	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2262	----
25397	CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2263	----
25398	CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2264	----
25399	CEFBS_HasStdEnc_HasMSA, // NORI_B = 2265	----
25400	CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2266	----
25401	CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2267	----
25402	CEFBS_HasStdEnc_HasMSA, // NOR_V = 2268	----
25403	CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2269	----
25404	CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2270	----
25405	CEFBS_InMips16Mode, // NegRxRy16 = 2271	----
25406	CEFBS_InMips16Mode, // NotRxRy16 = 2272	----
25407	CEFBS_HasStdEnc_NotInMicroMips, // OR = 2273	----
25408	CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2274	----
25409	CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2275	----
25410	CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2276	----
25411	CEFBS_HasStdEnc_HasMSA, // ORI_B = 2277	----
25412	CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2278	----
25413	CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2279	----
25414	CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2280	----
25415	CEFBS_HasStdEnc_HasMSA, // OR_V = 2281	----
25416	CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2282	----
25417	CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2283	----
25418	CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2284	----
25419	CEFBS_InMips16Mode, // OrRxRxRy16 = 2285	----
25420	CEFBS_HasDSP, // PACKRL_PH = 2286	----
25421	CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2287	----
25422	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2288	----
25423	CEFBS_InMicroMips, // PAUSE_MM = 2289	----
25424	CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2290	----
25425	CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2291	----
25426	CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2292	----
25427	CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2293	----
25428	CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2294	----
25429	CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2295	----
25430	CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2296	----
25431	CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2297	----
25432	CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2298	----
25433	CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2299	----
25434	CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2300	----
25435	CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2301	----
25436	CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2302	----
25437	CEFBS_HasDSP, // PICK_PH = 2303	----
25438	CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2304	----
25439	CEFBS_HasDSP, // PICK_QB = 2305	----
25440	CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2306	----
25441	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2307	----
25442	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2308	----
25443	CEFBS_HasCnMips, // POP = 2309	----
25444	CEFBS_HasDSP, // PRECEQU_PH_QBL = 2310	----
25445	CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2311	----
25446	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2312	----
25447	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2313	----
25448	CEFBS_HasDSP, // PRECEQU_PH_QBR = 2314	----
25449	CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2315	----
25450	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2316	----
25451	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2317	----
25452	CEFBS_HasDSP, // PRECEQ_W_PHL = 2318	----
25453	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2319	----
25454	CEFBS_HasDSP, // PRECEQ_W_PHR = 2320	----
25455	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2321	----
25456	CEFBS_HasDSP, // PRECEU_PH_QBL = 2322	----
25457	CEFBS_HasDSP, // PRECEU_PH_QBLA = 2323	----
25458	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2324	----
25459	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2325	----
25460	CEFBS_HasDSP, // PRECEU_PH_QBR = 2326	----
25461	CEFBS_HasDSP, // PRECEU_PH_QBRA = 2327	----
25462	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2328	----
25463	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2329	----
25464	CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2330	----
25465	CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2331	----
25466	CEFBS_HasDSP, // PRECRQ_PH_W = 2332	----
25467	CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2333	----
25468	CEFBS_HasDSP, // PRECRQ_QB_PH = 2334	----
25469	CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2335	----
25470	CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2336	----
25471	CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2337	----
25472	CEFBS_HasDSPR2, // PRECR_QB_PH = 2338	----
25473	CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2339	----
25474	CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2340	----
25475	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2341	----
25476	CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2342	----
25477	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2343	----
25478	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2344	----
25479	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2345	----
25480	CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2346	----
25481	CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2347	----
25482	CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2348	----
25483	CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2349	----
25484	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2350	----
25485	CEFBS_HasDSPR2, // PREPEND = 2351	----
25486	CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2352	----
25487	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2353	----
25488	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2354	----
25489	CEFBS_HasDSP, // RADDU_W_QB = 2355	----
25490	CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2356	----
25491	CEFBS_HasDSP, // RDDSP = 2357	----
25492	CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2358	----
25493	CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2359	----
25494	CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2360	----
25495	CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2361	----
25496	CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2362	----
25497	CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2363	----
25498	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2364	----
25499	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2365	----
25500	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2366	----
25501	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2367	----
25502	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2368	----
25503	CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2369	----
25504	CEFBS_HasDSP, // REPLV_PH = 2370	----
25505	CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2371	----
25506	CEFBS_HasDSP, // REPLV_QB = 2372	----
25507	CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2373	----
25508	CEFBS_HasDSP, // REPL_PH = 2374	----
25509	CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2375	----
25510	CEFBS_HasDSP, // REPL_QB = 2376	----
25511	CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2377	----
25512	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2378	----
25513	CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2379	----
25514	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2380	----
25515	CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2381	----
25516	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2382	----
25517	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2383	----
25518	CEFBS_InMicroMips, // ROTRV_MM = 2384	----
25519	CEFBS_InMicroMips, // ROTR_MM = 2385	----
25520	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2386	----
25521	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2387	----
25522	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2388	----
25523	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2389	----
25524	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2390	----
25525	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2391	----
25526	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2392	----
25527	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2393	----
25528	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2394	----
25529	CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2395	----
25530	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2396	----
25531	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2397	----
25532	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2398	----
25533	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2399	----
25534	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2400	----
25535	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2401	----
25536	CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2402	----
25537	CEFBS_InMips16Mode, // Restore16 = 2403	----
25538	CEFBS_InMips16Mode, // RestoreX16 = 2404	----
25539	CEFBS_HasCnMipsP, // SAA = 2405	----
25540	CEFBS_HasCnMipsP, // SAAD = 2406	----
25541	CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2407	----
25542	CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2408	----
25543	CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2409	----
25544	CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2410	----
25545	CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2411	----
25546	CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2412	----
25547	CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2413	----
25548	CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2414	----
25549	CEFBS_HasStdEnc_NotInMicroMips, // SB = 2415	----
25550	CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2416	----
25551	CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2417	----
25552	CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2418	----
25553	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2419	----
25554	CEFBS_InMicroMips_HasEVA, // SBE_MM = 2420	----
25555	CEFBS_InMicroMips, // SB_MM = 2421	----
25556	CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2422	----
25557	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2423	----
25558	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2424	----
25559	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2425	----
25560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2426	----
25561	CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2427	----
25562	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2428	----
25563	CEFBS_InMicroMips_HasEVA, // SCE_MM = 2429	----
25564	CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2430	----
25565	CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2431	----
25566	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2432	----
25567	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2433	----
25568	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2434	----
25569	CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2435	----
25570	CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2436	----
25571	CEFBS_InMicroMips, // SDBBP_MM = 2437	----
25572	CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2438	----
25573	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2439	----
25574	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2440	----
25575	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2441	----
25576	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2442	----
25577	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2443	----
25578	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2444	----
25579	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2445	----
25580	CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2446	----
25581	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2447	----
25582	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2448	----
25583	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2449	----
25584	CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2450	----
25585	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2451	----
25586	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2452	----
25587	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2453	----
25588	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2454	----
25589	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2455	----
25590	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2456	----
25591	CEFBS_InMicroMips, // SEB_MM = 2457	----
25592	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2458	----
25593	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2459	----
25594	CEFBS_InMicroMips, // SEH_MM = 2460	----
25595	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2461	----
25596	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2462	----
25597	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2463	----
25598	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2464	----
25599	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2465	----
25600	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2466	----
25601	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2467	----
25602	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2468	----
25603	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2469	----
25604	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2470	----
25605	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2471	----
25606	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2472	----
25607	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2473	----
25608	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2474	----
25609	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2475	----
25610	CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2476	----
25611	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2477	----
25612	CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2478	----
25613	CEFBS_HasCnMips, // SEQ = 2479	----
25614	CEFBS_HasCnMips, // SEQi = 2480	----
25615	CEFBS_HasStdEnc_NotInMicroMips, // SH = 2481	----
25616	CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2482	----
25617	CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2483	----
25618	CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2484	----
25619	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2485	----
25620	CEFBS_InMicroMips_HasEVA, // SHE_MM = 2486	----
25621	CEFBS_HasStdEnc_HasMSA, // SHF_B = 2487	----
25622	CEFBS_HasStdEnc_HasMSA, // SHF_H = 2488	----
25623	CEFBS_HasStdEnc_HasMSA, // SHF_W = 2489	----
25624	CEFBS_HasDSP, // SHILO = 2490	----
25625	CEFBS_HasDSP, // SHILOV = 2491	----
25626	CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2492	----
25627	CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2493	----
25628	CEFBS_HasDSP, // SHLLV_PH = 2494	----
25629	CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2495	----
25630	CEFBS_HasDSP, // SHLLV_QB = 2496	----
25631	CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2497	----
25632	CEFBS_HasDSP, // SHLLV_S_PH = 2498	----
25633	CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2499	----
25634	CEFBS_HasDSP, // SHLLV_S_W = 2500	----
25635	CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2501	----
25636	CEFBS_HasDSP, // SHLL_PH = 2502	----
25637	CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2503	----
25638	CEFBS_HasDSP, // SHLL_QB = 2504	----
25639	CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2505	----
25640	CEFBS_HasDSP, // SHLL_S_PH = 2506	----
25641	CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2507	----
25642	CEFBS_HasDSP, // SHLL_S_W = 2508	----
25643	CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2509	----
25644	CEFBS_HasDSP, // SHRAV_PH = 2510	----
25645	CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2511	----
25646	CEFBS_HasDSPR2, // SHRAV_QB = 2512	----
25647	CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2513	----
25648	CEFBS_HasDSP, // SHRAV_R_PH = 2514	----
25649	CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2515	----
25650	CEFBS_HasDSPR2, // SHRAV_R_QB = 2516	----
25651	CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2517	----
25652	CEFBS_HasDSP, // SHRAV_R_W = 2518	----
25653	CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2519	----
25654	CEFBS_HasDSP, // SHRA_PH = 2520	----
25655	CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2521	----
25656	CEFBS_HasDSPR2, // SHRA_QB = 2522	----
25657	CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2523	----
25658	CEFBS_HasDSP, // SHRA_R_PH = 2524	----
25659	CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2525	----
25660	CEFBS_HasDSPR2, // SHRA_R_QB = 2526	----
25661	CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2527	----
25662	CEFBS_HasDSP, // SHRA_R_W = 2528	----
25663	CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2529	----
25664	CEFBS_HasDSPR2, // SHRLV_PH = 2530	----
25665	CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2531	----
25666	CEFBS_HasDSP, // SHRLV_QB = 2532	----
25667	CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2533	----
25668	CEFBS_HasDSPR2, // SHRL_PH = 2534	----
25669	CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2535	----
25670	CEFBS_HasDSP, // SHRL_QB = 2536	----
25671	CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2537	----
25672	CEFBS_InMicroMips, // SH_MM = 2538	----
25673	CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2539	----
25674	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2540	----
25675	CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2541	----
25676	CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2542	----
25677	CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2543	----
25678	CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2544	----
25679	CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2545	----
25680	CEFBS_HasStdEnc_HasMSA, // SLD_B = 2546	----
25681	CEFBS_HasStdEnc_HasMSA, // SLD_D = 2547	----
25682	CEFBS_HasStdEnc_HasMSA, // SLD_H = 2548	----
25683	CEFBS_HasStdEnc_HasMSA, // SLD_W = 2549	----
25684	CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2550	----
25685	CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2551	----
25686	CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2552	----
25687	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2553	----
25688	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2554	----
25689	CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2555	----
25690	CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2556	----
25691	CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2557	----
25692	CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2558	----
25693	CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2559	----
25694	CEFBS_InMicroMips, // SLLV_MM = 2560	----
25695	CEFBS_HasStdEnc_HasMSA, // SLL_B = 2561	----
25696	CEFBS_HasStdEnc_HasMSA, // SLL_D = 2562	----
25697	CEFBS_HasStdEnc_HasMSA, // SLL_H = 2563	----
25698	CEFBS_InMicroMips, // SLL_MM = 2564	----
25699	CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2565	----
25700	CEFBS_HasStdEnc_HasMSA, // SLL_W = 2566	----
25701	CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2567	----
25702	CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2568	----
25703	CEFBS_InMicroMips, // SLT_MM = 2569	----
25704	CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2570	----
25705	CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2571	----
25706	CEFBS_InMicroMips, // SLTi_MM = 2572	----
25707	CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2573	----
25708	CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2574	----
25709	CEFBS_InMicroMips, // SLTiu_MM = 2575	----
25710	CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2576	----
25711	CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2577	----
25712	CEFBS_InMicroMips, // SLTu_MM = 2578	----
25713	CEFBS_HasCnMips, // SNE = 2579	----
25714	CEFBS_HasCnMips, // SNEi = 2580	----
25715	CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2581	----
25716	CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2582	----
25717	CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2583	----
25718	CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2584	----
25719	CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2585	----
25720	CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2586	----
25721	CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2587	----
25722	CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2588	----
25723	CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2589	----
25724	CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2590	----
25725	CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2591	----
25726	CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2592	----
25727	CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2593	----
25728	CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2594	----
25729	CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2595	----
25730	CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2596	----
25731	CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2597	----
25732	CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2598	----
25733	CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2599	----
25734	CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2600	----
25735	CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2601	----
25736	CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2602	----
25737	CEFBS_InMicroMips, // SRAV_MM = 2603	----
25738	CEFBS_HasStdEnc_HasMSA, // SRA_B = 2604	----
25739	CEFBS_HasStdEnc_HasMSA, // SRA_D = 2605	----
25740	CEFBS_HasStdEnc_HasMSA, // SRA_H = 2606	----
25741	CEFBS_InMicroMips, // SRA_MM = 2607	----
25742	CEFBS_HasStdEnc_HasMSA, // SRA_W = 2608	----
25743	CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2609	----
25744	CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2610	----
25745	CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2611	----
25746	CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2612	----
25747	CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2613	----
25748	CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2614	----
25749	CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2615	----
25750	CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2616	----
25751	CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2617	----
25752	CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2618	----
25753	CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2619	----
25754	CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2620	----
25755	CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2621	----
25756	CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2622	----
25757	CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2623	----
25758	CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2624	----
25759	CEFBS_InMicroMips, // SRLV_MM = 2625	----
25760	CEFBS_HasStdEnc_HasMSA, // SRL_B = 2626	----
25761	CEFBS_HasStdEnc_HasMSA, // SRL_D = 2627	----
25762	CEFBS_HasStdEnc_HasMSA, // SRL_H = 2628	----
25763	CEFBS_InMicroMips, // SRL_MM = 2629	----
25764	CEFBS_HasStdEnc_HasMSA, // SRL_W = 2630	----
25765	CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2631	----
25766	CEFBS_InMicroMips, // SSNOP_MM = 2632	----
25767	CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2633	----
25768	CEFBS_HasStdEnc_HasMSA, // ST_B = 2634	----
25769	CEFBS_HasStdEnc_HasMSA, // ST_D = 2635	----
25770	CEFBS_HasStdEnc_HasMSA, // ST_H = 2636	----
25771	CEFBS_HasStdEnc_HasMSA, // ST_W = 2637	----
25772	CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2638	----
25773	CEFBS_HasDSPR2, // SUBQH_PH = 2639	----
25774	CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2640	----
25775	CEFBS_HasDSPR2, // SUBQH_R_PH = 2641	----
25776	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2642	----
25777	CEFBS_HasDSPR2, // SUBQH_R_W = 2643	----
25778	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2644	----
25779	CEFBS_HasDSPR2, // SUBQH_W = 2645	----
25780	CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2646	----
25781	CEFBS_HasDSP, // SUBQ_PH = 2647	----
25782	CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2648	----
25783	CEFBS_HasDSP, // SUBQ_S_PH = 2649	----
25784	CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2650	----
25785	CEFBS_HasDSP, // SUBQ_S_W = 2651	----
25786	CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2652	----
25787	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2653	----
25788	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2654	----
25789	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2655	----
25790	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2656	----
25791	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2657	----
25792	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2658	----
25793	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2659	----
25794	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2660	----
25795	CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2661	----
25796	CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2662	----
25797	CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2663	----
25798	CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2664	----
25799	CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2665	----
25800	CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2666	----
25801	CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2667	----
25802	CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2668	----
25803	CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2669	----
25804	CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2670	----
25805	CEFBS_HasDSPR2, // SUBUH_QB = 2671	----
25806	CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2672	----
25807	CEFBS_HasDSPR2, // SUBUH_R_QB = 2673	----
25808	CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2674	----
25809	CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2675	----
25810	CEFBS_HasDSPR2, // SUBU_PH = 2676	----
25811	CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2677	----
25812	CEFBS_HasDSP, // SUBU_QB = 2678	----
25813	CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2679	----
25814	CEFBS_HasDSPR2, // SUBU_S_PH = 2680	----
25815	CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2681	----
25816	CEFBS_HasDSP, // SUBU_S_QB = 2682	----
25817	CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2683	----
25818	CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2684	----
25819	CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2685	----
25820	CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2686	----
25821	CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2687	----
25822	CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2688	----
25823	CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2689	----
25824	CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2690	----
25825	CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2691	----
25826	CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2692	----
25827	CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2693	----
25828	CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2694	----
25829	CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2695	----
25830	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2696	----
25831	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2697	----
25832	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2698	----
25833	CEFBS_HasStdEnc_NotInMicroMips, // SW = 2699	----
25834	CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2700	----
25835	CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2701	----
25836	CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2702	----
25837	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2703	----
25838	CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2704	----
25839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2705	----
25840	CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2706	----
25841	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2707	----
25842	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2708	----
25843	CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2709	----
25844	CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2710	----
25845	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2711	----
25846	CEFBS_InMicroMips_HasEVA, // SWE_MM = 2712	----
25847	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2713	----
25848	CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2714	----
25849	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2715	----
25850	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2716	----
25851	CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2717	----
25852	CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2718	----
25853	CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2719	----
25854	CEFBS_InMicroMips, // SWM32_MM = 2720	----
25855	CEFBS_InMicroMips, // SWP_MM = 2721	----
25856	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2722	----
25857	CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2723	----
25858	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2724	----
25859	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2725	----
25860	CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2726	----
25861	CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2727	----
25862	CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2728	----
25863	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2729	----
25864	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2730	----
25865	CEFBS_InMicroMips, // SW_MM = 2731	----
25866	CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2732	----
25867	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2733	----
25868	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2734	----
25869	CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2735	----
25870	CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2736	----
25871	CEFBS_InMicroMips, // SYNC_MM = 2737	----
25872	CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2738	----
25873	CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2739	----
25874	CEFBS_InMicroMips, // SYSCALL_MM = 2740	----
25875	CEFBS_InMips16Mode, // Save16 = 2741	----
25876	CEFBS_InMips16Mode, // SaveX16 = 2742	----
25877	CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2743	----
25878	CEFBS_InMips16Mode, // SebRx16 = 2744	----
25879	CEFBS_InMips16Mode, // SehRx16 = 2745	----
25880	CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2746	----
25881	CEFBS_InMips16Mode, // SllX16 = 2747	----
25882	CEFBS_InMips16Mode, // SllvRxRy16 = 2748	----
25883	CEFBS_InMips16Mode, // SltRxRy16 = 2749	----
25884	CEFBS_InMips16Mode, // SltiRxImm16 = 2750	----
25885	CEFBS_InMips16Mode, // SltiRxImmX16 = 2751	----
25886	CEFBS_InMips16Mode, // SltiuRxImm16 = 2752	----
25887	CEFBS_InMips16Mode, // SltiuRxImmX16 = 2753	----
25888	CEFBS_InMips16Mode, // SltuRxRy16 = 2754	----
25889	CEFBS_InMips16Mode, // SraX16 = 2755	----
25890	CEFBS_InMips16Mode, // SravRxRy16 = 2756	----
25891	CEFBS_InMips16Mode, // SrlX16 = 2757	----
25892	CEFBS_InMips16Mode, // SrlvRxRy16 = 2758	----
25893	CEFBS_InMips16Mode, // SubuRxRyRz16 = 2759	----
25894	CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2760	----
25895	CEFBS_InMips16Mode, // SwRxSpImmX16 = 2761	----
25896	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2762	----
25897	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2763	----
25898	CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2764	----
25899	CEFBS_InMicroMips, // TEQ_MM = 2765	----
25900	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2766	----
25901	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2767	----
25902	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2768	----
25903	CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2769	----
25904	CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2770	----
25905	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2771	----
25906	CEFBS_InMicroMips, // TGEU_MM = 2772	----
25907	CEFBS_InMicroMips, // TGE_MM = 2773	----
25908	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2774	----
25909	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2775	----
25910	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2776	----
25911	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2777	----
25912	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2778	----
25913	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2779	----
25914	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2780	----
25915	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2781	----
25916	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2782	----
25917	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2783	----
25918	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2784	----
25919	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2785	----
25920	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2786	----
25921	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2787	----
25922	CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2788	----
25923	CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2789	----
25924	CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2790	----
25925	CEFBS_InMicroMips, // TLBP_MM = 2791	----
25926	CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2792	----
25927	CEFBS_InMicroMips, // TLBR_MM = 2793	----
25928	CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2794	----
25929	CEFBS_InMicroMips, // TLBWI_MM = 2795	----
25930	CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2796	----
25931	CEFBS_InMicroMips, // TLBWR_MM = 2797	----
25932	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2798	----
25933	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2799	----
25934	CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2800	----
25935	CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2801	----
25936	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2802	----
25937	CEFBS_InMicroMips, // TLTU_MM = 2803	----
25938	CEFBS_InMicroMips, // TLT_MM = 2804	----
25939	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2805	----
25940	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2806	----
25941	CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2807	----
25942	CEFBS_InMicroMips, // TNE_MM = 2808	----
25943	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2809	----
25944	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2810	----
25945	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2811	----
25946	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2812	----
25947	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2813	----
25948	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2814	----
25949	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2815	----
25950	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2816	----
25951	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2817	----
25952	CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2818	----
25953	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2819	----
25954	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2820	----
25955	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2821	----
25956	CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2822	----
25957	CEFBS_HasCnMips, // V3MULU = 2823	----
25958	CEFBS_HasCnMips, // VMM0 = 2824	----
25959	CEFBS_HasCnMips, // VMULU = 2825	----
25960	CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2826	----
25961	CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2827	----
25962	CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2828	----
25963	CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2829	----
25964	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2830	----
25965	CEFBS_InMicroMips, // WAIT_MM = 2831	----
25966	CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2832	----
25967	CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2833	----
25968	CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2834	----
25969	CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2835	----
25970	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2836	----
25971	CEFBS_InMicroMips, // WSBH_MM = 2837	----
25972	CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2838	----
25973	CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2839	----
25974	CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2840	----
25975	CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2841	----
25976	CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2842	----
25977	CEFBS_HasStdEnc_HasMSA, // XORI_B = 2843	----
25978	CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2844	----
25979	CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2845	----
25980	CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2846	----
25981	CEFBS_HasStdEnc_HasMSA, // XOR_V = 2847	----
25982	CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2848	----
25983	CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2849	----
25984	CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2850	----
25985	CEFBS_InMips16Mode, // XorRxRxRy16 = 2851	----
25986	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2852	----
25987	};	----
25988		----
25989	assert(Opcode < 2853);	0
25990	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];	0
25991	}	----
25992		----
25993	} // end namespace Mips_MC	----
25994	} // end namespace llvm	----
25995	#endif // GET_COMPUTE_FEATURES	----
25996		----
25997	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER	----
25998	#undef ENABLE_INSTR_PREDICATE_VERIFIER	----
25999	#include	----
26000		----
26001	namespace llvm {	----
26002	namespace Mips_MC {	----
26003		----
26004	#ifndef NDEBUG	----
26005	static const char *SubtargetFeatureNames[] = {	----
26006	"Feature_HasCRC",	----
26007	"Feature_HasCnMips",	----
26008	"Feature_HasCnMipsP",	----
26009	"Feature_HasDSP",	----
26010	"Feature_HasDSPR2",	----
26011	"Feature_HasDSPR3",	----
26012	"Feature_HasEVA",	----
26013	"Feature_HasGINV",	----
26014	"Feature_HasMSA",	----
26015	"Feature_HasMT",	----
26016	"Feature_HasMadd4",	----
26017	"Feature_HasMips2",	----
26018	"Feature_HasMips3",	----
26019	"Feature_HasMips3D",	----
26020	"Feature_HasMips3_32",	----
26021	"Feature_HasMips3_32r2",	----
26022	"Feature_HasMips4_32",	----
26023	"Feature_HasMips4_32r2",	----
26024	"Feature_HasMips5_32r2",	----
26025	"Feature_HasMips32",	----
26026	"Feature_HasMips32r2",	----
26027	"Feature_HasMips32r5",	----
26028	"Feature_HasMips32r6",	----
26029	"Feature_HasMips64",	----
26030	"Feature_HasMips64r2",	----
26031	"Feature_HasMips64r5",	----
26032	"Feature_HasMips64r6",	----
26033	"Feature_HasStdEnc",	----
26034	"Feature_HasVirt",	----
26035	"Feature_InMicroMips",	----
26036	"Feature_InMips16Mode",	----
26037	"Feature_IsFP64bit",	----
26038	"Feature_IsGP32bit",	----
26039	"Feature_IsGP64bit",	----
26040	"Feature_IsNotSingleFloat",	----
26041	"Feature_IsNotSoftFloat",	----
26042	"Feature_IsPTR32bit",	----
26043	"Feature_IsPTR64bit",	----
26044	"Feature_IsSingleFloat",	----
26045	"Feature_IsSym32",	----
26046	"Feature_IsSym64",	----
26047	"Feature_NoIndirectJumpGuards",	----
26048	"Feature_NotCnMips",	----
26049	"Feature_NotCnMipsP",	----
26050	"Feature_NotFP64bit",	----
26051	"Feature_NotInMicroMips",	----
26052	"Feature_NotInMips16Mode",	----
26053	"Feature_NotMips3",	----
26054	"Feature_NotMips4_32",	----
26055	"Feature_NotMips32r6",	----
26056	"Feature_NotMips64",	----
26057	"Feature_NotMips64r6",	----
26058	"Feature_UseIndirectJumpsHazard",	----
26059	nullptr	----
26060	};	----
26061		----
26062	#endif // NDEBUG	----
26063		----
26064	void verifyInstructionPredicates(	0
26065	unsigned Opcode, const FeatureBitset &Features) {	----
26066	#ifndef NDEBUG	----
26067	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);	0
26068	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);	0
26069	FeatureBitset MissingFeatures =	----
26070	(AvailableFeatures & RequiredFeatures) ^	0
26071	RequiredFeatures;	0
26072	if (MissingFeatures.any()) {	0
26073	std::ostringstream Msg;	0
26074	Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]	0
26075	<< " instruction but the ";	0
26076	for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)	0
26077	if (MissingFeatures.test(i))	0
26078	Msg << SubtargetFeatureNames[i] << " ";	0
26079	Msg << "predicate(s) are not met";	0
26080	report_fatal_error(Msg.str().c_str());	0
26081	}	----
26082	#endif // NDEBUG	----
26083	}	0
26084	} // end namespace Mips_MC	----
26085	} // end namespace llvm	----
26086	#endif // ENABLE_INSTR_PREDICATE_VERIFIER	----
26087		----
26088	#ifdef GET_INSTRMAP_INFO	----
26089	#undef GET_INSTRMAP_INFO	----
26090	namespace llvm {	----
26091		----
26092	namespace Mips {	----
26093		----
26094	enum Arch {	----
26095	Arch_dsp,	----
26096	Arch_mmdsp,	----
26097	Arch_mipsr6,	----
26098	Arch_micromipsr6,	----
26099	Arch_se,	----
26100	Arch_micromips	----
26101	};	----
26102		----
26103	// Dsp2MicroMips	----
26104	LLVM_READONLY	----
26105	int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {	----
26106	static const uint16_t Dsp2MicroMipsTable[][3] = {	----
26107	{ Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },	----
26108	{ Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },	----
26109	{ Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },	----
26110	{ Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },	----
26111	{ Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },	----
26112	{ Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },	----
26113	{ Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },	----
26114	{ Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },	----
26115	{ Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },	----
26116	{ Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },	----
26117	{ Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },	----
26118	{ Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },	----
26119	{ Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },	----
26120	{ Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },	----
26121	{ Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },	----
26122	{ Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },	----
26123	{ Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },	----
26124	{ Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },	----
26125	{ Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },	----
26126	{ Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },	----
26127	{ Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },	----
26128	{ Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },	----
26129	{ Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },	----
26130	{ Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },	----
26131	{ Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },	----
26132	{ Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },	----
26133	{ Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },	----
26134	{ Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },	----
26135	{ Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },	----
26136	{ Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },	----
26137	{ Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },	----
26138	{ Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },	----
26139	{ Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },	----
26140	{ Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },	----
26141	{ Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },	----
26142	{ Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },	----
26143	{ Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },	----
26144	{ Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },	----
26145	{ Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },	----
26146	{ Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },	----
26147	{ Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },	----
26148	{ Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },	----
26149	{ Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },	----
26150	{ Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },	----
26151	{ Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },	----
26152	{ Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },	----
26153	{ Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },	----
26154	{ Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },	----
26155	{ Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },	----
26156	{ Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },	----
26157	{ Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },	----
26158	{ Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },	----
26159	{ Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },	----
26160	{ Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },	----
26161	{ Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },	----
26162	{ Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },	----
26163	{ Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },	----
26164	{ Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },	----
26165	{ Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },	----
26166	{ Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },	----
26167	{ Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },	----
26168	{ Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },	----
26169	{ Mips::INSV, Mips::INSV, Mips::INSV_MM },	----
26170	{ Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },	----
26171	{ Mips::LHX, Mips::LHX, Mips::LHX_MM },	----
26172	{ Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },	----
26173	{ Mips::LWX, Mips::LWX, Mips::LWX_MM },	----
26174	{ Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },	----
26175	{ Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },	----
26176	{ Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },	----
26177	{ Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },	----
26178	{ Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },	----
26179	{ Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },	----
26180	{ Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },	----
26181	{ Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },	----
26182	{ Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },	----
26183	{ Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },	----
26184	{ Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },	----
26185	{ Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },	----
26186	{ Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },	----
26187	{ Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },	----
26188	{ Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },	----
26189	{ Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },	----
26190	{ Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },	----
26191	{ Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },	----
26192	{ Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },	----
26193	{ Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },	----
26194	{ Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },	----
26195	{ Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },	----
26196	{ Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },	----
26197	{ Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },	----
26198	{ Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },	----
26199	{ Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },	----
26200	{ Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },	----
26201	{ Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },	----
26202	{ Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },	----
26203	{ Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },	----
26204	{ Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },	----
26205	{ Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },	----
26206	{ Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },	----
26207	{ Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },	----
26208	{ Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },	----
26209	{ Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },	----
26210	{ Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },	----
26211	{ Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },	----
26212	{ Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },	----
26213	{ Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },	----
26214	{ Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },	----
26215	{ Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },	----
26216	{ Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },	----
26217	{ Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },	----
26218	{ Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },	----
26219	{ Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },	----
26220	{ Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },	----
26221	{ Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },	----
26222	{ Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },	----
26223	{ Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },	----
26224	{ Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },	----
26225	{ Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },	----
26226	{ Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },	----
26227	{ Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },	----
26228	{ Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },	----
26229	{ Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },	----
26230	{ Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },	----
26231	{ Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },	----
26232	{ Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },	----
26233	{ Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },	----
26234	{ Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },	----
26235	{ Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },	----
26236	{ Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },	----
26237	{ Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },	----
26238	{ Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },	----
26239	{ Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },	----
26240	{ Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },	----
26241	{ Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },	----
26242	{ Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },	----
26243	{ Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },	----
26244	{ Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },	----
26245	{ Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },	----
26246	{ Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },	----
26247	{ Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },	----
26248	{ Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },	----
26249	{ Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },	----
26250	{ Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },	----
26251	{ Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },	----
26252	{ Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },	----
26253	{ Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },	----
26254	{ Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },	----
26255	{ Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },	----
26256	{ Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },	----
26257	{ Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },	----
26258	{ Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },	----
26259	{ Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },	----
26260	{ Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },	----
26261	{ Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },	----
26262	{ Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },	----
26263	{ Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },	----
26264	{ Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },	----
26265	{ Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },	----
26266	{ Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },	----
26267	}; // End of Dsp2MicroMipsTable	----
26268		----
26269	unsigned mid;	----
26270	unsigned start = 0;	----
26271	unsigned end = 160;	----
26272	while (start < end) {	----
26273	mid = start + (end - start) / 2;	----
26274	if (Opcode == Dsp2MicroMipsTable[mid][0]) {	----
26275	break;	----
26276	}	----
26277	if (Opcode < Dsp2MicroMipsTable[mid][0])	----
26278	end = mid;	----
26279	else	----
26280	start = mid + 1;	----
26281	}	----
26282	if (start == end)	----
26283	return -1; // Instruction doesn't exist in this table.	----
26284		----
26285	if (inArch == Arch_dsp)	----
26286	return Dsp2MicroMipsTable[mid][1];	----
26287	if (inArch == Arch_mmdsp)	----
26288	return Dsp2MicroMipsTable[mid][2];	----
26289	return -1;}	----
26290		----
26291	// MipsR62MicroMipsR6	----
26292	LLVM_READONLY	----
26293	int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	----
26294	static const uint16_t MipsR62MicroMipsR6Table[][3] = {	----
26295	{ Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },	----
26296	{ Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },	----
26297	{ Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },	----
26298	{ Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },	----
26299	{ Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },	----
26300	{ Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },	----
26301	{ Mips::BC, Mips::BC, Mips::BC_MMR6 },	----
26302	{ Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },	----
26303	{ Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },	----
26304	{ Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },	----
26305	{ Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },	----
26306	{ Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },	----
26307	{ Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },	----
26308	{ Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },	----
26309	{ Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },	----
26310	{ Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },	----
26311	{ Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },	----
26312	{ Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },	----
26313	{ Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },	----
26314	{ Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },	----
26315	{ Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },	----
26316	{ Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },	----
26317	{ Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },	----
26318	{ Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },	----
26319	{ Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },	----
26320	{ Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },	----
26321	{ Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },	----
26322	{ Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },	----
26323	{ Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },	----
26324	{ Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },	----
26325	{ Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },	----
26326	{ Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },	----
26327	{ Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },	----
26328	{ Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },	----
26329	{ Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },	----
26330	{ Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },	----
26331	{ Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },	----
26332	{ Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },	----
26333	{ Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },	----
26334	{ Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },	----
26335	{ Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },	----
26336	{ Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },	----
26337	{ Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },	----
26338	{ Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },	----
26339	{ Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },	----
26340	{ Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },	----
26341	{ Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },	----
26342	{ Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },	----
26343	{ Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },	----
26344	{ Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },	----
26345	{ Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },	----
26346	{ Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },	----
26347	{ Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },	----
26348	{ Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },	----
26349	{ Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },	----
26350	{ Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },	----
26351	{ Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },	----
26352	{ Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },	----
26353	{ Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },	----
26354	{ Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },	----
26355	{ Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },	----
26356	{ Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },	----
26357	{ Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },	----
26358	{ Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },	----
26359	{ Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },	----
26360	{ Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },	----
26361	{ Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },	----
26362	{ Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },	----
26363	{ Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },	----
26364	{ Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },	----
26365	{ Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },	----
26366	{ Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },	----
26367	{ Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },	----
26368	{ Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },	----
26369	{ Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },	----
26370	{ Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },	----
26371	{ Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },	----
26372	{ Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },	----
26373	{ Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },	----
26374	{ Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },	----
26375	{ Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },	----
26376	{ Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },	----
26377	{ Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },	----
26378	{ Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },	----
26379	{ Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },	----
26380	{ Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },	----
26381	{ Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },	----
26382	{ Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },	----
26383	{ Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },	----
26384	{ Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },	----
26385	{ Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },	----
26386	{ Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },	----
26387	{ Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },	----
26388	{ Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },	----
26389	{ Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },	----
26390	{ Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },	----
26391	}; // End of MipsR62MicroMipsR6Table	----
26392		----
26393	unsigned mid;	----
26394	unsigned start = 0;	----
26395	unsigned end = 96;	----
26396	while (start < end) {	----
26397	mid = start + (end - start) / 2;	----
26398	if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {	----
26399	break;	----
26400	}	----
26401	if (Opcode < MipsR62MicroMipsR6Table[mid][0])	----
26402	end = mid;	----
26403	else	----
26404	start = mid + 1;	----
26405	}	----
26406	if (start == end)	----
26407	return -1; // Instruction doesn't exist in this table.	----
26408		----
26409	if (inArch == Arch_mipsr6)	----
26410	return MipsR62MicroMipsR6Table[mid][1];	----
26411	if (inArch == Arch_micromipsr6)	----
26412	return MipsR62MicroMipsR6Table[mid][2];	----
26413	return -1;}	----
26414		----
26415	// Std2MicroMips	----
26416	LLVM_READONLY	----
26417	int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {	----
26418	static const uint16_t Std2MicroMipsTable[][3] = {	----
26419	{ Mips::ADD, Mips::ADD, Mips::ADD_MM },	----
26420	{ Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },	----
26421	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },	----
26422	{ Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },	----
26423	{ Mips::AND, Mips::AND, Mips::AND_MM },	----
26424	{ Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },	----
26425	{ Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },	----
26426	{ Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },	----
26427	{ Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },	----
26428	{ Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },	----
26429	{ Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },	----
26430	{ Mips::BEQL, Mips::BEQL, (uint16_t)-1U },	----
26431	{ Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },	----
26432	{ Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },	----
26433	{ Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },	----
26434	{ Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },	----
26435	{ Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },	----
26436	{ Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },	----
26437	{ Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },	----
26438	{ Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },	----
26439	{ Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },	----
26440	{ Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },	----
26441	{ Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },	----
26442	{ Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },	----
26443	{ Mips::BNE, Mips::BNE, Mips::BNE_MM },	----
26444	{ Mips::BNEL, Mips::BNEL, (uint16_t)-1U },	----
26445	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },	----
26446	{ Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },	----
26447	{ Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },	----
26448	{ Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },	----
26449	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },	----
26450	{ Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },	----
26451	{ Mips::CLO, Mips::CLO, Mips::CLO_MM },	----
26452	{ Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },	----
26453	{ Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },	----
26454	{ Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },	----
26455	{ Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },	----
26456	{ Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },	----
26457	{ Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },	----
26458	{ Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },	----
26459	{ Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },	----
26460	{ Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },	----
26461	{ Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },	----
26462	{ Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },	----
26463	{ Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },	----
26464	{ Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },	----
26465	{ Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },	----
26466	{ Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },	----
26467	{ Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },	----
26468	{ Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },	----
26469	{ Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },	----
26470	{ Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },	----
26471	{ Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },	----
26472	{ Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },	----
26473	{ Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },	----
26474	{ Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },	----
26475	{ Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },	----
26476	{ Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },	----
26477	{ Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },	----
26478	{ Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },	----
26479	{ Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },	----
26480	{ Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },	----
26481	{ Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },	----
26482	{ Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },	----
26483	{ Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },	----
26484	{ Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },	----
26485	{ Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },	----
26486	{ Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },	----
26487	{ Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },	----
26488	{ Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },	----
26489	{ Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },	----
26490	{ Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },	----
26491	{ Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },	----
26492	{ Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },	----
26493	{ Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },	----
26494	{ Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },	----
26495	{ Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },	----
26496	{ Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },	----
26497	{ Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },	----
26498	{ Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },	----
26499	{ Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },	----
26500	{ Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },	----
26501	{ Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },	----
26502	{ Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },	----
26503	{ Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },	----
26504	{ Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },	----
26505	{ Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },	----
26506	{ Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },	----
26507	{ Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },	----
26508	{ Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },	----
26509	{ Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },	----
26510	{ Mips::DERET, Mips::DERET, Mips::DERET_MM },	----
26511	{ Mips::DI, Mips::DI, Mips::DI_MM },	----
26512	{ Mips::EHB, Mips::EHB, Mips::EHB_MM },	----
26513	{ Mips::EI, Mips::EI, Mips::EI_MM },	----
26514	{ Mips::ERET, Mips::ERET, Mips::ERET_MM },	----
26515	{ Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },	----
26516	{ Mips::EXT, Mips::EXT, Mips::EXT_MM },	----
26517	{ Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },	----
26518	{ Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },	----
26519	{ Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },	----
26520	{ Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },	----
26521	{ Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },	----
26522	{ Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },	----
26523	{ Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },	----
26524	{ Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },	----
26525	{ Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },	----
26526	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },	----
26527	{ Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },	----
26528	{ Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },	----
26529	{ Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },	----
26530	{ Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },	----
26531	{ Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },	----
26532	{ Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },	----
26533	{ Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },	----
26534	{ Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },	----
26535	{ Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },	----
26536	{ Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },	----
26537	{ Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },	----
26538	{ Mips::INS, Mips::INS, Mips::INS_MM },	----
26539	{ Mips::J, Mips::J, Mips::J_MM },	----
26540	{ Mips::JAL, Mips::JAL, Mips::JAL_MM },	----
26541	{ Mips::JALX, Mips::JALX, Mips::JALX_MM },	----
26542	{ Mips::JR, Mips::JR, Mips::JR_MM },	----
26543	{ Mips::LB, Mips::LB, Mips::LB_MM },	----
26544	{ Mips::LBE, Mips::LBE, Mips::LBE_MM },	----
26545	{ Mips::LBu, Mips::LBu, Mips::LBu_MM },	----
26546	{ Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },	----
26547	{ Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },	----
26548	{ Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },	----
26549	{ Mips::LH, Mips::LH, Mips::LH_MM },	----
26550	{ Mips::LHE, Mips::LHE, Mips::LHE_MM },	----
26551	{ Mips::LHu, Mips::LHu, Mips::LHu_MM },	----
26552	{ Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },	----
26553	{ Mips::LLE, Mips::LLE, Mips::LLE_MM },	----
26554	{ Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },	----
26555	{ Mips::LUi, Mips::LUi, Mips::LUi_MM },	----
26556	{ Mips::LW, Mips::LW, Mips::LW_MM },	----
26557	{ Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },	----
26558	{ Mips::LWE, Mips::LWE, Mips::LWE_MM },	----
26559	{ Mips::LWL, Mips::LWL, Mips::LWL_MM },	----
26560	{ Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },	----
26561	{ Mips::LWR, Mips::LWR, Mips::LWR_MM },	----
26562	{ Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },	----
26563	{ Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },	----
26564	{ Mips::LWu, Mips::LWu, Mips::LWU_MM },	----
26565	{ Mips::MADD, Mips::MADD, Mips::MADD_MM },	----
26566	{ Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },	----
26567	{ Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },	----
26568	{ Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },	----
26569	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },	----
26570	{ Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },	----
26571	{ Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },	----
26572	{ Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },	----
26573	{ Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },	----
26574	{ Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },	----
26575	{ Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },	----
26576	{ Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },	----
26577	{ Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },	----
26578	{ Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },	----
26579	{ Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },	----
26580	{ Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },	----
26581	{ Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },	----
26582	{ Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },	----
26583	{ Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },	----
26584	{ Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },	----
26585	{ Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },	----
26586	{ Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },	----
26587	{ Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },	----
26588	{ Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },	----
26589	{ Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },	----
26590	{ Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },	----
26591	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },	----
26592	{ Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },	----
26593	{ Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },	----
26594	{ Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },	----
26595	{ Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },	----
26596	{ Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },	----
26597	{ Mips::MUL, Mips::MUL, Mips::MUL_MM },	----
26598	{ Mips::MULT, Mips::MULT, Mips::MULT_MM },	----
26599	{ Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },	----
26600	{ Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },	----
26601	{ Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },	----
26602	{ Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },	----
26603	{ Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },	----
26604	{ Mips::NOR, Mips::NOR, Mips::NOR_MM },	----
26605	{ Mips::OR, Mips::OR, Mips::OR_MM },	----
26606	{ Mips::ORi, Mips::ORi, Mips::ORi_MM },	----
26607	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },	----
26608	{ Mips::PREF, Mips::PREF, Mips::PREF_MM },	----
26609	{ Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },	----
26610	{ Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },	----
26611	{ Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },	----
26612	{ Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },	----
26613	{ Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },	----
26614	{ Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },	----
26615	{ Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },	----
26616	{ Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },	----
26617	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },	----
26618	{ Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },	----
26619	{ Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },	----
26620	{ Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },	----
26621	{ Mips::SB, Mips::SB, Mips::SB_MM },	----
26622	{ Mips::SBE, Mips::SBE, Mips::SBE_MM },	----
26623	{ Mips::SCE, Mips::SCE, Mips::SCE_MM },	----
26624	{ Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },	----
26625	{ Mips::SDC1, Mips::SDC1, (uint16_t)-1U },	----
26626	{ Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },	----
26627	{ Mips::SEB, Mips::SEB, Mips::SEB_MM },	----
26628	{ Mips::SEH, Mips::SEH, Mips::SEH_MM },	----
26629	{ Mips::SH, Mips::SH, Mips::SH_MM },	----
26630	{ Mips::SHE, Mips::SHE, Mips::SHE_MM },	----
26631	{ Mips::SLL, Mips::SLL, Mips::SLL_MM },	----
26632	{ Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },	----
26633	{ Mips::SLT, Mips::SLT, Mips::SLT_MM },	----
26634	{ Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },	----
26635	{ Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },	----
26636	{ Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },	----
26637	{ Mips::SRA, Mips::SRA, Mips::SRA_MM },	----
26638	{ Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },	----
26639	{ Mips::SRL, Mips::SRL, Mips::SRL_MM },	----
26640	{ Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },	----
26641	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },	----
26642	{ Mips::SUB, Mips::SUB, Mips::SUB_MM },	----
26643	{ Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },	----
26644	{ Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },	----
26645	{ Mips::SW, Mips::SW, Mips::SW_MM },	----
26646	{ Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },	----
26647	{ Mips::SWE, Mips::SWE, Mips::SWE_MM },	----
26648	{ Mips::SWL, Mips::SWL, Mips::SWL_MM },	----
26649	{ Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },	----
26650	{ Mips::SWR, Mips::SWR, Mips::SWR_MM },	----
26651	{ Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },	----
26652	{ Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },	----
26653	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },	----
26654	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },	----
26655	{ Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },	----
26656	{ Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },	----
26657	{ Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },	----
26658	{ Mips::TGE, Mips::TGE, Mips::TGE_MM },	----
26659	{ Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },	----
26660	{ Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },	----
26661	{ Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },	----
26662	{ Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },	----
26663	{ Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },	----
26664	{ Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },	----
26665	{ Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },	----
26666	{ Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },	----
26667	{ Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },	----
26668	{ Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },	----
26669	{ Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },	----
26670	{ Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },	----
26671	{ Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },	----
26672	{ Mips::TLT, Mips::TLT, Mips::TLT_MM },	----
26673	{ Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },	----
26674	{ Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },	----
26675	{ Mips::TNE, Mips::TNE, Mips::TNE_MM },	----
26676	{ Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },	----
26677	{ Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },	----
26678	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },	----
26679	{ Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },	----
26680	{ Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },	----
26681	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },	----
26682	{ Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },	----
26683	{ Mips::XOR, Mips::XOR, Mips::XOR_MM },	----
26684	{ Mips::XORi, Mips::XORi, Mips::XORi_MM },	----
26685	}; // End of Std2MicroMipsTable	----
26686		----
26687	unsigned mid;	----
26688	unsigned start = 0;	----
26689	unsigned end = 266;	----
26690	while (start < end) {	----
26691	mid = start + (end - start) / 2;	----
26692	if (Opcode == Std2MicroMipsTable[mid][0]) {	----
26693	break;	----
26694	}	----
26695	if (Opcode < Std2MicroMipsTable[mid][0])	----
26696	end = mid;	----
26697	else	----
26698	start = mid + 1;	----
26699	}	----
26700	if (start == end)	----
26701	return -1; // Instruction doesn't exist in this table.	----
26702		----
26703	if (inArch == Arch_se)	----
26704	return Std2MicroMipsTable[mid][1];	----
26705	if (inArch == Arch_micromips)	----
26706	return Std2MicroMipsTable[mid][2];	----
26707	return -1;}	----
26708		----
26709	// Std2MicroMipsR6	----
26710	LLVM_READONLY	----
26711	int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	----
26712	static const uint16_t Std2MicroMipsR6Table[][3] = {	----
26713	{ Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },	----
26714	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },	----
26715	{ Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },	----
26716	{ Mips::AND, Mips::AND, Mips::AND_MMR6 },	----
26717	{ Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },	----
26718	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },	----
26719	{ Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },	----
26720	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },	----
26721	{ Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },	----
26722	{ Mips::DI, Mips::DI, Mips::DI_MMR6 },	----
26723	{ Mips::EI, Mips::EI, Mips::EI_MMR6 },	----
26724	{ Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },	----
26725	{ Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },	----
26726	{ Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },	----
26727	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },	----
26728	{ Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },	----
26729	{ Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },	----
26730	{ Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },	----
26731	{ Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },	----
26732	{ Mips::INS, Mips::INS, Mips::INS_MMR6 },	----
26733	{ Mips::LDC1, Mips::LDC1, (uint16_t)-1U },	----
26734	{ Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },	----
26735	{ Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },	----
26736	{ Mips::LW, Mips::LW, Mips::LW_MMR6 },	----
26737	{ Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },	----
26738	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },	----
26739	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },	----
26740	{ Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },	----
26741	{ Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },	----
26742	{ Mips::OR, Mips::OR, Mips::OR_MMR6 },	----
26743	{ Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },	----
26744	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },	----
26745	{ Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },	----
26746	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },	----
26747	{ Mips::SB, Mips::SB, Mips::SB_MMR6 },	----
26748	{ Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },	----
26749	{ Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },	----
26750	{ Mips::SEB, Mips::SEB, (uint16_t)-1U },	----
26751	{ Mips::SEH, Mips::SEH, (uint16_t)-1U },	----
26752	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },	----
26753	{ Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },	----
26754	{ Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },	----
26755	{ Mips::SW, Mips::SW, Mips::SW_MMR6 },	----
26756	{ Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },	----
26757	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },	----
26758	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },	----
26759	{ Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },	----
26760	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },	----
26761	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },	----
26762	{ Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },	----
26763	{ Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },	----
26764	}; // End of Std2MicroMipsR6Table	----
26765		----
26766	unsigned mid;	----
26767	unsigned start = 0;	----
26768	unsigned end = 51;	----
26769	while (start < end) {	----
26770	mid = start + (end - start) / 2;	----
26771	if (Opcode == Std2MicroMipsR6Table[mid][0]) {	----
26772	break;	----
26773	}	----
26774	if (Opcode < Std2MicroMipsR6Table[mid][0])	----
26775	end = mid;	----
26776	else	----
26777	start = mid + 1;	----
26778	}	----
26779	if (start == end)	----
26780	return -1; // Instruction doesn't exist in this table.	----
26781		----
26782	if (inArch == Arch_se)	----
26783	return Std2MicroMipsR6Table[mid][1];	----
26784	if (inArch == Arch_micromipsr6)	----
26785	return Std2MicroMipsR6Table[mid][2];	----
26786	return -1;}	----
26787		----
26788	} // end namespace Mips	----
26789	} // end namespace llvm	----
26790	#endif // GET_INSTRMAP_INFO	----
26791		----
26792		----

Functions Report

Function name	Number of hits
_ZN4llvmL19InitMipsMCInstrInfoEPNS_11MCInstrInfoE	2
_ZN4llvm7Mips_MC24computeAvailableFeaturesERKNS_13FeatureBitsetE	0
_ZN4llvm7Mips_MC23computeRequiredFeaturesEj	0
_ZN4llvm7Mips_MC27verifyInstructionPredicatesEjRKNS_13FeatureBitsetE	0
_ZN4llvm16MipsGenInstrInfoD0Ev	0
_ZN4llvm16MipsGenInstrInfoD2Ev	10
_ZN4llvm16MipsGenInstrInfoC2Ejjjj	10

Coverage Diff

Line Number	../DebugInfoTest/example_mips_dbg.ll BUT NOT ../DebugInfoTest/example_mips.ll	Line Number	../DebugInfoTest/example_mips.ll BUT NOT ../DebugInfoTest/example_mips_dbg.ll
1	/===- TableGen'erated file -------------------------------------- C++ --===\	1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\|* *\|	2	\|* *\|
3	\|* Target Instruction Enum Values and Descriptors *\|	3	\|* Target Instruction Enum Values and Descriptors *\|
4	\|* *\|	4	\|* *\|
5	\|* Automatically generated file, do not edit! *\|	5	\|* Automatically generated file, do not edit! *\|
6	\|* *\|	6	\|* *\|
7	\===----------------------------------------------------------------------===/	7	\===----------------------------------------------------------------------===/
8		8
9	#ifdef GET_INSTRINFO_ENUM	9	#ifdef GET_INSTRINFO_ENUM
10	#undef GET_INSTRINFO_ENUM	10	#undef GET_INSTRINFO_ENUM
11	namespace llvm {	11	namespace llvm {
12		12
13	namespace Mips {	13	namespace Mips {
14	enum {	14	enum {
15	PHI = 0,	15	PHI = 0,
16	INLINEASM = 1,	16	INLINEASM = 1,
17	INLINEASM_BR = 2,	17	INLINEASM_BR = 2,
18	CFI_INSTRUCTION = 3,	18	CFI_INSTRUCTION = 3,
19	EH_LABEL = 4,	19	EH_LABEL = 4,
20	GC_LABEL = 5,	20	GC_LABEL = 5,
21	ANNOTATION_LABEL = 6,	21	ANNOTATION_LABEL = 6,
22	KILL = 7,	22	KILL = 7,
23	EXTRACT_SUBREG = 8,	23	EXTRACT_SUBREG = 8,
24	INSERT_SUBREG = 9,	24	INSERT_SUBREG = 9,
25	IMPLICIT_DEF = 10,	25	IMPLICIT_DEF = 10,
26	SUBREG_TO_REG = 11,	26	SUBREG_TO_REG = 11,
27	COPY_TO_REGCLASS = 12,	27	COPY_TO_REGCLASS = 12,
28	DBG_VALUE = 13,	28	DBG_VALUE = 13,
29	DBG_VALUE_LIST = 14,	29	DBG_VALUE_LIST = 14,
30	DBG_INSTR_REF = 15,	30	DBG_INSTR_REF = 15,
31	DBG_PHI = 16,	31	DBG_PHI = 16,
32	DBG_LABEL = 17,	32	DBG_LABEL = 17,
33	REG_SEQUENCE = 18,	33	REG_SEQUENCE = 18,
34	COPY = 19,	34	COPY = 19,
35	BUNDLE = 20,	35	BUNDLE = 20,
36	LIFETIME_START = 21,	36	LIFETIME_START = 21,
37	LIFETIME_END = 22,	37	LIFETIME_END = 22,
38	PSEUDO_PROBE = 23,	38	PSEUDO_PROBE = 23,
39	ARITH_FENCE = 24,	39	ARITH_FENCE = 24,
40	STACKMAP = 25,	40	STACKMAP = 25,
41	FENTRY_CALL = 26,	41	FENTRY_CALL = 26,
42	PATCHPOINT = 27,	42	PATCHPOINT = 27,
43	LOAD_STACK_GUARD = 28,	43	LOAD_STACK_GUARD = 28,
44	PREALLOCATED_SETUP = 29,	44	PREALLOCATED_SETUP = 29,
45	PREALLOCATED_ARG = 30,	45	PREALLOCATED_ARG = 30,
46	STATEPOINT = 31,	46	STATEPOINT = 31,
47	LOCAL_ESCAPE = 32,	47	LOCAL_ESCAPE = 32,
48	FAULTING_OP = 33,	48	FAULTING_OP = 33,
49	PATCHABLE_OP = 34,	49	PATCHABLE_OP = 34,
50	PATCHABLE_FUNCTION_ENTER = 35,	50	PATCHABLE_FUNCTION_ENTER = 35,
51	PATCHABLE_RET = 36,	51	PATCHABLE_RET = 36,
52	PATCHABLE_FUNCTION_EXIT = 37,	52	PATCHABLE_FUNCTION_EXIT = 37,
53	PATCHABLE_TAIL_CALL = 38,	53	PATCHABLE_TAIL_CALL = 38,
54	PATCHABLE_EVENT_CALL = 39,	54	PATCHABLE_EVENT_CALL = 39,
55	PATCHABLE_TYPED_EVENT_CALL = 40,	55	PATCHABLE_TYPED_EVENT_CALL = 40,
56	ICALL_BRANCH_FUNNEL = 41,	56	ICALL_BRANCH_FUNNEL = 41,
57	MEMBARRIER = 42,	57	MEMBARRIER = 42,
58	G_ASSERT_SEXT = 43,	58	G_ASSERT_SEXT = 43,
59	G_ASSERT_ZEXT = 44,	59	G_ASSERT_ZEXT = 44,
60	G_ASSERT_ALIGN = 45,	60	G_ASSERT_ALIGN = 45,
61	G_ADD = 46,	61	G_ADD = 46,
62	G_SUB = 47,	62	G_SUB = 47,
63	G_MUL = 48,	63	G_MUL = 48,
64	G_SDIV = 49,	64	G_SDIV = 49,
65	G_UDIV = 50,	65	G_UDIV = 50,
66	G_SREM = 51,	66	G_SREM = 51,
67	G_UREM = 52,	67	G_UREM = 52,
68	G_SDIVREM = 53,	68	G_SDIVREM = 53,
69	G_UDIVREM = 54,	69	G_UDIVREM = 54,
70	G_AND = 55,	70	G_AND = 55,
71	G_OR = 56,	71	G_OR = 56,
72	G_XOR = 57,	72	G_XOR = 57,
73	G_IMPLICIT_DEF = 58,	73	G_IMPLICIT_DEF = 58,
74	G_PHI = 59,	74	G_PHI = 59,
75	G_FRAME_INDEX = 60,	75	G_FRAME_INDEX = 60,
76	G_GLOBAL_VALUE = 61,	76	G_GLOBAL_VALUE = 61,
77	G_CONSTANT_POOL = 62,	77	G_CONSTANT_POOL = 62,
78	G_EXTRACT = 63,	78	G_EXTRACT = 63,
79	G_UNMERGE_VALUES = 64,	79	G_UNMERGE_VALUES = 64,
80	G_INSERT = 65,	80	G_INSERT = 65,
81	G_MERGE_VALUES = 66,	81	G_MERGE_VALUES = 66,
82	G_BUILD_VECTOR = 67,	82	G_BUILD_VECTOR = 67,
83	G_BUILD_VECTOR_TRUNC = 68,	83	G_BUILD_VECTOR_TRUNC = 68,
84	G_CONCAT_VECTORS = 69,	84	G_CONCAT_VECTORS = 69,
85	G_PTRTOINT = 70,	85	G_PTRTOINT = 70,
86	G_INTTOPTR = 71,	86	G_INTTOPTR = 71,
87	G_BITCAST = 72,	87	G_BITCAST = 72,
88	G_FREEZE = 73,	88	G_FREEZE = 73,
89	G_CONSTANT_FOLD_BARRIER = 74,	89	G_CONSTANT_FOLD_BARRIER = 74,
90	G_INTRINSIC_FPTRUNC_ROUND = 75,	90	G_INTRINSIC_FPTRUNC_ROUND = 75,
91	G_INTRINSIC_TRUNC = 76,	91	G_INTRINSIC_TRUNC = 76,
92	G_INTRINSIC_ROUND = 77,	92	G_INTRINSIC_ROUND = 77,
93	G_INTRINSIC_LRINT = 78,	93	G_INTRINSIC_LRINT = 78,
94	G_INTRINSIC_ROUNDEVEN = 79,	94	G_INTRINSIC_ROUNDEVEN = 79,
95	G_READCYCLECOUNTER = 80,	95	G_READCYCLECOUNTER = 80,
96	G_LOAD = 81,	96	G_LOAD = 81,
97	G_SEXTLOAD = 82,	97	G_SEXTLOAD = 82,
98	G_ZEXTLOAD = 83,	98	G_ZEXTLOAD = 83,
99	G_INDEXED_LOAD = 84,	99	G_INDEXED_LOAD = 84,
100	G_INDEXED_SEXTLOAD = 85,	100	G_INDEXED_SEXTLOAD = 85,
101	G_INDEXED_ZEXTLOAD = 86,	101	G_INDEXED_ZEXTLOAD = 86,
102	G_STORE = 87,	102	G_STORE = 87,
103	G_INDEXED_STORE = 88,	103	G_INDEXED_STORE = 88,
104	G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89,	104	G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89,
105	G_ATOMIC_CMPXCHG = 90,	105	G_ATOMIC_CMPXCHG = 90,
106	G_ATOMICRMW_XCHG = 91,	106	G_ATOMICRMW_XCHG = 91,
107	G_ATOMICRMW_ADD = 92,	107	G_ATOMICRMW_ADD = 92,
108	G_ATOMICRMW_SUB = 93,	108	G_ATOMICRMW_SUB = 93,
109	G_ATOMICRMW_AND = 94,	109	G_ATOMICRMW_AND = 94,
110	G_ATOMICRMW_NAND = 95,	110	G_ATOMICRMW_NAND = 95,
111	G_ATOMICRMW_OR = 96,	111	G_ATOMICRMW_OR = 96,
112	G_ATOMICRMW_XOR = 97,	112	G_ATOMICRMW_XOR = 97,
113	G_ATOMICRMW_MAX = 98,	113	G_ATOMICRMW_MAX = 98,
114	G_ATOMICRMW_MIN = 99,	114	G_ATOMICRMW_MIN = 99,
115	G_ATOMICRMW_UMAX = 100,	115	G_ATOMICRMW_UMAX = 100,
116	G_ATOMICRMW_UMIN = 101,	116	G_ATOMICRMW_UMIN = 101,
117	G_ATOMICRMW_FADD = 102,	117	G_ATOMICRMW_FADD = 102,
118	G_ATOMICRMW_FSUB = 103,	118	G_ATOMICRMW_FSUB = 103,
119	G_ATOMICRMW_FMAX = 104,	119	G_ATOMICRMW_FMAX = 104,
120	G_ATOMICRMW_FMIN = 105,	120	G_ATOMICRMW_FMIN = 105,
121	G_ATOMICRMW_UINC_WRAP = 106,	121	G_ATOMICRMW_UINC_WRAP = 106,
122	G_ATOMICRMW_UDEC_WRAP = 107,	122	G_ATOMICRMW_UDEC_WRAP = 107,
123	G_FENCE = 108,	123	G_FENCE = 108,
124	G_BRCOND = 109,	124	G_BRCOND = 109,
125	G_BRINDIRECT = 110,	125	G_BRINDIRECT = 110,
126	G_INVOKE_REGION_START = 111,	126	G_INVOKE_REGION_START = 111,
127	G_INTRINSIC = 112,	127	G_INTRINSIC = 112,
128	G_INTRINSIC_W_SIDE_EFFECTS = 113,	128	G_INTRINSIC_W_SIDE_EFFECTS = 113,
129	G_ANYEXT = 114,	129	G_ANYEXT = 114,
130	G_TRUNC = 115,	130	G_TRUNC = 115,
131	G_CONSTANT = 116,	131	G_CONSTANT = 116,
132	G_FCONSTANT = 117,	132	G_FCONSTANT = 117,
133	G_VASTART = 118,	133	G_VASTART = 118,
134	G_VAARG = 119,	134	G_VAARG = 119,
135	G_SEXT = 120,	135	G_SEXT = 120,
136	G_SEXT_INREG = 121,	136	G_SEXT_INREG = 121,
137	G_ZEXT = 122,	137	G_ZEXT = 122,
138	G_SHL = 123,	138	G_SHL = 123,
139	G_LSHR = 124,	139	G_LSHR = 124,
140	G_ASHR = 125,	140	G_ASHR = 125,
141	G_FSHL = 126,	141	G_FSHL = 126,
142	G_FSHR = 127,	142	G_FSHR = 127,
143	G_ROTR = 128,	143	G_ROTR = 128,
144	G_ROTL = 129,	144	G_ROTL = 129,
145	G_ICMP = 130,	145	G_ICMP = 130,
146	G_FCMP = 131,	146	G_FCMP = 131,
147	G_SELECT = 132,	147	G_SELECT = 132,
148	G_UADDO = 133,	148	G_UADDO = 133,
149	G_UADDE = 134,	149	G_UADDE = 134,
150	G_USUBO = 135,	150	G_USUBO = 135,
151	G_USUBE = 136,	151	G_USUBE = 136,
152	G_SADDO = 137,	152	G_SADDO = 137,
153	G_SADDE = 138,	153	G_SADDE = 138,
154	G_SSUBO = 139,	154	G_SSUBO = 139,
155	G_SSUBE = 140,	155	G_SSUBE = 140,
156	G_UMULO = 141,	156	G_UMULO = 141,
157	G_SMULO = 142,	157	G_SMULO = 142,
158	G_UMULH = 143,	158	G_UMULH = 143,
159	G_SMULH = 144,	159	G_SMULH = 144,
160	G_UADDSAT = 145,	160	G_UADDSAT = 145,
161	G_SADDSAT = 146,	161	G_SADDSAT = 146,
162	G_USUBSAT = 147,	162	G_USUBSAT = 147,
163	G_SSUBSAT = 148,	163	G_SSUBSAT = 148,
164	G_USHLSAT = 149,	164	G_USHLSAT = 149,
165	G_SSHLSAT = 150,	165	G_SSHLSAT = 150,
166	G_SMULFIX = 151,	166	G_SMULFIX = 151,
167	G_UMULFIX = 152,	167	G_UMULFIX = 152,
168	G_SMULFIXSAT = 153,	168	G_SMULFIXSAT = 153,
169	G_UMULFIXSAT = 154,	169	G_UMULFIXSAT = 154,
170	G_SDIVFIX = 155,	170	G_SDIVFIX = 155,
171	G_UDIVFIX = 156,	171	G_UDIVFIX = 156,
172	G_SDIVFIXSAT = 157,	172	G_SDIVFIXSAT = 157,
173	G_UDIVFIXSAT = 158,	173	G_UDIVFIXSAT = 158,
174	G_FADD = 159,	174	G_FADD = 159,
175	G_FSUB = 160,	175	G_FSUB = 160,
176	G_FMUL = 161,	176	G_FMUL = 161,
177	G_FMA = 162,	177	G_FMA = 162,
178	G_FMAD = 163,	178	G_FMAD = 163,
179	G_FDIV = 164,	179	G_FDIV = 164,
180	G_FREM = 165,	180	G_FREM = 165,
181	G_FPOW = 166,	181	G_FPOW = 166,
182	G_FPOWI = 167,	182	G_FPOWI = 167,
183	G_FEXP = 168,	183	G_FEXP = 168,
184	G_FEXP2 = 169,	184	G_FEXP2 = 169,
185	G_FLOG = 170,	185	G_FLOG = 170,
186	G_FLOG2 = 171,	186	G_FLOG2 = 171,
187	G_FLOG10 = 172,	187	G_FLOG10 = 172,
188	G_FLDEXP = 173,	188	G_FLDEXP = 173,
189	G_FFREXP = 174,	189	G_FFREXP = 174,
190	G_FNEG = 175,	190	G_FNEG = 175,
191	G_FPEXT = 176,	191	G_FPEXT = 176,
192	G_FPTRUNC = 177,	192	G_FPTRUNC = 177,
193	G_FPTOSI = 178,	193	G_FPTOSI = 178,
194	G_FPTOUI = 179,	194	G_FPTOUI = 179,
195	G_SITOFP = 180,	195	G_SITOFP = 180,
196	G_UITOFP = 181,	196	G_UITOFP = 181,
197	G_FABS = 182,	197	G_FABS = 182,
198	G_FCOPYSIGN = 183,	198	G_FCOPYSIGN = 183,
199	G_IS_FPCLASS = 184,	199	G_IS_FPCLASS = 184,
200	G_FCANONICALIZE = 185,	200	G_FCANONICALIZE = 185,
201	G_FMINNUM = 186,	201	G_FMINNUM = 186,
202	G_FMAXNUM = 187,	202	G_FMAXNUM = 187,
203	G_FMINNUM_IEEE = 188,	203	G_FMINNUM_IEEE = 188,
204	G_FMAXNUM_IEEE = 189,	204	G_FMAXNUM_IEEE = 189,
205	G_FMINIMUM = 190,	205	G_FMINIMUM = 190,
206	G_FMAXIMUM = 191,	206	G_FMAXIMUM = 191,
207	G_PTR_ADD = 192,	207	G_PTR_ADD = 192,
208	G_PTRMASK = 193,	208	G_PTRMASK = 193,
209	G_SMIN = 194,	209	G_SMIN = 194,
210	G_SMAX = 195,	210	G_SMAX = 195,
211	G_UMIN = 196,	211	G_UMIN = 196,
212	G_UMAX = 197,	212	G_UMAX = 197,
213	G_ABS = 198,	213	G_ABS = 198,
214	G_LROUND = 199,	214	G_LROUND = 199,
215	G_LLROUND = 200,	215	G_LLROUND = 200,
216	G_BR = 201,	216	G_BR = 201,
217	G_BRJT = 202,	217	G_BRJT = 202,
218	G_INSERT_VECTOR_ELT = 203,	218	G_INSERT_VECTOR_ELT = 203,
219	G_EXTRACT_VECTOR_ELT = 204,	219	G_EXTRACT_VECTOR_ELT = 204,
220	G_SHUFFLE_VECTOR = 205,	220	G_SHUFFLE_VECTOR = 205,
221	G_CTTZ = 206,	221	G_CTTZ = 206,
222	G_CTTZ_ZERO_UNDEF = 207,	222	G_CTTZ_ZERO_UNDEF = 207,
223	G_CTLZ = 208,	223	G_CTLZ = 208,
224	G_CTLZ_ZERO_UNDEF = 209,	224	G_CTLZ_ZERO_UNDEF = 209,
225	G_CTPOP = 210,	225	G_CTPOP = 210,
226	G_BSWAP = 211,	226	G_BSWAP = 211,
227	G_BITREVERSE = 212,	227	G_BITREVERSE = 212,
228	G_FCEIL = 213,	228	G_FCEIL = 213,
229	G_FCOS = 214,	229	G_FCOS = 214,
230	G_FSIN = 215,	230	G_FSIN = 215,
231	G_FSQRT = 216,	231	G_FSQRT = 216,
232	G_FFLOOR = 217,	232	G_FFLOOR = 217,
233	G_FRINT = 218,	233	G_FRINT = 218,
234	G_FNEARBYINT = 219,	234	G_FNEARBYINT = 219,
235	G_ADDRSPACE_CAST = 220,	235	G_ADDRSPACE_CAST = 220,
236	G_BLOCK_ADDR = 221,	236	G_BLOCK_ADDR = 221,
237	G_JUMP_TABLE = 222,	237	G_JUMP_TABLE = 222,
238	G_DYN_STACKALLOC = 223,	238	G_DYN_STACKALLOC = 223,
239	G_STRICT_FADD = 224,	239	G_STRICT_FADD = 224,
240	G_STRICT_FSUB = 225,	240	G_STRICT_FSUB = 225,
241	G_STRICT_FMUL = 226,	241	G_STRICT_FMUL = 226,
242	G_STRICT_FDIV = 227,	242	G_STRICT_FDIV = 227,
243	G_STRICT_FREM = 228,	243	G_STRICT_FREM = 228,
244	G_STRICT_FMA = 229,	244	G_STRICT_FMA = 229,
245	G_STRICT_FSQRT = 230,	245	G_STRICT_FSQRT = 230,
246	G_STRICT_FLDEXP = 231,	246	G_STRICT_FLDEXP = 231,
247	G_READ_REGISTER = 232,	247	G_READ_REGISTER = 232,
248	G_WRITE_REGISTER = 233,	248	G_WRITE_REGISTER = 233,
249	G_MEMCPY = 234,	249	G_MEMCPY = 234,
250	G_MEMCPY_INLINE = 235,	250	G_MEMCPY_INLINE = 235,
251	G_MEMMOVE = 236,	251	G_MEMMOVE = 236,
252	G_MEMSET = 237,	252	G_MEMSET = 237,
253	G_BZERO = 238,	253	G_BZERO = 238,
254	G_VECREDUCE_SEQ_FADD = 239,	254	G_VECREDUCE_SEQ_FADD = 239,
255	G_VECREDUCE_SEQ_FMUL = 240,	255	G_VECREDUCE_SEQ_FMUL = 240,
256	G_VECREDUCE_FADD = 241,	256	G_VECREDUCE_FADD = 241,
257	G_VECREDUCE_FMUL = 242,	257	G_VECREDUCE_FMUL = 242,
258	G_VECREDUCE_FMAX = 243,	258	G_VECREDUCE_FMAX = 243,
259	G_VECREDUCE_FMIN = 244,	259	G_VECREDUCE_FMIN = 244,
260	G_VECREDUCE_ADD = 245,	260	G_VECREDUCE_ADD = 245,
261	G_VECREDUCE_MUL = 246,	261	G_VECREDUCE_MUL = 246,
262	G_VECREDUCE_AND = 247,	262	G_VECREDUCE_AND = 247,
263	G_VECREDUCE_OR = 248,	263	G_VECREDUCE_OR = 248,
264	G_VECREDUCE_XOR = 249,	264	G_VECREDUCE_XOR = 249,
265	G_VECREDUCE_SMAX = 250,	265	G_VECREDUCE_SMAX = 250,
266	G_VECREDUCE_SMIN = 251,	266	G_VECREDUCE_SMIN = 251,
267	G_VECREDUCE_UMAX = 252,	267	G_VECREDUCE_UMAX = 252,
268	G_VECREDUCE_UMIN = 253,	268	G_VECREDUCE_UMIN = 253,
269	G_SBFX = 254,	269	G_SBFX = 254,
270	G_UBFX = 255,	270	G_UBFX = 255,
271	ABSMacro = 256,	271	ABSMacro = 256,
272	ADJCALLSTACKDOWN = 257,	272	ADJCALLSTACKDOWN = 257,
273	ADJCALLSTACKUP = 258,	273	ADJCALLSTACKUP = 258,
274	AND_V_D_PSEUDO = 259,	274	AND_V_D_PSEUDO = 259,
275	AND_V_H_PSEUDO = 260,	275	AND_V_H_PSEUDO = 260,
276	AND_V_W_PSEUDO = 261,	276	AND_V_W_PSEUDO = 261,
277	ATOMIC_CMP_SWAP_I16 = 262,	277	ATOMIC_CMP_SWAP_I16 = 262,
278	ATOMIC_CMP_SWAP_I16_POSTRA = 263,	278	ATOMIC_CMP_SWAP_I16_POSTRA = 263,
279	ATOMIC_CMP_SWAP_I32 = 264,	279	ATOMIC_CMP_SWAP_I32 = 264,
280	ATOMIC_CMP_SWAP_I32_POSTRA = 265,	280	ATOMIC_CMP_SWAP_I32_POSTRA = 265,
281	ATOMIC_CMP_SWAP_I64 = 266,	281	ATOMIC_CMP_SWAP_I64 = 266,
282	ATOMIC_CMP_SWAP_I64_POSTRA = 267,	282	ATOMIC_CMP_SWAP_I64_POSTRA = 267,
283	ATOMIC_CMP_SWAP_I8 = 268,	283	ATOMIC_CMP_SWAP_I8 = 268,
284	ATOMIC_CMP_SWAP_I8_POSTRA = 269,	284	ATOMIC_CMP_SWAP_I8_POSTRA = 269,
285	ATOMIC_LOAD_ADD_I16 = 270,	285	ATOMIC_LOAD_ADD_I16 = 270,
286	ATOMIC_LOAD_ADD_I16_POSTRA = 271,	286	ATOMIC_LOAD_ADD_I16_POSTRA = 271,
287	ATOMIC_LOAD_ADD_I32 = 272,	287	ATOMIC_LOAD_ADD_I32 = 272,
288	ATOMIC_LOAD_ADD_I32_POSTRA = 273,	288	ATOMIC_LOAD_ADD_I32_POSTRA = 273,
289	ATOMIC_LOAD_ADD_I64 = 274,	289	ATOMIC_LOAD_ADD_I64 = 274,
290	ATOMIC_LOAD_ADD_I64_POSTRA = 275,	290	ATOMIC_LOAD_ADD_I64_POSTRA = 275,
291	ATOMIC_LOAD_ADD_I8 = 276,	291	ATOMIC_LOAD_ADD_I8 = 276,
292	ATOMIC_LOAD_ADD_I8_POSTRA = 277,	292	ATOMIC_LOAD_ADD_I8_POSTRA = 277,
293	ATOMIC_LOAD_AND_I16 = 278,	293	ATOMIC_LOAD_AND_I16 = 278,
294	ATOMIC_LOAD_AND_I16_POSTRA = 279,	294	ATOMIC_LOAD_AND_I16_POSTRA = 279,
295	ATOMIC_LOAD_AND_I32 = 280,	295	ATOMIC_LOAD_AND_I32 = 280,
296	ATOMIC_LOAD_AND_I32_POSTRA = 281,	296	ATOMIC_LOAD_AND_I32_POSTRA = 281,
297	ATOMIC_LOAD_AND_I64 = 282,	297	ATOMIC_LOAD_AND_I64 = 282,
298	ATOMIC_LOAD_AND_I64_POSTRA = 283,	298	ATOMIC_LOAD_AND_I64_POSTRA = 283,
299	ATOMIC_LOAD_AND_I8 = 284,	299	ATOMIC_LOAD_AND_I8 = 284,
300	ATOMIC_LOAD_AND_I8_POSTRA = 285,	300	ATOMIC_LOAD_AND_I8_POSTRA = 285,
301	ATOMIC_LOAD_MAX_I16 = 286,	301	ATOMIC_LOAD_MAX_I16 = 286,
302	ATOMIC_LOAD_MAX_I16_POSTRA = 287,	302	ATOMIC_LOAD_MAX_I16_POSTRA = 287,
303	ATOMIC_LOAD_MAX_I32 = 288,	303	ATOMIC_LOAD_MAX_I32 = 288,
304	ATOMIC_LOAD_MAX_I32_POSTRA = 289,	304	ATOMIC_LOAD_MAX_I32_POSTRA = 289,
305	ATOMIC_LOAD_MAX_I64 = 290,	305	ATOMIC_LOAD_MAX_I64 = 290,
306	ATOMIC_LOAD_MAX_I64_POSTRA = 291,	306	ATOMIC_LOAD_MAX_I64_POSTRA = 291,
307	ATOMIC_LOAD_MAX_I8 = 292,	307	ATOMIC_LOAD_MAX_I8 = 292,
308	ATOMIC_LOAD_MAX_I8_POSTRA = 293,	308	ATOMIC_LOAD_MAX_I8_POSTRA = 293,
309	ATOMIC_LOAD_MIN_I16 = 294,	309	ATOMIC_LOAD_MIN_I16 = 294,
310	ATOMIC_LOAD_MIN_I16_POSTRA = 295,	310	ATOMIC_LOAD_MIN_I16_POSTRA = 295,
311	ATOMIC_LOAD_MIN_I32 = 296,	311	ATOMIC_LOAD_MIN_I32 = 296,
312	ATOMIC_LOAD_MIN_I32_POSTRA = 297,	312	ATOMIC_LOAD_MIN_I32_POSTRA = 297,
313	ATOMIC_LOAD_MIN_I64 = 298,	313	ATOMIC_LOAD_MIN_I64 = 298,
314	ATOMIC_LOAD_MIN_I64_POSTRA = 299,	314	ATOMIC_LOAD_MIN_I64_POSTRA = 299,
315	ATOMIC_LOAD_MIN_I8 = 300,	315	ATOMIC_LOAD_MIN_I8 = 300,
316	ATOMIC_LOAD_MIN_I8_POSTRA = 301,	316	ATOMIC_LOAD_MIN_I8_POSTRA = 301,
317	ATOMIC_LOAD_NAND_I16 = 302,	317	ATOMIC_LOAD_NAND_I16 = 302,
318	ATOMIC_LOAD_NAND_I16_POSTRA = 303,	318	ATOMIC_LOAD_NAND_I16_POSTRA = 303,
319	ATOMIC_LOAD_NAND_I32 = 304,	319	ATOMIC_LOAD_NAND_I32 = 304,
320	ATOMIC_LOAD_NAND_I32_POSTRA = 305,	320	ATOMIC_LOAD_NAND_I32_POSTRA = 305,
321	ATOMIC_LOAD_NAND_I64 = 306,	321	ATOMIC_LOAD_NAND_I64 = 306,
322	ATOMIC_LOAD_NAND_I64_POSTRA = 307,	322	ATOMIC_LOAD_NAND_I64_POSTRA = 307,
323	ATOMIC_LOAD_NAND_I8 = 308,	323	ATOMIC_LOAD_NAND_I8 = 308,
324	ATOMIC_LOAD_NAND_I8_POSTRA = 309,	324	ATOMIC_LOAD_NAND_I8_POSTRA = 309,
325	ATOMIC_LOAD_OR_I16 = 310,	325	ATOMIC_LOAD_OR_I16 = 310,
326	ATOMIC_LOAD_OR_I16_POSTRA = 311,	326	ATOMIC_LOAD_OR_I16_POSTRA = 311,
327	ATOMIC_LOAD_OR_I32 = 312,	327	ATOMIC_LOAD_OR_I32 = 312,
328	ATOMIC_LOAD_OR_I32_POSTRA = 313,	328	ATOMIC_LOAD_OR_I32_POSTRA = 313,
329	ATOMIC_LOAD_OR_I64 = 314,	329	ATOMIC_LOAD_OR_I64 = 314,
330	ATOMIC_LOAD_OR_I64_POSTRA = 315,	330	ATOMIC_LOAD_OR_I64_POSTRA = 315,
331	ATOMIC_LOAD_OR_I8 = 316,	331	ATOMIC_LOAD_OR_I8 = 316,
332	ATOMIC_LOAD_OR_I8_POSTRA = 317,	332	ATOMIC_LOAD_OR_I8_POSTRA = 317,
333	ATOMIC_LOAD_SUB_I16 = 318,	333	ATOMIC_LOAD_SUB_I16 = 318,
334	ATOMIC_LOAD_SUB_I16_POSTRA = 319,	334	ATOMIC_LOAD_SUB_I16_POSTRA = 319,
335	ATOMIC_LOAD_SUB_I32 = 320,	335	ATOMIC_LOAD_SUB_I32 = 320,
336	ATOMIC_LOAD_SUB_I32_POSTRA = 321,	336	ATOMIC_LOAD_SUB_I32_POSTRA = 321,
337	ATOMIC_LOAD_SUB_I64 = 322,	337	ATOMIC_LOAD_SUB_I64 = 322,
338	ATOMIC_LOAD_SUB_I64_POSTRA = 323,	338	ATOMIC_LOAD_SUB_I64_POSTRA = 323,
339	ATOMIC_LOAD_SUB_I8 = 324,	339	ATOMIC_LOAD_SUB_I8 = 324,
340	ATOMIC_LOAD_SUB_I8_POSTRA = 325,	340	ATOMIC_LOAD_SUB_I8_POSTRA = 325,
341	ATOMIC_LOAD_UMAX_I16 = 326,	341	ATOMIC_LOAD_UMAX_I16 = 326,
342	ATOMIC_LOAD_UMAX_I16_POSTRA = 327,	342	ATOMIC_LOAD_UMAX_I16_POSTRA = 327,
343	ATOMIC_LOAD_UMAX_I32 = 328,	343	ATOMIC_LOAD_UMAX_I32 = 328,
344	ATOMIC_LOAD_UMAX_I32_POSTRA = 329,	344	ATOMIC_LOAD_UMAX_I32_POSTRA = 329,
345	ATOMIC_LOAD_UMAX_I64 = 330,	345	ATOMIC_LOAD_UMAX_I64 = 330,
346	ATOMIC_LOAD_UMAX_I64_POSTRA = 331,	346	ATOMIC_LOAD_UMAX_I64_POSTRA = 331,
347	ATOMIC_LOAD_UMAX_I8 = 332,	347	ATOMIC_LOAD_UMAX_I8 = 332,
348	ATOMIC_LOAD_UMAX_I8_POSTRA = 333,	348	ATOMIC_LOAD_UMAX_I8_POSTRA = 333,
349	ATOMIC_LOAD_UMIN_I16 = 334,	349	ATOMIC_LOAD_UMIN_I16 = 334,
350	ATOMIC_LOAD_UMIN_I16_POSTRA = 335,	350	ATOMIC_LOAD_UMIN_I16_POSTRA = 335,
351	ATOMIC_LOAD_UMIN_I32 = 336,	351	ATOMIC_LOAD_UMIN_I32 = 336,
352	ATOMIC_LOAD_UMIN_I32_POSTRA = 337,	352	ATOMIC_LOAD_UMIN_I32_POSTRA = 337,
353	ATOMIC_LOAD_UMIN_I64 = 338,	353	ATOMIC_LOAD_UMIN_I64 = 338,
354	ATOMIC_LOAD_UMIN_I64_POSTRA = 339,	354	ATOMIC_LOAD_UMIN_I64_POSTRA = 339,
355	ATOMIC_LOAD_UMIN_I8 = 340,	355	ATOMIC_LOAD_UMIN_I8 = 340,
356	ATOMIC_LOAD_UMIN_I8_POSTRA = 341,	356	ATOMIC_LOAD_UMIN_I8_POSTRA = 341,
357	ATOMIC_LOAD_XOR_I16 = 342,	357	ATOMIC_LOAD_XOR_I16 = 342,
358	ATOMIC_LOAD_XOR_I16_POSTRA = 343,	358	ATOMIC_LOAD_XOR_I16_POSTRA = 343,
359	ATOMIC_LOAD_XOR_I32 = 344,	359	ATOMIC_LOAD_XOR_I32 = 344,
360	ATOMIC_LOAD_XOR_I32_POSTRA = 345,	360	ATOMIC_LOAD_XOR_I32_POSTRA = 345,
361	ATOMIC_LOAD_XOR_I64 = 346,	361	ATOMIC_LOAD_XOR_I64 = 346,
362	ATOMIC_LOAD_XOR_I64_POSTRA = 347,	362	ATOMIC_LOAD_XOR_I64_POSTRA = 347,
363	ATOMIC_LOAD_XOR_I8 = 348,	363	ATOMIC_LOAD_XOR_I8 = 348,
364	ATOMIC_LOAD_XOR_I8_POSTRA = 349,	364	ATOMIC_LOAD_XOR_I8_POSTRA = 349,
365	ATOMIC_SWAP_I16 = 350,	365	ATOMIC_SWAP_I16 = 350,
366	ATOMIC_SWAP_I16_POSTRA = 351,	366	ATOMIC_SWAP_I16_POSTRA = 351,
367	ATOMIC_SWAP_I32 = 352,	367	ATOMIC_SWAP_I32 = 352,
368	ATOMIC_SWAP_I32_POSTRA = 353,	368	ATOMIC_SWAP_I32_POSTRA = 353,
369	ATOMIC_SWAP_I64 = 354,	369	ATOMIC_SWAP_I64 = 354,
370	ATOMIC_SWAP_I64_POSTRA = 355,	370	ATOMIC_SWAP_I64_POSTRA = 355,
371	ATOMIC_SWAP_I8 = 356,	371	ATOMIC_SWAP_I8 = 356,
372	ATOMIC_SWAP_I8_POSTRA = 357,	372	ATOMIC_SWAP_I8_POSTRA = 357,
373	B = 358,	373	B = 358,
374	BAL_BR = 359,	374	BAL_BR = 359,
375	BAL_BR_MM = 360,	375	BAL_BR_MM = 360,
376	BEQLImmMacro = 361,	376	BEQLImmMacro = 361,
377	BGE = 362,	377	BGE = 362,
378	BGEImmMacro = 363,	378	BGEImmMacro = 363,
379	BGEL = 364,	379	BGEL = 364,
380	BGELImmMacro = 365,	380	BGELImmMacro = 365,
381	BGEU = 366,	381	BGEU = 366,
382	BGEUImmMacro = 367,	382	BGEUImmMacro = 367,
383	BGEUL = 368,	383	BGEUL = 368,
384	BGEULImmMacro = 369,	384	BGEULImmMacro = 369,
385	BGT = 370,	385	BGT = 370,
386	BGTImmMacro = 371,	386	BGTImmMacro = 371,
387	BGTL = 372,	387	BGTL = 372,
388	BGTLImmMacro = 373,	388	BGTLImmMacro = 373,
389	BGTU = 374,	389	BGTU = 374,
390	BGTUImmMacro = 375,	390	BGTUImmMacro = 375,
391	BGTUL = 376,	391	BGTUL = 376,
392	BGTULImmMacro = 377,	392	BGTULImmMacro = 377,
393	BLE = 378,	393	BLE = 378,
394	BLEImmMacro = 379,	394	BLEImmMacro = 379,
395	BLEL = 380,	395	BLEL = 380,
396	BLELImmMacro = 381,	396	BLELImmMacro = 381,
397	BLEU = 382,	397	BLEU = 382,
398	BLEUImmMacro = 383,	398	BLEUImmMacro = 383,
399	BLEUL = 384,	399	BLEUL = 384,
400	BLEULImmMacro = 385,	400	BLEULImmMacro = 385,
401	BLT = 386,	401	BLT = 386,
402	BLTImmMacro = 387,	402	BLTImmMacro = 387,
403	BLTL = 388,	403	BLTL = 388,
404	BLTLImmMacro = 389,	404	BLTLImmMacro = 389,
405	BLTU = 390,	405	BLTU = 390,
406	BLTUImmMacro = 391,	406	BLTUImmMacro = 391,
407	BLTUL = 392,	407	BLTUL = 392,
408	BLTULImmMacro = 393,	408	BLTULImmMacro = 393,
409	BNELImmMacro = 394,	409	BNELImmMacro = 394,
410	BPOSGE32_PSEUDO = 395,	410	BPOSGE32_PSEUDO = 395,
411	BSEL_D_PSEUDO = 396,	411	BSEL_D_PSEUDO = 396,
412	BSEL_FD_PSEUDO = 397,	412	BSEL_FD_PSEUDO = 397,
413	BSEL_FW_PSEUDO = 398,	413	BSEL_FW_PSEUDO = 398,
414	BSEL_H_PSEUDO = 399,	414	BSEL_H_PSEUDO = 399,
415	BSEL_W_PSEUDO = 400,	415	BSEL_W_PSEUDO = 400,
416	B_MM = 401,	416	B_MM = 401,
417	B_MMR6_Pseudo = 402,	417	B_MMR6_Pseudo = 402,
418	B_MM_Pseudo = 403,	418	B_MM_Pseudo = 403,
419	BeqImm = 404,	419	BeqImm = 404,
420	BneImm = 405,	420	BneImm = 405,
421	BteqzT8CmpX16 = 406,	421	BteqzT8CmpX16 = 406,
422	BteqzT8CmpiX16 = 407,	422	BteqzT8CmpiX16 = 407,
423	BteqzT8SltX16 = 408,	423	BteqzT8SltX16 = 408,
424	BteqzT8SltiX16 = 409,	424	BteqzT8SltiX16 = 409,
425	BteqzT8SltiuX16 = 410,	425	BteqzT8SltiuX16 = 410,
426	BteqzT8SltuX16 = 411,	426	BteqzT8SltuX16 = 411,
427	BtnezT8CmpX16 = 412,	427	BtnezT8CmpX16 = 412,
428	BtnezT8CmpiX16 = 413,	428	BtnezT8CmpiX16 = 413,
429	BtnezT8SltX16 = 414,	429	BtnezT8SltX16 = 414,
430	BtnezT8SltiX16 = 415,	430	BtnezT8SltiX16 = 415,
431	BtnezT8SltiuX16 = 416,	431	BtnezT8SltiuX16 = 416,
432	BtnezT8SltuX16 = 417,	432	BtnezT8SltuX16 = 417,
433	BuildPairF64 = 418,	433	BuildPairF64 = 418,
434	BuildPairF64_64 = 419,	434	BuildPairF64_64 = 419,
435	CFTC1 = 420,	435	CFTC1 = 420,
436	CONSTPOOL_ENTRY = 421,	436	CONSTPOOL_ENTRY = 421,
437	COPY_FD_PSEUDO = 422,	437	COPY_FD_PSEUDO = 422,
438	COPY_FW_PSEUDO = 423,	438	COPY_FW_PSEUDO = 423,
439	CTTC1 = 424,	439	CTTC1 = 424,
440	Constant32 = 425,	440	Constant32 = 425,
441	DMULImmMacro = 426,	441	DMULImmMacro = 426,
442	DMULMacro = 427,	442	DMULMacro = 427,
443	DMULOMacro = 428,	443	DMULOMacro = 428,
444	DMULOUMacro = 429,	444	DMULOUMacro = 429,
445	DROL = 430,	445	DROL = 430,
446	DROLImm = 431,	446	DROLImm = 431,
447	DROR = 432,	447	DROR = 432,
448	DRORImm = 433,	448	DRORImm = 433,
449	DSDivIMacro = 434,	449	DSDivIMacro = 434,
450	DSDivMacro = 435,	450	DSDivMacro = 435,
451	DSRemIMacro = 436,	451	DSRemIMacro = 436,
452	DSRemMacro = 437,	452	DSRemMacro = 437,
453	DUDivIMacro = 438,	453	DUDivIMacro = 438,
454	DUDivMacro = 439,	454	DUDivMacro = 439,
455	DURemIMacro = 440,	455	DURemIMacro = 440,
456	DURemMacro = 441,	456	DURemMacro = 441,
457	ERet = 442,	457	ERet = 442,
458	ExtractElementF64 = 443,	458	ExtractElementF64 = 443,
459	ExtractElementF64_64 = 444,	459	ExtractElementF64_64 = 444,
460	FABS_D = 445,	460	FABS_D = 445,
461	FABS_W = 446,	461	FABS_W = 446,
462	FEXP2_D_1_PSEUDO = 447,	462	FEXP2_D_1_PSEUDO = 447,
463	FEXP2_W_1_PSEUDO = 448,	463	FEXP2_W_1_PSEUDO = 448,
464	FILL_FD_PSEUDO = 449,	464	FILL_FD_PSEUDO = 449,
465	FILL_FW_PSEUDO = 450,	465	FILL_FW_PSEUDO = 450,
466	GotPrologue16 = 451,	466	GotPrologue16 = 451,
467	INSERT_B_VIDX64_PSEUDO = 452,	467	INSERT_B_VIDX64_PSEUDO = 452,
468	INSERT_B_VIDX_PSEUDO = 453,	468	INSERT_B_VIDX_PSEUDO = 453,
469	INSERT_D_VIDX64_PSEUDO = 454,	469	INSERT_D_VIDX64_PSEUDO = 454,
470	INSERT_D_VIDX_PSEUDO = 455,	470	INSERT_D_VIDX_PSEUDO = 455,
471	INSERT_FD_PSEUDO = 456,	471	INSERT_FD_PSEUDO = 456,
472	INSERT_FD_VIDX64_PSEUDO = 457,	472	INSERT_FD_VIDX64_PSEUDO = 457,
473	INSERT_FD_VIDX_PSEUDO = 458,	473	INSERT_FD_VIDX_PSEUDO = 458,
474	INSERT_FW_PSEUDO = 459,	474	INSERT_FW_PSEUDO = 459,
475	INSERT_FW_VIDX64_PSEUDO = 460,	475	INSERT_FW_VIDX64_PSEUDO = 460,
476	INSERT_FW_VIDX_PSEUDO = 461,	476	INSERT_FW_VIDX_PSEUDO = 461,
477	INSERT_H_VIDX64_PSEUDO = 462,	477	INSERT_H_VIDX64_PSEUDO = 462,
478	INSERT_H_VIDX_PSEUDO = 463,	478	INSERT_H_VIDX_PSEUDO = 463,
479	INSERT_W_VIDX64_PSEUDO = 464,	479	INSERT_W_VIDX64_PSEUDO = 464,
480	INSERT_W_VIDX_PSEUDO = 465,	480	INSERT_W_VIDX_PSEUDO = 465,
481	JALR64Pseudo = 466,	481	JALR64Pseudo = 466,
482	JALRHB64Pseudo = 467,	482	JALRHB64Pseudo = 467,
483	JALRHBPseudo = 468,	483	JALRHBPseudo = 468,
484	JALRPseudo = 469,	484	JALRPseudo = 469,
485	JAL_MMR6 = 470,	485	JAL_MMR6 = 470,
486	JalOneReg = 471,	486	JalOneReg = 471,
487	JalTwoReg = 472,	487	JalTwoReg = 472,
488	LDMacro = 473,	488	LDMacro = 473,
489	LDR_D = 474,	489	LDR_D = 474,
490	LDR_W = 475,	490	LDR_W = 475,
491	LD_F16 = 476,	491	LD_F16 = 476,
492	LOAD_ACC128 = 477,	492	LOAD_ACC128 = 477,
493	LOAD_ACC64 = 478,	493	LOAD_ACC64 = 478,
494	LOAD_ACC64DSP = 479,	494	LOAD_ACC64DSP = 479,
495	LOAD_CCOND_DSP = 480,	495	LOAD_CCOND_DSP = 480,
496	LONG_BRANCH_ADDiu = 481,	496	LONG_BRANCH_ADDiu = 481,
497	LONG_BRANCH_ADDiu2Op = 482,	497	LONG_BRANCH_ADDiu2Op = 482,
498	LONG_BRANCH_DADDiu = 483,	498	LONG_BRANCH_DADDiu = 483,
499	LONG_BRANCH_DADDiu2Op = 484,	499	LONG_BRANCH_DADDiu2Op = 484,
500	LONG_BRANCH_LUi = 485,	500	LONG_BRANCH_LUi = 485,
501	LONG_BRANCH_LUi2Op = 486,	501	LONG_BRANCH_LUi2Op = 486,
502	LONG_BRANCH_LUi2Op_64 = 487,	502	LONG_BRANCH_LUi2Op_64 = 487,
503	LWM_MM = 488,	503	LWM_MM = 488,
504	LoadAddrImm32 = 489,	504	LoadAddrImm32 = 489,
505	LoadAddrImm64 = 490,	505	LoadAddrImm64 = 490,
506	LoadAddrReg32 = 491,	506	LoadAddrReg32 = 491,
507	LoadAddrReg64 = 492,	507	LoadAddrReg64 = 492,
508	LoadImm32 = 493,	508	LoadImm32 = 493,
509	LoadImm64 = 494,	509	LoadImm64 = 494,
510	LoadImmDoubleFGR = 495,	510	LoadImmDoubleFGR = 495,
511	LoadImmDoubleFGR_32 = 496,	511	LoadImmDoubleFGR_32 = 496,
512	LoadImmDoubleGPR = 497,	512	LoadImmDoubleGPR = 497,
513	LoadImmSingleFGR = 498,	513	LoadImmSingleFGR = 498,
514	LoadImmSingleGPR = 499,	514	LoadImmSingleGPR = 499,
515	LwConstant32 = 500,	515	LwConstant32 = 500,
516	MFTACX = 501,	516	MFTACX = 501,
517	MFTC0 = 502,	517	MFTC0 = 502,
518	MFTC1 = 503,	518	MFTC1 = 503,
519	MFTDSP = 504,	519	MFTDSP = 504,
520	MFTGPR = 505,	520	MFTGPR = 505,
521	MFTHC1 = 506,	521	MFTHC1 = 506,
522	MFTHI = 507,	522	MFTHI = 507,
523	MFTLO = 508,	523	MFTLO = 508,
524	MIPSeh_return32 = 509,	524	MIPSeh_return32 = 509,
525	MIPSeh_return64 = 510,	525	MIPSeh_return64 = 510,
526	MSA_FP_EXTEND_D_PSEUDO = 511,	526	MSA_FP_EXTEND_D_PSEUDO = 511,
527	MSA_FP_EXTEND_W_PSEUDO = 512,	527	MSA_FP_EXTEND_W_PSEUDO = 512,
528	MSA_FP_ROUND_D_PSEUDO = 513,	528	MSA_FP_ROUND_D_PSEUDO = 513,
529	MSA_FP_ROUND_W_PSEUDO = 514,	529	MSA_FP_ROUND_W_PSEUDO = 514,
530	MTTACX = 515,	530	MTTACX = 515,
531	MTTC0 = 516,	531	MTTC0 = 516,
532	MTTC1 = 517,	532	MTTC1 = 517,
533	MTTDSP = 518,	533	MTTDSP = 518,
534	MTTGPR = 519,	534	MTTGPR = 519,
535	MTTHC1 = 520,	535	MTTHC1 = 520,
536	MTTHI = 521,	536	MTTHI = 521,
537	MTTLO = 522,	537	MTTLO = 522,
538	MULImmMacro = 523,	538	MULImmMacro = 523,
539	MULOMacro = 524,	539	MULOMacro = 524,
540	MULOUMacro = 525,	540	MULOUMacro = 525,
541	MultRxRy16 = 526,	541	MultRxRy16 = 526,
542	MultRxRyRz16 = 527,	542	MultRxRyRz16 = 527,
543	MultuRxRy16 = 528,	543	MultuRxRy16 = 528,
544	MultuRxRyRz16 = 529,	544	MultuRxRyRz16 = 529,
545	NOP = 530,	545	NOP = 530,
546	NORImm = 531,	546	NORImm = 531,
547	NORImm64 = 532,	547	NORImm64 = 532,
548	NOR_V_D_PSEUDO = 533,	548	NOR_V_D_PSEUDO = 533,
549	NOR_V_H_PSEUDO = 534,	549	NOR_V_H_PSEUDO = 534,
550	NOR_V_W_PSEUDO = 535,	550	NOR_V_W_PSEUDO = 535,
551	OR_V_D_PSEUDO = 536,	551	OR_V_D_PSEUDO = 536,
552	OR_V_H_PSEUDO = 537,	552	OR_V_H_PSEUDO = 537,
553	OR_V_W_PSEUDO = 538,	553	OR_V_W_PSEUDO = 538,
554	PseudoCMPU_EQ_QB = 539,	554	PseudoCMPU_EQ_QB = 539,
555	PseudoCMPU_LE_QB = 540,	555	PseudoCMPU_LE_QB = 540,
556	PseudoCMPU_LT_QB = 541,	556	PseudoCMPU_LT_QB = 541,
557	PseudoCMP_EQ_PH = 542,	557	PseudoCMP_EQ_PH = 542,
558	PseudoCMP_LE_PH = 543,	558	PseudoCMP_LE_PH = 543,
559	PseudoCMP_LT_PH = 544,	559	PseudoCMP_LT_PH = 544,
560	PseudoCVT_D32_W = 545,	560	PseudoCVT_D32_W = 545,
561	PseudoCVT_D64_L = 546,	561	PseudoCVT_D64_L = 546,
562	PseudoCVT_D64_W = 547,	562	PseudoCVT_D64_W = 547,
563	PseudoCVT_S_L = 548,	563	PseudoCVT_S_L = 548,
564	PseudoCVT_S_W = 549,	564	PseudoCVT_S_W = 549,
565	PseudoDMULT = 550,	565	PseudoDMULT = 550,
566	PseudoDMULTu = 551,	566	PseudoDMULTu = 551,
567	PseudoDSDIV = 552,	567	PseudoDSDIV = 552,
568	PseudoDUDIV = 553,	568	PseudoDUDIV = 553,
569	PseudoD_SELECT_I = 554,	569	PseudoD_SELECT_I = 554,
570	PseudoD_SELECT_I64 = 555,	570	PseudoD_SELECT_I64 = 555,
571	PseudoIndirectBranch = 556,	571	PseudoIndirectBranch = 556,
572	PseudoIndirectBranch64 = 557,	572	PseudoIndirectBranch64 = 557,
573	PseudoIndirectBranch64R6 = 558,	573	PseudoIndirectBranch64R6 = 558,
574	PseudoIndirectBranchR6 = 559,	574	PseudoIndirectBranchR6 = 559,
575	PseudoIndirectBranch_MM = 560,	575	PseudoIndirectBranch_MM = 560,
576	PseudoIndirectBranch_MMR6 = 561,	576	PseudoIndirectBranch_MMR6 = 561,
577	PseudoIndirectHazardBranch = 562,	577	PseudoIndirectHazardBranch = 562,
578	PseudoIndirectHazardBranch64 = 563,	578	PseudoIndirectHazardBranch64 = 563,
579	PseudoIndrectHazardBranch64R6 = 564,	579	PseudoIndrectHazardBranch64R6 = 564,
580	PseudoIndrectHazardBranchR6 = 565,	580	PseudoIndrectHazardBranchR6 = 565,
581	PseudoMADD = 566,	581	PseudoMADD = 566,
582	PseudoMADDU = 567,	582	PseudoMADDU = 567,
583	PseudoMADDU_MM = 568,	583	PseudoMADDU_MM = 568,
584	PseudoMADD_MM = 569,	584	PseudoMADD_MM = 569,
585	PseudoMFHI = 570,	585	PseudoMFHI = 570,
586	PseudoMFHI64 = 571,	586	PseudoMFHI64 = 571,
587	PseudoMFHI_MM = 572,	587	PseudoMFHI_MM = 572,
588	PseudoMFLO = 573,	588	PseudoMFLO = 573,
589	PseudoMFLO64 = 574,	589	PseudoMFLO64 = 574,
590	PseudoMFLO_MM = 575,	590	PseudoMFLO_MM = 575,
591	PseudoMSUB = 576,	591	PseudoMSUB = 576,
592	PseudoMSUBU = 577,	592	PseudoMSUBU = 577,
593	PseudoMSUBU_MM = 578,	593	PseudoMSUBU_MM = 578,
594	PseudoMSUB_MM = 579,	594	PseudoMSUB_MM = 579,
595	PseudoMTLOHI = 580,	595	PseudoMTLOHI = 580,
596	PseudoMTLOHI64 = 581,	596	PseudoMTLOHI64 = 581,
597	PseudoMTLOHI_DSP = 582,	597	PseudoMTLOHI_DSP = 582,
598	PseudoMTLOHI_MM = 583,	598	PseudoMTLOHI_MM = 583,
599	PseudoMULT = 584,	599	PseudoMULT = 584,
600	PseudoMULT_MM = 585,	600	PseudoMULT_MM = 585,
601	PseudoMULTu = 586,	601	PseudoMULTu = 586,
602	PseudoMULTu_MM = 587,	602	PseudoMULTu_MM = 587,
603	PseudoPICK_PH = 588,	603	PseudoPICK_PH = 588,
604	PseudoPICK_QB = 589,	604	PseudoPICK_QB = 589,
605	PseudoReturn = 590,	605	PseudoReturn = 590,
606	PseudoReturn64 = 591,	606	PseudoReturn64 = 591,
607	PseudoSDIV = 592,	607	PseudoSDIV = 592,
608	PseudoSELECTFP_F_D32 = 593,	608	PseudoSELECTFP_F_D32 = 593,
609	PseudoSELECTFP_F_D64 = 594,	609	PseudoSELECTFP_F_D64 = 594,
610	PseudoSELECTFP_F_I = 595,	610	PseudoSELECTFP_F_I = 595,
611	PseudoSELECTFP_F_I64 = 596,	611	PseudoSELECTFP_F_I64 = 596,
612	PseudoSELECTFP_F_S = 597,	612	PseudoSELECTFP_F_S = 597,
613	PseudoSELECTFP_T_D32 = 598,	613	PseudoSELECTFP_T_D32 = 598,
614	PseudoSELECTFP_T_D64 = 599,	614	PseudoSELECTFP_T_D64 = 599,
615	PseudoSELECTFP_T_I = 600,	615	PseudoSELECTFP_T_I = 600,
616	PseudoSELECTFP_T_I64 = 601,	616	PseudoSELECTFP_T_I64 = 601,
617	PseudoSELECTFP_T_S = 602,	617	PseudoSELECTFP_T_S = 602,
618	PseudoSELECT_D32 = 603,	618	PseudoSELECT_D32 = 603,
619	PseudoSELECT_D64 = 604,	619	PseudoSELECT_D64 = 604,
620	PseudoSELECT_I = 605,	620	PseudoSELECT_I = 605,
621	PseudoSELECT_I64 = 606,	621	PseudoSELECT_I64 = 606,
622	PseudoSELECT_S = 607,	622	PseudoSELECT_S = 607,
623	PseudoTRUNC_W_D = 608,	623	PseudoTRUNC_W_D = 608,
624	PseudoTRUNC_W_D32 = 609,	624	PseudoTRUNC_W_D32 = 609,
625	PseudoTRUNC_W_S = 610,	625	PseudoTRUNC_W_S = 610,
626	PseudoUDIV = 611,	626	PseudoUDIV = 611,
627	ROL = 612,	627	ROL = 612,
628	ROLImm = 613,	628	ROLImm = 613,
629	ROR = 614,	629	ROR = 614,
630	RORImm = 615,	630	RORImm = 615,
631	RetRA = 616,	631	RetRA = 616,
632	RetRA16 = 617,	632	RetRA16 = 617,
633	SDC1_M1 = 618,	633	SDC1_M1 = 618,
634	SDIV_MM_Pseudo = 619,	634	SDIV_MM_Pseudo = 619,
635	SDMacro = 620,	635	SDMacro = 620,
636	SDivIMacro = 621,	636	SDivIMacro = 621,
637	SDivMacro = 622,	637	SDivMacro = 622,
638	SEQIMacro = 623,	638	SEQIMacro = 623,
639	SEQMacro = 624,	639	SEQMacro = 624,
640	SGE = 625,	640	SGE = 625,
641	SGEImm = 626,	641	SGEImm = 626,
642	SGEImm64 = 627,	642	SGEImm64 = 627,
643	SGEU = 628,	643	SGEU = 628,
644	SGEUImm = 629,	644	SGEUImm = 629,
645	SGEUImm64 = 630,	645	SGEUImm64 = 630,
646	SGTImm = 631,	646	SGTImm = 631,
647	SGTImm64 = 632,	647	SGTImm64 = 632,
648	SGTUImm = 633,	648	SGTUImm = 633,
649	SGTUImm64 = 634,	649	SGTUImm64 = 634,
650	SLE = 635,	650	SLE = 635,
651	SLEImm = 636,	651	SLEImm = 636,
652	SLEImm64 = 637,	652	SLEImm64 = 637,
653	SLEU = 638,	653	SLEU = 638,
654	SLEUImm = 639,	654	SLEUImm = 639,
655	SLEUImm64 = 640,	655	SLEUImm64 = 640,
656	SLTImm64 = 641,	656	SLTImm64 = 641,
657	SLTUImm64 = 642,	657	SLTUImm64 = 642,
658	SNEIMacro = 643,	658	SNEIMacro = 643,
659	SNEMacro = 644,	659	SNEMacro = 644,
660	SNZ_B_PSEUDO = 645,	660	SNZ_B_PSEUDO = 645,
661	SNZ_D_PSEUDO = 646,	661	SNZ_D_PSEUDO = 646,
662	SNZ_H_PSEUDO = 647,	662	SNZ_H_PSEUDO = 647,
663	SNZ_V_PSEUDO = 648,	663	SNZ_V_PSEUDO = 648,
664	SNZ_W_PSEUDO = 649,	664	SNZ_W_PSEUDO = 649,
665	SRemIMacro = 650,	665	SRemIMacro = 650,
666	SRemMacro = 651,	666	SRemMacro = 651,
667	STORE_ACC128 = 652,	667	STORE_ACC128 = 652,
668	STORE_ACC64 = 653,	668	STORE_ACC64 = 653,
669	STORE_ACC64DSP = 654,	669	STORE_ACC64DSP = 654,
670	STORE_CCOND_DSP = 655,	670	STORE_CCOND_DSP = 655,
671	STR_D = 656,	671	STR_D = 656,
672	STR_W = 657,	672	STR_W = 657,
673	ST_F16 = 658,	673	ST_F16 = 658,
674	SWM_MM = 659,	674	SWM_MM = 659,
675	SZ_B_PSEUDO = 660,	675	SZ_B_PSEUDO = 660,
676	SZ_D_PSEUDO = 661,	676	SZ_D_PSEUDO = 661,
677	SZ_H_PSEUDO = 662,	677	SZ_H_PSEUDO = 662,
678	SZ_V_PSEUDO = 663,	678	SZ_V_PSEUDO = 663,
679	SZ_W_PSEUDO = 664,	679	SZ_W_PSEUDO = 664,
680	SaaAddr = 665,	680	SaaAddr = 665,
681	SaadAddr = 666,	681	SaadAddr = 666,
682	SelBeqZ = 667,	682	SelBeqZ = 667,
683	SelBneZ = 668,	683	SelBneZ = 668,
684	SelTBteqZCmp = 669,	684	SelTBteqZCmp = 669,
685	SelTBteqZCmpi = 670,	685	SelTBteqZCmpi = 670,
686	SelTBteqZSlt = 671,	686	SelTBteqZSlt = 671,
687	SelTBteqZSlti = 672,	687	SelTBteqZSlti = 672,
688	SelTBteqZSltiu = 673,	688	SelTBteqZSltiu = 673,
689	SelTBteqZSltu = 674,	689	SelTBteqZSltu = 674,
690	SelTBtneZCmp = 675,	690	SelTBtneZCmp = 675,
691	SelTBtneZCmpi = 676,	691	SelTBtneZCmpi = 676,
692	SelTBtneZSlt = 677,	692	SelTBtneZSlt = 677,
693	SelTBtneZSlti = 678,	693	SelTBtneZSlti = 678,
694	SelTBtneZSltiu = 679,	694	SelTBtneZSltiu = 679,
695	SelTBtneZSltu = 680,	695	SelTBtneZSltu = 680,
696	SltCCRxRy16 = 681,	696	SltCCRxRy16 = 681,
697	SltiCCRxImmX16 = 682,	697	SltiCCRxImmX16 = 682,
698	SltiuCCRxImmX16 = 683,	698	SltiuCCRxImmX16 = 683,
699	SltuCCRxRy16 = 684,	699	SltuCCRxRy16 = 684,
700	SltuRxRyRz16 = 685,	700	SltuRxRyRz16 = 685,
701	TAILCALL = 686,	701	TAILCALL = 686,
702	TAILCALL64R6REG = 687,	702	TAILCALL64R6REG = 687,
703	TAILCALLHB64R6REG = 688,	703	TAILCALLHB64R6REG = 688,
704	TAILCALLHBR6REG = 689,	704	TAILCALLHBR6REG = 689,
705	TAILCALLR6REG = 690,	705	TAILCALLR6REG = 690,
706	TAILCALLREG = 691,	706	TAILCALLREG = 691,
707	TAILCALLREG64 = 692,	707	TAILCALLREG64 = 692,
708	TAILCALLREGHB = 693,	708	TAILCALLREGHB = 693,
709	TAILCALLREGHB64 = 694,	709	TAILCALLREGHB64 = 694,
710	TAILCALLREG_MM = 695,	710	TAILCALLREG_MM = 695,
711	TAILCALLREG_MMR6 = 696,	711	TAILCALLREG_MMR6 = 696,
712	TAILCALL_MM = 697,	712	TAILCALL_MM = 697,
713	TAILCALL_MMR6 = 698,	713	TAILCALL_MMR6 = 698,
714	TRAP = 699,	714	TRAP = 699,
715	TRAP_MM = 700,	715	TRAP_MM = 700,
716	UDIV_MM_Pseudo = 701,	716	UDIV_MM_Pseudo = 701,
717	UDivIMacro = 702,	717	UDivIMacro = 702,
718	UDivMacro = 703,	718	UDivMacro = 703,
719	URemIMacro = 704,	719	URemIMacro = 704,
720	URemMacro = 705,	720	URemMacro = 705,
721	Ulh = 706,	721	Ulh = 706,
722	Ulhu = 707,	722	Ulhu = 707,
723	Ulw = 708,	723	Ulw = 708,
724	Ush = 709,	724	Ush = 709,
725	Usw = 710,	725	Usw = 710,
726	XOR_V_D_PSEUDO = 711,	726	XOR_V_D_PSEUDO = 711,
727	XOR_V_H_PSEUDO = 712,	727	XOR_V_H_PSEUDO = 712,
728	XOR_V_W_PSEUDO = 713,	728	XOR_V_W_PSEUDO = 713,
729	ABSQ_S_PH = 714,	729	ABSQ_S_PH = 714,
730	ABSQ_S_PH_MM = 715,	730	ABSQ_S_PH_MM = 715,
731	ABSQ_S_QB = 716,	731	ABSQ_S_QB = 716,
732	ABSQ_S_QB_MMR2 = 717,	732	ABSQ_S_QB_MMR2 = 717,
733	ABSQ_S_W = 718,	733	ABSQ_S_W = 718,
734	ABSQ_S_W_MM = 719,	734	ABSQ_S_W_MM = 719,
735	ADD = 720,	735	ADD = 720,
736	ADDIUPC = 721,	736	ADDIUPC = 721,
737	ADDIUPC_MM = 722,	737	ADDIUPC_MM = 722,
738	ADDIUPC_MMR6 = 723,	738	ADDIUPC_MMR6 = 723,
739	ADDIUR1SP_MM = 724,	739	ADDIUR1SP_MM = 724,
740	ADDIUR2_MM = 725,	740	ADDIUR2_MM = 725,
741	ADDIUS5_MM = 726,	741	ADDIUS5_MM = 726,
742	ADDIUSP_MM = 727,	742	ADDIUSP_MM = 727,
743	ADDIU_MMR6 = 728,	743	ADDIU_MMR6 = 728,
744	ADDQH_PH = 729,	744	ADDQH_PH = 729,
745	ADDQH_PH_MMR2 = 730,	745	ADDQH_PH_MMR2 = 730,
746	ADDQH_R_PH = 731,	746	ADDQH_R_PH = 731,
747	ADDQH_R_PH_MMR2 = 732,	747	ADDQH_R_PH_MMR2 = 732,
748	ADDQH_R_W = 733,	748	ADDQH_R_W = 733,
749	ADDQH_R_W_MMR2 = 734,	749	ADDQH_R_W_MMR2 = 734,
750	ADDQH_W = 735,	750	ADDQH_W = 735,
751	ADDQH_W_MMR2 = 736,	751	ADDQH_W_MMR2 = 736,
752	ADDQ_PH = 737,	752	ADDQ_PH = 737,
753	ADDQ_PH_MM = 738,	753	ADDQ_PH_MM = 738,
754	ADDQ_S_PH = 739,	754	ADDQ_S_PH = 739,
755	ADDQ_S_PH_MM = 740,	755	ADDQ_S_PH_MM = 740,
756	ADDQ_S_W = 741,	756	ADDQ_S_W = 741,
757	ADDQ_S_W_MM = 742,	757	ADDQ_S_W_MM = 742,
758	ADDR_PS64 = 743,	758	ADDR_PS64 = 743,
759	ADDSC = 744,	759	ADDSC = 744,
760	ADDSC_MM = 745,	760	ADDSC_MM = 745,
761	ADDS_A_B = 746,	761	ADDS_A_B = 746,
762	ADDS_A_D = 747,	762	ADDS_A_D = 747,
763	ADDS_A_H = 748,	763	ADDS_A_H = 748,
764	ADDS_A_W = 749,	764	ADDS_A_W = 749,
765	ADDS_S_B = 750,	765	ADDS_S_B = 750,
766	ADDS_S_D = 751,	766	ADDS_S_D = 751,
767	ADDS_S_H = 752,	767	ADDS_S_H = 752,
768	ADDS_S_W = 753,	768	ADDS_S_W = 753,
769	ADDS_U_B = 754,	769	ADDS_U_B = 754,
770	ADDS_U_D = 755,	770	ADDS_U_D = 755,
771	ADDS_U_H = 756,	771	ADDS_U_H = 756,
772	ADDS_U_W = 757,	772	ADDS_U_W = 757,
773	ADDU16_MM = 758,	773	ADDU16_MM = 758,
774	ADDU16_MMR6 = 759,	774	ADDU16_MMR6 = 759,
775	ADDUH_QB = 760,	775	ADDUH_QB = 760,
776	ADDUH_QB_MMR2 = 761,	776	ADDUH_QB_MMR2 = 761,
777	ADDUH_R_QB = 762,	777	ADDUH_R_QB = 762,
778	ADDUH_R_QB_MMR2 = 763,	778	ADDUH_R_QB_MMR2 = 763,
779	ADDU_MMR6 = 764,	779	ADDU_MMR6 = 764,
780	ADDU_PH = 765,	780	ADDU_PH = 765,
781	ADDU_PH_MMR2 = 766,	781	ADDU_PH_MMR2 = 766,
782	ADDU_QB = 767,	782	ADDU_QB = 767,
783	ADDU_QB_MM = 768,	783	ADDU_QB_MM = 768,
784	ADDU_S_PH = 769,	784	ADDU_S_PH = 769,
785	ADDU_S_PH_MMR2 = 770,	785	ADDU_S_PH_MMR2 = 770,
786	ADDU_S_QB = 771,	786	ADDU_S_QB = 771,
787	ADDU_S_QB_MM = 772,	787	ADDU_S_QB_MM = 772,
788	ADDVI_B = 773,	788	ADDVI_B = 773,
789	ADDVI_D = 774,	789	ADDVI_D = 774,
790	ADDVI_H = 775,	790	ADDVI_H = 775,
791	ADDVI_W = 776,	791	ADDVI_W = 776,
792	ADDV_B = 777,	792	ADDV_B = 777,
793	ADDV_D = 778,	793	ADDV_D = 778,
794	ADDV_H = 779,	794	ADDV_H = 779,
795	ADDV_W = 780,	795	ADDV_W = 780,
796	ADDWC = 781,	796	ADDWC = 781,
797	ADDWC_MM = 782,	797	ADDWC_MM = 782,
798	ADD_A_B = 783,	798	ADD_A_B = 783,
799	ADD_A_D = 784,	799	ADD_A_D = 784,
800	ADD_A_H = 785,	800	ADD_A_H = 785,
801	ADD_A_W = 786,	801	ADD_A_W = 786,
802	ADD_MM = 787,	802	ADD_MM = 787,
803	ADD_MMR6 = 788,	803	ADD_MMR6 = 788,
804	ADDi = 789,	804	ADDi = 789,
805	ADDi_MM = 790,	805	ADDi_MM = 790,
806	ADDiu = 791,	806	ADDiu = 791,
807	ADDiu_MM = 792,	807	ADDiu_MM = 792,
808	ADDu = 793,	808	ADDu = 793,
809	ADDu_MM = 794,	809	ADDu_MM = 794,
810	ALIGN = 795,	810	ALIGN = 795,
811	ALIGN_MMR6 = 796,	811	ALIGN_MMR6 = 796,
812	ALUIPC = 797,	812	ALUIPC = 797,
813	ALUIPC_MMR6 = 798,	813	ALUIPC_MMR6 = 798,
814	AND = 799,	814	AND = 799,
815	AND16_MM = 800,	815	AND16_MM = 800,
816	AND16_MMR6 = 801,	816	AND16_MMR6 = 801,
817	AND64 = 802,	817	AND64 = 802,
818	ANDI16_MM = 803,	818	ANDI16_MM = 803,
819	ANDI16_MMR6 = 804,	819	ANDI16_MMR6 = 804,
820	ANDI_B = 805,	820	ANDI_B = 805,
821	ANDI_MMR6 = 806,	821	ANDI_MMR6 = 806,
822	AND_MM = 807,	822	AND_MM = 807,
823	AND_MMR6 = 808,	823	AND_MMR6 = 808,
824	AND_V = 809,	824	AND_V = 809,
825	ANDi = 810,	825	ANDi = 810,
826	ANDi64 = 811,	826	ANDi64 = 811,
827	ANDi_MM = 812,	827	ANDi_MM = 812,
828	APPEND = 813,	828	APPEND = 813,
829	APPEND_MMR2 = 814,	829	APPEND_MMR2 = 814,
830	ASUB_S_B = 815,	830	ASUB_S_B = 815,
831	ASUB_S_D = 816,	831	ASUB_S_D = 816,
832	ASUB_S_H = 817,	832	ASUB_S_H = 817,
833	ASUB_S_W = 818,	833	ASUB_S_W = 818,
834	ASUB_U_B = 819,	834	ASUB_U_B = 819,
835	ASUB_U_D = 820,	835	ASUB_U_D = 820,
836	ASUB_U_H = 821,	836	ASUB_U_H = 821,
837	ASUB_U_W = 822,	837	ASUB_U_W = 822,
838	AUI = 823,	838	AUI = 823,
839	AUIPC = 824,	839	AUIPC = 824,
840	AUIPC_MMR6 = 825,	840	AUIPC_MMR6 = 825,
841	AUI_MMR6 = 826,	841	AUI_MMR6 = 826,
842	AVER_S_B = 827,	842	AVER_S_B = 827,
843	AVER_S_D = 828,	843	AVER_S_D = 828,
844	AVER_S_H = 829,	844	AVER_S_H = 829,
845	AVER_S_W = 830,	845	AVER_S_W = 830,
846	AVER_U_B = 831,	846	AVER_U_B = 831,
847	AVER_U_D = 832,	847	AVER_U_D = 832,
848	AVER_U_H = 833,	848	AVER_U_H = 833,
849	AVER_U_W = 834,	849	AVER_U_W = 834,
850	AVE_S_B = 835,	850	AVE_S_B = 835,
851	AVE_S_D = 836,	851	AVE_S_D = 836,
852	AVE_S_H = 837,	852	AVE_S_H = 837,
853	AVE_S_W = 838,	853	AVE_S_W = 838,
854	AVE_U_B = 839,	854	AVE_U_B = 839,
855	AVE_U_D = 840,	855	AVE_U_D = 840,
856	AVE_U_H = 841,	856	AVE_U_H = 841,
857	AVE_U_W = 842,	857	AVE_U_W = 842,
858	AddiuRxImmX16 = 843,	858	AddiuRxImmX16 = 843,
859	AddiuRxPcImmX16 = 844,	859	AddiuRxPcImmX16 = 844,
860	AddiuRxRxImm16 = 845,	860	AddiuRxRxImm16 = 845,
861	AddiuRxRxImmX16 = 846,	861	AddiuRxRxImmX16 = 846,
862	AddiuRxRyOffMemX16 = 847,	862	AddiuRxRyOffMemX16 = 847,
863	AddiuSpImm16 = 848,	863	AddiuSpImm16 = 848,
864	AddiuSpImmX16 = 849,	864	AddiuSpImmX16 = 849,
865	AdduRxRyRz16 = 850,	865	AdduRxRyRz16 = 850,
866	AndRxRxRy16 = 851,	866	AndRxRxRy16 = 851,
867	B16_MM = 852,	867	B16_MM = 852,
868	BADDu = 853,	868	BADDu = 853,
869	BAL = 854,	869	BAL = 854,
870	BALC = 855,	870	BALC = 855,
871	BALC_MMR6 = 856,	871	BALC_MMR6 = 856,
872	BALIGN = 857,	872	BALIGN = 857,
873	BALIGN_MMR2 = 858,	873	BALIGN_MMR2 = 858,
874	BBIT0 = 859,	874	BBIT0 = 859,
875	BBIT032 = 860,	875	BBIT032 = 860,
876	BBIT1 = 861,	876	BBIT1 = 861,
877	BBIT132 = 862,	877	BBIT132 = 862,
878	BC = 863,	878	BC = 863,
879	BC16_MMR6 = 864,	879	BC16_MMR6 = 864,
880	BC1EQZ = 865,	880	BC1EQZ = 865,
881	BC1EQZC_MMR6 = 866,	881	BC1EQZC_MMR6 = 866,
882	BC1F = 867,	882	BC1F = 867,
883	BC1FL = 868,	883	BC1FL = 868,
884	BC1F_MM = 869,	884	BC1F_MM = 869,
885	BC1NEZ = 870,	885	BC1NEZ = 870,
886	BC1NEZC_MMR6 = 871,	886	BC1NEZC_MMR6 = 871,
887	BC1T = 872,	887	BC1T = 872,
888	BC1TL = 873,	888	BC1TL = 873,
889	BC1T_MM = 874,	889	BC1T_MM = 874,
890	BC2EQZ = 875,	890	BC2EQZ = 875,
891	BC2EQZC_MMR6 = 876,	891	BC2EQZC_MMR6 = 876,
892	BC2NEZ = 877,	892	BC2NEZ = 877,
893	BC2NEZC_MMR6 = 878,	893	BC2NEZC_MMR6 = 878,
894	BCLRI_B = 879,	894	BCLRI_B = 879,
895	BCLRI_D = 880,	895	BCLRI_D = 880,
896	BCLRI_H = 881,	896	BCLRI_H = 881,
897	BCLRI_W = 882,	897	BCLRI_W = 882,
898	BCLR_B = 883,	898	BCLR_B = 883,
899	BCLR_D = 884,	899	BCLR_D = 884,
900	BCLR_H = 885,	900	BCLR_H = 885,
901	BCLR_W = 886,	901	BCLR_W = 886,
902	BC_MMR6 = 887,	902	BC_MMR6 = 887,
903	BEQ = 888,	903	BEQ = 888,
904	BEQ64 = 889,	904	BEQ64 = 889,
905	BEQC = 890,	905	BEQC = 890,
906	BEQC64 = 891,	906	BEQC64 = 891,
907	BEQC_MMR6 = 892,	907	BEQC_MMR6 = 892,
908	BEQL = 893,	908	BEQL = 893,
909	BEQZ16_MM = 894,	909	BEQZ16_MM = 894,
910	BEQZALC = 895,	910	BEQZALC = 895,
911	BEQZALC_MMR6 = 896,	911	BEQZALC_MMR6 = 896,
912	BEQZC = 897,	912	BEQZC = 897,
913	BEQZC16_MMR6 = 898,	913	BEQZC16_MMR6 = 898,
914	BEQZC64 = 899,	914	BEQZC64 = 899,
915	BEQZC_MM = 900,	915	BEQZC_MM = 900,
916	BEQZC_MMR6 = 901,	916	BEQZC_MMR6 = 901,
917	BEQ_MM = 902,	917	BEQ_MM = 902,
918	BGEC = 903,	918	BGEC = 903,
919	BGEC64 = 904,	919	BGEC64 = 904,
920	BGEC_MMR6 = 905,	920	BGEC_MMR6 = 905,
921	BGEUC = 906,	921	BGEUC = 906,
922	BGEUC64 = 907,	922	BGEUC64 = 907,
923	BGEUC_MMR6 = 908,	923	BGEUC_MMR6 = 908,
924	BGEZ = 909,	924	BGEZ = 909,
925	BGEZ64 = 910,	925	BGEZ64 = 910,
926	BGEZAL = 911,	926	BGEZAL = 911,
927	BGEZALC = 912,	927	BGEZALC = 912,
928	BGEZALC_MMR6 = 913,	928	BGEZALC_MMR6 = 913,
929	BGEZALL = 914,	929	BGEZALL = 914,
930	BGEZALS_MM = 915,	930	BGEZALS_MM = 915,
931	BGEZAL_MM = 916,	931	BGEZAL_MM = 916,
932	BGEZC = 917,	932	BGEZC = 917,
933	BGEZC64 = 918,	933	BGEZC64 = 918,
934	BGEZC_MMR6 = 919,	934	BGEZC_MMR6 = 919,
935	BGEZL = 920,	935	BGEZL = 920,
936	BGEZ_MM = 921,	936	BGEZ_MM = 921,
937	BGTZ = 922,	937	BGTZ = 922,
938	BGTZ64 = 923,	938	BGTZ64 = 923,
939	BGTZALC = 924,	939	BGTZALC = 924,
940	BGTZALC_MMR6 = 925,	940	BGTZALC_MMR6 = 925,
941	BGTZC = 926,	941	BGTZC = 926,
942	BGTZC64 = 927,	942	BGTZC64 = 927,
943	BGTZC_MMR6 = 928,	943	BGTZC_MMR6 = 928,
944	BGTZL = 929,	944	BGTZL = 929,
945	BGTZ_MM = 930,	945	BGTZ_MM = 930,
946	BINSLI_B = 931,	946	BINSLI_B = 931,
947	BINSLI_D = 932,	947	BINSLI_D = 932,
948	BINSLI_H = 933,	948	BINSLI_H = 933,
949	BINSLI_W = 934,	949	BINSLI_W = 934,
950	BINSL_B = 935,	950	BINSL_B = 935,
951	BINSL_D = 936,	951	BINSL_D = 936,
952	BINSL_H = 937,	952	BINSL_H = 937,
953	BINSL_W = 938,	953	BINSL_W = 938,
954	BINSRI_B = 939,	954	BINSRI_B = 939,
955	BINSRI_D = 940,	955	BINSRI_D = 940,
956	BINSRI_H = 941,	956	BINSRI_H = 941,
957	BINSRI_W = 942,	957	BINSRI_W = 942,
958	BINSR_B = 943,	958	BINSR_B = 943,
959	BINSR_D = 944,	959	BINSR_D = 944,
960	BINSR_H = 945,	960	BINSR_H = 945,
961	BINSR_W = 946,	961	BINSR_W = 946,
962	BITREV = 947,	962	BITREV = 947,
963	BITREV_MM = 948,	963	BITREV_MM = 948,
964	BITSWAP = 949,	964	BITSWAP = 949,
965	BITSWAP_MMR6 = 950,	965	BITSWAP_MMR6 = 950,
966	BLEZ = 951,	966	BLEZ = 951,
967	BLEZ64 = 952,	967	BLEZ64 = 952,
968	BLEZALC = 953,	968	BLEZALC = 953,
969	BLEZALC_MMR6 = 954,	969	BLEZALC_MMR6 = 954,
970	BLEZC = 955,	970	BLEZC = 955,
971	BLEZC64 = 956,	971	BLEZC64 = 956,
972	BLEZC_MMR6 = 957,	972	BLEZC_MMR6 = 957,
973	BLEZL = 958,	973	BLEZL = 958,
974	BLEZ_MM = 959,	974	BLEZ_MM = 959,
975	BLTC = 960,	975	BLTC = 960,
976	BLTC64 = 961,	976	BLTC64 = 961,
977	BLTC_MMR6 = 962,	977	BLTC_MMR6 = 962,
978	BLTUC = 963,	978	BLTUC = 963,
979	BLTUC64 = 964,	979	BLTUC64 = 964,
980	BLTUC_MMR6 = 965,	980	BLTUC_MMR6 = 965,
981	BLTZ = 966,	981	BLTZ = 966,
982	BLTZ64 = 967,	982	BLTZ64 = 967,
983	BLTZAL = 968,	983	BLTZAL = 968,
984	BLTZALC = 969,	984	BLTZALC = 969,
985	BLTZALC_MMR6 = 970,	985	BLTZALC_MMR6 = 970,
986	BLTZALL = 971,	986	BLTZALL = 971,
987	BLTZALS_MM = 972,	987	BLTZALS_MM = 972,
988	BLTZAL_MM = 973,	988	BLTZAL_MM = 973,
989	BLTZC = 974,	989	BLTZC = 974,
990	BLTZC64 = 975,	990	BLTZC64 = 975,
991	BLTZC_MMR6 = 976,	991	BLTZC_MMR6 = 976,
992	BLTZL = 977,	992	BLTZL = 977,
993	BLTZ_MM = 978,	993	BLTZ_MM = 978,
994	BMNZI_B = 979,	994	BMNZI_B = 979,
995	BMNZ_V = 980,	995	BMNZ_V = 980,
996	BMZI_B = 981,	996	BMZI_B = 981,
997	BMZ_V = 982,	997	BMZ_V = 982,
998	BNE = 983,	998	BNE = 983,
999	BNE64 = 984,	999	BNE64 = 984,
1000	BNEC = 985,	1000	BNEC = 985,
1001	BNEC64 = 986,	1001	BNEC64 = 986,
1002	BNEC_MMR6 = 987,	1002	BNEC_MMR6 = 987,
1003	BNEGI_B = 988,	1003	BNEGI_B = 988,
1004	BNEGI_D = 989,	1004	BNEGI_D = 989,
1005	BNEGI_H = 990,	1005	BNEGI_H = 990,
1006	BNEGI_W = 991,	1006	BNEGI_W = 991,
1007	BNEG_B = 992,	1007	BNEG_B = 992,
1008	BNEG_D = 993,	1008	BNEG_D = 993,
1009	BNEG_H = 994,	1009	BNEG_H = 994,
1010	BNEG_W = 995,	1010	BNEG_W = 995,
1011	BNEL = 996,	1011	BNEL = 996,
1012	BNEZ16_MM = 997,	1012	BNEZ16_MM = 997,
1013	BNEZALC = 998,	1013	BNEZALC = 998,
1014	BNEZALC_MMR6 = 999,	1014	BNEZALC_MMR6 = 999,
1015	BNEZC = 1000,	1015	BNEZC = 1000,
1016	BNEZC16_MMR6 = 1001,	1016	BNEZC16_MMR6 = 1001,
1017	BNEZC64 = 1002,	1017	BNEZC64 = 1002,
1018	BNEZC_MM = 1003,	1018	BNEZC_MM = 1003,
1019	BNEZC_MMR6 = 1004,	1019	BNEZC_MMR6 = 1004,
1020	BNE_MM = 1005,	1020	BNE_MM = 1005,
1021	BNVC = 1006,	1021	BNVC = 1006,
1022	BNVC_MMR6 = 1007,	1022	BNVC_MMR6 = 1007,
1023	BNZ_B = 1008,	1023	BNZ_B = 1008,
1024	BNZ_D = 1009,	1024	BNZ_D = 1009,
1025	BNZ_H = 1010,	1025	BNZ_H = 1010,
1026	BNZ_V = 1011,	1026	BNZ_V = 1011,
1027	BNZ_W = 1012,	1027	BNZ_W = 1012,
1028	BOVC = 1013,	1028	BOVC = 1013,
1029	BOVC_MMR6 = 1014,	1029	BOVC_MMR6 = 1014,
1030	BPOSGE32 = 1015,	1030	BPOSGE32 = 1015,
1031	BPOSGE32C_MMR3 = 1016,	1031	BPOSGE32C_MMR3 = 1016,
1032	BPOSGE32_MM = 1017,	1032	BPOSGE32_MM = 1017,
1033	BREAK = 1018,	1033	BREAK = 1018,
1034	BREAK16_MM = 1019,	1034	BREAK16_MM = 1019,
1035	BREAK16_MMR6 = 1020,	1035	BREAK16_MMR6 = 1020,
1036	BREAK_MM = 1021,	1036	BREAK_MM = 1021,
1037	BREAK_MMR6 = 1022,	1037	BREAK_MMR6 = 1022,
1038	BSELI_B = 1023,	1038	BSELI_B = 1023,
1039	BSEL_V = 1024,	1039	BSEL_V = 1024,
1040	BSETI_B = 1025,	1040	BSETI_B = 1025,
1041	BSETI_D = 1026,	1041	BSETI_D = 1026,
1042	BSETI_H = 1027,	1042	BSETI_H = 1027,
1043	BSETI_W = 1028,	1043	BSETI_W = 1028,
1044	BSET_B = 1029,	1044	BSET_B = 1029,
1045	BSET_D = 1030,	1045	BSET_D = 1030,
1046	BSET_H = 1031,	1046	BSET_H = 1031,
1047	BSET_W = 1032,	1047	BSET_W = 1032,
1048	BZ_B = 1033,	1048	BZ_B = 1033,
1049	BZ_D = 1034,	1049	BZ_D = 1034,
1050	BZ_H = 1035,	1050	BZ_H = 1035,
1051	BZ_V = 1036,	1051	BZ_V = 1036,
1052	BZ_W = 1037,	1052	BZ_W = 1037,
1053	BeqzRxImm16 = 1038,	1053	BeqzRxImm16 = 1038,
1054	BeqzRxImmX16 = 1039,	1054	BeqzRxImmX16 = 1039,
1055	Bimm16 = 1040,	1055	Bimm16 = 1040,
1056	BimmX16 = 1041,	1056	BimmX16 = 1041,
1057	BnezRxImm16 = 1042,	1057	BnezRxImm16 = 1042,
1058	BnezRxImmX16 = 1043,	1058	BnezRxImmX16 = 1043,
1059	Break16 = 1044,	1059	Break16 = 1044,
1060	Bteqz16 = 1045,	1060	Bteqz16 = 1045,
1061	BteqzX16 = 1046,	1061	BteqzX16 = 1046,
1062	Btnez16 = 1047,	1062	Btnez16 = 1047,
1063	BtnezX16 = 1048,	1063	BtnezX16 = 1048,
1064	CACHE = 1049,	1064	CACHE = 1049,
1065	CACHEE = 1050,	1065	CACHEE = 1050,
1066	CACHEE_MM = 1051,	1066	CACHEE_MM = 1051,
1067	CACHE_MM = 1052,	1067	CACHE_MM = 1052,
1068	CACHE_MMR6 = 1053,	1068	CACHE_MMR6 = 1053,
1069	CACHE_R6 = 1054,	1069	CACHE_R6 = 1054,
1070	CEIL_L_D64 = 1055,	1070	CEIL_L_D64 = 1055,
1071	CEIL_L_D_MMR6 = 1056,	1071	CEIL_L_D_MMR6 = 1056,
1072	CEIL_L_S = 1057,	1072	CEIL_L_S = 1057,
1073	CEIL_L_S_MMR6 = 1058,	1073	CEIL_L_S_MMR6 = 1058,
1074	CEIL_W_D32 = 1059,	1074	CEIL_W_D32 = 1059,
1075	CEIL_W_D64 = 1060,	1075	CEIL_W_D64 = 1060,
1076	CEIL_W_D_MMR6 = 1061,	1076	CEIL_W_D_MMR6 = 1061,
1077	CEIL_W_MM = 1062,	1077	CEIL_W_MM = 1062,
1078	CEIL_W_S = 1063,	1078	CEIL_W_S = 1063,
1079	CEIL_W_S_MM = 1064,	1079	CEIL_W_S_MM = 1064,
1080	CEIL_W_S_MMR6 = 1065,	1080	CEIL_W_S_MMR6 = 1065,
1081	CEQI_B = 1066,	1081	CEQI_B = 1066,
1082	CEQI_D = 1067,	1082	CEQI_D = 1067,
1083	CEQI_H = 1068,	1083	CEQI_H = 1068,
1084	CEQI_W = 1069,	1084	CEQI_W = 1069,
1085	CEQ_B = 1070,	1085	CEQ_B = 1070,
1086	CEQ_D = 1071,	1086	CEQ_D = 1071,
1087	CEQ_H = 1072,	1087	CEQ_H = 1072,
1088	CEQ_W = 1073,	1088	CEQ_W = 1073,
1089	CFC1 = 1074,	1089	CFC1 = 1074,
1090	CFC1_MM = 1075,	1090	CFC1_MM = 1075,
1091	CFC2_MM = 1076,	1091	CFC2_MM = 1076,
1092	CFCMSA = 1077,	1092	CFCMSA = 1077,
1093	CINS = 1078,	1093	CINS = 1078,
1094	CINS32 = 1079,	1094	CINS32 = 1079,
1095	CINS64_32 = 1080,	1095	CINS64_32 = 1080,
1096	CINS_i32 = 1081,	1096	CINS_i32 = 1081,
1097	CLASS_D = 1082,	1097	CLASS_D = 1082,
1098	CLASS_D_MMR6 = 1083,	1098	CLASS_D_MMR6 = 1083,
1099	CLASS_S = 1084,	1099	CLASS_S = 1084,
1100	CLASS_S_MMR6 = 1085,	1100	CLASS_S_MMR6 = 1085,
1101	CLEI_S_B = 1086,	1101	CLEI_S_B = 1086,
1102	CLEI_S_D = 1087,	1102	CLEI_S_D = 1087,
1103	CLEI_S_H = 1088,	1103	CLEI_S_H = 1088,
1104	CLEI_S_W = 1089,	1104	CLEI_S_W = 1089,
1105	CLEI_U_B = 1090,	1105	CLEI_U_B = 1090,
1106	CLEI_U_D = 1091,	1106	CLEI_U_D = 1091,
1107	CLEI_U_H = 1092,	1107	CLEI_U_H = 1092,
1108	CLEI_U_W = 1093,	1108	CLEI_U_W = 1093,
1109	CLE_S_B = 1094,	1109	CLE_S_B = 1094,
1110	CLE_S_D = 1095,	1110	CLE_S_D = 1095,
1111	CLE_S_H = 1096,	1111	CLE_S_H = 1096,
1112	CLE_S_W = 1097,	1112	CLE_S_W = 1097,
1113	CLE_U_B = 1098,	1113	CLE_U_B = 1098,
1114	CLE_U_D = 1099,	1114	CLE_U_D = 1099,
1115	CLE_U_H = 1100,	1115	CLE_U_H = 1100,
1116	CLE_U_W = 1101,	1116	CLE_U_W = 1101,
1117	CLO = 1102,	1117	CLO = 1102,
1118	CLO_MM = 1103,	1118	CLO_MM = 1103,
1119	CLO_MMR6 = 1104,	1119	CLO_MMR6 = 1104,
1120	CLO_R6 = 1105,	1120	CLO_R6 = 1105,
1121	CLTI_S_B = 1106,	1121	CLTI_S_B = 1106,
1122	CLTI_S_D = 1107,	1122	CLTI_S_D = 1107,
1123	CLTI_S_H = 1108,	1123	CLTI_S_H = 1108,
1124	CLTI_S_W = 1109,	1124	CLTI_S_W = 1109,
1125	CLTI_U_B = 1110,	1125	CLTI_U_B = 1110,
1126	CLTI_U_D = 1111,	1126	CLTI_U_D = 1111,
1127	CLTI_U_H = 1112,	1127	CLTI_U_H = 1112,
1128	CLTI_U_W = 1113,	1128	CLTI_U_W = 1113,
1129	CLT_S_B = 1114,	1129	CLT_S_B = 1114,
1130	CLT_S_D = 1115,	1130	CLT_S_D = 1115,
1131	CLT_S_H = 1116,	1131	CLT_S_H = 1116,
1132	CLT_S_W = 1117,	1132	CLT_S_W = 1117,
1133	CLT_U_B = 1118,	1133	CLT_U_B = 1118,
1134	CLT_U_D = 1119,	1134	CLT_U_D = 1119,
1135	CLT_U_H = 1120,	1135	CLT_U_H = 1120,
1136	CLT_U_W = 1121,	1136	CLT_U_W = 1121,
1137	CLZ = 1122,	1137	CLZ = 1122,
1138	CLZ_MM = 1123,	1138	CLZ_MM = 1123,
1139	CLZ_MMR6 = 1124,	1139	CLZ_MMR6 = 1124,
1140	CLZ_R6 = 1125,	1140	CLZ_R6 = 1125,
1141	CMPGDU_EQ_QB = 1126,	1141	CMPGDU_EQ_QB = 1126,
1142	CMPGDU_EQ_QB_MMR2 = 1127,	1142	CMPGDU_EQ_QB_MMR2 = 1127,
1143	CMPGDU_LE_QB = 1128,	1143	CMPGDU_LE_QB = 1128,
1144	CMPGDU_LE_QB_MMR2 = 1129,	1144	CMPGDU_LE_QB_MMR2 = 1129,
1145	CMPGDU_LT_QB = 1130,	1145	CMPGDU_LT_QB = 1130,
1146	CMPGDU_LT_QB_MMR2 = 1131,	1146	CMPGDU_LT_QB_MMR2 = 1131,
1147	CMPGU_EQ_QB = 1132,	1147	CMPGU_EQ_QB = 1132,
1148	CMPGU_EQ_QB_MM = 1133,	1148	CMPGU_EQ_QB_MM = 1133,
1149	CMPGU_LE_QB = 1134,	1149	CMPGU_LE_QB = 1134,
1150	CMPGU_LE_QB_MM = 1135,	1150	CMPGU_LE_QB_MM = 1135,
1151	CMPGU_LT_QB = 1136,	1151	CMPGU_LT_QB = 1136,
1152	CMPGU_LT_QB_MM = 1137,	1152	CMPGU_LT_QB_MM = 1137,
1153	CMPU_EQ_QB = 1138,	1153	CMPU_EQ_QB = 1138,
1154	CMPU_EQ_QB_MM = 1139,	1154	CMPU_EQ_QB_MM = 1139,
1155	CMPU_LE_QB = 1140,	1155	CMPU_LE_QB = 1140,
1156	CMPU_LE_QB_MM = 1141,	1156	CMPU_LE_QB_MM = 1141,
1157	CMPU_LT_QB = 1142,	1157	CMPU_LT_QB = 1142,
1158	CMPU_LT_QB_MM = 1143,	1158	CMPU_LT_QB_MM = 1143,
1159	CMP_AF_D_MMR6 = 1144,	1159	CMP_AF_D_MMR6 = 1144,
1160	CMP_AF_S_MMR6 = 1145,	1160	CMP_AF_S_MMR6 = 1145,
1161	CMP_EQ_D = 1146,	1161	CMP_EQ_D = 1146,
1162	CMP_EQ_D_MMR6 = 1147,	1162	CMP_EQ_D_MMR6 = 1147,
1163	CMP_EQ_PH = 1148,	1163	CMP_EQ_PH = 1148,
1164	CMP_EQ_PH_MM = 1149,	1164	CMP_EQ_PH_MM = 1149,
1165	CMP_EQ_S = 1150,	1165	CMP_EQ_S = 1150,
1166	CMP_EQ_S_MMR6 = 1151,	1166	CMP_EQ_S_MMR6 = 1151,
1167	CMP_F_D = 1152,	1167	CMP_F_D = 1152,
1168	CMP_F_S = 1153,	1168	CMP_F_S = 1153,
1169	CMP_LE_D = 1154,	1169	CMP_LE_D = 1154,
1170	CMP_LE_D_MMR6 = 1155,	1170	CMP_LE_D_MMR6 = 1155,
1171	CMP_LE_PH = 1156,	1171	CMP_LE_PH = 1156,
1172	CMP_LE_PH_MM = 1157,	1172	CMP_LE_PH_MM = 1157,
1173	CMP_LE_S = 1158,	1173	CMP_LE_S = 1158,
1174	CMP_LE_S_MMR6 = 1159,	1174	CMP_LE_S_MMR6 = 1159,
1175	CMP_LT_D = 1160,	1175	CMP_LT_D = 1160,
1176	CMP_LT_D_MMR6 = 1161,	1176	CMP_LT_D_MMR6 = 1161,
1177	CMP_LT_PH = 1162,	1177	CMP_LT_PH = 1162,
1178	CMP_LT_PH_MM = 1163,	1178	CMP_LT_PH_MM = 1163,
1179	CMP_LT_S = 1164,	1179	CMP_LT_S = 1164,
1180	CMP_LT_S_MMR6 = 1165,	1180	CMP_LT_S_MMR6 = 1165,
1181	CMP_SAF_D = 1166,	1181	CMP_SAF_D = 1166,
1182	CMP_SAF_D_MMR6 = 1167,	1182	CMP_SAF_D_MMR6 = 1167,
1183	CMP_SAF_S = 1168,	1183	CMP_SAF_S = 1168,
1184	CMP_SAF_S_MMR6 = 1169,	1184	CMP_SAF_S_MMR6 = 1169,
1185	CMP_SEQ_D = 1170,	1185	CMP_SEQ_D = 1170,
1186	CMP_SEQ_D_MMR6 = 1171,	1186	CMP_SEQ_D_MMR6 = 1171,
1187	CMP_SEQ_S = 1172,	1187	CMP_SEQ_S = 1172,
1188	CMP_SEQ_S_MMR6 = 1173,	1188	CMP_SEQ_S_MMR6 = 1173,
1189	CMP_SLE_D = 1174,	1189	CMP_SLE_D = 1174,
1190	CMP_SLE_D_MMR6 = 1175,	1190	CMP_SLE_D_MMR6 = 1175,
1191	CMP_SLE_S = 1176,	1191	CMP_SLE_S = 1176,
1192	CMP_SLE_S_MMR6 = 1177,	1192	CMP_SLE_S_MMR6 = 1177,
1193	CMP_SLT_D = 1178,	1193	CMP_SLT_D = 1178,
1194	CMP_SLT_D_MMR6 = 1179,	1194	CMP_SLT_D_MMR6 = 1179,
1195	CMP_SLT_S = 1180,	1195	CMP_SLT_S = 1180,
1196	CMP_SLT_S_MMR6 = 1181,	1196	CMP_SLT_S_MMR6 = 1181,
1197	CMP_SUEQ_D = 1182,	1197	CMP_SUEQ_D = 1182,
1198	CMP_SUEQ_D_MMR6 = 1183,	1198	CMP_SUEQ_D_MMR6 = 1183,
1199	CMP_SUEQ_S = 1184,	1199	CMP_SUEQ_S = 1184,
1200	CMP_SUEQ_S_MMR6 = 1185,	1200	CMP_SUEQ_S_MMR6 = 1185,
1201	CMP_SULE_D = 1186,	1201	CMP_SULE_D = 1186,
1202	CMP_SULE_D_MMR6 = 1187,	1202	CMP_SULE_D_MMR6 = 1187,
1203	CMP_SULE_S = 1188,	1203	CMP_SULE_S = 1188,
1204	CMP_SULE_S_MMR6 = 1189,	1204	CMP_SULE_S_MMR6 = 1189,
1205	CMP_SULT_D = 1190,	1205	CMP_SULT_D = 1190,
1206	CMP_SULT_D_MMR6 = 1191,	1206	CMP_SULT_D_MMR6 = 1191,
1207	CMP_SULT_S = 1192,	1207	CMP_SULT_S = 1192,
1208	CMP_SULT_S_MMR6 = 1193,	1208	CMP_SULT_S_MMR6 = 1193,
1209	CMP_SUN_D = 1194,	1209	CMP_SUN_D = 1194,
1210	CMP_SUN_D_MMR6 = 1195,	1210	CMP_SUN_D_MMR6 = 1195,
1211	CMP_SUN_S = 1196,	1211	CMP_SUN_S = 1196,
1212	CMP_SUN_S_MMR6 = 1197,	1212	CMP_SUN_S_MMR6 = 1197,
1213	CMP_UEQ_D = 1198,	1213	CMP_UEQ_D = 1198,
1214	CMP_UEQ_D_MMR6 = 1199,	1214	CMP_UEQ_D_MMR6 = 1199,
1215	CMP_UEQ_S = 1200,	1215	CMP_UEQ_S = 1200,
1216	CMP_UEQ_S_MMR6 = 1201,	1216	CMP_UEQ_S_MMR6 = 1201,
1217	CMP_ULE_D = 1202,	1217	CMP_ULE_D = 1202,
1218	CMP_ULE_D_MMR6 = 1203,	1218	CMP_ULE_D_MMR6 = 1203,
1219	CMP_ULE_S = 1204,	1219	CMP_ULE_S = 1204,
1220	CMP_ULE_S_MMR6 = 1205,	1220	CMP_ULE_S_MMR6 = 1205,
1221	CMP_ULT_D = 1206,	1221	CMP_ULT_D = 1206,
1222	CMP_ULT_D_MMR6 = 1207,	1222	CMP_ULT_D_MMR6 = 1207,
1223	CMP_ULT_S = 1208,	1223	CMP_ULT_S = 1208,
1224	CMP_ULT_S_MMR6 = 1209,	1224	CMP_ULT_S_MMR6 = 1209,
1225	CMP_UN_D = 1210,	1225	CMP_UN_D = 1210,
1226	CMP_UN_D_MMR6 = 1211,	1226	CMP_UN_D_MMR6 = 1211,
1227	CMP_UN_S = 1212,	1227	CMP_UN_S = 1212,
1228	CMP_UN_S_MMR6 = 1213,	1228	CMP_UN_S_MMR6 = 1213,
1229	COPY_S_B = 1214,	1229	COPY_S_B = 1214,
1230	COPY_S_D = 1215,	1230	COPY_S_D = 1215,
1231	COPY_S_H = 1216,	1231	COPY_S_H = 1216,
1232	COPY_S_W = 1217,	1232	COPY_S_W = 1217,
1233	COPY_U_B = 1218,	1233	COPY_U_B = 1218,
1234	COPY_U_H = 1219,	1234	COPY_U_H = 1219,
1235	COPY_U_W = 1220,	1235	COPY_U_W = 1220,
1236	CRC32B = 1221,	1236	CRC32B = 1221,
1237	CRC32CB = 1222,	1237	CRC32CB = 1222,
1238	CRC32CD = 1223,	1238	CRC32CD = 1223,
1239	CRC32CH = 1224,	1239	CRC32CH = 1224,
1240	CRC32CW = 1225,	1240	CRC32CW = 1225,
1241	CRC32D = 1226,	1241	CRC32D = 1226,
1242	CRC32H = 1227,	1242	CRC32H = 1227,
1243	CRC32W = 1228,	1243	CRC32W = 1228,
1244	CTC1 = 1229,	1244	CTC1 = 1229,
1245	CTC1_MM = 1230,	1245	CTC1_MM = 1230,
1246	CTC2_MM = 1231,	1246	CTC2_MM = 1231,
1247	CTCMSA = 1232,	1247	CTCMSA = 1232,
1248	CVT_D32_S = 1233,	1248	CVT_D32_S = 1233,
1249	CVT_D32_S_MM = 1234,	1249	CVT_D32_S_MM = 1234,
1250	CVT_D32_W = 1235,	1250	CVT_D32_W = 1235,
1251	CVT_D32_W_MM = 1236,	1251	CVT_D32_W_MM = 1236,
1252	CVT_D64_L = 1237,	1252	CVT_D64_L = 1237,
1253	CVT_D64_S = 1238,	1253	CVT_D64_S = 1238,
1254	CVT_D64_S_MM = 1239,	1254	CVT_D64_S_MM = 1239,
1255	CVT_D64_W = 1240,	1255	CVT_D64_W = 1240,
1256	CVT_D64_W_MM = 1241,	1256	CVT_D64_W_MM = 1241,
1257	CVT_D_L_MMR6 = 1242,	1257	CVT_D_L_MMR6 = 1242,
1258	CVT_L_D64 = 1243,	1258	CVT_L_D64 = 1243,
1259	CVT_L_D64_MM = 1244,	1259	CVT_L_D64_MM = 1244,
1260	CVT_L_D_MMR6 = 1245,	1260	CVT_L_D_MMR6 = 1245,
1261	CVT_L_S = 1246,	1261	CVT_L_S = 1246,
1262	CVT_L_S_MM = 1247,	1262	CVT_L_S_MM = 1247,
1263	CVT_L_S_MMR6 = 1248,	1263	CVT_L_S_MMR6 = 1248,
1264	CVT_PS_PW64 = 1249,	1264	CVT_PS_PW64 = 1249,
1265	CVT_PS_S64 = 1250,	1265	CVT_PS_S64 = 1250,
1266	CVT_PW_PS64 = 1251,	1266	CVT_PW_PS64 = 1251,
1267	CVT_S_D32 = 1252,	1267	CVT_S_D32 = 1252,
1268	CVT_S_D32_MM = 1253,	1268	CVT_S_D32_MM = 1253,
1269	CVT_S_D64 = 1254,	1269	CVT_S_D64 = 1254,
1270	CVT_S_D64_MM = 1255,	1270	CVT_S_D64_MM = 1255,
1271	CVT_S_L = 1256,	1271	CVT_S_L = 1256,
1272	CVT_S_L_MMR6 = 1257,	1272	CVT_S_L_MMR6 = 1257,
1273	CVT_S_PL64 = 1258,	1273	CVT_S_PL64 = 1258,
1274	CVT_S_PU64 = 1259,	1274	CVT_S_PU64 = 1259,
1275	CVT_S_W = 1260,	1275	CVT_S_W = 1260,
1276	CVT_S_W_MM = 1261,	1276	CVT_S_W_MM = 1261,
1277	CVT_S_W_MMR6 = 1262,	1277	CVT_S_W_MMR6 = 1262,
1278	CVT_W_D32 = 1263,	1278	CVT_W_D32 = 1263,
1279	CVT_W_D32_MM = 1264,	1279	CVT_W_D32_MM = 1264,
1280	CVT_W_D64 = 1265,	1280	CVT_W_D64 = 1265,
1281	CVT_W_D64_MM = 1266,	1281	CVT_W_D64_MM = 1266,
1282	CVT_W_S = 1267,	1282	CVT_W_S = 1267,
1283	CVT_W_S_MM = 1268,	1283	CVT_W_S_MM = 1268,
1284	CVT_W_S_MMR6 = 1269,	1284	CVT_W_S_MMR6 = 1269,
1285	C_EQ_D32 = 1270,	1285	C_EQ_D32 = 1270,
1286	C_EQ_D32_MM = 1271,	1286	C_EQ_D32_MM = 1271,
1287	C_EQ_D64 = 1272,	1287	C_EQ_D64 = 1272,
1288	C_EQ_D64_MM = 1273,	1288	C_EQ_D64_MM = 1273,
1289	C_EQ_S = 1274,	1289	C_EQ_S = 1274,
1290	C_EQ_S_MM = 1275,	1290	C_EQ_S_MM = 1275,
1291	C_F_D32 = 1276,	1291	C_F_D32 = 1276,
1292	C_F_D32_MM = 1277,	1292	C_F_D32_MM = 1277,
1293	C_F_D64 = 1278,	1293	C_F_D64 = 1278,
1294	C_F_D64_MM = 1279,	1294	C_F_D64_MM = 1279,
1295	C_F_S = 1280,	1295	C_F_S = 1280,
1296	C_F_S_MM = 1281,	1296	C_F_S_MM = 1281,
1297	C_LE_D32 = 1282,	1297	C_LE_D32 = 1282,
1298	C_LE_D32_MM = 1283,	1298	C_LE_D32_MM = 1283,
1299	C_LE_D64 = 1284,	1299	C_LE_D64 = 1284,
1300	C_LE_D64_MM = 1285,	1300	C_LE_D64_MM = 1285,
1301	C_LE_S = 1286,	1301	C_LE_S = 1286,
1302	C_LE_S_MM = 1287,	1302	C_LE_S_MM = 1287,
1303	C_LT_D32 = 1288,	1303	C_LT_D32 = 1288,
1304	C_LT_D32_MM = 1289,	1304	C_LT_D32_MM = 1289,
1305	C_LT_D64 = 1290,	1305	C_LT_D64 = 1290,
1306	C_LT_D64_MM = 1291,	1306	C_LT_D64_MM = 1291,
1307	C_LT_S = 1292,	1307	C_LT_S = 1292,
1308	C_LT_S_MM = 1293,	1308	C_LT_S_MM = 1293,
1309	C_NGE_D32 = 1294,	1309	C_NGE_D32 = 1294,
1310	C_NGE_D32_MM = 1295,	1310	C_NGE_D32_MM = 1295,
1311	C_NGE_D64 = 1296,	1311	C_NGE_D64 = 1296,
1312	C_NGE_D64_MM = 1297,	1312	C_NGE_D64_MM = 1297,
1313	C_NGE_S = 1298,	1313	C_NGE_S = 1298,
1314	C_NGE_S_MM = 1299,	1314	C_NGE_S_MM = 1299,
1315	C_NGLE_D32 = 1300,	1315	C_NGLE_D32 = 1300,
1316	C_NGLE_D32_MM = 1301,	1316	C_NGLE_D32_MM = 1301,
1317	C_NGLE_D64 = 1302,	1317	C_NGLE_D64 = 1302,
1318	C_NGLE_D64_MM = 1303,	1318	C_NGLE_D64_MM = 1303,
1319	C_NGLE_S = 1304,	1319	C_NGLE_S = 1304,
1320	C_NGLE_S_MM = 1305,	1320	C_NGLE_S_MM = 1305,
1321	C_NGL_D32 = 1306,	1321	C_NGL_D32 = 1306,
1322	C_NGL_D32_MM = 1307,	1322	C_NGL_D32_MM = 1307,
1323	C_NGL_D64 = 1308,	1323	C_NGL_D64 = 1308,
1324	C_NGL_D64_MM = 1309,	1324	C_NGL_D64_MM = 1309,
1325	C_NGL_S = 1310,	1325	C_NGL_S = 1310,
1326	C_NGL_S_MM = 1311,	1326	C_NGL_S_MM = 1311,
1327	C_NGT_D32 = 1312,	1327	C_NGT_D32 = 1312,
1328	C_NGT_D32_MM = 1313,	1328	C_NGT_D32_MM = 1313,
1329	C_NGT_D64 = 1314,	1329	C_NGT_D64 = 1314,
1330	C_NGT_D64_MM = 1315,	1330	C_NGT_D64_MM = 1315,
1331	C_NGT_S = 1316,	1331	C_NGT_S = 1316,
1332	C_NGT_S_MM = 1317,	1332	C_NGT_S_MM = 1317,
1333	C_OLE_D32 = 1318,	1333	C_OLE_D32 = 1318,
1334	C_OLE_D32_MM = 1319,	1334	C_OLE_D32_MM = 1319,
1335	C_OLE_D64 = 1320,	1335	C_OLE_D64 = 1320,
1336	C_OLE_D64_MM = 1321,	1336	C_OLE_D64_MM = 1321,
1337	C_OLE_S = 1322,	1337	C_OLE_S = 1322,
1338	C_OLE_S_MM = 1323,	1338	C_OLE_S_MM = 1323,
1339	C_OLT_D32 = 1324,	1339	C_OLT_D32 = 1324,
1340	C_OLT_D32_MM = 1325,	1340	C_OLT_D32_MM = 1325,
1341	C_OLT_D64 = 1326,	1341	C_OLT_D64 = 1326,
1342	C_OLT_D64_MM = 1327,	1342	C_OLT_D64_MM = 1327,
1343	C_OLT_S = 1328,	1343	C_OLT_S = 1328,
1344	C_OLT_S_MM = 1329,	1344	C_OLT_S_MM = 1329,
1345	C_SEQ_D32 = 1330,	1345	C_SEQ_D32 = 1330,
1346	C_SEQ_D32_MM = 1331,	1346	C_SEQ_D32_MM = 1331,
1347	C_SEQ_D64 = 1332,	1347	C_SEQ_D64 = 1332,
1348	C_SEQ_D64_MM = 1333,	1348	C_SEQ_D64_MM = 1333,
1349	C_SEQ_S = 1334,	1349	C_SEQ_S = 1334,
1350	C_SEQ_S_MM = 1335,	1350	C_SEQ_S_MM = 1335,
1351	C_SF_D32 = 1336,	1351	C_SF_D32 = 1336,
1352	C_SF_D32_MM = 1337,	1352	C_SF_D32_MM = 1337,
1353	C_SF_D64 = 1338,	1353	C_SF_D64 = 1338,
1354	C_SF_D64_MM = 1339,	1354	C_SF_D64_MM = 1339,
1355	C_SF_S = 1340,	1355	C_SF_S = 1340,
1356	C_SF_S_MM = 1341,	1356	C_SF_S_MM = 1341,
1357	C_UEQ_D32 = 1342,	1357	C_UEQ_D32 = 1342,
1358	C_UEQ_D32_MM = 1343,	1358	C_UEQ_D32_MM = 1343,
1359	C_UEQ_D64 = 1344,	1359	C_UEQ_D64 = 1344,
1360	C_UEQ_D64_MM = 1345,	1360	C_UEQ_D64_MM = 1345,
1361	C_UEQ_S = 1346,	1361	C_UEQ_S = 1346,
1362	C_UEQ_S_MM = 1347,	1362	C_UEQ_S_MM = 1347,
1363	C_ULE_D32 = 1348,	1363	C_ULE_D32 = 1348,
1364	C_ULE_D32_MM = 1349,	1364	C_ULE_D32_MM = 1349,
1365	C_ULE_D64 = 1350,	1365	C_ULE_D64 = 1350,
1366	C_ULE_D64_MM = 1351,	1366	C_ULE_D64_MM = 1351,
1367	C_ULE_S = 1352,	1367	C_ULE_S = 1352,
1368	C_ULE_S_MM = 1353,	1368	C_ULE_S_MM = 1353,
1369	C_ULT_D32 = 1354,	1369	C_ULT_D32 = 1354,
1370	C_ULT_D32_MM = 1355,	1370	C_ULT_D32_MM = 1355,
1371	C_ULT_D64 = 1356,	1371	C_ULT_D64 = 1356,
1372	C_ULT_D64_MM = 1357,	1372	C_ULT_D64_MM = 1357,
1373	C_ULT_S = 1358,	1373	C_ULT_S = 1358,
1374	C_ULT_S_MM = 1359,	1374	C_ULT_S_MM = 1359,
1375	C_UN_D32 = 1360,	1375	C_UN_D32 = 1360,
1376	C_UN_D32_MM = 1361,	1376	C_UN_D32_MM = 1361,
1377	C_UN_D64 = 1362,	1377	C_UN_D64 = 1362,
1378	C_UN_D64_MM = 1363,	1378	C_UN_D64_MM = 1363,
1379	C_UN_S = 1364,	1379	C_UN_S = 1364,
1380	C_UN_S_MM = 1365,	1380	C_UN_S_MM = 1365,
1381	CmpRxRy16 = 1366,	1381	CmpRxRy16 = 1366,
1382	CmpiRxImm16 = 1367,	1382	CmpiRxImm16 = 1367,
1383	CmpiRxImmX16 = 1368,	1383	CmpiRxImmX16 = 1368,
1384	DADD = 1369,	1384	DADD = 1369,
1385	DADDi = 1370,	1385	DADDi = 1370,
1386	DADDiu = 1371,	1386	DADDiu = 1371,
1387	DADDu = 1372,	1387	DADDu = 1372,
1388	DAHI = 1373,	1388	DAHI = 1373,
1389	DALIGN = 1374,	1389	DALIGN = 1374,
1390	DATI = 1375,	1390	DATI = 1375,
1391	DAUI = 1376,	1391	DAUI = 1376,
1392	DBITSWAP = 1377,	1392	DBITSWAP = 1377,
1393	DCLO = 1378,	1393	DCLO = 1378,
1394	DCLO_R6 = 1379,	1394	DCLO_R6 = 1379,
1395	DCLZ = 1380,	1395	DCLZ = 1380,
1396	DCLZ_R6 = 1381,	1396	DCLZ_R6 = 1381,
1397	DDIV = 1382,	1397	DDIV = 1382,
1398	DDIVU = 1383,	1398	DDIVU = 1383,
1399	DERET = 1384,	1399	DERET = 1384,
1400	DERET_MM = 1385,	1400	DERET_MM = 1385,
1401	DERET_MMR6 = 1386,	1401	DERET_MMR6 = 1386,
1402	DEXT = 1387,	1402	DEXT = 1387,
1403	DEXT64_32 = 1388,	1403	DEXT64_32 = 1388,
1404	DEXTM = 1389,	1404	DEXTM = 1389,
1405	DEXTU = 1390,	1405	DEXTU = 1390,
1406	DI = 1391,	1406	DI = 1391,
1407	DINS = 1392,	1407	DINS = 1392,
1408	DINSM = 1393,	1408	DINSM = 1393,
1409	DINSU = 1394,	1409	DINSU = 1394,
1410	DIV = 1395,	1410	DIV = 1395,
1411	DIVU = 1396,	1411	DIVU = 1396,
1412	DIVU_MMR6 = 1397,	1412	DIVU_MMR6 = 1397,
1413	DIV_MMR6 = 1398,	1413	DIV_MMR6 = 1398,
1414	DIV_S_B = 1399,	1414	DIV_S_B = 1399,
1415	DIV_S_D = 1400,	1415	DIV_S_D = 1400,
1416	DIV_S_H = 1401,	1416	DIV_S_H = 1401,
1417	DIV_S_W = 1402,	1417	DIV_S_W = 1402,
1418	DIV_U_B = 1403,	1418	DIV_U_B = 1403,
1419	DIV_U_D = 1404,	1419	DIV_U_D = 1404,
1420	DIV_U_H = 1405,	1420	DIV_U_H = 1405,
1421	DIV_U_W = 1406,	1421	DIV_U_W = 1406,
1422	DI_MM = 1407,	1422	DI_MM = 1407,
1423	DI_MMR6 = 1408,	1423	DI_MMR6 = 1408,
1424	DLSA = 1409,	1424	DLSA = 1409,
1425	DLSA_R6 = 1410,	1425	DLSA_R6 = 1410,
1426	DMFC0 = 1411,	1426	DMFC0 = 1411,
1427	DMFC1 = 1412,	1427	DMFC1 = 1412,
1428	DMFC2 = 1413,	1428	DMFC2 = 1413,
1429	DMFC2_OCTEON = 1414,	1429	DMFC2_OCTEON = 1414,
1430	DMFGC0 = 1415,	1430	DMFGC0 = 1415,
1431	DMOD = 1416,	1431	DMOD = 1416,
1432	DMODU = 1417,	1432	DMODU = 1417,
1433	DMT = 1418,	1433	DMT = 1418,
1434	DMTC0 = 1419,	1434	DMTC0 = 1419,
1435	DMTC1 = 1420,	1435	DMTC1 = 1420,
1436	DMTC2 = 1421,	1436	DMTC2 = 1421,
1437	DMTC2_OCTEON = 1422,	1437	DMTC2_OCTEON = 1422,
1438	DMTGC0 = 1423,	1438	DMTGC0 = 1423,
1439	DMUH = 1424,	1439	DMUH = 1424,
1440	DMUHU = 1425,	1440	DMUHU = 1425,
1441	DMUL = 1426,	1441	DMUL = 1426,
1442	DMULT = 1427,	1442	DMULT = 1427,
1443	DMULTu = 1428,	1443	DMULTu = 1428,
1444	DMULU = 1429,	1444	DMULU = 1429,
1445	DMUL_R6 = 1430,	1445	DMUL_R6 = 1430,
1446	DOTP_S_D = 1431,	1446	DOTP_S_D = 1431,
1447	DOTP_S_H = 1432,	1447	DOTP_S_H = 1432,
1448	DOTP_S_W = 1433,	1448	DOTP_S_W = 1433,
1449	DOTP_U_D = 1434,	1449	DOTP_U_D = 1434,
1450	DOTP_U_H = 1435,	1450	DOTP_U_H = 1435,
1451	DOTP_U_W = 1436,	1451	DOTP_U_W = 1436,
1452	DPADD_S_D = 1437,	1452	DPADD_S_D = 1437,
1453	DPADD_S_H = 1438,	1453	DPADD_S_H = 1438,
1454	DPADD_S_W = 1439,	1454	DPADD_S_W = 1439,
1455	DPADD_U_D = 1440,	1455	DPADD_U_D = 1440,
1456	DPADD_U_H = 1441,	1456	DPADD_U_H = 1441,
1457	DPADD_U_W = 1442,	1457	DPADD_U_W = 1442,
1458	DPAQX_SA_W_PH = 1443,	1458	DPAQX_SA_W_PH = 1443,
1459	DPAQX_SA_W_PH_MMR2 = 1444,	1459	DPAQX_SA_W_PH_MMR2 = 1444,
1460	DPAQX_S_W_PH = 1445,	1460	DPAQX_S_W_PH = 1445,
1461	DPAQX_S_W_PH_MMR2 = 1446,	1461	DPAQX_S_W_PH_MMR2 = 1446,
1462	DPAQ_SA_L_W = 1447,	1462	DPAQ_SA_L_W = 1447,
1463	DPAQ_SA_L_W_MM = 1448,	1463	DPAQ_SA_L_W_MM = 1448,
1464	DPAQ_S_W_PH = 1449,	1464	DPAQ_S_W_PH = 1449,
1465	DPAQ_S_W_PH_MM = 1450,	1465	DPAQ_S_W_PH_MM = 1450,
1466	DPAU_H_QBL = 1451,	1466	DPAU_H_QBL = 1451,
1467	DPAU_H_QBL_MM = 1452,	1467	DPAU_H_QBL_MM = 1452,
1468	DPAU_H_QBR = 1453,	1468	DPAU_H_QBR = 1453,
1469	DPAU_H_QBR_MM = 1454,	1469	DPAU_H_QBR_MM = 1454,
1470	DPAX_W_PH = 1455,	1470	DPAX_W_PH = 1455,
1471	DPAX_W_PH_MMR2 = 1456,	1471	DPAX_W_PH_MMR2 = 1456,
1472	DPA_W_PH = 1457,	1472	DPA_W_PH = 1457,
1473	DPA_W_PH_MMR2 = 1458,	1473	DPA_W_PH_MMR2 = 1458,
1474	DPOP = 1459,	1474	DPOP = 1459,
1475	DPSQX_SA_W_PH = 1460,	1475	DPSQX_SA_W_PH = 1460,
1476	DPSQX_SA_W_PH_MMR2 = 1461,	1476	DPSQX_SA_W_PH_MMR2 = 1461,
1477	DPSQX_S_W_PH = 1462,	1477	DPSQX_S_W_PH = 1462,
1478	DPSQX_S_W_PH_MMR2 = 1463,	1478	DPSQX_S_W_PH_MMR2 = 1463,
1479	DPSQ_SA_L_W = 1464,	1479	DPSQ_SA_L_W = 1464,
1480	DPSQ_SA_L_W_MM = 1465,	1480	DPSQ_SA_L_W_MM = 1465,
1481	DPSQ_S_W_PH = 1466,	1481	DPSQ_S_W_PH = 1466,
1482	DPSQ_S_W_PH_MM = 1467,	1482	DPSQ_S_W_PH_MM = 1467,
1483	DPSUB_S_D = 1468,	1483	DPSUB_S_D = 1468,
1484	DPSUB_S_H = 1469,	1484	DPSUB_S_H = 1469,
1485	DPSUB_S_W = 1470,	1485	DPSUB_S_W = 1470,
1486	DPSUB_U_D = 1471,	1486	DPSUB_U_D = 1471,
1487	DPSUB_U_H = 1472,	1487	DPSUB_U_H = 1472,
1488	DPSUB_U_W = 1473,	1488	DPSUB_U_W = 1473,
1489	DPSU_H_QBL = 1474,	1489	DPSU_H_QBL = 1474,
1490	DPSU_H_QBL_MM = 1475,	1490	DPSU_H_QBL_MM = 1475,
1491	DPSU_H_QBR = 1476,	1491	DPSU_H_QBR = 1476,
1492	DPSU_H_QBR_MM = 1477,	1492	DPSU_H_QBR_MM = 1477,
1493	DPSX_W_PH = 1478,	1493	DPSX_W_PH = 1478,
1494	DPSX_W_PH_MMR2 = 1479,	1494	DPSX_W_PH_MMR2 = 1479,
1495	DPS_W_PH = 1480,	1495	DPS_W_PH = 1480,
1496	DPS_W_PH_MMR2 = 1481,	1496	DPS_W_PH_MMR2 = 1481,
1497	DROTR = 1482,	1497	DROTR = 1482,
1498	DROTR32 = 1483,	1498	DROTR32 = 1483,
1499	DROTRV = 1484,	1499	DROTRV = 1484,
1500	DSBH = 1485,	1500	DSBH = 1485,
1501	DSDIV = 1486,	1501	DSDIV = 1486,
1502	DSHD = 1487,	1502	DSHD = 1487,
1503	DSLL = 1488,	1503	DSLL = 1488,
1504	DSLL32 = 1489,	1504	DSLL32 = 1489,
1505	DSLL64_32 = 1490,	1505	DSLL64_32 = 1490,
1506	DSLLV = 1491,	1506	DSLLV = 1491,
1507	DSRA = 1492,	1507	DSRA = 1492,
1508	DSRA32 = 1493,	1508	DSRA32 = 1493,
1509	DSRAV = 1494,	1509	DSRAV = 1494,
1510	DSRL = 1495,	1510	DSRL = 1495,
1511	DSRL32 = 1496,	1511	DSRL32 = 1496,
1512	DSRLV = 1497,	1512	DSRLV = 1497,
1513	DSUB = 1498,	1513	DSUB = 1498,
1514	DSUBu = 1499,	1514	DSUBu = 1499,
1515	DUDIV = 1500,	1515	DUDIV = 1500,
1516	DVP = 1501,	1516	DVP = 1501,
1517	DVPE = 1502,	1517	DVPE = 1502,
1518	DVP_MMR6 = 1503,	1518	DVP_MMR6 = 1503,
1519	DivRxRy16 = 1504,	1519	DivRxRy16 = 1504,
1520	DivuRxRy16 = 1505,	1520	DivuRxRy16 = 1505,
1521	EHB = 1506,	1521	EHB = 1506,
1522	EHB_MM = 1507,	1522	EHB_MM = 1507,
1523	EHB_MMR6 = 1508,	1523	EHB_MMR6 = 1508,
1524	EI = 1509,	1524	EI = 1509,
1525	EI_MM = 1510,	1525	EI_MM = 1510,
1526	EI_MMR6 = 1511,	1526	EI_MMR6 = 1511,
1527	EMT = 1512,	1527	EMT = 1512,
1528	ERET = 1513,	1528	ERET = 1513,
1529	ERETNC = 1514,	1529	ERETNC = 1514,
1530	ERETNC_MMR6 = 1515,	1530	ERETNC_MMR6 = 1515,
1531	ERET_MM = 1516,	1531	ERET_MM = 1516,
1532	ERET_MMR6 = 1517,	1532	ERET_MMR6 = 1517,
1533	EVP = 1518,	1533	EVP = 1518,
1534	EVPE = 1519,	1534	EVPE = 1519,
1535	EVP_MMR6 = 1520,	1535	EVP_MMR6 = 1520,
1536	EXT = 1521,	1536	EXT = 1521,
1537	EXTP = 1522,	1537	EXTP = 1522,
1538	EXTPDP = 1523,	1538	EXTPDP = 1523,
1539	EXTPDPV = 1524,	1539	EXTPDPV = 1524,
1540	EXTPDPV_MM = 1525,	1540	EXTPDPV_MM = 1525,
1541	EXTPDP_MM = 1526,	1541	EXTPDP_MM = 1526,
1542	EXTPV = 1527,	1542	EXTPV = 1527,
1543	EXTPV_MM = 1528,	1543	EXTPV_MM = 1528,
1544	EXTP_MM = 1529,	1544	EXTP_MM = 1529,
1545	EXTRV_RS_W = 1530,	1545	EXTRV_RS_W = 1530,
1546	EXTRV_RS_W_MM = 1531,	1546	EXTRV_RS_W_MM = 1531,
1547	EXTRV_R_W = 1532,	1547	EXTRV_R_W = 1532,
1548	EXTRV_R_W_MM = 1533,	1548	EXTRV_R_W_MM = 1533,
1549	EXTRV_S_H = 1534,	1549	EXTRV_S_H = 1534,
1550	EXTRV_S_H_MM = 1535,	1550	EXTRV_S_H_MM = 1535,
1551	EXTRV_W = 1536,	1551	EXTRV_W = 1536,
1552	EXTRV_W_MM = 1537,	1552	EXTRV_W_MM = 1537,
1553	EXTR_RS_W = 1538,	1553	EXTR_RS_W = 1538,
1554	EXTR_RS_W_MM = 1539,	1554	EXTR_RS_W_MM = 1539,
1555	EXTR_R_W = 1540,	1555	EXTR_R_W = 1540,
1556	EXTR_R_W_MM = 1541,	1556	EXTR_R_W_MM = 1541,
1557	EXTR_S_H = 1542,	1557	EXTR_S_H = 1542,
1558	EXTR_S_H_MM = 1543,	1558	EXTR_S_H_MM = 1543,
1559	EXTR_W = 1544,	1559	EXTR_W = 1544,
1560	EXTR_W_MM = 1545,	1560	EXTR_W_MM = 1545,
1561	EXTS = 1546,	1561	EXTS = 1546,
1562	EXTS32 = 1547,	1562	EXTS32 = 1547,
1563	EXT_MM = 1548,	1563	EXT_MM = 1548,
1564	EXT_MMR6 = 1549,	1564	EXT_MMR6 = 1549,
1565	FABS_D32 = 1550,	1565	FABS_D32 = 1550,
1566	FABS_D32_MM = 1551,	1566	FABS_D32_MM = 1551,
1567	FABS_D64 = 1552,	1567	FABS_D64 = 1552,
1568	FABS_D64_MM = 1553,	1568	FABS_D64_MM = 1553,
1569	FABS_S = 1554,	1569	FABS_S = 1554,
1570	FABS_S_MM = 1555,	1570	FABS_S_MM = 1555,
1571	FADD_D = 1556,	1571	FADD_D = 1556,
1572	FADD_D32 = 1557,	1572	FADD_D32 = 1557,
1573	FADD_D32_MM = 1558,	1573	FADD_D32_MM = 1558,
1574	FADD_D64 = 1559,	1574	FADD_D64 = 1559,
1575	FADD_D64_MM = 1560,	1575	FADD_D64_MM = 1560,
1576	FADD_PS64 = 1561,	1576	FADD_PS64 = 1561,
1577	FADD_S = 1562,	1577	FADD_S = 1562,
1578	FADD_S_MM = 1563,	1578	FADD_S_MM = 1563,
1579	FADD_S_MMR6 = 1564,	1579	FADD_S_MMR6 = 1564,
1580	FADD_W = 1565,	1580	FADD_W = 1565,
1581	FCAF_D = 1566,	1581	FCAF_D = 1566,
1582	FCAF_W = 1567,	1582	FCAF_W = 1567,
1583	FCEQ_D = 1568,	1583	FCEQ_D = 1568,
1584	FCEQ_W = 1569,	1584	FCEQ_W = 1569,
1585	FCLASS_D = 1570,	1585	FCLASS_D = 1570,
1586	FCLASS_W = 1571,	1586	FCLASS_W = 1571,
1587	FCLE_D = 1572,	1587	FCLE_D = 1572,
1588	FCLE_W = 1573,	1588	FCLE_W = 1573,
1589	FCLT_D = 1574,	1589	FCLT_D = 1574,
1590	FCLT_W = 1575,	1590	FCLT_W = 1575,
1591	FCMP_D32 = 1576,	1591	FCMP_D32 = 1576,
1592	FCMP_D32_MM = 1577,	1592	FCMP_D32_MM = 1577,
1593	FCMP_D64 = 1578,	1593	FCMP_D64 = 1578,
1594	FCMP_S32 = 1579,	1594	FCMP_S32 = 1579,
1595	FCMP_S32_MM = 1580,	1595	FCMP_S32_MM = 1580,
1596	FCNE_D = 1581,	1596	FCNE_D = 1581,
1597	FCNE_W = 1582,	1597	FCNE_W = 1582,
1598	FCOR_D = 1583,	1598	FCOR_D = 1583,
1599	FCOR_W = 1584,	1599	FCOR_W = 1584,
1600	FCUEQ_D = 1585,	1600	FCUEQ_D = 1585,
1601	FCUEQ_W = 1586,	1601	FCUEQ_W = 1586,
1602	FCULE_D = 1587,	1602	FCULE_D = 1587,
1603	FCULE_W = 1588,	1603	FCULE_W = 1588,
1604	FCULT_D = 1589,	1604	FCULT_D = 1589,
1605	FCULT_W = 1590,	1605	FCULT_W = 1590,
1606	FCUNE_D = 1591,	1606	FCUNE_D = 1591,
1607	FCUNE_W = 1592,	1607	FCUNE_W = 1592,
1608	FCUN_D = 1593,	1608	FCUN_D = 1593,
1609	FCUN_W = 1594,	1609	FCUN_W = 1594,
1610	FDIV_D = 1595,	1610	FDIV_D = 1595,
1611	FDIV_D32 = 1596,	1611	FDIV_D32 = 1596,
1612	FDIV_D32_MM = 1597,	1612	FDIV_D32_MM = 1597,
1613	FDIV_D64 = 1598,	1613	FDIV_D64 = 1598,
1614	FDIV_D64_MM = 1599,	1614	FDIV_D64_MM = 1599,
1615	FDIV_S = 1600,	1615	FDIV_S = 1600,
1616	FDIV_S_MM = 1601,	1616	FDIV_S_MM = 1601,
1617	FDIV_S_MMR6 = 1602,	1617	FDIV_S_MMR6 = 1602,
1618	FDIV_W = 1603,	1618	FDIV_W = 1603,
1619	FEXDO_H = 1604,	1619	FEXDO_H = 1604,
1620	FEXDO_W = 1605,	1620	FEXDO_W = 1605,
1621	FEXP2_D = 1606,	1621	FEXP2_D = 1606,
1622	FEXP2_W = 1607,	1622	FEXP2_W = 1607,
1623	FEXUPL_D = 1608,	1623	FEXUPL_D = 1608,
1624	FEXUPL_W = 1609,	1624	FEXUPL_W = 1609,
1625	FEXUPR_D = 1610,	1625	FEXUPR_D = 1610,
1626	FEXUPR_W = 1611,	1626	FEXUPR_W = 1611,
1627	FFINT_S_D = 1612,	1627	FFINT_S_D = 1612,
1628	FFINT_S_W = 1613,	1628	FFINT_S_W = 1613,
1629	FFINT_U_D = 1614,	1629	FFINT_U_D = 1614,
1630	FFINT_U_W = 1615,	1630	FFINT_U_W = 1615,
1631	FFQL_D = 1616,	1631	FFQL_D = 1616,
1632	FFQL_W = 1617,	1632	FFQL_W = 1617,
1633	FFQR_D = 1618,	1633	FFQR_D = 1618,
1634	FFQR_W = 1619,	1634	FFQR_W = 1619,
1635	FILL_B = 1620,	1635	FILL_B = 1620,
1636	FILL_D = 1621,	1636	FILL_D = 1621,
1637	FILL_H = 1622,	1637	FILL_H = 1622,
1638	FILL_W = 1623,	1638	FILL_W = 1623,
1639	FLOG2_D = 1624,	1639	FLOG2_D = 1624,
1640	FLOG2_W = 1625,	1640	FLOG2_W = 1625,
1641	FLOOR_L_D64 = 1626,	1641	FLOOR_L_D64 = 1626,
1642	FLOOR_L_D_MMR6 = 1627,	1642	FLOOR_L_D_MMR6 = 1627,
1643	FLOOR_L_S = 1628,	1643	FLOOR_L_S = 1628,
1644	FLOOR_L_S_MMR6 = 1629,	1644	FLOOR_L_S_MMR6 = 1629,
1645	FLOOR_W_D32 = 1630,	1645	FLOOR_W_D32 = 1630,
1646	FLOOR_W_D64 = 1631,	1646	FLOOR_W_D64 = 1631,
1647	FLOOR_W_D_MMR6 = 1632,	1647	FLOOR_W_D_MMR6 = 1632,
1648	FLOOR_W_MM = 1633,	1648	FLOOR_W_MM = 1633,
1649	FLOOR_W_S = 1634,	1649	FLOOR_W_S = 1634,
1650	FLOOR_W_S_MM = 1635,	1650	FLOOR_W_S_MM = 1635,
1651	FLOOR_W_S_MMR6 = 1636,	1651	FLOOR_W_S_MMR6 = 1636,
1652	FMADD_D = 1637,	1652	FMADD_D = 1637,
1653	FMADD_W = 1638,	1653	FMADD_W = 1638,
1654	FMAX_A_D = 1639,	1654	FMAX_A_D = 1639,
1655	FMAX_A_W = 1640,	1655	FMAX_A_W = 1640,
1656	FMAX_D = 1641,	1656	FMAX_D = 1641,
1657	FMAX_W = 1642,	1657	FMAX_W = 1642,
1658	FMIN_A_D = 1643,	1658	FMIN_A_D = 1643,
1659	FMIN_A_W = 1644,	1659	FMIN_A_W = 1644,
1660	FMIN_D = 1645,	1660	FMIN_D = 1645,
1661	FMIN_W = 1646,	1661	FMIN_W = 1646,
1662	FMOV_D32 = 1647,	1662	FMOV_D32 = 1647,
1663	FMOV_D32_MM = 1648,	1663	FMOV_D32_MM = 1648,
1664	FMOV_D64 = 1649,	1664	FMOV_D64 = 1649,
1665	FMOV_D64_MM = 1650,	1665	FMOV_D64_MM = 1650,
1666	FMOV_D_MMR6 = 1651,	1666	FMOV_D_MMR6 = 1651,
1667	FMOV_S = 1652,	1667	FMOV_S = 1652,
1668	FMOV_S_MM = 1653,	1668	FMOV_S_MM = 1653,
1669	FMOV_S_MMR6 = 1654,	1669	FMOV_S_MMR6 = 1654,
1670	FMSUB_D = 1655,	1670	FMSUB_D = 1655,
1671	FMSUB_W = 1656,	1671	FMSUB_W = 1656,
1672	FMUL_D = 1657,	1672	FMUL_D = 1657,
1673	FMUL_D32 = 1658,	1673	FMUL_D32 = 1658,
1674	FMUL_D32_MM = 1659,	1674	FMUL_D32_MM = 1659,
1675	FMUL_D64 = 1660,	1675	FMUL_D64 = 1660,
1676	FMUL_D64_MM = 1661,	1676	FMUL_D64_MM = 1661,
1677	FMUL_PS64 = 1662,	1677	FMUL_PS64 = 1662,
1678	FMUL_S = 1663,	1678	FMUL_S = 1663,
1679	FMUL_S_MM = 1664,	1679	FMUL_S_MM = 1664,
1680	FMUL_S_MMR6 = 1665,	1680	FMUL_S_MMR6 = 1665,
1681	FMUL_W = 1666,	1681	FMUL_W = 1666,
1682	FNEG_D32 = 1667,	1682	FNEG_D32 = 1667,
1683	FNEG_D32_MM = 1668,	1683	FNEG_D32_MM = 1668,
1684	FNEG_D64 = 1669,	1684	FNEG_D64 = 1669,
1685	FNEG_D64_MM = 1670,	1685	FNEG_D64_MM = 1670,
1686	FNEG_S = 1671,	1686	FNEG_S = 1671,
1687	FNEG_S_MM = 1672,	1687	FNEG_S_MM = 1672,
1688	FNEG_S_MMR6 = 1673,	1688	FNEG_S_MMR6 = 1673,
1689	FORK = 1674,	1689	FORK = 1674,
1690	FRCP_D = 1675,	1690	FRCP_D = 1675,
1691	FRCP_W = 1676,	1691	FRCP_W = 1676,
1692	FRINT_D = 1677,	1692	FRINT_D = 1677,
1693	FRINT_W = 1678,	1693	FRINT_W = 1678,
1694	FRSQRT_D = 1679,	1694	FRSQRT_D = 1679,
1695	FRSQRT_W = 1680,	1695	FRSQRT_W = 1680,
1696	FSAF_D = 1681,	1696	FSAF_D = 1681,
1697	FSAF_W = 1682,	1697	FSAF_W = 1682,
1698	FSEQ_D = 1683,	1698	FSEQ_D = 1683,
1699	FSEQ_W = 1684,	1699	FSEQ_W = 1684,
1700	FSLE_D = 1685,	1700	FSLE_D = 1685,
1701	FSLE_W = 1686,	1701	FSLE_W = 1686,
1702	FSLT_D = 1687,	1702	FSLT_D = 1687,
1703	FSLT_W = 1688,	1703	FSLT_W = 1688,
1704	FSNE_D = 1689,	1704	FSNE_D = 1689,
1705	FSNE_W = 1690,	1705	FSNE_W = 1690,
1706	FSOR_D = 1691,	1706	FSOR_D = 1691,
1707	FSOR_W = 1692,	1707	FSOR_W = 1692,
1708	FSQRT_D = 1693,	1708	FSQRT_D = 1693,
1709	FSQRT_D32 = 1694,	1709	FSQRT_D32 = 1694,
1710	FSQRT_D32_MM = 1695,	1710	FSQRT_D32_MM = 1695,
1711	FSQRT_D64 = 1696,	1711	FSQRT_D64 = 1696,
1712	FSQRT_D64_MM = 1697,	1712	FSQRT_D64_MM = 1697,
1713	FSQRT_S = 1698,	1713	FSQRT_S = 1698,
1714	FSQRT_S_MM = 1699,	1714	FSQRT_S_MM = 1699,
1715	FSQRT_W = 1700,	1715	FSQRT_W = 1700,
1716	FSUB_D = 1701,	1716	FSUB_D = 1701,
1717	FSUB_D32 = 1702,	1717	FSUB_D32 = 1702,
1718	FSUB_D32_MM = 1703,	1718	FSUB_D32_MM = 1703,
1719	FSUB_D64 = 1704,	1719	FSUB_D64 = 1704,
1720	FSUB_D64_MM = 1705,	1720	FSUB_D64_MM = 1705,
1721	FSUB_PS64 = 1706,	1721	FSUB_PS64 = 1706,
1722	FSUB_S = 1707,	1722	FSUB_S = 1707,
1723	FSUB_S_MM = 1708,	1723	FSUB_S_MM = 1708,
1724	FSUB_S_MMR6 = 1709,	1724	FSUB_S_MMR6 = 1709,
1725	FSUB_W = 1710,	1725	FSUB_W = 1710,
1726	FSUEQ_D = 1711,	1726	FSUEQ_D = 1711,
1727	FSUEQ_W = 1712,	1727	FSUEQ_W = 1712,
1728	FSULE_D = 1713,	1728	FSULE_D = 1713,
1729	FSULE_W = 1714,	1729	FSULE_W = 1714,
1730	FSULT_D = 1715,	1730	FSULT_D = 1715,
1731	FSULT_W = 1716,	1731	FSULT_W = 1716,
1732	FSUNE_D = 1717,	1732	FSUNE_D = 1717,
1733	FSUNE_W = 1718,	1733	FSUNE_W = 1718,
1734	FSUN_D = 1719,	1734	FSUN_D = 1719,
1735	FSUN_W = 1720,	1735	FSUN_W = 1720,
1736	FTINT_S_D = 1721,	1736	FTINT_S_D = 1721,
1737	FTINT_S_W = 1722,	1737	FTINT_S_W = 1722,
1738	FTINT_U_D = 1723,	1738	FTINT_U_D = 1723,
1739	FTINT_U_W = 1724,	1739	FTINT_U_W = 1724,
1740	FTQ_H = 1725,	1740	FTQ_H = 1725,
1741	FTQ_W = 1726,	1741	FTQ_W = 1726,
1742	FTRUNC_S_D = 1727,	1742	FTRUNC_S_D = 1727,
1743	FTRUNC_S_W = 1728,	1743	FTRUNC_S_W = 1728,
1744	FTRUNC_U_D = 1729,	1744	FTRUNC_U_D = 1729,
1745	FTRUNC_U_W = 1730,	1745	FTRUNC_U_W = 1730,
1746	GINVI = 1731,	1746	GINVI = 1731,
1747	GINVI_MMR6 = 1732,	1747	GINVI_MMR6 = 1732,
1748	GINVT = 1733,	1748	GINVT = 1733,
1749	GINVT_MMR6 = 1734,	1749	GINVT_MMR6 = 1734,
1750	HADD_S_D = 1735,	1750	HADD_S_D = 1735,
1751	HADD_S_H = 1736,	1751	HADD_S_H = 1736,
1752	HADD_S_W = 1737,	1752	HADD_S_W = 1737,
1753	HADD_U_D = 1738,	1753	HADD_U_D = 1738,
1754	HADD_U_H = 1739,	1754	HADD_U_H = 1739,
1755	HADD_U_W = 1740,	1755	HADD_U_W = 1740,
1756	HSUB_S_D = 1741,	1756	HSUB_S_D = 1741,
1757	HSUB_S_H = 1742,	1757	HSUB_S_H = 1742,
1758	HSUB_S_W = 1743,	1758	HSUB_S_W = 1743,
1759	HSUB_U_D = 1744,	1759	HSUB_U_D = 1744,
1760	HSUB_U_H = 1745,	1760	HSUB_U_H = 1745,
1761	HSUB_U_W = 1746,	1761	HSUB_U_W = 1746,
1762	HYPCALL = 1747,	1762	HYPCALL = 1747,
1763	HYPCALL_MM = 1748,	1763	HYPCALL_MM = 1748,
1764	ILVEV_B = 1749,	1764	ILVEV_B = 1749,
1765	ILVEV_D = 1750,	1765	ILVEV_D = 1750,
1766	ILVEV_H = 1751,	1766	ILVEV_H = 1751,
1767	ILVEV_W = 1752,	1767	ILVEV_W = 1752,
1768	ILVL_B = 1753,	1768	ILVL_B = 1753,
1769	ILVL_D = 1754,	1769	ILVL_D = 1754,
1770	ILVL_H = 1755,	1770	ILVL_H = 1755,
1771	ILVL_W = 1756,	1771	ILVL_W = 1756,
1772	ILVOD_B = 1757,	1772	ILVOD_B = 1757,
1773	ILVOD_D = 1758,	1773	ILVOD_D = 1758,
1774	ILVOD_H = 1759,	1774	ILVOD_H = 1759,
1775	ILVOD_W = 1760,	1775	ILVOD_W = 1760,
1776	ILVR_B = 1761,	1776	ILVR_B = 1761,
1777	ILVR_D = 1762,	1777	ILVR_D = 1762,
1778	ILVR_H = 1763,	1778	ILVR_H = 1763,
1779	ILVR_W = 1764,	1779	ILVR_W = 1764,
1780	INS = 1765,	1780	INS = 1765,
1781	INSERT_B = 1766,	1781	INSERT_B = 1766,
1782	INSERT_D = 1767,	1782	INSERT_D = 1767,
1783	INSERT_H = 1768,	1783	INSERT_H = 1768,
1784	INSERT_W = 1769,	1784	INSERT_W = 1769,
1785	INSV = 1770,	1785	INSV = 1770,
1786	INSVE_B = 1771,	1786	INSVE_B = 1771,
1787	INSVE_D = 1772,	1787	INSVE_D = 1772,
1788	INSVE_H = 1773,	1788	INSVE_H = 1773,
1789	INSVE_W = 1774,	1789	INSVE_W = 1774,
1790	INSV_MM = 1775,	1790	INSV_MM = 1775,
1791	INS_MM = 1776,	1791	INS_MM = 1776,
1792	INS_MMR6 = 1777,	1792	INS_MMR6 = 1777,
1793	J = 1778,	1793	J = 1778,
1794	JAL = 1779,	1794	JAL = 1779,
1795	JALR = 1780,	1795	JALR = 1780,
1796	JALR16_MM = 1781,	1796	JALR16_MM = 1781,
1797	JALR64 = 1782,	1797	JALR64 = 1782,
1798	JALRC16_MMR6 = 1783,	1798	JALRC16_MMR6 = 1783,
1799	JALRC_HB_MMR6 = 1784,	1799	JALRC_HB_MMR6 = 1784,
1800	JALRC_MMR6 = 1785,	1800	JALRC_MMR6 = 1785,
1801	JALRS16_MM = 1786,	1801	JALRS16_MM = 1786,
1802	JALRS_MM = 1787,	1802	JALRS_MM = 1787,
1803	JALR_HB = 1788,	1803	JALR_HB = 1788,
1804	JALR_HB64 = 1789,	1804	JALR_HB64 = 1789,
1805	JALR_MM = 1790,	1805	JALR_MM = 1790,
1806	JALS_MM = 1791,	1806	JALS_MM = 1791,
1807	JALX = 1792,	1807	JALX = 1792,
1808	JALX_MM = 1793,	1808	JALX_MM = 1793,
1809	JAL_MM = 1794,	1809	JAL_MM = 1794,
1810	JIALC = 1795,	1810	JIALC = 1795,
1811	JIALC64 = 1796,	1811	JIALC64 = 1796,
1812	JIALC_MMR6 = 1797,	1812	JIALC_MMR6 = 1797,
1813	JIC = 1798,	1813	JIC = 1798,
1814	JIC64 = 1799,	1814	JIC64 = 1799,
1815	JIC_MMR6 = 1800,	1815	JIC_MMR6 = 1800,
1816	JR = 1801,	1816	JR = 1801,
1817	JR16_MM = 1802,	1817	JR16_MM = 1802,
1818	JR64 = 1803,	1818	JR64 = 1803,
1819	JRADDIUSP = 1804,	1819	JRADDIUSP = 1804,
1820	JRC16_MM = 1805,	1820	JRC16_MM = 1805,
1821	JRC16_MMR6 = 1806,	1821	JRC16_MMR6 = 1806,
1822	JRCADDIUSP_MMR6 = 1807,	1822	JRCADDIUSP_MMR6 = 1807,
1823	JR_HB = 1808,	1823	JR_HB = 1808,
1824	JR_HB64 = 1809,	1824	JR_HB64 = 1809,
1825	JR_HB64_R6 = 1810,	1825	JR_HB64_R6 = 1810,
1826	JR_HB_R6 = 1811,	1826	JR_HB_R6 = 1811,
1827	JR_MM = 1812,	1827	JR_MM = 1812,
1828	J_MM = 1813,	1828	J_MM = 1813,
1829	Jal16 = 1814,	1829	Jal16 = 1814,
1830	JalB16 = 1815,	1830	JalB16 = 1815,
1831	JrRa16 = 1816,	1831	JrRa16 = 1816,
1832	JrcRa16 = 1817,	1832	JrcRa16 = 1817,
1833	JrcRx16 = 1818,	1833	JrcRx16 = 1818,
1834	JumpLinkReg16 = 1819,	1834	JumpLinkReg16 = 1819,
1835	LB = 1820,	1835	LB = 1820,
1836	LB64 = 1821,	1836	LB64 = 1821,
1837	LBE = 1822,	1837	LBE = 1822,
1838	LBE_MM = 1823,	1838	LBE_MM = 1823,
1839	LBU16_MM = 1824,	1839	LBU16_MM = 1824,
1840	LBUX = 1825,	1840	LBUX = 1825,
1841	LBUX_MM = 1826,	1841	LBUX_MM = 1826,
1842	LBU_MMR6 = 1827,	1842	LBU_MMR6 = 1827,
1843	LB_MM = 1828,	1843	LB_MM = 1828,
1844	LB_MMR6 = 1829,	1844	LB_MMR6 = 1829,
1845	LBu = 1830,	1845	LBu = 1830,
1846	LBu64 = 1831,	1846	LBu64 = 1831,
1847	LBuE = 1832,	1847	LBuE = 1832,
1848	LBuE_MM = 1833,	1848	LBuE_MM = 1833,
1849	LBu_MM = 1834,	1849	LBu_MM = 1834,
1850	LD = 1835,	1850	LD = 1835,
1851	LDC1 = 1836,	1851	LDC1 = 1836,
1852	LDC164 = 1837,	1852	LDC164 = 1837,
1853	LDC1_D64_MMR6 = 1838,	1853	LDC1_D64_MMR6 = 1838,
1854	LDC1_MM_D32 = 1839,	1854	LDC1_MM_D32 = 1839,
1855	LDC1_MM_D64 = 1840,	1855	LDC1_MM_D64 = 1840,
1856	LDC2 = 1841,	1856	LDC2 = 1841,
1857	LDC2_MMR6 = 1842,	1857	LDC2_MMR6 = 1842,
1858	LDC2_R6 = 1843,	1858	LDC2_R6 = 1843,
1859	LDC3 = 1844,	1859	LDC3 = 1844,
1860	LDI_B = 1845,	1860	LDI_B = 1845,
1861	LDI_D = 1846,	1861	LDI_D = 1846,
1862	LDI_H = 1847,	1862	LDI_H = 1847,
1863	LDI_W = 1848,	1863	LDI_W = 1848,
1864	LDL = 1849,	1864	LDL = 1849,
1865	LDPC = 1850,	1865	LDPC = 1850,
1866	LDR = 1851,	1866	LDR = 1851,
1867	LDXC1 = 1852,	1867	LDXC1 = 1852,
1868	LDXC164 = 1853,	1868	LDXC164 = 1853,
1869	LD_B = 1854,	1869	LD_B = 1854,
1870	LD_D = 1855,	1870	LD_D = 1855,
1871	LD_H = 1856,	1871	LD_H = 1856,
1872	LD_W = 1857,	1872	LD_W = 1857,
1873	LEA_ADDiu = 1858,	1873	LEA_ADDiu = 1858,
1874	LEA_ADDiu64 = 1859,	1874	LEA_ADDiu64 = 1859,
1875	LEA_ADDiu_MM = 1860,	1875	LEA_ADDiu_MM = 1860,
1876	LH = 1861,	1876	LH = 1861,
1877	LH64 = 1862,	1877	LH64 = 1862,
1878	LHE = 1863,	1878	LHE = 1863,
1879	LHE_MM = 1864,	1879	LHE_MM = 1864,
1880	LHU16_MM = 1865,	1880	LHU16_MM = 1865,
1881	LHX = 1866,	1881	LHX = 1866,
1882	LHX_MM = 1867,	1882	LHX_MM = 1867,
1883	LH_MM = 1868,	1883	LH_MM = 1868,
1884	LHu = 1869,	1884	LHu = 1869,
1885	LHu64 = 1870,	1885	LHu64 = 1870,
1886	LHuE = 1871,	1886	LHuE = 1871,
1887	LHuE_MM = 1872,	1887	LHuE_MM = 1872,
1888	LHu_MM = 1873,	1888	LHu_MM = 1873,
1889	LI16_MM = 1874,	1889	LI16_MM = 1874,
1890	LI16_MMR6 = 1875,	1890	LI16_MMR6 = 1875,
1891	LL = 1876,	1891	LL = 1876,
1892	LL64 = 1877,	1892	LL64 = 1877,
1893	LL64_R6 = 1878,	1893	LL64_R6 = 1878,
1894	LLD = 1879,	1894	LLD = 1879,
1895	LLD_R6 = 1880,	1895	LLD_R6 = 1880,
1896	LLE = 1881,	1896	LLE = 1881,
1897	LLE_MM = 1882,	1897	LLE_MM = 1882,
1898	LL_MM = 1883,	1898	LL_MM = 1883,
1899	LL_MMR6 = 1884,	1899	LL_MMR6 = 1884,
1900	LL_R6 = 1885,	1900	LL_R6 = 1885,
1901	LSA = 1886,	1901	LSA = 1886,
1902	LSA_MMR6 = 1887,	1902	LSA_MMR6 = 1887,
1903	LSA_R6 = 1888,	1903	LSA_R6 = 1888,
1904	LUI_MMR6 = 1889,	1904	LUI_MMR6 = 1889,
1905	LUXC1 = 1890,	1905	LUXC1 = 1890,
1906	LUXC164 = 1891,	1906	LUXC164 = 1891,
1907	LUXC1_MM = 1892,	1907	LUXC1_MM = 1892,
1908	LUi = 1893,	1908	LUi = 1893,
1909	LUi64 = 1894,	1909	LUi64 = 1894,
1910	LUi_MM = 1895,	1910	LUi_MM = 1895,
1911	LW = 1896,	1911	LW = 1896,
1912	LW16_MM = 1897,	1912	LW16_MM = 1897,
1913	LW64 = 1898,	1913	LW64 = 1898,
1914	LWC1 = 1899,	1914	LWC1 = 1899,
1915	LWC1_MM = 1900,	1915	LWC1_MM = 1900,
1916	LWC2 = 1901,	1916	LWC2 = 1901,
1917	LWC2_MMR6 = 1902,	1917	LWC2_MMR6 = 1902,
1918	LWC2_R6 = 1903,	1918	LWC2_R6 = 1903,
1919	LWC3 = 1904,	1919	LWC3 = 1904,
1920	LWDSP = 1905,	1920	LWDSP = 1905,
1921	LWDSP_MM = 1906,	1921	LWDSP_MM = 1906,
1922	LWE = 1907,	1922	LWE = 1907,
1923	LWE_MM = 1908,	1923	LWE_MM = 1908,
1924	LWGP_MM = 1909,	1924	LWGP_MM = 1909,
1925	LWL = 1910,	1925	LWL = 1910,
1926	LWL64 = 1911,	1926	LWL64 = 1911,
1927	LWLE = 1912,	1927	LWLE = 1912,
1928	LWLE_MM = 1913,	1928	LWLE_MM = 1913,
1929	LWL_MM = 1914,	1929	LWL_MM = 1914,
1930	LWM16_MM = 1915,	1930	LWM16_MM = 1915,
1931	LWM16_MMR6 = 1916,	1931	LWM16_MMR6 = 1916,
1932	LWM32_MM = 1917,	1932	LWM32_MM = 1917,
1933	LWPC = 1918,	1933	LWPC = 1918,
1934	LWPC_MMR6 = 1919,	1934	LWPC_MMR6 = 1919,
1935	LWP_MM = 1920,	1935	LWP_MM = 1920,
1936	LWR = 1921,	1936	LWR = 1921,
1937	LWR64 = 1922,	1937	LWR64 = 1922,
1938	LWRE = 1923,	1938	LWRE = 1923,
1939	LWRE_MM = 1924,	1939	LWRE_MM = 1924,
1940	LWR_MM = 1925,	1940	LWR_MM = 1925,
1941	LWSP_MM = 1926,	1941	LWSP_MM = 1926,
1942	LWUPC = 1927,	1942	LWUPC = 1927,
1943	LWU_MM = 1928,	1943	LWU_MM = 1928,
1944	LWX = 1929,	1944	LWX = 1929,
1945	LWXC1 = 1930,	1945	LWXC1 = 1930,
1946	LWXC1_MM = 1931,	1946	LWXC1_MM = 1931,
1947	LWXS_MM = 1932,	1947	LWXS_MM = 1932,
1948	LWX_MM = 1933,	1948	LWX_MM = 1933,
1949	LW_MM = 1934,	1949	LW_MM = 1934,
1950	LW_MMR6 = 1935,	1950	LW_MMR6 = 1935,
1951	LWu = 1936,	1951	LWu = 1936,
1952	LbRxRyOffMemX16 = 1937,	1952	LbRxRyOffMemX16 = 1937,
1953	LbuRxRyOffMemX16 = 1938,	1953	LbuRxRyOffMemX16 = 1938,
1954	LhRxRyOffMemX16 = 1939,	1954	LhRxRyOffMemX16 = 1939,
1955	LhuRxRyOffMemX16 = 1940,	1955	LhuRxRyOffMemX16 = 1940,
1956	LiRxImm16 = 1941,	1956	LiRxImm16 = 1941,
1957	LiRxImmAlignX16 = 1942,	1957	LiRxImmAlignX16 = 1942,
1958	LiRxImmX16 = 1943,	1958	LiRxImmX16 = 1943,
1959	LwRxPcTcp16 = 1944,	1959	LwRxPcTcp16 = 1944,
1960	LwRxPcTcpX16 = 1945,	1960	LwRxPcTcpX16 = 1945,
1961	LwRxRyOffMemX16 = 1946,	1961	LwRxRyOffMemX16 = 1946,
1962	LwRxSpImmX16 = 1947,	1962	LwRxSpImmX16 = 1947,
1963	MADD = 1948,	1963	MADD = 1948,
1964	MADDF_D = 1949,	1964	MADDF_D = 1949,
1965	MADDF_D_MMR6 = 1950,	1965	MADDF_D_MMR6 = 1950,
1966	MADDF_S = 1951,	1966	MADDF_S = 1951,
1967	MADDF_S_MMR6 = 1952,	1967	MADDF_S_MMR6 = 1952,
1968	MADDR_Q_H = 1953,	1968	MADDR_Q_H = 1953,
1969	MADDR_Q_W = 1954,	1969	MADDR_Q_W = 1954,
1970	MADDU = 1955,	1970	MADDU = 1955,
1971	MADDU_DSP = 1956,	1971	MADDU_DSP = 1956,
1972	MADDU_DSP_MM = 1957,	1972	MADDU_DSP_MM = 1957,
1973	MADDU_MM = 1958,	1973	MADDU_MM = 1958,
1974	MADDV_B = 1959,	1974	MADDV_B = 1959,
1975	MADDV_D = 1960,	1975	MADDV_D = 1960,
1976	MADDV_H = 1961,	1976	MADDV_H = 1961,
1977	MADDV_W = 1962,	1977	MADDV_W = 1962,
1978	MADD_D32 = 1963,	1978	MADD_D32 = 1963,
1979	MADD_D32_MM = 1964,	1979	MADD_D32_MM = 1964,
1980	MADD_D64 = 1965,	1980	MADD_D64 = 1965,
1981	MADD_DSP = 1966,	1981	MADD_DSP = 1966,
1982	MADD_DSP_MM = 1967,	1982	MADD_DSP_MM = 1967,
1983	MADD_MM = 1968,	1983	MADD_MM = 1968,
1984	MADD_Q_H = 1969,	1984	MADD_Q_H = 1969,
1985	MADD_Q_W = 1970,	1985	MADD_Q_W = 1970,
1986	MADD_S = 1971,	1986	MADD_S = 1971,
1987	MADD_S_MM = 1972,	1987	MADD_S_MM = 1972,
1988	MAQ_SA_W_PHL = 1973,	1988	MAQ_SA_W_PHL = 1973,
1989	MAQ_SA_W_PHL_MM = 1974,	1989	MAQ_SA_W_PHL_MM = 1974,
1990	MAQ_SA_W_PHR = 1975,	1990	MAQ_SA_W_PHR = 1975,
1991	MAQ_SA_W_PHR_MM = 1976,	1991	MAQ_SA_W_PHR_MM = 1976,
1992	MAQ_S_W_PHL = 1977,	1992	MAQ_S_W_PHL = 1977,
1993	MAQ_S_W_PHL_MM = 1978,	1993	MAQ_S_W_PHL_MM = 1978,
1994	MAQ_S_W_PHR = 1979,	1994	MAQ_S_W_PHR = 1979,
1995	MAQ_S_W_PHR_MM = 1980,	1995	MAQ_S_W_PHR_MM = 1980,
1996	MAXA_D = 1981,	1996	MAXA_D = 1981,
1997	MAXA_D_MMR6 = 1982,	1997	MAXA_D_MMR6 = 1982,
1998	MAXA_S = 1983,	1998	MAXA_S = 1983,
1999	MAXA_S_MMR6 = 1984,	1999	MAXA_S_MMR6 = 1984,
2000	MAXI_S_B = 1985,	2000	MAXI_S_B = 1985,
2001	MAXI_S_D = 1986,	2001	MAXI_S_D = 1986,
2002	MAXI_S_H = 1987,	2002	MAXI_S_H = 1987,
2003	MAXI_S_W = 1988,	2003	MAXI_S_W = 1988,
2004	MAXI_U_B = 1989,	2004	MAXI_U_B = 1989,
2005	MAXI_U_D = 1990,	2005	MAXI_U_D = 1990,
2006	MAXI_U_H = 1991,	2006	MAXI_U_H = 1991,
2007	MAXI_U_W = 1992,	2007	MAXI_U_W = 1992,
2008	MAX_A_B = 1993,	2008	MAX_A_B = 1993,
2009	MAX_A_D = 1994,	2009	MAX_A_D = 1994,
2010	MAX_A_H = 1995,	2010	MAX_A_H = 1995,
2011	MAX_A_W = 1996,	2011	MAX_A_W = 1996,
2012	MAX_D = 1997,	2012	MAX_D = 1997,
2013	MAX_D_MMR6 = 1998,	2013	MAX_D_MMR6 = 1998,
2014	MAX_S = 1999,	2014	MAX_S = 1999,
2015	MAX_S_B = 2000,	2015	MAX_S_B = 2000,
2016	MAX_S_D = 2001,	2016	MAX_S_D = 2001,
2017	MAX_S_H = 2002,	2017	MAX_S_H = 2002,
2018	MAX_S_MMR6 = 2003,	2018	MAX_S_MMR6 = 2003,
2019	MAX_S_W = 2004,	2019	MAX_S_W = 2004,
2020	MAX_U_B = 2005,	2020	MAX_U_B = 2005,
2021	MAX_U_D = 2006,	2021	MAX_U_D = 2006,
2022	MAX_U_H = 2007,	2022	MAX_U_H = 2007,
2023	MAX_U_W = 2008,	2023	MAX_U_W = 2008,
2024	MFC0 = 2009,	2024	MFC0 = 2009,
2025	MFC0_MMR6 = 2010,	2025	MFC0_MMR6 = 2010,
2026	MFC1 = 2011,	2026	MFC1 = 2011,
2027	MFC1_D64 = 2012,	2027	MFC1_D64 = 2012,
2028	MFC1_MM = 2013,	2028	MFC1_MM = 2013,
2029	MFC1_MMR6 = 2014,	2029	MFC1_MMR6 = 2014,
2030	MFC2 = 2015,	2030	MFC2 = 2015,
2031	MFC2_MMR6 = 2016,	2031	MFC2_MMR6 = 2016,
2032	MFGC0 = 2017,	2032	MFGC0 = 2017,
2033	MFGC0_MM = 2018,	2033	MFGC0_MM = 2018,
2034	MFHC0_MMR6 = 2019,	2034	MFHC0_MMR6 = 2019,
2035	MFHC1_D32 = 2020,	2035	MFHC1_D32 = 2020,
2036	MFHC1_D32_MM = 2021,	2036	MFHC1_D32_MM = 2021,
2037	MFHC1_D64 = 2022,	2037	MFHC1_D64 = 2022,
2038	MFHC1_D64_MM = 2023,	2038	MFHC1_D64_MM = 2023,
2039	MFHC2_MMR6 = 2024,	2039	MFHC2_MMR6 = 2024,
2040	MFHGC0 = 2025,	2040	MFHGC0 = 2025,
2041	MFHGC0_MM = 2026,	2041	MFHGC0_MM = 2026,
2042	MFHI = 2027,	2042	MFHI = 2027,
2043	MFHI16_MM = 2028,	2043	MFHI16_MM = 2028,
2044	MFHI64 = 2029,	2044	MFHI64 = 2029,
2045	MFHI_DSP = 2030,	2045	MFHI_DSP = 2030,
2046	MFHI_DSP_MM = 2031,	2046	MFHI_DSP_MM = 2031,
2047	MFHI_MM = 2032,	2047	MFHI_MM = 2032,
2048	MFLO = 2033,	2048	MFLO = 2033,
2049	MFLO16_MM = 2034,	2049	MFLO16_MM = 2034,
2050	MFLO64 = 2035,	2050	MFLO64 = 2035,
2051	MFLO_DSP = 2036,	2051	MFLO_DSP = 2036,
2052	MFLO_DSP_MM = 2037,	2052	MFLO_DSP_MM = 2037,
2053	MFLO_MM = 2038,	2053	MFLO_MM = 2038,
2054	MFTR = 2039,	2054	MFTR = 2039,
2055	MINA_D = 2040,	2055	MINA_D = 2040,
2056	MINA_D_MMR6 = 2041,	2056	MINA_D_MMR6 = 2041,
2057	MINA_S = 2042,	2057	MINA_S = 2042,
2058	MINA_S_MMR6 = 2043,	2058	MINA_S_MMR6 = 2043,
2059	MINI_S_B = 2044,	2059	MINI_S_B = 2044,
2060	MINI_S_D = 2045,	2060	MINI_S_D = 2045,
2061	MINI_S_H = 2046,	2061	MINI_S_H = 2046,
2062	MINI_S_W = 2047,	2062	MINI_S_W = 2047,
2063	MINI_U_B = 2048,	2063	MINI_U_B = 2048,
2064	MINI_U_D = 2049,	2064	MINI_U_D = 2049,
2065	MINI_U_H = 2050,	2065	MINI_U_H = 2050,
2066	MINI_U_W = 2051,	2066	MINI_U_W = 2051,
2067	MIN_A_B = 2052,	2067	MIN_A_B = 2052,
2068	MIN_A_D = 2053,	2068	MIN_A_D = 2053,
2069	MIN_A_H = 2054,	2069	MIN_A_H = 2054,
2070	MIN_A_W = 2055,	2070	MIN_A_W = 2055,
2071	MIN_D = 2056,	2071	MIN_D = 2056,
2072	MIN_D_MMR6 = 2057,	2072	MIN_D_MMR6 = 2057,
2073	MIN_S = 2058,	2073	MIN_S = 2058,
2074	MIN_S_B = 2059,	2074	MIN_S_B = 2059,
2075	MIN_S_D = 2060,	2075	MIN_S_D = 2060,
2076	MIN_S_H = 2061,	2076	MIN_S_H = 2061,
2077	MIN_S_MMR6 = 2062,	2077	MIN_S_MMR6 = 2062,
2078	MIN_S_W = 2063,	2078	MIN_S_W = 2063,
2079	MIN_U_B = 2064,	2079	MIN_U_B = 2064,
2080	MIN_U_D = 2065,	2080	MIN_U_D = 2065,
2081	MIN_U_H = 2066,	2081	MIN_U_H = 2066,
2082	MIN_U_W = 2067,	2082	MIN_U_W = 2067,
2083	MOD = 2068,	2083	MOD = 2068,
2084	MODSUB = 2069,	2084	MODSUB = 2069,
2085	MODSUB_MM = 2070,	2085	MODSUB_MM = 2070,
2086	MODU = 2071,	2086	MODU = 2071,
2087	MODU_MMR6 = 2072,	2087	MODU_MMR6 = 2072,
2088	MOD_MMR6 = 2073,	2088	MOD_MMR6 = 2073,
2089	MOD_S_B = 2074,	2089	MOD_S_B = 2074,
2090	MOD_S_D = 2075,	2090	MOD_S_D = 2075,
2091	MOD_S_H = 2076,	2091	MOD_S_H = 2076,
2092	MOD_S_W = 2077,	2092	MOD_S_W = 2077,
2093	MOD_U_B = 2078,	2093	MOD_U_B = 2078,
2094	MOD_U_D = 2079,	2094	MOD_U_D = 2079,
2095	MOD_U_H = 2080,	2095	MOD_U_H = 2080,
2096	MOD_U_W = 2081,	2096	MOD_U_W = 2081,
2097	MOVE16_MM = 2082,	2097	MOVE16_MM = 2082,
2098	MOVE16_MMR6 = 2083,	2098	MOVE16_MMR6 = 2083,
2099	MOVEP_MM = 2084,	2099	MOVEP_MM = 2084,
2100	MOVEP_MMR6 = 2085,	2100	MOVEP_MMR6 = 2085,
2101	MOVE_V = 2086,	2101	MOVE_V = 2086,
2102	MOVF_D32 = 2087,	2102	MOVF_D32 = 2087,
2103	MOVF_D32_MM = 2088,	2103	MOVF_D32_MM = 2088,
2104	MOVF_D64 = 2089,	2104	MOVF_D64 = 2089,
2105	MOVF_I = 2090,	2105	MOVF_I = 2090,
2106	MOVF_I64 = 2091,	2106	MOVF_I64 = 2091,
2107	MOVF_I_MM = 2092,	2107	MOVF_I_MM = 2092,
2108	MOVF_S = 2093,	2108	MOVF_S = 2093,
2109	MOVF_S_MM = 2094,	2109	MOVF_S_MM = 2094,
2110	MOVN_I64_D64 = 2095,	2110	MOVN_I64_D64 = 2095,
2111	MOVN_I64_I = 2096,	2111	MOVN_I64_I = 2096,
2112	MOVN_I64_I64 = 2097,	2112	MOVN_I64_I64 = 2097,
2113	MOVN_I64_S = 2098,	2113	MOVN_I64_S = 2098,
2114	MOVN_I_D32 = 2099,	2114	MOVN_I_D32 = 2099,
2115	MOVN_I_D32_MM = 2100,	2115	MOVN_I_D32_MM = 2100,
2116	MOVN_I_D64 = 2101,	2116	MOVN_I_D64 = 2101,
2117	MOVN_I_I = 2102,	2117	MOVN_I_I = 2102,
2118	MOVN_I_I64 = 2103,	2118	MOVN_I_I64 = 2103,
2119	MOVN_I_MM = 2104,	2119	MOVN_I_MM = 2104,
2120	MOVN_I_S = 2105,	2120	MOVN_I_S = 2105,
2121	MOVN_I_S_MM = 2106,	2121	MOVN_I_S_MM = 2106,
2122	MOVT_D32 = 2107,	2122	MOVT_D32 = 2107,
2123	MOVT_D32_MM = 2108,	2123	MOVT_D32_MM = 2108,
2124	MOVT_D64 = 2109,	2124	MOVT_D64 = 2109,
2125	MOVT_I = 2110,	2125	MOVT_I = 2110,
2126	MOVT_I64 = 2111,	2126	MOVT_I64 = 2111,
2127	MOVT_I_MM = 2112,	2127	MOVT_I_MM = 2112,
2128	MOVT_S = 2113,	2128	MOVT_S = 2113,
2129	MOVT_S_MM = 2114,	2129	MOVT_S_MM = 2114,
2130	MOVZ_I64_D64 = 2115,	2130	MOVZ_I64_D64 = 2115,
2131	MOVZ_I64_I = 2116,	2131	MOVZ_I64_I = 2116,
2132	MOVZ_I64_I64 = 2117,	2132	MOVZ_I64_I64 = 2117,
2133	MOVZ_I64_S = 2118,	2133	MOVZ_I64_S = 2118,
2134	MOVZ_I_D32 = 2119,	2134	MOVZ_I_D32 = 2119,
2135	MOVZ_I_D32_MM = 2120,	2135	MOVZ_I_D32_MM = 2120,
2136	MOVZ_I_D64 = 2121,	2136	MOVZ_I_D64 = 2121,
2137	MOVZ_I_I = 2122,	2137	MOVZ_I_I = 2122,
2138	MOVZ_I_I64 = 2123,	2138	MOVZ_I_I64 = 2123,
2139	MOVZ_I_MM = 2124,	2139	MOVZ_I_MM = 2124,
2140	MOVZ_I_S = 2125,	2140	MOVZ_I_S = 2125,
2141	MOVZ_I_S_MM = 2126,	2141	MOVZ_I_S_MM = 2126,
2142	MSUB = 2127,	2142	MSUB = 2127,
2143	MSUBF_D = 2128,	2143	MSUBF_D = 2128,
2144	MSUBF_D_MMR6 = 2129,	2144	MSUBF_D_MMR6 = 2129,
2145	MSUBF_S = 2130,	2145	MSUBF_S = 2130,
2146	MSUBF_S_MMR6 = 2131,	2146	MSUBF_S_MMR6 = 2131,
2147	MSUBR_Q_H = 2132,	2147	MSUBR_Q_H = 2132,
2148	MSUBR_Q_W = 2133,	2148	MSUBR_Q_W = 2133,
2149	MSUBU = 2134,	2149	MSUBU = 2134,
2150	MSUBU_DSP = 2135,	2150	MSUBU_DSP = 2135,
2151	MSUBU_DSP_MM = 2136,	2151	MSUBU_DSP_MM = 2136,
2152	MSUBU_MM = 2137,	2152	MSUBU_MM = 2137,
2153	MSUBV_B = 2138,	2153	MSUBV_B = 2138,
2154	MSUBV_D = 2139,	2154	MSUBV_D = 2139,
2155	MSUBV_H = 2140,	2155	MSUBV_H = 2140,
2156	MSUBV_W = 2141,	2156	MSUBV_W = 2141,
2157	MSUB_D32 = 2142,	2157	MSUB_D32 = 2142,
2158	MSUB_D32_MM = 2143,	2158	MSUB_D32_MM = 2143,
2159	MSUB_D64 = 2144,	2159	MSUB_D64 = 2144,
2160	MSUB_DSP = 2145,	2160	MSUB_DSP = 2145,
2161	MSUB_DSP_MM = 2146,	2161	MSUB_DSP_MM = 2146,
2162	MSUB_MM = 2147,	2162	MSUB_MM = 2147,
2163	MSUB_Q_H = 2148,	2163	MSUB_Q_H = 2148,
2164	MSUB_Q_W = 2149,	2164	MSUB_Q_W = 2149,
2165	MSUB_S = 2150,	2165	MSUB_S = 2150,
2166	MSUB_S_MM = 2151,	2166	MSUB_S_MM = 2151,
2167	MTC0 = 2152,	2167	MTC0 = 2152,
2168	MTC0_MMR6 = 2153,	2168	MTC0_MMR6 = 2153,
2169	MTC1 = 2154,	2169	MTC1 = 2154,
2170	MTC1_D64 = 2155,	2170	MTC1_D64 = 2155,
2171	MTC1_D64_MM = 2156,	2171	MTC1_D64_MM = 2156,
2172	MTC1_MM = 2157,	2172	MTC1_MM = 2157,
2173	MTC1_MMR6 = 2158,	2173	MTC1_MMR6 = 2158,
2174	MTC2 = 2159,	2174	MTC2 = 2159,
2175	MTC2_MMR6 = 2160,	2175	MTC2_MMR6 = 2160,
2176	MTGC0 = 2161,	2176	MTGC0 = 2161,
2177	MTGC0_MM = 2162,	2177	MTGC0_MM = 2162,
2178	MTHC0_MMR6 = 2163,	2178	MTHC0_MMR6 = 2163,
2179	MTHC1_D32 = 2164,	2179	MTHC1_D32 = 2164,
2180	MTHC1_D32_MM = 2165,	2180	MTHC1_D32_MM = 2165,
2181	MTHC1_D64 = 2166,	2181	MTHC1_D64 = 2166,
2182	MTHC1_D64_MM = 2167,	2182	MTHC1_D64_MM = 2167,
2183	MTHC2_MMR6 = 2168,	2183	MTHC2_MMR6 = 2168,
2184	MTHGC0 = 2169,	2184	MTHGC0 = 2169,
2185	MTHGC0_MM = 2170,	2185	MTHGC0_MM = 2170,
2186	MTHI = 2171,	2186	MTHI = 2171,
2187	MTHI64 = 2172,	2187	MTHI64 = 2172,
2188	MTHI_DSP = 2173,	2188	MTHI_DSP = 2173,
2189	MTHI_DSP_MM = 2174,	2189	MTHI_DSP_MM = 2174,
2190	MTHI_MM = 2175,	2190	MTHI_MM = 2175,
2191	MTHLIP = 2176,	2191	MTHLIP = 2176,
2192	MTHLIP_MM = 2177,	2192	MTHLIP_MM = 2177,
2193	MTLO = 2178,	2193	MTLO = 2178,
2194	MTLO64 = 2179,	2194	MTLO64 = 2179,
2195	MTLO_DSP = 2180,	2195	MTLO_DSP = 2180,
2196	MTLO_DSP_MM = 2181,	2196	MTLO_DSP_MM = 2181,
2197	MTLO_MM = 2182,	2197	MTLO_MM = 2182,
2198	MTM0 = 2183,	2198	MTM0 = 2183,
2199	MTM1 = 2184,	2199	MTM1 = 2184,
2200	MTM2 = 2185,	2200	MTM2 = 2185,
2201	MTP0 = 2186,	2201	MTP0 = 2186,
2202	MTP1 = 2187,	2202	MTP1 = 2187,
2203	MTP2 = 2188,	2203	MTP2 = 2188,
2204	MTTR = 2189,	2204	MTTR = 2189,
2205	MUH = 2190,	2205	MUH = 2190,
2206	MUHU = 2191,	2206	MUHU = 2191,
2207	MUHU_MMR6 = 2192,	2207	MUHU_MMR6 = 2192,
2208	MUH_MMR6 = 2193,	2208	MUH_MMR6 = 2193,
2209	MUL = 2194,	2209	MUL = 2194,
2210	MULEQ_S_W_PHL = 2195,	2210	MULEQ_S_W_PHL = 2195,
2211	MULEQ_S_W_PHL_MM = 2196,	2211	MULEQ_S_W_PHL_MM = 2196,
2212	MULEQ_S_W_PHR = 2197,	2212	MULEQ_S_W_PHR = 2197,
2213	MULEQ_S_W_PHR_MM = 2198,	2213	MULEQ_S_W_PHR_MM = 2198,
2214	MULEU_S_PH_QBL = 2199,	2214	MULEU_S_PH_QBL = 2199,
2215	MULEU_S_PH_QBL_MM = 2200,	2215	MULEU_S_PH_QBL_MM = 2200,
2216	MULEU_S_PH_QBR = 2201,	2216	MULEU_S_PH_QBR = 2201,
2217	MULEU_S_PH_QBR_MM = 2202,	2217	MULEU_S_PH_QBR_MM = 2202,
2218	MULQ_RS_PH = 2203,	2218	MULQ_RS_PH = 2203,
2219	MULQ_RS_PH_MM = 2204,	2219	MULQ_RS_PH_MM = 2204,
2220	MULQ_RS_W = 2205,	2220	MULQ_RS_W = 2205,
2221	MULQ_RS_W_MMR2 = 2206,	2221	MULQ_RS_W_MMR2 = 2206,
2222	MULQ_S_PH = 2207,	2222	MULQ_S_PH = 2207,
2223	MULQ_S_PH_MMR2 = 2208,	2223	MULQ_S_PH_MMR2 = 2208,
2224	MULQ_S_W = 2209,	2224	MULQ_S_W = 2209,
2225	MULQ_S_W_MMR2 = 2210,	2225	MULQ_S_W_MMR2 = 2210,
2226	MULR_PS64 = 2211,	2226	MULR_PS64 = 2211,
2227	MULR_Q_H = 2212,	2227	MULR_Q_H = 2212,
2228	MULR_Q_W = 2213,	2228	MULR_Q_W = 2213,
2229	MULSAQ_S_W_PH = 2214,	2229	MULSAQ_S_W_PH = 2214,
2230	MULSAQ_S_W_PH_MM = 2215,	2230	MULSAQ_S_W_PH_MM = 2215,
2231	MULSA_W_PH = 2216,	2231	MULSA_W_PH = 2216,
2232	MULSA_W_PH_MMR2 = 2217,	2232	MULSA_W_PH_MMR2 = 2217,
2233	MULT = 2218,	2233	MULT = 2218,
2234	MULTU_DSP = 2219,	2234	MULTU_DSP = 2219,
2235	MULTU_DSP_MM = 2220,	2235	MULTU_DSP_MM = 2220,
2236	MULT_DSP = 2221,	2236	MULT_DSP = 2221,
2237	MULT_DSP_MM = 2222,	2237	MULT_DSP_MM = 2222,
2238	MULT_MM = 2223,	2238	MULT_MM = 2223,
2239	MULTu = 2224,	2239	MULTu = 2224,
2240	MULTu_MM = 2225,	2240	MULTu_MM = 2225,
2241	MULU = 2226,	2241	MULU = 2226,
2242	MULU_MMR6 = 2227,	2242	MULU_MMR6 = 2227,
2243	MULV_B = 2228,	2243	MULV_B = 2228,
2244	MULV_D = 2229,	2244	MULV_D = 2229,
2245	MULV_H = 2230,	2245	MULV_H = 2230,
2246	MULV_W = 2231,	2246	MULV_W = 2231,
2247	MUL_MM = 2232,	2247	MUL_MM = 2232,
2248	MUL_MMR6 = 2233,	2248	MUL_MMR6 = 2233,
2249	MUL_PH = 2234,	2249	MUL_PH = 2234,
2250	MUL_PH_MMR2 = 2235,	2250	MUL_PH_MMR2 = 2235,
2251	MUL_Q_H = 2236,	2251	MUL_Q_H = 2236,
2252	MUL_Q_W = 2237,	2252	MUL_Q_W = 2237,
2253	MUL_R6 = 2238,	2253	MUL_R6 = 2238,
2254	MUL_S_PH = 2239,	2254	MUL_S_PH = 2239,
2255	MUL_S_PH_MMR2 = 2240,	2255	MUL_S_PH_MMR2 = 2240,
2256	Mfhi16 = 2241,	2256	Mfhi16 = 2241,
2257	Mflo16 = 2242,	2257	Mflo16 = 2242,
2258	Move32R16 = 2243,	2258	Move32R16 = 2243,
2259	MoveR3216 = 2244,	2259	MoveR3216 = 2244,
2260	NLOC_B = 2245,	2260	NLOC_B = 2245,
2261	NLOC_D = 2246,	2261	NLOC_D = 2246,
2262	NLOC_H = 2247,	2262	NLOC_H = 2247,
2263	NLOC_W = 2248,	2263	NLOC_W = 2248,
2264	NLZC_B = 2249,	2264	NLZC_B = 2249,
2265	NLZC_D = 2250,	2265	NLZC_D = 2250,
2266	NLZC_H = 2251,	2266	NLZC_H = 2251,
2267	NLZC_W = 2252,	2267	NLZC_W = 2252,
2268	NMADD_D32 = 2253,	2268	NMADD_D32 = 2253,
2269	NMADD_D32_MM = 2254,	2269	NMADD_D32_MM = 2254,
2270	NMADD_D64 = 2255,	2270	NMADD_D64 = 2255,
2271	NMADD_S = 2256,	2271	NMADD_S = 2256,
2272	NMADD_S_MM = 2257,	2272	NMADD_S_MM = 2257,
2273	NMSUB_D32 = 2258,	2273	NMSUB_D32 = 2258,
2274	NMSUB_D32_MM = 2259,	2274	NMSUB_D32_MM = 2259,
2275	NMSUB_D64 = 2260,	2275	NMSUB_D64 = 2260,
2276	NMSUB_S = 2261,	2276	NMSUB_S = 2261,
2277	NMSUB_S_MM = 2262,	2277	NMSUB_S_MM = 2262,
2278	NOR = 2263,	2278	NOR = 2263,
2279	NOR64 = 2264,	2279	NOR64 = 2264,
2280	NORI_B = 2265,	2280	NORI_B = 2265,
2281	NOR_MM = 2266,	2281	NOR_MM = 2266,
2282	NOR_MMR6 = 2267,	2282	NOR_MMR6 = 2267,
2283	NOR_V = 2268,	2283	NOR_V = 2268,
2284	NOT16_MM = 2269,	2284	NOT16_MM = 2269,
2285	NOT16_MMR6 = 2270,	2285	NOT16_MMR6 = 2270,
2286	NegRxRy16 = 2271,	2286	NegRxRy16 = 2271,
2287	NotRxRy16 = 2272,	2287	NotRxRy16 = 2272,
2288	OR = 2273,	2288	OR = 2273,
2289	OR16_MM = 2274,	2289	OR16_MM = 2274,
2290	OR16_MMR6 = 2275,	2290	OR16_MMR6 = 2275,
2291	OR64 = 2276,	2291	OR64 = 2276,
2292	ORI_B = 2277,	2292	ORI_B = 2277,
2293	ORI_MMR6 = 2278,	2293	ORI_MMR6 = 2278,
2294	OR_MM = 2279,	2294	OR_MM = 2279,
2295	OR_MMR6 = 2280,	2295	OR_MMR6 = 2280,
2296	OR_V = 2281,	2296	OR_V = 2281,
2297	ORi = 2282,	2297	ORi = 2282,
2298	ORi64 = 2283,	2298	ORi64 = 2283,
2299	ORi_MM = 2284,	2299	ORi_MM = 2284,
2300	OrRxRxRy16 = 2285,	2300	OrRxRxRy16 = 2285,
2301	PACKRL_PH = 2286,	2301	PACKRL_PH = 2286,
2302	PACKRL_PH_MM = 2287,	2302	PACKRL_PH_MM = 2287,
2303	PAUSE = 2288,	2303	PAUSE = 2288,
2304	PAUSE_MM = 2289,	2304	PAUSE_MM = 2289,
2305	PAUSE_MMR6 = 2290,	2305	PAUSE_MMR6 = 2290,
2306	PCKEV_B = 2291,	2306	PCKEV_B = 2291,
2307	PCKEV_D = 2292,	2307	PCKEV_D = 2292,
2308	PCKEV_H = 2293,	2308	PCKEV_H = 2293,
2309	PCKEV_W = 2294,	2309	PCKEV_W = 2294,
2310	PCKOD_B = 2295,	2310	PCKOD_B = 2295,
2311	PCKOD_D = 2296,	2311	PCKOD_D = 2296,
2312	PCKOD_H = 2297,	2312	PCKOD_H = 2297,
2313	PCKOD_W = 2298,	2313	PCKOD_W = 2298,
2314	PCNT_B = 2299,	2314	PCNT_B = 2299,
2315	PCNT_D = 2300,	2315	PCNT_D = 2300,
2316	PCNT_H = 2301,	2316	PCNT_H = 2301,
2317	PCNT_W = 2302,	2317	PCNT_W = 2302,
2318	PICK_PH = 2303,	2318	PICK_PH = 2303,
2319	PICK_PH_MM = 2304,	2319	PICK_PH_MM = 2304,
2320	PICK_QB = 2305,	2320	PICK_QB = 2305,
2321	PICK_QB_MM = 2306,	2321	PICK_QB_MM = 2306,
2322	PLL_PS64 = 2307,	2322	PLL_PS64 = 2307,
2323	PLU_PS64 = 2308,	2323	PLU_PS64 = 2308,
2324	POP = 2309,	2324	POP = 2309,
2325	PRECEQU_PH_QBL = 2310,	2325	PRECEQU_PH_QBL = 2310,
2326	PRECEQU_PH_QBLA = 2311,	2326	PRECEQU_PH_QBLA = 2311,
2327	PRECEQU_PH_QBLA_MM = 2312,	2327	PRECEQU_PH_QBLA_MM = 2312,
2328	PRECEQU_PH_QBL_MM = 2313,	2328	PRECEQU_PH_QBL_MM = 2313,
2329	PRECEQU_PH_QBR = 2314,	2329	PRECEQU_PH_QBR = 2314,
2330	PRECEQU_PH_QBRA = 2315,	2330	PRECEQU_PH_QBRA = 2315,
2331	PRECEQU_PH_QBRA_MM = 2316,	2331	PRECEQU_PH_QBRA_MM = 2316,
2332	PRECEQU_PH_QBR_MM = 2317,	2332	PRECEQU_PH_QBR_MM = 2317,
2333	PRECEQ_W_PHL = 2318,	2333	PRECEQ_W_PHL = 2318,
2334	PRECEQ_W_PHL_MM = 2319,	2334	PRECEQ_W_PHL_MM = 2319,
2335	PRECEQ_W_PHR = 2320,	2335	PRECEQ_W_PHR = 2320,
2336	PRECEQ_W_PHR_MM = 2321,	2336	PRECEQ_W_PHR_MM = 2321,
2337	PRECEU_PH_QBL = 2322,	2337	PRECEU_PH_QBL = 2322,
2338	PRECEU_PH_QBLA = 2323,	2338	PRECEU_PH_QBLA = 2323,
2339	PRECEU_PH_QBLA_MM = 2324,	2339	PRECEU_PH_QBLA_MM = 2324,
2340	PRECEU_PH_QBL_MM = 2325,	2340	PRECEU_PH_QBL_MM = 2325,
2341	PRECEU_PH_QBR = 2326,	2341	PRECEU_PH_QBR = 2326,
2342	PRECEU_PH_QBRA = 2327,	2342	PRECEU_PH_QBRA = 2327,
2343	PRECEU_PH_QBRA_MM = 2328,	2343	PRECEU_PH_QBRA_MM = 2328,
2344	PRECEU_PH_QBR_MM = 2329,	2344	PRECEU_PH_QBR_MM = 2329,
2345	PRECRQU_S_QB_PH = 2330,	2345	PRECRQU_S_QB_PH = 2330,
2346	PRECRQU_S_QB_PH_MM = 2331,	2346	PRECRQU_S_QB_PH_MM = 2331,
2347	PRECRQ_PH_W = 2332,	2347	PRECRQ_PH_W = 2332,
2348	PRECRQ_PH_W_MM = 2333,	2348	PRECRQ_PH_W_MM = 2333,
2349	PRECRQ_QB_PH = 2334,	2349	PRECRQ_QB_PH = 2334,
2350	PRECRQ_QB_PH_MM = 2335,	2350	PRECRQ_QB_PH_MM = 2335,
2351	PRECRQ_RS_PH_W = 2336,	2351	PRECRQ_RS_PH_W = 2336,
2352	PRECRQ_RS_PH_W_MM = 2337,	2352	PRECRQ_RS_PH_W_MM = 2337,
2353	PRECR_QB_PH = 2338,	2353	PRECR_QB_PH = 2338,
2354	PRECR_QB_PH_MMR2 = 2339,	2354	PRECR_QB_PH_MMR2 = 2339,
2355	PRECR_SRA_PH_W = 2340,	2355	PRECR_SRA_PH_W = 2340,
2356	PRECR_SRA_PH_W_MMR2 = 2341,	2356	PRECR_SRA_PH_W_MMR2 = 2341,
2357	PRECR_SRA_R_PH_W = 2342,	2357	PRECR_SRA_R_PH_W = 2342,
2358	PRECR_SRA_R_PH_W_MMR2 = 2343,	2358	PRECR_SRA_R_PH_W_MMR2 = 2343,
2359	PREF = 2344,	2359	PREF = 2344,
2360	PREFE = 2345,	2360	PREFE = 2345,
2361	PREFE_MM = 2346,	2361	PREFE_MM = 2346,
2362	PREFX_MM = 2347,	2362	PREFX_MM = 2347,
2363	PREF_MM = 2348,	2363	PREF_MM = 2348,
2364	PREF_MMR6 = 2349,	2364	PREF_MMR6 = 2349,
2365	PREF_R6 = 2350,	2365	PREF_R6 = 2350,
2366	PREPEND = 2351,	2366	PREPEND = 2351,
2367	PREPEND_MMR2 = 2352,	2367	PREPEND_MMR2 = 2352,
2368	PUL_PS64 = 2353,	2368	PUL_PS64 = 2353,
2369	PUU_PS64 = 2354,	2369	PUU_PS64 = 2354,
2370	RADDU_W_QB = 2355,	2370	RADDU_W_QB = 2355,
2371	RADDU_W_QB_MM = 2356,	2371	RADDU_W_QB_MM = 2356,
2372	RDDSP = 2357,	2372	RDDSP = 2357,
2373	RDDSP_MM = 2358,	2373	RDDSP_MM = 2358,
2374	RDHWR = 2359,	2374	RDHWR = 2359,
2375	RDHWR64 = 2360,	2375	RDHWR64 = 2360,
2376	RDHWR_MM = 2361,	2376	RDHWR_MM = 2361,
2377	RDHWR_MMR6 = 2362,	2377	RDHWR_MMR6 = 2362,
2378	RDPGPR_MMR6 = 2363,	2378	RDPGPR_MMR6 = 2363,
2379	RECIP_D32 = 2364,	2379	RECIP_D32 = 2364,
2380	RECIP_D32_MM = 2365,	2380	RECIP_D32_MM = 2365,
2381	RECIP_D64 = 2366,	2381	RECIP_D64 = 2366,
2382	RECIP_D64_MM = 2367,	2382	RECIP_D64_MM = 2367,
2383	RECIP_S = 2368,	2383	RECIP_S = 2368,
2384	RECIP_S_MM = 2369,	2384	RECIP_S_MM = 2369,
2385	REPLV_PH = 2370,	2385	REPLV_PH = 2370,
2386	REPLV_PH_MM = 2371,	2386	REPLV_PH_MM = 2371,
2387	REPLV_QB = 2372,	2387	REPLV_QB = 2372,
2388	REPLV_QB_MM = 2373,	2388	REPLV_QB_MM = 2373,
2389	REPL_PH = 2374,	2389	REPL_PH = 2374,
2390	REPL_PH_MM = 2375,	2390	REPL_PH_MM = 2375,
2391	REPL_QB = 2376,	2391	REPL_QB = 2376,
2392	REPL_QB_MM = 2377,	2392	REPL_QB_MM = 2377,
2393	RINT_D = 2378,	2393	RINT_D = 2378,
2394	RINT_D_MMR6 = 2379,	2394	RINT_D_MMR6 = 2379,
2395	RINT_S = 2380,	2395	RINT_S = 2380,
2396	RINT_S_MMR6 = 2381,	2396	RINT_S_MMR6 = 2381,
2397	ROTR = 2382,	2397	ROTR = 2382,
2398	ROTRV = 2383,	2398	ROTRV = 2383,
2399	ROTRV_MM = 2384,	2399	ROTRV_MM = 2384,
2400	ROTR_MM = 2385,	2400	ROTR_MM = 2385,
2401	ROUND_L_D64 = 2386,	2401	ROUND_L_D64 = 2386,
2402	ROUND_L_D_MMR6 = 2387,	2402	ROUND_L_D_MMR6 = 2387,
2403	ROUND_L_S = 2388,	2403	ROUND_L_S = 2388,
2404	ROUND_L_S_MMR6 = 2389,	2404	ROUND_L_S_MMR6 = 2389,
2405	ROUND_W_D32 = 2390,	2405	ROUND_W_D32 = 2390,
2406	ROUND_W_D64 = 2391,	2406	ROUND_W_D64 = 2391,
2407	ROUND_W_D_MMR6 = 2392,	2407	ROUND_W_D_MMR6 = 2392,
2408	ROUND_W_MM = 2393,	2408	ROUND_W_MM = 2393,
2409	ROUND_W_S = 2394,	2409	ROUND_W_S = 2394,
2410	ROUND_W_S_MM = 2395,	2410	ROUND_W_S_MM = 2395,
2411	ROUND_W_S_MMR6 = 2396,	2411	ROUND_W_S_MMR6 = 2396,
2412	RSQRT_D32 = 2397,	2412	RSQRT_D32 = 2397,
2413	RSQRT_D32_MM = 2398,	2413	RSQRT_D32_MM = 2398,
2414	RSQRT_D64 = 2399,	2414	RSQRT_D64 = 2399,
2415	RSQRT_D64_MM = 2400,	2415	RSQRT_D64_MM = 2400,
2416	RSQRT_S = 2401,	2416	RSQRT_S = 2401,
2417	RSQRT_S_MM = 2402,	2417	RSQRT_S_MM = 2402,
2418	Restore16 = 2403,	2418	Restore16 = 2403,
2419	RestoreX16 = 2404,	2419	RestoreX16 = 2404,
2420	SAA = 2405,	2420	SAA = 2405,
2421	SAAD = 2406,	2421	SAAD = 2406,
2422	SAT_S_B = 2407,	2422	SAT_S_B = 2407,
2423	SAT_S_D = 2408,	2423	SAT_S_D = 2408,
2424	SAT_S_H = 2409,	2424	SAT_S_H = 2409,
2425	SAT_S_W = 2410,	2425	SAT_S_W = 2410,
2426	SAT_U_B = 2411,	2426	SAT_U_B = 2411,
2427	SAT_U_D = 2412,	2427	SAT_U_D = 2412,
2428	SAT_U_H = 2413,	2428	SAT_U_H = 2413,
2429	SAT_U_W = 2414,	2429	SAT_U_W = 2414,
2430	SB = 2415,	2430	SB = 2415,
2431	SB16_MM = 2416,	2431	SB16_MM = 2416,
2432	SB16_MMR6 = 2417,	2432	SB16_MMR6 = 2417,
2433	SB64 = 2418,	2433	SB64 = 2418,
2434	SBE = 2419,	2434	SBE = 2419,
2435	SBE_MM = 2420,	2435	SBE_MM = 2420,
2436	SB_MM = 2421,	2436	SB_MM = 2421,
2437	SB_MMR6 = 2422,	2437	SB_MMR6 = 2422,
2438	SC = 2423,	2438	SC = 2423,
2439	SC64 = 2424,	2439	SC64 = 2424,
2440	SC64_R6 = 2425,	2440	SC64_R6 = 2425,
2441	SCD = 2426,	2441	SCD = 2426,
2442	SCD_R6 = 2427,	2442	SCD_R6 = 2427,
2443	SCE = 2428,	2443	SCE = 2428,
2444	SCE_MM = 2429,	2444	SCE_MM = 2429,
2445	SC_MM = 2430,	2445	SC_MM = 2430,
2446	SC_MMR6 = 2431,	2446	SC_MMR6 = 2431,
2447	SC_R6 = 2432,	2447	SC_R6 = 2432,
2448	SD = 2433,	2448	SD = 2433,
2449	SDBBP = 2434,	2449	SDBBP = 2434,
2450	SDBBP16_MM = 2435,	2450	SDBBP16_MM = 2435,
2451	SDBBP16_MMR6 = 2436,	2451	SDBBP16_MMR6 = 2436,
2452	SDBBP_MM = 2437,	2452	SDBBP_MM = 2437,
2453	SDBBP_MMR6 = 2438,	2453	SDBBP_MMR6 = 2438,
2454	SDBBP_R6 = 2439,	2454	SDBBP_R6 = 2439,
2455	SDC1 = 2440,	2455	SDC1 = 2440,
2456	SDC164 = 2441,	2456	SDC164 = 2441,
2457	SDC1_D64_MMR6 = 2442,	2457	SDC1_D64_MMR6 = 2442,
2458	SDC1_MM_D32 = 2443,	2458	SDC1_MM_D32 = 2443,
2459	SDC1_MM_D64 = 2444,	2459	SDC1_MM_D64 = 2444,
2460	SDC2 = 2445,	2460	SDC2 = 2445,
2461	SDC2_MMR6 = 2446,	2461	SDC2_MMR6 = 2446,
2462	SDC2_R6 = 2447,	2462	SDC2_R6 = 2447,
2463	SDC3 = 2448,	2463	SDC3 = 2448,
2464	SDIV = 2449,	2464	SDIV = 2449,
2465	SDIV_MM = 2450,	2465	SDIV_MM = 2450,
2466	SDL = 2451,	2466	SDL = 2451,
2467	SDR = 2452,	2467	SDR = 2452,
2468	SDXC1 = 2453,	2468	SDXC1 = 2453,
2469	SDXC164 = 2454,	2469	SDXC164 = 2454,
2470	SEB = 2455,	2470	SEB = 2455,
2471	SEB64 = 2456,	2471	SEB64 = 2456,
2472	SEB_MM = 2457,	2472	SEB_MM = 2457,
2473	SEH = 2458,	2473	SEH = 2458,
2474	SEH64 = 2459,	2474	SEH64 = 2459,
2475	SEH_MM = 2460,	2475	SEH_MM = 2460,
2476	SELEQZ = 2461,	2476	SELEQZ = 2461,
2477	SELEQZ64 = 2462,	2477	SELEQZ64 = 2462,
2478	SELEQZ_D = 2463,	2478	SELEQZ_D = 2463,
2479	SELEQZ_D_MMR6 = 2464,	2479	SELEQZ_D_MMR6 = 2464,
2480	SELEQZ_MMR6 = 2465,	2480	SELEQZ_MMR6 = 2465,
2481	SELEQZ_S = 2466,	2481	SELEQZ_S = 2466,
2482	SELEQZ_S_MMR6 = 2467,	2482	SELEQZ_S_MMR6 = 2467,
2483	SELNEZ = 2468,	2483	SELNEZ = 2468,
2484	SELNEZ64 = 2469,	2484	SELNEZ64 = 2469,
2485	SELNEZ_D = 2470,	2485	SELNEZ_D = 2470,
2486	SELNEZ_D_MMR6 = 2471,	2486	SELNEZ_D_MMR6 = 2471,
2487	SELNEZ_MMR6 = 2472,	2487	SELNEZ_MMR6 = 2472,
2488	SELNEZ_S = 2473,	2488	SELNEZ_S = 2473,
2489	SELNEZ_S_MMR6 = 2474,	2489	SELNEZ_S_MMR6 = 2474,
2490	SEL_D = 2475,	2490	SEL_D = 2475,
2491	SEL_D_MMR6 = 2476,	2491	SEL_D_MMR6 = 2476,
2492	SEL_S = 2477,	2492	SEL_S = 2477,
2493	SEL_S_MMR6 = 2478,	2493	SEL_S_MMR6 = 2478,
2494	SEQ = 2479,	2494	SEQ = 2479,
2495	SEQi = 2480,	2495	SEQi = 2480,
2496	SH = 2481,	2496	SH = 2481,
2497	SH16_MM = 2482,	2497	SH16_MM = 2482,
2498	SH16_MMR6 = 2483,	2498	SH16_MMR6 = 2483,
2499	SH64 = 2484,	2499	SH64 = 2484,
2500	SHE = 2485,	2500	SHE = 2485,
2501	SHE_MM = 2486,	2501	SHE_MM = 2486,
2502	SHF_B = 2487,	2502	SHF_B = 2487,
2503	SHF_H = 2488,	2503	SHF_H = 2488,
2504	SHF_W = 2489,	2504	SHF_W = 2489,
2505	SHILO = 2490,	2505	SHILO = 2490,
2506	SHILOV = 2491,	2506	SHILOV = 2491,
2507	SHILOV_MM = 2492,	2507	SHILOV_MM = 2492,
2508	SHILO_MM = 2493,	2508	SHILO_MM = 2493,
2509	SHLLV_PH = 2494,	2509	SHLLV_PH = 2494,
2510	SHLLV_PH_MM = 2495,	2510	SHLLV_PH_MM = 2495,
2511	SHLLV_QB = 2496,	2511	SHLLV_QB = 2496,
2512	SHLLV_QB_MM = 2497,	2512	SHLLV_QB_MM = 2497,
2513	SHLLV_S_PH = 2498,	2513	SHLLV_S_PH = 2498,
2514	SHLLV_S_PH_MM = 2499,	2514	SHLLV_S_PH_MM = 2499,
2515	SHLLV_S_W = 2500,	2515	SHLLV_S_W = 2500,
2516	SHLLV_S_W_MM = 2501,	2516	SHLLV_S_W_MM = 2501,
2517	SHLL_PH = 2502,	2517	SHLL_PH = 2502,
2518	SHLL_PH_MM = 2503,	2518	SHLL_PH_MM = 2503,
2519	SHLL_QB = 2504,	2519	SHLL_QB = 2504,
2520	SHLL_QB_MM = 2505,	2520	SHLL_QB_MM = 2505,
2521	SHLL_S_PH = 2506,	2521	SHLL_S_PH = 2506,
2522	SHLL_S_PH_MM = 2507,	2522	SHLL_S_PH_MM = 2507,
2523	SHLL_S_W = 2508,	2523	SHLL_S_W = 2508,
2524	SHLL_S_W_MM = 2509,	2524	SHLL_S_W_MM = 2509,
2525	SHRAV_PH = 2510,	2525	SHRAV_PH = 2510,
2526	SHRAV_PH_MM = 2511,	2526	SHRAV_PH_MM = 2511,
2527	SHRAV_QB = 2512,	2527	SHRAV_QB = 2512,
2528	SHRAV_QB_MMR2 = 2513,	2528	SHRAV_QB_MMR2 = 2513,
2529	SHRAV_R_PH = 2514,	2529	SHRAV_R_PH = 2514,
2530	SHRAV_R_PH_MM = 2515,	2530	SHRAV_R_PH_MM = 2515,
2531	SHRAV_R_QB = 2516,	2531	SHRAV_R_QB = 2516,
2532	SHRAV_R_QB_MMR2 = 2517,	2532	SHRAV_R_QB_MMR2 = 2517,
2533	SHRAV_R_W = 2518,	2533	SHRAV_R_W = 2518,
2534	SHRAV_R_W_MM = 2519,	2534	SHRAV_R_W_MM = 2519,
2535	SHRA_PH = 2520,	2535	SHRA_PH = 2520,
2536	SHRA_PH_MM = 2521,	2536	SHRA_PH_MM = 2521,
2537	SHRA_QB = 2522,	2537	SHRA_QB = 2522,
2538	SHRA_QB_MMR2 = 2523,	2538	SHRA_QB_MMR2 = 2523,
2539	SHRA_R_PH = 2524,	2539	SHRA_R_PH = 2524,
2540	SHRA_R_PH_MM = 2525,	2540	SHRA_R_PH_MM = 2525,
2541	SHRA_R_QB = 2526,	2541	SHRA_R_QB = 2526,
2542	SHRA_R_QB_MMR2 = 2527,	2542	SHRA_R_QB_MMR2 = 2527,
2543	SHRA_R_W = 2528,	2543	SHRA_R_W = 2528,
2544	SHRA_R_W_MM = 2529,	2544	SHRA_R_W_MM = 2529,
2545	SHRLV_PH = 2530,	2545	SHRLV_PH = 2530,
2546	SHRLV_PH_MMR2 = 2531,	2546	SHRLV_PH_MMR2 = 2531,
2547	SHRLV_QB = 2532,	2547	SHRLV_QB = 2532,
2548	SHRLV_QB_MM = 2533,	2548	SHRLV_QB_MM = 2533,
2549	SHRL_PH = 2534,	2549	SHRL_PH = 2534,
2550	SHRL_PH_MMR2 = 2535,	2550	SHRL_PH_MMR2 = 2535,
2551	SHRL_QB = 2536,	2551	SHRL_QB = 2536,
2552	SHRL_QB_MM = 2537,	2552	SHRL_QB_MM = 2537,
2553	SH_MM = 2538,	2553	SH_MM = 2538,
2554	SH_MMR6 = 2539,	2554	SH_MMR6 = 2539,
2555	SIGRIE = 2540,	2555	SIGRIE = 2540,
2556	SIGRIE_MMR6 = 2541,	2556	SIGRIE_MMR6 = 2541,
2557	SLDI_B = 2542,	2557	SLDI_B = 2542,
2558	SLDI_D = 2543,	2558	SLDI_D = 2543,
2559	SLDI_H = 2544,	2559	SLDI_H = 2544,
2560	SLDI_W = 2545,	2560	SLDI_W = 2545,
2561	SLD_B = 2546,	2561	SLD_B = 2546,
2562	SLD_D = 2547,	2562	SLD_D = 2547,
2563	SLD_H = 2548,	2563	SLD_H = 2548,
2564	SLD_W = 2549,	2564	SLD_W = 2549,
2565	SLL = 2550,	2565	SLL = 2550,
2566	SLL16_MM = 2551,	2566	SLL16_MM = 2551,
2567	SLL16_MMR6 = 2552,	2567	SLL16_MMR6 = 2552,
2568	SLL64_32 = 2553,	2568	SLL64_32 = 2553,
2569	SLL64_64 = 2554,	2569	SLL64_64 = 2554,
2570	SLLI_B = 2555,	2570	SLLI_B = 2555,
2571	SLLI_D = 2556,	2571	SLLI_D = 2556,
2572	SLLI_H = 2557,	2572	SLLI_H = 2557,
2573	SLLI_W = 2558,	2573	SLLI_W = 2558,
2574	SLLV = 2559,	2574	SLLV = 2559,
2575	SLLV_MM = 2560,	2575	SLLV_MM = 2560,
2576	SLL_B = 2561,	2576	SLL_B = 2561,
2577	SLL_D = 2562,	2577	SLL_D = 2562,
2578	SLL_H = 2563,	2578	SLL_H = 2563,
2579	SLL_MM = 2564,	2579	SLL_MM = 2564,
2580	SLL_MMR6 = 2565,	2580	SLL_MMR6 = 2565,
2581	SLL_W = 2566,	2581	SLL_W = 2566,
2582	SLT = 2567,	2582	SLT = 2567,
2583	SLT64 = 2568,	2583	SLT64 = 2568,
2584	SLT_MM = 2569,	2584	SLT_MM = 2569,
2585	SLTi = 2570,	2585	SLTi = 2570,
2586	SLTi64 = 2571,	2586	SLTi64 = 2571,
2587	SLTi_MM = 2572,	2587	SLTi_MM = 2572,
2588	SLTiu = 2573,	2588	SLTiu = 2573,
2589	SLTiu64 = 2574,	2589	SLTiu64 = 2574,
2590	SLTiu_MM = 2575,	2590	SLTiu_MM = 2575,
2591	SLTu = 2576,	2591	SLTu = 2576,
2592	SLTu64 = 2577,	2592	SLTu64 = 2577,
2593	SLTu_MM = 2578,	2593	SLTu_MM = 2578,
2594	SNE = 2579,	2594	SNE = 2579,
2595	SNEi = 2580,	2595	SNEi = 2580,
2596	SPLATI_B = 2581,	2596	SPLATI_B = 2581,
2597	SPLATI_D = 2582,	2597	SPLATI_D = 2582,
2598	SPLATI_H = 2583,	2598	SPLATI_H = 2583,
2599	SPLATI_W = 2584,	2599	SPLATI_W = 2584,
2600	SPLAT_B = 2585,	2600	SPLAT_B = 2585,
2601	SPLAT_D = 2586,	2601	SPLAT_D = 2586,
2602	SPLAT_H = 2587,	2602	SPLAT_H = 2587,
2603	SPLAT_W = 2588,	2603	SPLAT_W = 2588,
2604	SRA = 2589,	2604	SRA = 2589,
2605	SRAI_B = 2590,	2605	SRAI_B = 2590,
2606	SRAI_D = 2591,	2606	SRAI_D = 2591,
2607	SRAI_H = 2592,	2607	SRAI_H = 2592,
2608	SRAI_W = 2593,	2608	SRAI_W = 2593,
2609	SRARI_B = 2594,	2609	SRARI_B = 2594,
2610	SRARI_D = 2595,	2610	SRARI_D = 2595,
2611	SRARI_H = 2596,	2611	SRARI_H = 2596,
2612	SRARI_W = 2597,	2612	SRARI_W = 2597,
2613	SRAR_B = 2598,	2613	SRAR_B = 2598,
2614	SRAR_D = 2599,	2614	SRAR_D = 2599,
2615	SRAR_H = 2600,	2615	SRAR_H = 2600,
2616	SRAR_W = 2601,	2616	SRAR_W = 2601,
2617	SRAV = 2602,	2617	SRAV = 2602,
2618	SRAV_MM = 2603,	2618	SRAV_MM = 2603,
2619	SRA_B = 2604,	2619	SRA_B = 2604,
2620	SRA_D = 2605,	2620	SRA_D = 2605,
2621	SRA_H = 2606,	2621	SRA_H = 2606,
2622	SRA_MM = 2607,	2622	SRA_MM = 2607,
2623	SRA_W = 2608,	2623	SRA_W = 2608,
2624	SRL = 2609,	2624	SRL = 2609,
2625	SRL16_MM = 2610,	2625	SRL16_MM = 2610,
2626	SRL16_MMR6 = 2611,	2626	SRL16_MMR6 = 2611,
2627	SRLI_B = 2612,	2627	SRLI_B = 2612,
2628	SRLI_D = 2613,	2628	SRLI_D = 2613,
2629	SRLI_H = 2614,	2629	SRLI_H = 2614,
2630	SRLI_W = 2615,	2630	SRLI_W = 2615,
2631	SRLRI_B = 2616,	2631	SRLRI_B = 2616,
2632	SRLRI_D = 2617,	2632	SRLRI_D = 2617,
2633	SRLRI_H = 2618,	2633	SRLRI_H = 2618,
2634	SRLRI_W = 2619,	2634	SRLRI_W = 2619,
2635	SRLR_B = 2620,	2635	SRLR_B = 2620,
2636	SRLR_D = 2621,	2636	SRLR_D = 2621,
2637	SRLR_H = 2622,	2637	SRLR_H = 2622,
2638	SRLR_W = 2623,	2638	SRLR_W = 2623,
2639	SRLV = 2624,	2639	SRLV = 2624,
2640	SRLV_MM = 2625,	2640	SRLV_MM = 2625,
2641	SRL_B = 2626,	2641	SRL_B = 2626,
2642	SRL_D = 2627,	2642	SRL_D = 2627,
2643	SRL_H = 2628,	2643	SRL_H = 2628,
2644	SRL_MM = 2629,	2644	SRL_MM = 2629,
2645	SRL_W = 2630,	2645	SRL_W = 2630,
2646	SSNOP = 2631,	2646	SSNOP = 2631,
2647	SSNOP_MM = 2632,	2647	SSNOP_MM = 2632,
2648	SSNOP_MMR6 = 2633,	2648	SSNOP_MMR6 = 2633,
2649	ST_B = 2634,	2649	ST_B = 2634,
2650	ST_D = 2635,	2650	ST_D = 2635,
2651	ST_H = 2636,	2651	ST_H = 2636,
2652	ST_W = 2637,	2652	ST_W = 2637,
2653	SUB = 2638,	2653	SUB = 2638,
2654	SUBQH_PH = 2639,	2654	SUBQH_PH = 2639,
2655	SUBQH_PH_MMR2 = 2640,	2655	SUBQH_PH_MMR2 = 2640,
2656	SUBQH_R_PH = 2641,	2656	SUBQH_R_PH = 2641,
2657	SUBQH_R_PH_MMR2 = 2642,	2657	SUBQH_R_PH_MMR2 = 2642,
2658	SUBQH_R_W = 2643,	2658	SUBQH_R_W = 2643,
2659	SUBQH_R_W_MMR2 = 2644,	2659	SUBQH_R_W_MMR2 = 2644,
2660	SUBQH_W = 2645,	2660	SUBQH_W = 2645,
2661	SUBQH_W_MMR2 = 2646,	2661	SUBQH_W_MMR2 = 2646,
2662	SUBQ_PH = 2647,	2662	SUBQ_PH = 2647,
2663	SUBQ_PH_MM = 2648,	2663	SUBQ_PH_MM = 2648,
2664	SUBQ_S_PH = 2649,	2664	SUBQ_S_PH = 2649,
2665	SUBQ_S_PH_MM = 2650,	2665	SUBQ_S_PH_MM = 2650,
2666	SUBQ_S_W = 2651,	2666	SUBQ_S_W = 2651,
2667	SUBQ_S_W_MM = 2652,	2667	SUBQ_S_W_MM = 2652,
2668	SUBSUS_U_B = 2653,	2668	SUBSUS_U_B = 2653,
2669	SUBSUS_U_D = 2654,	2669	SUBSUS_U_D = 2654,
2670	SUBSUS_U_H = 2655,	2670	SUBSUS_U_H = 2655,
2671	SUBSUS_U_W = 2656,	2671	SUBSUS_U_W = 2656,
2672	SUBSUU_S_B = 2657,	2672	SUBSUU_S_B = 2657,
2673	SUBSUU_S_D = 2658,	2673	SUBSUU_S_D = 2658,
2674	SUBSUU_S_H = 2659,	2674	SUBSUU_S_H = 2659,
2675	SUBSUU_S_W = 2660,	2675	SUBSUU_S_W = 2660,
2676	SUBS_S_B = 2661,	2676	SUBS_S_B = 2661,
2677	SUBS_S_D = 2662,	2677	SUBS_S_D = 2662,
2678	SUBS_S_H = 2663,	2678	SUBS_S_H = 2663,
2679	SUBS_S_W = 2664,	2679	SUBS_S_W = 2664,
2680	SUBS_U_B = 2665,	2680	SUBS_U_B = 2665,
2681	SUBS_U_D = 2666,	2681	SUBS_U_D = 2666,
2682	SUBS_U_H = 2667,	2682	SUBS_U_H = 2667,
2683	SUBS_U_W = 2668,	2683	SUBS_U_W = 2668,
2684	SUBU16_MM = 2669,	2684	SUBU16_MM = 2669,
2685	SUBU16_MMR6 = 2670,	2685	SUBU16_MMR6 = 2670,
2686	SUBUH_QB = 2671,	2686	SUBUH_QB = 2671,
2687	SUBUH_QB_MMR2 = 2672,	2687	SUBUH_QB_MMR2 = 2672,
2688	SUBUH_R_QB = 2673,	2688	SUBUH_R_QB = 2673,
2689	SUBUH_R_QB_MMR2 = 2674,	2689	SUBUH_R_QB_MMR2 = 2674,
2690	SUBU_MMR6 = 2675,	2690	SUBU_MMR6 = 2675,
2691	SUBU_PH = 2676,	2691	SUBU_PH = 2676,
2692	SUBU_PH_MMR2 = 2677,	2692	SUBU_PH_MMR2 = 2677,
2693	SUBU_QB = 2678,	2693	SUBU_QB = 2678,
2694	SUBU_QB_MM = 2679,	2694	SUBU_QB_MM = 2679,
2695	SUBU_S_PH = 2680,	2695	SUBU_S_PH = 2680,
2696	SUBU_S_PH_MMR2 = 2681,	2696	SUBU_S_PH_MMR2 = 2681,
2697	SUBU_S_QB = 2682,	2697	SUBU_S_QB = 2682,
2698	SUBU_S_QB_MM = 2683,	2698	SUBU_S_QB_MM = 2683,
2699	SUBVI_B = 2684,	2699	SUBVI_B = 2684,
2700	SUBVI_D = 2685,	2700	SUBVI_D = 2685,
2701	SUBVI_H = 2686,	2701	SUBVI_H = 2686,
2702	SUBVI_W = 2687,	2702	SUBVI_W = 2687,
2703	SUBV_B = 2688,	2703	SUBV_B = 2688,
2704	SUBV_D = 2689,	2704	SUBV_D = 2689,
2705	SUBV_H = 2690,	2705	SUBV_H = 2690,
2706	SUBV_W = 2691,	2706	SUBV_W = 2691,
2707	SUB_MM = 2692,	2707	SUB_MM = 2692,
2708	SUB_MMR6 = 2693,	2708	SUB_MMR6 = 2693,
2709	SUBu = 2694,	2709	SUBu = 2694,
2710	SUBu_MM = 2695,	2710	SUBu_MM = 2695,
2711	SUXC1 = 2696,	2711	SUXC1 = 2696,
2712	SUXC164 = 2697,	2712	SUXC164 = 2697,
2713	SUXC1_MM = 2698,	2713	SUXC1_MM = 2698,
2714	SW = 2699,	2714	SW = 2699,
2715	SW16_MM = 2700,	2715	SW16_MM = 2700,
2716	SW16_MMR6 = 2701,	2716	SW16_MMR6 = 2701,
2717	SW64 = 2702,	2717	SW64 = 2702,
2718	SWC1 = 2703,	2718	SWC1 = 2703,
2719	SWC1_MM = 2704,	2719	SWC1_MM = 2704,
2720	SWC2 = 2705,	2720	SWC2 = 2705,
2721	SWC2_MMR6 = 2706,	2721	SWC2_MMR6 = 2706,
2722	SWC2_R6 = 2707,	2722	SWC2_R6 = 2707,
2723	SWC3 = 2708,	2723	SWC3 = 2708,
2724	SWDSP = 2709,	2724	SWDSP = 2709,
2725	SWDSP_MM = 2710,	2725	SWDSP_MM = 2710,
2726	SWE = 2711,	2726	SWE = 2711,
2727	SWE_MM = 2712,	2727	SWE_MM = 2712,
2728	SWL = 2713,	2728	SWL = 2713,
2729	SWL64 = 2714,	2729	SWL64 = 2714,
2730	SWLE = 2715,	2730	SWLE = 2715,
2731	SWLE_MM = 2716,	2731	SWLE_MM = 2716,
2732	SWL_MM = 2717,	2732	SWL_MM = 2717,
2733	SWM16_MM = 2718,	2733	SWM16_MM = 2718,
2734	SWM16_MMR6 = 2719,	2734	SWM16_MMR6 = 2719,
2735	SWM32_MM = 2720,	2735	SWM32_MM = 2720,
2736	SWP_MM = 2721,	2736	SWP_MM = 2721,
2737	SWR = 2722,	2737	SWR = 2722,
2738	SWR64 = 2723,	2738	SWR64 = 2723,
2739	SWRE = 2724,	2739	SWRE = 2724,
2740	SWRE_MM = 2725,	2740	SWRE_MM = 2725,
2741	SWR_MM = 2726,	2741	SWR_MM = 2726,
2742	SWSP_MM = 2727,	2742	SWSP_MM = 2727,
2743	SWSP_MMR6 = 2728,	2743	SWSP_MMR6 = 2728,
2744	SWXC1 = 2729,	2744	SWXC1 = 2729,
2745	SWXC1_MM = 2730,	2745	SWXC1_MM = 2730,
2746	SW_MM = 2731,	2746	SW_MM = 2731,
2747	SW_MMR6 = 2732,	2747	SW_MMR6 = 2732,
2748	SYNC = 2733,	2748	SYNC = 2733,
2749	SYNCI = 2734,	2749	SYNCI = 2734,
2750	SYNCI_MM = 2735,	2750	SYNCI_MM = 2735,
2751	SYNCI_MMR6 = 2736,	2751	SYNCI_MMR6 = 2736,
2752	SYNC_MM = 2737,	2752	SYNC_MM = 2737,
2753	SYNC_MMR6 = 2738,	2753	SYNC_MMR6 = 2738,
2754	SYSCALL = 2739,	2754	SYSCALL = 2739,
2755	SYSCALL_MM = 2740,	2755	SYSCALL_MM = 2740,
2756	Save16 = 2741,	2756	Save16 = 2741,
2757	SaveX16 = 2742,	2757	SaveX16 = 2742,
2758	SbRxRyOffMemX16 = 2743,	2758	SbRxRyOffMemX16 = 2743,
2759	SebRx16 = 2744,	2759	SebRx16 = 2744,
2760	SehRx16 = 2745,	2760	SehRx16 = 2745,
2761	ShRxRyOffMemX16 = 2746,	2761	ShRxRyOffMemX16 = 2746,
2762	SllX16 = 2747,	2762	SllX16 = 2747,
2763	SllvRxRy16 = 2748,	2763	SllvRxRy16 = 2748,
2764	SltRxRy16 = 2749,	2764	SltRxRy16 = 2749,
2765	SltiRxImm16 = 2750,	2765	SltiRxImm16 = 2750,
2766	SltiRxImmX16 = 2751,	2766	SltiRxImmX16 = 2751,
2767	SltiuRxImm16 = 2752,	2767	SltiuRxImm16 = 2752,
2768	SltiuRxImmX16 = 2753,	2768	SltiuRxImmX16 = 2753,
2769	SltuRxRy16 = 2754,	2769	SltuRxRy16 = 2754,
2770	SraX16 = 2755,	2770	SraX16 = 2755,
2771	SravRxRy16 = 2756,	2771	SravRxRy16 = 2756,
2772	SrlX16 = 2757,	2772	SrlX16 = 2757,
2773	SrlvRxRy16 = 2758,	2773	SrlvRxRy16 = 2758,
2774	SubuRxRyRz16 = 2759,	2774	SubuRxRyRz16 = 2759,
2775	SwRxRyOffMemX16 = 2760,	2775	SwRxRyOffMemX16 = 2760,
2776	SwRxSpImmX16 = 2761,	2776	SwRxSpImmX16 = 2761,
2777	TEQ = 2762,	2777	TEQ = 2762,
2778	TEQI = 2763,	2778	TEQI = 2763,
2779	TEQI_MM = 2764,	2779	TEQI_MM = 2764,
2780	TEQ_MM = 2765,	2780	TEQ_MM = 2765,
2781	TGE = 2766,	2781	TGE = 2766,
2782	TGEI = 2767,	2782	TGEI = 2767,
2783	TGEIU = 2768,	2783	TGEIU = 2768,
2784	TGEIU_MM = 2769,	2784	TGEIU_MM = 2769,
2785	TGEI_MM = 2770,	2785	TGEI_MM = 2770,
2786	TGEU = 2771,	2786	TGEU = 2771,
2787	TGEU_MM = 2772,	2787	TGEU_MM = 2772,
2788	TGE_MM = 2773,	2788	TGE_MM = 2773,
2789	TLBGINV = 2774,	2789	TLBGINV = 2774,
2790	TLBGINVF = 2775,	2790	TLBGINVF = 2775,
2791	TLBGINVF_MM = 2776,	2791	TLBGINVF_MM = 2776,
2792	TLBGINV_MM = 2777,	2792	TLBGINV_MM = 2777,
2793	TLBGP = 2778,	2793	TLBGP = 2778,
2794	TLBGP_MM = 2779,	2794	TLBGP_MM = 2779,
2795	TLBGR = 2780,	2795	TLBGR = 2780,
2796	TLBGR_MM = 2781,	2796	TLBGR_MM = 2781,
2797	TLBGWI = 2782,	2797	TLBGWI = 2782,
2798	TLBGWI_MM = 2783,	2798	TLBGWI_MM = 2783,
2799	TLBGWR = 2784,	2799	TLBGWR = 2784,
2800	TLBGWR_MM = 2785,	2800	TLBGWR_MM = 2785,
2801	TLBINV = 2786,	2801	TLBINV = 2786,
2802	TLBINVF = 2787,	2802	TLBINVF = 2787,
2803	TLBINVF_MMR6 = 2788,	2803	TLBINVF_MMR6 = 2788,
2804	TLBINV_MMR6 = 2789,	2804	TLBINV_MMR6 = 2789,
2805	TLBP = 2790,	2805	TLBP = 2790,
2806	TLBP_MM = 2791,	2806	TLBP_MM = 2791,
2807	TLBR = 2792,	2807	TLBR = 2792,
2808	TLBR_MM = 2793,	2808	TLBR_MM = 2793,
2809	TLBWI = 2794,	2809	TLBWI = 2794,
2810	TLBWI_MM = 2795,	2810	TLBWI_MM = 2795,
2811	TLBWR = 2796,	2811	TLBWR = 2796,
2812	TLBWR_MM = 2797,	2812	TLBWR_MM = 2797,
2813	TLT = 2798,	2813	TLT = 2798,
2814	TLTI = 2799,	2814	TLTI = 2799,
2815	TLTIU_MM = 2800,	2815	TLTIU_MM = 2800,
2816	TLTI_MM = 2801,	2816	TLTI_MM = 2801,
2817	TLTU = 2802,	2817	TLTU = 2802,
2818	TLTU_MM = 2803,	2818	TLTU_MM = 2803,
2819	TLT_MM = 2804,	2819	TLT_MM = 2804,
2820	TNE = 2805,	2820	TNE = 2805,
2821	TNEI = 2806,	2821	TNEI = 2806,
2822	TNEI_MM = 2807,	2822	TNEI_MM = 2807,
2823	TNE_MM = 2808,	2823	TNE_MM = 2808,
2824	TRUNC_L_D64 = 2809,	2824	TRUNC_L_D64 = 2809,
2825	TRUNC_L_D_MMR6 = 2810,	2825	TRUNC_L_D_MMR6 = 2810,
2826	TRUNC_L_S = 2811,	2826	TRUNC_L_S = 2811,
2827	TRUNC_L_S_MMR6 = 2812,	2827	TRUNC_L_S_MMR6 = 2812,
2828	TRUNC_W_D32 = 2813,	2828	TRUNC_W_D32 = 2813,
2829	TRUNC_W_D64 = 2814,	2829	TRUNC_W_D64 = 2814,
2830	TRUNC_W_D_MMR6 = 2815,	2830	TRUNC_W_D_MMR6 = 2815,
2831	TRUNC_W_MM = 2816,	2831	TRUNC_W_MM = 2816,
2832	TRUNC_W_S = 2817,	2832	TRUNC_W_S = 2817,
2833	TRUNC_W_S_MM = 2818,	2833	TRUNC_W_S_MM = 2818,
2834	TRUNC_W_S_MMR6 = 2819,	2834	TRUNC_W_S_MMR6 = 2819,
2835	TTLTIU = 2820,	2835	TTLTIU = 2820,
2836	UDIV = 2821,	2836	UDIV = 2821,
2837	UDIV_MM = 2822,	2837	UDIV_MM = 2822,
2838	V3MULU = 2823,	2838	V3MULU = 2823,
2839	VMM0 = 2824,	2839	VMM0 = 2824,
2840	VMULU = 2825,	2840	VMULU = 2825,
2841	VSHF_B = 2826,	2841	VSHF_B = 2826,
2842	VSHF_D = 2827,	2842	VSHF_D = 2827,
2843	VSHF_H = 2828,	2843	VSHF_H = 2828,
2844	VSHF_W = 2829,	2844	VSHF_W = 2829,
2845	WAIT = 2830,	2845	WAIT = 2830,
2846	WAIT_MM = 2831,	2846	WAIT_MM = 2831,
2847	WAIT_MMR6 = 2832,	2847	WAIT_MMR6 = 2832,
2848	WRDSP = 2833,	2848	WRDSP = 2833,
2849	WRDSP_MM = 2834,	2849	WRDSP_MM = 2834,
2850	WRPGPR_MMR6 = 2835,	2850	WRPGPR_MMR6 = 2835,
2851	WSBH = 2836,	2851	WSBH = 2836,
2852	WSBH_MM = 2837,	2852	WSBH_MM = 2837,
2853	WSBH_MMR6 = 2838,	2853	WSBH_MMR6 = 2838,
2854	XOR = 2839,	2854	XOR = 2839,
2855	XOR16_MM = 2840,	2855	XOR16_MM = 2840,
2856	XOR16_MMR6 = 2841,	2856	XOR16_MMR6 = 2841,
2857	XOR64 = 2842,	2857	XOR64 = 2842,
2858	XORI_B = 2843,	2858	XORI_B = 2843,
2859	XORI_MMR6 = 2844,	2859	XORI_MMR6 = 2844,
2860	XOR_MM = 2845,	2860	XOR_MM = 2845,
2861	XOR_MMR6 = 2846,	2861	XOR_MMR6 = 2846,
2862	XOR_V = 2847,	2862	XOR_V = 2847,
2863	XORi = 2848,	2863	XORi = 2848,
2864	XORi64 = 2849,	2864	XORi64 = 2849,
2865	XORi_MM = 2850,	2865	XORi_MM = 2850,
2866	XorRxRxRy16 = 2851,	2866	XorRxRxRy16 = 2851,
2867	YIELD = 2852,	2867	YIELD = 2852,
2868	INSTRUCTION_LIST_END = 2853	2868	INSTRUCTION_LIST_END = 2853
2869	};	2869	};
2870		2870
2871	} // end namespace Mips	2871	} // end namespace Mips
2872	} // end namespace llvm	2872	} // end namespace llvm
2873	#endif // GET_INSTRINFO_ENUM	2873	#endif // GET_INSTRINFO_ENUM
2874		2874
2875	#ifdef GET_INSTRINFO_SCHED_ENUM	2875	#ifdef GET_INSTRINFO_SCHED_ENUM
2876	#undef GET_INSTRINFO_SCHED_ENUM	2876	#undef GET_INSTRINFO_SCHED_ENUM
2877	namespace llvm {	2877	namespace llvm {
2878		2878
2879	namespace Mips {	2879	namespace Mips {
2880	namespace Sched {	2880	namespace Sched {
2881	enum {	2881	enum {
2882	NoInstrModel = 0,	2882	NoInstrModel = 0,
2883	IIPseudo = 1,	2883	IIPseudo = 1,
2884	II_B = 2,	2884	II_B = 2,
2885	II_BCCZAL = 3,	2885	II_BCCZAL = 3,
2886	II_MTC1 = 4,	2886	II_MTC1 = 4,
2887	II_MFC1 = 5,	2887	II_MFC1 = 5,
2888	II_JALR = 6,	2888	II_JALR = 6,
2889	II_JAL = 7,	2889	II_JAL = 7,
2890	II_CVT = 8,	2890	II_CVT = 8,
2891	II_DMULT = 9,	2891	II_DMULT = 9,
2892	II_DMULTU = 10,	2892	II_DMULTU = 10,
2893	II_DDIV = 11,	2893	II_DDIV = 11,
2894	II_DDIVU = 12,	2894	II_DDIVU = 12,
2895	II_IndirectBranchPseudo = 13,	2895	II_IndirectBranchPseudo = 13,
2896	II_MADD = 14,	2896	II_MADD = 14,
2897	II_MADDU = 15,	2897	II_MADDU = 15,
2898	II_MFHI_MFLO = 16,	2898	II_MFHI_MFLO = 16,
2899	II_MSUB = 17,	2899	II_MSUB = 17,
2900	II_MSUBU = 18,	2900	II_MSUBU = 18,
2901	II_MTHI_MTLO = 19,	2901	II_MTHI_MTLO = 19,
2902	II_MULT = 20,	2902	II_MULT = 20,
2903	II_MULTU = 21,	2903	II_MULTU = 21,
2904	II_ReturnPseudo = 22,	2904	II_ReturnPseudo = 22,
2905	II_DIV = 23,	2905	II_DIV = 23,
2906	II_DIVU = 24,	2906	II_DIVU = 24,
2907	II_J = 25,	2907	II_J = 25,
2908	II_JR = 26,	2908	II_JR = 26,
2909	II_TRAP = 27,	2909	II_TRAP = 27,
2910	II_ADD = 28,	2910	II_ADD = 28,
2911	II_ADDIUPC = 29,	2911	II_ADDIUPC = 29,
2912	II_ADDIU = 30,	2912	II_ADDIU = 30,
2913	II_ADDR_PS = 31,	2913	II_ADDR_PS = 31,
2914	II_ADDU = 32,	2914	II_ADDU = 32,
2915	II_ADDI = 33,	2915	II_ADDI = 33,
2916	II_ALIGN = 34,	2916	II_ALIGN = 34,
2917	II_ALUIPC = 35,	2917	II_ALUIPC = 35,
2918	II_AND = 36,	2918	II_AND = 36,
2919	II_ANDI = 37,	2919	II_ANDI = 37,
2920	II_AUI = 38,	2920	II_AUI = 38,
2921	II_AUIPC = 39,	2921	II_AUIPC = 39,
2922	IIM16Alu = 40,	2922	IIM16Alu = 40,
2923	II_BADDU = 41,	2923	II_BADDU = 41,
2924	II_BC = 42,	2924	II_BC = 42,
2925	II_BALC = 43,	2925	II_BALC = 43,
2926	II_BBIT = 44,	2926	II_BBIT = 44,
2927	II_BC1CCZ = 45,	2927	II_BC1CCZ = 45,
2928	II_BC1F = 46,	2928	II_BC1F = 46,
2929	II_BC1FL = 47,	2929	II_BC1FL = 47,
2930	II_BC1T = 48,	2930	II_BC1T = 48,
2931	II_BC1TL = 49,	2931	II_BC1TL = 49,
2932	II_BC2CCZ = 50,	2932	II_BC2CCZ = 50,
2933	II_BCC = 51,	2933	II_BCC = 51,
2934	II_BCCC = 52,	2934	II_BCCC = 52,
2935	II_BCCZ = 53,	2935	II_BCCZ = 53,
2936	II_BCCZC = 54,	2936	II_BCCZC = 54,
2937	II_BCCZALS = 55,	2937	II_BCCZALS = 55,
2938	II_BITSWAP = 56,	2938	II_BITSWAP = 56,
2939	II_BREAK = 57,	2939	II_BREAK = 57,
2940	II_CACHE = 58,	2940	II_CACHE = 58,
2941	II_CACHEE = 59,	2941	II_CACHEE = 59,
2942	II_CEIL = 60,	2942	II_CEIL = 60,
2943	II_CFC1 = 61,	2943	II_CFC1 = 61,
2944	II_CFC2 = 62,	2944	II_CFC2 = 62,
2945	II_INS = 63,	2945	II_INS = 63,
2946	II_CLASS_D = 64,	2946	II_CLASS_D = 64,
2947	II_CLASS_S = 65,	2947	II_CLASS_S = 65,
2948	II_CLO = 66,	2948	II_CLO = 66,
2949	II_CLZ = 67,	2949	II_CLZ = 67,
2950	II_CMP_CC_D = 68,	2950	II_CMP_CC_D = 68,
2951	II_CMP_CC_S = 69,	2951	II_CMP_CC_S = 69,
2952	II_CRC32B = 70,	2952	II_CRC32B = 70,
2953	II_CRC32CB = 71,	2953	II_CRC32CB = 71,
2954	II_CRC32CD = 72,	2954	II_CRC32CD = 72,
2955	II_CRC32CH = 73,	2955	II_CRC32CH = 73,
2956	II_CRC32CW = 74,	2956	II_CRC32CW = 74,
2957	II_CRC32D = 75,	2957	II_CRC32D = 75,
2958	II_CRC32H = 76,	2958	II_CRC32H = 76,
2959	II_CRC32W = 77,	2959	II_CRC32W = 77,
2960	II_CTC1 = 78,	2960	II_CTC1 = 78,
2961	II_CTC2 = 79,	2961	II_CTC2 = 79,
2962	II_C_CC_D = 80,	2962	II_C_CC_D = 80,
2963	II_C_CC_S = 81,	2963	II_C_CC_S = 81,
2964	II_DADD = 82,	2964	II_DADD = 82,
2965	II_DADDI = 83,	2965	II_DADDI = 83,
2966	II_DADDIU = 84,	2966	II_DADDIU = 84,
2967	II_DADDU = 85,	2967	II_DADDU = 85,
2968	II_DAHI = 86,	2968	II_DAHI = 86,
2969	II_DALIGN = 87,	2969	II_DALIGN = 87,
2970	II_DATI = 88,	2970	II_DATI = 88,
2971	II_DAUI = 89,	2971	II_DAUI = 89,
2972	II_DBITSWAP = 90,	2972	II_DBITSWAP = 90,
2973	II_DCLO = 91,	2973	II_DCLO = 91,
2974	II_DCLZ = 92,	2974	II_DCLZ = 92,
2975	II_DERET = 93,	2975	II_DERET = 93,
2976	II_EXT = 94,	2976	II_EXT = 94,
2977	II_DI = 95,	2977	II_DI = 95,
2978	II_DLSA = 96,	2978	II_DLSA = 96,
2979	II_DMFC0 = 97,	2979	II_DMFC0 = 97,
2980	II_DMFC1 = 98,	2980	II_DMFC1 = 98,
2981	II_DMFC2 = 99,	2981	II_DMFC2 = 99,
2982	II_DMFGC0 = 100,	2982	II_DMFGC0 = 100,
2983	II_DMOD = 101,	2983	II_DMOD = 101,
2984	II_DMODU = 102,	2984	II_DMODU = 102,
2985	II_DMT = 103,	2985	II_DMT = 103,
2986	II_DMTC0 = 104,	2986	II_DMTC0 = 104,
2987	II_DMTC1 = 105,	2987	II_DMTC1 = 105,
2988	II_DMTC2 = 106,	2988	II_DMTC2 = 106,
2989	II_DMTGC0 = 107,	2989	II_DMTGC0 = 107,
2990	II_DMUH = 108,	2990	II_DMUH = 108,
2991	II_DMUHU = 109,	2991	II_DMUHU = 109,
2992	II_DMUL = 110,	2992	II_DMUL = 110,
2993	II_POP = 111,	2993	II_POP = 111,
2994	II_DROTR = 112,	2994	II_DROTR = 112,
2995	II_DROTR32 = 113,	2995	II_DROTR32 = 113,
2996	II_DROTRV = 114,	2996	II_DROTRV = 114,
2997	II_DSBH = 115,	2997	II_DSBH = 115,
2998	II_DSHD = 116,	2998	II_DSHD = 116,
2999	II_DSLL = 117,	2999	II_DSLL = 117,
3000	II_DSLL32 = 118,	3000	II_DSLL32 = 118,
3001	II_DSLLV = 119,	3001	II_DSLLV = 119,
3002	II_DSRA = 120,	3002	II_DSRA = 120,
3003	II_DSRA32 = 121,	3003	II_DSRA32 = 121,
3004	II_DSRAV = 122,	3004	II_DSRAV = 122,
3005	II_DSRL = 123,	3005	II_DSRL = 123,
3006	II_DSRL32 = 124,	3006	II_DSRL32 = 124,
3007	II_DSRLV = 125,	3007	II_DSRLV = 125,
3008	II_DSUB = 126,	3008	II_DSUB = 126,
3009	II_DSUBU = 127,	3009	II_DSUBU = 127,
3010	II_DVP = 128,	3010	II_DVP = 128,
3011	II_DVPE = 129,	3011	II_DVPE = 129,
3012	II_EHB = 130,	3012	II_EHB = 130,
3013	II_EI = 131,	3013	II_EI = 131,
3014	II_EMT = 132,	3014	II_EMT = 132,
3015	II_ERET = 133,	3015	II_ERET = 133,
3016	II_ERETNC = 134,	3016	II_ERETNC = 134,
3017	II_EVP = 135,	3017	II_EVP = 135,
3018	II_EVPE = 136,	3018	II_EVPE = 136,
3019	II_ABS = 137,	3019	II_ABS = 137,
3020	II_SQRT_D = 138,	3020	II_SQRT_D = 138,
3021	II_ADD_D = 139,	3021	II_ADD_D = 139,
3022	II_ADD_PS = 140,	3022	II_ADD_PS = 140,
3023	II_ADD_S = 141,	3023	II_ADD_S = 141,
3024	II_DIV_D = 142,	3024	II_DIV_D = 142,
3025	II_DIV_S = 143,	3025	II_DIV_S = 143,
3026	II_FLOOR = 144,	3026	II_FLOOR = 144,
3027	II_MOV_D = 145,	3027	II_MOV_D = 145,
3028	II_MOV_S = 146,	3028	II_MOV_S = 146,
3029	II_MUL_D = 147,	3029	II_MUL_D = 147,
3030	II_MUL_PS = 148,	3030	II_MUL_PS = 148,
3031	II_MUL_S = 149,	3031	II_MUL_S = 149,
3032	II_NEG = 150,	3032	II_NEG = 150,
3033	II_FORK = 151,	3033	II_FORK = 151,
3034	II_SQRT_S = 152,	3034	II_SQRT_S = 152,
3035	II_SUB_D = 153,	3035	II_SUB_D = 153,
3036	II_SUB_PS = 154,	3036	II_SUB_PS = 154,
3037	II_SUB_S = 155,	3037	II_SUB_S = 155,
3038	II_GINVI = 156,	3038	II_GINVI = 156,
3039	II_GINVT = 157,	3039	II_GINVT = 157,
3040	II_HYPCALL = 158,	3040	II_HYPCALL = 158,
3041	II_JALR_HB = 159,	3041	II_JALR_HB = 159,
3042	II_JALRC = 160,	3042	II_JALRC = 160,
3043	II_JALRS = 161,	3043	II_JALRS = 161,
3044	II_JALS = 162,	3044	II_JALS = 162,
3045	II_JIALC = 163,	3045	II_JIALC = 163,
3046	II_JIC = 164,	3046	II_JIC = 164,
3047	II_JRADDIUSP = 165,	3047	II_JRADDIUSP = 165,
3048	II_JRC = 166,	3048	II_JRC = 166,
3049	II_JR_HB = 167,	3049	II_JR_HB = 167,
3050	II_LB = 168,	3050	II_LB = 168,
3051	II_LBE = 169,	3051	II_LBE = 169,
3052	II_LBU = 170,	3052	II_LBU = 170,
3053	II_LBUE = 171,	3053	II_LBUE = 171,
3054	II_LD = 172,	3054	II_LD = 172,
3055	II_LDC1 = 173,	3055	II_LDC1 = 173,
3056	II_LDC2 = 174,	3056	II_LDC2 = 174,
3057	II_LDC3 = 175,	3057	II_LDC3 = 175,
3058	II_LDL = 176,	3058	II_LDL = 176,
3059	II_LDPC = 177,	3059	II_LDPC = 177,
3060	II_LDR = 178,	3060	II_LDR = 178,
3061	II_LDXC1 = 179,	3061	II_LDXC1 = 179,
3062	II_LH = 180,	3062	II_LH = 180,
3063	II_LHE = 181,	3063	II_LHE = 181,
3064	II_LHU = 182,	3064	II_LHU = 182,
3065	II_LHUE = 183,	3065	II_LHUE = 183,
3066	II_LI = 184,	3066	II_LI = 184,
3067	II_LL = 185,	3067	II_LL = 185,
3068	II_LLD = 186,	3068	II_LLD = 186,
3069	II_LLE = 187,	3069	II_LLE = 187,
3070	II_LSA = 188,	3070	II_LSA = 188,
3071	II_LUI = 189,	3071	II_LUI = 189,
3072	II_LUXC1 = 190,	3072	II_LUXC1 = 190,
3073	II_LW = 191,	3073	II_LW = 191,
3074	II_LWC1 = 192,	3074	II_LWC1 = 192,
3075	II_LWC2 = 193,	3075	II_LWC2 = 193,
3076	II_LWC3 = 194,	3076	II_LWC3 = 194,
3077	II_LWE = 195,	3077	II_LWE = 195,
3078	II_LWL = 196,	3078	II_LWL = 196,
3079	II_LWLE = 197,	3079	II_LWLE = 197,
3080	II_LWM = 198,	3080	II_LWM = 198,
3081	II_LWPC = 199,	3081	II_LWPC = 199,
3082	II_LWP = 200,	3082	II_LWP = 200,
3083	II_LWR = 201,	3083	II_LWR = 201,
3084	II_LWRE = 202,	3084	II_LWRE = 202,
3085	II_LWUPC = 203,	3085	II_LWUPC = 203,
3086	II_LWU = 204,	3086	II_LWU = 204,
3087	II_LWXC1 = 205,	3087	II_LWXC1 = 205,
3088	II_LWXS = 206,	3088	II_LWXS = 206,
3089	II_MADDF_D = 207,	3089	II_MADDF_D = 207,
3090	II_MADDF_S = 208,	3090	II_MADDF_S = 208,
3091	II_MADD_D = 209,	3091	II_MADD_D = 209,
3092	II_MADD_S = 210,	3092	II_MADD_S = 210,
3093	II_MAX_D = 211,	3093	II_MAX_D = 211,
3094	II_MAXA_D = 212,	3094	II_MAXA_D = 212,
3095	II_MAX_S = 213,	3095	II_MAX_S = 213,
3096	II_MAXA_S = 214,	3096	II_MAXA_S = 214,
3097	II_MFC0 = 215,	3097	II_MFC0 = 215,
3098	II_MFC2 = 216,	3098	II_MFC2 = 216,
3099	II_MFGC0 = 217,	3099	II_MFGC0 = 217,
3100	II_MFHC0 = 218,	3100	II_MFHC0 = 218,
3101	II_MFHC1 = 219,	3101	II_MFHC1 = 219,
3102	II_MFHGC0 = 220,	3102	II_MFHGC0 = 220,
3103	II_MFTR = 221,	3103	II_MFTR = 221,
3104	II_MIN_S = 222,	3104	II_MIN_S = 222,
3105	II_MINA_D = 223,	3105	II_MINA_D = 223,
3106	II_MIN_D = 224,	3106	II_MIN_D = 224,
3107	II_MINA_S = 225,	3107	II_MINA_S = 225,
3108	II_MOD = 226,	3108	II_MOD = 226,
3109	II_MODU = 227,	3109	II_MODU = 227,
3110	II_MOVE = 228,	3110	II_MOVE = 228,
3111	II_MOVF_D = 229,	3111	II_MOVF_D = 229,
3112	II_MOVF = 230,	3112	II_MOVF = 230,
3113	II_MOVF_S = 231,	3113	II_MOVF_S = 231,
3114	II_MOVN_D = 232,	3114	II_MOVN_D = 232,
3115	II_MOVN = 233,	3115	II_MOVN = 233,
3116	II_MOVN_S = 234,	3116	II_MOVN_S = 234,
3117	II_MOVT_D = 235,	3117	II_MOVT_D = 235,
3118	II_MOVT = 236,	3118	II_MOVT = 236,
3119	II_MOVT_S = 237,	3119	II_MOVT_S = 237,
3120	II_MOVZ_D = 238,	3120	II_MOVZ_D = 238,
3121	II_MOVZ = 239,	3121	II_MOVZ = 239,
3122	II_MOVZ_S = 240,	3122	II_MOVZ_S = 240,
3123	II_MSUBF_D = 241,	3123	II_MSUBF_D = 241,
3124	II_MSUBF_S = 242,	3124	II_MSUBF_S = 242,
3125	II_MSUB_D = 243,	3125	II_MSUB_D = 243,
3126	II_MSUB_S = 244,	3126	II_MSUB_S = 244,
3127	II_MTC0 = 245,	3127	II_MTC0 = 245,
3128	II_MTC2 = 246,	3128	II_MTC2 = 246,
3129	II_MTGC0 = 247,	3129	II_MTGC0 = 247,
3130	II_MTHC0 = 248,	3130	II_MTHC0 = 248,
3131	II_MTHC1 = 249,	3131	II_MTHC1 = 249,
3132	II_MTHGC0 = 250,	3132	II_MTHGC0 = 250,
3133	II_MTTR = 251,	3133	II_MTTR = 251,
3134	II_MUH = 252,	3134	II_MUH = 252,
3135	II_MUHU = 253,	3135	II_MUHU = 253,
3136	II_MUL = 254,	3136	II_MUL = 254,
3137	II_MULR_PS = 255,	3137	II_MULR_PS = 255,
3138	II_MULU = 256,	3138	II_MULU = 256,
3139	II_NMADD_D = 257,	3139	II_NMADD_D = 257,
3140	II_NMADD_S = 258,	3140	II_NMADD_S = 258,
3141	II_NMSUB_D = 259,	3141	II_NMSUB_D = 259,
3142	II_NMSUB_S = 260,	3142	II_NMSUB_S = 260,
3143	II_NOR = 261,	3143	II_NOR = 261,
3144	II_NOT = 262,	3144	II_NOT = 262,
3145	II_OR = 263,	3145	II_OR = 263,
3146	II_ORI = 264,	3146	II_ORI = 264,
3147	II_PAUSE = 265,	3147	II_PAUSE = 265,
3148	II_PREF = 266,	3148	II_PREF = 266,
3149	II_PREFE = 267,	3149	II_PREFE = 267,
3150	II_RDHWR = 268,	3150	II_RDHWR = 268,
3151	II_RDPGPR = 269,	3151	II_RDPGPR = 269,
3152	II_RECIP_D = 270,	3152	II_RECIP_D = 270,
3153	II_RECIP_S = 271,	3153	II_RECIP_S = 271,
3154	II_RINT_D = 272,	3154	II_RINT_D = 272,
3155	II_RINT_S = 273,	3155	II_RINT_S = 273,
3156	II_ROTR = 274,	3156	II_ROTR = 274,
3157	II_ROTRV = 275,	3157	II_ROTRV = 275,
3158	II_ROUND = 276,	3158	II_ROUND = 276,
3159	II_RSQRT_D = 277,	3159	II_RSQRT_D = 277,
3160	II_RSQRT_S = 278,	3160	II_RSQRT_S = 278,
3161	II_RESTORE = 279,	3161	II_RESTORE = 279,
3162	II_SB = 280,	3162	II_SB = 280,
3163	II_SBE = 281,	3163	II_SBE = 281,
3164	II_SC = 282,	3164	II_SC = 282,
3165	II_SCD = 283,	3165	II_SCD = 283,
3166	II_SCE = 284,	3166	II_SCE = 284,
3167	II_SD = 285,	3167	II_SD = 285,
3168	II_SDBBP = 286,	3168	II_SDBBP = 286,
3169	II_SDC1 = 287,	3169	II_SDC1 = 287,
3170	II_SDC2 = 288,	3170	II_SDC2 = 288,
3171	II_SDC3 = 289,	3171	II_SDC3 = 289,
3172	II_SDL = 290,	3172	II_SDL = 290,
3173	II_SDR = 291,	3173	II_SDR = 291,
3174	II_SDXC1 = 292,	3174	II_SDXC1 = 292,
3175	II_SEB = 293,	3175	II_SEB = 293,
3176	II_SEH = 294,	3176	II_SEH = 294,
3177	II_SELCCZ = 295,	3177	II_SELCCZ = 295,
3178	II_SELCCZ_D = 296,	3178	II_SELCCZ_D = 296,
3179	II_SELCCZ_S = 297,	3179	II_SELCCZ_S = 297,
3180	II_SEL_D = 298,	3180	II_SEL_D = 298,
3181	II_SEL_S = 299,	3181	II_SEL_S = 299,
3182	II_SEQ_SNE = 300,	3182	II_SEQ_SNE = 300,
3183	II_SEQI_SNEI = 301,	3183	II_SEQI_SNEI = 301,
3184	II_SH = 302,	3184	II_SH = 302,
3185	II_SHE = 303,	3185	II_SHE = 303,
3186	II_SIGRIE = 304,	3186	II_SIGRIE = 304,
3187	II_SLL = 305,	3187	II_SLL = 305,
3188	II_SLLV = 306,	3188	II_SLLV = 306,
3189	II_SLT_SLTU = 307,	3189	II_SLT_SLTU = 307,
3190	II_SLTI_SLTIU = 308,	3190	II_SLTI_SLTIU = 308,
3191	II_SRA = 309,	3191	II_SRA = 309,
3192	II_SRAV = 310,	3192	II_SRAV = 310,
3193	II_SRL = 311,	3193	II_SRL = 311,
3194	II_SRLV = 312,	3194	II_SRLV = 312,
3195	II_SSNOP = 313,	3195	II_SSNOP = 313,
3196	II_SUB = 314,	3196	II_SUB = 314,
3197	II_SUBU = 315,	3197	II_SUBU = 315,
3198	II_SUXC1 = 316,	3198	II_SUXC1 = 316,
3199	II_SW = 317,	3199	II_SW = 317,
3200	II_SWC1 = 318,	3200	II_SWC1 = 318,
3201	II_SWC2 = 319,	3201	II_SWC2 = 319,
3202	II_SWC3 = 320,	3202	II_SWC3 = 320,
3203	II_SWE = 321,	3203	II_SWE = 321,
3204	II_SWL = 322,	3204	II_SWL = 322,
3205	II_SWLE = 323,	3205	II_SWLE = 323,
3206	II_SWM = 324,	3206	II_SWM = 324,
3207	II_SWP = 325,	3207	II_SWP = 325,
3208	II_SWR = 326,	3208	II_SWR = 326,
3209	II_SWRE = 327,	3209	II_SWRE = 327,
3210	II_SWXC1 = 328,	3210	II_SWXC1 = 328,
3211	II_SYNC = 329,	3211	II_SYNC = 329,
3212	II_SYNCI = 330,	3212	II_SYNCI = 330,
3213	II_SYSCALL = 331,	3213	II_SYSCALL = 331,
3214	II_SAVE = 332,	3214	II_SAVE = 332,
3215	II_TEQ = 333,	3215	II_TEQ = 333,
3216	II_TEQI = 334,	3216	II_TEQI = 334,
3217	II_TGE = 335,	3217	II_TGE = 335,
3218	II_TGEI = 336,	3218	II_TGEI = 336,
3219	II_TGEIU = 337,	3219	II_TGEIU = 337,
3220	II_TGEU = 338,	3220	II_TGEU = 338,
3221	II_TLBGINV = 339,	3221	II_TLBGINV = 339,
3222	II_TLBGINVF = 340,	3222	II_TLBGINVF = 340,
3223	II_TLBGP = 341,	3223	II_TLBGP = 341,
3224	II_TLBGR = 342,	3224	II_TLBGR = 342,
3225	II_TLBGWI = 343,	3225	II_TLBGWI = 343,
3226	II_TLBGWR = 344,	3226	II_TLBGWR = 344,
3227	II_TLBINV = 345,	3227	II_TLBINV = 345,
3228	II_TLBINVF = 346,	3228	II_TLBINVF = 346,
3229	II_TLBP = 347,	3229	II_TLBP = 347,
3230	II_TLBR = 348,	3230	II_TLBR = 348,
3231	II_TLBWI = 349,	3231	II_TLBWI = 349,
3232	II_TLBWR = 350,	3232	II_TLBWR = 350,
3233	II_TLT = 351,	3233	II_TLT = 351,
3234	II_TLTI = 352,	3234	II_TLTI = 352,
3235	II_TTLTIU = 353,	3235	II_TTLTIU = 353,
3236	II_TLTU = 354,	3236	II_TLTU = 354,
3237	II_TNE = 355,	3237	II_TNE = 355,
3238	II_TNEI = 356,	3238	II_TNEI = 356,
3239	II_TRUNC = 357,	3239	II_TRUNC = 357,
3240	II_WAIT = 358,	3240	II_WAIT = 358,
3241	II_WRPGPR = 359,	3241	II_WRPGPR = 359,
3242	II_WSBH = 360,	3242	II_WSBH = 360,
3243	II_XOR = 361,	3243	II_XOR = 361,
3244	II_XORI = 362,	3244	II_XORI = 362,
3245	II_YIELD = 363,	3245	II_YIELD = 363,
3246	AND = 364,	3246	AND = 364,
3247	LUi = 365,	3247	LUi = 365,
3248	NOR = 366,	3248	NOR = 366,
3249	OR = 367,	3249	OR = 367,
3250	SLTi_SLTiu = 368,	3250	SLTi_SLTiu = 368,
3251	SUB = 369,	3251	SUB = 369,
3252	SUBu = 370,	3252	SUBu = 370,
3253	XOR = 371,	3253	XOR = 371,
3254	SSNOP = 372,	3254	SSNOP = 372,
3255	NOP = 373,	3255	NOP = 373,
3256	B = 374,	3256	B = 374,
3257	BAL = 375,	3257	BAL = 375,
3258	BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,	3258	BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,
3259	BEQ_BEQL_BNE_BNEL = 377,	3259	BEQ_BEQL_BNE_BNEL = 377,
3260	BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,	3260	BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,
3261	BREAK = 379,	3261	BREAK = 379,
3262	DERET = 380,	3262	DERET = 380,
3263	ERET = 381,	3263	ERET = 381,
3264	ERet_RetRA = 382,	3264	ERet_RetRA = 382,
3265	ERETNC = 383,	3265	ERETNC = 383,
3266	J_TAILCALL = 384,	3266	J_TAILCALL = 384,
3267	JR_TAILCALLREG_TAILCALLREGHB = 385,	3267	JR_TAILCALLREG_TAILCALLREGHB = 385,
3268	JR_HB = 386,	3268	JR_HB = 386,
3269	PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,	3269	PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,
3270	PseudoReturn = 388,	3270	PseudoReturn = 388,
3271	SDBBP = 389,	3271	SDBBP = 389,
3272	SYSCALL = 390,	3272	SYSCALL = 390,
3273	TEQ = 391,	3273	TEQ = 391,
3274	TEQI = 392,	3274	TEQI = 392,
3275	TGE = 393,	3275	TGE = 393,
3276	TGEI = 394,	3276	TGEI = 394,
3277	TGEIU = 395,	3277	TGEIU = 395,
3278	TGEU = 396,	3278	TGEU = 396,
3279	TLT = 397,	3279	TLT = 397,
3280	TLTI = 398,	3280	TLTI = 398,
3281	TLTU = 399,	3281	TLTU = 399,
3282	TNE = 400,	3282	TNE = 400,
3283	TNEI = 401,	3283	TNEI = 401,
3284	TRAP = 402,	3284	TRAP = 402,
3285	TTLTIU = 403,	3285	TTLTIU = 403,
3286	WAIT = 404,	3286	WAIT = 404,
3287	PAUSE = 405,	3287	PAUSE = 405,
3288	JAL = 406,	3288	JAL = 406,
3289	JALR_JALRHBPseudo_JALRPseudo = 407,	3289	JALR_JALRHBPseudo_JALRPseudo = 407,
3290	JALR_HB = 408,	3290	JALR_HB = 408,
3291	JALX = 409,	3291	JALX = 409,
3292	TLBINV = 410,	3292	TLBINV = 410,
3293	TLBINVF = 411,	3293	TLBINVF = 411,
3294	TLBP = 412,	3294	TLBP = 412,
3295	TLBR = 413,	3295	TLBR = 413,
3296	TLBWI = 414,	3296	TLBWI = 414,
3297	TLBWR = 415,	3297	TLBWR = 415,
3298	MFC0 = 416,	3298	MFC0 = 416,
3299	MTC0 = 417,	3299	MTC0 = 417,
3300	MFC2 = 418,	3300	MFC2 = 418,
3301	MTC2 = 419,	3301	MTC2 = 419,
3302	HYPCALL = 420,	3302	HYPCALL = 420,
3303	MFGC0 = 421,	3303	MFGC0 = 421,
3304	MFHGC0 = 422,	3304	MFHGC0 = 422,
3305	MTGC0 = 423,	3305	MTGC0 = 423,
3306	MTHGC0 = 424,	3306	MTHGC0 = 424,
3307	TLBGINV = 425,	3307	TLBGINV = 425,
3308	TLBGINVF = 426,	3308	TLBGINVF = 426,
3309	TLBGP = 427,	3309	TLBGP = 427,
3310	TLBGR = 428,	3310	TLBGR = 428,
3311	TLBGWI = 429,	3311	TLBGWI = 429,
3312	TLBGWR = 430,	3312	TLBGWR = 430,
3313	LB = 431,	3313	LB = 431,
3314	LBu = 432,	3314	LBu = 432,
3315	LH = 433,	3315	LH = 433,
3316	LHu = 434,	3316	LHu = 434,
3317	LW = 435,	3317	LW = 435,
3318	LL = 436,	3318	LL = 436,
3319	LWC2 = 437,	3319	LWC2 = 437,
3320	LWC3 = 438,	3320	LWC3 = 438,
3321	LDC2 = 439,	3321	LDC2 = 439,
3322	LDC3 = 440,	3322	LDC3 = 440,
3323	LBE = 441,	3323	LBE = 441,
3324	LBuE = 442,	3324	LBuE = 442,
3325	LHE = 443,	3325	LHE = 443,
3326	LHuE = 444,	3326	LHuE = 444,
3327	LWE = 445,	3327	LWE = 445,
3328	LLE = 446,	3328	LLE = 446,
3329	LWPC = 447,	3329	LWPC = 447,
3330	LWL = 448,	3330	LWL = 448,
3331	LWR = 449,	3331	LWR = 449,
3332	LWLE = 450,	3332	LWLE = 450,
3333	LWRE = 451,	3333	LWRE = 451,
3334	SB = 452,	3334	SB = 452,
3335	SH = 453,	3335	SH = 453,
3336	SW = 454,	3336	SW = 454,
3337	SWC2 = 455,	3337	SWC2 = 455,
3338	SWC3 = 456,	3338	SWC3 = 456,
3339	SDC2 = 457,	3339	SDC2 = 457,
3340	SDC3 = 458,	3340	SDC3 = 458,
3341	SC = 459,	3341	SC = 459,
3342	SBE = 460,	3342	SBE = 460,
3343	SHE = 461,	3343	SHE = 461,
3344	SWE = 462,	3344	SWE = 462,
3345	SCE = 463,	3345	SCE = 463,
3346	SWL = 464,	3346	SWL = 464,
3347	SWR = 465,	3347	SWR = 465,
3348	SWLE = 466,	3348	SWLE = 466,
3349	SWRE = 467,	3349	SWRE = 467,
3350	PREF = 468,	3350	PREF = 468,
3351	PREFE = 469,	3351	PREFE = 469,
3352	CACHE = 470,	3352	CACHE = 470,
3353	CACHEE = 471,	3353	CACHEE = 471,
3354	SYNC = 472,	3354	SYNC = 472,
3355	SYNCI = 473,	3355	SYNCI = 473,
3356	CLO = 474,	3356	CLO = 474,
3357	CLZ = 475,	3357	CLZ = 475,
3358	DI = 476,	3358	DI = 476,
3359	EI = 477,	3359	EI = 477,
3360	MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,	3360	MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,
3361	EHB = 479,	3361	EHB = 479,
3362	RDHWR = 480,	3362	RDHWR = 480,
3363	WSBH = 481,	3363	WSBH = 481,
3364	MOVN_I_I = 482,	3364	MOVN_I_I = 482,
3365	MOVZ_I_I = 483,	3365	MOVZ_I_I = 483,
3366	DIV_PseudoSDIV_SDIV = 484,	3366	DIV_PseudoSDIV_SDIV = 484,
3367	DIVU_PseudoUDIV_UDIV = 485,	3367	DIVU_PseudoUDIV_UDIV = 485,
3368	MUL = 486,	3368	MUL = 486,
3369	MULT_PseudoMULT = 487,	3369	MULT_PseudoMULT = 487,
3370	MULTu_PseudoMULTu = 488,	3370	MULTu_PseudoMULTu = 488,
3371	MADD_PseudoMADD = 489,	3371	MADD_PseudoMADD = 489,
3372	MADDU_PseudoMADDU = 490,	3372	MADDU_PseudoMADDU = 490,
3373	MSUB_PseudoMSUB = 491,	3373	MSUB_PseudoMSUB = 491,
3374	MSUBU_PseudoMSUBU = 492,	3374	MSUBU_PseudoMSUBU = 492,
3375	MTHI_MTLO_PseudoMTLOHI = 493,	3375	MTHI_MTLO_PseudoMTLOHI = 493,
3376	EXT = 494,	3376	EXT = 494,
3377	INS = 495,	3377	INS = 495,
3378	ADD = 496,	3378	ADD = 496,
3379	ADDi = 497,	3379	ADDi = 497,
3380	ADDiu = 498,	3380	ADDiu = 498,
3381	ANDi = 499,	3381	ANDi = 499,
3382	ORi = 500,	3382	ORi = 500,
3383	ROTR = 501,	3383	ROTR = 501,
3384	SEB = 502,	3384	SEB = 502,
3385	SEH = 503,	3385	SEH = 503,
3386	SLT_SLTu = 504,	3386	SLT_SLTu = 504,
3387	SLL = 505,	3387	SLL = 505,
3388	SRA = 506,	3388	SRA = 506,
3389	SRL = 507,	3389	SRL = 507,
3390	XORi = 508,	3390	XORi = 508,
3391	ADDu = 509,	3391	ADDu = 509,
3392	SLLV = 510,	3392	SLLV = 510,
3393	SRAV = 511,	3393	SRAV = 511,
3394	SRLV = 512,	3394	SRLV = 512,
3395	LSA = 513,	3395	LSA = 513,
3396	COPY = 514,	3396	COPY = 514,
3397	VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,	3397	VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,
3398	BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,	3398	BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,
3399	BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,	3399	BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,
3400	INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,	3400	INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,
3401	SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,	3401	SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,
3402	BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,	3402	BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,
3403	BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,	3403	BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,
3404	BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,	3404	BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,
3405	BSELI_B_BSEL_V = 523,	3405	BSELI_B_BSEL_V = 523,
3406	BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,	3406	BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,
3407	BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,	3407	BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,
3408	PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,	3408	PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,
3409	SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,	3409	SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,
3410	BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,	3410	BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,
3411	CFCMSA_CTCMSA = 529,	3411	CFCMSA_CTCMSA = 529,
3412	FABS_S_FABS_D32_FABS_D64 = 530,	3412	FABS_S_FABS_D32_FABS_D64 = 530,
3413	MOVF_D32_MOVF_D64 = 531,	3413	MOVF_D32_MOVF_D64 = 531,
3414	MOVF_S = 532,	3414	MOVF_S = 532,
3415	MOVT_D32_MOVT_D64 = 533,	3415	MOVT_D32_MOVT_D64 = 533,
3416	MOVT_S = 534,	3416	MOVT_S = 534,
3417	FMOV_D32_FMOV_D64 = 535,	3417	FMOV_D32_FMOV_D64 = 535,
3418	FMOV_S = 536,	3418	FMOV_S = 536,
3419	FNEG_S_FNEG_D32_FNEG_D64 = 537,	3419	FNEG_S_FNEG_D32_FNEG_D64 = 537,
3420	ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,	3420	ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,
3421	ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,	3421	ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,
3422	ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,	3422	ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,
3423	ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,	3423	ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,
3424	AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,	3424	AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,
3425	SHF_B_SHF_H_SHF_W = 543,	3425	SHF_B_SHF_H_SHF_W = 543,
3426	FILL_B_FILL_D_FILL_H_FILL_W = 544,	3426	FILL_B_FILL_D_FILL_H_FILL_W = 544,
3427	SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,	3427	SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,
3428	MOVE_V = 546,	3428	MOVE_V = 546,
3429	LDI_B_LDI_D_LDI_H_LDI_W = 547,	3429	LDI_B_LDI_D_LDI_H_LDI_W = 547,
3430	AND_V_NOR_V_OR_V_XOR_V = 548,	3430	AND_V_NOR_V_OR_V_XOR_V = 548,
3431	ANDI_B_NORI_B_ORI_B_XORI_B = 549,	3431	ANDI_B_NORI_B_ORI_B_XORI_B = 549,
3432	AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,	3432	AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,
3433	FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,	3433	FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,
3434	INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,	3434	INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,
3435	FEXP2_D_FEXP2_W = 553,	3435	FEXP2_D_FEXP2_W = 553,
3436	CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,	3436	CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,
3437	CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,	3437	CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,
3438	CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,	3438	CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,
3439	CMP_UN_D = 557,	3439	CMP_UN_D = 557,
3440	CMP_UN_S = 558,	3440	CMP_UN_S = 558,
3441	CMP_UEQ_D = 559,	3441	CMP_UEQ_D = 559,
3442	CMP_UEQ_S = 560,	3442	CMP_UEQ_S = 560,
3443	CMP_EQ_D = 561,	3443	CMP_EQ_D = 561,
3444	CMP_EQ_S = 562,	3444	CMP_EQ_S = 562,
3445	CMP_LT_D = 563,	3445	CMP_LT_D = 563,
3446	CMP_LT_S = 564,	3446	CMP_LT_S = 564,
3447	CMP_ULT_D = 565,	3447	CMP_ULT_D = 565,
3448	CMP_ULT_S = 566,	3448	CMP_ULT_S = 566,
3449	CMP_LE_D = 567,	3449	CMP_LE_D = 567,
3450	CMP_LE_S = 568,	3450	CMP_LE_S = 568,
3451	CMP_ULE_D = 569,	3451	CMP_ULE_D = 569,
3452	CMP_ULE_S = 570,	3452	CMP_ULE_S = 570,
3453	FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,	3453	FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,
3454	FSUEQ_D_FSUEQ_W = 572,	3454	FSUEQ_D_FSUEQ_W = 572,
3455	FSULE_D_FSULE_W = 573,	3455	FSULE_D_FSULE_W = 573,
3456	FSULT_D_FSULT_W = 574,	3456	FSULT_D_FSULT_W = 574,
3457	FSUNE_D_FSUNE_W = 575,	3457	FSUNE_D_FSUNE_W = 575,
3458	FSUN_D_FSUN_W = 576,	3458	FSUN_D_FSUN_W = 576,
3459	FCAF_D_FCAF_W = 577,	3459	FCAF_D_FCAF_W = 577,
3460	FCEQ_D_FCEQ_W = 578,	3460	FCEQ_D_FCEQ_W = 578,
3461	FCLE_D_FCLE_W = 579,	3461	FCLE_D_FCLE_W = 579,
3462	FCLT_D_FCLT_W = 580,	3462	FCLT_D_FCLT_W = 580,
3463	FCNE_D_FCNE_W = 581,	3463	FCNE_D_FCNE_W = 581,
3464	FCOR_D_FCOR_W = 582,	3464	FCOR_D_FCOR_W = 582,
3465	FCUEQ_D_FCUEQ_W = 583,	3465	FCUEQ_D_FCUEQ_W = 583,
3466	FCULE_D_FCULE_W = 584,	3466	FCULE_D_FCULE_W = 584,
3467	FCULT_D_FCULT_W = 585,	3467	FCULT_D_FCULT_W = 585,
3468	FCUNE_D_FCUNE_W = 586,	3468	FCUNE_D_FCUNE_W = 586,
3469	FCUN_D_FCUN_W = 587,	3469	FCUN_D_FCUN_W = 587,
3470	FABS_D_FABS_W = 588,	3470	FABS_D_FABS_W = 588,
3471	FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,	3471	FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,
3472	FFQL_D_FFQL_W = 590,	3472	FFQL_D_FFQL_W = 590,
3473	FFQR_D_FFQR_W = 591,	3473	FFQR_D_FFQR_W = 591,
3474	FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,	3474	FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,
3475	FRINT_D_FRINT_W = 593,	3475	FRINT_D_FRINT_W = 593,
3476	FTQ_H_FTQ_W = 594,	3476	FTQ_H_FTQ_W = 594,
3477	FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,	3477	FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,
3478	FEXDO_H_FEXDO_W = 596,	3478	FEXDO_H_FEXDO_W = 596,
3479	FEXUPL_D_FEXUPL_W = 597,	3479	FEXUPL_D_FEXUPL_W = 597,
3480	FEXUPR_D_FEXUPR_W = 598,	3480	FEXUPR_D_FEXUPR_W = 598,
3481	FCLASS_D_FCLASS_W = 599,	3481	FCLASS_D_FCLASS_W = 599,
3482	FMAX_A_D_FMAX_A_W = 600,	3482	FMAX_A_D_FMAX_A_W = 600,
3483	FMAX_D_FMAX_W = 601,	3483	FMAX_D_FMAX_W = 601,
3484	FMIN_A_D_FMIN_A_W = 602,	3484	FMIN_A_D_FMIN_A_W = 602,
3485	FMIN_D_FMIN_W = 603,	3485	FMIN_D_FMIN_W = 603,
3486	FLOG2_D_FLOG2_W = 604,	3486	FLOG2_D_FLOG2_W = 604,
3487	ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,	3487	ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,
3488	ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,	3488	ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,
3489	INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,	3489	INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,
3490	SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,	3490	SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,
3491	SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,	3491	SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,
3492	SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,	3492	SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,
3493	SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,	3493	SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,
3494	SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,	3494	SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,
3495	MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,	3495	MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,
3496	DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,	3496	DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,
3497	HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,	3497	HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,
3498	HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,	3498	HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,
3499	MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,	3499	MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,
3500	MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,	3500	MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,
3501	MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,	3501	MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,
3502	MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,	3502	MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,
3503	SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,	3503	SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,
3504	SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,	3504	SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,
3505	SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,	3505	SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,
3506	SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,	3506	SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,
3507	SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,	3507	SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,
3508	PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,	3508	PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,
3509	NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,	3509	NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,
3510	FADD_D32_FADD_D64 = 628,	3510	FADD_D32_FADD_D64 = 628,
3511	FADD_PS64 = 629,	3511	FADD_PS64 = 629,
3512	FADD_S = 630,	3512	FADD_S = 630,
3513	FMUL_D32_FMUL_D64 = 631,	3513	FMUL_D32_FMUL_D64 = 631,
3514	FMUL_PS64 = 632,	3514	FMUL_PS64 = 632,
3515	FMUL_S = 633,	3515	FMUL_S = 633,
3516	FSUB_D32_FSUB_D64 = 634,	3516	FSUB_D32_FSUB_D64 = 634,
3517	FSUB_PS64 = 635,	3517	FSUB_PS64 = 635,
3518	FSUB_S = 636,	3518	FSUB_S = 636,
3519	TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,	3519	TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,
3520	CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,	3520	CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,
3521	CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,	3521	CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,
3522	C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,	3522	C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,
3523	C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,	3523	C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,
3524	FCMP_D32_FCMP_D64 = 642,	3524	FCMP_D32_FCMP_D64 = 642,
3525	FCMP_S32 = 643,	3525	FCMP_S32 = 643,
3526	PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,	3526	PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,
3527	PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,	3527	PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,
3528	FDIV_S = 646,	3528	FDIV_S = 646,
3529	FDIV_D32_FDIV_D64 = 647,	3529	FDIV_D32_FDIV_D64 = 647,
3530	FSQRT_S = 648,	3530	FSQRT_S = 648,
3531	FSQRT_D32_FSQRT_D64 = 649,	3531	FSQRT_D32_FSQRT_D64 = 649,
3532	FRCP_D_FRCP_W = 650,	3532	FRCP_D_FRCP_W = 650,
3533	FRSQRT_D_FRSQRT_W = 651,	3533	FRSQRT_D_FRSQRT_W = 651,
3534	RECIP_D32_RECIP_D64 = 652,	3534	RECIP_D32_RECIP_D64 = 652,
3535	RSQRT_D32_RSQRT_D64 = 653,	3535	RSQRT_D32_RSQRT_D64 = 653,
3536	RECIP_S = 654,	3536	RECIP_S = 654,
3537	RSQRT_S = 655,	3537	RSQRT_S = 655,
3538	FMADD_D_FMADD_W = 656,	3538	FMADD_D_FMADD_W = 656,
3539	FMSUB_D_FMSUB_W = 657,	3539	FMSUB_D_FMSUB_W = 657,
3540	FDIV_W = 658,	3540	FDIV_W = 658,
3541	FDIV_D = 659,	3541	FDIV_D = 659,
3542	FSQRT_W = 660,	3542	FSQRT_W = 660,
3543	FSQRT_D = 661,	3543	FSQRT_D = 661,
3544	FMUL_D_FMUL_W = 662,	3544	FMUL_D_FMUL_W = 662,
3545	FADD_D_FADD_W = 663,	3545	FADD_D_FADD_W = 663,
3546	FSUB_D_FSUB_W = 664,	3546	FSUB_D_FSUB_W = 664,
3547	DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,	3547	DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,
3548	DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,	3548	DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,
3549	DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,	3549	DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,
3550	MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,	3550	MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,
3551	MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,	3551	MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,
3552	MULV_B_MULV_D_MULV_H_MULV_W = 670,	3552	MULV_B_MULV_D_MULV_H_MULV_W = 670,
3553	MADDR_Q_H_MADDR_Q_W = 671,	3553	MADDR_Q_H_MADDR_Q_W = 671,
3554	MADD_Q_H_MADD_Q_W = 672,	3554	MADD_Q_H_MADD_Q_W = 672,
3555	MSUBR_Q_H_MSUBR_Q_W = 673,	3555	MSUBR_Q_H_MSUBR_Q_W = 673,
3556	MSUB_Q_H_MSUB_Q_W = 674,	3556	MSUB_Q_H_MSUB_Q_W = 674,
3557	MULR_Q_H_MULR_Q_W = 675,	3557	MULR_Q_H_MULR_Q_W = 675,
3558	MUL_Q_H_MUL_Q_W = 676,	3558	MUL_Q_H_MUL_Q_W = 676,
3559	MADD_D32_MADD_D64 = 677,	3559	MADD_D32_MADD_D64 = 677,
3560	MADD_S = 678,	3560	MADD_S = 678,
3561	MSUB_D32_MSUB_D64 = 679,	3561	MSUB_D32_MSUB_D64 = 679,
3562	MSUB_S = 680,	3562	MSUB_S = 680,
3563	NMADD_D32_NMADD_D64 = 681,	3563	NMADD_D32_NMADD_D64 = 681,
3564	NMADD_S = 682,	3564	NMADD_S = 682,
3565	NMSUB_D32_NMSUB_D64 = 683,	3565	NMSUB_D32_NMSUB_D64 = 683,
3566	NMSUB_S = 684,	3566	NMSUB_S = 684,
3567	CTC1 = 685,	3567	CTC1 = 685,
3568	MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,	3568	MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,
3569	MTHC1_D32_MTHC1_D64 = 687,	3569	MTHC1_D32_MTHC1_D64 = 687,
3570	COPY_U_B_COPY_U_H_COPY_U_W = 688,	3570	COPY_U_B_COPY_U_H_COPY_U_W = 688,
3571	COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,	3571	COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,
3572	BC1F = 690,	3572	BC1F = 690,
3573	BC1FL = 691,	3573	BC1FL = 691,
3574	BC1T = 692,	3574	BC1T = 692,
3575	BC1TL = 693,	3575	BC1TL = 693,
3576	CFC1 = 694,	3576	CFC1 = 694,
3577	MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,	3577	MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,
3578	MFHC1_D32_MFHC1_D64 = 696,	3578	MFHC1_D32_MFHC1_D64 = 696,
3579	MOVF_I = 697,	3579	MOVF_I = 697,
3580	MOVT_I = 698,	3580	MOVT_I = 698,
3581	SDC1_SDC164 = 699,	3581	SDC1_SDC164 = 699,
3582	SDXC1_SDXC164 = 700,	3582	SDXC1_SDXC164 = 700,
3583	SWC1 = 701,	3583	SWC1 = 701,
3584	SWXC1 = 702,	3584	SWXC1 = 702,
3585	SUXC1_SUXC164 = 703,	3585	SUXC1_SUXC164 = 703,
3586	ST_B_ST_D_ST_H_ST_W = 704,	3586	ST_B_ST_D_ST_H_ST_W = 704,
3587	ST_F16 = 705,	3587	ST_F16 = 705,
3588	MOVN_I_D32_MOVN_I_D64 = 706,	3588	MOVN_I_D32_MOVN_I_D64 = 706,
3589	MOVN_I_S = 707,	3589	MOVN_I_S = 707,
3590	MOVZ_I_D32_MOVZ_I_D64 = 708,	3590	MOVZ_I_D32_MOVZ_I_D64 = 708,
3591	MOVZ_I_S = 709,	3591	MOVZ_I_S = 709,
3592	LDC1_LDC164 = 710,	3592	LDC1_LDC164 = 710,
3593	LDXC1_LDXC164 = 711,	3593	LDXC1_LDXC164 = 711,
3594	LWC1 = 712,	3594	LWC1 = 712,
3595	LWXC1 = 713,	3595	LWXC1 = 713,
3596	LUXC1_LUXC164 = 714,	3596	LUXC1_LUXC164 = 714,
3597	LD_B_LD_D_LD_H_LD_W = 715,	3597	LD_B_LD_D_LD_H_LD_W = 715,
3598	LD_F16 = 716,	3598	LD_F16 = 716,
3599	CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,	3599	CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,
3600	FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,	3600	FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,
3601	ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,	3601	ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,
3602	ROTRV = 720,	3602	ROTRV = 720,
3603	ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,	3603	ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,
3604	ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,	3604	ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,
3605	ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,	3605	ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,
3606	LEA_ADDiu = 724,	3606	LEA_ADDiu = 724,
3607	ADDIUPC = 725,	3607	ADDIUPC = 725,
3608	ALIGN = 726,	3608	ALIGN = 726,
3609	ALUIPC = 727,	3609	ALUIPC = 727,
3610	AUI = 728,	3610	AUI = 728,
3611	AUIPC = 729,	3611	AUIPC = 729,
3612	BITSWAP = 730,	3612	BITSWAP = 730,
3613	CLO_R6 = 731,	3613	CLO_R6 = 731,
3614	CLZ_R6 = 732,	3614	CLZ_R6 = 732,
3615	LSA_R6 = 733,	3615	LSA_R6 = 733,
3616	SELEQZ_SELNEZ = 734,	3616	SELEQZ_SELNEZ = 734,
3617	AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,	3617	AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,
3618	SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,	3618	SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,
3619	Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,	3619	Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,
3620	ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,	3620	ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,
3621	ADDU16_MM_ADDu_MM = 739,	3621	ADDU16_MM_ADDu_MM = 739,
3622	ADD_MM = 740,	3622	ADD_MM = 740,
3623	ADDi_MM = 741,	3623	ADDi_MM = 741,
3624	AND16_MM_ANDI16_MM_AND_MM = 742,	3624	AND16_MM_ANDI16_MM_AND_MM = 742,
3625	ANDi_MM = 743,	3625	ANDi_MM = 743,
3626	CLO_MM = 744,	3626	CLO_MM = 744,
3627	CLZ_MM = 745,	3627	CLZ_MM = 745,
3628	EXT_MM = 746,	3628	EXT_MM = 746,
3629	INS_MM = 747,	3629	INS_MM = 747,
3630	LI16_MM = 748,	3630	LI16_MM = 748,
3631	LUi_MM = 749,	3631	LUi_MM = 749,
3632	MOVE16_MM = 750,	3632	MOVE16_MM = 750,
3633	MOVEP_MM = 751,	3633	MOVEP_MM = 751,
3634	NOR_MM = 752,	3634	NOR_MM = 752,
3635	NOT16_MM = 753,	3635	NOT16_MM = 753,
3636	OR16_MM_OR_MM = 754,	3636	OR16_MM_OR_MM = 754,
3637	ORi_MM = 755,	3637	ORi_MM = 755,
3638	ROTRV_MM = 756,	3638	ROTRV_MM = 756,
3639	ROTR_MM = 757,	3639	ROTR_MM = 757,
3640	SEB_MM = 758,	3640	SEB_MM = 758,
3641	SEH_MM = 759,	3641	SEH_MM = 759,
3642	SLL16_MM_SLL_MM = 760,	3642	SLL16_MM_SLL_MM = 760,
3643	SLLV_MM = 761,	3643	SLLV_MM = 761,
3644	SLT_MM_SLTu_MM = 762,	3644	SLT_MM_SLTu_MM = 762,
3645	SLTi_MM_SLTiu_MM = 763,	3645	SLTi_MM_SLTiu_MM = 763,
3646	SRAV_MM = 764,	3646	SRAV_MM = 764,
3647	SRA_MM = 765,	3647	SRA_MM = 765,
3648	SRL16_MM_SRL_MM = 766,	3648	SRL16_MM_SRL_MM = 766,
3649	SRLV_MM = 767,	3649	SRLV_MM = 767,
3650	SSNOP_MM = 768,	3650	SSNOP_MM = 768,
3651	SUBU16_MM_SUBu_MM = 769,	3651	SUBU16_MM_SUBu_MM = 769,
3652	SUB_MM = 770,	3652	SUB_MM = 770,
3653	WSBH_MM = 771,	3653	WSBH_MM = 771,
3654	XOR16_MM_XOR_MM = 772,	3654	XOR16_MM_XOR_MM = 772,
3655	XORi_MM = 773,	3655	XORi_MM = 773,
3656	ADDIUPC_MMR6 = 774,	3656	ADDIUPC_MMR6 = 774,
3657	ADDIU_MMR6 = 775,	3657	ADDIU_MMR6 = 775,
3658	ADDU16_MMR6_ADDU_MMR6 = 776,	3658	ADDU16_MMR6_ADDU_MMR6 = 776,
3659	ADD_MMR6 = 777,	3659	ADD_MMR6 = 777,
3660	ALIGN_MMR6 = 778,	3660	ALIGN_MMR6 = 778,
3661	ALUIPC_MMR6 = 779,	3661	ALUIPC_MMR6 = 779,
3662	AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,	3662	AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,
3663	ANDI_MMR6 = 781,	3663	ANDI_MMR6 = 781,
3664	AUIPC_MMR6 = 782,	3664	AUIPC_MMR6 = 782,
3665	AUI_MMR6 = 783,	3665	AUI_MMR6 = 783,
3666	BITSWAP_MMR6 = 784,	3666	BITSWAP_MMR6 = 784,
3667	CLO_MMR6 = 785,	3667	CLO_MMR6 = 785,
3668	CLZ_MMR6 = 786,	3668	CLZ_MMR6 = 786,
3669	EXT_MMR6 = 787,	3669	EXT_MMR6 = 787,
3670	INS_MMR6 = 788,	3670	INS_MMR6 = 788,
3671	LI16_MMR6 = 789,	3671	LI16_MMR6 = 789,
3672	LSA_MMR6 = 790,	3672	LSA_MMR6 = 790,
3673	LUI_MMR6 = 791,	3673	LUI_MMR6 = 791,
3674	MOVE16_MMR6 = 792,	3674	MOVE16_MMR6 = 792,
3675	NOR_MMR6 = 793,	3675	NOR_MMR6 = 793,
3676	NOT16_MMR6 = 794,	3676	NOT16_MMR6 = 794,
3677	OR16_MMR6_OR_MMR6 = 795,	3677	OR16_MMR6_OR_MMR6 = 795,
3678	ORI_MMR6 = 796,	3678	ORI_MMR6 = 796,
3679	SELEQZ_MMR6_SELNEZ_MMR6 = 797,	3679	SELEQZ_MMR6_SELNEZ_MMR6 = 797,
3680	SLL16_MMR6_SLL_MMR6 = 798,	3680	SLL16_MMR6_SLL_MMR6 = 798,
3681	SRL16_MMR6 = 799,	3681	SRL16_MMR6 = 799,
3682	SSNOP_MMR6 = 800,	3682	SSNOP_MMR6 = 800,
3683	SUBU16_MMR6_SUBU_MMR6 = 801,	3683	SUBU16_MMR6_SUBU_MMR6 = 801,
3684	SUB_MMR6 = 802,	3684	SUB_MMR6 = 802,
3685	WSBH_MMR6 = 803,	3685	WSBH_MMR6 = 803,
3686	XOR16_MMR6_XOR_MMR6 = 804,	3686	XOR16_MMR6_XOR_MMR6 = 804,
3687	XORI_MMR6 = 805,	3687	XORI_MMR6 = 805,
3688	AND64_ANDi64 = 806,	3688	AND64_ANDi64 = 806,
3689	DEXT64_32 = 807,	3689	DEXT64_32 = 807,
3690	DSLL64_32 = 808,	3690	DSLL64_32 = 808,
3691	ORi64 = 809,	3691	ORi64 = 809,
3692	SEB64 = 810,	3692	SEB64 = 810,
3693	SEH64 = 811,	3693	SEH64 = 811,
3694	SLL64_32_SLL64_64 = 812,	3694	SLL64_32_SLL64_64 = 812,
3695	SLT64_SLTu64 = 813,	3695	SLT64_SLTu64 = 813,
3696	SLTi64_SLTiu64 = 814,	3696	SLTi64_SLTiu64 = 814,
3697	XOR64_XORi64 = 815,	3697	XOR64_XORi64 = 815,
3698	DADD = 816,	3698	DADD = 816,
3699	DADDi = 817,	3699	DADDi = 817,
3700	DADDiu = 818,	3700	DADDiu = 818,
3701	DADDu = 819,	3701	DADDu = 819,
3702	DCLO = 820,	3702	DCLO = 820,
3703	DCLZ = 821,	3703	DCLZ = 821,
3704	DEXT_DEXTM_DEXTU = 822,	3704	DEXT_DEXTM_DEXTU = 822,
3705	DINS_DINSM_DINSU = 823,	3705	DINS_DINSM_DINSU = 823,
3706	DROTR = 824,	3706	DROTR = 824,
3707	DROTR32 = 825,	3707	DROTR32 = 825,
3708	DROTRV = 826,	3708	DROTRV = 826,
3709	DSBH = 827,	3709	DSBH = 827,
3710	DSHD = 828,	3710	DSHD = 828,
3711	DSLL = 829,	3711	DSLL = 829,
3712	DSLL32 = 830,	3712	DSLL32 = 830,
3713	DSLLV = 831,	3713	DSLLV = 831,
3714	DSRA = 832,	3714	DSRA = 832,
3715	DSRA32 = 833,	3715	DSRA32 = 833,
3716	DSRAV = 834,	3716	DSRAV = 834,
3717	DSRL = 835,	3717	DSRL = 835,
3718	DSRL32 = 836,	3718	DSRL32 = 836,
3719	DSRLV = 837,	3719	DSRLV = 837,
3720	DSUB = 838,	3720	DSUB = 838,
3721	DSUBu = 839,	3721	DSUBu = 839,
3722	LEA_ADDiu64 = 840,	3722	LEA_ADDiu64 = 840,
3723	LUi64 = 841,	3723	LUi64 = 841,
3724	NOR64 = 842,	3724	NOR64 = 842,
3725	OR64 = 843,	3725	OR64 = 843,
3726	DALIGN = 844,	3726	DALIGN = 844,
3727	DAHI = 845,	3727	DAHI = 845,
3728	DATI = 846,	3728	DATI = 846,
3729	DAUI = 847,	3729	DAUI = 847,
3730	DCLO_R6 = 848,	3730	DCLO_R6 = 848,
3731	DCLZ_R6 = 849,	3731	DCLZ_R6 = 849,
3732	DBITSWAP = 850,	3732	DBITSWAP = 850,
3733	DLSA_DLSA_R6 = 851,	3733	DLSA_DLSA_R6 = 851,
3734	SELEQZ64_SELNEZ64 = 852,	3734	SELEQZ64_SELNEZ64 = 852,
3735	MADD = 853,	3735	MADD = 853,
3736	MADDU = 854,	3736	MADDU = 854,
3737	MSUB = 855,	3737	MSUB = 855,
3738	MSUBU = 856,	3738	MSUBU = 856,
3739	PseudoMADD_MM = 857,	3739	PseudoMADD_MM = 857,
3740	PseudoMADDU_MM = 858,	3740	PseudoMADDU_MM = 858,
3741	PseudoMSUB_MM = 859,	3741	PseudoMSUB_MM = 859,
3742	PseudoMSUBU_MM = 860,	3742	PseudoMSUBU_MM = 860,
3743	PseudoMULT_MM = 861,	3743	PseudoMULT_MM = 861,
3744	PseudoMULTu_MM = 862,	3744	PseudoMULTu_MM = 862,
3745	PseudoMULT = 863,	3745	PseudoMULT = 863,
3746	PseudoMULTu = 864,	3746	PseudoMULTu = 864,
3747	PseudoSDIV_SDIV = 865,	3747	PseudoSDIV_SDIV = 865,
3748	PseudoUDIV_UDIV = 866,	3748	PseudoUDIV_UDIV = 866,
3749	PseudoMFHI_MM_PseudoMFLO_MM = 867,	3749	PseudoMFHI_MM_PseudoMFLO_MM = 867,
3750	PseudoMTLOHI_MM = 868,	3750	PseudoMTLOHI_MM = 868,
3751	MUH = 869,	3751	MUH = 869,
3752	MUHU = 870,	3752	MUHU = 870,
3753	MULU = 871,	3753	MULU = 871,
3754	MUL_R6 = 872,	3754	MUL_R6 = 872,
3755	MOD = 873,	3755	MOD = 873,
3756	MODU = 874,	3756	MODU = 874,
3757	MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,	3757	MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,
3758	DivRxRy16 = 876,	3758	DivRxRy16 = 876,
3759	DivuRxRy16 = 877,	3759	DivuRxRy16 = 877,
3760	MULT_MM = 878,	3760	MULT_MM = 878,
3761	MULTu_MM = 879,	3761	MULTu_MM = 879,
3762	MADD_MM = 880,	3762	MADD_MM = 880,
3763	MADDU_MM = 881,	3763	MADDU_MM = 881,
3764	MSUB_MM = 882,	3764	MSUB_MM = 882,
3765	MSUBU_MM = 883,	3765	MSUBU_MM = 883,
3766	MUL_MM = 884,	3766	MUL_MM = 884,
3767	SDIV_MM_SDIV_MM_Pseudo = 885,	3767	SDIV_MM_SDIV_MM_Pseudo = 885,
3768	UDIV_MM_UDIV_MM_Pseudo = 886,	3768	UDIV_MM_UDIV_MM_Pseudo = 886,
3769	MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,	3769	MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,
3770	MOVF_I_MM = 888,	3770	MOVF_I_MM = 888,
3771	MOVT_I_MM = 889,	3771	MOVT_I_MM = 889,
3772	MTHI_MM_MTLO_MM = 890,	3772	MTHI_MM_MTLO_MM = 890,
3773	RDHWR_MM = 891,	3773	RDHWR_MM = 891,
3774	MUHU_MMR6 = 892,	3774	MUHU_MMR6 = 892,
3775	MUH_MMR6 = 893,	3775	MUH_MMR6 = 893,
3776	MULU_MMR6 = 894,	3776	MULU_MMR6 = 894,
3777	MUL_MMR6 = 895,	3777	MUL_MMR6 = 895,
3778	MODU_MMR6 = 896,	3778	MODU_MMR6 = 896,
3779	MOD_MMR6 = 897,	3779	MOD_MMR6 = 897,
3780	DIVU_MMR6 = 898,	3780	DIVU_MMR6 = 898,
3781	DIV_MMR6 = 899,	3781	DIV_MMR6 = 899,
3782	RDHWR_MMR6 = 900,	3782	RDHWR_MMR6 = 900,
3783	DMULU = 901,	3783	DMULU = 901,
3784	DMULT_PseudoDMULT = 902,	3784	DMULT_PseudoDMULT = 902,
3785	DMULTu_PseudoDMULTu = 903,	3785	DMULTu_PseudoDMULTu = 903,
3786	DSDIV_PseudoDSDIV = 904,	3786	DSDIV_PseudoDSDIV = 904,
3787	DUDIV_PseudoDUDIV = 905,	3787	DUDIV_PseudoDUDIV = 905,
3788	MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,	3788	MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,
3789	PseudoMTLOHI64 = 907,	3789	PseudoMTLOHI64 = 907,
3790	MTHI64_MTLO64 = 908,	3790	MTHI64_MTLO64 = 908,
3791	RDHWR64 = 909,	3791	RDHWR64 = 909,
3792	MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,	3792	MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,
3793	MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,	3793	MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,
3794	DMUH = 912,	3794	DMUH = 912,
3795	DMUHU = 913,	3795	DMUHU = 913,
3796	DMUL_R6 = 914,	3796	DMUL_R6 = 914,
3797	DDIV = 915,	3797	DDIV = 915,
3798	DMOD = 916,	3798	DMOD = 916,
3799	DDIVU = 917,	3799	DDIVU = 917,
3800	DMODU = 918,	3800	DMODU = 918,
3801	BAL_BR_BLTZAL = 919,	3801	BAL_BR_BLTZAL = 919,
3802	BEQ_BNE = 920,	3802	BEQ_BNE = 920,
3803	BGTZ_BGEZ_BLEZ_BLTZ = 921,	3803	BGTZ_BGEZ_BLEZ_BLTZ = 921,
3804	J = 922,	3804	J = 922,
3805	JR = 923,	3805	JR = 923,
3806	ERet = 924,	3806	ERet = 924,
3807	BGEZAL = 925,	3807	BGEZAL = 925,
3808	BALC = 926,	3808	BALC = 926,
3809	BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927,	3809	BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927,
3810	JIALC = 928,	3810	JIALC = 928,
3811	BC = 929,	3811	BC = 929,
3812	BC2EQZ_BC2NEZ = 930,	3812	BC2EQZ_BC2NEZ = 930,
3813	BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931,	3813	BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931,
3814	BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932,	3814	BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932,
3815	JIC = 933,	3815	JIC = 933,
3816	JR_HB_R6 = 934,	3816	JR_HB_R6 = 934,
3817	SIGRIE = 935,	3817	SIGRIE = 935,
3818	PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936,	3818	PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936,
3819	TAILCALLR6REG_TAILCALLHBR6REG = 937,	3819	TAILCALLR6REG_TAILCALLHBR6REG = 937,
3820	SDBBP_R6 = 938,	3820	SDBBP_R6 = 938,
3821	Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939,	3821	Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939,
3822	BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940,	3822	BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940,
3823	Jal16_JalB16 = 941,	3823	Jal16_JalB16 = 941,
3824	JumpLinkReg16 = 942,	3824	JumpLinkReg16 = 942,
3825	Break16 = 943,	3825	Break16 = 943,
3826	SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944,	3826	SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944,
3827	B16_MM_B_MM = 945,	3827	B16_MM_B_MM = 945,
3828	BAL_BR_MM = 946,	3828	BAL_BR_MM = 946,
3829	BC1F_MM = 947,	3829	BC1F_MM = 947,
3830	BC1T_MM = 948,	3830	BC1T_MM = 948,
3831	BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949,	3831	BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949,
3832	BEQZC_MM_BNEZC_MM = 950,	3832	BEQZC_MM_BNEZC_MM = 950,
3833	BEQ_MM_BNE_MM = 951,	3833	BEQ_MM_BNE_MM = 951,
3834	DERET_MM = 952,	3834	DERET_MM = 952,
3835	ERET_MM = 953,	3835	ERET_MM = 953,
3836	JR16_MM_JR_MM = 954,	3836	JR16_MM_JR_MM = 954,
3837	J_MM = 955,	3837	J_MM = 955,
3838	B_MM_Pseudo = 956,	3838	B_MM_Pseudo = 956,
3839	BGEZALS_MM_BLTZALS_MM = 957,	3839	BGEZALS_MM_BLTZALS_MM = 957,
3840	BGEZAL_MM_BLTZAL_MM = 958,	3840	BGEZAL_MM_BLTZAL_MM = 958,
3841	JALR16_MM_JALR_MM = 959,	3841	JALR16_MM_JALR_MM = 959,
3842	JALRS16_MM_JALRS_MM = 960,	3842	JALRS16_MM_JALRS_MM = 960,
3843	JALS_MM = 961,	3843	JALS_MM = 961,
3844	JALX_MM_JAL_MM = 962,	3844	JALX_MM_JAL_MM = 962,
3845	TAILCALLREG_MM = 963,	3845	TAILCALLREG_MM = 963,
3846	TAILCALL_MM = 964,	3846	TAILCALL_MM = 964,
3847	PseudoIndirectBranch_MM = 965,	3847	PseudoIndirectBranch_MM = 965,
3848	BREAK16_MM_BREAK_MM = 966,	3848	BREAK16_MM_BREAK_MM = 966,
3849	SDBBP16_MM_SDBBP_MM = 967,	3849	SDBBP16_MM_SDBBP_MM = 967,
3850	SYSCALL_MM = 968,	3850	SYSCALL_MM = 968,
3851	TEQI_MM = 969,	3851	TEQI_MM = 969,
3852	TEQ_MM = 970,	3852	TEQ_MM = 970,
3853	TGEIU_MM = 971,	3853	TGEIU_MM = 971,
3854	TGEI_MM = 972,	3854	TGEI_MM = 972,
3855	TGEU_MM = 973,	3855	TGEU_MM = 973,
3856	TGE_MM = 974,	3856	TGE_MM = 974,
3857	TLTIU_MM = 975,	3857	TLTIU_MM = 975,
3858	TLTI_MM = 976,	3858	TLTI_MM = 976,
3859	TLTU_MM = 977,	3859	TLTU_MM = 977,
3860	TLT_MM = 978,	3860	TLT_MM = 978,
3861	TNEI_MM = 979,	3861	TNEI_MM = 979,
3862	TNE_MM = 980,	3862	TNE_MM = 980,
3863	TRAP_MM = 981,	3863	TRAP_MM = 981,
3864	BC16_MMR6_BC_MMR6 = 982,	3864	BC16_MMR6_BC_MMR6 = 982,
3865	BC1EQZC_MMR6_BC1NEZC_MMR6 = 983,	3865	BC1EQZC_MMR6_BC1NEZC_MMR6 = 983,
3866	BC2EQZC_MMR6_BC2NEZC_MMR6 = 984,	3866	BC2EQZC_MMR6_BC2NEZC_MMR6 = 984,
3867	BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985,	3867	BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985,
3868	BEQZC16_MMR6_BNEZC16_MMR6 = 986,	3868	BEQZC16_MMR6_BNEZC16_MMR6 = 986,
3869	BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987,	3869	BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987,
3870	DERET_MMR6 = 988,	3870	DERET_MMR6 = 988,
3871	ERETNC_MMR6 = 989,	3871	ERETNC_MMR6 = 989,
3872	JAL_MMR6 = 990,	3872	JAL_MMR6 = 990,
3873	ERET_MMR6 = 991,	3873	ERET_MMR6 = 991,
3874	JIC_MMR6 = 992,	3874	JIC_MMR6 = 992,
3875	JRADDIUSP_JRCADDIUSP_MMR6 = 993,	3875	JRADDIUSP_JRCADDIUSP_MMR6 = 993,
3876	JRC16_MM = 994,	3876	JRC16_MM = 994,
3877	JRC16_MMR6 = 995,	3877	JRC16_MMR6 = 995,
3878	SIGRIE_MMR6 = 996,	3878	SIGRIE_MMR6 = 996,
3879	B_MMR6_Pseudo = 997,	3879	B_MMR6_Pseudo = 997,
3880	PseudoIndirectBranch_MMR6 = 998,	3880	PseudoIndirectBranch_MMR6 = 998,
3881	BALC_MMR6 = 999,	3881	BALC_MMR6 = 999,
3882	BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000,	3882	BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000,
3883	JALRC16_MMR6 = 1001,	3883	JALRC16_MMR6 = 1001,
3884	JALRC_HB_MMR6 = 1002,	3884	JALRC_HB_MMR6 = 1002,
3885	JALRC_MMR6 = 1003,	3885	JALRC_MMR6 = 1003,
3886	JIALC_MMR6 = 1004,	3886	JIALC_MMR6 = 1004,
3887	TAILCALLREG_MMR6 = 1005,	3887	TAILCALLREG_MMR6 = 1005,
3888	TAILCALL_MMR6 = 1006,	3888	TAILCALL_MMR6 = 1006,
3889	BREAK16_MMR6_BREAK_MMR6 = 1007,	3889	BREAK16_MMR6_BREAK_MMR6 = 1007,
3890	SDBBP_MMR6_SDBBP16_MMR6 = 1008,	3890	SDBBP_MMR6_SDBBP16_MMR6 = 1008,
3891	BEQ64_BNE64 = 1009,	3891	BEQ64_BNE64 = 1009,
3892	BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010,	3892	BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010,
3893	JR64 = 1011,	3893	JR64 = 1011,
3894	JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012,	3894	JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012,
3895	JALR_HB64 = 1013,	3895	JALR_HB64 = 1013,
3896	JR_HB64 = 1014,	3896	JR_HB64 = 1014,
3897	TAILCALLREG64_TAILCALLREGHB64 = 1015,	3897	TAILCALLREG64_TAILCALLREGHB64 = 1015,
3898	PseudoReturn64 = 1016,	3898	PseudoReturn64 = 1016,
3899	BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017,	3899	BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017,
3900	BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018,	3900	BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018,
3901	JIC64 = 1019,	3901	JIC64 = 1019,
3902	PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020,	3902	PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020,
3903	JIALC64 = 1021,	3903	JIALC64 = 1021,
3904	JR_HB64_R6 = 1022,	3904	JR_HB64_R6 = 1022,
3905	TAILCALL64R6REG_TAILCALLHB64R6REG = 1023,	3905	TAILCALL64R6REG_TAILCALLHB64R6REG = 1023,
3906	PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024,	3906	PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024,
3907	EVP = 1025,	3907	EVP = 1025,
3908	DVP = 1026,	3908	DVP = 1026,
3909	TLBP_MM = 1027,	3909	TLBP_MM = 1027,
3910	TLBR_MM = 1028,	3910	TLBR_MM = 1028,
3911	TLBWI_MM = 1029,	3911	TLBWI_MM = 1029,
3912	TLBWR_MM = 1030,	3912	TLBWR_MM = 1030,
3913	DI_MM = 1031,	3913	DI_MM = 1031,
3914	EI_MM = 1032,	3914	EI_MM = 1032,
3915	EHB_MM = 1033,	3915	EHB_MM = 1033,
3916	PAUSE_MM = 1034,	3916	PAUSE_MM = 1034,
3917	WAIT_MM = 1035,	3917	WAIT_MM = 1035,
3918	RDPGPR_MMR6 = 1036,	3918	RDPGPR_MMR6 = 1036,
3919	WRPGPR_MMR6 = 1037,	3919	WRPGPR_MMR6 = 1037,
3920	TLBINV_MMR6 = 1038,	3920	TLBINV_MMR6 = 1038,
3921	TLBINVF_MMR6 = 1039,	3921	TLBINVF_MMR6 = 1039,
3922	MFHC0_MMR6 = 1040,	3922	MFHC0_MMR6 = 1040,
3923	MFC0_MMR6 = 1041,	3923	MFC0_MMR6 = 1041,
3924	MFHC2_MMR6_MFC2_MMR6 = 1042,	3924	MFHC2_MMR6_MFC2_MMR6 = 1042,
3925	MTHC0_MMR6 = 1043,	3925	MTHC0_MMR6 = 1043,
3926	MTC0_MMR6 = 1044,	3926	MTC0_MMR6 = 1044,
3927	MTHC2_MMR6_MTC2_MMR6 = 1045,	3927	MTHC2_MMR6_MTC2_MMR6 = 1045,
3928	EVP_MMR6 = 1046,	3928	EVP_MMR6 = 1046,
3929	DVP_MMR6 = 1047,	3929	DVP_MMR6 = 1047,
3930	DI_MMR6 = 1048,	3930	DI_MMR6 = 1048,
3931	EI_MMR6 = 1049,	3931	EI_MMR6 = 1049,
3932	EHB_MMR6 = 1050,	3932	EHB_MMR6 = 1050,
3933	PAUSE_MMR6 = 1051,	3933	PAUSE_MMR6 = 1051,
3934	WAIT_MMR6 = 1052,	3934	WAIT_MMR6 = 1052,
3935	DMFC0 = 1053,	3935	DMFC0 = 1053,
3936	DMTC0 = 1054,	3936	DMTC0 = 1054,
3937	DMFC2 = 1055,	3937	DMFC2 = 1055,
3938	DMTC2 = 1056,	3938	DMTC2 = 1056,
3939	CFC2_MM = 1057,	3939	CFC2_MM = 1057,
3940	CTC2_MM = 1058,	3940	CTC2_MM = 1058,
3941	DMT = 1059,	3941	DMT = 1059,
3942	DVPE = 1060,	3942	DVPE = 1060,
3943	EMT = 1061,	3943	EMT = 1061,
3944	EVPE = 1062,	3944	EVPE = 1062,
3945	MFTR = 1063,	3945	MFTR = 1063,
3946	MTTR = 1064,	3946	MTTR = 1064,
3947	YIELD = 1065,	3947	YIELD = 1065,
3948	FORK = 1066,	3948	FORK = 1066,
3949	DMFGC0 = 1067,	3949	DMFGC0 = 1067,
3950	DMTGC0 = 1068,	3950	DMTGC0 = 1068,
3951	HYPCALL_MM = 1069,	3951	HYPCALL_MM = 1069,
3952	TLBGINVF_MM = 1070,	3952	TLBGINVF_MM = 1070,
3953	TLBGINV_MM = 1071,	3953	TLBGINV_MM = 1071,
3954	TLBGP_MM = 1072,	3954	TLBGP_MM = 1072,
3955	TLBGR_MM = 1073,	3955	TLBGR_MM = 1073,
3956	TLBGWI_MM = 1074,	3956	TLBGWI_MM = 1074,
3957	TLBGWR_MM = 1075,	3957	TLBGWR_MM = 1075,
3958	MFGC0_MM = 1076,	3958	MFGC0_MM = 1076,
3959	MFHGC0_MM = 1077,	3959	MFHGC0_MM = 1077,
3960	MTGC0_MM = 1078,	3960	MTGC0_MM = 1078,
3961	MTHGC0_MM = 1079,	3961	MTHGC0_MM = 1079,
3962	SC_MMR6 = 1080,	3962	SC_MMR6 = 1080,
3963	LDC2_R6 = 1081,	3963	LDC2_R6 = 1081,
3964	LL_R6 = 1082,	3964	LL_R6 = 1082,
3965	LWC2_R6 = 1083,	3965	LWC2_R6 = 1083,
3966	SWC2_R6 = 1084,	3966	SWC2_R6 = 1084,
3967	SDC2_R6 = 1085,	3967	SDC2_R6 = 1085,
3968	SC_R6 = 1086,	3968	SC_R6 = 1086,
3969	PREF_R6 = 1087,	3969	PREF_R6 = 1087,
3970	CACHE_R6 = 1088,	3970	CACHE_R6 = 1088,
3971	GINVI = 1089,	3971	GINVI = 1089,
3972	GINVT = 1090,	3972	GINVT = 1090,
3973	LBE_MM = 1091,	3973	LBE_MM = 1091,
3974	LBuE_MM = 1092,	3974	LBuE_MM = 1092,
3975	LHE_MM = 1093,	3975	LHE_MM = 1093,
3976	LHuE_MM = 1094,	3976	LHuE_MM = 1094,
3977	LWE_MM = 1095,	3977	LWE_MM = 1095,
3978	LWLE_MM = 1096,	3978	LWLE_MM = 1096,
3979	LWRE_MM = 1097,	3979	LWRE_MM = 1097,
3980	LLE_MM = 1098,	3980	LLE_MM = 1098,
3981	SBE_MM = 1099,	3981	SBE_MM = 1099,
3982	SB_MM = 1100,	3982	SB_MM = 1100,
3983	SHE_MM = 1101,	3983	SHE_MM = 1101,
3984	SWE_MM = 1102,	3984	SWE_MM = 1102,
3985	SWLE_MM = 1103,	3985	SWLE_MM = 1103,
3986	SWRE_MM = 1104,	3986	SWRE_MM = 1104,
3987	SCE_MM = 1105,	3987	SCE_MM = 1105,
3988	PREFE_MM = 1106,	3988	PREFE_MM = 1106,
3989	CACHEE_MM = 1107,	3989	CACHEE_MM = 1107,
3990	Restore16_RestoreX16 = 1108,	3990	Restore16_RestoreX16 = 1108,
3991	LbRxRyOffMemX16 = 1109,	3991	LbRxRyOffMemX16 = 1109,
3992	LbuRxRyOffMemX16 = 1110,	3992	LbuRxRyOffMemX16 = 1110,
3993	LhRxRyOffMemX16 = 1111,	3993	LhRxRyOffMemX16 = 1111,
3994	LhuRxRyOffMemX16 = 1112,	3994	LhuRxRyOffMemX16 = 1112,
3995	LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113,	3995	LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113,
3996	Save16_SaveX16 = 1114,	3996	Save16_SaveX16 = 1114,
3997	SbRxRyOffMemX16 = 1115,	3997	SbRxRyOffMemX16 = 1115,
3998	ShRxRyOffMemX16 = 1116,	3998	ShRxRyOffMemX16 = 1116,
3999	SwRxRyOffMemX16_SwRxSpImmX16 = 1117,	3999	SwRxRyOffMemX16_SwRxSpImmX16 = 1117,
4000	LBU16_MM_LBu_MM = 1118,	4000	LBU16_MM_LBu_MM = 1118,
4001	LB_MM = 1119,	4001	LB_MM = 1119,
4002	LHU16_MM_LHu_MM = 1120,	4002	LHU16_MM_LHu_MM = 1120,
4003	LH_MM = 1121,	4003	LH_MM = 1121,
4004	LL_MM = 1122,	4004	LL_MM = 1122,
4005	LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123,	4005	LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123,
4006	LWL_MM = 1124,	4006	LWL_MM = 1124,
4007	LWM16_MM_LWM32_MM = 1125,	4007	LWM16_MM_LWM32_MM = 1125,
4008	LWP_MM = 1126,	4008	LWP_MM = 1126,
4009	LWR_MM = 1127,	4009	LWR_MM = 1127,
4010	LWU_MM = 1128,	4010	LWU_MM = 1128,
4011	LWXS_MM = 1129,	4011	LWXS_MM = 1129,
4012	SB16_MM = 1130,	4012	SB16_MM = 1130,
4013	SC_MM = 1131,	4013	SC_MM = 1131,
4014	SH16_MM_SH_MM = 1132,	4014	SH16_MM_SH_MM = 1132,
4015	SW16_MM_SWSP_MM_SW_MM = 1133,	4015	SW16_MM_SWSP_MM_SW_MM = 1133,
4016	SWL_MM = 1134,	4016	SWL_MM = 1134,
4017	SWM16_MM_SWM32_MM = 1135,	4017	SWM16_MM_SWM32_MM = 1135,
4018	SWM_MM = 1136,	4018	SWM_MM = 1136,
4019	SWP_MM = 1137,	4019	SWP_MM = 1137,
4020	SWR_MM = 1138,	4020	SWR_MM = 1138,
4021	PREF_MM_PREFX_MM = 1139,	4021	PREF_MM_PREFX_MM = 1139,
4022	CACHE_MM = 1140,	4022	CACHE_MM = 1140,
4023	SYNC_MM = 1141,	4023	SYNC_MM = 1141,
4024	SYNCI_MM = 1142,	4024	SYNCI_MM = 1142,
4025	GINVI_MMR6 = 1143,	4025	GINVI_MMR6 = 1143,
4026	GINVT_MMR6 = 1144,	4026	GINVT_MMR6 = 1144,
4027	LBU_MMR6 = 1145,	4027	LBU_MMR6 = 1145,
4028	LB_MMR6 = 1146,	4028	LB_MMR6 = 1146,
4029	LDC2_MMR6 = 1147,	4029	LDC2_MMR6 = 1147,
4030	LL_MMR6 = 1148,	4030	LL_MMR6 = 1148,
4031	LWM16_MMR6 = 1149,	4031	LWM16_MMR6 = 1149,
4032	LWC2_MMR6 = 1150,	4032	LWC2_MMR6 = 1150,
4033	LWPC_MMR6 = 1151,	4033	LWPC_MMR6 = 1151,
4034	LW_MMR6 = 1152,	4034	LW_MMR6 = 1152,
4035	SB16_MMR6_SB_MMR6 = 1153,	4035	SB16_MMR6_SB_MMR6 = 1153,
4036	SDC2_MMR6 = 1154,	4036	SDC2_MMR6 = 1154,
4037	SH16_MMR6_SH_MMR6 = 1155,	4037	SH16_MMR6_SH_MMR6 = 1155,
4038	SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156,	4038	SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156,
4039	SWC2_MMR6 = 1157,	4039	SWC2_MMR6 = 1157,
4040	SWM16_MMR6 = 1158,	4040	SWM16_MMR6 = 1158,
4041	SYNC_MMR6 = 1159,	4041	SYNC_MMR6 = 1159,
4042	SYNCI_MMR6 = 1160,	4042	SYNCI_MMR6 = 1160,
4043	PREF_MMR6 = 1161,	4043	PREF_MMR6 = 1161,
4044	CACHE_MMR6 = 1162,	4044	CACHE_MMR6 = 1162,
4045	LD = 1163,	4045	LD = 1163,
4046	LL64_LLD = 1164,	4046	LL64_LLD = 1164,
4047	LWu = 1165,	4047	LWu = 1165,
4048	LB64 = 1166,	4048	LB64 = 1166,
4049	LBu64 = 1167,	4049	LBu64 = 1167,
4050	LH64 = 1168,	4050	LH64 = 1168,
4051	LHu64 = 1169,	4051	LHu64 = 1169,
4052	LW64 = 1170,	4052	LW64 = 1170,
4053	LWL64 = 1171,	4053	LWL64 = 1171,
4054	LWR64 = 1172,	4054	LWR64 = 1172,
4055	LDL = 1173,	4055	LDL = 1173,
4056	LDR = 1174,	4056	LDR = 1174,
4057	SD = 1175,	4057	SD = 1175,
4058	SC64_SCD = 1176,	4058	SC64_SCD = 1176,
4059	SB64 = 1177,	4059	SB64 = 1177,
4060	SH64 = 1178,	4060	SH64 = 1178,
4061	SW64 = 1179,	4061	SW64 = 1179,
4062	SWL64 = 1180,	4062	SWL64 = 1180,
4063	SWR64 = 1181,	4063	SWR64 = 1181,
4064	SDL = 1182,	4064	SDL = 1182,
4065	SDR = 1183,	4065	SDR = 1183,
4066	LWUPC = 1184,	4066	LWUPC = 1184,
4067	LDPC = 1185,	4067	LDPC = 1185,
4068	LLD_R6 = 1186,	4068	LLD_R6 = 1186,
4069	LL64_R6 = 1187,	4069	LL64_R6 = 1187,
4070	SC64_R6 = 1188,	4070	SC64_R6 = 1188,
4071	SCD_R6 = 1189,	4071	SCD_R6 = 1189,
4072	CRC32B = 1190,	4072	CRC32B = 1190,
4073	CRC32H = 1191,	4073	CRC32H = 1191,
4074	CRC32W = 1192,	4074	CRC32W = 1192,
4075	CRC32CB = 1193,	4075	CRC32CB = 1193,
4076	CRC32CH = 1194,	4076	CRC32CH = 1194,
4077	CRC32CW = 1195,	4077	CRC32CW = 1195,
4078	CRC32D = 1196,	4078	CRC32D = 1196,
4079	CRC32CD = 1197,	4079	CRC32CD = 1197,
4080	BADDu = 1198,	4080	BADDu = 1198,
4081	BBIT0_BBIT032_BBIT1_BBIT132 = 1199,	4081	BBIT0_BBIT032_BBIT1_BBIT132 = 1199,
4082	CINS_CINS32_CINS64_32_CINS_i32 = 1200,	4082	CINS_CINS32_CINS64_32_CINS_i32 = 1200,
4083	DMFC2_OCTEON = 1201,	4083	DMFC2_OCTEON = 1201,
4084	DMTC2_OCTEON = 1202,	4084	DMTC2_OCTEON = 1202,
4085	DPOP_POP = 1203,	4085	DPOP_POP = 1203,
4086	EXTS_EXTS32 = 1204,	4086	EXTS_EXTS32 = 1204,
4087	MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205,	4087	MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205,
4088	SEQ_SNE = 1206,	4088	SEQ_SNE = 1206,
4089	SEQi_SNEi = 1207,	4089	SEQi_SNEi = 1207,
4090	V3MULU_VMM0_VMULU = 1208,	4090	V3MULU_VMM0_VMULU = 1208,
4091	DMUL = 1209,	4091	DMUL = 1209,
4092	SAA_SAAD = 1210,	4092	SAA_SAAD = 1210,
4093	ADDR_PS64 = 1211,	4093	ADDR_PS64 = 1211,
4094	CVT_PS_PW64_CVT_PW_PS64 = 1212,	4094	CVT_PS_PW64_CVT_PW_PS64 = 1212,
4095	MULR_PS64 = 1213,	4095	MULR_PS64 = 1213,
4096	PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214,	4096	PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214,
4097	MOVT_I64 = 1215,	4097	MOVT_I64 = 1215,
4098	MOVF_I64 = 1216,	4098	MOVF_I64 = 1216,
4099	MOVZ_I64_S = 1217,	4099	MOVZ_I64_S = 1217,
4100	MOVN_I64_D64 = 1218,	4100	MOVN_I64_D64 = 1218,
4101	MOVN_I64_S = 1219,	4101	MOVN_I64_S = 1219,
4102	MOVZ_I64_D64 = 1220,	4102	MOVZ_I64_D64 = 1220,
4103	SELEQZ_S_SELNEZ_S = 1221,	4103	SELEQZ_S_SELNEZ_S = 1221,
4104	SELEQZ_D_SELNEZ_D = 1222,	4104	SELEQZ_D_SELNEZ_D = 1222,
4105	MAX_S_MAXA_S = 1223,	4105	MAX_S_MAXA_S = 1223,
4106	MAX_D_MAXA_D = 1224,	4106	MAX_D_MAXA_D = 1224,
4107	MIN_S_MINA_D = 1225,	4107	MIN_S_MINA_D = 1225,
4108	MIN_D_MINA_S = 1226,	4108	MIN_D_MINA_S = 1226,
4109	CLASS_S = 1227,	4109	CLASS_S = 1227,
4110	CLASS_D = 1228,	4110	CLASS_D = 1228,
4111	RINT_S = 1229,	4111	RINT_S = 1229,
4112	RINT_D = 1230,	4112	RINT_D = 1230,
4113	BC1EQZ_BC1NEZ = 1231,	4113	BC1EQZ_BC1NEZ = 1231,
4114	SEL_D = 1232,	4114	SEL_D = 1232,
4115	SEL_S = 1233,	4115	SEL_S = 1233,
4116	MADDF_S = 1234,	4116	MADDF_S = 1234,
4117	MSUBF_S = 1235,	4117	MSUBF_S = 1235,
4118	MADDF_D = 1236,	4118	MADDF_D = 1236,
4119	MSUBF_D = 1237,	4119	MSUBF_D = 1237,
4120	MOVF_D32_MM = 1238,	4120	MOVF_D32_MM = 1238,
4121	MOVF_S_MM = 1239,	4121	MOVF_S_MM = 1239,
4122	MOVN_I_D32_MM = 1240,	4122	MOVN_I_D32_MM = 1240,
4123	MOVN_I_S_MM = 1241,	4123	MOVN_I_S_MM = 1241,
4124	MOVT_D32_MM = 1242,	4124	MOVT_D32_MM = 1242,
4125	MOVT_S_MM = 1243,	4125	MOVT_S_MM = 1243,
4126	MOVZ_I_D32_MM = 1244,	4126	MOVZ_I_D32_MM = 1244,
4127	MOVZ_I_S_MM = 1245,	4127	MOVZ_I_S_MM = 1245,
4128	CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246,	4128	CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246,
4129	CEIL_W_MM_CEIL_W_S_MM = 1247,	4129	CEIL_W_MM_CEIL_W_S_MM = 1247,
4130	FLOOR_W_MM_FLOOR_W_S_MM = 1248,	4130	FLOOR_W_MM_FLOOR_W_S_MM = 1248,
4131	NMADD_S_MM = 1249,	4131	NMADD_S_MM = 1249,
4132	NMADD_D32_MM = 1250,	4132	NMADD_D32_MM = 1250,
4133	NMSUB_S_MM = 1251,	4133	NMSUB_S_MM = 1251,
4134	NMSUB_D32_MM = 1252,	4134	NMSUB_D32_MM = 1252,
4135	MADD_S_MM = 1253,	4135	MADD_S_MM = 1253,
4136	MADD_D32_MM = 1254,	4136	MADD_D32_MM = 1254,
4137	ROUND_W_MM_ROUND_W_S_MM = 1255,	4137	ROUND_W_MM_ROUND_W_S_MM = 1255,
4138	TRUNC_W_MM_TRUNC_W_S_MM = 1256,	4138	TRUNC_W_MM_TRUNC_W_S_MM = 1256,
4139	C_F_D32_MM_C_F_D64_MM = 1257,	4139	C_F_D32_MM_C_F_D64_MM = 1257,
4140	C_F_S_MM = 1258,	4140	C_F_S_MM = 1258,
4141	C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259,	4141	C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259,
4142	C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260,	4142	C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260,
4143	C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261,	4143	C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261,
4144	C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262,	4144	C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262,
4145	C_NGLE_D32_MM_C_NGLE_D64_MM = 1263,	4145	C_NGLE_D32_MM_C_NGLE_D64_MM = 1263,
4146	C_NGLE_S_MM = 1264,	4146	C_NGLE_S_MM = 1264,
4147	FCMP_S32_MM = 1265,	4147	FCMP_S32_MM = 1265,
4148	FCMP_D32_MM = 1266,	4148	FCMP_D32_MM = 1266,
4149	MFC1_MM = 1267,	4149	MFC1_MM = 1267,
4150	MFHC1_D32_MM_MFHC1_D64_MM = 1268,	4150	MFHC1_D32_MM_MFHC1_D64_MM = 1268,
4151	MTC1_MM_MTC1_D64_MM = 1269,	4151	MTC1_MM_MTC1_D64_MM = 1269,
4152	MTHC1_D32_MM_MTHC1_D64_MM = 1270,	4152	MTHC1_D32_MM_MTHC1_D64_MM = 1270,
4153	FABS_D32_MM_FABS_D64_MM = 1271,	4153	FABS_D32_MM_FABS_D64_MM = 1271,
4154	FABS_S_MM = 1272,	4154	FABS_S_MM = 1272,
4155	FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273,	4155	FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273,
4156	FADD_D32_MM_FADD_D64_MM = 1274,	4156	FADD_D32_MM_FADD_D64_MM = 1274,
4157	FADD_S_MM = 1275,	4157	FADD_S_MM = 1275,
4158	FMOV_D32_MM_FMOV_D64_MM = 1276,	4158	FMOV_D32_MM_FMOV_D64_MM = 1276,
4159	FMOV_S_MM = 1277,	4159	FMOV_S_MM = 1277,
4160	FMUL_D32_MM_FMUL_D64_MM = 1278,	4160	FMUL_D32_MM_FMUL_D64_MM = 1278,
4161	FMUL_S_MM = 1279,	4161	FMUL_S_MM = 1279,
4162	FSUB_D32_MM_FSUB_D64_MM = 1280,	4162	FSUB_D32_MM_FSUB_D64_MM = 1280,
4163	FSUB_S_MM = 1281,	4163	FSUB_S_MM = 1281,
4164	MSUB_S_MM = 1282,	4164	MSUB_S_MM = 1282,
4165	MSUB_D32_MM = 1283,	4165	MSUB_D32_MM = 1283,
4166	FDIV_S_MM = 1284,	4166	FDIV_S_MM = 1284,
4167	FDIV_D32_MM_FDIV_D64_MM = 1285,	4167	FDIV_D32_MM_FDIV_D64_MM = 1285,
4168	FSQRT_S_MM = 1286,	4168	FSQRT_S_MM = 1286,
4169	FSQRT_D32_MM_FSQRT_D64_MM = 1287,	4169	FSQRT_D32_MM_FSQRT_D64_MM = 1287,
4170	RECIP_S_MM_RSQRT_S_MM = 1288,	4170	RECIP_S_MM_RSQRT_S_MM = 1288,
4171	RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289,	4171	RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289,
4172	SDC1_MM_D32_SDC1_MM_D64 = 1290,	4172	SDC1_MM_D32_SDC1_MM_D64 = 1290,
4173	SWC1_MM = 1291,	4173	SWC1_MM = 1291,
4174	SUXC1_MM = 1292,	4174	SUXC1_MM = 1292,
4175	SWXC1_MM = 1293,	4175	SWXC1_MM = 1293,
4176	CFC1_MM = 1294,	4176	CFC1_MM = 1294,
4177	CTC1_MM = 1295,	4177	CTC1_MM = 1295,
4178	LDC1_MM_D32_LDC1_MM_D64 = 1296,	4178	LDC1_MM_D32_LDC1_MM_D64 = 1296,
4179	LUXC1_MM = 1297,	4179	LUXC1_MM = 1297,
4180	LWC1_MM = 1298,	4180	LWC1_MM = 1298,
4181	LWXC1_MM = 1299,	4181	LWXC1_MM = 1299,
4182	FNEG_S_MMR6 = 1300,	4182	FNEG_S_MMR6 = 1300,
4183	CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301,	4183	CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301,
4184	CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302,	4184	CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302,
4185	CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303,	4185	CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303,
4186	CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304,	4186	CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304,
4187	CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305,	4187	CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305,
4188	CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306,	4188	CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306,
4189	CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307,	4189	CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307,
4190	TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308,	4190	TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308,
4191	ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309,	4191	ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309,
4192	FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310,	4192	FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310,
4193	CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311,	4193	CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311,
4194	MFC1_MMR6 = 1312,	4194	MFC1_MMR6 = 1312,
4195	MTC1_MMR6 = 1313,	4195	MTC1_MMR6 = 1313,
4196	CLASS_S_MMR6_CLASS_D_MMR6 = 1314,	4196	CLASS_S_MMR6_CLASS_D_MMR6 = 1314,
4197	FADD_S_MMR6 = 1315,	4197	FADD_S_MMR6 = 1315,
4198	MAX_D_MMR6 = 1316,	4198	MAX_D_MMR6 = 1316,
4199	MAX_S_MMR6 = 1317,	4199	MAX_S_MMR6 = 1317,
4200	MIN_D_MMR6 = 1318,	4200	MIN_D_MMR6 = 1318,
4201	MIN_S_MMR6 = 1319,	4201	MIN_S_MMR6 = 1319,
4202	MAXA_D_MMR6 = 1320,	4202	MAXA_D_MMR6 = 1320,
4203	MAXA_S_MMR6 = 1321,	4203	MAXA_S_MMR6 = 1321,
4204	MINA_D_MMR6 = 1322,	4204	MINA_D_MMR6 = 1322,
4205	MINA_S_MMR6 = 1323,	4205	MINA_S_MMR6 = 1323,
4206	SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324,	4206	SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324,
4207	SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325,	4207	SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325,
4208	SEL_D_MMR6 = 1326,	4208	SEL_D_MMR6 = 1326,
4209	SEL_S_MMR6 = 1327,	4209	SEL_S_MMR6 = 1327,
4210	RINT_S_MMR6_RINT_D_MMR6 = 1328,	4210	RINT_S_MMR6_RINT_D_MMR6 = 1328,
4211	MADDF_D_MMR6 = 1329,	4211	MADDF_D_MMR6 = 1329,
4212	MADDF_S_MMR6 = 1330,	4212	MADDF_S_MMR6 = 1330,
4213	MSUBF_D_MMR6 = 1331,	4213	MSUBF_D_MMR6 = 1331,
4214	MSUBF_S_MMR6 = 1332,	4214	MSUBF_S_MMR6 = 1332,
4215	FMOV_S_MMR6 = 1333,	4215	FMOV_S_MMR6 = 1333,
4216	FMUL_S_MMR6 = 1334,	4216	FMUL_S_MMR6 = 1334,
4217	FSUB_S_MMR6 = 1335,	4217	FSUB_S_MMR6 = 1335,
4218	FMOV_D_MMR6 = 1336,	4218	FMOV_D_MMR6 = 1336,
4219	FDIV_S_MMR6 = 1337,	4219	FDIV_S_MMR6 = 1337,
4220	SDC1_D64_MMR6 = 1338,	4220	SDC1_D64_MMR6 = 1338,
4221	LDC1_D64_MMR6 = 1339,	4221	LDC1_D64_MMR6 = 1339,
4222	DMFC1 = 1340,	4222	DMFC1 = 1340,
4223	DMTC1 = 1341,	4223	DMTC1 = 1341,
4224	SWDSP = 1342,	4224	SWDSP = 1342,
4225	LWDSP = 1343,	4225	LWDSP = 1343,
4226	PseudoMTLOHI_DSP = 1344,	4226	PseudoMTLOHI_DSP = 1344,
4227	EXTRV_RS_W = 1345,	4227	EXTRV_RS_W = 1345,
4228	EXTRV_R_W = 1346,	4228	EXTRV_R_W = 1346,
4229	EXTRV_S_H = 1347,	4229	EXTRV_S_H = 1347,
4230	EXTRV_W = 1348,	4230	EXTRV_W = 1348,
4231	EXTR_RS_W = 1349,	4231	EXTR_RS_W = 1349,
4232	EXTR_R_W = 1350,	4232	EXTR_R_W = 1350,
4233	EXTR_S_H = 1351,	4233	EXTR_S_H = 1351,
4234	EXTR_W = 1352,	4234	EXTR_W = 1352,
4235	INSV = 1353,	4235	INSV = 1353,
4236	MTHLIP = 1354,	4236	MTHLIP = 1354,
4237	MTHI_DSP = 1355,	4237	MTHI_DSP = 1355,
4238	MTLO_DSP = 1356,	4238	MTLO_DSP = 1356,
4239	ABSQ_S_PH = 1357,	4239	ABSQ_S_PH = 1357,
4240	ABSQ_S_W = 1358,	4240	ABSQ_S_W = 1358,
4241	ADDQ_PH = 1359,	4241	ADDQ_PH = 1359,
4242	ADDQ_S_PH = 1360,	4242	ADDQ_S_PH = 1360,
4243	ADDQ_S_W = 1361,	4243	ADDQ_S_W = 1361,
4244	ADDSC = 1362,	4244	ADDSC = 1362,
4245	ADDU_QB = 1363,	4245	ADDU_QB = 1363,
4246	ADDU_S_QB = 1364,	4246	ADDU_S_QB = 1364,
4247	ADDWC = 1365,	4247	ADDWC = 1365,
4248	BITREV = 1366,	4248	BITREV = 1366,
4249	BPOSGE32 = 1367,	4249	BPOSGE32 = 1367,
4250	CMPGU_EQ_QB = 1368,	4250	CMPGU_EQ_QB = 1368,
4251	CMPGU_LE_QB = 1369,	4251	CMPGU_LE_QB = 1369,
4252	CMPGU_LT_QB = 1370,	4252	CMPGU_LT_QB = 1370,
4253	CMPU_EQ_QB = 1371,	4253	CMPU_EQ_QB = 1371,
4254	CMPU_LE_QB = 1372,	4254	CMPU_LE_QB = 1372,
4255	CMPU_LT_QB = 1373,	4255	CMPU_LT_QB = 1373,
4256	CMP_EQ_PH = 1374,	4256	CMP_EQ_PH = 1374,
4257	CMP_LE_PH = 1375,	4257	CMP_LE_PH = 1375,
4258	CMP_LT_PH = 1376,	4258	CMP_LT_PH = 1376,
4259	DPAQ_SA_L_W = 1377,	4259	DPAQ_SA_L_W = 1377,
4260	DPAQ_S_W_PH = 1378,	4260	DPAQ_S_W_PH = 1378,
4261	DPAU_H_QBL = 1379,	4261	DPAU_H_QBL = 1379,
4262	DPAU_H_QBR = 1380,	4262	DPAU_H_QBR = 1380,
4263	DPSQ_SA_L_W = 1381,	4263	DPSQ_SA_L_W = 1381,
4264	DPSQ_S_W_PH = 1382,	4264	DPSQ_S_W_PH = 1382,
4265	DPSU_H_QBL = 1383,	4265	DPSU_H_QBL = 1383,
4266	DPSU_H_QBR = 1384,	4266	DPSU_H_QBR = 1384,
4267	EXTPDPV = 1385,	4267	EXTPDPV = 1385,
4268	EXTPDP = 1386,	4268	EXTPDP = 1386,
4269	EXTPV = 1387,	4269	EXTPV = 1387,
4270	EXTP = 1388,	4270	EXTP = 1388,
4271	LBUX = 1389,	4271	LBUX = 1389,
4272	LHX = 1390,	4272	LHX = 1390,
4273	LWX = 1391,	4273	LWX = 1391,
4274	MADDU_DSP = 1392,	4274	MADDU_DSP = 1392,
4275	MADD_DSP = 1393,	4275	MADD_DSP = 1393,
4276	MAQ_SA_W_PHL = 1394,	4276	MAQ_SA_W_PHL = 1394,
4277	MAQ_SA_W_PHR = 1395,	4277	MAQ_SA_W_PHR = 1395,
4278	MAQ_S_W_PHL = 1396,	4278	MAQ_S_W_PHL = 1396,
4279	MAQ_S_W_PHR = 1397,	4279	MAQ_S_W_PHR = 1397,
4280	MFHI_DSP = 1398,	4280	MFHI_DSP = 1398,
4281	MFLO_DSP = 1399,	4281	MFLO_DSP = 1399,
4282	MODSUB = 1400,	4282	MODSUB = 1400,
4283	MSUBU_DSP = 1401,	4283	MSUBU_DSP = 1401,
4284	MSUB_DSP = 1402,	4284	MSUB_DSP = 1402,
4285	MULEQ_S_W_PHL = 1403,	4285	MULEQ_S_W_PHL = 1403,
4286	MULEQ_S_W_PHR = 1404,	4286	MULEQ_S_W_PHR = 1404,
4287	MULEU_S_PH_QBL = 1405,	4287	MULEU_S_PH_QBL = 1405,
4288	MULEU_S_PH_QBR = 1406,	4288	MULEU_S_PH_QBR = 1406,
4289	MULQ_RS_PH = 1407,	4289	MULQ_RS_PH = 1407,
4290	MULSAQ_S_W_PH = 1408,	4290	MULSAQ_S_W_PH = 1408,
4291	MULTU_DSP = 1409,	4291	MULTU_DSP = 1409,
4292	MULT_DSP = 1410,	4292	MULT_DSP = 1410,
4293	PACKRL_PH = 1411,	4293	PACKRL_PH = 1411,
4294	PICK_PH = 1412,	4294	PICK_PH = 1412,
4295	PICK_QB = 1413,	4295	PICK_QB = 1413,
4296	PRECEQU_PH_QBLA = 1414,	4296	PRECEQU_PH_QBLA = 1414,
4297	PRECEQU_PH_QBL = 1415,	4297	PRECEQU_PH_QBL = 1415,
4298	PRECEQU_PH_QBRA = 1416,	4298	PRECEQU_PH_QBRA = 1416,
4299	PRECEQU_PH_QBR = 1417,	4299	PRECEQU_PH_QBR = 1417,
4300	PRECEQ_W_PHL = 1418,	4300	PRECEQ_W_PHL = 1418,
4301	PRECEQ_W_PHR = 1419,	4301	PRECEQ_W_PHR = 1419,
4302	PRECEU_PH_QBLA = 1420,	4302	PRECEU_PH_QBLA = 1420,
4303	PRECEU_PH_QBL = 1421,	4303	PRECEU_PH_QBL = 1421,
4304	PRECEU_PH_QBRA = 1422,	4304	PRECEU_PH_QBRA = 1422,
4305	PRECEU_PH_QBR = 1423,	4305	PRECEU_PH_QBR = 1423,
4306	PRECRQU_S_QB_PH = 1424,	4306	PRECRQU_S_QB_PH = 1424,
4307	PRECRQ_PH_W = 1425,	4307	PRECRQ_PH_W = 1425,
4308	PRECRQ_QB_PH = 1426,	4308	PRECRQ_QB_PH = 1426,
4309	PRECRQ_RS_PH_W = 1427,	4309	PRECRQ_RS_PH_W = 1427,
4310	RADDU_W_QB = 1428,	4310	RADDU_W_QB = 1428,
4311	RDDSP = 1429,	4311	RDDSP = 1429,
4312	REPLV_PH = 1430,	4312	REPLV_PH = 1430,
4313	REPLV_QB = 1431,	4313	REPLV_QB = 1431,
4314	REPL_PH = 1432,	4314	REPL_PH = 1432,
4315	REPL_QB = 1433,	4315	REPL_QB = 1433,
4316	SHILOV = 1434,	4316	SHILOV = 1434,
4317	SHILO = 1435,	4317	SHILO = 1435,
4318	SHLLV_PH = 1436,	4318	SHLLV_PH = 1436,
4319	SHLLV_QB = 1437,	4319	SHLLV_QB = 1437,
4320	SHLLV_S_PH = 1438,	4320	SHLLV_S_PH = 1438,
4321	SHLLV_S_W = 1439,	4321	SHLLV_S_W = 1439,
4322	SHLL_PH = 1440,	4322	SHLL_PH = 1440,
4323	SHLL_QB = 1441,	4323	SHLL_QB = 1441,
4324	SHLL_S_PH = 1442,	4324	SHLL_S_PH = 1442,
4325	SHLL_S_W = 1443,	4325	SHLL_S_W = 1443,
4326	SHRAV_PH = 1444,	4326	SHRAV_PH = 1444,
4327	SHRAV_R_PH = 1445,	4327	SHRAV_R_PH = 1445,
4328	SHRAV_R_W = 1446,	4328	SHRAV_R_W = 1446,
4329	SHRA_PH = 1447,	4329	SHRA_PH = 1447,
4330	SHRA_R_PH = 1448,	4330	SHRA_R_PH = 1448,
4331	SHRA_R_W = 1449,	4331	SHRA_R_W = 1449,
4332	SHRLV_QB = 1450,	4332	SHRLV_QB = 1450,
4333	SHRL_QB = 1451,	4333	SHRL_QB = 1451,
4334	SUBQ_PH = 1452,	4334	SUBQ_PH = 1452,
4335	SUBQ_S_PH = 1453,	4335	SUBQ_S_PH = 1453,
4336	SUBQ_S_W = 1454,	4336	SUBQ_S_W = 1454,
4337	SUBU_QB = 1455,	4337	SUBU_QB = 1455,
4338	SUBU_S_QB = 1456,	4338	SUBU_S_QB = 1456,
4339	WRDSP = 1457,	4339	WRDSP = 1457,
4340	PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458,	4340	PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458,
4341	PseudoPICK_PH_PseudoPICK_QB = 1459,	4341	PseudoPICK_PH_PseudoPICK_QB = 1459,
4342	ABSQ_S_QB = 1460,	4342	ABSQ_S_QB = 1460,
4343	ADDQH_PH = 1461,	4343	ADDQH_PH = 1461,
4344	ADDQH_R_PH = 1462,	4344	ADDQH_R_PH = 1462,
4345	ADDQH_R_W = 1463,	4345	ADDQH_R_W = 1463,
4346	ADDQH_W = 1464,	4346	ADDQH_W = 1464,
4347	ADDUH_QB = 1465,	4347	ADDUH_QB = 1465,
4348	ADDUH_R_QB = 1466,	4348	ADDUH_R_QB = 1466,
4349	ADDU_PH = 1467,	4349	ADDU_PH = 1467,
4350	ADDU_S_PH = 1468,	4350	ADDU_S_PH = 1468,
4351	APPEND = 1469,	4351	APPEND = 1469,
4352	BALIGN = 1470,	4352	BALIGN = 1470,
4353	CMPGDU_EQ_QB = 1471,	4353	CMPGDU_EQ_QB = 1471,
4354	CMPGDU_LE_QB = 1472,	4354	CMPGDU_LE_QB = 1472,
4355	CMPGDU_LT_QB = 1473,	4355	CMPGDU_LT_QB = 1473,
4356	DPA_W_PH = 1474,	4356	DPA_W_PH = 1474,
4357	DPAQX_SA_W_PH = 1475,	4357	DPAQX_SA_W_PH = 1475,
4358	DPAQX_S_W_PH = 1476,	4358	DPAQX_S_W_PH = 1476,
4359	DPAX_W_PH = 1477,	4359	DPAX_W_PH = 1477,
4360	DPS_W_PH = 1478,	4360	DPS_W_PH = 1478,
4361	DPSQX_S_W_PH = 1479,	4361	DPSQX_S_W_PH = 1479,
4362	DPSQX_SA_W_PH = 1480,	4362	DPSQX_SA_W_PH = 1480,
4363	DPSX_W_PH = 1481,	4363	DPSX_W_PH = 1481,
4364	MUL_PH = 1482,	4364	MUL_PH = 1482,
4365	MUL_S_PH = 1483,	4365	MUL_S_PH = 1483,
4366	MULQ_RS_W = 1484,	4366	MULQ_RS_W = 1484,
4367	MULQ_S_PH = 1485,	4367	MULQ_S_PH = 1485,
4368	MULQ_S_W = 1486,	4368	MULQ_S_W = 1486,
4369	MULSA_W_PH = 1487,	4369	MULSA_W_PH = 1487,
4370	PRECR_QB_PH = 1488,	4370	PRECR_QB_PH = 1488,
4371	PRECR_SRA_PH_W = 1489,	4371	PRECR_SRA_PH_W = 1489,
4372	PRECR_SRA_R_PH_W = 1490,	4372	PRECR_SRA_R_PH_W = 1490,
4373	PREPEND = 1491,	4373	PREPEND = 1491,
4374	SHRA_QB = 1492,	4374	SHRA_QB = 1492,
4375	SHRA_R_QB = 1493,	4375	SHRA_R_QB = 1493,
4376	SHRAV_QB = 1494,	4376	SHRAV_QB = 1494,
4377	SHRAV_R_QB = 1495,	4377	SHRAV_R_QB = 1495,
4378	SHRL_PH = 1496,	4378	SHRL_PH = 1496,
4379	SHRLV_PH = 1497,	4379	SHRLV_PH = 1497,
4380	SUBQH_PH = 1498,	4380	SUBQH_PH = 1498,
4381	SUBQH_R_PH = 1499,	4381	SUBQH_R_PH = 1499,
4382	SUBQH_W = 1500,	4382	SUBQH_W = 1500,
4383	SUBQH_R_W = 1501,	4383	SUBQH_R_W = 1501,
4384	SUBU_PH = 1502,	4384	SUBU_PH = 1502,
4385	SUBU_S_PH = 1503,	4385	SUBU_S_PH = 1503,
4386	SUBUH_QB = 1504,	4386	SUBUH_QB = 1504,
4387	SUBUH_R_QB = 1505,	4387	SUBUH_R_QB = 1505,
4388	LWDSP_MM = 1506,	4388	LWDSP_MM = 1506,
4389	SWDSP_MM = 1507,	4389	SWDSP_MM = 1507,
4390	ABSQ_S_PH_MM = 1508,	4390	ABSQ_S_PH_MM = 1508,
4391	ABSQ_S_W_MM = 1509,	4391	ABSQ_S_W_MM = 1509,
4392	ADDQ_PH_MM = 1510,	4392	ADDQ_PH_MM = 1510,
4393	ADDQ_S_PH_MM = 1511,	4393	ADDQ_S_PH_MM = 1511,
4394	ADDQ_S_W_MM = 1512,	4394	ADDQ_S_W_MM = 1512,
4395	ADDSC_MM = 1513,	4395	ADDSC_MM = 1513,
4396	ADDU_QB_MM = 1514,	4396	ADDU_QB_MM = 1514,
4397	ADDU_S_QB_MM = 1515,	4397	ADDU_S_QB_MM = 1515,
4398	ADDWC_MM = 1516,	4398	ADDWC_MM = 1516,
4399	BITREV_MM = 1517,	4399	BITREV_MM = 1517,
4400	BPOSGE32_MM = 1518,	4400	BPOSGE32_MM = 1518,
4401	CMPGU_EQ_QB_MM = 1519,	4401	CMPGU_EQ_QB_MM = 1519,
4402	CMPGU_LE_QB_MM = 1520,	4402	CMPGU_LE_QB_MM = 1520,
4403	CMPGU_LT_QB_MM = 1521,	4403	CMPGU_LT_QB_MM = 1521,
4404	CMPU_EQ_QB_MM = 1522,	4404	CMPU_EQ_QB_MM = 1522,
4405	CMPU_LE_QB_MM = 1523,	4405	CMPU_LE_QB_MM = 1523,
4406	CMPU_LT_QB_MM = 1524,	4406	CMPU_LT_QB_MM = 1524,
4407	CMP_EQ_PH_MM = 1525,	4407	CMP_EQ_PH_MM = 1525,
4408	CMP_LE_PH_MM = 1526,	4408	CMP_LE_PH_MM = 1526,
4409	CMP_LT_PH_MM = 1527,	4409	CMP_LT_PH_MM = 1527,
4410	DPAQ_SA_L_W_MM = 1528,	4410	DPAQ_SA_L_W_MM = 1528,
4411	DPAQ_S_W_PH_MM = 1529,	4411	DPAQ_S_W_PH_MM = 1529,
4412	DPAU_H_QBL_MM = 1530,	4412	DPAU_H_QBL_MM = 1530,
4413	DPAU_H_QBR_MM = 1531,	4413	DPAU_H_QBR_MM = 1531,
4414	DPSQ_SA_L_W_MM = 1532,	4414	DPSQ_SA_L_W_MM = 1532,
4415	DPSQ_S_W_PH_MM = 1533,	4415	DPSQ_S_W_PH_MM = 1533,
4416	DPSU_H_QBL_MM = 1534,	4416	DPSU_H_QBL_MM = 1534,
4417	DPSU_H_QBR_MM = 1535,	4417	DPSU_H_QBR_MM = 1535,
4418	EXTPDPV_MM = 1536,	4418	EXTPDPV_MM = 1536,
4419	EXTPDP_MM = 1537,	4419	EXTPDP_MM = 1537,
4420	EXTPV_MM = 1538,	4420	EXTPV_MM = 1538,
4421	EXTP_MM = 1539,	4421	EXTP_MM = 1539,
4422	EXTRV_RS_W_MM = 1540,	4422	EXTRV_RS_W_MM = 1540,
4423	EXTRV_R_W_MM = 1541,	4423	EXTRV_R_W_MM = 1541,
4424	EXTRV_S_H_MM = 1542,	4424	EXTRV_S_H_MM = 1542,
4425	EXTRV_W_MM = 1543,	4425	EXTRV_W_MM = 1543,
4426	EXTR_RS_W_MM = 1544,	4426	EXTR_RS_W_MM = 1544,
4427	EXTR_R_W_MM = 1545,	4427	EXTR_R_W_MM = 1545,
4428	EXTR_S_H_MM = 1546,	4428	EXTR_S_H_MM = 1546,
4429	EXTR_W_MM = 1547,	4429	EXTR_W_MM = 1547,
4430	INSV_MM = 1548,	4430	INSV_MM = 1548,
4431	LBUX_MM = 1549,	4431	LBUX_MM = 1549,
4432	LHX_MM = 1550,	4432	LHX_MM = 1550,
4433	LWX_MM = 1551,	4433	LWX_MM = 1551,
4434	MADDU_DSP_MM = 1552,	4434	MADDU_DSP_MM = 1552,
4435	MADD_DSP_MM = 1553,	4435	MADD_DSP_MM = 1553,
4436	MAQ_SA_W_PHL_MM = 1554,	4436	MAQ_SA_W_PHL_MM = 1554,
4437	MAQ_SA_W_PHR_MM = 1555,	4437	MAQ_SA_W_PHR_MM = 1555,
4438	MAQ_S_W_PHL_MM = 1556,	4438	MAQ_S_W_PHL_MM = 1556,
4439	MAQ_S_W_PHR_MM = 1557,	4439	MAQ_S_W_PHR_MM = 1557,
4440	MFHI_DSP_MM = 1558,	4440	MFHI_DSP_MM = 1558,
4441	MFLO_DSP_MM = 1559,	4441	MFLO_DSP_MM = 1559,
4442	MODSUB_MM = 1560,	4442	MODSUB_MM = 1560,
4443	MOVEP_MMR6 = 1561,	4443	MOVEP_MMR6 = 1561,
4444	MOVN_I_MM = 1562,	4444	MOVN_I_MM = 1562,
4445	MOVZ_I_MM = 1563,	4445	MOVZ_I_MM = 1563,
4446	MSUBU_DSP_MM = 1564,	4446	MSUBU_DSP_MM = 1564,
4447	MSUB_DSP_MM = 1565,	4447	MSUB_DSP_MM = 1565,
4448	MTHI_DSP_MM = 1566,	4448	MTHI_DSP_MM = 1566,
4449	MTHLIP_MM = 1567,	4449	MTHLIP_MM = 1567,
4450	MTLO_DSP_MM = 1568,	4450	MTLO_DSP_MM = 1568,
4451	MULEQ_S_W_PHL_MM = 1569,	4451	MULEQ_S_W_PHL_MM = 1569,
4452	MULEQ_S_W_PHR_MM = 1570,	4452	MULEQ_S_W_PHR_MM = 1570,
4453	MULEU_S_PH_QBL_MM = 1571,	4453	MULEU_S_PH_QBL_MM = 1571,
4454	MULEU_S_PH_QBR_MM = 1572,	4454	MULEU_S_PH_QBR_MM = 1572,
4455	MULQ_RS_PH_MM = 1573,	4455	MULQ_RS_PH_MM = 1573,
4456	MULSAQ_S_W_PH_MM = 1574,	4456	MULSAQ_S_W_PH_MM = 1574,
4457	MULTU_DSP_MM = 1575,	4457	MULTU_DSP_MM = 1575,
4458	MULT_DSP_MM = 1576,	4458	MULT_DSP_MM = 1576,
4459	PACKRL_PH_MM = 1577,	4459	PACKRL_PH_MM = 1577,
4460	PICK_PH_MM = 1578,	4460	PICK_PH_MM = 1578,
4461	PICK_QB_MM = 1579,	4461	PICK_QB_MM = 1579,
4462	PRECEQU_PH_QBLA_MM = 1580,	4462	PRECEQU_PH_QBLA_MM = 1580,
4463	PRECEQU_PH_QBL_MM = 1581,	4463	PRECEQU_PH_QBL_MM = 1581,
4464	PRECEQU_PH_QBRA_MM = 1582,	4464	PRECEQU_PH_QBRA_MM = 1582,
4465	PRECEQU_PH_QBR_MM = 1583,	4465	PRECEQU_PH_QBR_MM = 1583,
4466	PRECEQ_W_PHL_MM = 1584,	4466	PRECEQ_W_PHL_MM = 1584,
4467	PRECEQ_W_PHR_MM = 1585,	4467	PRECEQ_W_PHR_MM = 1585,
4468	PRECEU_PH_QBLA_MM = 1586,	4468	PRECEU_PH_QBLA_MM = 1586,
4469	PRECEU_PH_QBL_MM = 1587,	4469	PRECEU_PH_QBL_MM = 1587,
4470	PRECEU_PH_QBRA_MM = 1588,	4470	PRECEU_PH_QBRA_MM = 1588,
4471	PRECEU_PH_QBR_MM = 1589,	4471	PRECEU_PH_QBR_MM = 1589,
4472	PRECRQU_S_QB_PH_MM = 1590,	4472	PRECRQU_S_QB_PH_MM = 1590,
4473	PRECRQ_PH_W_MM = 1591,	4473	PRECRQ_PH_W_MM = 1591,
4474	PRECRQ_QB_PH_MM = 1592,	4474	PRECRQ_QB_PH_MM = 1592,
4475	PRECRQ_RS_PH_W_MM = 1593,	4475	PRECRQ_RS_PH_W_MM = 1593,
4476	RADDU_W_QB_MM = 1594,	4476	RADDU_W_QB_MM = 1594,
4477	RDDSP_MM = 1595,	4477	RDDSP_MM = 1595,
4478	REPLV_PH_MM = 1596,	4478	REPLV_PH_MM = 1596,
4479	REPLV_QB_MM = 1597,	4479	REPLV_QB_MM = 1597,
4480	REPL_PH_MM = 1598,	4480	REPL_PH_MM = 1598,
4481	REPL_QB_MM = 1599,	4481	REPL_QB_MM = 1599,
4482	SHILOV_MM = 1600,	4482	SHILOV_MM = 1600,
4483	SHILO_MM = 1601,	4483	SHILO_MM = 1601,
4484	SHLLV_PH_MM = 1602,	4484	SHLLV_PH_MM = 1602,
4485	SHLLV_QB_MM = 1603,	4485	SHLLV_QB_MM = 1603,
4486	SHLLV_S_PH_MM = 1604,	4486	SHLLV_S_PH_MM = 1604,
4487	SHLLV_S_W_MM = 1605,	4487	SHLLV_S_W_MM = 1605,
4488	SHLL_PH_MM = 1606,	4488	SHLL_PH_MM = 1606,
4489	SHLL_QB_MM = 1607,	4489	SHLL_QB_MM = 1607,
4490	SHLL_S_PH_MM = 1608,	4490	SHLL_S_PH_MM = 1608,
4491	SHLL_S_W_MM = 1609,	4491	SHLL_S_W_MM = 1609,
4492	SHRAV_PH_MM = 1610,	4492	SHRAV_PH_MM = 1610,
4493	SHRAV_R_PH_MM = 1611,	4493	SHRAV_R_PH_MM = 1611,
4494	SHRAV_R_W_MM = 1612,	4494	SHRAV_R_W_MM = 1612,
4495	SHRA_PH_MM = 1613,	4495	SHRA_PH_MM = 1613,
4496	SHRA_R_PH_MM = 1614,	4496	SHRA_R_PH_MM = 1614,
4497	SHRA_R_W_MM = 1615,	4497	SHRA_R_W_MM = 1615,
4498	SHRLV_QB_MM = 1616,	4498	SHRLV_QB_MM = 1616,
4499	SHRL_QB_MM = 1617,	4499	SHRL_QB_MM = 1617,
4500	SUBQ_PH_MM = 1618,	4500	SUBQ_PH_MM = 1618,
4501	SUBQ_S_PH_MM = 1619,	4501	SUBQ_S_PH_MM = 1619,
4502	SUBQ_S_W_MM = 1620,	4502	SUBQ_S_W_MM = 1620,
4503	SUBU_QB_MM = 1621,	4503	SUBU_QB_MM = 1621,
4504	SUBU_S_QB_MM = 1622,	4504	SUBU_S_QB_MM = 1622,
4505	WRDSP_MM = 1623,	4505	WRDSP_MM = 1623,
4506	ABSQ_S_QB_MMR2 = 1624,	4506	ABSQ_S_QB_MMR2 = 1624,
4507	ADDQH_PH_MMR2 = 1625,	4507	ADDQH_PH_MMR2 = 1625,
4508	ADDQH_R_PH_MMR2 = 1626,	4508	ADDQH_R_PH_MMR2 = 1626,
4509	ADDQH_R_W_MMR2 = 1627,	4509	ADDQH_R_W_MMR2 = 1627,
4510	ADDQH_W_MMR2 = 1628,	4510	ADDQH_W_MMR2 = 1628,
4511	ADDUH_QB_MMR2 = 1629,	4511	ADDUH_QB_MMR2 = 1629,
4512	ADDUH_R_QB_MMR2 = 1630,	4512	ADDUH_R_QB_MMR2 = 1630,
4513	ADDU_PH_MMR2 = 1631,	4513	ADDU_PH_MMR2 = 1631,
4514	ADDU_S_PH_MMR2 = 1632,	4514	ADDU_S_PH_MMR2 = 1632,
4515	APPEND_MMR2 = 1633,	4515	APPEND_MMR2 = 1633,
4516	BALIGN_MMR2 = 1634,	4516	BALIGN_MMR2 = 1634,
4517	CMPGDU_EQ_QB_MMR2 = 1635,	4517	CMPGDU_EQ_QB_MMR2 = 1635,
4518	CMPGDU_LE_QB_MMR2 = 1636,	4518	CMPGDU_LE_QB_MMR2 = 1636,
4519	CMPGDU_LT_QB_MMR2 = 1637,	4519	CMPGDU_LT_QB_MMR2 = 1637,
4520	DPA_W_PH_MMR2 = 1638,	4520	DPA_W_PH_MMR2 = 1638,
4521	DPAQX_SA_W_PH_MMR2 = 1639,	4521	DPAQX_SA_W_PH_MMR2 = 1639,
4522	DPAQX_S_W_PH_MMR2 = 1640,	4522	DPAQX_S_W_PH_MMR2 = 1640,
4523	DPAX_W_PH_MMR2 = 1641,	4523	DPAX_W_PH_MMR2 = 1641,
4524	DPS_W_PH_MMR2 = 1642,	4524	DPS_W_PH_MMR2 = 1642,
4525	DPSQX_S_W_PH_MMR2 = 1643,	4525	DPSQX_S_W_PH_MMR2 = 1643,
4526	DPSQX_SA_W_PH_MMR2 = 1644,	4526	DPSQX_SA_W_PH_MMR2 = 1644,
4527	DPSX_W_PH_MMR2 = 1645,	4527	DPSX_W_PH_MMR2 = 1645,
4528	MUL_PH_MMR2 = 1646,	4528	MUL_PH_MMR2 = 1646,
4529	MUL_S_PH_MMR2 = 1647,	4529	MUL_S_PH_MMR2 = 1647,
4530	MULQ_RS_W_MMR2 = 1648,	4530	MULQ_RS_W_MMR2 = 1648,
4531	MULQ_S_PH_MMR2 = 1649,	4531	MULQ_S_PH_MMR2 = 1649,
4532	MULQ_S_W_MMR2 = 1650,	4532	MULQ_S_W_MMR2 = 1650,
4533	MULSA_W_PH_MMR2 = 1651,	4533	MULSA_W_PH_MMR2 = 1651,
4534	PRECR_QB_PH_MMR2 = 1652,	4534	PRECR_QB_PH_MMR2 = 1652,
4535	PRECR_SRA_PH_W_MMR2 = 1653,	4535	PRECR_SRA_PH_W_MMR2 = 1653,
4536	PRECR_SRA_R_PH_W_MMR2 = 1654,	4536	PRECR_SRA_R_PH_W_MMR2 = 1654,
4537	PREPEND_MMR2 = 1655,	4537	PREPEND_MMR2 = 1655,
4538	SHRA_QB_MMR2 = 1656,	4538	SHRA_QB_MMR2 = 1656,
4539	SHRA_R_QB_MMR2 = 1657,	4539	SHRA_R_QB_MMR2 = 1657,
4540	SHRAV_QB_MMR2 = 1658,	4540	SHRAV_QB_MMR2 = 1658,
4541	SHRAV_R_QB_MMR2 = 1659,	4541	SHRAV_R_QB_MMR2 = 1659,
4542	SHRL_PH_MMR2 = 1660,	4542	SHRL_PH_MMR2 = 1660,
4543	SHRLV_PH_MMR2 = 1661,	4543	SHRLV_PH_MMR2 = 1661,
4544	SUBQH_PH_MMR2 = 1662,	4544	SUBQH_PH_MMR2 = 1662,
4545	SUBQH_R_PH_MMR2 = 1663,	4545	SUBQH_R_PH_MMR2 = 1663,
4546	SUBQH_W_MMR2 = 1664,	4546	SUBQH_W_MMR2 = 1664,
4547	SUBQH_R_W_MMR2 = 1665,	4547	SUBQH_R_W_MMR2 = 1665,
4548	SUBU_PH_MMR2 = 1666,	4548	SUBU_PH_MMR2 = 1666,
4549	SUBU_S_PH_MMR2 = 1667,	4549	SUBU_S_PH_MMR2 = 1667,
4550	SUBUH_QB_MMR2 = 1668,	4550	SUBUH_QB_MMR2 = 1668,
4551	SUBUH_R_QB_MMR2 = 1669,	4551	SUBUH_R_QB_MMR2 = 1669,
4552	BPOSGE32C_MMR3 = 1670,	4552	BPOSGE32C_MMR3 = 1670,
4553	CMP_F_D = 1671,	4553	CMP_F_D = 1671,
4554	CMP_F_S = 1672,	4554	CMP_F_S = 1672,
4555	CMP_SAF_D = 1673,	4555	CMP_SAF_D = 1673,
4556	CMP_SAF_S = 1674,	4556	CMP_SAF_S = 1674,
4557	CMP_SEQ_D = 1675,	4557	CMP_SEQ_D = 1675,
4558	CMP_SEQ_S = 1676,	4558	CMP_SEQ_S = 1676,
4559	CMP_SLE_D = 1677,	4559	CMP_SLE_D = 1677,
4560	CMP_SLE_S = 1678,	4560	CMP_SLE_S = 1678,
4561	CMP_SLT_D = 1679,	4561	CMP_SLT_D = 1679,
4562	CMP_SLT_S = 1680,	4562	CMP_SLT_S = 1680,
4563	CMP_SUEQ_D = 1681,	4563	CMP_SUEQ_D = 1681,
4564	CMP_SUEQ_S = 1682,	4564	CMP_SUEQ_S = 1682,
4565	CMP_SULE_D = 1683,	4565	CMP_SULE_D = 1683,
4566	CMP_SULE_S = 1684,	4566	CMP_SULE_S = 1684,
4567	CMP_SULT_D = 1685,	4567	CMP_SULT_D = 1685,
4568	CMP_SULT_S = 1686,	4568	CMP_SULT_S = 1686,
4569	CMP_SUN_D = 1687,	4569	CMP_SUN_D = 1687,
4570	CMP_SUN_S = 1688,	4570	CMP_SUN_S = 1688,
4571	SCHED_LIST_END = 1689	4571	SCHED_LIST_END = 1689
4572	};	4572	};
4573	} // end namespace Sched	4573	} // end namespace Sched
4574	} // end namespace Mips	4574	} // end namespace Mips
4575	} // end namespace llvm	4575	} // end namespace llvm
4576	#endif // GET_INSTRINFO_SCHED_ENUM	4576	#endif // GET_INSTRINFO_SCHED_ENUM
4577		4577
4578	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	4578	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
4579	namespace llvm {	4579	namespace llvm {
4580		4580
4581	struct MipsInstrTable {	4581	struct MipsInstrTable {
4582	MCInstrDesc Insts[2853];	4582	MCInstrDesc Insts[2853];
4583	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");	4583	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
4584	MCOperandInfo OperandInfo[1126];	4584	MCOperandInfo OperandInfo[1126];
4585	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");	4585	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
4586	MCPhysReg ImplicitOps[67];	4586	MCPhysReg ImplicitOps[67];
4587	};	4587	};
4588		4588
4589	} // end namespace llvm	4589	} // end namespace llvm
4590	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	4590	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
4591		4591
4592	#ifdef GET_INSTRINFO_MC_DESC	4592	#ifdef GET_INSTRINFO_MC_DESC
4593	#undef GET_INSTRINFO_MC_DESC	4593	#undef GET_INSTRINFO_MC_DESC
4594	namespace llvm {	4594	namespace llvm {
4595		4595
4596	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);	4596	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
4597	static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));	4597	static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));
4598		4598
4599	extern const MipsInstrTable MipsDescs = {	4599	extern const MipsInstrTable MipsDescs = {
4600	{	4600	{
4601	{ 2852, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	4601	{ 2852, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
4602	{ 2851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	4602	{ 2851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<
4603	{ 2850, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4603	{ 2850, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4604	{ 2849, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	4604	{ 2849, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
4605	{ 2848, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4605	{ 2848, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4606	{ 2847, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2847 = XOR_V	4606	{ 2847, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2847 = XOR_V
4607	{ 2846, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4607	{ 2846, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4608	{ 2845, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4608	{ 2845, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4609	{ 2844, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4609	{ 2844, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4610	{ 2843, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2843 = XORI_B	4610	{ 2843, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2843 = XORI_B
4611	{ 2842, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	4611	{ 2842, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
4612	{ 2841, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	4612	{ 2841, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
4613	{ 2840, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	4613	{ 2840, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
4614	{ 2839, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4614	{ 2839, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4615	{ 2838, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2838 = WSBH_MMR6	4615	{ 2838, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2838 = WSBH_MMR6
4616	{ 2837, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2837 = WSBH_MM	4616	{ 2837, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2837 = WSBH_MM
4617	{ 2836, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2836 = WSBH	4617	{ 2836, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2836 = WSBH
4618	{ 2835, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2835 = WRPGPR_MMR6	4618	{ 2835, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2835 = WRPGPR_MMR6
4619	{ 2834, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4619	{ 2834, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4620	{ 2833, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4620	{ 2833, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4621	{ 2832, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4621	{ 2832, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4622	{ 2831, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4622	{ 2831, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4623	{ 2830, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4623	{ 2830, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4624	{ 2829, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2829 = VSHF_W	4624	{ 2829, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2829 = VSHF_W
4625	{ 2828, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2828 = VSHF_H	4625	{ 2828, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2828 = VSHF_H
4626	{ 2827, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2827 = VSHF_D	4626	{ 2827, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2827 = VSHF_D
4627	{ 2826, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2826 = VSHF_B	4627	{ 2826, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2826 = VSHF_B
4628	{ 2825, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 219, 0\|(1ULL<	4628	{ 2825, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 219, 0\|(1ULL<
4629	{ 2824, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 219, 0\|(1ULL<	4629	{ 2824, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 219, 0\|(1ULL<
4630	{ 2823, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 219, 0\|(1ULL<	4630	{ 2823, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 219, 0\|(1ULL<
4631	{ 2822, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	4631	{ 2822, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
4632	{ 2821, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	4632	{ 2821, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
4633	{ 2820, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4633	{ 2820, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4634	{ 2819, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2819 = TRUNC_W_S_MMR6	4634	{ 2819, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2819 = TRUNC_W_S_MMR6
4635	{ 2818, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2818 = TRUNC_W_S_MM	4635	{ 2818, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2818 = TRUNC_W_S_MM
4636	{ 2817, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2817 = TRUNC_W_S	4636	{ 2817, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2817 = TRUNC_W_S
4637	{ 2816, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2816 = TRUNC_W_MM	4637	{ 2816, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2816 = TRUNC_W_MM
4638	{ 2815, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2815 = TRUNC_W_D_MMR6	4638	{ 2815, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2815 = TRUNC_W_D_MMR6
4639	{ 2814, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2814 = TRUNC_W_D64	4639	{ 2814, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2814 = TRUNC_W_D64
4640	{ 2813, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2813 = TRUNC_W_D32	4640	{ 2813, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2813 = TRUNC_W_D32
4641	{ 2812, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2812 = TRUNC_L_S_MMR6	4641	{ 2812, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2812 = TRUNC_L_S_MMR6
4642	{ 2811, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2811 = TRUNC_L_S	4642	{ 2811, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2811 = TRUNC_L_S
4643	{ 2810, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2810 = TRUNC_L_D_MMR6	4643	{ 2810, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2810 = TRUNC_L_D_MMR6
4644	{ 2809, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2809 = TRUNC_L_D64	4644	{ 2809, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2809 = TRUNC_L_D64
4645	{ 2808, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4645	{ 2808, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4646	{ 2807, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4646	{ 2807, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4647	{ 2806, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4647	{ 2806, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4648	{ 2805, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4648	{ 2805, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4649	{ 2804, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4649	{ 2804, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4650	{ 2803, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4650	{ 2803, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4651	{ 2802, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4651	{ 2802, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4652	{ 2801, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4652	{ 2801, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4653	{ 2800, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4653	{ 2800, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4654	{ 2799, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4654	{ 2799, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4655	{ 2798, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4655	{ 2798, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4656	{ 2797, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4656	{ 2797, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4657	{ 2796, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4657	{ 2796, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4658	{ 2795, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4658	{ 2795, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4659	{ 2794, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4659	{ 2794, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4660	{ 2793, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4660	{ 2793, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4661	{ 2792, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4661	{ 2792, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4662	{ 2791, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4662	{ 2791, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4663	{ 2790, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4663	{ 2790, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4664	{ 2789, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4664	{ 2789, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4665	{ 2788, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4665	{ 2788, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4666	{ 2787, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4666	{ 2787, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4667	{ 2786, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4667	{ 2786, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4668	{ 2785, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4668	{ 2785, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4669	{ 2784, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4669	{ 2784, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4670	{ 2783, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4670	{ 2783, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4671	{ 2782, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4671	{ 2782, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4672	{ 2781, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4672	{ 2781, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4673	{ 2780, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4673	{ 2780, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4674	{ 2779, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4674	{ 2779, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4675	{ 2778, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4675	{ 2778, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4676	{ 2777, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4676	{ 2777, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4677	{ 2776, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4677	{ 2776, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4678	{ 2775, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4678	{ 2775, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4679	{ 2774, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4679	{ 2774, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4680	{ 2773, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4680	{ 2773, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4681	{ 2772, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4681	{ 2772, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4682	{ 2771, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4682	{ 2771, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4683	{ 2770, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4683	{ 2770, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4684	{ 2769, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4684	{ 2769, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4685	{ 2768, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4685	{ 2768, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4686	{ 2767, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4686	{ 2767, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4687	{ 2766, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4687	{ 2766, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4688	{ 2765, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4688	{ 2765, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4689	{ 2764, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4689	{ 2764, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4690	{ 2763, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	4690	{ 2763, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
4691	{ 2762, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4691	{ 2762, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4692	{ 2761, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	4692	{ 2761, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<
4693	{ 2760, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	4693	{ 2760, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
4694	{ 2759, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	4694	{ 2759, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<
4695	{ 2758, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2758 = SrlvRxRy16	4695	{ 2758, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2758 = SrlvRxRy16
4696	{ 2757, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2757 = SrlX16	4696	{ 2757, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2757 = SrlX16
4697	{ 2756, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2756 = SravRxRy16	4697	{ 2756, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2756 = SravRxRy16
4698	{ 2755, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2755 = SraX16	4698	{ 2755, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2755 = SraX16
4699	{ 2754, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	4699	{ 2754, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<
4700	{ 2753, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	4700	{ 2753, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
4701	{ 2752, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	4701	{ 2752, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
4702	{ 2751, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	4702	{ 2751, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
4703	{ 2750, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	4703	{ 2750, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
4704	{ 2749, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	4704	{ 2749, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<
4705	{ 2748, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2748 = SllvRxRy16	4705	{ 2748, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2748 = SllvRxRy16
4706	{ 2747, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2747 = SllX16	4706	{ 2747, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2747 = SllX16
4707	{ 2746, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	4707	{ 2746, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
4708	{ 2745, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2745 = SehRx16	4708	{ 2745, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2745 = SehRx16
4709	{ 2744, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2744 = SebRx16	4709	{ 2744, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2744 = SebRx16
4710	{ 2743, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	4710	{ 2743, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
4711	{ 2742, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	4711	{ 2742, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<
4712	{ 2741, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	4712	{ 2741, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<
4713	{ 2740, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4713	{ 2740, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4714	{ 2739, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4714	{ 2739, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4715	{ 2738, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4715	{ 2738, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4716	{ 2737, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4716	{ 2737, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4717	{ 2736, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	4717	{ 2736, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<
4718	{ 2735, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	4718	{ 2735, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<
4719	{ 2734, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	4719	{ 2734, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<
4720	{ 2733, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4720	{ 2733, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4721	{ 2732, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4721	{ 2732, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4722	{ 2731, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4722	{ 2731, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4723	{ 2730, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	4723	{ 2730, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<
4724	{ 2729, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	4724	{ 2729, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<
4725	{ 2728, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	4725	{ 2728, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<
4726	{ 2727, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	4726	{ 2727, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<
4727	{ 2726, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4727	{ 2726, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4728	{ 2725, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4728	{ 2725, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4729	{ 2724, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4729	{ 2724, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4730	{ 2723, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	4730	{ 2723, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
4731	{ 2722, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4731	{ 2722, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4732	{ 2721, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	4732	{ 2721, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<
4733	{ 2720, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	4733	{ 2720, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<
4734	{ 2719, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	4734	{ 2719, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<
4735	{ 2718, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	4735	{ 2718, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<
4736	{ 2717, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4736	{ 2717, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4737	{ 2716, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4737	{ 2716, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4738	{ 2715, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4738	{ 2715, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4739	{ 2714, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	4739	{ 2714, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
4740	{ 2713, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4740	{ 2713, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4741	{ 2712, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4741	{ 2712, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4742	{ 2711, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4742	{ 2711, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4743	{ 2710, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	4743	{ 2710, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<
4744	{ 2709, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	4744	{ 2709, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<
4745	{ 2708, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	4745	{ 2708, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<
4746	{ 2707, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	4746	{ 2707, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
4747	{ 2706, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	4747	{ 2706, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<
4748	{ 2705, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	4748	{ 2705, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
4749	{ 2704, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	4749	{ 2704, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<
4750	{ 2703, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	4750	{ 2703, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<
4751	{ 2702, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	4751	{ 2702, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
4752	{ 2701, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	4752	{ 2701, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
4753	{ 2700, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	4753	{ 2700, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
4754	{ 2699, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4754	{ 2699, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4755	{ 2698, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	4755	{ 2698, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
4756	{ 2697, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	4756	{ 2697, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
4757	{ 2696, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	4757	{ 2696, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<
4758	{ 2695, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4758	{ 2695, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4759	{ 2694, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4759	{ 2694, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4760	{ 2693, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4760	{ 2693, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4761	{ 2692, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4761	{ 2692, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4762	{ 2691, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2691 = SUBV_W	4762	{ 2691, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2691 = SUBV_W
4763	{ 2690, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2690 = SUBV_H	4763	{ 2690, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2690 = SUBV_H
4764	{ 2689, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2689 = SUBV_D	4764	{ 2689, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2689 = SUBV_D
4765	{ 2688, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2688 = SUBV_B	4765	{ 2688, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2688 = SUBV_B
4766	{ 2687, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2687 = SUBVI_W	4766	{ 2687, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2687 = SUBVI_W
4767	{ 2686, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2686 = SUBVI_H	4767	{ 2686, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2686 = SUBVI_H
4768	{ 2685, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2685 = SUBVI_D	4768	{ 2685, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2685 = SUBVI_D
4769	{ 2684, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2684 = SUBVI_B	4769	{ 2684, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2684 = SUBVI_B
4770	{ 2683, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2683 = SUBU_S_QB_MM	4770	{ 2683, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2683 = SUBU_S_QB_MM
4771	{ 2682, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2682 = SUBU_S_QB	4771	{ 2682, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2682 = SUBU_S_QB
4772	{ 2681, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4772	{ 2681, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4773	{ 2680, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4773	{ 2680, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4774	{ 2679, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4774	{ 2679, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4775	{ 2678, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2678 = SUBU_QB	4775	{ 2678, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2678 = SUBU_QB
4776	{ 2677, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4776	{ 2677, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4777	{ 2676, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4777	{ 2676, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4778	{ 2675, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4778	{ 2675, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4779	{ 2674, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2674 = SUBUH_R_QB_MMR2	4779	{ 2674, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2674 = SUBUH_R_QB_MMR2
4780	{ 2673, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2673 = SUBUH_R_QB	4780	{ 2673, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2673 = SUBUH_R_QB
4781	{ 2672, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2672 = SUBUH_QB_MMR2	4781	{ 2672, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2672 = SUBUH_QB_MMR2
4782	{ 2671, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2671 = SUBUH_QB	4782	{ 2671, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2671 = SUBUH_QB
4783	{ 2670, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2670 = SUBU16_MMR6	4783	{ 2670, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2670 = SUBU16_MMR6
4784	{ 2669, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2669 = SUBU16_MM	4784	{ 2669, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2669 = SUBU16_MM
4785	{ 2668, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2668 = SUBS_U_W	4785	{ 2668, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2668 = SUBS_U_W
4786	{ 2667, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2667 = SUBS_U_H	4786	{ 2667, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2667 = SUBS_U_H
4787	{ 2666, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2666 = SUBS_U_D	4787	{ 2666, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2666 = SUBS_U_D
4788	{ 2665, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2665 = SUBS_U_B	4788	{ 2665, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2665 = SUBS_U_B
4789	{ 2664, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2664 = SUBS_S_W	4789	{ 2664, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2664 = SUBS_S_W
4790	{ 2663, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2663 = SUBS_S_H	4790	{ 2663, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2663 = SUBS_S_H
4791	{ 2662, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2662 = SUBS_S_D	4791	{ 2662, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2662 = SUBS_S_D
4792	{ 2661, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2661 = SUBS_S_B	4792	{ 2661, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2661 = SUBS_S_B
4793	{ 2660, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2660 = SUBSUU_S_W	4793	{ 2660, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2660 = SUBSUU_S_W
4794	{ 2659, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2659 = SUBSUU_S_H	4794	{ 2659, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2659 = SUBSUU_S_H
4795	{ 2658, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2658 = SUBSUU_S_D	4795	{ 2658, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2658 = SUBSUU_S_D
4796	{ 2657, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2657 = SUBSUU_S_B	4796	{ 2657, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2657 = SUBSUU_S_B
4797	{ 2656, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2656 = SUBSUS_U_W	4797	{ 2656, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2656 = SUBSUS_U_W
4798	{ 2655, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2655 = SUBSUS_U_H	4798	{ 2655, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2655 = SUBSUS_U_H
4799	{ 2654, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2654 = SUBSUS_U_D	4799	{ 2654, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2654 = SUBSUS_U_D
4800	{ 2653, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2653 = SUBSUS_U_B	4800	{ 2653, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2653 = SUBSUS_U_B
4801	{ 2652, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	4801	{ 2652, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<
4802	{ 2651, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	4802	{ 2651, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<
4803	{ 2650, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2650 = SUBQ_S_PH_MM	4803	{ 2650, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2650 = SUBQ_S_PH_MM
4804	{ 2649, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2649 = SUBQ_S_PH	4804	{ 2649, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2649 = SUBQ_S_PH
4805	{ 2648, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	4805	{ 2648, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
4806	{ 2647, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2647 = SUBQ_PH	4806	{ 2647, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2647 = SUBQ_PH
4807	{ 2646, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2646 = SUBQH_W_MMR2	4807	{ 2646, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2646 = SUBQH_W_MMR2
4808	{ 2645, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2645 = SUBQH_W	4808	{ 2645, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2645 = SUBQH_W
4809	{ 2644, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2644 = SUBQH_R_W_MMR2	4809	{ 2644, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2644 = SUBQH_R_W_MMR2
4810	{ 2643, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2643 = SUBQH_R_W	4810	{ 2643, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2643 = SUBQH_R_W
4811	{ 2642, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2642 = SUBQH_R_PH_MMR2	4811	{ 2642, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2642 = SUBQH_R_PH_MMR2
4812	{ 2641, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2641 = SUBQH_R_PH	4812	{ 2641, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2641 = SUBQH_R_PH
4813	{ 2640, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2640 = SUBQH_PH_MMR2	4813	{ 2640, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2640 = SUBQH_PH_MMR2
4814	{ 2639, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2639 = SUBQH_PH	4814	{ 2639, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2639 = SUBQH_PH
4815	{ 2638, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	4815	{ 2638, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
4816	{ 2637, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	4816	{ 2637, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<
4817	{ 2636, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	4817	{ 2636, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<
4818	{ 2635, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	4818	{ 2635, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<
4819	{ 2634, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	4819	{ 2634, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<
4820	{ 2633, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4820	{ 2633, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4821	{ 2632, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4821	{ 2632, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4822	{ 2631, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	4822	{ 2631, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
4823	{ 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2630 = SRL_W	4823	{ 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2630 = SRL_W
4824	{ 2629, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2629 = SRL_MM	4824	{ 2629, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2629 = SRL_MM
4825	{ 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2628 = SRL_H	4825	{ 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2628 = SRL_H
4826	{ 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2627 = SRL_D	4826	{ 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2627 = SRL_D
4827	{ 2626, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2626 = SRL_B	4827	{ 2626, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2626 = SRL_B
4828	{ 2625, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2625 = SRLV_MM	4828	{ 2625, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2625 = SRLV_MM
4829	{ 2624, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2624 = SRLV	4829	{ 2624, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2624 = SRLV
4830	{ 2623, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2623 = SRLR_W	4830	{ 2623, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2623 = SRLR_W
4831	{ 2622, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2622 = SRLR_H	4831	{ 2622, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2622 = SRLR_H
4832	{ 2621, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2621 = SRLR_D	4832	{ 2621, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2621 = SRLR_D
4833	{ 2620, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2620 = SRLR_B	4833	{ 2620, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2620 = SRLR_B
4834	{ 2619, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2619 = SRLRI_W	4834	{ 2619, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2619 = SRLRI_W
4835	{ 2618, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2618 = SRLRI_H	4835	{ 2618, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2618 = SRLRI_H
4836	{ 2617, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2617 = SRLRI_D	4836	{ 2617, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2617 = SRLRI_D
4837	{ 2616, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2616 = SRLRI_B	4837	{ 2616, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2616 = SRLRI_B
4838	{ 2615, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2615 = SRLI_W	4838	{ 2615, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2615 = SRLI_W
4839	{ 2614, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2614 = SRLI_H	4839	{ 2614, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2614 = SRLI_H
4840	{ 2613, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2613 = SRLI_D	4840	{ 2613, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2613 = SRLI_D
4841	{ 2612, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2612 = SRLI_B	4841	{ 2612, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2612 = SRLI_B
4842	{ 2611, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	4842	{ 2611, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<
4843	{ 2610, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2610 = SRL16_MM	4843	{ 2610, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2610 = SRL16_MM
4844	{ 2609, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2609 = SRL	4844	{ 2609, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2609 = SRL
4845	{ 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2608 = SRA_W	4845	{ 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2608 = SRA_W
4846	{ 2607, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2607 = SRA_MM	4846	{ 2607, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2607 = SRA_MM
4847	{ 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2606 = SRA_H	4847	{ 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2606 = SRA_H
4848	{ 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2605 = SRA_D	4848	{ 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2605 = SRA_D
4849	{ 2604, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2604 = SRA_B	4849	{ 2604, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2604 = SRA_B
4850	{ 2603, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2603 = SRAV_MM	4850	{ 2603, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2603 = SRAV_MM
4851	{ 2602, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2602 = SRAV	4851	{ 2602, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2602 = SRAV
4852	{ 2601, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2601 = SRAR_W	4852	{ 2601, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2601 = SRAR_W
4853	{ 2600, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2600 = SRAR_H	4853	{ 2600, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2600 = SRAR_H
4854	{ 2599, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2599 = SRAR_D	4854	{ 2599, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2599 = SRAR_D
4855	{ 2598, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2598 = SRAR_B	4855	{ 2598, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2598 = SRAR_B
4856	{ 2597, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2597 = SRARI_W	4856	{ 2597, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2597 = SRARI_W
4857	{ 2596, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2596 = SRARI_H	4857	{ 2596, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2596 = SRARI_H
4858	{ 2595, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2595 = SRARI_D	4858	{ 2595, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2595 = SRARI_D
4859	{ 2594, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2594 = SRARI_B	4859	{ 2594, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2594 = SRARI_B
4860	{ 2593, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2593 = SRAI_W	4860	{ 2593, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2593 = SRAI_W
4861	{ 2592, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2592 = SRAI_H	4861	{ 2592, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2592 = SRAI_H
4862	{ 2591, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2591 = SRAI_D	4862	{ 2591, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2591 = SRAI_D
4863	{ 2590, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2590 = SRAI_B	4863	{ 2590, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2590 = SRAI_B
4864	{ 2589, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2589 = SRA	4864	{ 2589, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2589 = SRA
4865	{ 2588, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1119, 0, 0x6ULL }, // Inst #2588 = SPLAT_W	4865	{ 2588, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1119, 0, 0x6ULL }, // Inst #2588 = SPLAT_W
4866	{ 2587, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2587 = SPLAT_H	4866	{ 2587, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2587 = SPLAT_H
4867	{ 2586, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1113, 0, 0x6ULL }, // Inst #2586 = SPLAT_D	4867	{ 2586, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1113, 0, 0x6ULL }, // Inst #2586 = SPLAT_D
4868	{ 2585, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1110, 0, 0x6ULL }, // Inst #2585 = SPLAT_B	4868	{ 2585, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1110, 0, 0x6ULL }, // Inst #2585 = SPLAT_B
4869	{ 2584, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2584 = SPLATI_W	4869	{ 2584, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2584 = SPLATI_W
4870	{ 2583, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2583 = SPLATI_H	4870	{ 2583, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2583 = SPLATI_H
4871	{ 2582, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2582 = SPLATI_D	4871	{ 2582, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2582 = SPLATI_D
4872	{ 2581, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2581 = SPLATI_B	4872	{ 2581, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2581 = SPLATI_B
4873	{ 2580, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2580 = SNEi	4873	{ 2580, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2580 = SNEi
4874	{ 2579, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2579 = SNE	4874	{ 2579, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2579 = SNE
4875	{ 2578, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2578 = SLTu_MM	4875	{ 2578, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2578 = SLTu_MM
4876	{ 2577, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2577 = SLTu64	4876	{ 2577, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2577 = SLTu64
4877	{ 2576, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2576 = SLTu	4877	{ 2576, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2576 = SLTu
4878	{ 2575, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2575 = SLTiu_MM	4878	{ 2575, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2575 = SLTiu_MM
4879	{ 2574, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2574 = SLTiu64	4879	{ 2574, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2574 = SLTiu64
4880	{ 2573, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2573 = SLTiu	4880	{ 2573, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2573 = SLTiu
4881	{ 2572, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2572 = SLTi_MM	4881	{ 2572, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2572 = SLTi_MM
4882	{ 2571, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2571 = SLTi64	4882	{ 2571, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2571 = SLTi64
4883	{ 2570, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2570 = SLTi	4883	{ 2570, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2570 = SLTi
4884	{ 2569, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2569 = SLT_MM	4884	{ 2569, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2569 = SLT_MM
4885	{ 2568, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2568 = SLT64	4885	{ 2568, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2568 = SLT64
4886	{ 2567, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2567 = SLT	4886	{ 2567, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2567 = SLT
4887	{ 2566, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2566 = SLL_W	4887	{ 2566, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2566 = SLL_W
4888	{ 2565, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4888	{ 2565, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4889	{ 2564, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2564 = SLL_MM	4889	{ 2564, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2564 = SLL_MM
4890	{ 2563, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2563 = SLL_H	4890	{ 2563, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2563 = SLL_H
4891	{ 2562, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2562 = SLL_D	4891	{ 2562, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2562 = SLL_D
4892	{ 2561, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2561 = SLL_B	4892	{ 2561, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2561 = SLL_B
4893	{ 2560, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2560 = SLLV_MM	4893	{ 2560, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2560 = SLLV_MM
4894	{ 2559, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2559 = SLLV	4894	{ 2559, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2559 = SLLV
4895	{ 2558, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2558 = SLLI_W	4895	{ 2558, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2558 = SLLI_W
4896	{ 2557, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2557 = SLLI_H	4896	{ 2557, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2557 = SLLI_H
4897	{ 2556, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2556 = SLLI_D	4897	{ 2556, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2556 = SLLI_D
4898	{ 2555, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2555 = SLLI_B	4898	{ 2555, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2555 = SLLI_B
4899	{ 2554, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	4899	{ 2554, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<
4900	{ 2553, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	4900	{ 2553, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<
4901	{ 2552, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	4901	{ 2552, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<
4902	{ 2551, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2551 = SLL16_MM	4902	{ 2551, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2551 = SLL16_MM
4903	{ 2550, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2550 = SLL	4903	{ 2550, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2550 = SLL
4904	{ 2549, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2549 = SLD_W	4904	{ 2549, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2549 = SLD_W
4905	{ 2548, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2548 = SLD_H	4905	{ 2548, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2548 = SLD_H
4906	{ 2547, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2547 = SLD_D	4906	{ 2547, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2547 = SLD_D
4907	{ 2546, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1088, 0, 0x6ULL }, // Inst #2546 = SLD_B	4907	{ 2546, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1088, 0, 0x6ULL }, // Inst #2546 = SLD_B
4908	{ 2545, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2545 = SLDI_W	4908	{ 2545, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2545 = SLDI_W
4909	{ 2544, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2544 = SLDI_H	4909	{ 2544, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2544 = SLDI_H
4910	{ 2543, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2543 = SLDI_D	4910	{ 2543, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2543 = SLDI_D
4911	{ 2542, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #2542 = SLDI_B	4911	{ 2542, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #2542 = SLDI_B
4912	{ 2541, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4912	{ 2541, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4913	{ 2540, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	4913	{ 2540, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
4914	{ 2539, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4914	{ 2539, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4915	{ 2538, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4915	{ 2538, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4916	{ 2537, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4916	{ 2537, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4917	{ 2536, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4917	{ 2536, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4918	{ 2535, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4918	{ 2535, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4919	{ 2534, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4919	{ 2534, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4920	{ 2533, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2533 = SHRLV_QB_MM	4920	{ 2533, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2533 = SHRLV_QB_MM
4921	{ 2532, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2532 = SHRLV_QB	4921	{ 2532, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2532 = SHRLV_QB
4922	{ 2531, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2531 = SHRLV_PH_MMR2	4922	{ 2531, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2531 = SHRLV_PH_MMR2
4923	{ 2530, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2530 = SHRLV_PH	4923	{ 2530, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2530 = SHRLV_PH
4924	{ 2529, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4924	{ 2529, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4925	{ 2528, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	4925	{ 2528, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
4926	{ 2527, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4926	{ 2527, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4927	{ 2526, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4927	{ 2526, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4928	{ 2525, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4928	{ 2525, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4929	{ 2524, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4929	{ 2524, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4930	{ 2523, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4930	{ 2523, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4931	{ 2522, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4931	{ 2522, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4932	{ 2521, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4932	{ 2521, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4933	{ 2520, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	4933	{ 2520, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<
4934	{ 2519, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2519 = SHRAV_R_W_MM	4934	{ 2519, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2519 = SHRAV_R_W_MM
4935	{ 2518, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2518 = SHRAV_R_W	4935	{ 2518, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2518 = SHRAV_R_W
4936	{ 2517, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2517 = SHRAV_R_QB_MMR2	4936	{ 2517, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2517 = SHRAV_R_QB_MMR2
4937	{ 2516, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2516 = SHRAV_R_QB	4937	{ 2516, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2516 = SHRAV_R_QB
4938	{ 2515, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2515 = SHRAV_R_PH_MM	4938	{ 2515, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2515 = SHRAV_R_PH_MM
4939	{ 2514, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2514 = SHRAV_R_PH	4939	{ 2514, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2514 = SHRAV_R_PH
4940	{ 2513, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2513 = SHRAV_QB_MMR2	4940	{ 2513, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2513 = SHRAV_QB_MMR2
4941	{ 2512, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2512 = SHRAV_QB	4941	{ 2512, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2512 = SHRAV_QB
4942	{ 2511, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2511 = SHRAV_PH_MM	4942	{ 2511, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2511 = SHRAV_PH_MM
4943	{ 2510, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2510 = SHRAV_PH	4943	{ 2510, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2510 = SHRAV_PH
4944	{ 2509, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	4944	{ 2509, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<
4945	{ 2508, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	4945	{ 2508, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<
4946	{ 2507, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4946	{ 2507, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4947	{ 2506, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4947	{ 2506, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4948	{ 2505, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4948	{ 2505, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4949	{ 2504, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4949	{ 2504, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4950	{ 2503, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4950	{ 2503, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4951	{ 2502, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	4951	{ 2502, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<
4952	{ 2501, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	4952	{ 2501, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<
4953	{ 2500, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	4953	{ 2500, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<
4954	{ 2499, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4954	{ 2499, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4955	{ 2498, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4955	{ 2498, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4956	{ 2497, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4956	{ 2497, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4957	{ 2496, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4957	{ 2496, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4958	{ 2495, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4958	{ 2495, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4959	{ 2494, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	4959	{ 2494, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<
4960	{ 2493, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SHILO_MM	4960	{ 2493, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SHILO_MM
4961	{ 2492, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2492 = SHILOV_MM	4961	{ 2492, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2492 = SHILOV_MM
4962	{ 2491, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2491 = SHILOV	4962	{ 2491, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2491 = SHILOV
4963	{ 2490, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2490 = SHILO	4963	{ 2490, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2490 = SHILO
4964	{ 2489, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2489 = SHF_W	4964	{ 2489, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2489 = SHF_W
4965	{ 2488, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2488 = SHF_H	4965	{ 2488, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2488 = SHF_H
4966	{ 2487, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2487 = SHF_B	4966	{ 2487, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2487 = SHF_B
4967	{ 2486, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4967	{ 2486, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4968	{ 2485, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4968	{ 2485, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4969	{ 2484, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	4969	{ 2484, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
4970	{ 2483, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	4970	{ 2483, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
4971	{ 2482, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	4971	{ 2482, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
4972	{ 2481, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	4972	{ 2481, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
4973	{ 2480, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2480 = SEQi	4973	{ 2480, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2480 = SEQi
4974	{ 2479, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2479 = SEQ	4974	{ 2479, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2479 = SEQ
4975	{ 2478, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2478 = SEL_S_MMR6	4975	{ 2478, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2478 = SEL_S_MMR6
4976	{ 2477, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2477 = SEL_S	4976	{ 2477, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2477 = SEL_S
4977	{ 2476, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2476 = SEL_D_MMR6	4977	{ 2476, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2476 = SEL_D_MMR6
4978	{ 2475, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2475 = SEL_D	4978	{ 2475, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2475 = SEL_D
4979	{ 2474, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	4979	{ 2474, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
4980	{ 2473, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	4980	{ 2473, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
4981	{ 2472, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2472 = SELNEZ_MMR6	4981	{ 2472, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2472 = SELNEZ_MMR6
4982	{ 2471, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	4982	{ 2471, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
4983	{ 2470, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	4983	{ 2470, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
4984	{ 2469, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2469 = SELNEZ64	4984	{ 2469, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2469 = SELNEZ64
4985	{ 2468, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2468 = SELNEZ	4985	{ 2468, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2468 = SELNEZ
4986	{ 2467, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	4986	{ 2467, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
4987	{ 2466, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	4987	{ 2466, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
4988	{ 2465, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2465 = SELEQZ_MMR6	4988	{ 2465, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2465 = SELEQZ_MMR6
4989	{ 2464, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	4989	{ 2464, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
4990	{ 2463, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	4990	{ 2463, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
4991	{ 2462, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2462 = SELEQZ64	4991	{ 2462, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2462 = SELEQZ64
4992	{ 2461, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2461 = SELEQZ	4992	{ 2461, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2461 = SELEQZ
4993	{ 2460, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2460 = SEH_MM	4993	{ 2460, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2460 = SEH_MM
4994	{ 2459, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2459 = SEH64	4994	{ 2459, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2459 = SEH64
4995	{ 2458, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2458 = SEH	4995	{ 2458, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2458 = SEH
4996	{ 2457, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2457 = SEB_MM	4996	{ 2457, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2457 = SEB_MM
4997	{ 2456, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2456 = SEB64	4997	{ 2456, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2456 = SEB64
4998	{ 2455, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2455 = SEB	4998	{ 2455, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2455 = SEB
4999	{ 2454, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	4999	{ 2454, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
5000	{ 2453, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	5000	{ 2453, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<
5001	{ 2452, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5001	{ 2452, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5002	{ 2451, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5002	{ 2451, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5003	{ 2450, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5003	{ 2450, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5004	{ 2449, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5004	{ 2449, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5005	{ 2448, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	5005	{ 2448, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<
5006	{ 2447, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5006	{ 2447, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5007	{ 2446, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	5007	{ 2446, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<
5008	{ 2445, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5008	{ 2445, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5009	{ 2444, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5009	{ 2444, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5010	{ 2443, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	5010	{ 2443, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<
5011	{ 2442, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5011	{ 2442, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5012	{ 2441, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5012	{ 2441, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5013	{ 2440, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	5013	{ 2440, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<
5014	{ 2439, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5014	{ 2439, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5015	{ 2438, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5015	{ 2438, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5016	{ 2437, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5016	{ 2437, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5017	{ 2436, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5017	{ 2436, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5018	{ 2435, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5018	{ 2435, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5019	{ 2434, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5019	{ 2434, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5020	{ 2433, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5020	{ 2433, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5021	{ 2432, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	5021	{ 2432, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<
5022	{ 2431, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5022	{ 2431, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5023	{ 2430, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5023	{ 2430, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5024	{ 2429, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5024	{ 2429, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5025	{ 2428, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5025	{ 2428, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5026	{ 2427, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1071, 0\|(1ULL<	5026	{ 2427, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1071, 0\|(1ULL<
5027	{ 2426, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1067, 0\|(1ULL<	5027	{ 2426, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1067, 0\|(1ULL<
5028	{ 2425, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	5028	{ 2425, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<
5029	{ 2424, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5029	{ 2424, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5030	{ 2423, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	5030	{ 2423, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<
5031	{ 2422, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5031	{ 2422, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5032	{ 2421, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5032	{ 2421, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5033	{ 2420, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5033	{ 2420, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5034	{ 2419, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5034	{ 2419, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5035	{ 2418, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5035	{ 2418, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5036	{ 2417, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	5036	{ 2417, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
5037	{ 2416, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	5037	{ 2416, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<
5038	{ 2415, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5038	{ 2415, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5039	{ 2414, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2414 = SAT_U_W	5039	{ 2414, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2414 = SAT_U_W
5040	{ 2413, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2413 = SAT_U_H	5040	{ 2413, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2413 = SAT_U_H
5041	{ 2412, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2412 = SAT_U_D	5041	{ 2412, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2412 = SAT_U_D
5042	{ 2411, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2411 = SAT_U_B	5042	{ 2411, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2411 = SAT_U_B
5043	{ 2410, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2410 = SAT_S_W	5043	{ 2410, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2410 = SAT_S_W
5044	{ 2409, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2409 = SAT_S_H	5044	{ 2409, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2409 = SAT_S_H
5045	{ 2408, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2408 = SAT_S_D	5045	{ 2408, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2408 = SAT_S_D
5046	{ 2407, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2407 = SAT_S_B	5046	{ 2407, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2407 = SAT_S_B
5047	{ 2406, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	5047	{ 2406, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<
5048	{ 2405, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	5048	{ 2405, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<
5049	{ 2404, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	5049	{ 2404, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<
5050	{ 2403, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	5050	{ 2403, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<
5051	{ 2402, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2402 = RSQRT_S_MM	5051	{ 2402, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2402 = RSQRT_S_MM
5052	{ 2401, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2401 = RSQRT_S	5052	{ 2401, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2401 = RSQRT_S
5053	{ 2400, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2400 = RSQRT_D64_MM	5053	{ 2400, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2400 = RSQRT_D64_MM
5054	{ 2399, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2399 = RSQRT_D64	5054	{ 2399, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2399 = RSQRT_D64
5055	{ 2398, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2398 = RSQRT_D32_MM	5055	{ 2398, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2398 = RSQRT_D32_MM
5056	{ 2397, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2397 = RSQRT_D32	5056	{ 2397, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2397 = RSQRT_D32
5057	{ 2396, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2396 = ROUND_W_S_MMR6	5057	{ 2396, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2396 = ROUND_W_S_MMR6
5058	{ 2395, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2395 = ROUND_W_S_MM	5058	{ 2395, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2395 = ROUND_W_S_MM
5059	{ 2394, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2394 = ROUND_W_S	5059	{ 2394, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2394 = ROUND_W_S
5060	{ 2393, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2393 = ROUND_W_MM	5060	{ 2393, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2393 = ROUND_W_MM
5061	{ 2392, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2392 = ROUND_W_D_MMR6	5061	{ 2392, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2392 = ROUND_W_D_MMR6
5062	{ 2391, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2391 = ROUND_W_D64	5062	{ 2391, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2391 = ROUND_W_D64
5063	{ 2390, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2390 = ROUND_W_D32	5063	{ 2390, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2390 = ROUND_W_D32
5064	{ 2389, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2389 = ROUND_L_S_MMR6	5064	{ 2389, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2389 = ROUND_L_S_MMR6
5065	{ 2388, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2388 = ROUND_L_S	5065	{ 2388, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2388 = ROUND_L_S
5066	{ 2387, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2387 = ROUND_L_D_MMR6	5066	{ 2387, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2387 = ROUND_L_D_MMR6
5067	{ 2386, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2386 = ROUND_L_D64	5067	{ 2386, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2386 = ROUND_L_D64
5068	{ 2385, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2385 = ROTR_MM	5068	{ 2385, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2385 = ROTR_MM
5069	{ 2384, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2384 = ROTRV_MM	5069	{ 2384, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2384 = ROTRV_MM
5070	{ 2383, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2383 = ROTRV	5070	{ 2383, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2383 = ROTRV
5071	{ 2382, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2382 = ROTR	5071	{ 2382, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2382 = ROTR
5072	{ 2381, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	5072	{ 2381, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
5073	{ 2380, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	5073	{ 2380, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
5074	{ 2379, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	5074	{ 2379, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<
5075	{ 2378, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	5075	{ 2378, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<
5076	{ 2377, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2377 = REPL_QB_MM	5076	{ 2377, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2377 = REPL_QB_MM
5077	{ 2376, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2376 = REPL_QB	5077	{ 2376, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2376 = REPL_QB
5078	{ 2375, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2375 = REPL_PH_MM	5078	{ 2375, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2375 = REPL_PH_MM
5079	{ 2374, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2374 = REPL_PH	5079	{ 2374, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2374 = REPL_PH
5080	{ 2373, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = REPLV_QB_MM	5080	{ 2373, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = REPLV_QB_MM
5081	{ 2372, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = REPLV_QB	5081	{ 2372, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = REPLV_QB
5082	{ 2371, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2371 = REPLV_PH_MM	5082	{ 2371, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2371 = REPLV_PH_MM
5083	{ 2370, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2370 = REPLV_PH	5083	{ 2370, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2370 = REPLV_PH
5084	{ 2369, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2369 = RECIP_S_MM	5084	{ 2369, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2369 = RECIP_S_MM
5085	{ 2368, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2368 = RECIP_S	5085	{ 2368, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2368 = RECIP_S
5086	{ 2367, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2367 = RECIP_D64_MM	5086	{ 2367, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2367 = RECIP_D64_MM
5087	{ 2366, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2366 = RECIP_D64	5087	{ 2366, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2366 = RECIP_D64
5088	{ 2365, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2365 = RECIP_D32_MM	5088	{ 2365, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2365 = RECIP_D32_MM
5089	{ 2364, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2364 = RECIP_D32	5089	{ 2364, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2364 = RECIP_D32
5090	{ 2363, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	5090	{ 2363, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
5091	{ 2362, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	5091	{ 2362, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<
5092	{ 2361, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	5092	{ 2361, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<
5093	{ 2360, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1049, 0\|(1ULL<	5093	{ 2360, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1049, 0\|(1ULL<
5094	{ 2359, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	5094	{ 2359, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<
5095	{ 2358, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5095	{ 2358, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5096	{ 2357, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5096	{ 2357, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5097	{ 2356, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2356 = RADDU_W_QB_MM	5097	{ 2356, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2356 = RADDU_W_QB_MM
5098	{ 2355, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2355 = RADDU_W_QB	5098	{ 2355, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2355 = RADDU_W_QB
5099	{ 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5099	{ 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5100	{ 2353, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5100	{ 2353, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5101	{ 2352, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2352 = PREPEND_MMR2	5101	{ 2352, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2352 = PREPEND_MMR2
5102	{ 2351, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2351 = PREPEND	5102	{ 2351, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2351 = PREPEND
5103	{ 2350, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5103	{ 2350, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5104	{ 2349, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5104	{ 2349, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5105	{ 2348, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5105	{ 2348, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5106	{ 2347, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1043, 0\|(1ULL<	5106	{ 2347, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1043, 0\|(1ULL<
5107	{ 2346, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5107	{ 2346, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5108	{ 2345, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5108	{ 2345, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5109	{ 2344, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	5109	{ 2344, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
5110	{ 2343, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2343 = PRECR_SRA_R_PH_W_MMR2	5110	{ 2343, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2343 = PRECR_SRA_R_PH_W_MMR2
5111	{ 2342, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2342 = PRECR_SRA_R_PH_W	5111	{ 2342, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2342 = PRECR_SRA_R_PH_W
5112	{ 2341, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2341 = PRECR_SRA_PH_W_MMR2	5112	{ 2341, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2341 = PRECR_SRA_PH_W_MMR2
5113	{ 2340, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2340 = PRECR_SRA_PH_W	5113	{ 2340, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2340 = PRECR_SRA_PH_W
5114	{ 2339, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	5114	{ 2339, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
5115	{ 2338, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	5115	{ 2338, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
5116	{ 2337, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	5116	{ 2337, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<
5117	{ 2336, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	5117	{ 2336, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<
5118	{ 2335, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2335 = PRECRQ_QB_PH_MM	5118	{ 2335, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2335 = PRECRQ_QB_PH_MM
5119	{ 2334, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2334 = PRECRQ_QB_PH	5119	{ 2334, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2334 = PRECRQ_QB_PH
5120	{ 2333, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2333 = PRECRQ_PH_W_MM	5120	{ 2333, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2333 = PRECRQ_PH_W_MM
5121	{ 2332, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2332 = PRECRQ_PH_W	5121	{ 2332, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2332 = PRECRQ_PH_W
5122	{ 2331, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	5122	{ 2331, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<
5123	{ 2330, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	5123	{ 2330, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<
5124	{ 2329, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2329 = PRECEU_PH_QBR_MM	5124	{ 2329, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2329 = PRECEU_PH_QBR_MM
5125	{ 2328, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2328 = PRECEU_PH_QBRA_MM	5125	{ 2328, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2328 = PRECEU_PH_QBRA_MM
5126	{ 2327, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2327 = PRECEU_PH_QBRA	5126	{ 2327, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2327 = PRECEU_PH_QBRA
5127	{ 2326, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2326 = PRECEU_PH_QBR	5127	{ 2326, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2326 = PRECEU_PH_QBR
5128	{ 2325, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2325 = PRECEU_PH_QBL_MM	5128	{ 2325, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2325 = PRECEU_PH_QBL_MM
5129	{ 2324, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2324 = PRECEU_PH_QBLA_MM	5129	{ 2324, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2324 = PRECEU_PH_QBLA_MM
5130	{ 2323, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2323 = PRECEU_PH_QBLA	5130	{ 2323, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2323 = PRECEU_PH_QBLA
5131	{ 2322, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2322 = PRECEU_PH_QBL	5131	{ 2322, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2322 = PRECEU_PH_QBL
5132	{ 2321, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2321 = PRECEQ_W_PHR_MM	5132	{ 2321, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2321 = PRECEQ_W_PHR_MM
5133	{ 2320, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2320 = PRECEQ_W_PHR	5133	{ 2320, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2320 = PRECEQ_W_PHR
5134	{ 2319, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2319 = PRECEQ_W_PHL_MM	5134	{ 2319, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2319 = PRECEQ_W_PHL_MM
5135	{ 2318, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2318 = PRECEQ_W_PHL	5135	{ 2318, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2318 = PRECEQ_W_PHL
5136	{ 2317, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2317 = PRECEQU_PH_QBR_MM	5136	{ 2317, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2317 = PRECEQU_PH_QBR_MM
5137	{ 2316, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2316 = PRECEQU_PH_QBRA_MM	5137	{ 2316, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2316 = PRECEQU_PH_QBRA_MM
5138	{ 2315, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2315 = PRECEQU_PH_QBRA	5138	{ 2315, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2315 = PRECEQU_PH_QBRA
5139	{ 2314, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2314 = PRECEQU_PH_QBR	5139	{ 2314, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2314 = PRECEQU_PH_QBR
5140	{ 2313, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2313 = PRECEQU_PH_QBL_MM	5140	{ 2313, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2313 = PRECEQU_PH_QBL_MM
5141	{ 2312, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2312 = PRECEQU_PH_QBLA_MM	5141	{ 2312, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2312 = PRECEQU_PH_QBLA_MM
5142	{ 2311, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2311 = PRECEQU_PH_QBLA	5142	{ 2311, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2311 = PRECEQU_PH_QBLA
5143	{ 2310, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2310 = PRECEQU_PH_QBL	5143	{ 2310, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2310 = PRECEQU_PH_QBL
5144	{ 2309, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2309 = POP	5144	{ 2309, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2309 = POP
5145	{ 2308, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5145	{ 2308, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5146	{ 2307, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5146	{ 2307, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5147	{ 2306, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	5147	{ 2306, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<
5148	{ 2305, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	5148	{ 2305, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<
5149	{ 2304, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	5149	{ 2304, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<
5150	{ 2303, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	5150	{ 2303, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<
5151	{ 2302, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2302 = PCNT_W	5151	{ 2302, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2302 = PCNT_W
5152	{ 2301, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2301 = PCNT_H	5152	{ 2301, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2301 = PCNT_H
5153	{ 2300, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2300 = PCNT_D	5153	{ 2300, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2300 = PCNT_D
5154	{ 2299, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2299 = PCNT_B	5154	{ 2299, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2299 = PCNT_B
5155	{ 2298, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2298 = PCKOD_W	5155	{ 2298, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2298 = PCKOD_W
5156	{ 2297, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2297 = PCKOD_H	5156	{ 2297, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2297 = PCKOD_H
5157	{ 2296, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2296 = PCKOD_D	5157	{ 2296, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2296 = PCKOD_D
5158	{ 2295, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2295 = PCKOD_B	5158	{ 2295, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2295 = PCKOD_B
5159	{ 2294, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2294 = PCKEV_W	5159	{ 2294, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2294 = PCKEV_W
5160	{ 2293, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2293 = PCKEV_H	5160	{ 2293, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2293 = PCKEV_H
5161	{ 2292, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2292 = PCKEV_D	5161	{ 2292, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2292 = PCKEV_D
5162	{ 2291, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2291 = PCKEV_B	5162	{ 2291, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2291 = PCKEV_B
5163	{ 2290, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5163	{ 2290, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5164	{ 2289, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5164	{ 2289, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5165	{ 2288, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5165	{ 2288, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5166	{ 2287, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2287 = PACKRL_PH_MM	5166	{ 2287, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2287 = PACKRL_PH_MM
5167	{ 2286, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2286 = PACKRL_PH	5167	{ 2286, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2286 = PACKRL_PH
5168	{ 2285, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	5168	{ 2285, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<
5169	{ 2284, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	5169	{ 2284, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
5170	{ 2283, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	5170	{ 2283, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
5171	{ 2282, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	5171	{ 2282, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
5172	{ 2281, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2281 = OR_V	5172	{ 2281, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2281 = OR_V
5173	{ 2280, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5173	{ 2280, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5174	{ 2279, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5174	{ 2279, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5175	{ 2278, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	5175	{ 2278, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
5176	{ 2277, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2277 = ORI_B	5176	{ 2277, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2277 = ORI_B
5177	{ 2276, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	5177	{ 2276, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
5178	{ 2275, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	5178	{ 2275, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
5179	{ 2274, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	5179	{ 2274, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
5180	{ 2273, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5180	{ 2273, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5181	{ 2272, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2272 = NotRxRy16	5181	{ 2272, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2272 = NotRxRy16
5182	{ 2271, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2271 = NegRxRy16	5182	{ 2271, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2271 = NegRxRy16
5183	{ 2270, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2270 = NOT16_MMR6	5183	{ 2270, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2270 = NOT16_MMR6
5184	{ 2269, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2269 = NOT16_MM	5184	{ 2269, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2269 = NOT16_MM
5185	{ 2268, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2268 = NOR_V	5185	{ 2268, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2268 = NOR_V
5186	{ 2267, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5186	{ 2267, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5187	{ 2266, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5187	{ 2266, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5188	{ 2265, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2265 = NORI_B	5188	{ 2265, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2265 = NORI_B
5189	{ 2264, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	5189	{ 2264, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
5190	{ 2263, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5190	{ 2263, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5191	{ 2262, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2262 = NMSUB_S_MM	5191	{ 2262, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2262 = NMSUB_S_MM
5192	{ 2261, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2261 = NMSUB_S	5192	{ 2261, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2261 = NMSUB_S
5193	{ 2260, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2260 = NMSUB_D64	5193	{ 2260, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2260 = NMSUB_D64
5194	{ 2259, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2259 = NMSUB_D32_MM	5194	{ 2259, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2259 = NMSUB_D32_MM
5195	{ 2258, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2258 = NMSUB_D32	5195	{ 2258, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2258 = NMSUB_D32
5196	{ 2257, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2257 = NMADD_S_MM	5196	{ 2257, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2257 = NMADD_S_MM
5197	{ 2256, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2256 = NMADD_S	5197	{ 2256, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2256 = NMADD_S
5198	{ 2255, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2255 = NMADD_D64	5198	{ 2255, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2255 = NMADD_D64
5199	{ 2254, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2254 = NMADD_D32_MM	5199	{ 2254, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2254 = NMADD_D32_MM
5200	{ 2253, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2253 = NMADD_D32	5200	{ 2253, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2253 = NMADD_D32
5201	{ 2252, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2252 = NLZC_W	5201	{ 2252, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2252 = NLZC_W
5202	{ 2251, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2251 = NLZC_H	5202	{ 2251, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2251 = NLZC_H
5203	{ 2250, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2250 = NLZC_D	5203	{ 2250, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2250 = NLZC_D
5204	{ 2249, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2249 = NLZC_B	5204	{ 2249, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2249 = NLZC_B
5205	{ 2248, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2248 = NLOC_W	5205	{ 2248, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2248 = NLOC_W
5206	{ 2247, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2247 = NLOC_H	5206	{ 2247, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2247 = NLOC_H
5207	{ 2246, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2246 = NLOC_D	5207	{ 2246, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2246 = NLOC_D
5208	{ 2245, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2245 = NLOC_B	5208	{ 2245, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2245 = NLOC_B
5209	{ 2244, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1028, 0\|(1ULL<	5209	{ 2244, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1028, 0\|(1ULL<
5210	{ 2243, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1026, 0\|(1ULL<	5210	{ 2243, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1026, 0\|(1ULL<
5211	{ 2242, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 829, 0, 0x0ULL }, // Inst #2242 = Mflo16	5211	{ 2242, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 829, 0, 0x0ULL }, // Inst #2242 = Mflo16
5212	{ 2241, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 829, 0\|(1ULL<	5212	{ 2241, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 829, 0\|(1ULL<
5213	{ 2240, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5213	{ 2240, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5214	{ 2239, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5214	{ 2239, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5215	{ 2238, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2238 = MUL_R6	5215	{ 2238, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2238 = MUL_R6
5216	{ 2237, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2237 = MUL_Q_W	5216	{ 2237, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2237 = MUL_Q_W
5217	{ 2236, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2236 = MUL_Q_H	5217	{ 2236, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2236 = MUL_Q_H
5218	{ 2235, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5218	{ 2235, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5219	{ 2234, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5219	{ 2234, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5220	{ 2233, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5220	{ 2233, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5221	{ 2232, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	5221	{ 2232, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<
5222	{ 2231, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2231 = MULV_W	5222	{ 2231, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2231 = MULV_W
5223	{ 2230, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2230 = MULV_H	5223	{ 2230, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2230 = MULV_H
5224	{ 2229, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2229 = MULV_D	5224	{ 2229, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2229 = MULV_D
5225	{ 2228, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2228 = MULV_B	5225	{ 2228, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2228 = MULV_B
5226	{ 2227, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5226	{ 2227, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5227	{ 2226, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5227	{ 2226, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5228	{ 2225, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5228	{ 2225, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5229	{ 2224, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5229	{ 2224, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5230	{ 2223, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5230	{ 2223, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5231	{ 2222, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	5231	{ 2222, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<
5232	{ 2221, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	5232	{ 2221, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<
5233	{ 2220, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	5233	{ 2220, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<
5234	{ 2219, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	5234	{ 2219, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<
5235	{ 2218, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	5235	{ 2218, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<
5236	{ 2217, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2217 = MULSA_W_PH_MMR2	5236	{ 2217, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2217 = MULSA_W_PH_MMR2
5237	{ 2216, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2216 = MULSA_W_PH	5237	{ 2216, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2216 = MULSA_W_PH
5238	{ 2215, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5238	{ 2215, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5239	{ 2214, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5239	{ 2214, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5240	{ 2213, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2213 = MULR_Q_W	5240	{ 2213, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2213 = MULR_Q_W
5241	{ 2212, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2212 = MULR_Q_H	5241	{ 2212, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2212 = MULR_Q_H
5242	{ 2211, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5242	{ 2211, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5243	{ 2210, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	5243	{ 2210, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<
5244	{ 2209, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	5244	{ 2209, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<
5245	{ 2208, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5245	{ 2208, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5246	{ 2207, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5246	{ 2207, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5247	{ 2206, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	5247	{ 2206, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<
5248	{ 2205, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	5248	{ 2205, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<
5249	{ 2204, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5249	{ 2204, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5250	{ 2203, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5250	{ 2203, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5251	{ 2202, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5251	{ 2202, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5252	{ 2201, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5252	{ 2201, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5253	{ 2200, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5253	{ 2200, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5254	{ 2199, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	5254	{ 2199, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<
5255	{ 2198, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	5255	{ 2198, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<
5256	{ 2197, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	5256	{ 2197, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<
5257	{ 2196, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	5257	{ 2196, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<
5258	{ 2195, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	5258	{ 2195, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<
5259	{ 2194, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	5259	{ 2194, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<
5260	{ 2193, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5260	{ 2193, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5261	{ 2192, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5261	{ 2192, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5262	{ 2191, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2191 = MUHU	5262	{ 2191, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2191 = MUHU
5263	{ 2190, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2190 = MUH	5263	{ 2190, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2190 = MUH
5264	{ 2189, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	5264	{ 2189, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<
5265	{ 2188, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 302, 0\|(1ULL<	5265	{ 2188, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 302, 0\|(1ULL<
5266	{ 2187, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 302, 0\|(1ULL<	5266	{ 2187, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 302, 0\|(1ULL<
5267	{ 2186, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 302, 0\|(1ULL<	5267	{ 2186, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 302, 0\|(1ULL<
5268	{ 2185, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 302, 0\|(1ULL<	5268	{ 2185, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 302, 0\|(1ULL<
5269	{ 2184, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 302, 0\|(1ULL<	5269	{ 2184, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 302, 0\|(1ULL<
5270	{ 2183, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 302, 0\|(1ULL<	5270	{ 2183, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 302, 0\|(1ULL<
5271	{ 2182, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	5271	{ 2182, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<
5272	{ 2181, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	5272	{ 2181, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<
5273	{ 2180, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	5273	{ 2180, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<
5274	{ 2179, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 302, 0\|(1ULL<	5274	{ 2179, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 302, 0\|(1ULL<
5275	{ 2178, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	5275	{ 2178, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<
5276	{ 2177, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	5276	{ 2177, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<
5277	{ 2176, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	5277	{ 2176, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<
5278	{ 2175, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	5278	{ 2175, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<
5279	{ 2174, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	5279	{ 2174, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<
5280	{ 2173, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	5280	{ 2173, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<
5281	{ 2172, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 302, 0\|(1ULL<	5281	{ 2172, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 302, 0\|(1ULL<
5282	{ 2171, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	5282	{ 2171, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<
5283	{ 2170, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5283	{ 2170, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5284	{ 2169, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5284	{ 2169, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5285	{ 2168, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	5285	{ 2168, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<
5286	{ 2167, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	5286	{ 2167, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<
5287	{ 2166, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	5287	{ 2166, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<
5288	{ 2165, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	5288	{ 2165, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<
5289	{ 2164, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	5289	{ 2164, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<
5290	{ 2163, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5290	{ 2163, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5291	{ 2162, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5291	{ 2162, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5292	{ 2161, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5292	{ 2161, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5293	{ 2160, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	5293	{ 2160, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<
5294	{ 2159, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1010, 0\|(1ULL<	5294	{ 2159, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1010, 0\|(1ULL<
5295	{ 2158, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	5295	{ 2158, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
5296	{ 2157, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	5296	{ 2157, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
5297	{ 2156, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	5297	{ 2156, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<
5298	{ 2155, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	5298	{ 2155, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<
5299	{ 2154, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	5299	{ 2154, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
5300	{ 2153, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5300	{ 2153, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5301	{ 2152, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	5301	{ 2152, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
5302	{ 2151, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	5302	{ 2151, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<
5303	{ 2150, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2150 = MSUB_S	5303	{ 2150, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2150 = MSUB_S
5304	{ 2149, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2149 = MSUB_Q_W	5304	{ 2149, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2149 = MSUB_Q_W
5305	{ 2148, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUB_Q_H	5305	{ 2148, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUB_Q_H
5306	{ 2147, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5306	{ 2147, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5307	{ 2146, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2146 = MSUB_DSP_MM	5307	{ 2146, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2146 = MSUB_DSP_MM
5308	{ 2145, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2145 = MSUB_DSP	5308	{ 2145, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2145 = MSUB_DSP
5309	{ 2144, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2144 = MSUB_D64	5309	{ 2144, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2144 = MSUB_D64
5310	{ 2143, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	5310	{ 2143, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<
5311	{ 2142, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2142 = MSUB_D32	5311	{ 2142, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2142 = MSUB_D32
5312	{ 2141, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2141 = MSUBV_W	5312	{ 2141, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2141 = MSUBV_W
5313	{ 2140, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2140 = MSUBV_H	5313	{ 2140, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2140 = MSUBV_H
5314	{ 2139, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2139 = MSUBV_D	5314	{ 2139, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2139 = MSUBV_D
5315	{ 2138, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2138 = MSUBV_B	5315	{ 2138, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2138 = MSUBV_B
5316	{ 2137, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5316	{ 2137, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5317	{ 2136, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2136 = MSUBU_DSP_MM	5317	{ 2136, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2136 = MSUBU_DSP_MM
5318	{ 2135, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2135 = MSUBU_DSP	5318	{ 2135, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2135 = MSUBU_DSP
5319	{ 2134, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5319	{ 2134, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5320	{ 2133, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2133 = MSUBR_Q_W	5320	{ 2133, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2133 = MSUBR_Q_W
5321	{ 2132, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2132 = MSUBR_Q_H	5321	{ 2132, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2132 = MSUBR_Q_H
5322	{ 2131, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	5322	{ 2131, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<
5323	{ 2130, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	5323	{ 2130, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<
5324	{ 2129, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	5324	{ 2129, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<
5325	{ 2128, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	5325	{ 2128, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<
5326	{ 2127, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5326	{ 2127, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5327	{ 2126, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2126 = MOVZ_I_S_MM	5327	{ 2126, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2126 = MOVZ_I_S_MM
5328	{ 2125, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2125 = MOVZ_I_S	5328	{ 2125, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2125 = MOVZ_I_S
5329	{ 2124, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2124 = MOVZ_I_MM	5329	{ 2124, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2124 = MOVZ_I_MM
5330	{ 2123, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2123 = MOVZ_I_I64	5330	{ 2123, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2123 = MOVZ_I_I64
5331	{ 2122, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2122 = MOVZ_I_I	5331	{ 2122, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2122 = MOVZ_I_I
5332	{ 2121, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2121 = MOVZ_I_D64	5332	{ 2121, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2121 = MOVZ_I_D64
5333	{ 2120, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2120 = MOVZ_I_D32_MM	5333	{ 2120, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2120 = MOVZ_I_D32_MM
5334	{ 2119, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2119 = MOVZ_I_D32	5334	{ 2119, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2119 = MOVZ_I_D32
5335	{ 2118, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2118 = MOVZ_I64_S	5335	{ 2118, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2118 = MOVZ_I64_S
5336	{ 2117, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2117 = MOVZ_I64_I64	5336	{ 2117, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2117 = MOVZ_I64_I64
5337	{ 2116, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2116 = MOVZ_I64_I	5337	{ 2116, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2116 = MOVZ_I64_I
5338	{ 2115, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2115 = MOVZ_I64_D64	5338	{ 2115, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2115 = MOVZ_I64_D64
5339	{ 2114, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2114 = MOVT_S_MM	5339	{ 2114, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2114 = MOVT_S_MM
5340	{ 2113, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2113 = MOVT_S	5340	{ 2113, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2113 = MOVT_S
5341	{ 2112, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2112 = MOVT_I_MM	5341	{ 2112, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2112 = MOVT_I_MM
5342	{ 2111, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2111 = MOVT_I64	5342	{ 2111, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2111 = MOVT_I64
5343	{ 2110, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2110 = MOVT_I	5343	{ 2110, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2110 = MOVT_I
5344	{ 2109, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2109 = MOVT_D64	5344	{ 2109, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2109 = MOVT_D64
5345	{ 2108, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2108 = MOVT_D32_MM	5345	{ 2108, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2108 = MOVT_D32_MM
5346	{ 2107, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2107 = MOVT_D32	5346	{ 2107, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2107 = MOVT_D32
5347	{ 2106, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2106 = MOVN_I_S_MM	5347	{ 2106, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2106 = MOVN_I_S_MM
5348	{ 2105, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2105 = MOVN_I_S	5348	{ 2105, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2105 = MOVN_I_S
5349	{ 2104, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2104 = MOVN_I_MM	5349	{ 2104, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2104 = MOVN_I_MM
5350	{ 2103, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2103 = MOVN_I_I64	5350	{ 2103, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2103 = MOVN_I_I64
5351	{ 2102, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2102 = MOVN_I_I	5351	{ 2102, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2102 = MOVN_I_I
5352	{ 2101, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2101 = MOVN_I_D64	5352	{ 2101, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2101 = MOVN_I_D64
5353	{ 2100, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2100 = MOVN_I_D32_MM	5353	{ 2100, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2100 = MOVN_I_D32_MM
5354	{ 2099, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2099 = MOVN_I_D32	5354	{ 2099, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2099 = MOVN_I_D32
5355	{ 2098, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2098 = MOVN_I64_S	5355	{ 2098, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2098 = MOVN_I64_S
5356	{ 2097, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2097 = MOVN_I64_I64	5356	{ 2097, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2097 = MOVN_I64_I64
5357	{ 2096, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2096 = MOVN_I64_I	5357	{ 2096, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2096 = MOVN_I64_I
5358	{ 2095, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2095 = MOVN_I64_D64	5358	{ 2095, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2095 = MOVN_I64_D64
5359	{ 2094, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2094 = MOVF_S_MM	5359	{ 2094, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2094 = MOVF_S_MM
5360	{ 2093, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2093 = MOVF_S	5360	{ 2093, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2093 = MOVF_S
5361	{ 2092, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2092 = MOVF_I_MM	5361	{ 2092, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2092 = MOVF_I_MM
5362	{ 2091, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2091 = MOVF_I64	5362	{ 2091, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2091 = MOVF_I64
5363	{ 2090, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2090 = MOVF_I	5363	{ 2090, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2090 = MOVF_I
5364	{ 2089, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2089 = MOVF_D64	5364	{ 2089, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2089 = MOVF_D64
5365	{ 2088, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2088 = MOVF_D32_MM	5365	{ 2088, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2088 = MOVF_D32_MM
5366	{ 2087, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2087 = MOVF_D32	5366	{ 2087, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2087 = MOVF_D32
5367	{ 2086, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 952, 0\|(1ULL<	5367	{ 2086, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 952, 0\|(1ULL<
5368	{ 2085, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	5368	{ 2085, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<
5369	{ 2084, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	5369	{ 2084, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<
5370	{ 2083, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	5370	{ 2083, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
5371	{ 2082, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	5371	{ 2082, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
5372	{ 2081, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2081 = MOD_U_W	5372	{ 2081, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2081 = MOD_U_W
5373	{ 2080, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2080 = MOD_U_H	5373	{ 2080, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2080 = MOD_U_H
5374	{ 2079, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2079 = MOD_U_D	5374	{ 2079, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2079 = MOD_U_D
5375	{ 2078, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2078 = MOD_U_B	5375	{ 2078, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2078 = MOD_U_B
5376	{ 2077, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2077 = MOD_S_W	5376	{ 2077, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2077 = MOD_S_W
5377	{ 2076, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2076 = MOD_S_H	5377	{ 2076, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2076 = MOD_S_H
5378	{ 2075, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2075 = MOD_S_D	5378	{ 2075, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2075 = MOD_S_D
5379	{ 2074, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2074 = MOD_S_B	5379	{ 2074, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2074 = MOD_S_B
5380	{ 2073, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5380	{ 2073, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5381	{ 2072, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5381	{ 2072, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5382	{ 2071, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5382	{ 2071, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5383	{ 2070, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2070 = MODSUB_MM	5383	{ 2070, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2070 = MODSUB_MM
5384	{ 2069, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2069 = MODSUB	5384	{ 2069, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2069 = MODSUB
5385	{ 2068, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5385	{ 2068, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5386	{ 2067, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2067 = MIN_U_W	5386	{ 2067, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2067 = MIN_U_W
5387	{ 2066, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2066 = MIN_U_H	5387	{ 2066, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2066 = MIN_U_H
5388	{ 2065, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2065 = MIN_U_D	5388	{ 2065, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2065 = MIN_U_D
5389	{ 2064, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2064 = MIN_U_B	5389	{ 2064, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2064 = MIN_U_B
5390	{ 2063, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2063 = MIN_S_W	5390	{ 2063, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2063 = MIN_S_W
5391	{ 2062, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5391	{ 2062, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5392	{ 2061, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2061 = MIN_S_H	5392	{ 2061, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2061 = MIN_S_H
5393	{ 2060, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2060 = MIN_S_D	5393	{ 2060, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2060 = MIN_S_D
5394	{ 2059, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2059 = MIN_S_B	5394	{ 2059, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2059 = MIN_S_B
5395	{ 2058, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5395	{ 2058, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5396	{ 2057, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5396	{ 2057, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5397	{ 2056, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5397	{ 2056, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5398	{ 2055, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2055 = MIN_A_W	5398	{ 2055, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2055 = MIN_A_W
5399	{ 2054, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2054 = MIN_A_H	5399	{ 2054, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2054 = MIN_A_H
5400	{ 2053, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2053 = MIN_A_D	5400	{ 2053, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2053 = MIN_A_D
5401	{ 2052, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2052 = MIN_A_B	5401	{ 2052, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2052 = MIN_A_B
5402	{ 2051, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2051 = MINI_U_W	5402	{ 2051, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2051 = MINI_U_W
5403	{ 2050, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2050 = MINI_U_H	5403	{ 2050, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2050 = MINI_U_H
5404	{ 2049, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2049 = MINI_U_D	5404	{ 2049, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2049 = MINI_U_D
5405	{ 2048, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2048 = MINI_U_B	5405	{ 2048, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2048 = MINI_U_B
5406	{ 2047, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2047 = MINI_S_W	5406	{ 2047, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2047 = MINI_S_W
5407	{ 2046, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2046 = MINI_S_H	5407	{ 2046, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2046 = MINI_S_H
5408	{ 2045, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2045 = MINI_S_D	5408	{ 2045, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2045 = MINI_S_D
5409	{ 2044, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2044 = MINI_S_B	5409	{ 2044, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2044 = MINI_S_B
5410	{ 2043, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5410	{ 2043, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5411	{ 2042, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5411	{ 2042, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5412	{ 2041, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5412	{ 2041, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5413	{ 2040, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5413	{ 2040, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5414	{ 2039, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	5414	{ 2039, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<
5415	{ 2038, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5415	{ 2038, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5416	{ 2037, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2037 = MFLO_DSP_MM	5416	{ 2037, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2037 = MFLO_DSP_MM
5417	{ 2036, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	5417	{ 2036, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<
5418	{ 2035, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	5418	{ 2035, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<
5419	{ 2034, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5419	{ 2034, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5420	{ 2033, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5420	{ 2033, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5421	{ 2032, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5421	{ 2032, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5422	{ 2031, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2031 = MFHI_DSP_MM	5422	{ 2031, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2031 = MFHI_DSP_MM
5423	{ 2030, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	5423	{ 2030, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<
5424	{ 2029, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	5424	{ 2029, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<
5425	{ 2028, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5425	{ 2028, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5426	{ 2027, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	5426	{ 2027, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<
5427	{ 2026, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5427	{ 2026, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5428	{ 2025, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5428	{ 2025, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5429	{ 2024, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	5429	{ 2024, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<
5430	{ 2023, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	5430	{ 2023, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<
5431	{ 2022, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	5431	{ 2022, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<
5432	{ 2021, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	5432	{ 2021, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<
5433	{ 2020, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	5433	{ 2020, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<
5434	{ 2019, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5434	{ 2019, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5435	{ 2018, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5435	{ 2018, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5436	{ 2017, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5436	{ 2017, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5437	{ 2016, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	5437	{ 2016, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<
5438	{ 2015, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 938, 0\|(1ULL<	5438	{ 2015, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 938, 0\|(1ULL<
5439	{ 2014, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	5439	{ 2014, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<
5440	{ 2013, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	5440	{ 2013, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<
5441	{ 2012, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	5441	{ 2012, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<
5442	{ 2011, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	5442	{ 2011, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<
5443	{ 2010, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5443	{ 2010, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5444	{ 2009, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	5444	{ 2009, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
5445	{ 2008, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2008 = MAX_U_W	5445	{ 2008, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2008 = MAX_U_W
5446	{ 2007, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2007 = MAX_U_H	5446	{ 2007, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2007 = MAX_U_H
5447	{ 2006, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2006 = MAX_U_D	5447	{ 2006, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2006 = MAX_U_D
5448	{ 2005, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2005 = MAX_U_B	5448	{ 2005, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2005 = MAX_U_B
5449	{ 2004, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2004 = MAX_S_W	5449	{ 2004, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2004 = MAX_S_W
5450	{ 2003, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5450	{ 2003, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5451	{ 2002, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2002 = MAX_S_H	5451	{ 2002, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2002 = MAX_S_H
5452	{ 2001, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2001 = MAX_S_D	5452	{ 2001, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2001 = MAX_S_D
5453	{ 2000, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2000 = MAX_S_B	5453	{ 2000, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2000 = MAX_S_B
5454	{ 1999, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5454	{ 1999, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5455	{ 1998, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5455	{ 1998, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5456	{ 1997, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5456	{ 1997, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5457	{ 1996, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1996 = MAX_A_W	5457	{ 1996, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1996 = MAX_A_W
5458	{ 1995, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1995 = MAX_A_H	5458	{ 1995, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1995 = MAX_A_H
5459	{ 1994, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1994 = MAX_A_D	5459	{ 1994, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1994 = MAX_A_D
5460	{ 1993, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1993 = MAX_A_B	5460	{ 1993, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1993 = MAX_A_B
5461	{ 1992, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1992 = MAXI_U_W	5461	{ 1992, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1992 = MAXI_U_W
5462	{ 1991, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1991 = MAXI_U_H	5462	{ 1991, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1991 = MAXI_U_H
5463	{ 1990, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1990 = MAXI_U_D	5463	{ 1990, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1990 = MAXI_U_D
5464	{ 1989, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1989 = MAXI_U_B	5464	{ 1989, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1989 = MAXI_U_B
5465	{ 1988, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1988 = MAXI_S_W	5465	{ 1988, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1988 = MAXI_S_W
5466	{ 1987, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1987 = MAXI_S_H	5466	{ 1987, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1987 = MAXI_S_H
5467	{ 1986, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1986 = MAXI_S_D	5467	{ 1986, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1986 = MAXI_S_D
5468	{ 1985, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1985 = MAXI_S_B	5468	{ 1985, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1985 = MAXI_S_B
5469	{ 1984, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5469	{ 1984, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5470	{ 1983, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5470	{ 1983, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5471	{ 1982, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5471	{ 1982, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5472	{ 1981, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5472	{ 1981, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5473	{ 1980, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5473	{ 1980, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5474	{ 1979, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5474	{ 1979, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5475	{ 1978, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5475	{ 1978, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5476	{ 1977, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5476	{ 1977, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5477	{ 1976, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5477	{ 1976, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5478	{ 1975, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5478	{ 1975, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5479	{ 1974, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5479	{ 1974, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5480	{ 1973, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5480	{ 1973, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5481	{ 1972, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	5481	{ 1972, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<
5482	{ 1971, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1971 = MADD_S	5482	{ 1971, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1971 = MADD_S
5483	{ 1970, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1970 = MADD_Q_W	5483	{ 1970, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1970 = MADD_Q_W
5484	{ 1969, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADD_Q_H	5484	{ 1969, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADD_Q_H
5485	{ 1968, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5485	{ 1968, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5486	{ 1967, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1967 = MADD_DSP_MM	5486	{ 1967, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1967 = MADD_DSP_MM
5487	{ 1966, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1966 = MADD_DSP	5487	{ 1966, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1966 = MADD_DSP
5488	{ 1965, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1965 = MADD_D64	5488	{ 1965, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1965 = MADD_D64
5489	{ 1964, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	5489	{ 1964, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<
5490	{ 1963, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #1963 = MADD_D32	5490	{ 1963, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #1963 = MADD_D32
5491	{ 1962, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1962 = MADDV_W	5491	{ 1962, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1962 = MADDV_W
5492	{ 1961, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1961 = MADDV_H	5492	{ 1961, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1961 = MADDV_H
5493	{ 1960, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1960 = MADDV_D	5493	{ 1960, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1960 = MADDV_D
5494	{ 1959, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1959 = MADDV_B	5494	{ 1959, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1959 = MADDV_B
5495	{ 1958, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5495	{ 1958, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5496	{ 1957, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1957 = MADDU_DSP_MM	5496	{ 1957, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1957 = MADDU_DSP_MM
5497	{ 1956, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1956 = MADDU_DSP	5497	{ 1956, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1956 = MADDU_DSP
5498	{ 1955, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5498	{ 1955, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5499	{ 1954, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1954 = MADDR_Q_W	5499	{ 1954, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1954 = MADDR_Q_W
5500	{ 1953, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1953 = MADDR_Q_H	5500	{ 1953, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1953 = MADDR_Q_H
5501	{ 1952, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	5501	{ 1952, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<
5502	{ 1951, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	5502	{ 1951, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<
5503	{ 1950, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	5503	{ 1950, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<
5504	{ 1949, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	5504	{ 1949, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<
5505	{ 1948, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	5505	{ 1948, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<
5506	{ 1947, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	5506	{ 1947, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<
5507	{ 1946, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	5507	{ 1946, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
5508	{ 1945, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	5508	{ 1945, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<
5509	{ 1944, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	5509	{ 1944, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<
5510	{ 1943, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0, 0x0ULL }, // Inst #1943 = LiRxImmX16	5510	{ 1943, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0, 0x0ULL }, // Inst #1943 = LiRxImmX16
5511	{ 1942, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	5511	{ 1942, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<
5512	{ 1941, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	5512	{ 1941, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<
5513	{ 1940, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	5513	{ 1940, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
5514	{ 1939, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	5514	{ 1939, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
5515	{ 1938, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	5515	{ 1938, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
5516	{ 1937, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	5516	{ 1937, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<
5517	{ 1936, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5517	{ 1936, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5518	{ 1935, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5518	{ 1935, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5519	{ 1934, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5519	{ 1934, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5520	{ 1933, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5520	{ 1933, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5521	{ 1932, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5521	{ 1932, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5522	{ 1931, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	5522	{ 1931, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<
5523	{ 1930, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	5523	{ 1930, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<
5524	{ 1929, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5524	{ 1929, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5525	{ 1928, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5525	{ 1928, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5526	{ 1927, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5526	{ 1927, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5527	{ 1926, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	5527	{ 1926, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<
5528	{ 1925, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5528	{ 1925, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5529	{ 1924, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5529	{ 1924, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5530	{ 1923, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5530	{ 1923, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5531	{ 1922, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	5531	{ 1922, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<
5532	{ 1921, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5532	{ 1921, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5533	{ 1920, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	5533	{ 1920, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<
5534	{ 1919, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5534	{ 1919, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5535	{ 1918, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5535	{ 1918, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5536	{ 1917, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	5536	{ 1917, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<
5537	{ 1916, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	5537	{ 1916, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<
5538	{ 1915, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	5538	{ 1915, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<
5539	{ 1914, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5539	{ 1914, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5540	{ 1913, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5540	{ 1913, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5541	{ 1912, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5541	{ 1912, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5542	{ 1911, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	5542	{ 1911, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<
5543	{ 1910, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	5543	{ 1910, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<
5544	{ 1909, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 890, 0\|(1ULL<	5544	{ 1909, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 890, 0\|(1ULL<
5545	{ 1908, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5545	{ 1908, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5546	{ 1907, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5546	{ 1907, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5547	{ 1906, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	5547	{ 1906, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<
5548	{ 1905, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	5548	{ 1905, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<
5549	{ 1904, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	5549	{ 1904, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<
5550	{ 1903, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5550	{ 1903, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5551	{ 1902, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	5551	{ 1902, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<
5552	{ 1901, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5552	{ 1901, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5553	{ 1900, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	5553	{ 1900, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<
5554	{ 1899, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	5554	{ 1899, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<
5555	{ 1898, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5555	{ 1898, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5556	{ 1897, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	5556	{ 1897, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<
5557	{ 1896, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5557	{ 1896, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5558	{ 1895, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5558	{ 1895, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5559	{ 1894, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	5559	{ 1894, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
5560	{ 1893, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5560	{ 1893, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5561	{ 1892, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	5561	{ 1892, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
5562	{ 1891, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	5562	{ 1891, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
5563	{ 1890, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	5563	{ 1890, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<
5564	{ 1889, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5564	{ 1889, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5565	{ 1888, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	5565	{ 1888, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<
5566	{ 1887, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	5566	{ 1887, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<
5567	{ 1886, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 553, 0, 0x6ULL }, // Inst #1886 = LSA	5567	{ 1886, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 553, 0, 0x6ULL }, // Inst #1886 = LSA
5568	{ 1885, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	5568	{ 1885, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<
5569	{ 1884, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5569	{ 1884, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5570	{ 1883, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5570	{ 1883, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5571	{ 1882, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5571	{ 1882, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5572	{ 1881, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5572	{ 1881, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5573	{ 1880, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 881, 0\|(1ULL<	5573	{ 1880, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 881, 0\|(1ULL<
5574	{ 1879, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5574	{ 1879, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5575	{ 1878, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	5575	{ 1878, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<
5576	{ 1877, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5576	{ 1877, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5577	{ 1876, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5577	{ 1876, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5578	{ 1875, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	5578	{ 1875, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<
5579	{ 1874, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	5579	{ 1874, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<
5580	{ 1873, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5580	{ 1873, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5581	{ 1872, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5581	{ 1872, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5582	{ 1871, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5582	{ 1871, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5583	{ 1870, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5583	{ 1870, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5584	{ 1869, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5584	{ 1869, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5585	{ 1868, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5585	{ 1868, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5586	{ 1867, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5586	{ 1867, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5587	{ 1866, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5587	{ 1866, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5588	{ 1865, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	5588	{ 1865, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<
5589	{ 1864, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5589	{ 1864, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5590	{ 1863, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5590	{ 1863, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5591	{ 1862, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5591	{ 1862, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5592	{ 1861, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5592	{ 1861, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5593	{ 1860, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1860 = LEA_ADDiu_MM	5593	{ 1860, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1860 = LEA_ADDiu_MM
5594	{ 1859, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 352, 0, 0x2ULL }, // Inst #1859 = LEA_ADDiu64	5594	{ 1859, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 352, 0, 0x2ULL }, // Inst #1859 = LEA_ADDiu64
5595	{ 1858, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1858 = LEA_ADDiu	5595	{ 1858, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1858 = LEA_ADDiu
5596	{ 1857, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	5596	{ 1857, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<
5597	{ 1856, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	5597	{ 1856, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<
5598	{ 1855, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	5598	{ 1855, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<
5599	{ 1854, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	5599	{ 1854, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<
5600	{ 1853, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	5600	{ 1853, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<
5601	{ 1852, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	5601	{ 1852, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<
5602	{ 1851, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	5602	{ 1851, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<
5603	{ 1850, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	5603	{ 1850, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
5604	{ 1849, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	5604	{ 1849, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<
5605	{ 1848, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0\|(1ULL<	5605	{ 1848, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0\|(1ULL<
5606	{ 1847, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0\|(1ULL<	5606	{ 1847, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0\|(1ULL<
5607	{ 1846, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 850, 0\|(1ULL<	5607	{ 1846, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 850, 0\|(1ULL<
5608	{ 1845, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 848, 0\|(1ULL<	5608	{ 1845, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 848, 0\|(1ULL<
5609	{ 1844, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	5609	{ 1844, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<
5610	{ 1843, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5610	{ 1843, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5611	{ 1842, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	5611	{ 1842, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<
5612	{ 1841, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	5612	{ 1841, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<
5613	{ 1840, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5613	{ 1840, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5614	{ 1839, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	5614	{ 1839, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<
5615	{ 1838, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5615	{ 1838, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5616	{ 1837, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	5616	{ 1837, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<
5617	{ 1836, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	5617	{ 1836, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<
5618	{ 1835, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5618	{ 1835, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5619	{ 1834, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5619	{ 1834, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5620	{ 1833, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5620	{ 1833, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5621	{ 1832, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5621	{ 1832, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5622	{ 1831, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5622	{ 1831, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5623	{ 1830, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5623	{ 1830, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5624	{ 1829, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5624	{ 1829, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5625	{ 1828, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5625	{ 1828, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5626	{ 1827, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5626	{ 1827, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5627	{ 1826, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5627	{ 1826, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5628	{ 1825, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	5628	{ 1825, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<
5629	{ 1824, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	5629	{ 1824, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<
5630	{ 1823, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5630	{ 1823, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5631	{ 1822, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5631	{ 1822, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5632	{ 1821, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	5632	{ 1821, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
5633	{ 1820, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	5633	{ 1820, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
5634	{ 1819, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 829, 0\|(1ULL<	5634	{ 1819, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 829, 0\|(1ULL<
5635	{ 1818, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 829, 0\|(1ULL<	5635	{ 1818, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 829, 0\|(1ULL<
5636	{ 1817, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5636	{ 1817, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5637	{ 1816, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5637	{ 1816, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5638	{ 1815, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5638	{ 1815, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5639	{ 1814, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5639	{ 1814, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5640	{ 1813, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	5640	{ 1813, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<
5641	{ 1812, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5641	{ 1812, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5642	{ 1811, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5642	{ 1811, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5643	{ 1810, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	5643	{ 1810, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
5644	{ 1809, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	5644	{ 1809, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
5645	{ 1808, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5645	{ 1808, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5646	{ 1807, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5646	{ 1807, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5647	{ 1806, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5647	{ 1806, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5648	{ 1805, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5648	{ 1805, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5649	{ 1804, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5649	{ 1804, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5650	{ 1803, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	5650	{ 1803, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
5651	{ 1802, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5651	{ 1802, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5652	{ 1801, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5652	{ 1801, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5653	{ 1800, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	5653	{ 1800, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<
5654	{ 1799, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 350, 0\|(1ULL<	5654	{ 1799, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 350, 0\|(1ULL<
5655	{ 1798, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	5655	{ 1798, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<
5656	{ 1797, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	5656	{ 1797, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<
5657	{ 1796, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 350, 0\|(1ULL<	5657	{ 1796, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 350, 0\|(1ULL<
5658	{ 1795, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	5658	{ 1795, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<
5659	{ 1794, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5659	{ 1794, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5660	{ 1793, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5660	{ 1793, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5661	{ 1792, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5661	{ 1792, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5662	{ 1791, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5662	{ 1791, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5663	{ 1790, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	5663	{ 1790, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<
5664	{ 1789, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	5664	{ 1789, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<
5665	{ 1788, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	5665	{ 1788, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
5666	{ 1787, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	5666	{ 1787, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<
5667	{ 1786, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	5667	{ 1786, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<
5668	{ 1785, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	5668	{ 1785, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<
5669	{ 1784, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	5669	{ 1784, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
5670	{ 1783, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	5670	{ 1783, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<
5671	{ 1782, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 373, 0\|(1ULL<	5671	{ 1782, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 373, 0\|(1ULL<
5672	{ 1781, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	5672	{ 1781, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<
5673	{ 1780, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	5673	{ 1780, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<
5674	{ 1779, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	5674	{ 1779, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
5675	{ 1778, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	5675	{ 1778, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<
5676	{ 1777, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 785, 0, 0x1ULL }, // Inst #1777 = INS_MMR6	5676	{ 1777, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 785, 0, 0x1ULL }, // Inst #1777 = INS_MMR6
5677	{ 1776, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	5677	{ 1776, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<
5678	{ 1775, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	5678	{ 1775, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<
5679	{ 1774, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 824, 0, 0x6ULL }, // Inst #1774 = INSVE_W	5679	{ 1774, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 824, 0, 0x6ULL }, // Inst #1774 = INSVE_W
5680	{ 1773, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 819, 0, 0x6ULL }, // Inst #1773 = INSVE_H	5680	{ 1773, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 819, 0, 0x6ULL }, // Inst #1773 = INSVE_H
5681	{ 1772, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1772 = INSVE_D	5681	{ 1772, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1772 = INSVE_D
5682	{ 1771, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 809, 0, 0x6ULL }, // Inst #1771 = INSVE_B	5682	{ 1771, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 809, 0, 0x6ULL }, // Inst #1771 = INSVE_B
5683	{ 1770, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	5683	{ 1770, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<
5684	{ 1769, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1769 = INSERT_W	5684	{ 1769, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1769 = INSERT_W
5685	{ 1768, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1768 = INSERT_H	5685	{ 1768, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1768 = INSERT_H
5686	{ 1767, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1767 = INSERT_D	5686	{ 1767, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1767 = INSERT_D
5687	{ 1766, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 790, 0, 0x6ULL }, // Inst #1766 = INSERT_B	5687	{ 1766, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 790, 0, 0x6ULL }, // Inst #1766 = INSERT_B
5688	{ 1765, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	5688	{ 1765, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<
5689	{ 1764, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1764 = ILVR_W	5689	{ 1764, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1764 = ILVR_W
5690	{ 1763, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1763 = ILVR_H	5690	{ 1763, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1763 = ILVR_H
5691	{ 1762, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1762 = ILVR_D	5691	{ 1762, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1762 = ILVR_D
5692	{ 1761, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1761 = ILVR_B	5692	{ 1761, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1761 = ILVR_B
5693	{ 1760, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1760 = ILVOD_W	5693	{ 1760, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1760 = ILVOD_W
5694	{ 1759, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1759 = ILVOD_H	5694	{ 1759, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1759 = ILVOD_H
5695	{ 1758, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1758 = ILVOD_D	5695	{ 1758, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1758 = ILVOD_D
5696	{ 1757, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1757 = ILVOD_B	5696	{ 1757, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1757 = ILVOD_B
5697	{ 1756, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1756 = ILVL_W	5697	{ 1756, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1756 = ILVL_W
5698	{ 1755, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1755 = ILVL_H	5698	{ 1755, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1755 = ILVL_H
5699	{ 1754, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1754 = ILVL_D	5699	{ 1754, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1754 = ILVL_D
5700	{ 1753, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1753 = ILVL_B	5700	{ 1753, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1753 = ILVL_B
5701	{ 1752, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1752 = ILVEV_W	5701	{ 1752, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1752 = ILVEV_W
5702	{ 1751, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1751 = ILVEV_H	5702	{ 1751, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1751 = ILVEV_H
5703	{ 1750, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1750 = ILVEV_D	5703	{ 1750, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1750 = ILVEV_D
5704	{ 1749, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1749 = ILVEV_B	5704	{ 1749, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1749 = ILVEV_B
5705	{ 1748, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5705	{ 1748, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5706	{ 1747, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	5706	{ 1747, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
5707	{ 1746, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1746 = HSUB_U_W	5707	{ 1746, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1746 = HSUB_U_W
5708	{ 1745, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1745 = HSUB_U_H	5708	{ 1745, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1745 = HSUB_U_H
5709	{ 1744, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1744 = HSUB_U_D	5709	{ 1744, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1744 = HSUB_U_D
5710	{ 1743, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1743 = HSUB_S_W	5710	{ 1743, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1743 = HSUB_S_W
5711	{ 1742, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1742 = HSUB_S_H	5711	{ 1742, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1742 = HSUB_S_H
5712	{ 1741, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1741 = HSUB_S_D	5712	{ 1741, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1741 = HSUB_S_D
5713	{ 1740, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1740 = HADD_U_W	5713	{ 1740, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1740 = HADD_U_W
5714	{ 1739, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1739 = HADD_U_H	5714	{ 1739, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1739 = HADD_U_H
5715	{ 1738, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1738 = HADD_U_D	5715	{ 1738, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1738 = HADD_U_D
5716	{ 1737, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1737 = HADD_S_W	5716	{ 1737, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1737 = HADD_S_W
5717	{ 1736, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1736 = HADD_S_H	5717	{ 1736, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1736 = HADD_S_H
5718	{ 1735, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1735 = HADD_S_D	5718	{ 1735, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1735 = HADD_S_D
5719	{ 1734, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5719	{ 1734, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5720	{ 1733, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	5720	{ 1733, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
5721	{ 1732, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5721	{ 1732, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5722	{ 1731, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5722	{ 1731, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5723	{ 1730, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1730 = FTRUNC_U_W	5723	{ 1730, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1730 = FTRUNC_U_W
5724	{ 1729, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1729 = FTRUNC_U_D	5724	{ 1729, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1729 = FTRUNC_U_D
5725	{ 1728, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1728 = FTRUNC_S_W	5725	{ 1728, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1728 = FTRUNC_S_W
5726	{ 1727, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1727 = FTRUNC_S_D	5726	{ 1727, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1727 = FTRUNC_S_D
5727	{ 1726, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1726 = FTQ_W	5727	{ 1726, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1726 = FTQ_W
5728	{ 1725, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1725 = FTQ_H	5728	{ 1725, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1725 = FTQ_H
5729	{ 1724, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1724 = FTINT_U_W	5729	{ 1724, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1724 = FTINT_U_W
5730	{ 1723, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1723 = FTINT_U_D	5730	{ 1723, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1723 = FTINT_U_D
5731	{ 1722, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1722 = FTINT_S_W	5731	{ 1722, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1722 = FTINT_S_W
5732	{ 1721, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1721 = FTINT_S_D	5732	{ 1721, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1721 = FTINT_S_D
5733	{ 1720, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1720 = FSUN_W	5733	{ 1720, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1720 = FSUN_W
5734	{ 1719, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1719 = FSUN_D	5734	{ 1719, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1719 = FSUN_D
5735	{ 1718, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1718 = FSUNE_W	5735	{ 1718, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1718 = FSUNE_W
5736	{ 1717, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1717 = FSUNE_D	5736	{ 1717, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1717 = FSUNE_D
5737	{ 1716, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1716 = FSULT_W	5737	{ 1716, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1716 = FSULT_W
5738	{ 1715, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1715 = FSULT_D	5738	{ 1715, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1715 = FSULT_D
5739	{ 1714, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1714 = FSULE_W	5739	{ 1714, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1714 = FSULE_W
5740	{ 1713, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1713 = FSULE_D	5740	{ 1713, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1713 = FSULE_D
5741	{ 1712, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1712 = FSUEQ_W	5741	{ 1712, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1712 = FSUEQ_W
5742	{ 1711, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1711 = FSUEQ_D	5742	{ 1711, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1711 = FSUEQ_D
5743	{ 1710, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1710 = FSUB_W	5743	{ 1710, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1710 = FSUB_W
5744	{ 1709, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1709 = FSUB_S_MMR6	5744	{ 1709, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1709 = FSUB_S_MMR6
5745	{ 1708, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1708 = FSUB_S_MM	5745	{ 1708, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1708 = FSUB_S_MM
5746	{ 1707, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1707 = FSUB_S	5746	{ 1707, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1707 = FSUB_S
5747	{ 1706, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5747	{ 1706, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5748	{ 1705, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1705 = FSUB_D64_MM	5748	{ 1705, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1705 = FSUB_D64_MM
5749	{ 1704, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1704 = FSUB_D64	5749	{ 1704, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1704 = FSUB_D64
5750	{ 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1703 = FSUB_D32_MM	5750	{ 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1703 = FSUB_D32_MM
5751	{ 1702, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1702 = FSUB_D32	5751	{ 1702, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1702 = FSUB_D32
5752	{ 1701, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1701 = FSUB_D	5752	{ 1701, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1701 = FSUB_D
5753	{ 1700, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1700 = FSQRT_W	5753	{ 1700, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1700 = FSQRT_W
5754	{ 1699, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1699 = FSQRT_S_MM	5754	{ 1699, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1699 = FSQRT_S_MM
5755	{ 1698, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1698 = FSQRT_S	5755	{ 1698, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1698 = FSQRT_S
5756	{ 1697, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1697 = FSQRT_D64_MM	5756	{ 1697, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1697 = FSQRT_D64_MM
5757	{ 1696, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1696 = FSQRT_D64	5757	{ 1696, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1696 = FSQRT_D64
5758	{ 1695, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1695 = FSQRT_D32_MM	5758	{ 1695, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1695 = FSQRT_D32_MM
5759	{ 1694, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1694 = FSQRT_D32	5759	{ 1694, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1694 = FSQRT_D32
5760	{ 1693, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1693 = FSQRT_D	5760	{ 1693, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1693 = FSQRT_D
5761	{ 1692, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1692 = FSOR_W	5761	{ 1692, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1692 = FSOR_W
5762	{ 1691, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1691 = FSOR_D	5762	{ 1691, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1691 = FSOR_D
5763	{ 1690, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1690 = FSNE_W	5763	{ 1690, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1690 = FSNE_W
5764	{ 1689, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1689 = FSNE_D	5764	{ 1689, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1689 = FSNE_D
5765	{ 1688, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1688 = FSLT_W	5765	{ 1688, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1688 = FSLT_W
5766	{ 1687, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1687 = FSLT_D	5766	{ 1687, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1687 = FSLT_D
5767	{ 1686, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1686 = FSLE_W	5767	{ 1686, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1686 = FSLE_W
5768	{ 1685, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1685 = FSLE_D	5768	{ 1685, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1685 = FSLE_D
5769	{ 1684, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1684 = FSEQ_W	5769	{ 1684, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1684 = FSEQ_W
5770	{ 1683, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1683 = FSEQ_D	5770	{ 1683, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1683 = FSEQ_D
5771	{ 1682, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1682 = FSAF_W	5771	{ 1682, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1682 = FSAF_W
5772	{ 1681, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1681 = FSAF_D	5772	{ 1681, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1681 = FSAF_D
5773	{ 1680, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1680 = FRSQRT_W	5773	{ 1680, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1680 = FRSQRT_W
5774	{ 1679, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1679 = FRSQRT_D	5774	{ 1679, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1679 = FRSQRT_D
5775	{ 1678, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1678 = FRINT_W	5775	{ 1678, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1678 = FRINT_W
5776	{ 1677, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1677 = FRINT_D	5776	{ 1677, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1677 = FRINT_D
5777	{ 1676, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1676 = FRCP_W	5777	{ 1676, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1676 = FRCP_W
5778	{ 1675, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1675 = FRCP_D	5778	{ 1675, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1675 = FRCP_D
5779	{ 1674, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	5779	{ 1674, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
5780	{ 1673, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1673 = FNEG_S_MMR6	5780	{ 1673, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1673 = FNEG_S_MMR6
5781	{ 1672, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1672 = FNEG_S_MM	5781	{ 1672, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1672 = FNEG_S_MM
5782	{ 1671, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1671 = FNEG_S	5782	{ 1671, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1671 = FNEG_S
5783	{ 1670, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1670 = FNEG_D64_MM	5783	{ 1670, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1670 = FNEG_D64_MM
5784	{ 1669, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1669 = FNEG_D64	5784	{ 1669, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1669 = FNEG_D64
5785	{ 1668, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1668 = FNEG_D32_MM	5785	{ 1668, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1668 = FNEG_D32_MM
5786	{ 1667, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1667 = FNEG_D32	5786	{ 1667, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1667 = FNEG_D32
5787	{ 1666, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1666 = FMUL_W	5787	{ 1666, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1666 = FMUL_W
5788	{ 1665, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5788	{ 1665, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5789	{ 1664, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5789	{ 1664, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5790	{ 1663, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5790	{ 1663, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5791	{ 1662, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5791	{ 1662, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5792	{ 1661, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5792	{ 1661, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5793	{ 1660, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5793	{ 1660, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5794	{ 1659, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	5794	{ 1659, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<
5795	{ 1658, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	5795	{ 1658, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<
5796	{ 1657, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1657 = FMUL_D	5796	{ 1657, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1657 = FMUL_D
5797	{ 1656, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1656 = FMSUB_W	5797	{ 1656, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1656 = FMSUB_W
5798	{ 1655, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1655 = FMSUB_D	5798	{ 1655, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1655 = FMSUB_D
5799	{ 1654, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1654 = FMOV_S_MMR6	5799	{ 1654, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1654 = FMOV_S_MMR6
5800	{ 1653, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	5800	{ 1653, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
5801	{ 1652, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	5801	{ 1652, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
5802	{ 1651, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1651 = FMOV_D_MMR6	5802	{ 1651, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1651 = FMOV_D_MMR6
5803	{ 1650, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1650 = FMOV_D64_MM	5803	{ 1650, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1650 = FMOV_D64_MM
5804	{ 1649, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	5804	{ 1649, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<
5805	{ 1648, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1648 = FMOV_D32_MM	5805	{ 1648, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1648 = FMOV_D32_MM
5806	{ 1647, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 750, 0\|(1ULL<	5806	{ 1647, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 750, 0\|(1ULL<
5807	{ 1646, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1646 = FMIN_W	5807	{ 1646, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1646 = FMIN_W
5808	{ 1645, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1645 = FMIN_D	5808	{ 1645, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1645 = FMIN_D
5809	{ 1644, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1644 = FMIN_A_W	5809	{ 1644, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1644 = FMIN_A_W
5810	{ 1643, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1643 = FMIN_A_D	5810	{ 1643, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1643 = FMIN_A_D
5811	{ 1642, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1642 = FMAX_W	5811	{ 1642, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1642 = FMAX_W
5812	{ 1641, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1641 = FMAX_D	5812	{ 1641, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1641 = FMAX_D
5813	{ 1640, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1640 = FMAX_A_W	5813	{ 1640, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1640 = FMAX_A_W
5814	{ 1639, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1639 = FMAX_A_D	5814	{ 1639, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1639 = FMAX_A_D
5815	{ 1638, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1638 = FMADD_W	5815	{ 1638, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1638 = FMADD_W
5816	{ 1637, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1637 = FMADD_D	5816	{ 1637, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1637 = FMADD_D
5817	{ 1636, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1636 = FLOOR_W_S_MMR6	5817	{ 1636, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1636 = FLOOR_W_S_MMR6
5818	{ 1635, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1635 = FLOOR_W_S_MM	5818	{ 1635, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1635 = FLOOR_W_S_MM
5819	{ 1634, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1634 = FLOOR_W_S	5819	{ 1634, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1634 = FLOOR_W_S
5820	{ 1633, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1633 = FLOOR_W_MM	5820	{ 1633, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1633 = FLOOR_W_MM
5821	{ 1632, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1632 = FLOOR_W_D_MMR6	5821	{ 1632, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1632 = FLOOR_W_D_MMR6
5822	{ 1631, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1631 = FLOOR_W_D64	5822	{ 1631, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1631 = FLOOR_W_D64
5823	{ 1630, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1630 = FLOOR_W_D32	5823	{ 1630, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1630 = FLOOR_W_D32
5824	{ 1629, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1629 = FLOOR_L_S_MMR6	5824	{ 1629, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1629 = FLOOR_L_S_MMR6
5825	{ 1628, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1628 = FLOOR_L_S	5825	{ 1628, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1628 = FLOOR_L_S
5826	{ 1627, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1627 = FLOOR_L_D_MMR6	5826	{ 1627, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1627 = FLOOR_L_D_MMR6
5827	{ 1626, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1626 = FLOOR_L_D64	5827	{ 1626, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1626 = FLOOR_L_D64
5828	{ 1625, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1625 = FLOG2_W	5828	{ 1625, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1625 = FLOG2_W
5829	{ 1624, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1624 = FLOG2_D	5829	{ 1624, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1624 = FLOG2_D
5830	{ 1623, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1623 = FILL_W	5830	{ 1623, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1623 = FILL_W
5831	{ 1622, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1622 = FILL_H	5831	{ 1622, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1622 = FILL_H
5832	{ 1621, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1621 = FILL_D	5832	{ 1621, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1621 = FILL_D
5833	{ 1620, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1620 = FILL_B	5833	{ 1620, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1620 = FILL_B
5834	{ 1619, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1619 = FFQR_W	5834	{ 1619, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1619 = FFQR_W
5835	{ 1618, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1618 = FFQR_D	5835	{ 1618, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1618 = FFQR_D
5836	{ 1617, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1617 = FFQL_W	5836	{ 1617, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1617 = FFQL_W
5837	{ 1616, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1616 = FFQL_D	5837	{ 1616, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1616 = FFQL_D
5838	{ 1615, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1615 = FFINT_U_W	5838	{ 1615, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1615 = FFINT_U_W
5839	{ 1614, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1614 = FFINT_U_D	5839	{ 1614, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1614 = FFINT_U_D
5840	{ 1613, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1613 = FFINT_S_W	5840	{ 1613, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1613 = FFINT_S_W
5841	{ 1612, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1612 = FFINT_S_D	5841	{ 1612, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1612 = FFINT_S_D
5842	{ 1611, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1611 = FEXUPR_W	5842	{ 1611, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1611 = FEXUPR_W
5843	{ 1610, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1610 = FEXUPR_D	5843	{ 1610, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1610 = FEXUPR_D
5844	{ 1609, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1609 = FEXUPL_W	5844	{ 1609, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1609 = FEXUPL_W
5845	{ 1608, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1608 = FEXUPL_D	5845	{ 1608, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1608 = FEXUPL_D
5846	{ 1607, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1607 = FEXP2_W	5846	{ 1607, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1607 = FEXP2_W
5847	{ 1606, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1606 = FEXP2_D	5847	{ 1606, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1606 = FEXP2_D
5848	{ 1605, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1605 = FEXDO_W	5848	{ 1605, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1605 = FEXDO_W
5849	{ 1604, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1604 = FEXDO_H	5849	{ 1604, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1604 = FEXDO_H
5850	{ 1603, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1603 = FDIV_W	5850	{ 1603, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1603 = FDIV_W
5851	{ 1602, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1602 = FDIV_S_MMR6	5851	{ 1602, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1602 = FDIV_S_MMR6
5852	{ 1601, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1601 = FDIV_S_MM	5852	{ 1601, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1601 = FDIV_S_MM
5853	{ 1600, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1600 = FDIV_S	5853	{ 1600, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1600 = FDIV_S
5854	{ 1599, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1599 = FDIV_D64_MM	5854	{ 1599, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1599 = FDIV_D64_MM
5855	{ 1598, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1598 = FDIV_D64	5855	{ 1598, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1598 = FDIV_D64
5856	{ 1597, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1597 = FDIV_D32_MM	5856	{ 1597, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1597 = FDIV_D32_MM
5857	{ 1596, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1596 = FDIV_D32	5857	{ 1596, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1596 = FDIV_D32
5858	{ 1595, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1595 = FDIV_D	5858	{ 1595, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1595 = FDIV_D
5859	{ 1594, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5859	{ 1594, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5860	{ 1593, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5860	{ 1593, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5861	{ 1592, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5861	{ 1592, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5862	{ 1591, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5862	{ 1591, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5863	{ 1590, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5863	{ 1590, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5864	{ 1589, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5864	{ 1589, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5865	{ 1588, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5865	{ 1588, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5866	{ 1587, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5866	{ 1587, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5867	{ 1586, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5867	{ 1586, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5868	{ 1585, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5868	{ 1585, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5869	{ 1584, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5869	{ 1584, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5870	{ 1583, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5870	{ 1583, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5871	{ 1582, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5871	{ 1582, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5872	{ 1581, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5872	{ 1581, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5873	{ 1580, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1580 = FCMP_S32_MM	5873	{ 1580, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1580 = FCMP_S32_MM
5874	{ 1579, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1579 = FCMP_S32	5874	{ 1579, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1579 = FCMP_S32
5875	{ 1578, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 761, 0, 0x44ULL }, // Inst #1578 = FCMP_D64	5875	{ 1578, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 761, 0, 0x44ULL }, // Inst #1578 = FCMP_D64
5876	{ 1577, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1577 = FCMP_D32_MM	5876	{ 1577, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1577 = FCMP_D32_MM
5877	{ 1576, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1576 = FCMP_D32	5877	{ 1576, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1576 = FCMP_D32
5878	{ 1575, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1575 = FCLT_W	5878	{ 1575, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1575 = FCLT_W
5879	{ 1574, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1574 = FCLT_D	5879	{ 1574, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1574 = FCLT_D
5880	{ 1573, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1573 = FCLE_W	5880	{ 1573, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1573 = FCLE_W
5881	{ 1572, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1572 = FCLE_D	5881	{ 1572, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1572 = FCLE_D
5882	{ 1571, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1571 = FCLASS_W	5882	{ 1571, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1571 = FCLASS_W
5883	{ 1570, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1570 = FCLASS_D	5883	{ 1570, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1570 = FCLASS_D
5884	{ 1569, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5884	{ 1569, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5885	{ 1568, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5885	{ 1568, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5886	{ 1567, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5886	{ 1567, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5887	{ 1566, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5887	{ 1566, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5888	{ 1565, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	5888	{ 1565, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
5889	{ 1564, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5889	{ 1564, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5890	{ 1563, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5890	{ 1563, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5891	{ 1562, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	5891	{ 1562, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<
5892	{ 1561, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5892	{ 1561, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5893	{ 1560, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5893	{ 1560, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5894	{ 1559, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	5894	{ 1559, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
5895	{ 1558, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	5895	{ 1558, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<
5896	{ 1557, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	5896	{ 1557, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<
5897	{ 1556, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	5897	{ 1556, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
5898	{ 1555, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1555 = FABS_S_MM	5898	{ 1555, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1555 = FABS_S_MM
5899	{ 1554, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1554 = FABS_S	5899	{ 1554, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1554 = FABS_S
5900	{ 1553, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1553 = FABS_D64_MM	5900	{ 1553, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1553 = FABS_D64_MM
5901	{ 1552, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1552 = FABS_D64	5901	{ 1552, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1552 = FABS_D64
5902	{ 1551, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1551 = FABS_D32_MM	5902	{ 1551, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1551 = FABS_D32_MM
5903	{ 1550, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1550 = FABS_D32	5903	{ 1550, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1550 = FABS_D32
5904	{ 1549, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1549 = EXT_MMR6	5904	{ 1549, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1549 = EXT_MMR6
5905	{ 1548, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1548 = EXT_MM	5905	{ 1548, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1548 = EXT_MM
5906	{ 1547, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	5906	{ 1547, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<
5907	{ 1546, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	5907	{ 1546, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<
5908	{ 1545, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5908	{ 1545, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5909	{ 1544, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5909	{ 1544, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5910	{ 1543, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5910	{ 1543, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5911	{ 1542, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5911	{ 1542, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5912	{ 1541, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5912	{ 1541, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5913	{ 1540, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5913	{ 1540, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5914	{ 1539, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5914	{ 1539, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5915	{ 1538, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	5915	{ 1538, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<
5916	{ 1537, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5916	{ 1537, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5917	{ 1536, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5917	{ 1536, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5918	{ 1535, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5918	{ 1535, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5919	{ 1534, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5919	{ 1534, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5920	{ 1533, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5920	{ 1533, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5921	{ 1532, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5921	{ 1532, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5922	{ 1531, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5922	{ 1531, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5923	{ 1530, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	5923	{ 1530, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<
5924	{ 1529, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	5924	{ 1529, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<
5925	{ 1528, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	5925	{ 1528, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<
5926	{ 1527, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	5926	{ 1527, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<
5927	{ 1526, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	5927	{ 1526, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<
5928	{ 1525, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	5928	{ 1525, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<
5929	{ 1524, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	5929	{ 1524, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<
5930	{ 1523, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	5930	{ 1523, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<
5931	{ 1522, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	5931	{ 1522, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<
5932	{ 1521, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1521 = EXT	5932	{ 1521, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1521 = EXT
5933	{ 1520, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5933	{ 1520, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5934	{ 1519, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5934	{ 1519, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5935	{ 1518, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5935	{ 1518, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5936	{ 1517, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5936	{ 1517, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5937	{ 1516, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5937	{ 1516, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5938	{ 1515, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5938	{ 1515, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5939	{ 1514, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5939	{ 1514, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5940	{ 1513, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5940	{ 1513, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5941	{ 1512, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5941	{ 1512, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5942	{ 1511, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5942	{ 1511, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5943	{ 1510, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5943	{ 1510, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5944	{ 1509, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5944	{ 1509, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5945	{ 1508, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5945	{ 1508, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5946	{ 1507, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5946	{ 1507, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5947	{ 1506, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	5947	{ 1506, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
5948	{ 1505, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1505 = DivuRxRy16	5948	{ 1505, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1505 = DivuRxRy16
5949	{ 1504, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1504 = DivRxRy16	5949	{ 1504, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1504 = DivRxRy16
5950	{ 1503, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5950	{ 1503, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5951	{ 1502, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5951	{ 1502, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5952	{ 1501, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	5952	{ 1501, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
5953	{ 1500, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	5953	{ 1500, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<
5954	{ 1499, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	5954	{ 1499, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
5955	{ 1498, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	5955	{ 1498, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
5956	{ 1497, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1497 = DSRLV	5956	{ 1497, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1497 = DSRLV
5957	{ 1496, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	5957	{ 1496, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
5958	{ 1495, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1495 = DSRL	5958	{ 1495, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1495 = DSRL
5959	{ 1494, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1494 = DSRAV	5959	{ 1494, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1494 = DSRAV
5960	{ 1493, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	5960	{ 1493, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
5961	{ 1492, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1492 = DSRA	5961	{ 1492, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1492 = DSRA
5962	{ 1491, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1491 = DSLLV	5962	{ 1491, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1491 = DSLLV
5963	{ 1490, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	5963	{ 1490, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<
5964	{ 1489, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	5964	{ 1489, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
5965	{ 1488, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1488 = DSLL	5965	{ 1488, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1488 = DSLL
5966	{ 1487, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1487 = DSHD	5966	{ 1487, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1487 = DSHD
5967	{ 1486, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	5967	{ 1486, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<
5968	{ 1485, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1485 = DSBH	5968	{ 1485, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1485 = DSBH
5969	{ 1484, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1484 = DROTRV	5969	{ 1484, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1484 = DROTRV
5970	{ 1483, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	5970	{ 1483, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
5971	{ 1482, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1482 = DROTR	5971	{ 1482, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1482 = DROTR
5972	{ 1481, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1481 = DPS_W_PH_MMR2	5972	{ 1481, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1481 = DPS_W_PH_MMR2
5973	{ 1480, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1480 = DPS_W_PH	5973	{ 1480, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1480 = DPS_W_PH
5974	{ 1479, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1479 = DPSX_W_PH_MMR2	5974	{ 1479, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1479 = DPSX_W_PH_MMR2
5975	{ 1478, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1478 = DPSX_W_PH	5975	{ 1478, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1478 = DPSX_W_PH
5976	{ 1477, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1477 = DPSU_H_QBR_MM	5976	{ 1477, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1477 = DPSU_H_QBR_MM
5977	{ 1476, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1476 = DPSU_H_QBR	5977	{ 1476, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1476 = DPSU_H_QBR
5978	{ 1475, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1475 = DPSU_H_QBL_MM	5978	{ 1475, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1475 = DPSU_H_QBL_MM
5979	{ 1474, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1474 = DPSU_H_QBL	5979	{ 1474, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1474 = DPSU_H_QBL
5980	{ 1473, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1473 = DPSUB_U_W	5980	{ 1473, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1473 = DPSUB_U_W
5981	{ 1472, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1472 = DPSUB_U_H	5981	{ 1472, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1472 = DPSUB_U_H
5982	{ 1471, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1471 = DPSUB_U_D	5982	{ 1471, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1471 = DPSUB_U_D
5983	{ 1470, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1470 = DPSUB_S_W	5983	{ 1470, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1470 = DPSUB_S_W
5984	{ 1469, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1469 = DPSUB_S_H	5984	{ 1469, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1469 = DPSUB_S_H
5985	{ 1468, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1468 = DPSUB_S_D	5985	{ 1468, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1468 = DPSUB_S_D
5986	{ 1467, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5986	{ 1467, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5987	{ 1466, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5987	{ 1466, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5988	{ 1465, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5988	{ 1465, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5989	{ 1464, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5989	{ 1464, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5990	{ 1463, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5990	{ 1463, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5991	{ 1462, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5991	{ 1462, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5992	{ 1461, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5992	{ 1461, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5993	{ 1460, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	5993	{ 1460, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
5994	{ 1459, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1459 = DPOP	5994	{ 1459, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1459 = DPOP
5995	{ 1458, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1458 = DPA_W_PH_MMR2	5995	{ 1458, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1458 = DPA_W_PH_MMR2
5996	{ 1457, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1457 = DPA_W_PH	5996	{ 1457, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1457 = DPA_W_PH
5997	{ 1456, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1456 = DPAX_W_PH_MMR2	5997	{ 1456, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1456 = DPAX_W_PH_MMR2
5998	{ 1455, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1455 = DPAX_W_PH	5998	{ 1455, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1455 = DPAX_W_PH
5999	{ 1454, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1454 = DPAU_H_QBR_MM	5999	{ 1454, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1454 = DPAU_H_QBR_MM
6000	{ 1453, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1453 = DPAU_H_QBR	6000	{ 1453, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1453 = DPAU_H_QBR
6001	{ 1452, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1452 = DPAU_H_QBL_MM	6001	{ 1452, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1452 = DPAU_H_QBL_MM
6002	{ 1451, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1451 = DPAU_H_QBL	6002	{ 1451, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1451 = DPAU_H_QBL
6003	{ 1450, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6003	{ 1450, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6004	{ 1449, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6004	{ 1449, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6005	{ 1448, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6005	{ 1448, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6006	{ 1447, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6006	{ 1447, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6007	{ 1446, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6007	{ 1446, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6008	{ 1445, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6008	{ 1445, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6009	{ 1444, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6009	{ 1444, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6010	{ 1443, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	6010	{ 1443, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<
6011	{ 1442, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	6011	{ 1442, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<
6012	{ 1441, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	6012	{ 1441, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<
6013	{ 1440, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	6013	{ 1440, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<
6014	{ 1439, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	6014	{ 1439, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<
6015	{ 1438, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	6015	{ 1438, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<
6016	{ 1437, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	6016	{ 1437, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<
6017	{ 1436, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	6017	{ 1436, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<
6018	{ 1435, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	6018	{ 1435, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<
6019	{ 1434, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	6019	{ 1434, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<
6020	{ 1433, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	6020	{ 1433, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<
6021	{ 1432, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	6021	{ 1432, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<
6022	{ 1431, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	6022	{ 1431, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<
6023	{ 1430, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1430 = DMUL_R6	6023	{ 1430, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1430 = DMUL_R6
6024	{ 1429, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6024	{ 1429, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6025	{ 1428, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	6025	{ 1428, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<
6026	{ 1427, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	6026	{ 1427, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<
6027	{ 1426, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 219, 0\|(1ULL<	6027	{ 1426, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 219, 0\|(1ULL<
6028	{ 1425, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1425 = DMUHU	6028	{ 1425, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1425 = DMUHU
6029	{ 1424, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1424 = DMUH	6029	{ 1424, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1424 = DMUH
6030	{ 1423, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	6030	{ 1423, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<
6031	{ 1422, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	6031	{ 1422, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
6032	{ 1421, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 711, 0\|(1ULL<	6032	{ 1421, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 711, 0\|(1ULL<
6033	{ 1420, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	6033	{ 1420, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<
6034	{ 1419, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	6034	{ 1419, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<
6035	{ 1418, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6035	{ 1418, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6036	{ 1417, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6036	{ 1417, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6037	{ 1416, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6037	{ 1416, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6038	{ 1415, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	6038	{ 1415, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<
6039	{ 1414, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	6039	{ 1414, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
6040	{ 1413, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 705, 0\|(1ULL<	6040	{ 1413, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 705, 0\|(1ULL<
6041	{ 1412, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 703, 0\|(1ULL<	6041	{ 1412, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 703, 0\|(1ULL<
6042	{ 1411, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	6042	{ 1411, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<
6043	{ 1410, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	6043	{ 1410, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<
6044	{ 1409, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0, 0x6ULL }, // Inst #1409 = DLSA	6044	{ 1409, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0, 0x6ULL }, // Inst #1409 = DLSA
6045	{ 1408, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6045	{ 1408, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6046	{ 1407, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6046	{ 1407, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6047	{ 1406, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1406 = DIV_U_W	6047	{ 1406, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1406 = DIV_U_W
6048	{ 1405, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1405 = DIV_U_H	6048	{ 1405, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1405 = DIV_U_H
6049	{ 1404, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1404 = DIV_U_D	6049	{ 1404, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1404 = DIV_U_D
6050	{ 1403, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1403 = DIV_U_B	6050	{ 1403, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1403 = DIV_U_B
6051	{ 1402, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1402 = DIV_S_W	6051	{ 1402, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1402 = DIV_S_W
6052	{ 1401, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1401 = DIV_S_H	6052	{ 1401, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1401 = DIV_S_H
6053	{ 1400, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1400 = DIV_S_D	6053	{ 1400, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1400 = DIV_S_D
6054	{ 1399, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1399 = DIV_S_B	6054	{ 1399, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1399 = DIV_S_B
6055	{ 1398, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6055	{ 1398, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6056	{ 1397, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6056	{ 1397, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6057	{ 1396, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6057	{ 1396, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6058	{ 1395, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6058	{ 1395, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6059	{ 1394, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	6059	{ 1394, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<
6060	{ 1393, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	6060	{ 1393, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<
6061	{ 1392, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	6061	{ 1392, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<
6062	{ 1391, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6062	{ 1391, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6063	{ 1390, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1390 = DEXTU	6063	{ 1390, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1390 = DEXTU
6064	{ 1389, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1389 = DEXTM	6064	{ 1389, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1389 = DEXTM
6065	{ 1388, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1388 = DEXT64_32	6065	{ 1388, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1388 = DEXT64_32
6066	{ 1387, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1387 = DEXT	6066	{ 1387, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1387 = DEXT
6067	{ 1386, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6067	{ 1386, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6068	{ 1385, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6068	{ 1385, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6069	{ 1384, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6069	{ 1384, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6070	{ 1383, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6070	{ 1383, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6071	{ 1382, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6071	{ 1382, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6072	{ 1381, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1381 = DCLZ_R6	6072	{ 1381, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1381 = DCLZ_R6
6073	{ 1380, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1380 = DCLZ	6073	{ 1380, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1380 = DCLZ
6074	{ 1379, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1379 = DCLO_R6	6074	{ 1379, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1379 = DCLO_R6
6075	{ 1378, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1378 = DCLO	6075	{ 1378, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1378 = DCLO
6076	{ 1377, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	6076	{ 1377, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<
6077	{ 1376, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6077	{ 1376, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6078	{ 1375, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	6078	{ 1375, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<
6079	{ 1374, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	6079	{ 1374, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<
6080	{ 1373, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	6080	{ 1373, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<
6081	{ 1372, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6081	{ 1372, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6082	{ 1371, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6082	{ 1371, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6083	{ 1370, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6083	{ 1370, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6084	{ 1369, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6084	{ 1369, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6085	{ 1368, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	6085	{ 1368, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
6086	{ 1367, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	6086	{ 1367, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<
6087	{ 1366, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	6087	{ 1366, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<
6088	{ 1365, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6088	{ 1365, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6089	{ 1364, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6089	{ 1364, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6090	{ 1363, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6090	{ 1363, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6091	{ 1362, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6091	{ 1362, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6092	{ 1361, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6092	{ 1361, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6093	{ 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6093	{ 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6094	{ 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6094	{ 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6095	{ 1358, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6095	{ 1358, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6096	{ 1357, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6096	{ 1357, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6097	{ 1356, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6097	{ 1356, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6098	{ 1355, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6098	{ 1355, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6099	{ 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6099	{ 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6100	{ 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6100	{ 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6101	{ 1352, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6101	{ 1352, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6102	{ 1351, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6102	{ 1351, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6103	{ 1350, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6103	{ 1350, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6104	{ 1349, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6104	{ 1349, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6105	{ 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6105	{ 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6106	{ 1347, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6106	{ 1347, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6107	{ 1346, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6107	{ 1346, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6108	{ 1345, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6108	{ 1345, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6109	{ 1344, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6109	{ 1344, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6110	{ 1343, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6110	{ 1343, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6111	{ 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6111	{ 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6112	{ 1341, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6112	{ 1341, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6113	{ 1340, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6113	{ 1340, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6114	{ 1339, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6114	{ 1339, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6115	{ 1338, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6115	{ 1338, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6116	{ 1337, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6116	{ 1337, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6117	{ 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6117	{ 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6118	{ 1335, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6118	{ 1335, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6119	{ 1334, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6119	{ 1334, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6120	{ 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6120	{ 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6121	{ 1332, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6121	{ 1332, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6122	{ 1331, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6122	{ 1331, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6123	{ 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6123	{ 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6124	{ 1329, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6124	{ 1329, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6125	{ 1328, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6125	{ 1328, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6126	{ 1327, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6126	{ 1327, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6127	{ 1326, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6127	{ 1326, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6128	{ 1325, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6128	{ 1325, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6129	{ 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6129	{ 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6130	{ 1323, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6130	{ 1323, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6131	{ 1322, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6131	{ 1322, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6132	{ 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6132	{ 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6133	{ 1320, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6133	{ 1320, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6134	{ 1319, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6134	{ 1319, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6135	{ 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6135	{ 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6136	{ 1317, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6136	{ 1317, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6137	{ 1316, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6137	{ 1316, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6138	{ 1315, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6138	{ 1315, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6139	{ 1314, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6139	{ 1314, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6140	{ 1313, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6140	{ 1313, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6141	{ 1312, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6141	{ 1312, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6142	{ 1311, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6142	{ 1311, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6143	{ 1310, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6143	{ 1310, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6144	{ 1309, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6144	{ 1309, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6145	{ 1308, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6145	{ 1308, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6146	{ 1307, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6146	{ 1307, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6147	{ 1306, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6147	{ 1306, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6148	{ 1305, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6148	{ 1305, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6149	{ 1304, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6149	{ 1304, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6150	{ 1303, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6150	{ 1303, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6151	{ 1302, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6151	{ 1302, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6152	{ 1301, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6152	{ 1301, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6153	{ 1300, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6153	{ 1300, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6154	{ 1299, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6154	{ 1299, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6155	{ 1298, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6155	{ 1298, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6156	{ 1297, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6156	{ 1297, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6157	{ 1296, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6157	{ 1296, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6158	{ 1295, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6158	{ 1295, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6159	{ 1294, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6159	{ 1294, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6160	{ 1293, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6160	{ 1293, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6161	{ 1292, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6161	{ 1292, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6162	{ 1291, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6162	{ 1291, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6163	{ 1290, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6163	{ 1290, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6164	{ 1289, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6164	{ 1289, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6165	{ 1288, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6165	{ 1288, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6166	{ 1287, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6166	{ 1287, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6167	{ 1286, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6167	{ 1286, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6168	{ 1285, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6168	{ 1285, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6169	{ 1284, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6169	{ 1284, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6170	{ 1283, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6170	{ 1283, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6171	{ 1282, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6171	{ 1282, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6172	{ 1281, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6172	{ 1281, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6173	{ 1280, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6173	{ 1280, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6174	{ 1279, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6174	{ 1279, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6175	{ 1278, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6175	{ 1278, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6176	{ 1277, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6176	{ 1277, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6177	{ 1276, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6177	{ 1276, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6178	{ 1275, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6178	{ 1275, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6179	{ 1274, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	6179	{ 1274, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<
6180	{ 1273, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6180	{ 1273, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6181	{ 1272, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	6181	{ 1272, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<
6182	{ 1271, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6182	{ 1271, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6183	{ 1270, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	6183	{ 1270, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<
6184	{ 1269, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1269 = CVT_W_S_MMR6	6184	{ 1269, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1269 = CVT_W_S_MMR6
6185	{ 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_W_S_MM	6185	{ 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_W_S_MM
6186	{ 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_W_S	6186	{ 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_W_S
6187	{ 1266, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1266 = CVT_W_D64_MM	6187	{ 1266, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1266 = CVT_W_D64_MM
6188	{ 1265, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1265 = CVT_W_D64	6188	{ 1265, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1265 = CVT_W_D64
6189	{ 1264, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_W_D32_MM	6189	{ 1264, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_W_D32_MM
6190	{ 1263, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1263 = CVT_W_D32	6190	{ 1263, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1263 = CVT_W_D32
6191	{ 1262, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1262 = CVT_S_W_MMR6	6191	{ 1262, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1262 = CVT_S_W_MMR6
6192	{ 1261, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1261 = CVT_S_W_MM	6192	{ 1261, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1261 = CVT_S_W_MM
6193	{ 1260, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1260 = CVT_S_W	6193	{ 1260, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1260 = CVT_S_W
6194	{ 1259, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1259 = CVT_S_PU64	6194	{ 1259, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1259 = CVT_S_PU64
6195	{ 1258, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1258 = CVT_S_PL64	6195	{ 1258, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1258 = CVT_S_PL64
6196	{ 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1257 = CVT_S_L_MMR6	6196	{ 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1257 = CVT_S_L_MMR6
6197	{ 1256, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_S_L	6197	{ 1256, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_S_L
6198	{ 1255, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_S_D64_MM	6198	{ 1255, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_S_D64_MM
6199	{ 1254, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_S_D64	6199	{ 1254, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_S_D64
6200	{ 1253, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1253 = CVT_S_D32_MM	6200	{ 1253, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1253 = CVT_S_D32_MM
6201	{ 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_S_D32	6201	{ 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_S_D32
6202	{ 1251, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1251 = CVT_PW_PS64	6202	{ 1251, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1251 = CVT_PW_PS64
6203	{ 1250, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 676, 0\|(1ULL<	6203	{ 1250, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 676, 0\|(1ULL<
6204	{ 1249, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1249 = CVT_PS_PW64	6204	{ 1249, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1249 = CVT_PS_PW64
6205	{ 1248, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1248 = CVT_L_S_MMR6	6205	{ 1248, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1248 = CVT_L_S_MMR6
6206	{ 1247, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1247 = CVT_L_S_MM	6206	{ 1247, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1247 = CVT_L_S_MM
6207	{ 1246, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1246 = CVT_L_S	6207	{ 1246, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1246 = CVT_L_S
6208	{ 1245, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1245 = CVT_L_D_MMR6	6208	{ 1245, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1245 = CVT_L_D_MMR6
6209	{ 1244, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1244 = CVT_L_D64_MM	6209	{ 1244, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1244 = CVT_L_D64_MM
6210	{ 1243, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1243 = CVT_L_D64	6210	{ 1243, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1243 = CVT_L_D64
6211	{ 1242, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1242 = CVT_D_L_MMR6	6211	{ 1242, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1242 = CVT_D_L_MMR6
6212	{ 1241, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1241 = CVT_D64_W_MM	6212	{ 1241, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1241 = CVT_D64_W_MM
6213	{ 1240, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1240 = CVT_D64_W	6213	{ 1240, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1240 = CVT_D64_W
6214	{ 1239, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1239 = CVT_D64_S_MM	6214	{ 1239, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1239 = CVT_D64_S_MM
6215	{ 1238, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1238 = CVT_D64_S	6215	{ 1238, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1238 = CVT_D64_S
6216	{ 1237, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1237 = CVT_D64_L	6216	{ 1237, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1237 = CVT_D64_L
6217	{ 1236, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1236 = CVT_D32_W_MM	6217	{ 1236, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1236 = CVT_D32_W_MM
6218	{ 1235, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1235 = CVT_D32_W	6218	{ 1235, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1235 = CVT_D32_W
6219	{ 1234, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1234 = CVT_D32_S_MM	6219	{ 1234, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1234 = CVT_D32_S_MM
6220	{ 1233, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1233 = CVT_D32_S	6220	{ 1233, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1233 = CVT_D32_S
6221	{ 1232, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 672, 0\|(1ULL<	6221	{ 1232, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 672, 0\|(1ULL<
6222	{ 1231, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	6222	{ 1231, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<
6223	{ 1230, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	6223	{ 1230, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<
6224	{ 1229, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	6224	{ 1229, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<
6225	{ 1228, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6225	{ 1228, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6226	{ 1227, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6226	{ 1227, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6227	{ 1226, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6227	{ 1226, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6228	{ 1225, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6228	{ 1225, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6229	{ 1224, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6229	{ 1224, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6230	{ 1223, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6230	{ 1223, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6231	{ 1222, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6231	{ 1222, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6232	{ 1221, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6232	{ 1221, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6233	{ 1220, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1220 = COPY_U_W	6233	{ 1220, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1220 = COPY_U_W
6234	{ 1219, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1219 = COPY_U_H	6234	{ 1219, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1219 = COPY_U_H
6235	{ 1218, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1218 = COPY_U_B	6235	{ 1218, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1218 = COPY_U_B
6236	{ 1217, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1217 = COPY_S_W	6236	{ 1217, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1217 = COPY_S_W
6237	{ 1216, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1216 = COPY_S_H	6237	{ 1216, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1216 = COPY_S_H
6238	{ 1215, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 659, 0, 0x6ULL }, // Inst #1215 = COPY_S_D	6238	{ 1215, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 659, 0, 0x6ULL }, // Inst #1215 = COPY_S_D
6239	{ 1214, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1214 = COPY_S_B	6239	{ 1214, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1214 = COPY_S_B
6240	{ 1213, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1213 = CMP_UN_S_MMR6	6240	{ 1213, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1213 = CMP_UN_S_MMR6
6241	{ 1212, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1212 = CMP_UN_S	6241	{ 1212, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1212 = CMP_UN_S
6242	{ 1211, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1211 = CMP_UN_D_MMR6	6242	{ 1211, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1211 = CMP_UN_D_MMR6
6243	{ 1210, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1210 = CMP_UN_D	6243	{ 1210, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1210 = CMP_UN_D
6244	{ 1209, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1209 = CMP_ULT_S_MMR6	6244	{ 1209, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1209 = CMP_ULT_S_MMR6
6245	{ 1208, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1208 = CMP_ULT_S	6245	{ 1208, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1208 = CMP_ULT_S
6246	{ 1207, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1207 = CMP_ULT_D_MMR6	6246	{ 1207, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1207 = CMP_ULT_D_MMR6
6247	{ 1206, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1206 = CMP_ULT_D	6247	{ 1206, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1206 = CMP_ULT_D
6248	{ 1205, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1205 = CMP_ULE_S_MMR6	6248	{ 1205, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1205 = CMP_ULE_S_MMR6
6249	{ 1204, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1204 = CMP_ULE_S	6249	{ 1204, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1204 = CMP_ULE_S
6250	{ 1203, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1203 = CMP_ULE_D_MMR6	6250	{ 1203, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1203 = CMP_ULE_D_MMR6
6251	{ 1202, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1202 = CMP_ULE_D	6251	{ 1202, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1202 = CMP_ULE_D
6252	{ 1201, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1201 = CMP_UEQ_S_MMR6	6252	{ 1201, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1201 = CMP_UEQ_S_MMR6
6253	{ 1200, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1200 = CMP_UEQ_S	6253	{ 1200, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1200 = CMP_UEQ_S
6254	{ 1199, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1199 = CMP_UEQ_D_MMR6	6254	{ 1199, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1199 = CMP_UEQ_D_MMR6
6255	{ 1198, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1198 = CMP_UEQ_D	6255	{ 1198, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1198 = CMP_UEQ_D
6256	{ 1197, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6256	{ 1197, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6257	{ 1196, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6257	{ 1196, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6258	{ 1195, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6258	{ 1195, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6259	{ 1194, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6259	{ 1194, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6260	{ 1193, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6260	{ 1193, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6261	{ 1192, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6261	{ 1192, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6262	{ 1191, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6262	{ 1191, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6263	{ 1190, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6263	{ 1190, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6264	{ 1189, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6264	{ 1189, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6265	{ 1188, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6265	{ 1188, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6266	{ 1187, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6266	{ 1187, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6267	{ 1186, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6267	{ 1186, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6268	{ 1185, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6268	{ 1185, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6269	{ 1184, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6269	{ 1184, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6270	{ 1183, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6270	{ 1183, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6271	{ 1182, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6271	{ 1182, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6272	{ 1181, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6272	{ 1181, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6273	{ 1180, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6273	{ 1180, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6274	{ 1179, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6274	{ 1179, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6275	{ 1178, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6275	{ 1178, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6276	{ 1177, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6276	{ 1177, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6277	{ 1176, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6277	{ 1176, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6278	{ 1175, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6278	{ 1175, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6279	{ 1174, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6279	{ 1174, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6280	{ 1173, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6280	{ 1173, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6281	{ 1172, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6281	{ 1172, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6282	{ 1171, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6282	{ 1171, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6283	{ 1170, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6283	{ 1170, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6284	{ 1169, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6284	{ 1169, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6285	{ 1168, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6285	{ 1168, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6286	{ 1167, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6286	{ 1167, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6287	{ 1166, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6287	{ 1166, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6288	{ 1165, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1165 = CMP_LT_S_MMR6	6288	{ 1165, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1165 = CMP_LT_S_MMR6
6289	{ 1164, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1164 = CMP_LT_S	6289	{ 1164, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1164 = CMP_LT_S
6290	{ 1163, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6290	{ 1163, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6291	{ 1162, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6291	{ 1162, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6292	{ 1161, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1161 = CMP_LT_D_MMR6	6292	{ 1161, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1161 = CMP_LT_D_MMR6
6293	{ 1160, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1160 = CMP_LT_D	6293	{ 1160, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1160 = CMP_LT_D
6294	{ 1159, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1159 = CMP_LE_S_MMR6	6294	{ 1159, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1159 = CMP_LE_S_MMR6
6295	{ 1158, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1158 = CMP_LE_S	6295	{ 1158, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1158 = CMP_LE_S
6296	{ 1157, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6296	{ 1157, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6297	{ 1156, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6297	{ 1156, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6298	{ 1155, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1155 = CMP_LE_D_MMR6	6298	{ 1155, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1155 = CMP_LE_D_MMR6
6299	{ 1154, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1154 = CMP_LE_D	6299	{ 1154, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1154 = CMP_LE_D
6300	{ 1153, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6300	{ 1153, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6301	{ 1152, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6301	{ 1152, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6302	{ 1151, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1151 = CMP_EQ_S_MMR6	6302	{ 1151, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1151 = CMP_EQ_S_MMR6
6303	{ 1150, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1150 = CMP_EQ_S	6303	{ 1150, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1150 = CMP_EQ_S
6304	{ 1149, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6304	{ 1149, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6305	{ 1148, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6305	{ 1148, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6306	{ 1147, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1147 = CMP_EQ_D_MMR6	6306	{ 1147, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1147 = CMP_EQ_D_MMR6
6307	{ 1146, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1146 = CMP_EQ_D	6307	{ 1146, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1146 = CMP_EQ_D
6308	{ 1145, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	6308	{ 1145, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<
6309	{ 1144, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	6309	{ 1144, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<
6310	{ 1143, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6310	{ 1143, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6311	{ 1142, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6311	{ 1142, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6312	{ 1141, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6312	{ 1141, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6313	{ 1140, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6313	{ 1140, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6314	{ 1139, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6314	{ 1139, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6315	{ 1138, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	6315	{ 1138, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<
6316	{ 1137, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6316	{ 1137, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6317	{ 1136, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6317	{ 1136, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6318	{ 1135, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6318	{ 1135, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6319	{ 1134, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6319	{ 1134, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6320	{ 1133, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6320	{ 1133, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6321	{ 1132, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	6321	{ 1132, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<
6322	{ 1131, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6322	{ 1131, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6323	{ 1130, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6323	{ 1130, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6324	{ 1129, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6324	{ 1129, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6325	{ 1128, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6325	{ 1128, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6326	{ 1127, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6326	{ 1127, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6327	{ 1126, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	6327	{ 1126, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<
6328	{ 1125, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1125 = CLZ_R6	6328	{ 1125, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1125 = CLZ_R6
6329	{ 1124, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6329	{ 1124, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6330	{ 1123, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1123 = CLZ_MM	6330	{ 1123, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1123 = CLZ_MM
6331	{ 1122, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1122 = CLZ	6331	{ 1122, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1122 = CLZ
6332	{ 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1121 = CLT_U_W	6332	{ 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1121 = CLT_U_W
6333	{ 1120, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1120 = CLT_U_H	6333	{ 1120, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1120 = CLT_U_H
6334	{ 1119, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1119 = CLT_U_D	6334	{ 1119, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1119 = CLT_U_D
6335	{ 1118, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1118 = CLT_U_B	6335	{ 1118, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1118 = CLT_U_B
6336	{ 1117, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1117 = CLT_S_W	6336	{ 1117, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1117 = CLT_S_W
6337	{ 1116, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1116 = CLT_S_H	6337	{ 1116, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1116 = CLT_S_H
6338	{ 1115, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1115 = CLT_S_D	6338	{ 1115, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1115 = CLT_S_D
6339	{ 1114, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1114 = CLT_S_B	6339	{ 1114, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1114 = CLT_S_B
6340	{ 1113, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1113 = CLTI_U_W	6340	{ 1113, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1113 = CLTI_U_W
6341	{ 1112, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1112 = CLTI_U_H	6341	{ 1112, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1112 = CLTI_U_H
6342	{ 1111, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1111 = CLTI_U_D	6342	{ 1111, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1111 = CLTI_U_D
6343	{ 1110, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1110 = CLTI_U_B	6343	{ 1110, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1110 = CLTI_U_B
6344	{ 1109, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1109 = CLTI_S_W	6344	{ 1109, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1109 = CLTI_S_W
6345	{ 1108, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1108 = CLTI_S_H	6345	{ 1108, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1108 = CLTI_S_H
6346	{ 1107, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1107 = CLTI_S_D	6346	{ 1107, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1107 = CLTI_S_D
6347	{ 1106, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1106 = CLTI_S_B	6347	{ 1106, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1106 = CLTI_S_B
6348	{ 1105, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1105 = CLO_R6	6348	{ 1105, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1105 = CLO_R6
6349	{ 1104, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6349	{ 1104, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6350	{ 1103, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1103 = CLO_MM	6350	{ 1103, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1103 = CLO_MM
6351	{ 1102, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1102 = CLO	6351	{ 1102, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1102 = CLO
6352	{ 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1101 = CLE_U_W	6352	{ 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1101 = CLE_U_W
6353	{ 1100, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1100 = CLE_U_H	6353	{ 1100, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1100 = CLE_U_H
6354	{ 1099, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1099 = CLE_U_D	6354	{ 1099, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1099 = CLE_U_D
6355	{ 1098, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1098 = CLE_U_B	6355	{ 1098, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1098 = CLE_U_B
6356	{ 1097, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1097 = CLE_S_W	6356	{ 1097, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1097 = CLE_S_W
6357	{ 1096, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1096 = CLE_S_H	6357	{ 1096, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1096 = CLE_S_H
6358	{ 1095, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1095 = CLE_S_D	6358	{ 1095, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1095 = CLE_S_D
6359	{ 1094, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1094 = CLE_S_B	6359	{ 1094, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1094 = CLE_S_B
6360	{ 1093, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1093 = CLEI_U_W	6360	{ 1093, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1093 = CLEI_U_W
6361	{ 1092, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1092 = CLEI_U_H	6361	{ 1092, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1092 = CLEI_U_H
6362	{ 1091, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1091 = CLEI_U_D	6362	{ 1091, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1091 = CLEI_U_D
6363	{ 1090, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1090 = CLEI_U_B	6363	{ 1090, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1090 = CLEI_U_B
6364	{ 1089, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1089 = CLEI_S_W	6364	{ 1089, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1089 = CLEI_S_W
6365	{ 1088, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1088 = CLEI_S_H	6365	{ 1088, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1088 = CLEI_S_H
6366	{ 1087, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1087 = CLEI_S_D	6366	{ 1087, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1087 = CLEI_S_D
6367	{ 1086, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1086 = CLEI_S_B	6367	{ 1086, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1086 = CLEI_S_B
6368	{ 1085, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	6368	{ 1085, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
6369	{ 1084, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	6369	{ 1084, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<
6370	{ 1083, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	6370	{ 1083, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<
6371	{ 1082, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	6371	{ 1082, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<
6372	{ 1081, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1081 = CINS_i32	6372	{ 1081, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1081 = CINS_i32
6373	{ 1080, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1080 = CINS64_32	6373	{ 1080, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1080 = CINS64_32
6374	{ 1079, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1079 = CINS32	6374	{ 1079, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1079 = CINS32
6375	{ 1078, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1078 = CINS	6375	{ 1078, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1078 = CINS
6376	{ 1077, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 633, 0\|(1ULL<	6376	{ 1077, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 633, 0\|(1ULL<
6377	{ 1076, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	6377	{ 1076, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<
6378	{ 1075, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	6378	{ 1075, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<
6379	{ 1074, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	6379	{ 1074, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<
6380	{ 1073, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6380	{ 1073, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6381	{ 1072, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6381	{ 1072, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6382	{ 1071, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6382	{ 1071, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6383	{ 1070, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6383	{ 1070, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6384	{ 1069, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1069 = CEQI_W	6384	{ 1069, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1069 = CEQI_W
6385	{ 1068, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1068 = CEQI_H	6385	{ 1068, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1068 = CEQI_H
6386	{ 1067, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1067 = CEQI_D	6386	{ 1067, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1067 = CEQI_D
6387	{ 1066, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1066 = CEQI_B	6387	{ 1066, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1066 = CEQI_B
6388	{ 1065, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1065 = CEIL_W_S_MMR6	6388	{ 1065, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1065 = CEIL_W_S_MMR6
6389	{ 1064, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1064 = CEIL_W_S_MM	6389	{ 1064, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1064 = CEIL_W_S_MM
6390	{ 1063, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1063 = CEIL_W_S	6390	{ 1063, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1063 = CEIL_W_S
6391	{ 1062, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1062 = CEIL_W_MM	6391	{ 1062, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1062 = CEIL_W_MM
6392	{ 1061, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1061 = CEIL_W_D_MMR6	6392	{ 1061, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1061 = CEIL_W_D_MMR6
6393	{ 1060, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1060 = CEIL_W_D64	6393	{ 1060, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1060 = CEIL_W_D64
6394	{ 1059, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1059 = CEIL_W_D32	6394	{ 1059, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1059 = CEIL_W_D32
6395	{ 1058, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1058 = CEIL_L_S_MMR6	6395	{ 1058, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1058 = CEIL_L_S_MMR6
6396	{ 1057, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1057 = CEIL_L_S	6396	{ 1057, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1057 = CEIL_L_S
6397	{ 1056, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1056 = CEIL_L_D_MMR6	6397	{ 1056, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1056 = CEIL_L_D_MMR6
6398	{ 1055, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1055 = CEIL_L_D64	6398	{ 1055, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1055 = CEIL_L_D64
6399	{ 1054, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6399	{ 1054, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6400	{ 1053, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6400	{ 1053, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6401	{ 1052, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6401	{ 1052, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6402	{ 1051, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6402	{ 1051, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6403	{ 1050, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6403	{ 1050, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6404	{ 1049, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	6404	{ 1049, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<
6405	{ 1048, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	6405	{ 1048, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<
6406	{ 1047, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	6406	{ 1047, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<
6407	{ 1046, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	6407	{ 1046, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<
6408	{ 1045, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	6408	{ 1045, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<
6409	{ 1044, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6409	{ 1044, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6410	{ 1043, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	6410	{ 1043, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<
6411	{ 1042, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	6411	{ 1042, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<
6412	{ 1041, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6412	{ 1041, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6413	{ 1040, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6413	{ 1040, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6414	{ 1039, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	6414	{ 1039, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<
6415	{ 1038, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	6415	{ 1038, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<
6416	{ 1037, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	6416	{ 1037, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<
6417	{ 1036, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	6417	{ 1036, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<
6418	{ 1035, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	6418	{ 1035, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<
6419	{ 1034, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	6419	{ 1034, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<
6420	{ 1033, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	6420	{ 1033, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<
6421	{ 1032, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1032 = BSET_W	6421	{ 1032, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1032 = BSET_W
6422	{ 1031, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1031 = BSET_H	6422	{ 1031, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1031 = BSET_H
6423	{ 1030, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1030 = BSET_D	6423	{ 1030, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1030 = BSET_D
6424	{ 1029, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1029 = BSET_B	6424	{ 1029, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1029 = BSET_B
6425	{ 1028, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1028 = BSETI_W	6425	{ 1028, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1028 = BSETI_W
6426	{ 1027, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1027 = BSETI_H	6426	{ 1027, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1027 = BSETI_H
6427	{ 1026, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1026 = BSETI_D	6427	{ 1026, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1026 = BSETI_D
6428	{ 1025, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1025 = BSETI_B	6428	{ 1025, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1025 = BSETI_B
6429	{ 1024, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1024 = BSEL_V	6429	{ 1024, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1024 = BSEL_V
6430	{ 1023, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #1023 = BSELI_B	6430	{ 1023, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #1023 = BSELI_B
6431	{ 1022, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	6431	{ 1022, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<
6432	{ 1021, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	6432	{ 1021, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<
6433	{ 1020, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	6433	{ 1020, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
6434	{ 1019, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	6434	{ 1019, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
6435	{ 1018, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	6435	{ 1018, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<
6436	{ 1017, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6436	{ 1017, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6437	{ 1016, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6437	{ 1016, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6438	{ 1015, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6438	{ 1015, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6439	{ 1014, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6439	{ 1014, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6440	{ 1013, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6440	{ 1013, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6441	{ 1012, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	6441	{ 1012, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<
6442	{ 1011, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	6442	{ 1011, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<
6443	{ 1010, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	6443	{ 1010, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<
6444	{ 1009, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	6444	{ 1009, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<
6445	{ 1008, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	6445	{ 1008, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<
6446	{ 1007, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6446	{ 1007, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6447	{ 1006, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6447	{ 1006, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6448	{ 1005, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6448	{ 1005, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6449	{ 1004, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6449	{ 1004, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6450	{ 1003, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6450	{ 1003, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6451	{ 1002, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6451	{ 1002, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6452	{ 1001, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	6452	{ 1001, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<
6453	{ 1000, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6453	{ 1000, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6454	{ 999, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6454	{ 999, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6455	{ 998, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6455	{ 998, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6456	{ 997, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	6456	{ 997, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<
6457	{ 996, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6457	{ 996, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6458	{ 995, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #995 = BNEG_W	6458	{ 995, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #995 = BNEG_W
6459	{ 994, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #994 = BNEG_H	6459	{ 994, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #994 = BNEG_H
6460	{ 993, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #993 = BNEG_D	6460	{ 993, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #993 = BNEG_D
6461	{ 992, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #992 = BNEG_B	6461	{ 992, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #992 = BNEG_B
6462	{ 991, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #991 = BNEGI_W	6462	{ 991, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #991 = BNEGI_W
6463	{ 990, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #990 = BNEGI_H	6463	{ 990, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #990 = BNEGI_H
6464	{ 989, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #989 = BNEGI_D	6464	{ 989, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #989 = BNEGI_D
6465	{ 988, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #988 = BNEGI_B	6465	{ 988, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #988 = BNEGI_B
6466	{ 987, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6466	{ 987, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6467	{ 986, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6467	{ 986, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6468	{ 985, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6468	{ 985, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6469	{ 984, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6469	{ 984, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6470	{ 983, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6470	{ 983, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6471	{ 982, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #982 = BMZ_V	6471	{ 982, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #982 = BMZ_V
6472	{ 981, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #981 = BMZI_B	6472	{ 981, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #981 = BMZI_B
6473	{ 980, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #980 = BMNZ_V	6473	{ 980, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #980 = BMNZ_V
6474	{ 979, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #979 = BMNZI_B	6474	{ 979, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #979 = BMNZI_B
6475	{ 978, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6475	{ 978, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6476	{ 977, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6476	{ 977, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6477	{ 976, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6477	{ 976, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6478	{ 975, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6478	{ 975, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6479	{ 974, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6479	{ 974, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6480	{ 973, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6480	{ 973, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6481	{ 972, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6481	{ 972, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6482	{ 971, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6482	{ 971, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6483	{ 970, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6483	{ 970, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6484	{ 969, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6484	{ 969, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6485	{ 968, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6485	{ 968, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6486	{ 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6486	{ 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6487	{ 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6487	{ 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6488	{ 965, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6488	{ 965, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6489	{ 964, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6489	{ 964, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6490	{ 963, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6490	{ 963, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6491	{ 962, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6491	{ 962, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6492	{ 961, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6492	{ 961, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6493	{ 960, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6493	{ 960, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6494	{ 959, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6494	{ 959, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6495	{ 958, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6495	{ 958, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6496	{ 957, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6496	{ 957, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6497	{ 956, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6497	{ 956, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6498	{ 955, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6498	{ 955, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6499	{ 954, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6499	{ 954, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6500	{ 953, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6500	{ 953, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6501	{ 952, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6501	{ 952, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6502	{ 951, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6502	{ 951, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6503	{ 950, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6503	{ 950, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6504	{ 949, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6504	{ 949, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6505	{ 948, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #948 = BITREV_MM	6505	{ 948, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #948 = BITREV_MM
6506	{ 947, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #947 = BITREV	6506	{ 947, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #947 = BITREV
6507	{ 946, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #946 = BINSR_W	6507	{ 946, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #946 = BINSR_W
6508	{ 945, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #945 = BINSR_H	6508	{ 945, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #945 = BINSR_H
6509	{ 944, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #944 = BINSR_D	6509	{ 944, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #944 = BINSR_D
6510	{ 943, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #943 = BINSR_B	6510	{ 943, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #943 = BINSR_B
6511	{ 942, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #942 = BINSRI_W	6511	{ 942, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #942 = BINSRI_W
6512	{ 941, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #941 = BINSRI_H	6512	{ 941, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #941 = BINSRI_H
6513	{ 940, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #940 = BINSRI_D	6513	{ 940, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #940 = BINSRI_D
6514	{ 939, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #939 = BINSRI_B	6514	{ 939, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #939 = BINSRI_B
6515	{ 938, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #938 = BINSL_W	6515	{ 938, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #938 = BINSL_W
6516	{ 937, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #937 = BINSL_H	6516	{ 937, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #937 = BINSL_H
6517	{ 936, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #936 = BINSL_D	6517	{ 936, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #936 = BINSL_D
6518	{ 935, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #935 = BINSL_B	6518	{ 935, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #935 = BINSL_B
6519	{ 934, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #934 = BINSLI_W	6519	{ 934, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #934 = BINSLI_W
6520	{ 933, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #933 = BINSLI_H	6520	{ 933, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #933 = BINSLI_H
6521	{ 932, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #932 = BINSLI_D	6521	{ 932, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #932 = BINSLI_D
6522	{ 931, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #931 = BINSLI_B	6522	{ 931, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #931 = BINSLI_B
6523	{ 930, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6523	{ 930, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6524	{ 929, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6524	{ 929, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6525	{ 928, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6525	{ 928, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6526	{ 927, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6526	{ 927, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6527	{ 926, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6527	{ 926, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6528	{ 925, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6528	{ 925, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6529	{ 924, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6529	{ 924, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6530	{ 923, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6530	{ 923, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6531	{ 922, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6531	{ 922, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6532	{ 921, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6532	{ 921, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6533	{ 920, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6533	{ 920, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6534	{ 919, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6534	{ 919, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6535	{ 918, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6535	{ 918, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6536	{ 917, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6536	{ 917, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6537	{ 916, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6537	{ 916, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6538	{ 915, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6538	{ 915, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6539	{ 914, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6539	{ 914, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6540	{ 913, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6540	{ 913, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6541	{ 912, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6541	{ 912, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6542	{ 911, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6542	{ 911, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6543	{ 910, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6543	{ 910, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6544	{ 909, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6544	{ 909, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6545	{ 908, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6545	{ 908, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6546	{ 907, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6546	{ 907, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6547	{ 906, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6547	{ 906, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6548	{ 905, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6548	{ 905, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6549	{ 904, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6549	{ 904, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6550	{ 903, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6550	{ 903, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6551	{ 902, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6551	{ 902, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6552	{ 901, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6552	{ 901, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6553	{ 900, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6553	{ 900, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6554	{ 899, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	6554	{ 899, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<
6555	{ 898, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	6555	{ 898, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<
6556	{ 897, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	6556	{ 897, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<
6557	{ 896, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6557	{ 896, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6558	{ 895, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	6558	{ 895, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<
6559	{ 894, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	6559	{ 894, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<
6560	{ 893, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6560	{ 893, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6561	{ 892, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6561	{ 892, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6562	{ 891, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6562	{ 891, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6563	{ 890, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6563	{ 890, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6564	{ 889, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	6564	{ 889, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<
6565	{ 888, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	6565	{ 888, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<
6566	{ 887, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6566	{ 887, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6567	{ 886, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #886 = BCLR_W	6567	{ 886, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #886 = BCLR_W
6568	{ 885, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #885 = BCLR_H	6568	{ 885, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #885 = BCLR_H
6569	{ 884, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #884 = BCLR_D	6569	{ 884, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #884 = BCLR_D
6570	{ 883, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #883 = BCLR_B	6570	{ 883, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #883 = BCLR_B
6571	{ 882, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #882 = BCLRI_W	6571	{ 882, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #882 = BCLRI_W
6572	{ 881, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #881 = BCLRI_H	6572	{ 881, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #881 = BCLRI_H
6573	{ 880, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #880 = BCLRI_D	6573	{ 880, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #880 = BCLRI_D
6574	{ 879, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #879 = BCLRI_B	6574	{ 879, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #879 = BCLRI_B
6575	{ 878, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	6575	{ 878, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<
6576	{ 877, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	6576	{ 877, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<
6577	{ 876, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	6577	{ 876, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<
6578	{ 875, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	6578	{ 875, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<
6579	{ 874, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6579	{ 874, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6580	{ 873, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6580	{ 873, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6581	{ 872, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6581	{ 872, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6582	{ 871, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	6582	{ 871, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<
6583	{ 870, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	6583	{ 870, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<
6584	{ 869, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6584	{ 869, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6585	{ 868, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6585	{ 868, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6586	{ 867, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	6586	{ 867, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<
6587	{ 866, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	6587	{ 866, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<
6588	{ 865, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	6588	{ 865, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<
6589	{ 864, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	6589	{ 864, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<
6590	{ 863, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	6590	{ 863, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
6591	{ 862, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	6591	{ 862, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<
6592	{ 861, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	6592	{ 861, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<
6593	{ 860, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	6593	{ 860, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<
6594	{ 859, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	6594	{ 859, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<
6595	{ 858, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #858 = BALIGN_MMR2	6595	{ 858, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #858 = BALIGN_MMR2
6596	{ 857, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #857 = BALIGN	6596	{ 857, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #857 = BALIGN
6597	{ 856, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	6597	{ 856, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<
6598	{ 855, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	6598	{ 855, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<
6599	{ 854, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	6599	{ 854, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<
6600	{ 853, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6600	{ 853, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6601	{ 852, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	6601	{ 852, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<
6602	{ 851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	6602	{ 851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<
6603	{ 850, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	6603	{ 850, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<
6604	{ 849, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	6604	{ 849, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<
6605	{ 848, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	6605	{ 848, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<
6606	{ 847, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 569, 0, 0x0ULL }, // Inst #847 = AddiuRxRyOffMemX16	6606	{ 847, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 569, 0, 0x0ULL }, // Inst #847 = AddiuRxRyOffMemX16
6607	{ 846, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	6607	{ 846, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<
6608	{ 845, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	6608	{ 845, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<
6609	{ 844, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	6609	{ 844, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<
6610	{ 843, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	6610	{ 843, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<
6611	{ 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6611	{ 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6612	{ 841, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6612	{ 841, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6613	{ 840, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6613	{ 840, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6614	{ 839, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6614	{ 839, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6615	{ 838, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6615	{ 838, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6616	{ 837, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6616	{ 837, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6617	{ 836, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6617	{ 836, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6618	{ 835, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6618	{ 835, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6619	{ 834, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6619	{ 834, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6620	{ 833, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6620	{ 833, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6621	{ 832, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6621	{ 832, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6622	{ 831, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6622	{ 831, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6623	{ 830, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6623	{ 830, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6624	{ 829, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6624	{ 829, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6625	{ 828, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6625	{ 828, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6626	{ 827, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6626	{ 827, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6627	{ 826, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6627	{ 826, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6628	{ 825, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6628	{ 825, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6629	{ 824, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6629	{ 824, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6630	{ 823, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6630	{ 823, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6631	{ 822, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #822 = ASUB_U_W	6631	{ 822, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #822 = ASUB_U_W
6632	{ 821, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #821 = ASUB_U_H	6632	{ 821, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #821 = ASUB_U_H
6633	{ 820, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #820 = ASUB_U_D	6633	{ 820, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #820 = ASUB_U_D
6634	{ 819, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #819 = ASUB_U_B	6634	{ 819, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #819 = ASUB_U_B
6635	{ 818, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #818 = ASUB_S_W	6635	{ 818, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #818 = ASUB_S_W
6636	{ 817, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #817 = ASUB_S_H	6636	{ 817, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #817 = ASUB_S_H
6637	{ 816, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #816 = ASUB_S_D	6637	{ 816, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #816 = ASUB_S_D
6638	{ 815, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #815 = ASUB_S_B	6638	{ 815, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #815 = ASUB_S_B
6639	{ 814, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #814 = APPEND_MMR2	6639	{ 814, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #814 = APPEND_MMR2
6640	{ 813, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = APPEND	6640	{ 813, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = APPEND
6641	{ 812, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6641	{ 812, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6642	{ 811, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6642	{ 811, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6643	{ 810, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6643	{ 810, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6644	{ 809, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #809 = AND_V	6644	{ 809, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #809 = AND_V
6645	{ 808, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6645	{ 808, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6646	{ 807, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6646	{ 807, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6647	{ 806, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6647	{ 806, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6648	{ 805, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #805 = ANDI_B	6648	{ 805, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #805 = ANDI_B
6649	{ 804, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #804 = ANDI16_MMR6	6649	{ 804, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #804 = ANDI16_MMR6
6650	{ 803, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #803 = ANDI16_MM	6650	{ 803, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #803 = ANDI16_MM
6651	{ 802, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	6651	{ 802, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
6652	{ 801, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	6652	{ 801, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
6653	{ 800, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	6653	{ 800, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<
6654	{ 799, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6654	{ 799, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6655	{ 798, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6655	{ 798, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6656	{ 797, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6656	{ 797, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6657	{ 796, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	6657	{ 796, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<
6658	{ 795, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	6658	{ 795, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<
6659	{ 794, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6659	{ 794, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6660	{ 793, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6660	{ 793, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6661	{ 792, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6661	{ 792, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6662	{ 791, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6662	{ 791, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6663	{ 790, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6663	{ 790, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6664	{ 789, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6664	{ 789, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6665	{ 788, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6665	{ 788, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6666	{ 787, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6666	{ 787, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6667	{ 786, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6667	{ 786, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6668	{ 785, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6668	{ 785, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6669	{ 784, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6669	{ 784, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6670	{ 783, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6670	{ 783, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6671	{ 782, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	6671	{ 782, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<
6672	{ 781, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	6672	{ 781, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<
6673	{ 780, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6673	{ 780, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6674	{ 779, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6674	{ 779, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6675	{ 778, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6675	{ 778, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6676	{ 777, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6676	{ 777, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6677	{ 776, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #776 = ADDVI_W	6677	{ 776, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #776 = ADDVI_W
6678	{ 775, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #775 = ADDVI_H	6678	{ 775, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #775 = ADDVI_H
6679	{ 774, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #774 = ADDVI_D	6679	{ 774, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #774 = ADDVI_D
6680	{ 773, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #773 = ADDVI_B	6680	{ 773, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #773 = ADDVI_B
6681	{ 772, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6681	{ 772, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6682	{ 771, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6682	{ 771, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6683	{ 770, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6683	{ 770, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6684	{ 769, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6684	{ 769, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6685	{ 768, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6685	{ 768, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6686	{ 767, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6686	{ 767, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6687	{ 766, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6687	{ 766, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6688	{ 765, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6688	{ 765, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6689	{ 764, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6689	{ 764, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6690	{ 763, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6690	{ 763, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6691	{ 762, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6691	{ 762, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6692	{ 761, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6692	{ 761, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6693	{ 760, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6693	{ 760, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6694	{ 759, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	6694	{ 759, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<
6695	{ 758, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	6695	{ 758, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<
6696	{ 757, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6696	{ 757, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6697	{ 756, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6697	{ 756, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6698	{ 755, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6698	{ 755, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6699	{ 754, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6699	{ 754, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6700	{ 753, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6700	{ 753, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6701	{ 752, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6701	{ 752, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6702	{ 751, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6702	{ 751, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6703	{ 750, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6703	{ 750, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6704	{ 749, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6704	{ 749, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6705	{ 748, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6705	{ 748, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6706	{ 747, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6706	{ 747, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6707	{ 746, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	6707	{ 746, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<
6708	{ 745, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	6708	{ 745, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<
6709	{ 744, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	6709	{ 744, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<
6710	{ 743, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	6710	{ 743, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<
6711	{ 742, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	6711	{ 742, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<
6712	{ 741, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	6712	{ 741, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<
6713	{ 740, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6713	{ 740, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6714	{ 739, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6714	{ 739, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6715	{ 738, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6715	{ 738, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6716	{ 737, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	6716	{ 737, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<
6717	{ 736, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6717	{ 736, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6718	{ 735, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6718	{ 735, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6719	{ 734, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6719	{ 734, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6720	{ 733, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6720	{ 733, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6721	{ 732, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6721	{ 732, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6722	{ 731, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6722	{ 731, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6723	{ 730, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6723	{ 730, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6724	{ 729, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	6724	{ 729, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<
6725	{ 728, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6725	{ 728, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6726	{ 727, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	6726	{ 727, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
6727	{ 726, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #726 = ADDIUS5_MM	6727	{ 726, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #726 = ADDIUS5_MM
6728	{ 725, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	6728	{ 725, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<
6729	{ 724, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	6729	{ 724, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<
6730	{ 723, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6730	{ 723, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6731	{ 722, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	6731	{ 722, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<
6732	{ 721, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6732	{ 721, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6733	{ 720, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6733	{ 720, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6734	{ 719, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	6734	{ 719, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<
6735	{ 718, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	6735	{ 718, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<
6736	{ 717, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	6736	{ 717, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<
6737	{ 716, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	6737	{ 716, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<
6738	{ 715, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	6738	{ 715, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<
6739	{ 714, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	6739	{ 714, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<
6740	{ 713, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6740	{ 713, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6741	{ 712, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6741	{ 712, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6742	{ 711, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6742	{ 711, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6743	{ 710, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6743	{ 710, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6744	{ 709, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6744	{ 709, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6745	{ 708, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6745	{ 708, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6746	{ 707, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6746	{ 707, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6747	{ 706, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6747	{ 706, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6748	{ 705, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6748	{ 705, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6749	{ 704, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6749	{ 704, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6750	{ 703, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6750	{ 703, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6751	{ 702, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6751	{ 702, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6752	{ 701, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6752	{ 701, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6753	{ 700, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6753	{ 700, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6754	{ 699, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6754	{ 699, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6755	{ 698, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	6755	{ 698, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<
6756	{ 697, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	6756	{ 697, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<
6757	{ 696, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6757	{ 696, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6758	{ 695, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6758	{ 695, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6759	{ 694, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	6759	{ 694, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<
6760	{ 693, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6760	{ 693, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6761	{ 692, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	6761	{ 692, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<
6762	{ 691, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6762	{ 691, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6763	{ 690, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6763	{ 690, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6764	{ 689, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	6764	{ 689, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<
6765	{ 688, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	6765	{ 688, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<
6766	{ 687, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	6766	{ 687, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<
6767	{ 686, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	6767	{ 686, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<
6768	{ 685, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 392, 0\|(1ULL<	6768	{ 685, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 392, 0\|(1ULL<
6769	{ 684, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	6769	{ 684, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<
6770	{ 683, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	6770	{ 683, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<
6771	{ 682, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	6771	{ 682, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<
6772	{ 681, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	6772	{ 681, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<
6773	{ 680, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6773	{ 680, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6774	{ 679, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6774	{ 679, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6775	{ 678, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6775	{ 678, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6776	{ 677, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6776	{ 677, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6777	{ 676, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6777	{ 676, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6778	{ 675, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6778	{ 675, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6779	{ 674, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6779	{ 674, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6780	{ 673, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6780	{ 673, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6781	{ 672, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6781	{ 672, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6782	{ 671, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6782	{ 671, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6783	{ 670, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	6783	{ 670, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<
6784	{ 669, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	6784	{ 669, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<
6785	{ 668, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	6785	{ 668, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<
6786	{ 667, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	6786	{ 667, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<
6787	{ 666, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	6787	{ 666, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
6788	{ 665, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	6788	{ 665, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
6789	{ 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	6789	{ 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<
6790	{ 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	6790	{ 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<
6791	{ 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	6791	{ 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<
6792	{ 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	6792	{ 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<
6793	{ 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	6793	{ 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<
6794	{ 659, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	6794	{ 659, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<
6795	{ 658, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	6795	{ 658, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<
6796	{ 657, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	6796	{ 657, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<
6797	{ 656, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	6797	{ 656, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<
6798	{ 655, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	6798	{ 655, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<
6799	{ 654, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	6799	{ 654, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<
6800	{ 653, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	6800	{ 653, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<
6801	{ 652, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	6801	{ 652, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<
6802	{ 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6802	{ 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6803	{ 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6803	{ 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6804	{ 649, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	6804	{ 649, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<
6805	{ 648, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	6805	{ 648, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<
6806	{ 647, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	6806	{ 647, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<
6807	{ 646, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	6807	{ 646, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<
6808	{ 645, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	6808	{ 645, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<
6809	{ 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6809	{ 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6810	{ 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6810	{ 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6811	{ 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6811	{ 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6812	{ 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6812	{ 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6813	{ 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6813	{ 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6814	{ 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6814	{ 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6815	{ 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6815	{ 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6816	{ 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6816	{ 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6817	{ 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6817	{ 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6818	{ 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6818	{ 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6819	{ 634, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6819	{ 634, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6820	{ 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6820	{ 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6821	{ 632, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6821	{ 632, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6822	{ 631, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6822	{ 631, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6823	{ 630, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6823	{ 630, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6824	{ 629, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6824	{ 629, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6825	{ 628, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6825	{ 628, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6826	{ 627, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6826	{ 627, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6827	{ 626, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6827	{ 626, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6828	{ 625, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6828	{ 625, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6829	{ 624, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6829	{ 624, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6830	{ 623, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6830	{ 623, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6831	{ 622, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0\|(1ULL<	6831	{ 622, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0\|(1ULL<
6832	{ 621, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6832	{ 621, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6833	{ 620, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6833	{ 620, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6834	{ 619, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6834	{ 619, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6835	{ 618, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	6835	{ 618, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<
6836	{ 617, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6836	{ 617, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6837	{ 616, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6837	{ 616, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6838	{ 615, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6838	{ 615, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6839	{ 614, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6839	{ 614, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6840	{ 613, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6840	{ 613, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6841	{ 612, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6841	{ 612, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6842	{ 611, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6842	{ 611, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6843	{ 610, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 485, 0\|(1ULL<	6843	{ 610, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 485, 0\|(1ULL<
6844	{ 609, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 482, 0\|(1ULL<	6844	{ 609, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 482, 0\|(1ULL<
6845	{ 608, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 479, 0\|(1ULL<	6845	{ 608, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 479, 0\|(1ULL<
6846	{ 607, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0\|(1ULL<	6846	{ 607, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0\|(1ULL<
6847	{ 606, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0\|(1ULL<	6847	{ 606, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0\|(1ULL<
6848	{ 605, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0\|(1ULL<	6848	{ 605, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0\|(1ULL<
6849	{ 604, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0\|(1ULL<	6849	{ 604, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0\|(1ULL<
6850	{ 603, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0\|(1ULL<	6850	{ 603, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0\|(1ULL<
6851	{ 602, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	6851	{ 602, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<
6852	{ 601, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	6852	{ 601, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<
6853	{ 600, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	6853	{ 600, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<
6854	{ 599, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	6854	{ 599, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<
6855	{ 598, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	6855	{ 598, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<
6856	{ 597, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	6856	{ 597, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<
6857	{ 596, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	6857	{ 596, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<
6858	{ 595, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	6858	{ 595, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<
6859	{ 594, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	6859	{ 594, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<
6860	{ 593, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	6860	{ 593, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<
6861	{ 592, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6861	{ 592, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6862	{ 591, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	6862	{ 591, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
6863	{ 590, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6863	{ 590, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6864	{ 589, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	6864	{ 589, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<
6865	{ 588, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	6865	{ 588, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<
6866	{ 587, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6866	{ 587, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6867	{ 586, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6867	{ 586, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6868	{ 585, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6868	{ 585, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6869	{ 584, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6869	{ 584, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6870	{ 583, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6870	{ 583, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6871	{ 582, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	6871	{ 582, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<
6872	{ 581, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	6872	{ 581, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<
6873	{ 580, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	6873	{ 580, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<
6874	{ 579, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6874	{ 579, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6875	{ 578, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6875	{ 578, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6876	{ 577, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6876	{ 577, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6877	{ 576, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6877	{ 576, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6878	{ 575, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	6878	{ 575, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<
6879	{ 574, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	6879	{ 574, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<
6880	{ 573, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	6880	{ 573, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<
6881	{ 572, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	6881	{ 572, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<
6882	{ 571, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	6882	{ 571, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<
6883	{ 570, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	6883	{ 570, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<
6884	{ 569, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6884	{ 569, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6885	{ 568, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6885	{ 568, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6886	{ 567, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6886	{ 567, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6887	{ 566, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	6887	{ 566, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<
6888	{ 565, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6888	{ 565, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6889	{ 564, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	6889	{ 564, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
6890	{ 563, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	6890	{ 563, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
6891	{ 562, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6891	{ 562, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6892	{ 561, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6892	{ 561, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6893	{ 560, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6893	{ 560, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6894	{ 559, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6894	{ 559, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6895	{ 558, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	6895	{ 558, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
6896	{ 557, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	6896	{ 557, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<
6897	{ 556, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6897	{ 556, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6898	{ 555, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 414, 0\|(1ULL<	6898	{ 555, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 414, 0\|(1ULL<
6899	{ 554, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 407, 0\|(1ULL<	6899	{ 554, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 407, 0\|(1ULL<
6900	{ 553, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	6900	{ 553, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<
6901	{ 552, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	6901	{ 552, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<
6902	{ 551, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	6902	{ 551, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<
6903	{ 550, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	6903	{ 550, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<
6904	{ 549, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	6904	{ 549, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
6905	{ 548, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	6905	{ 548, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<
6906	{ 547, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	6906	{ 547, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<
6907	{ 546, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	6907	{ 546, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<
6908	{ 545, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 398, 0\|(1ULL<	6908	{ 545, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 398, 0\|(1ULL<
6909	{ 544, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6909	{ 544, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6910	{ 543, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6910	{ 543, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6911	{ 542, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6911	{ 542, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6912	{ 541, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6912	{ 541, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6913	{ 540, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6913	{ 540, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6914	{ 539, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	6914	{ 539, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<
6915	{ 538, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6915	{ 538, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6916	{ 537, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6916	{ 537, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6917	{ 536, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6917	{ 536, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6918	{ 535, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	6918	{ 535, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
6919	{ 534, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	6919	{ 534, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
6920	{ 533, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	6920	{ 533, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
6921	{ 532, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	6921	{ 532, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
6922	{ 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6922	{ 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6923	{ 530, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	6923	{ 530, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
6924	{ 529, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	6924	{ 529, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<
6925	{ 528, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	6925	{ 528, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<
6926	{ 527, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	6926	{ 527, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<
6927	{ 526, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	6927	{ 526, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<
6928	{ 525, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6928	{ 525, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6929	{ 524, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	6929	{ 524, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
6930	{ 523, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6930	{ 523, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6931	{ 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	6931	{ 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<
6932	{ 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	6932	{ 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<
6933	{ 520, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	6933	{ 520, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
6934	{ 519, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6934	{ 519, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6935	{ 518, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6935	{ 518, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6936	{ 517, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	6936	{ 517, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<
6937	{ 516, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	6937	{ 516, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<
6938	{ 515, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	6938	{ 515, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<
6939	{ 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0\|(1ULL<	6939	{ 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0\|(1ULL<
6940	{ 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0\|(1ULL<	6940	{ 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0\|(1ULL<
6941	{ 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0\|(1ULL<	6941	{ 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0\|(1ULL<
6942	{ 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0\|(1ULL<	6942	{ 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0\|(1ULL<
6943	{ 510, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 373, 0\|(1ULL<	6943	{ 510, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 373, 0\|(1ULL<
6944	{ 509, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 136, 0\|(1ULL<	6944	{ 509, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 136, 0\|(1ULL<
6945	{ 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	6945	{ 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<
6946	{ 507, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	6946	{ 507, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<
6947	{ 506, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	6947	{ 506, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<
6948	{ 505, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	6948	{ 505, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
6949	{ 504, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6949	{ 504, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6950	{ 503, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	6950	{ 503, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<
6951	{ 502, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	6951	{ 502, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<
6952	{ 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	6952	{ 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<
6953	{ 500, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 363, 0\|(1ULL<	6953	{ 500, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 363, 0\|(1ULL<
6954	{ 499, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6954	{ 499, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6955	{ 498, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0\|(1ULL<	6955	{ 498, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0\|(1ULL<
6956	{ 497, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6956	{ 497, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6957	{ 496, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0\|(1ULL<	6957	{ 496, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0\|(1ULL<
6958	{ 495, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0\|(1ULL<	6958	{ 495, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0\|(1ULL<
6959	{ 494, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	6959	{ 494, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
6960	{ 493, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	6960	{ 493, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<
6961	{ 492, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	6961	{ 492, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<
6962	{ 491, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6962	{ 491, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6963	{ 490, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	6963	{ 490, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<
6964	{ 489, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 348, 0\|(1ULL<	6964	{ 489, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 348, 0\|(1ULL<
6965	{ 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	6965	{ 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<
6966	{ 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0\|(1ULL<	6966	{ 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0\|(1ULL<
6967	{ 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 341, 0\|(1ULL<	6967	{ 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 341, 0\|(1ULL<
6968	{ 485, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 338, 0\|(1ULL<	6968	{ 485, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 338, 0\|(1ULL<
6969	{ 484, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0\|(1ULL<	6969	{ 484, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0\|(1ULL<
6970	{ 483, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0\|(1ULL<	6970	{ 483, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0\|(1ULL<
6971	{ 482, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	6971	{ 482, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
6972	{ 481, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 327, 0\|(1ULL<	6972	{ 481, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 327, 0\|(1ULL<
6973	{ 480, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	6973	{ 480, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<
6974	{ 479, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	6974	{ 479, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<
6975	{ 478, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	6975	{ 478, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<
6976	{ 477, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	6976	{ 477, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<
6977	{ 476, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	6977	{ 476, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<
6978	{ 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	6978	{ 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<
6979	{ 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	6979	{ 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<
6980	{ 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	6980	{ 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<
6981	{ 472, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	6981	{ 472, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
6982	{ 471, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	6982	{ 471, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<
6983	{ 470, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	6983	{ 470, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<
6984	{ 469, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	6984	{ 469, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<
6985	{ 468, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	6985	{ 468, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<
6986	{ 467, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	6986	{ 467, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<
6987	{ 466, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	6987	{ 466, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<
6988	{ 465, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0\|(1ULL<	6988	{ 465, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0\|(1ULL<
6989	{ 464, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0\|(1ULL<	6989	{ 464, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0\|(1ULL<
6990	{ 463, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0\|(1ULL<	6990	{ 463, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0\|(1ULL<
6991	{ 462, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0\|(1ULL<	6991	{ 462, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0\|(1ULL<
6992	{ 461, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0\|(1ULL<	6992	{ 461, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0\|(1ULL<
6993	{ 460, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 278, 0\|(1ULL<	6993	{ 460, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 278, 0\|(1ULL<
6994	{ 459, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 274, 0\|(1ULL<	6994	{ 459, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 274, 0\|(1ULL<
6995	{ 458, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0\|(1ULL<	6995	{ 458, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0\|(1ULL<
6996	{ 457, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0\|(1ULL<	6996	{ 457, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0\|(1ULL<
6997	{ 456, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 262, 0\|(1ULL<	6997	{ 456, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 262, 0\|(1ULL<
6998	{ 455, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0\|(1ULL<	6998	{ 455, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0\|(1ULL<
6999	{ 454, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0\|(1ULL<	6999	{ 454, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0\|(1ULL<
7000	{ 453, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0\|(1ULL<	7000	{ 453, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0\|(1ULL<
7001	{ 452, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 246, 0\|(1ULL<	7001	{ 452, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 246, 0\|(1ULL<
7002	{ 451, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 242, 0\|(1ULL<	7002	{ 451, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 242, 0\|(1ULL<
7003	{ 450, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 240, 0\|(1ULL<	7003	{ 450, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 240, 0\|(1ULL<
7004	{ 449, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 238, 0\|(1ULL<	7004	{ 449, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 238, 0\|(1ULL<
7005	{ 448, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	7005	{ 448, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<
7006	{ 447, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	7006	{ 447, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<
7007	{ 446, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	7007	{ 446, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<
7008	{ 445, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	7008	{ 445, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<
7009	{ 444, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 231, 0\|(1ULL<	7009	{ 444, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 231, 0\|(1ULL<
7010	{ 443, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 228, 0\|(1ULL<	7010	{ 443, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 228, 0\|(1ULL<
7011	{ 442, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7011	{ 442, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7012	{ 441, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7012	{ 441, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7013	{ 440, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	7013	{ 440, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
7014	{ 439, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7014	{ 439, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7015	{ 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	7015	{ 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
7016	{ 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7016	{ 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7017	{ 436, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	7017	{ 436, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
7018	{ 435, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7018	{ 435, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7019	{ 434, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	7019	{ 434, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
7020	{ 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	7020	{ 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
7021	{ 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	7021	{ 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
7022	{ 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	7022	{ 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<
7023	{ 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	7023	{ 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<
7024	{ 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7024	{ 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7025	{ 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7025	{ 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7026	{ 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	7026	{ 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<
7027	{ 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	7027	{ 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<
7028	{ 425, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7028	{ 425, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7029	{ 424, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 214, 0\|(1ULL<	7029	{ 424, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 214, 0\|(1ULL<
7030	{ 423, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 211, 0\|(1ULL<	7030	{ 423, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 211, 0\|(1ULL<
7031	{ 422, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 208, 0\|(1ULL<	7031	{ 422, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 208, 0\|(1ULL<
7032	{ 421, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	7032	{ 421, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<
7033	{ 420, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 206, 0\|(1ULL<	7033	{ 420, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 206, 0\|(1ULL<
7034	{ 419, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 203, 0\|(1ULL<	7034	{ 419, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 203, 0\|(1ULL<
7035	{ 418, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 200, 0\|(1ULL<	7035	{ 418, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 200, 0\|(1ULL<
7036	{ 417, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7036	{ 417, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7037	{ 416, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7037	{ 416, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7038	{ 415, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7038	{ 415, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7039	{ 414, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7039	{ 414, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7040	{ 413, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7040	{ 413, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7041	{ 412, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7041	{ 412, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7042	{ 411, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7042	{ 411, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7043	{ 410, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7043	{ 410, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7044	{ 409, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7044	{ 409, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7045	{ 408, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7045	{ 408, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7046	{ 407, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	7046	{ 407, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<
7047	{ 406, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	7047	{ 406, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<
7048	{ 405, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7048	{ 405, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7049	{ 404, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7049	{ 404, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7050	{ 403, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	7050	{ 403, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
7051	{ 402, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	7051	{ 402, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<
7052	{ 401, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	7052	{ 401, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<
7053	{ 400, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	7053	{ 400, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<
7054	{ 399, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0\|(1ULL<	7054	{ 399, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0\|(1ULL<
7055	{ 398, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	7055	{ 398, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<
7056	{ 397, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	7056	{ 397, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<
7057	{ 396, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	7057	{ 396, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<
7058	{ 395, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 181, 0\|(1ULL<	7058	{ 395, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 181, 0\|(1ULL<
7059	{ 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7059	{ 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7060	{ 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7060	{ 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7061	{ 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7061	{ 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7062	{ 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7062	{ 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7063	{ 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7063	{ 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7064	{ 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7064	{ 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7065	{ 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7065	{ 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7066	{ 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7066	{ 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7067	{ 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7067	{ 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7068	{ 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7068	{ 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7069	{ 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7069	{ 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7070	{ 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7070	{ 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7071	{ 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7071	{ 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7072	{ 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7072	{ 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7073	{ 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7073	{ 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7074	{ 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7074	{ 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7075	{ 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7075	{ 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7076	{ 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7076	{ 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7077	{ 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7077	{ 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7078	{ 375, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7078	{ 375, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7079	{ 374, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7079	{ 374, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7080	{ 373, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7080	{ 373, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7081	{ 372, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7081	{ 372, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7082	{ 371, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7082	{ 371, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7083	{ 370, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7083	{ 370, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7084	{ 369, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7084	{ 369, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7085	{ 368, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7085	{ 368, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7086	{ 367, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7086	{ 367, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7087	{ 366, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7087	{ 366, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7088	{ 365, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7088	{ 365, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7089	{ 364, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7089	{ 364, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7090	{ 363, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7090	{ 363, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7091	{ 362, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	7091	{ 362, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<
7092	{ 361, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	7092	{ 361, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<
7093	{ 360, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	7093	{ 360, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<
7094	{ 359, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	7094	{ 359, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<
7095	{ 358, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	7095	{ 358, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<
7096	{ 357, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7096	{ 357, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7097	{ 356, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7097	{ 356, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7098	{ 355, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7098	{ 355, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7099	{ 354, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7099	{ 354, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7100	{ 353, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7100	{ 353, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7101	{ 352, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7101	{ 352, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7102	{ 351, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7102	{ 351, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7103	{ 350, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7103	{ 350, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7104	{ 349, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7104	{ 349, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7105	{ 348, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7105	{ 348, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7106	{ 347, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7106	{ 347, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7107	{ 346, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7107	{ 346, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7108	{ 345, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7108	{ 345, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7109	{ 344, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7109	{ 344, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7110	{ 343, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7110	{ 343, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7111	{ 342, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7111	{ 342, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7112	{ 341, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7112	{ 341, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7113	{ 340, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7113	{ 340, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7114	{ 339, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7114	{ 339, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7115	{ 338, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7115	{ 338, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7116	{ 337, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7116	{ 337, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7117	{ 336, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7117	{ 336, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7118	{ 335, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7118	{ 335, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7119	{ 334, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7119	{ 334, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7120	{ 333, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7120	{ 333, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7121	{ 332, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7121	{ 332, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7122	{ 331, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7122	{ 331, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7123	{ 330, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7123	{ 330, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7124	{ 329, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7124	{ 329, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7125	{ 328, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7125	{ 328, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7126	{ 327, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7126	{ 327, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7127	{ 326, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7127	{ 326, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7128	{ 325, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7128	{ 325, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7129	{ 324, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7129	{ 324, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7130	{ 323, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7130	{ 323, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7131	{ 322, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7131	{ 322, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7132	{ 321, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7132	{ 321, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7133	{ 320, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7133	{ 320, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7134	{ 319, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7134	{ 319, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7135	{ 318, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7135	{ 318, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7136	{ 317, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7136	{ 317, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7137	{ 316, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7137	{ 316, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7138	{ 315, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7138	{ 315, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7139	{ 314, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7139	{ 314, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7140	{ 313, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7140	{ 313, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7141	{ 312, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7141	{ 312, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7142	{ 311, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7142	{ 311, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7143	{ 310, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7143	{ 310, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7144	{ 309, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7144	{ 309, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7145	{ 308, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7145	{ 308, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7146	{ 307, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7146	{ 307, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7147	{ 306, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7147	{ 306, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7148	{ 305, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7148	{ 305, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7149	{ 304, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7149	{ 304, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7150	{ 303, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7150	{ 303, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7151	{ 302, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7151	{ 302, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7152	{ 301, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7152	{ 301, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7153	{ 300, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7153	{ 300, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7154	{ 299, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7154	{ 299, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7155	{ 298, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7155	{ 298, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7156	{ 297, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7156	{ 297, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7157	{ 296, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7157	{ 296, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7158	{ 295, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7158	{ 295, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7159	{ 294, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7159	{ 294, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7160	{ 293, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7160	{ 293, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7161	{ 292, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7161	{ 292, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7162	{ 291, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7162	{ 291, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7163	{ 290, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7163	{ 290, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7164	{ 289, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7164	{ 289, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7165	{ 288, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7165	{ 288, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7166	{ 287, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7166	{ 287, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7167	{ 286, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7167	{ 286, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7168	{ 285, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7168	{ 285, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7169	{ 284, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7169	{ 284, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7170	{ 283, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7170	{ 283, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7171	{ 282, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7171	{ 282, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7172	{ 281, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7172	{ 281, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7173	{ 280, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7173	{ 280, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7174	{ 279, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7174	{ 279, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7175	{ 278, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7175	{ 278, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7176	{ 277, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7176	{ 277, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7177	{ 276, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7177	{ 276, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7178	{ 275, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7178	{ 275, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7179	{ 274, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	7179	{ 274, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<
7180	{ 273, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7180	{ 273, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7181	{ 272, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7181	{ 272, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7182	{ 271, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	7182	{ 271, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<
7183	{ 270, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	7183	{ 270, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<
7184	{ 269, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	7184	{ 269, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<
7185	{ 268, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	7185	{ 268, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<
7186	{ 267, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	7186	{ 267, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<
7187	{ 266, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	7187	{ 266, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<
7188	{ 265, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	7188	{ 265, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<
7189	{ 264, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	7189	{ 264, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<
7190	{ 263, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	7190	{ 263, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<
7191	{ 262, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	7191	{ 262, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<
7192	{ 261, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	7192	{ 261, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<
7193	{ 260, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	7193	{ 260, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<
7194	{ 259, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	7194	{ 259, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<
7195	{ 258, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	7195	{ 258, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<
7196	{ 257, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	7196	{ 257, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<
7197	{ 256, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	7197	{ 256, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<
7198	{ 255, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	7198	{ 255, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<
7199	{ 254, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	7199	{ 254, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<
7200	{ 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7200	{ 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7201	{ 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7201	{ 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7202	{ 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7202	{ 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7203	{ 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7203	{ 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7204	{ 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7204	{ 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7205	{ 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7205	{ 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7206	{ 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7206	{ 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7207	{ 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7207	{ 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7208	{ 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7208	{ 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7209	{ 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7209	{ 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7210	{ 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7210	{ 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7211	{ 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7211	{ 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7212	{ 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7212	{ 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7213	{ 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	7213	{ 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<
7214	{ 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	7214	{ 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<
7215	{ 238, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	7215	{ 238, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<
7216	{ 237, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	7216	{ 237, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<
7217	{ 236, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	7217	{ 236, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<
7218	{ 235, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	7218	{ 235, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<
7219	{ 234, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	7219	{ 234, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<
7220	{ 233, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0\|(1ULL<	7220	{ 233, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0\|(1ULL<
7221	{ 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7221	{ 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7222	{ 231, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7222	{ 231, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7223	{ 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7223	{ 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7224	{ 229, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	7224	{ 229, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<
7225	{ 228, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7225	{ 228, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7226	{ 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7226	{ 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7227	{ 226, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7227	{ 226, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7228	{ 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7228	{ 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7229	{ 224, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7229	{ 224, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7230	{ 223, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	7230	{ 223, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<
7231	{ 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7231	{ 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7232	{ 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7232	{ 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7233	{ 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7233	{ 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7234	{ 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7234	{ 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7235	{ 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7235	{ 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7236	{ 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7236	{ 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7237	{ 216, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7237	{ 216, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7238	{ 215, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7238	{ 215, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7239	{ 214, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7239	{ 214, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7240	{ 213, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7240	{ 213, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7241	{ 212, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7241	{ 212, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7242	{ 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7242	{ 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7243	{ 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7243	{ 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7244	{ 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7244	{ 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7245	{ 208, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7245	{ 208, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7246	{ 207, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7246	{ 207, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7247	{ 206, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7247	{ 206, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7248	{ 205, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 122, 0\|(1ULL<	7248	{ 205, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 122, 0\|(1ULL<
7249	{ 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	7249	{ 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<
7250	{ 203, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0\|(1ULL<	7250	{ 203, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0\|(1ULL<
7251	{ 202, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0\|(1ULL<	7251	{ 202, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0\|(1ULL<
7252	{ 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7252	{ 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7253	{ 200, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7253	{ 200, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7254	{ 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7254	{ 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7255	{ 198, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7255	{ 198, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7256	{ 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7256	{ 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7257	{ 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7257	{ 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7258	{ 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7258	{ 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7259	{ 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7259	{ 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7260	{ 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7260	{ 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7261	{ 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7261	{ 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7262	{ 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7262	{ 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7263	{ 190, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7263	{ 190, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7264	{ 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7264	{ 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7265	{ 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7265	{ 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7266	{ 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7266	{ 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7267	{ 186, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7267	{ 186, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7268	{ 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7268	{ 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7269	{ 184, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	7269	{ 184, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<
7270	{ 183, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7270	{ 183, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7271	{ 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7271	{ 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7272	{ 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7272	{ 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7273	{ 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7273	{ 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7274	{ 179, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7274	{ 179, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7275	{ 178, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7275	{ 178, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7276	{ 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7276	{ 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7277	{ 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7277	{ 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7278	{ 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7278	{ 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7279	{ 174, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7279	{ 174, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7280	{ 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7280	{ 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7281	{ 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7281	{ 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7282	{ 171, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7282	{ 171, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7283	{ 170, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7283	{ 170, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7284	{ 169, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7284	{ 169, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7285	{ 168, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7285	{ 168, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7286	{ 167, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7286	{ 167, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7287	{ 166, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7287	{ 166, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7288	{ 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7288	{ 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7289	{ 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7289	{ 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7290	{ 163, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	7290	{ 163, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<
7291	{ 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	7291	{ 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<
7292	{ 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7292	{ 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7293	{ 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7293	{ 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7294	{ 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7294	{ 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7295	{ 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7295	{ 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7296	{ 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7296	{ 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7297	{ 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7297	{ 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7298	{ 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7298	{ 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7299	{ 154, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7299	{ 154, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7300	{ 153, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7300	{ 153, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7301	{ 152, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7301	{ 152, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7302	{ 151, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	7302	{ 151, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<
7303	{ 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7303	{ 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7304	{ 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7304	{ 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7305	{ 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7305	{ 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7306	{ 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7306	{ 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7307	{ 146, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7307	{ 146, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7308	{ 145, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7308	{ 145, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7309	{ 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7309	{ 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7310	{ 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7310	{ 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7311	{ 142, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7311	{ 142, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7312	{ 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7312	{ 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7313	{ 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	7313	{ 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<
7314	{ 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7314	{ 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7315	{ 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	7315	{ 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<
7316	{ 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7316	{ 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7317	{ 136, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	7317	{ 136, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<
7318	{ 135, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7318	{ 135, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7319	{ 134, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	7319	{ 134, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<
7320	{ 133, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7320	{ 133, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7321	{ 132, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7321	{ 132, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7322	{ 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	7322	{ 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<
7323	{ 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	7323	{ 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<
7324	{ 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7324	{ 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7325	{ 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7325	{ 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7326	{ 127, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	7326	{ 127, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<
7327	{ 126, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	7327	{ 126, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<
7328	{ 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7328	{ 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7329	{ 124, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7329	{ 124, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7330	{ 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	7330	{ 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<
7331	{ 122, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7331	{ 122, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7332	{ 121, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	7332	{ 121, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<
7333	{ 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7333	{ 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7334	{ 119, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	7334	{ 119, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<
7335	{ 118, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	7335	{ 118, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<
7336	{ 117, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7336	{ 117, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7337	{ 116, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7337	{ 116, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7338	{ 115, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7338	{ 115, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7339	{ 114, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7339	{ 114, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7340	{ 113, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7340	{ 113, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7341	{ 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7341	{ 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7342	{ 111, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7342	{ 111, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7343	{ 110, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	7343	{ 110, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<
7344	{ 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7344	{ 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7345	{ 108, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	7345	{ 108, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<
7346	{ 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7346	{ 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7347	{ 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7347	{ 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7348	{ 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7348	{ 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7349	{ 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7349	{ 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7350	{ 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7350	{ 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7351	{ 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7351	{ 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7352	{ 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7352	{ 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7353	{ 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7353	{ 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7354	{ 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7354	{ 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7355	{ 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7355	{ 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7356	{ 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7356	{ 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7357	{ 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7357	{ 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7358	{ 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7358	{ 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7359	{ 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7359	{ 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7360	{ 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7360	{ 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7361	{ 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7361	{ 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7362	{ 91, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	7362	{ 91, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<
7363	{ 90, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	7363	{ 90, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<
7364	{ 89, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0\|(1ULL<	7364	{ 89, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0\|(1ULL<
7365	{ 88, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0\|(1ULL<	7365	{ 88, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0\|(1ULL<
7366	{ 87, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7366	{ 87, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7367	{ 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	7367	{ 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<
7368	{ 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	7368	{ 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<
7369	{ 84, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	7369	{ 84, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<
7370	{ 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7370	{ 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7371	{ 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7371	{ 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7372	{ 81, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7372	{ 81, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7373	{ 80, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	7373	{ 80, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<
7374	{ 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7374	{ 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7375	{ 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7375	{ 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7376	{ 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7376	{ 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7377	{ 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7377	{ 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7378	{ 75, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	7378	{ 75, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<
7379	{ 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7379	{ 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7380	{ 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	7380	{ 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<
7381	{ 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7381	{ 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7382	{ 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7382	{ 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7383	{ 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7383	{ 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7384	{ 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7384	{ 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7385	{ 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7385	{ 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7386	{ 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7386	{ 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7387	{ 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7387	{ 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7388	{ 65, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0\|(1ULL<	7388	{ 65, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0\|(1ULL<
7389	{ 64, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	7389	{ 64, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<
7390	{ 63, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	7390	{ 63, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<
7391	{ 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7391	{ 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7392	{ 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7392	{ 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7393	{ 60, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	7393	{ 60, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<
7394	{ 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	7394	{ 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<
7395	{ 58, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	7395	{ 58, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<
7396	{ 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7396	{ 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7397	{ 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7397	{ 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7398	{ 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7398	{ 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7399	{ 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	7399	{ 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<
7400	{ 53, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	7400	{ 53, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<
7401	{ 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7401	{ 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7402	{ 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7402	{ 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7403	{ 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7403	{ 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7404	{ 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7404	{ 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7405	{ 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7405	{ 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7406	{ 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7406	{ 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7407	{ 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	7407	{ 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<
7408	{ 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	7408	{ 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<
7409	{ 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	7409	{ 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<
7410	{ 43, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	7410	{ 43, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<
7411	{ 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7411	{ 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7412	{ 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7412	{ 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7413	{ 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0\|(1ULL<	7413	{ 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0\|(1ULL<
7414	{ 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0\|(1ULL<	7414	{ 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0\|(1ULL<
7415	{ 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7415	{ 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7416	{ 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7416	{ 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7417	{ 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7417	{ 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7418	{ 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7418	{ 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7419	{ 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7419	{ 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7420	{ 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7420	{ 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7421	{ 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0\|(1ULL<	7421	{ 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0\|(1ULL<
7422	{ 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7422	{ 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7423	{ 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0\|(1ULL<	7423	{ 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0\|(1ULL<
7424	{ 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7424	{ 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7425	{ 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0\|(1ULL<	7425	{ 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0\|(1ULL<
7426	{ 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0\|(1ULL<	7426	{ 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0\|(1ULL<
7427	{ 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7427	{ 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7428	{ 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	7428	{ 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<
7429	{ 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0\|(1ULL<	7429	{ 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0\|(1ULL<
7430	{ 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0\|(1ULL<	7430	{ 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0\|(1ULL<
7431	{ 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7431	{ 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7432	{ 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7432	{ 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7433	{ 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7433	{ 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7434	{ 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	7434	{ 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<
7435	{ 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	7435	{ 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<
7436	{ 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7436	{ 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7437	{ 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7437	{ 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7438	{ 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7438	{ 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7439	{ 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7439	{ 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7440	{ 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7440	{ 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7441	{ 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	7441	{ 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<
7442	{ 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0\|(1ULL<	7442	{ 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0\|(1ULL<
7443	{ 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7443	{ 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7444	{ 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0\|(1ULL<	7444	{ 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0\|(1ULL<
7445	{ 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	7445	{ 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<
7446	{ 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7446	{ 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7447	{ 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7447	{ 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7448	{ 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7448	{ 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7449	{ 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7449	{ 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7450	{ 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7450	{ 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7451	{ 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7451	{ 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7452	{ 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	7452	{ 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<
7453	{ 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	7453	{ 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<
7454	}, {	7454	}, {
7455	/* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7455	/* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7456	/* 1 */	7456	/* 1 */
7457	/* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7457	/* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7458	/* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7458	/* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7459	/* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7459	/* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7460	/* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7460	/* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7461	/* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7461	/* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7462	/* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7462	/* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7463	/* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },	7463	/* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
7464	/* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7464	/* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7465	/* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7465	/* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7466	/* 29 */ { 0, 0\|(1<	7466	/* 29 */ { 0, 0\|(1<
7467	/* 30 */ { 0, 0\|(1<	7467	/* 30 */ { 0, 0\|(1<
7468	/* 33 */ { 0, 0\|(1<	7468	/* 33 */ { 0, 0\|(1<
7469	/* 35 */ { 0, 0\|(1<	7469	/* 35 */ { 0, 0\|(1<
7470	/* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	7470	/* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<
7471	/* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	7471	/* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7472	/* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7472	/* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7473	/* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7473	/* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7474	/* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7474	/* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7475	/* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7475	/* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7476	/* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	7476	/* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7477	/* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7477	/* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7478	/* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	7478	/* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7479	/* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7479	/* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7480	/* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7480	/* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7481	/* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7481	/* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7482	/* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7482	/* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7483	/* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7483	/* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7484	/* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7484	/* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7485	/* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7485	/* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7486	/* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7486	/* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7487	/* 92 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7487	/* 92 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7488	/* 95 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7488	/* 95 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7489	/* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7489	/* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7490	/* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7490	/* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7491	/* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	7491	/* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7492	/* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7492	/* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7493	/* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	7493	/* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7494	/* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	7494	/* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7495	/* 122 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7495	/* 122 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7496	/* 126 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	7496	/* 126 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7497	/* 128 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	7497	/* 128 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7498	/* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	7498	/* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7499	/* 136 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7499	/* 136 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7500	/* 138 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7500	/* 138 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7501	/* 141 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7501	/* 141 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7502	/* 144 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7502	/* 144 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7503	/* 147 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7503	/* 147 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7504	/* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7504	/* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7505	/* 158 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7505	/* 158 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7506	/* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7506	/* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7507	/* 165 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7507	/* 165 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7508	/* 171 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7508	/* 171 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7509	/* 174 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },	7509	/* 174 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
7510	/* 175 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7510	/* 175 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7511	/* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7511	/* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7512	/* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7512	/* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7513	/* 182 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7513	/* 182 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7514	/* 186 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7514	/* 186 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7515	/* 190 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7515	/* 190 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7516	/* 194 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7516	/* 194 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7517	/* 197 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7517	/* 197 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7518	/* 200 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7518	/* 200 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7519	/* 203 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7519	/* 203 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7520	/* 206 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7520	/* 206 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7521	/* 208 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7521	/* 208 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7522	/* 211 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7522	/* 211 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7523	/* 214 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7523	/* 214 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7524	/* 216 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7524	/* 216 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7525	/* 219 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7525	/* 219 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7526	/* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7526	/* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7527	/* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7527	/* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7528	/* 228 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7528	/* 228 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7529	/* 231 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7529	/* 231 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7530	/* 234 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7530	/* 234 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7531	/* 236 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7531	/* 236 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7532	/* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7532	/* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7533	/* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7533	/* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7534	/* 242 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7534	/* 242 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7535	/* 246 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7535	/* 246 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7536	/* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7536	/* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7537	/* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7537	/* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7538	/* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7538	/* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7539	/* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7539	/* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7540	/* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7540	/* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7541	/* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7541	/* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7542	/* 274 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7542	/* 274 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7543	/* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7543	/* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7544	/* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7544	/* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7545	/* 286 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7545	/* 286 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7546	/* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7546	/* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7547	/* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7547	/* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7548	/* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7548	/* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7549	/* 302 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7549	/* 302 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7550	/* 303 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7550	/* 303 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7551	/* 306 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7551	/* 306 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7552	/* 309 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7552	/* 309 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7553	/* 312 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7553	/* 312 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7554	/* 315 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7554	/* 315 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7555	/* 318 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7555	/* 318 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7556	/* 321 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7556	/* 321 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7557	/* 324 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7557	/* 324 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7558	/* 327 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7558	/* 327 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7559	/* 331 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7559	/* 331 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7560	/* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7560	/* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7561	/* 338 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7561	/* 338 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7562	/* 341 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7562	/* 341 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7563	/* 343 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7563	/* 343 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7564	/* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	7564	/* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<
7565	/* 348 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7565	/* 348 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7566	/* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7566	/* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7567	/* 352 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7567	/* 352 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7568	/* 355 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7568	/* 355 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7569	/* 357 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7569	/* 357 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7570	/* 359 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7570	/* 359 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7571	/* 361 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7571	/* 361 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7572	/* 363 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7572	/* 363 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7573	/* 366 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7573	/* 366 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7574	/* 368 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7574	/* 368 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7575	/* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7575	/* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7576	/* 373 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7576	/* 373 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7577	/* 375 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7577	/* 375 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7578	/* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7578	/* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7579	/* 379 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7579	/* 379 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7580	/* 381 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7580	/* 381 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7581	/* 383 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7581	/* 383 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7582	/* 385 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7582	/* 385 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7583	/* 388 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7583	/* 388 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7584	/* 390 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7584	/* 390 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7585	/* 392 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7585	/* 392 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7586	/* 395 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7586	/* 395 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7587	/* 398 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7587	/* 398 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7588	/* 400 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7588	/* 400 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7589	/* 402 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7589	/* 402 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7590	/* 404 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7590	/* 404 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7591	/* 407 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7591	/* 407 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7592	/* 414 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7592	/* 414 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7593	/* 421 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7593	/* 421 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7594	/* 425 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7594	/* 425 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7595	/* 427 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7595	/* 427 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7596	/* 429 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7596	/* 429 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7597	/* 432 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7597	/* 432 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7598	/* 435 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7598	/* 435 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7599	/* 439 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7599	/* 439 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7600	/* 443 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7600	/* 443 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7601	/* 447 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7601	/* 447 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7602	/* 451 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7602	/* 451 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7603	/* 455 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7603	/* 455 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7604	/* 459 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7604	/* 459 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7605	/* 463 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7605	/* 463 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7606	/* 467 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7606	/* 467 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7607	/* 471 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7607	/* 471 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7608	/* 475 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7608	/* 475 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7609	/* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7609	/* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7610	/* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7610	/* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7611	/* 485 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7611	/* 485 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7612	/* 488 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7612	/* 488 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7613	/* 491 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7613	/* 491 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7614	/* 494 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7614	/* 494 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7615	/* 496 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7615	/* 496 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7616	/* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7616	/* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7617	/* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7617	/* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7618	/* 502 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7618	/* 502 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7619	/* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7619	/* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7620	/* 511 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7620	/* 511 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7621	/* 516 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7621	/* 516 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7622	/* 519 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7622	/* 519 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7623	/* 521 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7623	/* 521 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7624	/* 523 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7624	/* 523 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7625	/* 526 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7625	/* 526 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7626	/* 529 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7626	/* 529 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7627	/* 532 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7627	/* 532 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7628	/* 535 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7628	/* 535 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7629	/* 538 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7629	/* 538 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7630	/* 541 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7630	/* 541 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7631	/* 544 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7631	/* 544 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7632	/* 547 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7632	/* 547 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7633	/* 550 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7633	/* 550 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7634	/* 553 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7634	/* 553 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7635	/* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7635	/* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7636	/* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7636	/* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7637	/* 564 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7637	/* 564 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7638	/* 566 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7638	/* 566 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7639	/* 569 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7639	/* 569 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7640	/* 572 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7640	/* 572 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7641	/* 575 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7641	/* 575 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7642	/* 578 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7642	/* 578 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7643	/* 580 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7643	/* 580 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7644	/* 582 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7644	/* 582 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7645	/* 584 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7645	/* 584 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7646	/* 586 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7646	/* 586 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7647	/* 590 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7647	/* 590 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7648	/* 594 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7648	/* 594 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7649	/* 598 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7649	/* 598 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7650	/* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7650	/* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7651	/* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7651	/* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7652	/* 608 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7652	/* 608 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7653	/* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7653	/* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7654	/* 612 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7654	/* 612 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7655	/* 614 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	7655	/* 614 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7656	/* 616 */ { 0, 0\|(1<	7656	/* 616 */ { 0, 0\|(1<
7657	/* 619 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7657	/* 619 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7658	/* 621 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7658	/* 621 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7659	/* 623 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7659	/* 623 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7660	/* 625 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7660	/* 625 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7661	/* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7661	/* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7662	/* 629 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7662	/* 629 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7663	/* 631 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7663	/* 631 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7664	/* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7664	/* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7665	/* 635 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7665	/* 635 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7666	/* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7666	/* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7667	/* 643 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7667	/* 643 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7668	/* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7668	/* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7669	/* 650 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7669	/* 650 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7670	/* 653 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7670	/* 653 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7671	/* 656 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7671	/* 656 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7672	/* 659 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7672	/* 659 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7673	/* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7673	/* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7674	/* 665 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7674	/* 665 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7675	/* 668 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7675	/* 668 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7676	/* 670 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7676	/* 670 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7677	/* 672 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7677	/* 672 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7678	/* 674 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7678	/* 674 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7679	/* 676 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7679	/* 676 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7680	/* 679 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7680	/* 679 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7681	/* 682 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7681	/* 682 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7682	/* 685 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7682	/* 685 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7683	/* 688 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7683	/* 688 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7684	/* 691 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7684	/* 691 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7685	/* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7685	/* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7686	/* 700 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7686	/* 700 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7687	/* 703 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7687	/* 703 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7688	/* 705 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7688	/* 705 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7689	/* 708 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7689	/* 708 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7690	/* 711 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7690	/* 711 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7691	/* 714 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7691	/* 714 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7692	/* 717 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7692	/* 717 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7693	/* 720 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7693	/* 720 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7694	/* 723 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7694	/* 723 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7695	/* 727 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7695	/* 727 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7696	/* 731 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7696	/* 731 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7697	/* 735 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7697	/* 735 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7698	/* 739 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7698	/* 739 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7699	/* 742 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7699	/* 742 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7700	/* 744 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7700	/* 744 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7701	/* 747 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7701	/* 747 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7702	/* 750 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7702	/* 750 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7703	/* 752 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7703	/* 752 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7704	/* 755 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7704	/* 755 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7705	/* 758 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7705	/* 758 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7706	/* 761 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7706	/* 761 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7707	/* 764 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7707	/* 764 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7708	/* 767 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7708	/* 767 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7709	/* 770 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7709	/* 770 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7710	/* 773 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7710	/* 773 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7711	/* 775 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7711	/* 775 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7712	/* 777 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7712	/* 777 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7713	/* 779 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7713	/* 779 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7714	/* 781 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7714	/* 781 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7715	/* 783 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7715	/* 783 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7716	/* 785 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7716	/* 785 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7717	/* 790 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7717	/* 790 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7718	/* 794 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7718	/* 794 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7719	/* 798 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7719	/* 798 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7720	/* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7720	/* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7721	/* 806 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7721	/* 806 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7722	/* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7722	/* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7723	/* 814 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7723	/* 814 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7724	/* 819 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7724	/* 819 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7725	/* 824 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7725	/* 824 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7726	/* 829 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7726	/* 829 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7727	/* 830 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	7727	/* 830 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<
7728	/* 833 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7728	/* 833 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7729	/* 836 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7729	/* 836 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7730	/* 839 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7730	/* 839 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7731	/* 842 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },	7731	/* 842 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7732	/* 845 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7732	/* 845 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7733	/* 848 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7733	/* 848 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7734	/* 850 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7734	/* 850 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7735	/* 852 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7735	/* 852 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7736	/* 854 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7736	/* 854 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7737	/* 856 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7737	/* 856 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7738	/* 860 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7738	/* 860 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7739	/* 863 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7739	/* 863 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7740	/* 866 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7740	/* 866 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7741	/* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7741	/* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7742	/* 872 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7742	/* 872 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7743	/* 875 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7743	/* 875 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7744	/* 878 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7744	/* 878 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7745	/* 881 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7745	/* 881 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7746	/* 884 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7746	/* 884 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7747	/* 887 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7747	/* 887 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7748	/* 890 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0\|(1<	7748	/* 890 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0\|(1<
7749	/* 893 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7749	/* 893 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7750	/* 897 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0\|(1<	7750	/* 897 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0\|(1<
7751	/* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7751	/* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7752	/* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0\|(1<	7752	/* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0\|(1<
7753	/* 907 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	7753	/* 907 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<
7754	/* 910 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7754	/* 910 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7755	/* 913 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	7755	/* 913 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7756	/* 916 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7756	/* 916 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7757	/* 920 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7757	/* 920 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7758	/* 924 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7758	/* 924 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7759	/* 928 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7759	/* 928 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7760	/* 932 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7760	/* 932 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7761	/* 936 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7761	/* 936 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7762	/* 938 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7762	/* 938 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7763	/* 941 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7763	/* 941 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7764	/* 943 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7764	/* 943 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7765	/* 948 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7765	/* 948 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7766	/* 952 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7766	/* 952 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7767	/* 954 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7767	/* 954 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7768	/* 958 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7768	/* 958 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7769	/* 962 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7769	/* 962 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7770	/* 966 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7770	/* 966 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7771	/* 970 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7771	/* 970 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7772	/* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7772	/* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7773	/* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7773	/* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7774	/* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7774	/* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7775	/* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7775	/* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7776	/* 990 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7776	/* 990 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7777	/* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7777	/* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7778	/* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7778	/* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7779	/* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7779	/* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7780	/* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7780	/* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7781	/* 1010 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7781	/* 1010 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7782	/* 1013 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7782	/* 1013 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7783	/* 1016 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7783	/* 1016 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7784	/* 1019 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7784	/* 1019 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7785	/* 1021 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7785	/* 1021 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7786	/* 1024 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7786	/* 1024 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7787	/* 1026 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7787	/* 1026 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7788	/* 1028 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7788	/* 1028 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7789	/* 1030 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7789	/* 1030 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7790	/* 1032 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7790	/* 1032 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7791	/* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7791	/* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7792	/* 1036 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7792	/* 1036 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7793	/* 1039 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7793	/* 1039 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7794	/* 1043 */ { 0, 0\|(1<	7794	/* 1043 */ { 0, 0\|(1<
7795	/* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7795	/* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7796	/* 1049 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7796	/* 1049 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7797	/* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7797	/* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7798	/* 1054 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7798	/* 1054 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7799	/* 1056 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	7799	/* 1056 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<
7800	/* 1059 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	7800	/* 1059 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<
7801	/* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	7801	/* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<
7802	/* 1067 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	7802	/* 1067 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<
7803	/* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	7803	/* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<
7804	/* 1075 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7804	/* 1075 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7805	/* 1079 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7805	/* 1079 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7806	/* 1082 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7806	/* 1082 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7807	/* 1085 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7807	/* 1085 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7808	/* 1088 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7808	/* 1088 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7809	/* 1092 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7809	/* 1092 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7810	/* 1096 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7810	/* 1096 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7811	/* 1100 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7811	/* 1100 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7812	/* 1104 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7812	/* 1104 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7813	/* 1107 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	7813	/* 1107 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7814	/* 1110 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7814	/* 1110 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7815	/* 1113 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7815	/* 1113 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7816	/* 1116 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7816	/* 1116 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7817	/* 1119 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	7817	/* 1119 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7818	/* 1122 */ { 0, 0\|(1<	7818	/* 1122 */ { 0, 0\|(1<
7819	/* 1124 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	7819	/* 1124 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7820	}, {	7820	}, {
7821	/* 0 */	7821	/* 0 */
7822	/* 0 */ Mips::SP, Mips::SP,	7822	/* 0 */ Mips::SP, Mips::SP,
7823	/* 2 */ Mips::AT,	7823	/* 2 */ Mips::AT,
7824	/* 3 */ Mips::RA,	7824	/* 3 */ Mips::RA,
7825	/* 4 */ Mips::DSPPos,	7825	/* 4 */ Mips::DSPPos,
7826	/* 5 */ Mips::V0, Mips::V1,	7826	/* 5 */ Mips::V0, Mips::V1,
7827	/* 7 */ Mips::HI0, Mips::LO0,	7827	/* 7 */ Mips::HI0, Mips::LO0,
7828	/* 9 */ Mips::T8,	7828	/* 9 */ Mips::T8,
7829	/* 10 */ Mips::DSPOutFlag20,	7829	/* 10 */ Mips::DSPOutFlag20,
7830	/* 11 */ Mips::DSPCarry,	7830	/* 11 */ Mips::DSPCarry,
7831	/* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,	7831	/* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,
7832	/* 14 */ Mips::DSPCCond,	7832	/* 14 */ Mips::DSPCCond,
7833	/* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,	7833	/* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,
7834	/* 20 */ Mips::HI0_64, Mips::LO0_64,	7834	/* 20 */ Mips::HI0_64, Mips::LO0_64,
7835	/* 22 */ Mips::DSPOutFlag16_19,	7835	/* 22 */ Mips::DSPOutFlag16_19,
7836	/* 23 */ Mips::DSPPos, Mips::DSPEFI,	7836	/* 23 */ Mips::DSPPos, Mips::DSPEFI,
7837	/* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,	7837	/* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,
7838	/* 28 */ Mips::DSPOutFlag23,	7838	/* 28 */ Mips::DSPOutFlag23,
7839	/* 29 */ Mips::FCC0,	7839	/* 29 */ Mips::FCC0,
7840	/* 30 */ Mips::DSPPos, Mips::DSPSCount,	7840	/* 30 */ Mips::DSPPos, Mips::DSPSCount,
7841	/* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,	7841	/* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,
7842	/* 36 */ Mips::AC0,	7842	/* 36 */ Mips::AC0,
7843	/* 37 */ Mips::AC0_64,	7843	/* 37 */ Mips::AC0_64,
7844	/* 38 */ Mips::HI0,	7844	/* 38 */ Mips::HI0,
7845	/* 39 */ Mips::HI0_64,	7845	/* 39 */ Mips::HI0_64,
7846	/* 40 */ Mips::LO0,	7846	/* 40 */ Mips::LO0,
7847	/* 41 */ Mips::LO0_64,	7847	/* 41 */ Mips::LO0_64,
7848	/* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,	7848	/* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,
7849	/* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,	7849	/* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,
7850	/* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	7850	/* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7851	/* 54 */ Mips::P0,	7851	/* 54 */ Mips::P0,
7852	/* 55 */ Mips::P1,	7852	/* 55 */ Mips::P1,
7853	/* 56 */ Mips::P2,	7853	/* 56 */ Mips::P2,
7854	/* 57 */ Mips::DSPOutFlag21,	7854	/* 57 */ Mips::DSPOutFlag21,
7855	/* 58 */ Mips::DSPOutFlag22,	7855	/* 58 */ Mips::DSPOutFlag22,
7856	/* 59 */ Mips::P0, Mips::P1, Mips::P2,	7856	/* 59 */ Mips::P0, Mips::P1, Mips::P2,
7857	/* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	7857	/* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7858	}	7858	}
7859	};	7859	};
7860		7860
7861		7861
7862	#ifdef __GNUC__	7862	#ifdef __GNUC__
7863	#pragma GCC diagnostic push	7863	#pragma GCC diagnostic push
7864	#pragma GCC diagnostic ignored "-Woverlength-strings"	7864	#pragma GCC diagnostic ignored "-Woverlength-strings"
7865	#endif	7865	#endif
7866	extern const char MipsInstrNameData[] = {	7866	extern const char MipsInstrNameData[] = {
7867	/* 0 */ "G_FLOG10\0"	7867	/* 0 */ "G_FLOG10\0"
7868	/* 9 */ "DMFC0\0"	7868	/* 9 */ "DMFC0\0"
7869	/* 15 */ "DMFGC0\0"	7869	/* 15 */ "DMFGC0\0"
7870	/* 22 */ "MFHGC0\0"	7870	/* 22 */ "MFHGC0\0"
7871	/* 29 */ "MTHGC0\0"	7871	/* 29 */ "MTHGC0\0"
7872	/* 36 */ "DMTGC0\0"	7872	/* 36 */ "DMTGC0\0"
7873	/* 43 */ "MFTC0\0"	7873	/* 43 */ "MFTC0\0"
7874	/* 49 */ "DMTC0\0"	7874	/* 49 */ "DMTC0\0"
7875	/* 55 */ "MTTC0\0"	7875	/* 55 */ "MTTC0\0"
7876	/* 61 */ "VMM0\0"	7876	/* 61 */ "VMM0\0"
7877	/* 66 */ "MTM0\0"	7877	/* 66 */ "MTM0\0"
7878	/* 71 */ "MTP0\0"	7878	/* 71 */ "MTP0\0"
7879	/* 76 */ "BBIT0\0"	7879	/* 76 */ "BBIT0\0"
7880	/* 82 */ "LDC1\0"	7880	/* 82 */ "LDC1\0"
7881	/* 87 */ "SDC1\0"	7881	/* 87 */ "SDC1\0"
7882	/* 92 */ "CFC1\0"	7882	/* 92 */ "CFC1\0"
7883	/* 97 */ "DMFC1\0"	7883	/* 97 */ "DMFC1\0"
7884	/* 103 */ "MFTHC1\0"	7884	/* 103 */ "MFTHC1\0"
7885	/* 110 */ "MTTHC1\0"	7885	/* 110 */ "MTTHC1\0"
7886	/* 117 */ "CTC1\0"	7886	/* 117 */ "CTC1\0"
7887	/* 122 */ "CFTC1\0"	7887	/* 122 */ "CFTC1\0"
7888	/* 128 */ "MFTC1\0"	7888	/* 128 */ "MFTC1\0"
7889	/* 134 */ "DMTC1\0"	7889	/* 134 */ "DMTC1\0"
7890	/* 140 */ "CTTC1\0"	7890	/* 140 */ "CTTC1\0"
7891	/* 146 */ "MTTC1\0"	7891	/* 146 */ "MTTC1\0"
7892	/* 152 */ "LWC1\0"	7892	/* 152 */ "LWC1\0"
7893	/* 157 */ "SWC1\0"	7893	/* 157 */ "SWC1\0"
7894	/* 162 */ "LDXC1\0"	7894	/* 162 */ "LDXC1\0"
7895	/* 168 */ "SDXC1\0"	7895	/* 168 */ "SDXC1\0"
7896	/* 174 */ "LUXC1\0"	7896	/* 174 */ "LUXC1\0"
7897	/* 180 */ "SUXC1\0"	7897	/* 180 */ "SUXC1\0"
7898	/* 186 */ "LWXC1\0"	7898	/* 186 */ "LWXC1\0"
7899	/* 192 */ "SWXC1\0"	7899	/* 192 */ "SWXC1\0"
7900	/* 198 */ "MTM1\0"	7900	/* 198 */ "MTM1\0"
7901	/* 203 */ "SDC1_M1\0"	7901	/* 203 */ "SDC1_M1\0"
7902	/* 211 */ "MTP1\0"	7902	/* 211 */ "MTP1\0"
7903	/* 216 */ "BBIT1\0"	7903	/* 216 */ "BBIT1\0"
7904	/* 222 */ "BBIT032\0"	7904	/* 222 */ "BBIT032\0"
7905	/* 230 */ "BBIT132\0"	7905	/* 230 */ "BBIT132\0"
7906	/* 238 */ "DSRA32\0"	7906	/* 238 */ "DSRA32\0"
7907	/* 245 */ "MFHC1_D32\0"	7907	/* 245 */ "MFHC1_D32\0"
7908	/* 255 */ "MTHC1_D32\0"	7908	/* 255 */ "MTHC1_D32\0"
7909	/* 265 */ "FSUB_D32\0"	7909	/* 265 */ "FSUB_D32\0"
7910	/* 274 */ "NMSUB_D32\0"	7910	/* 274 */ "NMSUB_D32\0"
7911	/* 284 */ "FADD_D32\0"	7911	/* 284 */ "FADD_D32\0"
7912	/* 293 */ "NMADD_D32\0"	7912	/* 293 */ "NMADD_D32\0"
7913	/* 303 */ "C_NGE_D32\0"	7913	/* 303 */ "C_NGE_D32\0"
7914	/* 313 */ "C_NGLE_D32\0"	7914	/* 313 */ "C_NGLE_D32\0"
7915	/* 324 */ "C_OLE_D32\0"	7915	/* 324 */ "C_OLE_D32\0"
7916	/* 334 */ "C_ULE_D32\0"	7916	/* 334 */ "C_ULE_D32\0"
7917	/* 344 */ "C_LE_D32\0"	7917	/* 344 */ "C_LE_D32\0"
7918	/* 353 */ "C_SF_D32\0"	7918	/* 353 */ "C_SF_D32\0"
7919	/* 362 */ "MOVF_D32\0"	7919	/* 362 */ "MOVF_D32\0"
7920	/* 371 */ "C_F_D32\0"	7920	/* 371 */ "C_F_D32\0"
7921	/* 379 */ "PseudoSELECTFP_F_D32\0"	7921	/* 379 */ "PseudoSELECTFP_F_D32\0"
7922	/* 400 */ "FNEG_D32\0"	7922	/* 400 */ "FNEG_D32\0"
7923	/* 409 */ "MOVN_I_D32\0"	7923	/* 409 */ "MOVN_I_D32\0"
7924	/* 420 */ "MOVZ_I_D32\0"	7924	/* 420 */ "MOVZ_I_D32\0"
7925	/* 431 */ "C_NGL_D32\0"	7925	/* 431 */ "C_NGL_D32\0"
7926	/* 441 */ "FMUL_D32\0"	7926	/* 441 */ "FMUL_D32\0"
7927	/* 450 */ "LDC1_MM_D32\0"	7927	/* 450 */ "LDC1_MM_D32\0"
7928	/* 462 */ "SDC1_MM_D32\0"	7928	/* 462 */ "SDC1_MM_D32\0"
7929	/* 474 */ "C_UN_D32\0"	7929	/* 474 */ "C_UN_D32\0"
7930	/* 483 */ "RECIP_D32\0"	7930	/* 483 */ "RECIP_D32\0"
7931	/* 493 */ "FCMP_D32\0"	7931	/* 493 */ "FCMP_D32\0"
7932	/* 502 */ "C_SEQ_D32\0"	7932	/* 502 */ "C_SEQ_D32\0"
7933	/* 512 */ "C_UEQ_D32\0"	7933	/* 512 */ "C_UEQ_D32\0"
7934	/* 522 */ "C_EQ_D32\0"	7934	/* 522 */ "C_EQ_D32\0"
7935	/* 531 */ "FABS_D32\0"	7935	/* 531 */ "FABS_D32\0"
7936	/* 540 */ "CVT_S_D32\0"	7936	/* 540 */ "CVT_S_D32\0"
7937	/* 550 */ "PseudoSELECT_D32\0"	7937	/* 550 */ "PseudoSELECT_D32\0"
7938	/* 567 */ "C_NGT_D32\0"	7938	/* 567 */ "C_NGT_D32\0"
7939	/* 577 */ "C_OLT_D32\0"	7939	/* 577 */ "C_OLT_D32\0"
7940	/* 587 */ "C_ULT_D32\0"	7940	/* 587 */ "C_ULT_D32\0"
7941	/* 597 */ "C_LT_D32\0"	7941	/* 597 */ "C_LT_D32\0"
7942	/* 606 */ "FSQRT_D32\0"	7942	/* 606 */ "FSQRT_D32\0"
7943	/* 616 */ "RSQRT_D32\0"	7943	/* 616 */ "RSQRT_D32\0"
7944	/* 626 */ "MOVT_D32\0"	7944	/* 626 */ "MOVT_D32\0"
7945	/* 635 */ "PseudoSELECTFP_T_D32\0"	7945	/* 635 */ "PseudoSELECTFP_T_D32\0"
7946	/* 656 */ "FDIV_D32\0"	7946	/* 656 */ "FDIV_D32\0"
7947	/* 665 */ "FMOV_D32\0"	7947	/* 665 */ "FMOV_D32\0"
7948	/* 674 */ "PseudoTRUNC_W_D32\0"	7948	/* 674 */ "PseudoTRUNC_W_D32\0"
7949	/* 692 */ "ROUND_W_D32\0"	7949	/* 692 */ "ROUND_W_D32\0"
7950	/* 704 */ "CEIL_W_D32\0"	7950	/* 704 */ "CEIL_W_D32\0"
7951	/* 715 */ "FLOOR_W_D32\0"	7951	/* 715 */ "FLOOR_W_D32\0"
7952	/* 727 */ "CVT_W_D32\0"	7952	/* 727 */ "CVT_W_D32\0"
7953	/* 737 */ "BPOSGE32\0"	7953	/* 737 */ "BPOSGE32\0"
7954	/* 746 */ "ATOMIC_LOAD_SUB_I32\0"	7954	/* 746 */ "ATOMIC_LOAD_SUB_I32\0"
7955	/* 766 */ "ATOMIC_LOAD_ADD_I32\0"	7955	/* 766 */ "ATOMIC_LOAD_ADD_I32\0"
7956	/* 786 */ "ATOMIC_LOAD_NAND_I32\0"	7956	/* 786 */ "ATOMIC_LOAD_NAND_I32\0"
7957	/* 807 */ "ATOMIC_LOAD_AND_I32\0"	7957	/* 807 */ "ATOMIC_LOAD_AND_I32\0"
7958	/* 827 */ "ATOMIC_LOAD_UMIN_I32\0"	7958	/* 827 */ "ATOMIC_LOAD_UMIN_I32\0"
7959	/* 848 */ "ATOMIC_LOAD_MIN_I32\0"	7959	/* 848 */ "ATOMIC_LOAD_MIN_I32\0"
7960	/* 868 */ "ATOMIC_SWAP_I32\0"	7960	/* 868 */ "ATOMIC_SWAP_I32\0"
7961	/* 884 */ "ATOMIC_CMP_SWAP_I32\0"	7961	/* 884 */ "ATOMIC_CMP_SWAP_I32\0"
7962	/* 904 */ "ATOMIC_LOAD_XOR_I32\0"	7962	/* 904 */ "ATOMIC_LOAD_XOR_I32\0"
7963	/* 924 */ "ATOMIC_LOAD_OR_I32\0"	7963	/* 924 */ "ATOMIC_LOAD_OR_I32\0"
7964	/* 943 */ "ATOMIC_LOAD_UMAX_I32\0"	7964	/* 943 */ "ATOMIC_LOAD_UMAX_I32\0"
7965	/* 964 */ "ATOMIC_LOAD_MAX_I32\0"	7965	/* 964 */ "ATOMIC_LOAD_MAX_I32\0"
7966	/* 984 */ "DSLL32\0"	7966	/* 984 */ "DSLL32\0"
7967	/* 991 */ "DSRL32\0"	7967	/* 991 */ "DSRL32\0"
7968	/* 998 */ "DROTR32\0"	7968	/* 998 */ "DROTR32\0"
7969	/* 1006 */ "CINS32\0"	7969	/* 1006 */ "CINS32\0"
7970	/* 1013 */ "EXTS32\0"	7970	/* 1013 */ "EXTS32\0"
7971	/* 1020 */ "FCMP_S32\0"	7971	/* 1020 */ "FCMP_S32\0"
7972	/* 1029 */ "DSLL64_32\0"	7972	/* 1029 */ "DSLL64_32\0"
7973	/* 1039 */ "CINS64_32\0"	7973	/* 1039 */ "CINS64_32\0"
7974	/* 1049 */ "DEXT64_32\0"	7974	/* 1049 */ "DEXT64_32\0"
7975	/* 1059 */ "LoadImmDoubleFGR_32\0"	7975	/* 1059 */ "LoadImmDoubleFGR_32\0"
7976	/* 1079 */ "LoadAddrReg32\0"	7976	/* 1079 */ "LoadAddrReg32\0"
7977	/* 1093 */ "CINS_i32\0"	7977	/* 1093 */ "CINS_i32\0"
7978	/* 1102 */ "LoadImm32\0"	7978	/* 1102 */ "LoadImm32\0"
7979	/* 1112 */ "LoadAddrImm32\0"	7979	/* 1112 */ "LoadAddrImm32\0"
7980	/* 1126 */ "MIPSeh_return32\0"	7980	/* 1126 */ "MIPSeh_return32\0"
7981	/* 1142 */ "LwConstant32\0"	7981	/* 1142 */ "LwConstant32\0"
7982	/* 1155 */ "LDC2\0"	7982	/* 1155 */ "LDC2\0"
7983	/* 1160 */ "SDC2\0"	7983	/* 1160 */ "SDC2\0"
7984	/* 1165 */ "DMFC2\0"	7984	/* 1165 */ "DMFC2\0"
7985	/* 1171 */ "DMTC2\0"	7985	/* 1171 */ "DMTC2\0"
7986	/* 1177 */ "LWC2\0"	7986	/* 1177 */ "LWC2\0"
7987	/* 1182 */ "SWC2\0"	7987	/* 1182 */ "SWC2\0"
7988	/* 1187 */ "G_FLOG2\0"	7988	/* 1187 */ "G_FLOG2\0"
7989	/* 1195 */ "MTM2\0"	7989	/* 1195 */ "MTM2\0"
7990	/* 1200 */ "MTP2\0"	7990	/* 1200 */ "MTP2\0"
7991	/* 1205 */ "G_FEXP2\0"	7991	/* 1205 */ "G_FEXP2\0"
7992	/* 1213 */ "SHRA_QB_MMR2\0"	7992	/* 1213 */ "SHRA_QB_MMR2\0"
7993	/* 1226 */ "CMPGDU_LE_QB_MMR2\0"	7993	/* 1226 */ "CMPGDU_LE_QB_MMR2\0"
7994	/* 1244 */ "SUBUH_QB_MMR2\0"	7994	/* 1244 */ "SUBUH_QB_MMR2\0"
7995	/* 1258 */ "ADDUH_QB_MMR2\0"	7995	/* 1258 */ "ADDUH_QB_MMR2\0"
7996	/* 1272 */ "CMPGDU_EQ_QB_MMR2\0"	7996	/* 1272 */ "CMPGDU_EQ_QB_MMR2\0"
7997	/* 1290 */ "SHRA_R_QB_MMR2\0"	7997	/* 1290 */ "SHRA_R_QB_MMR2\0"
7998	/* 1305 */ "SUBUH_R_QB_MMR2\0"	7998	/* 1305 */ "SUBUH_R_QB_MMR2\0"
7999	/* 1321 */ "ADDUH_R_QB_MMR2\0"	7999	/* 1321 */ "ADDUH_R_QB_MMR2\0"
8000	/* 1337 */ "SHRAV_R_QB_MMR2\0"	8000	/* 1337 */ "SHRAV_R_QB_MMR2\0"
8001	/* 1353 */ "ABSQ_S_QB_MMR2\0"	8001	/* 1353 */ "ABSQ_S_QB_MMR2\0"
8002	/* 1368 */ "CMPGDU_LT_QB_MMR2\0"	8002	/* 1368 */ "CMPGDU_LT_QB_MMR2\0"
8003	/* 1386 */ "SHRAV_QB_MMR2\0"	8003	/* 1386 */ "SHRAV_QB_MMR2\0"
8004	/* 1400 */ "PREPEND_MMR2\0"	8004	/* 1400 */ "PREPEND_MMR2\0"
8005	/* 1413 */ "APPEND_MMR2\0"	8005	/* 1413 */ "APPEND_MMR2\0"
8006	/* 1425 */ "PRECR_QB_PH_MMR2\0"	8006	/* 1425 */ "PRECR_QB_PH_MMR2\0"
8007	/* 1442 */ "SUBQH_PH_MMR2\0"	8007	/* 1442 */ "SUBQH_PH_MMR2\0"
8008	/* 1456 */ "ADDQH_PH_MMR2\0"	8008	/* 1456 */ "ADDQH_PH_MMR2\0"
8009	/* 1470 */ "SHRL_PH_MMR2\0"	8009	/* 1470 */ "SHRL_PH_MMR2\0"
8010	/* 1483 */ "MUL_PH_MMR2\0"	8010	/* 1483 */ "MUL_PH_MMR2\0"
8011	/* 1495 */ "SUBQH_R_PH_MMR2\0"	8011	/* 1495 */ "SUBQH_R_PH_MMR2\0"
8012	/* 1511 */ "ADDQH_R_PH_MMR2\0"	8012	/* 1511 */ "ADDQH_R_PH_MMR2\0"
8013	/* 1527 */ "MUL_S_PH_MMR2\0"	8013	/* 1527 */ "MUL_S_PH_MMR2\0"
8014	/* 1541 */ "MULQ_S_PH_MMR2\0"	8014	/* 1541 */ "MULQ_S_PH_MMR2\0"
8015	/* 1556 */ "SUBU_S_PH_MMR2\0"	8015	/* 1556 */ "SUBU_S_PH_MMR2\0"
8016	/* 1571 */ "ADDU_S_PH_MMR2\0"	8016	/* 1571 */ "ADDU_S_PH_MMR2\0"
8017	/* 1586 */ "SUBU_PH_MMR2\0"	8017	/* 1586 */ "SUBU_PH_MMR2\0"
8018	/* 1599 */ "ADDU_PH_MMR2\0"	8018	/* 1599 */ "ADDU_PH_MMR2\0"
8019	/* 1612 */ "SHRLV_PH_MMR2\0"	8019	/* 1612 */ "SHRLV_PH_MMR2\0"
8020	/* 1626 */ "DPA_W_PH_MMR2\0"	8020	/* 1626 */ "DPA_W_PH_MMR2\0"
8021	/* 1640 */ "MULSA_W_PH_MMR2\0"	8021	/* 1640 */ "MULSA_W_PH_MMR2\0"
8022	/* 1656 */ "DPAQX_SA_W_PH_MMR2\0"	8022	/* 1656 */ "DPAQX_SA_W_PH_MMR2\0"
8023	/* 1675 */ "DPSQX_SA_W_PH_MMR2\0"	8023	/* 1675 */ "DPSQX_SA_W_PH_MMR2\0"
8024	/* 1694 */ "DPS_W_PH_MMR2\0"	8024	/* 1694 */ "DPS_W_PH_MMR2\0"
8025	/* 1708 */ "DPAQX_S_W_PH_MMR2\0"	8025	/* 1708 */ "DPAQX_S_W_PH_MMR2\0"
8026	/* 1726 */ "DPSQX_S_W_PH_MMR2\0"	8026	/* 1726 */ "DPSQX_S_W_PH_MMR2\0"
8027	/* 1744 */ "DPAX_W_PH_MMR2\0"	8027	/* 1744 */ "DPAX_W_PH_MMR2\0"
8028	/* 1759 */ "DPSX_W_PH_MMR2\0"	8028	/* 1759 */ "DPSX_W_PH_MMR2\0"
8029	/* 1774 */ "BALIGN_MMR2\0"	8029	/* 1774 */ "BALIGN_MMR2\0"
8030	/* 1786 */ "PRECR_SRA_PH_W_MMR2\0"	8030	/* 1786 */ "PRECR_SRA_PH_W_MMR2\0"
8031	/* 1806 */ "PRECR_SRA_R_PH_W_MMR2\0"	8031	/* 1806 */ "PRECR_SRA_R_PH_W_MMR2\0"
8032	/* 1828 */ "SUBQH_W_MMR2\0"	8032	/* 1828 */ "SUBQH_W_MMR2\0"
8033	/* 1841 */ "ADDQH_W_MMR2\0"	8033	/* 1841 */ "ADDQH_W_MMR2\0"
8034	/* 1854 */ "SUBQH_R_W_MMR2\0"	8034	/* 1854 */ "SUBQH_R_W_MMR2\0"
8035	/* 1869 */ "ADDQH_R_W_MMR2\0"	8035	/* 1869 */ "ADDQH_R_W_MMR2\0"
8036	/* 1884 */ "MULQ_RS_W_MMR2\0"	8036	/* 1884 */ "MULQ_RS_W_MMR2\0"
8037	/* 1899 */ "MULQ_S_W_MMR2\0"	8037	/* 1899 */ "MULQ_S_W_MMR2\0"
8038	/* 1913 */ "LDC3\0"	8038	/* 1913 */ "LDC3\0"
8039	/* 1918 */ "SDC3\0"	8039	/* 1918 */ "SDC3\0"
8040	/* 1923 */ "LWC3\0"	8040	/* 1923 */ "LWC3\0"
8041	/* 1928 */ "SWC3\0"	8041	/* 1928 */ "SWC3\0"
8042	/* 1933 */ "BPOSGE32C_MMR3\0"	8042	/* 1933 */ "BPOSGE32C_MMR3\0"
8043	/* 1948 */ "LDC164\0"	8043	/* 1948 */ "LDC164\0"
8044	/* 1955 */ "SDC164\0"	8044	/* 1955 */ "SDC164\0"
8045	/* 1962 */ "LDXC164\0"	8045	/* 1962 */ "LDXC164\0"
8046	/* 1970 */ "SDXC164\0"	8046	/* 1970 */ "SDXC164\0"
8047	/* 1978 */ "LUXC164\0"	8047	/* 1978 */ "LUXC164\0"
8048	/* 1986 */ "SUXC164\0"	8048	/* 1986 */ "SUXC164\0"
8049	/* 1994 */ "SEB64\0"	8049	/* 1994 */ "SEB64\0"
8050	/* 2000 */ "TAILCALLREGHB64\0"	8050	/* 2000 */ "TAILCALLREGHB64\0"
8051	/* 2016 */ "JR_HB64\0"	8051	/* 2016 */ "JR_HB64\0"
8052	/* 2024 */ "JALR_HB64\0"	8052	/* 2024 */ "JALR_HB64\0"
8053	/* 2034 */ "LB64\0"	8053	/* 2034 */ "LB64\0"
8054	/* 2039 */ "SB64\0"	8054	/* 2039 */ "SB64\0"
8055	/* 2044 */ "LOAD_ACC64\0"	8055	/* 2044 */ "LOAD_ACC64\0"
8056	/* 2055 */ "STORE_ACC64\0"	8056	/* 2055 */ "STORE_ACC64\0"
8057	/* 2067 */ "BGEC64\0"	8057	/* 2067 */ "BGEC64\0"
8058	/* 2074 */ "BNEC64\0"	8058	/* 2074 */ "BNEC64\0"
8059	/* 2081 */ "JIC64\0"	8059	/* 2081 */ "JIC64\0"
8060	/* 2087 */ "JIALC64\0"	8060	/* 2087 */ "JIALC64\0"
8061	/* 2095 */ "BEQC64\0"	8061	/* 2095 */ "BEQC64\0"
8062	/* 2102 */ "SC64\0"	8062	/* 2102 */ "SC64\0"
8063	/* 2107 */ "BLTC64\0"	8063	/* 2107 */ "BLTC64\0"
8064	/* 2114 */ "BGEUC64\0"	8064	/* 2114 */ "BGEUC64\0"
8065	/* 2122 */ "BLTUC64\0"	8065	/* 2122 */ "BLTUC64\0"
8066	/* 2130 */ "BGEZC64\0"	8066	/* 2130 */ "BGEZC64\0"
8067	/* 2138 */ "BLEZC64\0"	8067	/* 2138 */ "BLEZC64\0"
8068	/* 2146 */ "BNEZC64\0"	8068	/* 2146 */ "BNEZC64\0"
8069	/* 2154 */ "BEQZC64\0"	8069	/* 2154 */ "BEQZC64\0"
8070	/* 2162 */ "BGTZC64\0"	8070	/* 2162 */ "BGTZC64\0"
8071	/* 2170 */ "BLTZC64\0"	8071	/* 2170 */ "BLTZC64\0"
8072	/* 2178 */ "AND64\0"	8072	/* 2178 */ "AND64\0"
8073	/* 2184 */ "MFC1_D64\0"	8073	/* 2184 */ "MFC1_D64\0"
8074	/* 2193 */ "MFHC1_D64\0"	8074	/* 2193 */ "MFHC1_D64\0"
8075	/* 2203 */ "MTHC1_D64\0"	8075	/* 2203 */ "MTHC1_D64\0"
8076	/* 2213 */ "MTC1_D64\0"	8076	/* 2213 */ "MTC1_D64\0"
8077	/* 2222 */ "MOVN_I64_D64\0"	8077	/* 2222 */ "MOVN_I64_D64\0"
8078	/* 2235 */ "MOVZ_I64_D64\0"	8078	/* 2235 */ "MOVZ_I64_D64\0"
8079	/* 2248 */ "FSUB_D64\0"	8079	/* 2248 */ "FSUB_D64\0"
8080	/* 2257 */ "NMSUB_D64\0"	8080	/* 2257 */ "NMSUB_D64\0"
8081	/* 2267 */ "FADD_D64\0"	8081	/* 2267 */ "FADD_D64\0"
8082	/* 2276 */ "NMADD_D64\0"	8082	/* 2276 */ "NMADD_D64\0"
8083	/* 2286 */ "C_NGE_D64\0"	8083	/* 2286 */ "C_NGE_D64\0"
8084	/* 2296 */ "C_NGLE_D64\0"	8084	/* 2296 */ "C_NGLE_D64\0"
8085	/* 2307 */ "C_OLE_D64\0"	8085	/* 2307 */ "C_OLE_D64\0"
8086	/* 2317 */ "C_ULE_D64\0"	8086	/* 2317 */ "C_ULE_D64\0"
8087	/* 2327 */ "C_LE_D64\0"	8087	/* 2327 */ "C_LE_D64\0"
8088	/* 2336 */ "C_SF_D64\0"	8088	/* 2336 */ "C_SF_D64\0"
8089	/* 2345 */ "MOVF_D64\0"	8089	/* 2345 */ "MOVF_D64\0"
8090	/* 2354 */ "C_F_D64\0"	8090	/* 2354 */ "C_F_D64\0"
8091	/* 2362 */ "PseudoSELECTFP_F_D64\0"	8091	/* 2362 */ "PseudoSELECTFP_F_D64\0"
8092	/* 2383 */ "FNEG_D64\0"	8092	/* 2383 */ "FNEG_D64\0"
8093	/* 2392 */ "MOVN_I_D64\0"	8093	/* 2392 */ "MOVN_I_D64\0"
8094	/* 2403 */ "MOVZ_I_D64\0"	8094	/* 2403 */ "MOVZ_I_D64\0"
8095	/* 2414 */ "C_NGL_D64\0"	8095	/* 2414 */ "C_NGL_D64\0"
8096	/* 2424 */ "FMUL_D64\0"	8096	/* 2424 */ "FMUL_D64\0"
8097	/* 2433 */ "TRUNC_L_D64\0"	8097	/* 2433 */ "TRUNC_L_D64\0"
8098	/* 2445 */ "ROUND_L_D64\0"	8098	/* 2445 */ "ROUND_L_D64\0"
8099	/* 2457 */ "CEIL_L_D64\0"	8099	/* 2457 */ "CEIL_L_D64\0"
8100	/* 2468 */ "FLOOR_L_D64\0"	8100	/* 2468 */ "FLOOR_L_D64\0"
8101	/* 2480 */ "CVT_L_D64\0"	8101	/* 2480 */ "CVT_L_D64\0"
8102	/* 2490 */ "LDC1_MM_D64\0"	8102	/* 2490 */ "LDC1_MM_D64\0"
8103	/* 2502 */ "SDC1_MM_D64\0"	8103	/* 2502 */ "SDC1_MM_D64\0"
8104	/* 2514 */ "C_UN_D64\0"	8104	/* 2514 */ "C_UN_D64\0"
8105	/* 2523 */ "RECIP_D64\0"	8105	/* 2523 */ "RECIP_D64\0"
8106	/* 2533 */ "FCMP_D64\0"	8106	/* 2533 */ "FCMP_D64\0"
8107	/* 2542 */ "C_SEQ_D64\0"	8107	/* 2542 */ "C_SEQ_D64\0"
8108	/* 2552 */ "C_UEQ_D64\0"	8108	/* 2552 */ "C_UEQ_D64\0"
8109	/* 2562 */ "C_EQ_D64\0"	8109	/* 2562 */ "C_EQ_D64\0"
8110	/* 2571 */ "FABS_D64\0"	8110	/* 2571 */ "FABS_D64\0"
8111	/* 2580 */ "CVT_S_D64\0"	8111	/* 2580 */ "CVT_S_D64\0"
8112	/* 2590 */ "PseudoSELECT_D64\0"	8112	/* 2590 */ "PseudoSELECT_D64\0"
8113	/* 2607 */ "C_NGT_D64\0"	8113	/* 2607 */ "C_NGT_D64\0"
8114	/* 2617 */ "C_OLT_D64\0"	8114	/* 2617 */ "C_OLT_D64\0"
8115	/* 2627 */ "C_ULT_D64\0"	8115	/* 2627 */ "C_ULT_D64\0"
8116	/* 2637 */ "C_LT_D64\0"	8116	/* 2637 */ "C_LT_D64\0"
8117	/* 2646 */ "FSQRT_D64\0"	8117	/* 2646 */ "FSQRT_D64\0"
8118	/* 2656 */ "RSQRT_D64\0"	8118	/* 2656 */ "RSQRT_D64\0"
8119	/* 2666 */ "MOVT_D64\0"	8119	/* 2666 */ "MOVT_D64\0"
8120	/* 2675 */ "PseudoSELECTFP_T_D64\0"	8120	/* 2675 */ "PseudoSELECTFP_T_D64\0"
8121	/* 2696 */ "FDIV_D64\0"	8121	/* 2696 */ "FDIV_D64\0"
8122	/* 2705 */ "FMOV_D64\0"	8122	/* 2705 */ "FMOV_D64\0"
8123	/* 2714 */ "TRUNC_W_D64\0"	8123	/* 2714 */ "TRUNC_W_D64\0"
8124	/* 2726 */ "ROUND_W_D64\0"	8124	/* 2726 */ "ROUND_W_D64\0"
8125	/* 2738 */ "CEIL_W_D64\0"	8125	/* 2738 */ "CEIL_W_D64\0"
8126	/* 2749 */ "FLOOR_W_D64\0"	8126	/* 2749 */ "FLOOR_W_D64\0"
8127	/* 2761 */ "CVT_W_D64\0"	8127	/* 2761 */ "CVT_W_D64\0"
8128	/* 2771 */ "BNE64\0"	8128	/* 2771 */ "BNE64\0"
8129	/* 2777 */ "BuildPairF64\0"	8129	/* 2777 */ "BuildPairF64\0"
8130	/* 2790 */ "ExtractElementF64\0"	8130	/* 2790 */ "ExtractElementF64\0"
8131	/* 2808 */ "TAILCALLREG64\0"	8131	/* 2808 */ "TAILCALLREG64\0"
8132	/* 2822 */ "SEH64\0"	8132	/* 2822 */ "SEH64\0"
8133	/* 2828 */ "LH64\0"	8133	/* 2828 */ "LH64\0"
8134	/* 2833 */ "SH64\0"	8134	/* 2833 */ "SH64\0"
8135	/* 2838 */ "PseudoMFHI64\0"	8135	/* 2838 */ "PseudoMFHI64\0"
8136	/* 2851 */ "PseudoMTLOHI64\0"	8136	/* 2851 */ "PseudoMTLOHI64\0"
8137	/* 2866 */ "MTHI64\0"	8137	/* 2866 */ "MTHI64\0"
8138	/* 2873 */ "MOVN_I64_I64\0"	8138	/* 2873 */ "MOVN_I64_I64\0"
8139	/* 2886 */ "MOVZ_I64_I64\0"	8139	/* 2886 */ "MOVZ_I64_I64\0"
8140	/* 2899 */ "ATOMIC_LOAD_SUB_I64\0"	8140	/* 2899 */ "ATOMIC_LOAD_SUB_I64\0"
8141	/* 2919 */ "ATOMIC_LOAD_ADD_I64\0"	8141	/* 2919 */ "ATOMIC_LOAD_ADD_I64\0"
8142	/* 2939 */ "ATOMIC_LOAD_NAND_I64\0"	8142	/* 2939 */ "ATOMIC_LOAD_NAND_I64\0"
8143	/* 2960 */ "ATOMIC_LOAD_AND_I64\0"	8143	/* 2960 */ "ATOMIC_LOAD_AND_I64\0"
8144	/* 2980 */ "MOVF_I64\0"	8144	/* 2980 */ "MOVF_I64\0"
8145	/* 2989 */ "PseudoSELECTFP_F_I64\0"	8145	/* 2989 */ "PseudoSELECTFP_F_I64\0"
8146	/* 3010 */ "MOVN_I_I64\0"	8146	/* 3010 */ "MOVN_I_I64\0"
8147	/* 3021 */ "MOVZ_I_I64\0"	8147	/* 3021 */ "MOVZ_I_I64\0"
8148	/* 3032 */ "ATOMIC_LOAD_UMIN_I64\0"	8148	/* 3032 */ "ATOMIC_LOAD_UMIN_I64\0"
8149	/* 3053 */ "ATOMIC_LOAD_MIN_I64\0"	8149	/* 3053 */ "ATOMIC_LOAD_MIN_I64\0"
8150	/* 3073 */ "ATOMIC_SWAP_I64\0"	8150	/* 3073 */ "ATOMIC_SWAP_I64\0"
8151	/* 3089 */ "ATOMIC_CMP_SWAP_I64\0"	8151	/* 3089 */ "ATOMIC_CMP_SWAP_I64\0"
8152	/* 3109 */ "ATOMIC_LOAD_XOR_I64\0"	8152	/* 3109 */ "ATOMIC_LOAD_XOR_I64\0"
8153	/* 3129 */ "ATOMIC_LOAD_OR_I64\0"	8153	/* 3129 */ "ATOMIC_LOAD_OR_I64\0"
8154	/* 3148 */ "PseudoD_SELECT_I64\0"	8154	/* 3148 */ "PseudoD_SELECT_I64\0"
8155	/* 3167 */ "PseudoSELECT_I64\0"	8155	/* 3167 */ "PseudoSELECT_I64\0"
8156	/* 3184 */ "MOVT_I64\0"	8156	/* 3184 */ "MOVT_I64\0"
8157	/* 3193 */ "PseudoSELECTFP_T_I64\0"	8157	/* 3193 */ "PseudoSELECTFP_T_I64\0"
8158	/* 3214 */ "ATOMIC_LOAD_UMAX_I64\0"	8158	/* 3214 */ "ATOMIC_LOAD_UMAX_I64\0"
8159	/* 3235 */ "ATOMIC_LOAD_MAX_I64\0"	8159	/* 3235 */ "ATOMIC_LOAD_MAX_I64\0"
8160	/* 3255 */ "LL64\0"	8160	/* 3255 */ "LL64\0"
8161	/* 3260 */ "CVT_S_PL64\0"	8161	/* 3260 */ "CVT_S_PL64\0"
8162	/* 3271 */ "LWL64\0"	8162	/* 3271 */ "LWL64\0"
8163	/* 3277 */ "SWL64\0"	8163	/* 3277 */ "SWL64\0"
8164	/* 3283 */ "PseudoMFLO64\0"	8164	/* 3283 */ "PseudoMFLO64\0"
8165	/* 3296 */ "MTLO64\0"	8165	/* 3296 */ "MTLO64\0"
8166	/* 3303 */ "BEQ64\0"	8166	/* 3303 */ "BEQ64\0"
8167	/* 3309 */ "JR64\0"	8167	/* 3309 */ "JR64\0"
8168	/* 3314 */ "JALR64\0"	8168	/* 3314 */ "JALR64\0"
8169	/* 3321 */ "NOR64\0"	8169	/* 3321 */ "NOR64\0"
8170	/* 3327 */ "XOR64\0"	8170	/* 3327 */ "XOR64\0"
8171	/* 3333 */ "RDHWR64\0"	8171	/* 3333 */ "RDHWR64\0"
8172	/* 3341 */ "LWR64\0"	8172	/* 3341 */ "LWR64\0"
8173	/* 3347 */ "SWR64\0"	8173	/* 3347 */ "SWR64\0"
8174	/* 3353 */ "FSUB_PS64\0"	8174	/* 3353 */ "FSUB_PS64\0"
8175	/* 3363 */ "FADD_PS64\0"	8175	/* 3363 */ "FADD_PS64\0"
8176	/* 3373 */ "PLL_PS64\0"	8176	/* 3373 */ "PLL_PS64\0"
8177	/* 3382 */ "FMUL_PS64\0"	8177	/* 3382 */ "FMUL_PS64\0"
8178	/* 3392 */ "PUL_PS64\0"	8178	/* 3392 */ "PUL_PS64\0"
8179	/* 3401 */ "ADDR_PS64\0"	8179	/* 3401 */ "ADDR_PS64\0"
8180	/* 3411 */ "MULR_PS64\0"	8180	/* 3411 */ "MULR_PS64\0"
8181	/* 3421 */ "PLU_PS64\0"	8181	/* 3421 */ "PLU_PS64\0"
8182	/* 3430 */ "PUU_PS64\0"	8182	/* 3430 */ "PUU_PS64\0"
8183	/* 3439 */ "CVT_PW_PS64\0"	8183	/* 3439 */ "CVT_PW_PS64\0"
8184	/* 3451 */ "CVT_PS_S64\0"	8184	/* 3451 */ "CVT_PS_S64\0"
8185	/* 3462 */ "SLT64\0"	8185	/* 3462 */ "SLT64\0"
8186	/* 3468 */ "CVT_S_PU64\0"	8186	/* 3468 */ "CVT_S_PU64\0"
8187	/* 3479 */ "LW64\0"	8187	/* 3479 */ "LW64\0"
8188	/* 3484 */ "CVT_PS_PW64\0"	8188	/* 3484 */ "CVT_PS_PW64\0"
8189	/* 3496 */ "SW64\0"	8189	/* 3496 */ "SW64\0"
8190	/* 3501 */ "BGEZ64\0"	8190	/* 3501 */ "BGEZ64\0"
8191	/* 3508 */ "BLEZ64\0"	8191	/* 3508 */ "BLEZ64\0"
8192	/* 3515 */ "SELNEZ64\0"	8192	/* 3515 */ "SELNEZ64\0"
8193	/* 3524 */ "SELEQZ64\0"	8193	/* 3524 */ "SELEQZ64\0"
8194	/* 3533 */ "BGTZ64\0"	8194	/* 3533 */ "BGTZ64\0"
8195	/* 3540 */ "BLTZ64\0"	8195	/* 3540 */ "BLTZ64\0"
8196	/* 3547 */ "BuildPairF64_64\0"	8196	/* 3547 */ "BuildPairF64_64\0"
8197	/* 3563 */ "ExtractElementF64_64\0"	8197	/* 3563 */ "ExtractElementF64_64\0"
8198	/* 3584 */ "SLL64_64\0"	8198	/* 3584 */ "SLL64_64\0"
8199	/* 3593 */ "LONG_BRANCH_LUi2Op_64\0"	8199	/* 3593 */ "LONG_BRANCH_LUi2Op_64\0"
8200	/* 3615 */ "LoadAddrReg64\0"	8200	/* 3615 */ "LoadAddrReg64\0"
8201	/* 3629 */ "PseudoIndirectHazardBranch64\0"	8201	/* 3629 */ "PseudoIndirectHazardBranch64\0"
8202	/* 3658 */ "PseudoIndirectBranch64\0"	8202	/* 3658 */ "PseudoIndirectBranch64\0"
8203	/* 3681 */ "ANDi64\0"	8203	/* 3681 */ "ANDi64\0"
8204	/* 3688 */ "XORi64\0"	8204	/* 3688 */ "XORi64\0"
8205	/* 3695 */ "SLTi64\0"	8205	/* 3695 */ "SLTi64\0"
8206	/* 3702 */ "LUi64\0"	8206	/* 3702 */ "LUi64\0"
8207	/* 3708 */ "SGEImm64\0"	8207	/* 3708 */ "SGEImm64\0"
8208	/* 3717 */ "SLEImm64\0"	8208	/* 3717 */ "SLEImm64\0"
8209	/* 3726 */ "NORImm64\0"	8209	/* 3726 */ "NORImm64\0"
8210	/* 3735 */ "SGTImm64\0"	8210	/* 3735 */ "SGTImm64\0"
8211	/* 3744 */ "SLTImm64\0"	8211	/* 3744 */ "SLTImm64\0"
8212	/* 3753 */ "SGEUImm64\0"	8212	/* 3753 */ "SGEUImm64\0"
8213	/* 3763 */ "SLEUImm64\0"	8213	/* 3763 */ "SLEUImm64\0"
8214	/* 3773 */ "SGTUImm64\0"	8214	/* 3773 */ "SGTUImm64\0"
8215	/* 3783 */ "SLTUImm64\0"	8215	/* 3783 */ "SLTUImm64\0"
8216	/* 3793 */ "LoadImm64\0"	8216	/* 3793 */ "LoadImm64\0"
8217	/* 3803 */ "LoadAddrImm64\0"	8217	/* 3803 */ "LoadAddrImm64\0"
8218	/* 3817 */ "PseudoReturn64\0"	8218	/* 3817 */ "PseudoReturn64\0"
8219	/* 3832 */ "MIPSeh_return64\0"	8219	/* 3832 */ "MIPSeh_return64\0"
8220	/* 3848 */ "LBu64\0"	8220	/* 3848 */ "LBu64\0"
8221	/* 3854 */ "LHu64\0"	8221	/* 3854 */ "LHu64\0"
8222	/* 3860 */ "SLTu64\0"	8222	/* 3860 */ "SLTu64\0"
8223	/* 3867 */ "LEA_ADDiu64\0"	8223	/* 3867 */ "LEA_ADDiu64\0"
8224	/* 3879 */ "SLTiu64\0"	8224	/* 3879 */ "SLTiu64\0"
8225	/* 3887 */ "MoveR3216\0"	8225	/* 3887 */ "MoveR3216\0"
8226	/* 3897 */ "RetRA16\0"	8226	/* 3897 */ "RetRA16\0"
8227	/* 3905 */ "JalB16\0"	8227	/* 3905 */ "JalB16\0"
8228	/* 3912 */ "LD_F16\0"	8228	/* 3912 */ "LD_F16\0"
8229	/* 3919 */ "ST_F16\0"	8229	/* 3919 */ "ST_F16\0"
8230	/* 3926 */ "ATOMIC_LOAD_SUB_I16\0"	8230	/* 3926 */ "ATOMIC_LOAD_SUB_I16\0"
8231	/* 3946 */ "ATOMIC_LOAD_ADD_I16\0"	8231	/* 3946 */ "ATOMIC_LOAD_ADD_I16\0"
8232	/* 3966 */ "ATOMIC_LOAD_NAND_I16\0"	8232	/* 3966 */ "ATOMIC_LOAD_NAND_I16\0"
8233	/* 3987 */ "ATOMIC_LOAD_AND_I16\0"	8233	/* 3987 */ "ATOMIC_LOAD_AND_I16\0"
8234	/* 4007 */ "ATOMIC_LOAD_UMIN_I16\0"	8234	/* 4007 */ "ATOMIC_LOAD_UMIN_I16\0"
8235	/* 4028 */ "ATOMIC_LOAD_MIN_I16\0"	8235	/* 4028 */ "ATOMIC_LOAD_MIN_I16\0"
8236	/* 4048 */ "ATOMIC_SWAP_I16\0"	8236	/* 4048 */ "ATOMIC_SWAP_I16\0"
8237	/* 4064 */ "ATOMIC_CMP_SWAP_I16\0"	8237	/* 4064 */ "ATOMIC_CMP_SWAP_I16\0"
8238	/* 4084 */ "ATOMIC_LOAD_XOR_I16\0"	8238	/* 4084 */ "ATOMIC_LOAD_XOR_I16\0"
8239	/* 4104 */ "ATOMIC_LOAD_OR_I16\0"	8239	/* 4104 */ "ATOMIC_LOAD_OR_I16\0"
8240	/* 4123 */ "ATOMIC_LOAD_UMAX_I16\0"	8240	/* 4123 */ "ATOMIC_LOAD_UMAX_I16\0"
8241	/* 4144 */ "ATOMIC_LOAD_MAX_I16\0"	8241	/* 4144 */ "ATOMIC_LOAD_MAX_I16\0"
8242	/* 4164 */ "Move32R16\0"	8242	/* 4164 */ "Move32R16\0"
8243	/* 4174 */ "SraX16\0"	8243	/* 4174 */ "SraX16\0"
8244	/* 4181 */ "RestoreX16\0"	8244	/* 4181 */ "RestoreX16\0"
8245	/* 4192 */ "SaveX16\0"	8245	/* 4192 */ "SaveX16\0"
8246	/* 4200 */ "BtnezT8CmpiX16\0"	8246	/* 4200 */ "BtnezT8CmpiX16\0"
8247	/* 4215 */ "BteqzT8CmpiX16\0"	8247	/* 4215 */ "BteqzT8CmpiX16\0"
8248	/* 4230 */ "BtnezT8SltiX16\0"	8248	/* 4230 */ "BtnezT8SltiX16\0"
8249	/* 4245 */ "BteqzT8SltiX16\0"	8249	/* 4245 */ "BteqzT8SltiX16\0"
8250	/* 4260 */ "SllX16\0"	8250	/* 4260 */ "SllX16\0"
8251	/* 4267 */ "SrlX16\0"	8251	/* 4267 */ "SrlX16\0"
8252	/* 4274 */ "LbRxRyOffMemX16\0"	8252	/* 4274 */ "LbRxRyOffMemX16\0"
8253	/* 4290 */ "SbRxRyOffMemX16\0"	8253	/* 4290 */ "SbRxRyOffMemX16\0"
8254	/* 4306 */ "LhRxRyOffMemX16\0"	8254	/* 4306 */ "LhRxRyOffMemX16\0"
8255	/* 4322 */ "ShRxRyOffMemX16\0"	8255	/* 4322 */ "ShRxRyOffMemX16\0"
8256	/* 4338 */ "LbuRxRyOffMemX16\0"	8256	/* 4338 */ "LbuRxRyOffMemX16\0"
8257	/* 4355 */ "LhuRxRyOffMemX16\0"	8257	/* 4355 */ "LhuRxRyOffMemX16\0"
8258	/* 4372 */ "AddiuRxRyOffMemX16\0"	8258	/* 4372 */ "AddiuRxRyOffMemX16\0"
8259	/* 4391 */ "LwRxRyOffMemX16\0"	8259	/* 4391 */ "LwRxRyOffMemX16\0"
8260	/* 4407 */ "SwRxRyOffMemX16\0"	8260	/* 4407 */ "SwRxRyOffMemX16\0"
8261	/* 4423 */ "AddiuRxPcImmX16\0"	8261	/* 4423 */ "AddiuRxPcImmX16\0"
8262	/* 4439 */ "AddiuSpImmX16\0"	8262	/* 4439 */ "AddiuSpImmX16\0"
8263	/* 4453 */ "LwRxSpImmX16\0"	8263	/* 4453 */ "LwRxSpImmX16\0"
8264	/* 4466 */ "SwRxSpImmX16\0"	8264	/* 4466 */ "SwRxSpImmX16\0"
8265	/* 4479 */ "SltiCCRxImmX16\0"	8265	/* 4479 */ "SltiCCRxImmX16\0"
8266	/* 4494 */ "SltiuCCRxImmX16\0"	8266	/* 4494 */ "SltiuCCRxImmX16\0"
8267	/* 4510 */ "LiRxImmX16\0"	8267	/* 4510 */ "LiRxImmX16\0"
8268	/* 4521 */ "CmpiRxImmX16\0"	8268	/* 4521 */ "CmpiRxImmX16\0"
8269	/* 4534 */ "SltiRxImmX16\0"	8269	/* 4534 */ "SltiRxImmX16\0"
8270	/* 4547 */ "AddiuRxImmX16\0"	8270	/* 4547 */ "AddiuRxImmX16\0"
8271	/* 4561 */ "SltiuRxImmX16\0"	8271	/* 4561 */ "SltiuRxImmX16\0"
8272	/* 4575 */ "AddiuRxRxImmX16\0"	8272	/* 4575 */ "AddiuRxRxImmX16\0"
8273	/* 4591 */ "BnezRxImmX16\0"	8273	/* 4591 */ "BnezRxImmX16\0"
8274	/* 4604 */ "BeqzRxImmX16\0"	8274	/* 4604 */ "BeqzRxImmX16\0"
8275	/* 4617 */ "BimmX16\0"	8275	/* 4617 */ "BimmX16\0"
8276	/* 4625 */ "LiRxImmAlignX16\0"	8276	/* 4625 */ "LiRxImmAlignX16\0"
8277	/* 4641 */ "LwRxPcTcpX16\0"	8277	/* 4641 */ "LwRxPcTcpX16\0"
8278	/* 4654 */ "BtnezT8CmpX16\0"	8278	/* 4654 */ "BtnezT8CmpX16\0"
8279	/* 4668 */ "BteqzT8CmpX16\0"	8279	/* 4668 */ "BteqzT8CmpX16\0"
8280	/* 4682 */ "BtnezT8SltX16\0"	8280	/* 4682 */ "BtnezT8SltX16\0"
8281	/* 4696 */ "BteqzT8SltX16\0"	8281	/* 4696 */ "BteqzT8SltX16\0"
8282	/* 4710 */ "BtnezT8SltiuX16\0"	8282	/* 4710 */ "BtnezT8SltiuX16\0"
8283	/* 4726 */ "BteqzT8SltiuX16\0"	8283	/* 4726 */ "BteqzT8SltiuX16\0"
8284	/* 4742 */ "BtnezT8SltuX16\0"	8284	/* 4742 */ "BtnezT8SltuX16\0"
8285	/* 4757 */ "BteqzT8SltuX16\0"	8285	/* 4757 */ "BteqzT8SltuX16\0"
8286	/* 4772 */ "BtnezX16\0"	8286	/* 4772 */ "BtnezX16\0"
8287	/* 4781 */ "BteqzX16\0"	8287	/* 4781 */ "BteqzX16\0"
8288	/* 4790 */ "JrcRa16\0"	8288	/* 4790 */ "JrcRa16\0"
8289	/* 4798 */ "JrRa16\0"	8289	/* 4798 */ "JrRa16\0"
8290	/* 4805 */ "Restore16\0"	8290	/* 4805 */ "Restore16\0"
8291	/* 4815 */ "GotPrologue16\0"	8291	/* 4815 */ "GotPrologue16\0"
8292	/* 4829 */ "Save16\0"	8292	/* 4829 */ "Save16\0"
8293	/* 4836 */ "JumpLinkReg16\0"	8293	/* 4836 */ "JumpLinkReg16\0"
8294	/* 4850 */ "Mfhi16\0"	8294	/* 4850 */ "Mfhi16\0"
8295	/* 4857 */ "Break16\0"	8295	/* 4857 */ "Break16\0"
8296	/* 4865 */ "Jal16\0"	8296	/* 4865 */ "Jal16\0"
8297	/* 4871 */ "AddiuSpImm16\0"	8297	/* 4871 */ "AddiuSpImm16\0"
8298	/* 4884 */ "LiRxImm16\0"	8298	/* 4884 */ "LiRxImm16\0"
8299	/* 4894 */ "CmpiRxImm16\0"	8299	/* 4894 */ "CmpiRxImm16\0"
8300	/* 4906 */ "SltiRxImm16\0"	8300	/* 4906 */ "SltiRxImm16\0"
8301	/* 4918 */ "SltiuRxImm16\0"	8301	/* 4918 */ "SltiuRxImm16\0"
8302	/* 4931 */ "AddiuRxRxImm16\0"	8302	/* 4931 */ "AddiuRxRxImm16\0"
8303	/* 4946 */ "BnezRxImm16\0"	8303	/* 4946 */ "BnezRxImm16\0"
8304	/* 4958 */ "BeqzRxImm16\0"	8304	/* 4958 */ "BeqzRxImm16\0"
8305	/* 4970 */ "Bimm16\0"	8305	/* 4970 */ "Bimm16\0"
8306	/* 4977 */ "Mflo16\0"	8306	/* 4977 */ "Mflo16\0"
8307	/* 4984 */ "LwRxPcTcp16\0"	8307	/* 4984 */ "LwRxPcTcp16\0"
8308	/* 4996 */ "SebRx16\0"	8308	/* 4996 */ "SebRx16\0"
8309	/* 5004 */ "JrcRx16\0"	8309	/* 5004 */ "JrcRx16\0"
8310	/* 5012 */ "SehRx16\0"	8310	/* 5012 */ "SehRx16\0"
8311	/* 5020 */ "SltCCRxRy16\0"	8311	/* 5020 */ "SltCCRxRy16\0"
8312	/* 5032 */ "SltuCCRxRy16\0"	8312	/* 5032 */ "SltuCCRxRy16\0"
8313	/* 5045 */ "NegRxRy16\0"	8313	/* 5045 */ "NegRxRy16\0"
8314	/* 5055 */ "CmpRxRy16\0"	8314	/* 5055 */ "CmpRxRy16\0"
8315	/* 5065 */ "SltRxRy16\0"	8315	/* 5065 */ "SltRxRy16\0"
8316	/* 5075 */ "MultRxRy16\0"	8316	/* 5075 */ "MultRxRy16\0"
8317	/* 5086 */ "NotRxRy16\0"	8317	/* 5086 */ "NotRxRy16\0"
8318	/* 5096 */ "SltuRxRy16\0"	8318	/* 5096 */ "SltuRxRy16\0"
8319	/* 5107 */ "MultuRxRy16\0"	8319	/* 5107 */ "MultuRxRy16\0"
8320	/* 5119 */ "DivuRxRy16\0"	8320	/* 5119 */ "DivuRxRy16\0"
8321	/* 5130 */ "SravRxRy16\0"	8321	/* 5130 */ "SravRxRy16\0"
8322	/* 5141 */ "DivRxRy16\0"	8322	/* 5141 */ "DivRxRy16\0"
8323	/* 5151 */ "SllvRxRy16\0"	8323	/* 5151 */ "SllvRxRy16\0"
8324	/* 5162 */ "SrlvRxRy16\0"	8324	/* 5162 */ "SrlvRxRy16\0"
8325	/* 5173 */ "AndRxRxRy16\0"	8325	/* 5173 */ "AndRxRxRy16\0"
8326	/* 5185 */ "OrRxRxRy16\0"	8326	/* 5185 */ "OrRxRxRy16\0"
8327	/* 5196 */ "XorRxRxRy16\0"	8327	/* 5196 */ "XorRxRxRy16\0"
8328	/* 5208 */ "MultRxRyRz16\0"	8328	/* 5208 */ "MultRxRyRz16\0"
8329	/* 5221 */ "SubuRxRyRz16\0"	8329	/* 5221 */ "SubuRxRyRz16\0"
8330	/* 5234 */ "AdduRxRyRz16\0"	8330	/* 5234 */ "AdduRxRyRz16\0"
8331	/* 5247 */ "SltuRxRyRz16\0"	8331	/* 5247 */ "SltuRxRyRz16\0"
8332	/* 5260 */ "MultuRxRyRz16\0"	8332	/* 5260 */ "MultuRxRyRz16\0"
8333	/* 5274 */ "Btnez16\0"	8333	/* 5274 */ "Btnez16\0"
8334	/* 5282 */ "Bteqz16\0"	8334	/* 5282 */ "Bteqz16\0"
8335	/* 5290 */ "PseudoIndrectHazardBranch64R6\0"	8335	/* 5290 */ "PseudoIndrectHazardBranch64R6\0"
8336	/* 5320 */ "PseudoIndirectBranch64R6\0"	8336	/* 5320 */ "PseudoIndirectBranch64R6\0"
8337	/* 5345 */ "MFC0_MMR6\0"	8337	/* 5345 */ "MFC0_MMR6\0"
8338	/* 5355 */ "MFHC0_MMR6\0"	8338	/* 5355 */ "MFHC0_MMR6\0"
8339	/* 5366 */ "MTHC0_MMR6\0"	8339	/* 5366 */ "MTHC0_MMR6\0"
8340	/* 5377 */ "MTC0_MMR6\0"	8340	/* 5377 */ "MTC0_MMR6\0"
8341	/* 5387 */ "MFC1_MMR6\0"	8341	/* 5387 */ "MFC1_MMR6\0"
8342	/* 5397 */ "MTC1_MMR6\0"	8342	/* 5397 */ "MTC1_MMR6\0"
8343	/* 5407 */ "LDC2_MMR6\0"	8343	/* 5407 */ "LDC2_MMR6\0"
8344	/* 5417 */ "SDC2_MMR6\0"	8344	/* 5417 */ "SDC2_MMR6\0"
8345	/* 5427 */ "MFC2_MMR6\0"	8345	/* 5427 */ "MFC2_MMR6\0"
8346	/* 5437 */ "MFHC2_MMR6\0"	8346	/* 5437 */ "MFHC2_MMR6\0"
8347	/* 5448 */ "MTHC2_MMR6\0"	8347	/* 5448 */ "MTHC2_MMR6\0"
8348	/* 5459 */ "MTC2_MMR6\0"	8348	/* 5459 */ "MTC2_MMR6\0"
8349	/* 5469 */ "LWC2_MMR6\0"	8349	/* 5469 */ "LWC2_MMR6\0"
8350	/* 5479 */ "SWC2_MMR6\0"	8350	/* 5479 */ "SWC2_MMR6\0"
8351	/* 5489 */ "LDC1_D64_MMR6\0"	8351	/* 5489 */ "LDC1_D64_MMR6\0"
8352	/* 5503 */ "SDC1_D64_MMR6\0"	8352	/* 5503 */ "SDC1_D64_MMR6\0"
8353	/* 5517 */ "SB16_MMR6\0"	8353	/* 5517 */ "SB16_MMR6\0"
8354	/* 5527 */ "BC16_MMR6\0"	8354	/* 5527 */ "BC16_MMR6\0"
8355	/* 5537 */ "JRC16_MMR6\0"	8355	/* 5537 */ "JRC16_MMR6\0"
8356	/* 5548 */ "JALRC16_MMR6\0"	8356	/* 5548 */ "JALRC16_MMR6\0"
8357	/* 5561 */ "BNEZC16_MMR6\0"	8357	/* 5561 */ "BNEZC16_MMR6\0"
8358	/* 5574 */ "BEQZC16_MMR6\0"	8358	/* 5574 */ "BEQZC16_MMR6\0"
8359	/* 5587 */ "AND16_MMR6\0"	8359	/* 5587 */ "AND16_MMR6\0"
8360	/* 5598 */ "MOVE16_MMR6\0"	8360	/* 5598 */ "MOVE16_MMR6\0"
8361	/* 5610 */ "SH16_MMR6\0"	8361	/* 5610 */ "SH16_MMR6\0"
8362	/* 5620 */ "ANDI16_MMR6\0"	8362	/* 5620 */ "ANDI16_MMR6\0"
8363	/* 5632 */ "LI16_MMR6\0"	8363	/* 5632 */ "LI16_MMR6\0"
8364	/* 5642 */ "BREAK16_MMR6\0"	8364	/* 5642 */ "BREAK16_MMR6\0"
8365	/* 5655 */ "SLL16_MMR6\0"	8365	/* 5655 */ "SLL16_MMR6\0"
8366	/* 5666 */ "SRL16_MMR6\0"	8366	/* 5666 */ "SRL16_MMR6\0"
8367	/* 5677 */ "LWM16_MMR6\0"	8367	/* 5677 */ "LWM16_MMR6\0"
8368	/* 5688 */ "SWM16_MMR6\0"	8368	/* 5688 */ "SWM16_MMR6\0"
8369	/* 5699 */ "SDBBP16_MMR6\0"	8369	/* 5699 */ "SDBBP16_MMR6\0"
8370	/* 5712 */ "XOR16_MMR6\0"	8370	/* 5712 */ "XOR16_MMR6\0"
8371	/* 5723 */ "NOT16_MMR6\0"	8371	/* 5723 */ "NOT16_MMR6\0"
8372	/* 5734 */ "SUBU16_MMR6\0"	8372	/* 5734 */ "SUBU16_MMR6\0"
8373	/* 5746 */ "ADDU16_MMR6\0"	8373	/* 5746 */ "ADDU16_MMR6\0"
8374	/* 5758 */ "SW16_MMR6\0"	8374	/* 5758 */ "SW16_MMR6\0"
8375	/* 5768 */ "LSA_MMR6\0"	8375	/* 5768 */ "LSA_MMR6\0"
8376	/* 5777 */ "EHB_MMR6\0"	8376	/* 5777 */ "EHB_MMR6\0"
8377	/* 5786 */ "JALRC_HB_MMR6\0"	8377	/* 5786 */ "JALRC_HB_MMR6\0"
8378	/* 5800 */ "LB_MMR6\0"	8378	/* 5800 */ "LB_MMR6\0"
8379	/* 5808 */ "SB_MMR6\0"	8379	/* 5808 */ "SB_MMR6\0"
8380	/* 5816 */ "SUB_MMR6\0"	8380	/* 5816 */ "SUB_MMR6\0"
8381	/* 5825 */ "BC_MMR6\0"	8381	/* 5825 */ "BC_MMR6\0"
8382	/* 5833 */ "BGEC_MMR6\0"	8382	/* 5833 */ "BGEC_MMR6\0"
8383	/* 5843 */ "BNEC_MMR6\0"	8383	/* 5843 */ "BNEC_MMR6\0"
8384	/* 5853 */ "JIC_MMR6\0"	8384	/* 5853 */ "JIC_MMR6\0"
8385	/* 5862 */ "BALC_MMR6\0"	8385	/* 5862 */ "BALC_MMR6\0"
8386	/* 5872 */ "JIALC_MMR6\0"	8386	/* 5872 */ "JIALC_MMR6\0"
8387	/* 5883 */ "BGEZALC_MMR6\0"	8387	/* 5883 */ "BGEZALC_MMR6\0"
8388	/* 5896 */ "BLEZALC_MMR6\0"	8388	/* 5896 */ "BLEZALC_MMR6\0"
8389	/* 5909 */ "BNEZALC_MMR6\0"	8389	/* 5909 */ "BNEZALC_MMR6\0"
8390	/* 5922 */ "BEQZALC_MMR6\0"	8390	/* 5922 */ "BEQZALC_MMR6\0"
8391	/* 5935 */ "BGTZALC_MMR6\0"	8391	/* 5935 */ "BGTZALC_MMR6\0"
8392	/* 5948 */ "BLTZALC_MMR6\0"	8392	/* 5948 */ "BLTZALC_MMR6\0"
8393	/* 5961 */ "ERETNC_MMR6\0"	8393	/* 5961 */ "ERETNC_MMR6\0"
8394	/* 5973 */ "SYNC_MMR6\0"	8394	/* 5973 */ "SYNC_MMR6\0"
8395	/* 5983 */ "AUIPC_MMR6\0"	8395	/* 5983 */ "AUIPC_MMR6\0"
8396	/* 5994 */ "ALUIPC_MMR6\0"	8396	/* 5994 */ "ALUIPC_MMR6\0"
8397	/* 6006 */ "ADDIUPC_MMR6\0"	8397	/* 6006 */ "ADDIUPC_MMR6\0"
8398	/* 6019 */ "LWPC_MMR6\0"	8398	/* 6019 */ "LWPC_MMR6\0"
8399	/* 6029 */ "BEQC_MMR6\0"	8399	/* 6029 */ "BEQC_MMR6\0"
8400	/* 6039 */ "JALRC_MMR6\0"	8400	/* 6039 */ "JALRC_MMR6\0"
8401	/* 6050 */ "SC_MMR6\0"	8401	/* 6050 */ "SC_MMR6\0"
8402	/* 6058 */ "BLTC_MMR6\0"	8402	/* 6058 */ "BLTC_MMR6\0"
8403	/* 6068 */ "BGEUC_MMR6\0"	8403	/* 6068 */ "BGEUC_MMR6\0"
8404	/* 6079 */ "BLTUC_MMR6\0"	8404	/* 6079 */ "BLTUC_MMR6\0"
8405	/* 6090 */ "BNVC_MMR6\0"	8405	/* 6090 */ "BNVC_MMR6\0"
8406	/* 6100 */ "BOVC_MMR6\0"	8406	/* 6100 */ "BOVC_MMR6\0"
8407	/* 6110 */ "BGEZC_MMR6\0"	8407	/* 6110 */ "BGEZC_MMR6\0"
8408	/* 6121 */ "BLEZC_MMR6\0"	8408	/* 6121 */ "BLEZC_MMR6\0"
8409	/* 6132 */ "BC1NEZC_MMR6\0"	8409	/* 6132 */ "BC1NEZC_MMR6\0"
8410	/* 6145 */ "BC2NEZC_MMR6\0"	8410	/* 6145 */ "BC2NEZC_MMR6\0"
8411	/* 6158 */ "BNEZC_MMR6\0"	8411	/* 6158 */ "BNEZC_MMR6\0"
8412	/* 6169 */ "BC1EQZC_MMR6\0"	8412	/* 6169 */ "BC1EQZC_MMR6\0"
8413	/* 6182 */ "BC2EQZC_MMR6\0"	8413	/* 6182 */ "BC2EQZC_MMR6\0"
8414	/* 6195 */ "BEQZC_MMR6\0"	8414	/* 6195 */ "BEQZC_MMR6\0"
8415	/* 6206 */ "BGTZC_MMR6\0"	8415	/* 6206 */ "BGTZC_MMR6\0"
8416	/* 6217 */ "BLTZC_MMR6\0"	8416	/* 6217 */ "BLTZC_MMR6\0"
8417	/* 6228 */ "ADD_MMR6\0"	8417	/* 6228 */ "ADD_MMR6\0"
8418	/* 6237 */ "AND_MMR6\0"	8418	/* 6237 */ "AND_MMR6\0"
8419	/* 6246 */ "MOD_MMR6\0"	8419	/* 6246 */ "MOD_MMR6\0"
8420	/* 6255 */ "MINA_D_MMR6\0"	8420	/* 6255 */ "MINA_D_MMR6\0"
8421	/* 6267 */ "MAXA_D_MMR6\0"	8421	/* 6267 */ "MAXA_D_MMR6\0"
8422	/* 6279 */ "CMP_SLE_D_MMR6\0"	8422	/* 6279 */ "CMP_SLE_D_MMR6\0"
8423	/* 6294 */ "CMP_SULE_D_MMR6\0"	8423	/* 6294 */ "CMP_SULE_D_MMR6\0"
8424	/* 6310 */ "CMP_ULE_D_MMR6\0"	8424	/* 6310 */ "CMP_ULE_D_MMR6\0"
8425	/* 6325 */ "CMP_LE_D_MMR6\0"	8425	/* 6325 */ "CMP_LE_D_MMR6\0"
8426	/* 6339 */ "CMP_SAF_D_MMR6\0"	8426	/* 6339 */ "CMP_SAF_D_MMR6\0"
8427	/* 6354 */ "CMP_AF_D_MMR6\0"	8427	/* 6354 */ "CMP_AF_D_MMR6\0"
8428	/* 6368 */ "MSUBF_D_MMR6\0"	8428	/* 6368 */ "MSUBF_D_MMR6\0"
8429	/* 6381 */ "MADDF_D_MMR6\0"	8429	/* 6381 */ "MADDF_D_MMR6\0"
8430	/* 6394 */ "SEL_D_MMR6\0"	8430	/* 6394 */ "SEL_D_MMR6\0"
8431	/* 6405 */ "TRUNC_L_D_MMR6\0"	8431	/* 6405 */ "TRUNC_L_D_MMR6\0"
8432	/* 6420 */ "ROUND_L_D_MMR6\0"	8432	/* 6420 */ "ROUND_L_D_MMR6\0"
8433	/* 6435 */ "CEIL_L_D_MMR6\0"	8433	/* 6435 */ "CEIL_L_D_MMR6\0"
8434	/* 6449 */ "FLOOR_L_D_MMR6\0"	8434	/* 6449 */ "FLOOR_L_D_MMR6\0"
8435	/* 6464 */ "CVT_L_D_MMR6\0"	8435	/* 6464 */ "CVT_L_D_MMR6\0"
8436	/* 6477 */ "MIN_D_MMR6\0"	8436	/* 6477 */ "MIN_D_MMR6\0"
8437	/* 6488 */ "CMP_SUN_D_MMR6\0"	8437	/* 6488 */ "CMP_SUN_D_MMR6\0"
8438	/* 6503 */ "CMP_UN_D_MMR6\0"	8438	/* 6503 */ "CMP_UN_D_MMR6\0"
8439	/* 6517 */ "CMP_SEQ_D_MMR6\0"	8439	/* 6517 */ "CMP_SEQ_D_MMR6\0"
8440	/* 6532 */ "CMP_SUEQ_D_MMR6\0"	8440	/* 6532 */ "CMP_SUEQ_D_MMR6\0"
8441	/* 6548 */ "CMP_UEQ_D_MMR6\0"	8441	/* 6548 */ "CMP_UEQ_D_MMR6\0"
8442	/* 6563 */ "CMP_EQ_D_MMR6\0"	8442	/* 6563 */ "CMP_EQ_D_MMR6\0"
8443	/* 6577 */ "CLASS_D_MMR6\0"	8443	/* 6577 */ "CLASS_D_MMR6\0"
8444	/* 6590 */ "CMP_SLT_D_MMR6\0"	8444	/* 6590 */ "CMP_SLT_D_MMR6\0"
8445	/* 6605 */ "CMP_SULT_D_MMR6\0"	8445	/* 6605 */ "CMP_SULT_D_MMR6\0"
8446	/* 6621 */ "CMP_ULT_D_MMR6\0"	8446	/* 6621 */ "CMP_ULT_D_MMR6\0"
8447	/* 6636 */ "CMP_LT_D_MMR6\0"	8447	/* 6636 */ "CMP_LT_D_MMR6\0"
8448	/* 6650 */ "RINT_D_MMR6\0"	8448	/* 6650 */ "RINT_D_MMR6\0"
8449	/* 6662 */ "FMOV_D_MMR6\0"	8449	/* 6662 */ "FMOV_D_MMR6\0"
8450	/* 6674 */ "TRUNC_W_D_MMR6\0"	8450	/* 6674 */ "TRUNC_W_D_MMR6\0"
8451	/* 6689 */ "ROUND_W_D_MMR6\0"	8451	/* 6689 */ "ROUND_W_D_MMR6\0"
8452	/* 6704 */ "CEIL_W_D_MMR6\0"	8452	/* 6704 */ "CEIL_W_D_MMR6\0"
8453	/* 6718 */ "FLOOR_W_D_MMR6\0"	8453	/* 6718 */ "FLOOR_W_D_MMR6\0"
8454	/* 6733 */ "MAX_D_MMR6\0"	8454	/* 6733 */ "MAX_D_MMR6\0"
8455	/* 6744 */ "SELNEZ_D_MMR6\0"	8455	/* 6744 */ "SELNEZ_D_MMR6\0"
8456	/* 6758 */ "SELEQZ_D_MMR6\0"	8456	/* 6758 */ "SELEQZ_D_MMR6\0"
8457	/* 6772 */ "CACHE_MMR6\0"	8457	/* 6772 */ "CACHE_MMR6\0"
8458	/* 6783 */ "SIGRIE_MMR6\0"	8458	/* 6783 */ "SIGRIE_MMR6\0"
8459	/* 6795 */ "PAUSE_MMR6\0"	8459	/* 6795 */ "PAUSE_MMR6\0"
8460	/* 6806 */ "PREF_MMR6\0"	8460	/* 6806 */ "PREF_MMR6\0"
8461	/* 6816 */ "TLBINVF_MMR6\0"	8461	/* 6816 */ "TLBINVF_MMR6\0"
8462	/* 6829 */ "TAILCALLREG_MMR6\0"	8462	/* 6829 */ "TAILCALLREG_MMR6\0"
8463	/* 6846 */ "WSBH_MMR6\0"	8463	/* 6846 */ "WSBH_MMR6\0"
8464	/* 6856 */ "SH_MMR6\0"	8464	/* 6856 */ "SH_MMR6\0"
8465	/* 6864 */ "MUH_MMR6\0"	8465	/* 6864 */ "MUH_MMR6\0"
8466	/* 6873 */ "SYNCI_MMR6\0"	8466	/* 6873 */ "SYNCI_MMR6\0"
8467	/* 6884 */ "ANDI_MMR6\0"	8467	/* 6884 */ "ANDI_MMR6\0"
8468	/* 6894 */ "EI_MMR6\0"	8468	/* 6894 */ "EI_MMR6\0"
8469	/* 6902 */ "XORI_MMR6\0"	8469	/* 6902 */ "XORI_MMR6\0"
8470	/* 6912 */ "AUI_MMR6\0"	8470	/* 6912 */ "AUI_MMR6\0"
8471	/* 6921 */ "LUI_MMR6\0"	8471	/* 6921 */ "LUI_MMR6\0"
8472	/* 6930 */ "GINVI_MMR6\0"	8472	/* 6930 */ "GINVI_MMR6\0"
8473	/* 6941 */ "BREAK_MMR6\0"	8473	/* 6941 */ "BREAK_MMR6\0"
8474	/* 6952 */ "JAL_MMR6\0"	8474	/* 6952 */ "JAL_MMR6\0"
8475	/* 6961 */ "TAILCALL_MMR6\0"	8475	/* 6961 */ "TAILCALL_MMR6\0"
8476	/* 6975 */ "SLL_MMR6\0"	8476	/* 6975 */ "SLL_MMR6\0"
8477	/* 6984 */ "MUL_MMR6\0"	8477	/* 6984 */ "MUL_MMR6\0"
8478	/* 6993 */ "CVT_D_L_MMR6\0"	8478	/* 6993 */ "CVT_D_L_MMR6\0"
8479	/* 7006 */ "CVT_S_L_MMR6\0"	8479	/* 7006 */ "CVT_S_L_MMR6\0"
8480	/* 7019 */ "ALIGN_MMR6\0"	8480	/* 7019 */ "ALIGN_MMR6\0"
8481	/* 7030 */ "CLO_MMR6\0"	8481	/* 7030 */ "CLO_MMR6\0"
8482	/* 7039 */ "BITSWAP_MMR6\0"	8482	/* 7039 */ "BITSWAP_MMR6\0"
8483	/* 7052 */ "SDBBP_MMR6\0"	8483	/* 7052 */ "SDBBP_MMR6\0"
8484	/* 7063 */ "MOVEP_MMR6\0"	8484	/* 7063 */ "MOVEP_MMR6\0"
8485	/* 7074 */ "SSNOP_MMR6\0"	8485	/* 7074 */ "SSNOP_MMR6\0"
8486	/* 7085 */ "JRCADDIUSP_MMR6\0"	8486	/* 7085 */ "JRCADDIUSP_MMR6\0"
8487	/* 7101 */ "SWSP_MMR6\0"	8487	/* 7101 */ "SWSP_MMR6\0"
8488	/* 7111 */ "DVP_MMR6\0"	8488	/* 7111 */ "DVP_MMR6\0"
8489	/* 7120 */ "EVP_MMR6\0"	8489	/* 7120 */ "EVP_MMR6\0"
8490	/* 7129 */ "NOR_MMR6\0"	8490	/* 7129 */ "NOR_MMR6\0"
8491	/* 7138 */ "XOR_MMR6\0"	8491	/* 7138 */ "XOR_MMR6\0"
8492	/* 7147 */ "RDPGPR_MMR6\0"	8492	/* 7147 */ "RDPGPR_MMR6\0"
8493	/* 7159 */ "WRPGPR_MMR6\0"	8493	/* 7159 */ "WRPGPR_MMR6\0"
8494	/* 7171 */ "RDHWR_MMR6\0"	8494	/* 7171 */ "RDHWR_MMR6\0"
8495	/* 7182 */ "INS_MMR6\0"	8495	/* 7182 */ "INS_MMR6\0"
8496	/* 7191 */ "MINA_S_MMR6\0"	8496	/* 7191 */ "MINA_S_MMR6\0"
8497	/* 7203 */ "MAXA_S_MMR6\0"	8497	/* 7203 */ "MAXA_S_MMR6\0"
8498	/* 7215 */ "FSUB_S_MMR6\0"	8498	/* 7215 */ "FSUB_S_MMR6\0"
8499	/* 7227 */ "FADD_S_MMR6\0"	8499	/* 7227 */ "FADD_S_MMR6\0"
8500	/* 7239 */ "CMP_SLE_S_MMR6\0"	8500	/* 7239 */ "CMP_SLE_S_MMR6\0"
8501	/* 7254 */ "CMP_SULE_S_MMR6\0"	8501	/* 7254 */ "CMP_SULE_S_MMR6\0"
8502	/* 7270 */ "CMP_ULE_S_MMR6\0"	8502	/* 7270 */ "CMP_ULE_S_MMR6\0"
8503	/* 7285 */ "CMP_LE_S_MMR6\0"	8503	/* 7285 */ "CMP_LE_S_MMR6\0"
8504	/* 7299 */ "CMP_SAF_S_MMR6\0"	8504	/* 7299 */ "CMP_SAF_S_MMR6\0"
8505	/* 7314 */ "CMP_AF_S_MMR6\0"	8505	/* 7314 */ "CMP_AF_S_MMR6\0"
8506	/* 7328 */ "MSUBF_S_MMR6\0"	8506	/* 7328 */ "MSUBF_S_MMR6\0"
8507	/* 7341 */ "MADDF_S_MMR6\0"	8507	/* 7341 */ "MADDF_S_MMR6\0"
8508	/* 7354 */ "FNEG_S_MMR6\0"	8508	/* 7354 */ "FNEG_S_MMR6\0"
8509	/* 7366 */ "SEL_S_MMR6\0"	8509	/* 7366 */ "SEL_S_MMR6\0"
8510	/* 7377 */ "FMUL_S_MMR6\0"	8510	/* 7377 */ "FMUL_S_MMR6\0"
8511	/* 7389 */ "TRUNC_L_S_MMR6\0"	8511	/* 7389 */ "TRUNC_L_S_MMR6\0"
8512	/* 7404 */ "ROUND_L_S_MMR6\0"	8512	/* 7404 */ "ROUND_L_S_MMR6\0"
8513	/* 7419 */ "CEIL_L_S_MMR6\0"	8513	/* 7419 */ "CEIL_L_S_MMR6\0"
8514	/* 7433 */ "FLOOR_L_S_MMR6\0"	8514	/* 7433 */ "FLOOR_L_S_MMR6\0"
8515	/* 7448 */ "CVT_L_S_MMR6\0"	8515	/* 7448 */ "CVT_L_S_MMR6\0"
8516	/* 7461 */ "MIN_S_MMR6\0"	8516	/* 7461 */ "MIN_S_MMR6\0"
8517	/* 7472 */ "CMP_SUN_S_MMR6\0"	8517	/* 7472 */ "CMP_SUN_S_MMR6\0"
8518	/* 7487 */ "CMP_UN_S_MMR6\0"	8518	/* 7487 */ "CMP_UN_S_MMR6\0"
8519	/* 7501 */ "CMP_SEQ_S_MMR6\0"	8519	/* 7501 */ "CMP_SEQ_S_MMR6\0"
8520	/* 7516 */ "CMP_SUEQ_S_MMR6\0"	8520	/* 7516 */ "CMP_SUEQ_S_MMR6\0"
8521	/* 7532 */ "CMP_UEQ_S_MMR6\0"	8521	/* 7532 */ "CMP_UEQ_S_MMR6\0"
8522	/* 7547 */ "CMP_EQ_S_MMR6\0"	8522	/* 7547 */ "CMP_EQ_S_MMR6\0"
8523	/* 7561 */ "CLASS_S_MMR6\0"	8523	/* 7561 */ "CLASS_S_MMR6\0"
8524	/* 7574 */ "CMP_SLT_S_MMR6\0"	8524	/* 7574 */ "CMP_SLT_S_MMR6\0"
8525	/* 7589 */ "CMP_SULT_S_MMR6\0"	8525	/* 7589 */ "CMP_SULT_S_MMR6\0"
8526	/* 7605 */ "CMP_ULT_S_MMR6\0"	8526	/* 7605 */ "CMP_ULT_S_MMR6\0"
8527	/* 7620 */ "CMP_LT_S_MMR6\0"	8527	/* 7620 */ "CMP_LT_S_MMR6\0"
8528	/* 7634 */ "RINT_S_MMR6\0"	8528	/* 7634 */ "RINT_S_MMR6\0"
8529	/* 7646 */ "FDIV_S_MMR6\0"	8529	/* 7646 */ "FDIV_S_MMR6\0"
8530	/* 7658 */ "FMOV_S_MMR6\0"	8530	/* 7658 */ "FMOV_S_MMR6\0"
8531	/* 7670 */ "TRUNC_W_S_MMR6\0"	8531	/* 7670 */ "TRUNC_W_S_MMR6\0"
8532	/* 7685 */ "ROUND_W_S_MMR6\0"	8532	/* 7685 */ "ROUND_W_S_MMR6\0"
8533	/* 7700 */ "CEIL_W_S_MMR6\0"	8533	/* 7700 */ "CEIL_W_S_MMR6\0"
8534	/* 7714 */ "FLOOR_W_S_MMR6\0"	8534	/* 7714 */ "FLOOR_W_S_MMR6\0"
8535	/* 7729 */ "CVT_W_S_MMR6\0"	8535	/* 7729 */ "CVT_W_S_MMR6\0"
8536	/* 7742 */ "MAX_S_MMR6\0"	8536	/* 7742 */ "MAX_S_MMR6\0"
8537	/* 7753 */ "SELNEZ_S_MMR6\0"	8537	/* 7753 */ "SELNEZ_S_MMR6\0"
8538	/* 7767 */ "SELEQZ_S_MMR6\0"	8538	/* 7767 */ "SELEQZ_S_MMR6\0"
8539	/* 7781 */ "DERET_MMR6\0"	8539	/* 7781 */ "DERET_MMR6\0"
8540	/* 7792 */ "WAIT_MMR6\0"	8540	/* 7792 */ "WAIT_MMR6\0"
8541	/* 7802 */ "GINVT_MMR6\0"	8541	/* 7802 */ "GINVT_MMR6\0"
8542	/* 7813 */ "EXT_MMR6\0"	8542	/* 7813 */ "EXT_MMR6\0"
8543	/* 7822 */ "LBU_MMR6\0"	8543	/* 7822 */ "LBU_MMR6\0"
8544	/* 7831 */ "SUBU_MMR6\0"	8544	/* 7831 */ "SUBU_MMR6\0"
8545	/* 7841 */ "ADDU_MMR6\0"	8545	/* 7841 */ "ADDU_MMR6\0"
8546	/* 7851 */ "MODU_MMR6\0"	8546	/* 7851 */ "MODU_MMR6\0"
8547	/* 7861 */ "MUHU_MMR6\0"	8547	/* 7861 */ "MUHU_MMR6\0"
8548	/* 7871 */ "ADDIU_MMR6\0"	8548	/* 7871 */ "ADDIU_MMR6\0"
8549	/* 7882 */ "MULU_MMR6\0"	8549	/* 7882 */ "MULU_MMR6\0"
8550	/* 7892 */ "DIVU_MMR6\0"	8550	/* 7892 */ "DIVU_MMR6\0"
8551	/* 7902 */ "DIV_MMR6\0"	8551	/* 7902 */ "DIV_MMR6\0"
8552	/* 7911 */ "TLBINV_MMR6\0"	8552	/* 7911 */ "TLBINV_MMR6\0"
8553	/* 7923 */ "LW_MMR6\0"	8553	/* 7923 */ "LW_MMR6\0"
8554	/* 7931 */ "SW_MMR6\0"	8554	/* 7931 */ "SW_MMR6\0"
8555	/* 7939 */ "CVT_S_W_MMR6\0"	8555	/* 7939 */ "CVT_S_W_MMR6\0"
8556	/* 7952 */ "SELNEZ_MMR6\0"	8556	/* 7952 */ "SELNEZ_MMR6\0"
8557	/* 7964 */ "CLZ_MMR6\0"	8557	/* 7964 */ "CLZ_MMR6\0"
8558	/* 7973 */ "SELEQZ_MMR6\0"	8558	/* 7973 */ "SELEQZ_MMR6\0"
8559	/* 7985 */ "PseudoIndirectBranch_MMR6\0"	8559	/* 7985 */ "PseudoIndirectBranch_MMR6\0"
8560	/* 8011 */ "LDC2_R6\0"	8560	/* 8011 */ "LDC2_R6\0"
8561	/* 8019 */ "SDC2_R6\0"	8561	/* 8019 */ "SDC2_R6\0"
8562	/* 8027 */ "LWC2_R6\0"	8562	/* 8027 */ "LWC2_R6\0"
8563	/* 8035 */ "SWC2_R6\0"	8563	/* 8035 */ "SWC2_R6\0"
8564	/* 8043 */ "JR_HB64_R6\0"	8564	/* 8043 */ "JR_HB64_R6\0"
8565	/* 8054 */ "SC64_R6\0"	8565	/* 8054 */ "SC64_R6\0"
8566	/* 8062 */ "LL64_R6\0"	8566	/* 8062 */ "LL64_R6\0"
8567	/* 8070 */ "DLSA_R6\0"	8567	/* 8070 */ "DLSA_R6\0"
8568	/* 8078 */ "JR_HB_R6\0"	8568	/* 8078 */ "JR_HB_R6\0"
8569	/* 8087 */ "SC_R6\0"	8569	/* 8087 */ "SC_R6\0"
8570	/* 8093 */ "SCD_R6\0"	8570	/* 8093 */ "SCD_R6\0"
8571	/* 8100 */ "LLD_R6\0"	8571	/* 8100 */ "LLD_R6\0"
8572	/* 8107 */ "CACHE_R6\0"	8572	/* 8107 */ "CACHE_R6\0"
8573	/* 8116 */ "PREF_R6\0"	8573	/* 8116 */ "PREF_R6\0"
8574	/* 8124 */ "LL_R6\0"	8574	/* 8124 */ "LL_R6\0"
8575	/* 8130 */ "DMUL_R6\0"	8575	/* 8130 */ "DMUL_R6\0"
8576	/* 8138 */ "DCLO_R6\0"	8576	/* 8138 */ "DCLO_R6\0"
8577	/* 8146 */ "SDBBP_R6\0"	8577	/* 8146 */ "SDBBP_R6\0"
8578	/* 8155 */ "DCLZ_R6\0"	8578	/* 8155 */ "DCLZ_R6\0"
8579	/* 8163 */ "PseudoIndrectHazardBranchR6\0"	8579	/* 8163 */ "PseudoIndrectHazardBranchR6\0"
8580	/* 8191 */ "PseudoIndirectBranchR6\0"	8580	/* 8191 */ "PseudoIndirectBranchR6\0"
8581	/* 8214 */ "LOAD_ACC128\0"	8581	/* 8214 */ "LOAD_ACC128\0"
8582	/* 8226 */ "STORE_ACC128\0"	8582	/* 8226 */ "STORE_ACC128\0"
8583	/* 8239 */ "ATOMIC_LOAD_SUB_I8\0"	8583	/* 8239 */ "ATOMIC_LOAD_SUB_I8\0"
8584	/* 8258 */ "ATOMIC_LOAD_ADD_I8\0"	8584	/* 8258 */ "ATOMIC_LOAD_ADD_I8\0"
8585	/* 8277 */ "ATOMIC_LOAD_NAND_I8\0"	8585	/* 8277 */ "ATOMIC_LOAD_NAND_I8\0"
8586	/* 8297 */ "ATOMIC_LOAD_AND_I8\0"	8586	/* 8297 */ "ATOMIC_LOAD_AND_I8\0"
8587	/* 8316 */ "ATOMIC_LOAD_UMIN_I8\0"	8587	/* 8316 */ "ATOMIC_LOAD_UMIN_I8\0"
8588	/* 8336 */ "ATOMIC_LOAD_MIN_I8\0"	8588	/* 8336 */ "ATOMIC_LOAD_MIN_I8\0"
8589	/* 8355 */ "ATOMIC_SWAP_I8\0"	8589	/* 8355 */ "ATOMIC_SWAP_I8\0"
8590	/* 8370 */ "ATOMIC_CMP_SWAP_I8\0"	8590	/* 8370 */ "ATOMIC_CMP_SWAP_I8\0"
8591	/* 8389 */ "ATOMIC_LOAD_XOR_I8\0"	8591	/* 8389 */ "ATOMIC_LOAD_XOR_I8\0"
8592	/* 8408 */ "ATOMIC_LOAD_OR_I8\0"	8592	/* 8408 */ "ATOMIC_LOAD_OR_I8\0"
8593	/* 8426 */ "ATOMIC_LOAD_UMAX_I8\0"	8593	/* 8426 */ "ATOMIC_LOAD_UMAX_I8\0"
8594	/* 8446 */ "ATOMIC_LOAD_MAX_I8\0"	8594	/* 8446 */ "ATOMIC_LOAD_MAX_I8\0"
8595	/* 8465 */ "SAA\0"	8595	/* 8465 */ "SAA\0"
8596	/* 8469 */ "PRECEU_PH_QBLA\0"	8596	/* 8469 */ "PRECEU_PH_QBLA\0"
8597	/* 8484 */ "PRECEQU_PH_QBLA\0"	8597	/* 8484 */ "PRECEQU_PH_QBLA\0"
8598	/* 8500 */ "G_FMA\0"	8598	/* 8500 */ "G_FMA\0"
8599	/* 8506 */ "G_STRICT_FMA\0"	8599	/* 8506 */ "G_STRICT_FMA\0"
8600	/* 8519 */ "PRECEU_PH_QBRA\0"	8600	/* 8519 */ "PRECEU_PH_QBRA\0"
8601	/* 8534 */ "PRECEQU_PH_QBRA\0"	8601	/* 8534 */ "PRECEQU_PH_QBRA\0"
8602	/* 8550 */ "DSRA\0"	8602	/* 8550 */ "DSRA\0"
8603	/* 8555 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"	8603	/* 8555 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"
8604	/* 8582 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"	8604	/* 8582 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"
8605	/* 8609 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"	8605	/* 8609 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"
8606	/* 8637 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"	8606	/* 8637 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"
8607	/* 8664 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"	8607	/* 8664 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"
8608	/* 8692 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"	8608	/* 8692 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"
8609	/* 8719 */ "ATOMIC_SWAP_I32_POSTRA\0"	8609	/* 8719 */ "ATOMIC_SWAP_I32_POSTRA\0"
8610	/* 8742 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"	8610	/* 8742 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"
8611	/* 8769 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"	8611	/* 8769 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"
8612	/* 8796 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"	8612	/* 8796 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"
8613	/* 8822 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"	8613	/* 8822 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"
8614	/* 8850 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"	8614	/* 8850 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"
8615	/* 8877 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"	8615	/* 8877 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"
8616	/* 8904 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"	8616	/* 8904 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"
8617	/* 8931 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"	8617	/* 8931 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"
8618	/* 8959 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"	8618	/* 8959 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"
8619	/* 8986 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"	8619	/* 8986 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"
8620	/* 9014 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"	8620	/* 9014 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"
8621	/* 9041 */ "ATOMIC_SWAP_I64_POSTRA\0"	8621	/* 9041 */ "ATOMIC_SWAP_I64_POSTRA\0"
8622	/* 9064 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"	8622	/* 9064 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"
8623	/* 9091 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"	8623	/* 9091 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"
8624	/* 9118 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"	8624	/* 9118 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"
8625	/* 9144 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"	8625	/* 9144 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"
8626	/* 9172 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"	8626	/* 9172 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"
8627	/* 9199 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"	8627	/* 9199 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"
8628	/* 9226 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"	8628	/* 9226 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"
8629	/* 9253 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"	8629	/* 9253 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"
8630	/* 9281 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"	8630	/* 9281 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"
8631	/* 9308 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"	8631	/* 9308 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"
8632	/* 9336 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"	8632	/* 9336 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"
8633	/* 9363 */ "ATOMIC_SWAP_I16_POSTRA\0"	8633	/* 9363 */ "ATOMIC_SWAP_I16_POSTRA\0"
8634	/* 9386 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"	8634	/* 9386 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"
8635	/* 9413 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"	8635	/* 9413 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"
8636	/* 9440 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"	8636	/* 9440 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"
8637	/* 9466 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"	8637	/* 9466 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"
8638	/* 9494 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"	8638	/* 9494 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"
8639	/* 9521 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"	8639	/* 9521 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"
8640	/* 9547 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"	8640	/* 9547 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"
8641	/* 9573 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"	8641	/* 9573 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"
8642	/* 9600 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"	8642	/* 9600 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"
8643	/* 9626 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"	8643	/* 9626 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"
8644	/* 9653 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"	8644	/* 9653 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"
8645	/* 9679 */ "ATOMIC_SWAP_I8_POSTRA\0"	8645	/* 9679 */ "ATOMIC_SWAP_I8_POSTRA\0"
8646	/* 9701 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"	8646	/* 9701 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"
8647	/* 9727 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"	8647	/* 9727 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"
8648	/* 9753 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"	8648	/* 9753 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"
8649	/* 9778 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"	8649	/* 9778 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"
8650	/* 9805 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"	8650	/* 9805 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"
8651	/* 9831 */ "RetRA\0"	8651	/* 9831 */ "RetRA\0"
8652	/* 9837 */ "DLSA\0"	8652	/* 9837 */ "DLSA\0"
8653	/* 9842 */ "CFCMSA\0"	8653	/* 9842 */ "CFCMSA\0"
8654	/* 9849 */ "CTCMSA\0"	8654	/* 9849 */ "CTCMSA\0"
8655	/* 9856 */ "CRC32B\0"	8655	/* 9856 */ "CRC32B\0"
8656	/* 9863 */ "CRC32CB\0"	8656	/* 9863 */ "CRC32CB\0"
8657	/* 9871 */ "SEB\0"	8657	/* 9871 */ "SEB\0"
8658	/* 9875 */ "EHB\0"	8658	/* 9875 */ "EHB\0"
8659	/* 9879 */ "TAILCALLREGHB\0"	8659	/* 9879 */ "TAILCALLREGHB\0"
8660	/* 9893 */ "JR_HB\0"	8660	/* 9893 */ "JR_HB\0"
8661	/* 9899 */ "JALR_HB\0"	8661	/* 9899 */ "JALR_HB\0"
8662	/* 9907 */ "LB\0"	8662	/* 9907 */ "LB\0"
8663	/* 9910 */ "SHRA_QB\0"	8663	/* 9910 */ "SHRA_QB\0"
8664	/* 9918 */ "CMPGDU_LE_QB\0"	8664	/* 9918 */ "CMPGDU_LE_QB\0"
8665	/* 9931 */ "CMPGU_LE_QB\0"	8665	/* 9931 */ "CMPGU_LE_QB\0"
8666	/* 9943 */ "PseudoCMPU_LE_QB\0"	8666	/* 9943 */ "PseudoCMPU_LE_QB\0"
8667	/* 9960 */ "SUBUH_QB\0"	8667	/* 9960 */ "SUBUH_QB\0"
8668	/* 9969 */ "ADDUH_QB\0"	8668	/* 9969 */ "ADDUH_QB\0"
8669	/* 9978 */ "PseudoPICK_QB\0"	8669	/* 9978 */ "PseudoPICK_QB\0"
8670	/* 9992 */ "SHLL_QB\0"	8670	/* 9992 */ "SHLL_QB\0"
8671	/* 10000 */ "REPL_QB\0"	8671	/* 10000 */ "REPL_QB\0"
8672	/* 10008 */ "SHRL_QB\0"	8672	/* 10008 */ "SHRL_QB\0"
8673	/* 10016 */ "CMPGDU_EQ_QB\0"	8673	/* 10016 */ "CMPGDU_EQ_QB\0"
8674	/* 10029 */ "CMPGU_EQ_QB\0"	8674	/* 10029 */ "CMPGU_EQ_QB\0"
8675	/* 10041 */ "PseudoCMPU_EQ_QB\0"	8675	/* 10041 */ "PseudoCMPU_EQ_QB\0"
8676	/* 10058 */ "SHRA_R_QB\0"	8676	/* 10058 */ "SHRA_R_QB\0"
8677	/* 10068 */ "SUBUH_R_QB\0"	8677	/* 10068 */ "SUBUH_R_QB\0"
8678	/* 10079 */ "ADDUH_R_QB\0"	8678	/* 10079 */ "ADDUH_R_QB\0"
8679	/* 10090 */ "SHRAV_R_QB\0"	8679	/* 10090 */ "SHRAV_R_QB\0"
8680	/* 10101 */ "ABSQ_S_QB\0"	8680	/* 10101 */ "ABSQ_S_QB\0"
8681	/* 10111 */ "SUBU_S_QB\0"	8681	/* 10111 */ "SUBU_S_QB\0"
8682	/* 10121 */ "ADDU_S_QB\0"	8682	/* 10121 */ "ADDU_S_QB\0"
8683	/* 10131 */ "CMPGDU_LT_QB\0"	8683	/* 10131 */ "CMPGDU_LT_QB\0"
8684	/* 10144 */ "CMPGU_LT_QB\0"	8684	/* 10144 */ "CMPGU_LT_QB\0"
8685	/* 10156 */ "PseudoCMPU_LT_QB\0"	8685	/* 10156 */ "PseudoCMPU_LT_QB\0"
8686	/* 10173 */ "SUBU_QB\0"	8686	/* 10173 */ "SUBU_QB\0"
8687	/* 10181 */ "ADDU_QB\0"	8687	/* 10181 */ "ADDU_QB\0"
8688	/* 10189 */ "SHRAV_QB\0"	8688	/* 10189 */ "SHRAV_QB\0"
8689	/* 10198 */ "SHLLV_QB\0"	8689	/* 10198 */ "SHLLV_QB\0"
8690	/* 10207 */ "REPLV_QB\0"	8690	/* 10207 */ "REPLV_QB\0"
8691	/* 10216 */ "SHRLV_QB\0"	8691	/* 10216 */ "SHRLV_QB\0"
8692	/* 10225 */ "RADDU_W_QB\0"	8692	/* 10225 */ "RADDU_W_QB\0"
8693	/* 10236 */ "SB\0"	8693	/* 10236 */ "SB\0"
8694	/* 10239 */ "MODSUB\0"	8694	/* 10239 */ "MODSUB\0"
8695	/* 10246 */ "G_FSUB\0"	8695	/* 10246 */ "G_FSUB\0"
8696	/* 10253 */ "G_STRICT_FSUB\0"	8696	/* 10253 */ "G_STRICT_FSUB\0"
8697	/* 10267 */ "G_ATOMICRMW_FSUB\0"	8697	/* 10267 */ "G_ATOMICRMW_FSUB\0"
8698	/* 10284 */ "PseudoMSUB\0"	8698	/* 10284 */ "PseudoMSUB\0"
8699	/* 10295 */ "G_SUB\0"	8699	/* 10295 */ "G_SUB\0"
8700	/* 10301 */ "G_ATOMICRMW_SUB\0"	8700	/* 10301 */ "G_ATOMICRMW_SUB\0"
8701	/* 10317 */ "SRA_B\0"	8701	/* 10317 */ "SRA_B\0"
8702	/* 10323 */ "ADD_A_B\0"	8702	/* 10323 */ "ADD_A_B\0"
8703	/* 10331 */ "MIN_A_B\0"	8703	/* 10331 */ "MIN_A_B\0"
8704	/* 10339 */ "ADDS_A_B\0"	8704	/* 10339 */ "ADDS_A_B\0"
8705	/* 10348 */ "MAX_A_B\0"	8705	/* 10348 */ "MAX_A_B\0"
8706	/* 10356 */ "NLOC_B\0"	8706	/* 10356 */ "NLOC_B\0"
8707	/* 10363 */ "NLZC_B\0"	8707	/* 10363 */ "NLZC_B\0"
8708	/* 10370 */ "SLD_B\0"	8708	/* 10370 */ "SLD_B\0"
8709	/* 10376 */ "PCKOD_B\0"	8709	/* 10376 */ "PCKOD_B\0"
8710	/* 10384 */ "ILVOD_B\0"	8710	/* 10384 */ "ILVOD_B\0"
8711	/* 10392 */ "INSVE_B\0"	8711	/* 10392 */ "INSVE_B\0"
8712	/* 10400 */ "VSHF_B\0"	8712	/* 10400 */ "VSHF_B\0"
8713	/* 10407 */ "BNEG_B\0"	8713	/* 10407 */ "BNEG_B\0"
8714	/* 10414 */ "SRAI_B\0"	8714	/* 10414 */ "SRAI_B\0"
8715	/* 10421 */ "SLDI_B\0"	8715	/* 10421 */ "SLDI_B\0"
8716	/* 10428 */ "ANDI_B\0"	8716	/* 10428 */ "ANDI_B\0"
8717	/* 10435 */ "BNEGI_B\0"	8717	/* 10435 */ "BNEGI_B\0"
8718	/* 10443 */ "BSELI_B\0"	8718	/* 10443 */ "BSELI_B\0"
8719	/* 10451 */ "SLLI_B\0"	8719	/* 10451 */ "SLLI_B\0"
8720	/* 10458 */ "SRLI_B\0"	8720	/* 10458 */ "SRLI_B\0"
8721	/* 10465 */ "BINSLI_B\0"	8721	/* 10465 */ "BINSLI_B\0"
8722	/* 10474 */ "CEQI_B\0"	8722	/* 10474 */ "CEQI_B\0"
8723	/* 10481 */ "SRARI_B\0"	8723	/* 10481 */ "SRARI_B\0"
8724	/* 10489 */ "BCLRI_B\0"	8724	/* 10489 */ "BCLRI_B\0"
8725	/* 10497 */ "SRLRI_B\0"	8725	/* 10497 */ "SRLRI_B\0"
8726	/* 10505 */ "NORI_B\0"	8726	/* 10505 */ "NORI_B\0"
8727	/* 10512 */ "XORI_B\0"	8727	/* 10512 */ "XORI_B\0"
8728	/* 10519 */ "BINSRI_B\0"	8728	/* 10519 */ "BINSRI_B\0"
8729	/* 10528 */ "SPLATI_B\0"	8729	/* 10528 */ "SPLATI_B\0"
8730	/* 10537 */ "BSETI_B\0"	8730	/* 10537 */ "BSETI_B\0"
8731	/* 10545 */ "SUBVI_B\0"	8731	/* 10545 */ "SUBVI_B\0"
8732	/* 10553 */ "ADDVI_B\0"	8732	/* 10553 */ "ADDVI_B\0"
8733	/* 10561 */ "BMZI_B\0"	8733	/* 10561 */ "BMZI_B\0"
8734	/* 10568 */ "BMNZI_B\0"	8734	/* 10568 */ "BMNZI_B\0"
8735	/* 10576 */ "FILL_B\0"	8735	/* 10576 */ "FILL_B\0"
8736	/* 10583 */ "SLL_B\0"	8736	/* 10583 */ "SLL_B\0"
8737	/* 10589 */ "SRL_B\0"	8737	/* 10589 */ "SRL_B\0"
8738	/* 10595 */ "BINSL_B\0"	8738	/* 10595 */ "BINSL_B\0"
8739	/* 10603 */ "ILVL_B\0"	8739	/* 10603 */ "ILVL_B\0"
8740	/* 10610 */ "CEQ_B\0"	8740	/* 10610 */ "CEQ_B\0"
8741	/* 10616 */ "SRAR_B\0"	8741	/* 10616 */ "SRAR_B\0"
8742	/* 10623 */ "BCLR_B\0"	8742	/* 10623 */ "BCLR_B\0"
8743	/* 10630 */ "SRLR_B\0"	8743	/* 10630 */ "SRLR_B\0"
8744	/* 10637 */ "BINSR_B\0"	8744	/* 10637 */ "BINSR_B\0"
8745	/* 10645 */ "ILVR_B\0"	8745	/* 10645 */ "ILVR_B\0"
8746	/* 10652 */ "ASUB_S_B\0"	8746	/* 10652 */ "ASUB_S_B\0"
8747	/* 10661 */ "MOD_S_B\0"	8747	/* 10661 */ "MOD_S_B\0"
8748	/* 10669 */ "CLE_S_B\0"	8748	/* 10669 */ "CLE_S_B\0"
8749	/* 10677 */ "AVE_S_B\0"	8749	/* 10677 */ "AVE_S_B\0"
8750	/* 10685 */ "CLEI_S_B\0"	8750	/* 10685 */ "CLEI_S_B\0"
8751	/* 10694 */ "MINI_S_B\0"	8751	/* 10694 */ "MINI_S_B\0"
8752	/* 10703 */ "CLTI_S_B\0"	8752	/* 10703 */ "CLTI_S_B\0"
8753	/* 10712 */ "MAXI_S_B\0"	8753	/* 10712 */ "MAXI_S_B\0"
8754	/* 10721 */ "MIN_S_B\0"	8754	/* 10721 */ "MIN_S_B\0"
8755	/* 10729 */ "AVER_S_B\0"	8755	/* 10729 */ "AVER_S_B\0"
8756	/* 10738 */ "SUBS_S_B\0"	8756	/* 10738 */ "SUBS_S_B\0"
8757	/* 10747 */ "ADDS_S_B\0"	8757	/* 10747 */ "ADDS_S_B\0"
8758	/* 10756 */ "SAT_S_B\0"	8758	/* 10756 */ "SAT_S_B\0"
8759	/* 10764 */ "CLT_S_B\0"	8759	/* 10764 */ "CLT_S_B\0"
8760	/* 10772 */ "SUBSUU_S_B\0"	8760	/* 10772 */ "SUBSUU_S_B\0"
8761	/* 10783 */ "DIV_S_B\0"	8761	/* 10783 */ "DIV_S_B\0"
8762	/* 10791 */ "MAX_S_B\0"	8762	/* 10791 */ "MAX_S_B\0"
8763	/* 10799 */ "COPY_S_B\0"	8763	/* 10799 */ "COPY_S_B\0"
8764	/* 10808 */ "SPLAT_B\0"	8764	/* 10808 */ "SPLAT_B\0"
8765	/* 10816 */ "BSET_B\0"	8765	/* 10816 */ "BSET_B\0"
8766	/* 10823 */ "PCNT_B\0"	8766	/* 10823 */ "PCNT_B\0"
8767	/* 10830 */ "INSERT_B\0"	8767	/* 10830 */ "INSERT_B\0"
8768	/* 10839 */ "ST_B\0"	8768	/* 10839 */ "ST_B\0"
8769	/* 10844 */ "ASUB_U_B\0"	8769	/* 10844 */ "ASUB_U_B\0"
8770	/* 10853 */ "MOD_U_B\0"	8770	/* 10853 */ "MOD_U_B\0"
8771	/* 10861 */ "CLE_U_B\0"	8771	/* 10861 */ "CLE_U_B\0"
8772	/* 10869 */ "AVE_U_B\0"	8772	/* 10869 */ "AVE_U_B\0"
8773	/* 10877 */ "CLEI_U_B\0"	8773	/* 10877 */ "CLEI_U_B\0"
8774	/* 10886 */ "MINI_U_B\0"	8774	/* 10886 */ "MINI_U_B\0"
8775	/* 10895 */ "CLTI_U_B\0"	8775	/* 10895 */ "CLTI_U_B\0"
8776	/* 10904 */ "MAXI_U_B\0"	8776	/* 10904 */ "MAXI_U_B\0"
8777	/* 10913 */ "MIN_U_B\0"	8777	/* 10913 */ "MIN_U_B\0"
8778	/* 10921 */ "AVER_U_B\0"	8778	/* 10921 */ "AVER_U_B\0"
8779	/* 10930 */ "SUBS_U_B\0"	8779	/* 10930 */ "SUBS_U_B\0"
8780	/* 10939 */ "ADDS_U_B\0"	8780	/* 10939 */ "ADDS_U_B\0"
8781	/* 10948 */ "SUBSUS_U_B\0"	8781	/* 10948 */ "SUBSUS_U_B\0"
8782	/* 10959 */ "SAT_U_B\0"	8782	/* 10959 */ "SAT_U_B\0"
8783	/* 10967 */ "CLT_U_B\0"	8783	/* 10967 */ "CLT_U_B\0"
8784	/* 10975 */ "DIV_U_B\0"	8784	/* 10975 */ "DIV_U_B\0"
8785	/* 10983 */ "MAX_U_B\0"	8785	/* 10983 */ "MAX_U_B\0"
8786	/* 10991 */ "COPY_U_B\0"	8786	/* 10991 */ "COPY_U_B\0"
8787	/* 11000 */ "MSUBV_B\0"	8787	/* 11000 */ "MSUBV_B\0"
8788	/* 11008 */ "MADDV_B\0"	8788	/* 11008 */ "MADDV_B\0"
8789	/* 11016 */ "PCKEV_B\0"	8789	/* 11016 */ "PCKEV_B\0"
8790	/* 11024 */ "ILVEV_B\0"	8790	/* 11024 */ "ILVEV_B\0"
8791	/* 11032 */ "MULV_B\0"	8791	/* 11032 */ "MULV_B\0"
8792	/* 11039 */ "BZ_B\0"	8792	/* 11039 */ "BZ_B\0"
8793	/* 11044 */ "BNZ_B\0"	8793	/* 11044 */ "BNZ_B\0"
8794	/* 11050 */ "BC\0"	8794	/* 11050 */ "BC\0"
8795	/* 11053 */ "BGEC\0"	8795	/* 11053 */ "BGEC\0"
8796	/* 11058 */ "BNEC\0"	8796	/* 11058 */ "BNEC\0"
8797	/* 11063 */ "JIC\0"	8797	/* 11063 */ "JIC\0"
8798	/* 11067 */ "G_INTRINSIC\0"	8798	/* 11067 */ "G_INTRINSIC\0"
8799	/* 11079 */ "BALC\0"	8799	/* 11079 */ "BALC\0"
8800	/* 11084 */ "JIALC\0"	8800	/* 11084 */ "JIALC\0"
8801	/* 11090 */ "BGEZALC\0"	8801	/* 11090 */ "BGEZALC\0"
8802	/* 11098 */ "BLEZALC\0"	8802	/* 11098 */ "BLEZALC\0"
8803	/* 11106 */ "BNEZALC\0"	8803	/* 11106 */ "BNEZALC\0"
8804	/* 11114 */ "BEQZALC\0"	8804	/* 11114 */ "BEQZALC\0"
8805	/* 11122 */ "BGTZALC\0"	8805	/* 11122 */ "BGTZALC\0"
8806	/* 11130 */ "BLTZALC\0"	8806	/* 11130 */ "BLTZALC\0"
8807	/* 11138 */ "ERETNC\0"	8807	/* 11138 */ "ERETNC\0"
8808	/* 11145 */ "G_FPTRUNC\0"	8808	/* 11145 */ "G_FPTRUNC\0"
8809	/* 11155 */ "G_INTRINSIC_TRUNC\0"	8809	/* 11155 */ "G_INTRINSIC_TRUNC\0"
8810	/* 11173 */ "G_TRUNC\0"	8810	/* 11173 */ "G_TRUNC\0"
8811	/* 11181 */ "G_BUILD_VECTOR_TRUNC\0"	8811	/* 11181 */ "G_BUILD_VECTOR_TRUNC\0"
8812	/* 11202 */ "SYNC\0"	8812	/* 11202 */ "SYNC\0"
8813	/* 11207 */ "G_DYN_STACKALLOC\0"	8813	/* 11207 */ "G_DYN_STACKALLOC\0"
8814	/* 11224 */ "LDPC\0"	8814	/* 11224 */ "LDPC\0"
8815	/* 11229 */ "AUIPC\0"	8815	/* 11229 */ "AUIPC\0"
8816	/* 11235 */ "ALUIPC\0"	8816	/* 11235 */ "ALUIPC\0"
8817	/* 11242 */ "ADDIUPC\0"	8817	/* 11242 */ "ADDIUPC\0"
8818	/* 11250 */ "LWUPC\0"	8818	/* 11250 */ "LWUPC\0"
8819	/* 11256 */ "LWPC\0"	8819	/* 11256 */ "LWPC\0"
8820	/* 11261 */ "BEQC\0"	8820	/* 11261 */ "BEQC\0"
8821	/* 11266 */ "ADDSC\0"	8821	/* 11266 */ "ADDSC\0"
8822	/* 11272 */ "BLTC\0"	8822	/* 11272 */ "BLTC\0"
8823	/* 11277 */ "BGEUC\0"	8823	/* 11277 */ "BGEUC\0"
8824	/* 11283 */ "BLTUC\0"	8824	/* 11283 */ "BLTUC\0"
8825	/* 11289 */ "BNVC\0"	8825	/* 11289 */ "BNVC\0"
8826	/* 11294 */ "BOVC\0"	8826	/* 11294 */ "BOVC\0"
8827	/* 11299 */ "ADDWC\0"	8827	/* 11299 */ "ADDWC\0"
8828	/* 11305 */ "BGEZC\0"	8828	/* 11305 */ "BGEZC\0"
8829	/* 11311 */ "BLEZC\0"	8829	/* 11311 */ "BLEZC\0"
8830	/* 11317 */ "BNEZC\0"	8830	/* 11317 */ "BNEZC\0"
8831	/* 11323 */ "BEQZC\0"	8831	/* 11323 */ "BEQZC\0"
8832	/* 11329 */ "BGTZC\0"	8832	/* 11329 */ "BGTZC\0"
8833	/* 11335 */ "BLTZC\0"	8833	/* 11335 */ "BLTZC\0"
8834	/* 11341 */ "CRC32D\0"	8834	/* 11341 */ "CRC32D\0"
8835	/* 11348 */ "SAAD\0"	8835	/* 11348 */ "SAAD\0"
8836	/* 11353 */ "G_FMAD\0"	8836	/* 11353 */ "G_FMAD\0"
8837	/* 11360 */ "G_INDEXED_SEXTLOAD\0"	8837	/* 11360 */ "G_INDEXED_SEXTLOAD\0"
8838	/* 11379 */ "G_SEXTLOAD\0"	8838	/* 11379 */ "G_SEXTLOAD\0"
8839	/* 11390 */ "G_INDEXED_ZEXTLOAD\0"	8839	/* 11390 */ "G_INDEXED_ZEXTLOAD\0"
8840	/* 11409 */ "G_ZEXTLOAD\0"	8840	/* 11409 */ "G_ZEXTLOAD\0"
8841	/* 11420 */ "G_INDEXED_LOAD\0"	8841	/* 11420 */ "G_INDEXED_LOAD\0"
8842	/* 11435 */ "G_LOAD\0"	8842	/* 11435 */ "G_LOAD\0"
8843	/* 11442 */ "CRC32CD\0"	8843	/* 11442 */ "CRC32CD\0"
8844	/* 11450 */ "SCD\0"	8844	/* 11450 */ "SCD\0"
8845	/* 11454 */ "DADD\0"	8845	/* 11454 */ "DADD\0"
8846	/* 11459 */ "G_VECREDUCE_FADD\0"	8846	/* 11459 */ "G_VECREDUCE_FADD\0"
8847	/* 11476 */ "G_FADD\0"	8847	/* 11476 */ "G_FADD\0"
8848	/* 11483 */ "G_VECREDUCE_SEQ_FADD\0"	8848	/* 11483 */ "G_VECREDUCE_SEQ_FADD\0"
8849	/* 11504 */ "G_STRICT_FADD\0"	8849	/* 11504 */ "G_STRICT_FADD\0"
8850	/* 11518 */ "G_ATOMICRMW_FADD\0"	8850	/* 11518 */ "G_ATOMICRMW_FADD\0"
8851	/* 11535 */ "PseudoMADD\0"	8851	/* 11535 */ "PseudoMADD\0"
8852	/* 11546 */ "G_VECREDUCE_ADD\0"	8852	/* 11546 */ "G_VECREDUCE_ADD\0"
8853	/* 11562 */ "G_ADD\0"	8853	/* 11562 */ "G_ADD\0"
8854	/* 11568 */ "G_PTR_ADD\0"	8854	/* 11568 */ "G_PTR_ADD\0"
8855	/* 11578 */ "G_ATOMICRMW_ADD\0"	8855	/* 11578 */ "G_ATOMICRMW_ADD\0"
8856	/* 11594 */ "DSHD\0"	8856	/* 11594 */ "DSHD\0"
8857	/* 11599 */ "YIELD\0"	8857	/* 11599 */ "YIELD\0"
8858	/* 11605 */ "LLD\0"	8858	/* 11605 */ "LLD\0"
8859	/* 11609 */ "G_ATOMICRMW_NAND\0"	8859	/* 11609 */ "G_ATOMICRMW_NAND\0"
8860	/* 11626 */ "G_VECREDUCE_AND\0"	8860	/* 11626 */ "G_VECREDUCE_AND\0"
8861	/* 11642 */ "G_AND\0"	8861	/* 11642 */ "G_AND\0"
8862	/* 11648 */ "G_ATOMICRMW_AND\0"	8862	/* 11648 */ "G_ATOMICRMW_AND\0"
8863	/* 11664 */ "PREPEND\0"	8863	/* 11664 */ "PREPEND\0"
8864	/* 11672 */ "APPEND\0"	8864	/* 11672 */ "APPEND\0"
8865	/* 11679 */ "LIFETIME_END\0"	8865	/* 11679 */ "LIFETIME_END\0"
8866	/* 11692 */ "G_BRCOND\0"	8866	/* 11692 */ "G_BRCOND\0"
8867	/* 11701 */ "G_LLROUND\0"	8867	/* 11701 */ "G_LLROUND\0"
8868	/* 11711 */ "G_LROUND\0"	8868	/* 11711 */ "G_LROUND\0"
8869	/* 11720 */ "G_INTRINSIC_ROUND\0"	8869	/* 11720 */ "G_INTRINSIC_ROUND\0"
8870	/* 11738 */ "G_INTRINSIC_FPTRUNC_ROUND\0"	8870	/* 11738 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
8871	/* 11764 */ "DMOD\0"	8871	/* 11764 */ "DMOD\0"
8872	/* 11769 */ "LOAD_STACK_GUARD\0"	8872	/* 11769 */ "LOAD_STACK_GUARD\0"
8873	/* 11786 */ "SD\0"	8873	/* 11786 */ "SD\0"
8874	/* 11789 */ "FLOG2_D\0"	8874	/* 11789 */ "FLOG2_D\0"
8875	/* 11797 */ "FEXP2_D\0"	8875	/* 11797 */ "FEXP2_D\0"
8876	/* 11805 */ "MINA_D\0"	8876	/* 11805 */ "MINA_D\0"
8877	/* 11812 */ "SRA_D\0"	8877	/* 11812 */ "SRA_D\0"
8878	/* 11818 */ "MAXA_D\0"	8878	/* 11818 */ "MAXA_D\0"
8879	/* 11825 */ "ADD_A_D\0"	8879	/* 11825 */ "ADD_A_D\0"
8880	/* 11833 */ "FMIN_A_D\0"	8880	/* 11833 */ "FMIN_A_D\0"
8881	/* 11842 */ "ADDS_A_D\0"	8881	/* 11842 */ "ADDS_A_D\0"
8882	/* 11851 */ "FMAX_A_D\0"	8882	/* 11851 */ "FMAX_A_D\0"
8883	/* 11860 */ "FSUB_D\0"	8883	/* 11860 */ "FSUB_D\0"
8884	/* 11867 */ "FMSUB_D\0"	8884	/* 11867 */ "FMSUB_D\0"
8885	/* 11875 */ "NLOC_D\0"	8885	/* 11875 */ "NLOC_D\0"
8886	/* 11882 */ "NLZC_D\0"	8886	/* 11882 */ "NLZC_D\0"
8887	/* 11889 */ "FADD_D\0"	8887	/* 11889 */ "FADD_D\0"
8888	/* 11896 */ "FMADD_D\0"	8888	/* 11896 */ "FMADD_D\0"
8889	/* 11904 */ "SLD_D\0"	8889	/* 11904 */ "SLD_D\0"
8890	/* 11910 */ "PCKOD_D\0"	8890	/* 11910 */ "PCKOD_D\0"
8891	/* 11918 */ "ILVOD_D\0"	8891	/* 11918 */ "ILVOD_D\0"
8892	/* 11926 */ "FCLE_D\0"	8892	/* 11926 */ "FCLE_D\0"
8893	/* 11933 */ "FSLE_D\0"	8893	/* 11933 */ "FSLE_D\0"
8894	/* 11940 */ "CMP_SLE_D\0"	8894	/* 11940 */ "CMP_SLE_D\0"
8895	/* 11950 */ "FCULE_D\0"	8895	/* 11950 */ "FCULE_D\0"
8896	/* 11958 */ "FSULE_D\0"	8896	/* 11958 */ "FSULE_D\0"
8897	/* 11966 */ "CMP_SULE_D\0"	8897	/* 11966 */ "CMP_SULE_D\0"
8898	/* 11977 */ "CMP_ULE_D\0"	8898	/* 11977 */ "CMP_ULE_D\0"
8899	/* 11987 */ "CMP_LE_D\0"	8899	/* 11987 */ "CMP_LE_D\0"
8900	/* 11996 */ "FCNE_D\0"	8900	/* 11996 */ "FCNE_D\0"
8901	/* 12003 */ "FSNE_D\0"	8901	/* 12003 */ "FSNE_D\0"
8902	/* 12010 */ "FCUNE_D\0"	8902	/* 12010 */ "FCUNE_D\0"
8903	/* 12018 */ "FSUNE_D\0"	8903	/* 12018 */ "FSUNE_D\0"
8904	/* 12026 */ "INSVE_D\0"	8904	/* 12026 */ "INSVE_D\0"
8905	/* 12034 */ "FCAF_D\0"	8905	/* 12034 */ "FCAF_D\0"
8906	/* 12041 */ "FSAF_D\0"	8906	/* 12041 */ "FSAF_D\0"
8907	/* 12048 */ "CMP_SAF_D\0"	8907	/* 12048 */ "CMP_SAF_D\0"
8908	/* 12058 */ "MSUBF_D\0"	8908	/* 12058 */ "MSUBF_D\0"
8909	/* 12066 */ "MADDF_D\0"	8909	/* 12066 */ "MADDF_D\0"
8910	/* 12074 */ "VSHF_D\0"	8910	/* 12074 */ "VSHF_D\0"
8911	/* 12081 */ "CMP_F_D\0"	8911	/* 12081 */ "CMP_F_D\0"
8912	/* 12089 */ "BNEG_D\0"	8912	/* 12089 */ "BNEG_D\0"
8913	/* 12096 */ "SRAI_D\0"	8913	/* 12096 */ "SRAI_D\0"
8914	/* 12103 */ "SLDI_D\0"	8914	/* 12103 */ "SLDI_D\0"
8915	/* 12110 */ "BNEGI_D\0"	8915	/* 12110 */ "BNEGI_D\0"
8916	/* 12118 */ "SLLI_D\0"	8916	/* 12118 */ "SLLI_D\0"
8917	/* 12125 */ "SRLI_D\0"	8917	/* 12125 */ "SRLI_D\0"
8918	/* 12132 */ "BINSLI_D\0"	8918	/* 12132 */ "BINSLI_D\0"
8919	/* 12141 */ "CEQI_D\0"	8919	/* 12141 */ "CEQI_D\0"
8920	/* 12148 */ "SRARI_D\0"	8920	/* 12148 */ "SRARI_D\0"
8921	/* 12156 */ "BCLRI_D\0"	8921	/* 12156 */ "BCLRI_D\0"
8922	/* 12164 */ "SRLRI_D\0"	8922	/* 12164 */ "SRLRI_D\0"
8923	/* 12172 */ "BINSRI_D\0"	8923	/* 12172 */ "BINSRI_D\0"
8924	/* 12181 */ "SPLATI_D\0"	8924	/* 12181 */ "SPLATI_D\0"
8925	/* 12190 */ "BSETI_D\0"	8925	/* 12190 */ "BSETI_D\0"
8926	/* 12198 */ "SUBVI_D\0"	8926	/* 12198 */ "SUBVI_D\0"
8927	/* 12206 */ "ADDVI_D\0"	8927	/* 12206 */ "ADDVI_D\0"
8928	/* 12214 */ "SEL_D\0"	8928	/* 12214 */ "SEL_D\0"
8929	/* 12220 */ "FILL_D\0"	8929	/* 12220 */ "FILL_D\0"
8930	/* 12227 */ "SLL_D\0"	8930	/* 12227 */ "SLL_D\0"
8931	/* 12233 */ "FEXUPL_D\0"	8931	/* 12233 */ "FEXUPL_D\0"
8932	/* 12242 */ "FFQL_D\0"	8932	/* 12242 */ "FFQL_D\0"
8933	/* 12249 */ "SRL_D\0"	8933	/* 12249 */ "SRL_D\0"
8934	/* 12255 */ "BINSL_D\0"	8934	/* 12255 */ "BINSL_D\0"
8935	/* 12263 */ "FMUL_D\0"	8935	/* 12263 */ "FMUL_D\0"
8936	/* 12270 */ "ILVL_D\0"	8936	/* 12270 */ "ILVL_D\0"
8937	/* 12277 */ "FMIN_D\0"	8937	/* 12277 */ "FMIN_D\0"
8938	/* 12284 */ "FCUN_D\0"	8938	/* 12284 */ "FCUN_D\0"
8939	/* 12291 */ "FSUN_D\0"	8939	/* 12291 */ "FSUN_D\0"
8940	/* 12298 */ "CMP_SUN_D\0"	8940	/* 12298 */ "CMP_SUN_D\0"
8941	/* 12308 */ "CMP_UN_D\0"	8941	/* 12308 */ "CMP_UN_D\0"
8942	/* 12317 */ "FRCP_D\0"	8942	/* 12317 */ "FRCP_D\0"
8943	/* 12324 */ "FCEQ_D\0"	8943	/* 12324 */ "FCEQ_D\0"
8944	/* 12331 */ "FSEQ_D\0"	8944	/* 12331 */ "FSEQ_D\0"
8945	/* 12338 */ "CMP_SEQ_D\0"	8945	/* 12338 */ "CMP_SEQ_D\0"
8946	/* 12348 */ "FCUEQ_D\0"	8946	/* 12348 */ "FCUEQ_D\0"
8947	/* 12356 */ "FSUEQ_D\0"	8947	/* 12356 */ "FSUEQ_D\0"
8948	/* 12364 */ "CMP_SUEQ_D\0"	8948	/* 12364 */ "CMP_SUEQ_D\0"
8949	/* 12375 */ "CMP_UEQ_D\0"	8949	/* 12375 */ "CMP_UEQ_D\0"
8950	/* 12385 */ "CMP_EQ_D\0"	8950	/* 12385 */ "CMP_EQ_D\0"
8951	/* 12394 */ "SRAR_D\0"	8951	/* 12394 */ "SRAR_D\0"
8952	/* 12401 */ "LDR_D\0"	8952	/* 12401 */ "LDR_D\0"
8953	/* 12407 */ "BCLR_D\0"	8953	/* 12407 */ "BCLR_D\0"
8954	/* 12414 */ "SRLR_D\0"	8954	/* 12414 */ "SRLR_D\0"
8955	/* 12421 */ "FCOR_D\0"	8955	/* 12421 */ "FCOR_D\0"
8956	/* 12428 */ "FSOR_D\0"	8956	/* 12428 */ "FSOR_D\0"
8957	/* 12435 */ "FEXUPR_D\0"	8957	/* 12435 */ "FEXUPR_D\0"
8958	/* 12444 */ "FFQR_D\0"	8958	/* 12444 */ "FFQR_D\0"
8959	/* 12451 */ "BINSR_D\0"	8959	/* 12451 */ "BINSR_D\0"
8960	/* 12459 */ "STR_D\0"	8960	/* 12459 */ "STR_D\0"
8961	/* 12465 */ "ILVR_D\0"	8961	/* 12465 */ "ILVR_D\0"
8962	/* 12472 */ "FABS_D\0"	8962	/* 12472 */ "FABS_D\0"
8963	/* 12479 */ "FCLASS_D\0"	8963	/* 12479 */ "FCLASS_D\0"
8964	/* 12488 */ "ASUB_S_D\0"	8964	/* 12488 */ "ASUB_S_D\0"
8965	/* 12497 */ "HSUB_S_D\0"	8965	/* 12497 */ "HSUB_S_D\0"
8966	/* 12506 */ "DPSUB_S_D\0"	8966	/* 12506 */ "DPSUB_S_D\0"
8967	/* 12516 */ "FTRUNC_S_D\0"	8967	/* 12516 */ "FTRUNC_S_D\0"
8968	/* 12527 */ "HADD_S_D\0"	8968	/* 12527 */ "HADD_S_D\0"
8969	/* 12536 */ "DPADD_S_D\0"	8969	/* 12536 */ "DPADD_S_D\0"
8970	/* 12546 */ "MOD_S_D\0"	8970	/* 12546 */ "MOD_S_D\0"
8971	/* 12554 */ "CLE_S_D\0"	8971	/* 12554 */ "CLE_S_D\0"
8972	/* 12562 */ "AVE_S_D\0"	8972	/* 12562 */ "AVE_S_D\0"
8973	/* 12570 */ "CLEI_S_D\0"	8973	/* 12570 */ "CLEI_S_D\0"
8974	/* 12579 */ "MINI_S_D\0"	8974	/* 12579 */ "MINI_S_D\0"
8975	/* 12588 */ "CLTI_S_D\0"	8975	/* 12588 */ "CLTI_S_D\0"
8976	/* 12597 */ "MAXI_S_D\0"	8976	/* 12597 */ "MAXI_S_D\0"
8977	/* 12606 */ "MIN_S_D\0"	8977	/* 12606 */ "MIN_S_D\0"
8978	/* 12614 */ "DOTP_S_D\0"	8978	/* 12614 */ "DOTP_S_D\0"
8979	/* 12623 */ "AVER_S_D\0"	8979	/* 12623 */ "AVER_S_D\0"
8980	/* 12632 */ "SUBS_S_D\0"	8980	/* 12632 */ "SUBS_S_D\0"
8981	/* 12641 */ "ADDS_S_D\0"	8981	/* 12641 */ "ADDS_S_D\0"
8982	/* 12650 */ "SAT_S_D\0"	8982	/* 12650 */ "SAT_S_D\0"
8983	/* 12658 */ "CLT_S_D\0"	8983	/* 12658 */ "CLT_S_D\0"
8984	/* 12666 */ "FFINT_S_D\0"	8984	/* 12666 */ "FFINT_S_D\0"
8985	/* 12676 */ "FTINT_S_D\0"	8985	/* 12676 */ "FTINT_S_D\0"
8986	/* 12686 */ "SUBSUU_S_D\0"	8986	/* 12686 */ "SUBSUU_S_D\0"
8987	/* 12697 */ "DIV_S_D\0"	8987	/* 12697 */ "DIV_S_D\0"
8988	/* 12705 */ "MAX_S_D\0"	8988	/* 12705 */ "MAX_S_D\0"
8989	/* 12713 */ "COPY_S_D\0"	8989	/* 12713 */ "COPY_S_D\0"
8990	/* 12722 */ "SPLAT_D\0"	8990	/* 12722 */ "SPLAT_D\0"
8991	/* 12730 */ "BSET_D\0"	8991	/* 12730 */ "BSET_D\0"
8992	/* 12737 */ "FCLT_D\0"	8992	/* 12737 */ "FCLT_D\0"
8993	/* 12744 */ "FSLT_D\0"	8993	/* 12744 */ "FSLT_D\0"
8994	/* 12751 */ "CMP_SLT_D\0"	8994	/* 12751 */ "CMP_SLT_D\0"
8995	/* 12761 */ "FCULT_D\0"	8995	/* 12761 */ "FCULT_D\0"
8996	/* 12769 */ "FSULT_D\0"	8996	/* 12769 */ "FSULT_D\0"
8997	/* 12777 */ "CMP_SULT_D\0"	8997	/* 12777 */ "CMP_SULT_D\0"
8998	/* 12788 */ "CMP_ULT_D\0"	8998	/* 12788 */ "CMP_ULT_D\0"
8999	/* 12798 */ "CMP_LT_D\0"	8999	/* 12798 */ "CMP_LT_D\0"
9000	/* 12807 */ "PCNT_D\0"	9000	/* 12807 */ "PCNT_D\0"
9001	/* 12814 */ "FRINT_D\0"	9001	/* 12814 */ "FRINT_D\0"
9002	/* 12822 */ "INSERT_D\0"	9002	/* 12822 */ "INSERT_D\0"
9003	/* 12831 */ "FSQRT_D\0"	9003	/* 12831 */ "FSQRT_D\0"
9004	/* 12839 */ "FRSQRT_D\0"	9004	/* 12839 */ "FRSQRT_D\0"
9005	/* 12848 */ "ST_D\0"	9005	/* 12848 */ "ST_D\0"
9006	/* 12853 */ "ASUB_U_D\0"	9006	/* 12853 */ "ASUB_U_D\0"
9007	/* 12862 */ "HSUB_U_D\0"	9007	/* 12862 */ "HSUB_U_D\0"
9008	/* 12871 */ "DPSUB_U_D\0"	9008	/* 12871 */ "DPSUB_U_D\0"
9009	/* 12881 */ "FTRUNC_U_D\0"	9009	/* 12881 */ "FTRUNC_U_D\0"
9010	/* 12892 */ "HADD_U_D\0"	9010	/* 12892 */ "HADD_U_D\0"
9011	/* 12901 */ "DPADD_U_D\0"	9011	/* 12901 */ "DPADD_U_D\0"
9012	/* 12911 */ "MOD_U_D\0"	9012	/* 12911 */ "MOD_U_D\0"
9013	/* 12919 */ "CLE_U_D\0"	9013	/* 12919 */ "CLE_U_D\0"
9014	/* 12927 */ "AVE_U_D\0"	9014	/* 12927 */ "AVE_U_D\0"
9015	/* 12935 */ "CLEI_U_D\0"	9015	/* 12935 */ "CLEI_U_D\0"
9016	/* 12944 */ "MINI_U_D\0"	9016	/* 12944 */ "MINI_U_D\0"
9017	/* 12953 */ "CLTI_U_D\0"	9017	/* 12953 */ "CLTI_U_D\0"
9018	/* 12962 */ "MAXI_U_D\0"	9018	/* 12962 */ "MAXI_U_D\0"
9019	/* 12971 */ "MIN_U_D\0"	9019	/* 12971 */ "MIN_U_D\0"
9020	/* 12979 */ "DOTP_U_D\0"	9020	/* 12979 */ "DOTP_U_D\0"
9021	/* 12988 */ "AVER_U_D\0"	9021	/* 12988 */ "AVER_U_D\0"
9022	/* 12997 */ "SUBS_U_D\0"	9022	/* 12997 */ "SUBS_U_D\0"
9023	/* 13006 */ "ADDS_U_D\0"	9023	/* 13006 */ "ADDS_U_D\0"
9024	/* 13015 */ "SUBSUS_U_D\0"	9024	/* 13015 */ "SUBSUS_U_D\0"
9025	/* 13026 */ "SAT_U_D\0"	9025	/* 13026 */ "SAT_U_D\0"
9026	/* 13034 */ "CLT_U_D\0"	9026	/* 13034 */ "CLT_U_D\0"
9027	/* 13042 */ "FFINT_U_D\0"	9027	/* 13042 */ "FFINT_U_D\0"
9028	/* 13052 */ "FTINT_U_D\0"	9028	/* 13052 */ "FTINT_U_D\0"
9029	/* 13062 */ "DIV_U_D\0"	9029	/* 13062 */ "DIV_U_D\0"
9030	/* 13070 */ "MAX_U_D\0"	9030	/* 13070 */ "MAX_U_D\0"
9031	/* 13078 */ "MSUBV_D\0"	9031	/* 13078 */ "MSUBV_D\0"
9032	/* 13086 */ "MADDV_D\0"	9032	/* 13086 */ "MADDV_D\0"
9033	/* 13094 */ "PCKEV_D\0"	9033	/* 13094 */ "PCKEV_D\0"
9034	/* 13102 */ "ILVEV_D\0"	9034	/* 13102 */ "ILVEV_D\0"
9035	/* 13110 */ "FDIV_D\0"	9035	/* 13110 */ "FDIV_D\0"
9036	/* 13117 */ "MULV_D\0"	9036	/* 13117 */ "MULV_D\0"
9037	/* 13124 */ "PseudoTRUNC_W_D\0"	9037	/* 13124 */ "PseudoTRUNC_W_D\0"
9038	/* 13140 */ "FMAX_D\0"	9038	/* 13140 */ "FMAX_D\0"
9039	/* 13147 */ "BZ_D\0"	9039	/* 13147 */ "BZ_D\0"
9040	/* 13152 */ "SELNEZ_D\0"	9040	/* 13152 */ "SELNEZ_D\0"
9041	/* 13161 */ "BNZ_D\0"	9041	/* 13161 */ "BNZ_D\0"
9042	/* 13167 */ "SELEQZ_D\0"	9042	/* 13167 */ "SELEQZ_D\0"
9043	/* 13176 */ "LBE\0"	9043	/* 13176 */ "LBE\0"
9044	/* 13180 */ "PSEUDO_PROBE\0"	9044	/* 13180 */ "PSEUDO_PROBE\0"
9045	/* 13193 */ "SBE\0"	9045	/* 13193 */ "SBE\0"
9046	/* 13197 */ "G_SSUBE\0"	9046	/* 13197 */ "G_SSUBE\0"
9047	/* 13205 */ "G_USUBE\0"	9047	/* 13205 */ "G_USUBE\0"
9048	/* 13213 */ "G_FENCE\0"	9048	/* 13213 */ "G_FENCE\0"
9049	/* 13221 */ "ARITH_FENCE\0"	9049	/* 13221 */ "ARITH_FENCE\0"
9050	/* 13233 */ "REG_SEQUENCE\0"	9050	/* 13233 */ "REG_SEQUENCE\0"
9051	/* 13246 */ "SCE\0"	9051	/* 13246 */ "SCE\0"
9052	/* 13250 */ "G_SADDE\0"	9052	/* 13250 */ "G_SADDE\0"
9053	/* 13258 */ "G_UADDE\0"	9053	/* 13258 */ "G_UADDE\0"
9054	/* 13266 */ "G_FMINNUM_IEEE\0"	9054	/* 13266 */ "G_FMINNUM_IEEE\0"
9055	/* 13281 */ "G_FMAXNUM_IEEE\0"	9055	/* 13281 */ "G_FMAXNUM_IEEE\0"
9056	/* 13296 */ "CACHEE\0"	9056	/* 13296 */ "CACHEE\0"
9057	/* 13303 */ "PREFE\0"	9057	/* 13303 */ "PREFE\0"
9058	/* 13309 */ "BGE\0"	9058	/* 13309 */ "BGE\0"
9059	/* 13313 */ "SGE\0"	9059	/* 13313 */ "SGE\0"
9060	/* 13317 */ "TGE\0"	9060	/* 13317 */ "TGE\0"
9061	/* 13321 */ "CACHE\0"	9061	/* 13321 */ "CACHE\0"
9062	/* 13327 */ "LHE\0"	9062	/* 13327 */ "LHE\0"
9063	/* 13331 */ "SHE\0"	9063	/* 13331 */ "SHE\0"
9064	/* 13335 */ "SIGRIE\0"	9064	/* 13335 */ "SIGRIE\0"
9065	/* 13342 */ "G_JUMP_TABLE\0"	9065	/* 13342 */ "G_JUMP_TABLE\0"
9066	/* 13355 */ "BUNDLE\0"	9066	/* 13355 */ "BUNDLE\0"
9067	/* 13362 */ "LLE\0"	9067	/* 13362 */ "LLE\0"
9068	/* 13366 */ "SLE\0"	9068	/* 13366 */ "SLE\0"
9069	/* 13370 */ "LWLE\0"	9069	/* 13370 */ "LWLE\0"
9070	/* 13375 */ "SWLE\0"	9070	/* 13375 */ "SWLE\0"
9071	/* 13380 */ "BNE\0"	9071	/* 13380 */ "BNE\0"
9072	/* 13384 */ "G_MEMCPY_INLINE\0"	9072	/* 13384 */ "G_MEMCPY_INLINE\0"
9073	/* 13400 */ "SNE\0"	9073	/* 13400 */ "SNE\0"
9074	/* 13404 */ "TNE\0"	9074	/* 13404 */ "TNE\0"
9075	/* 13408 */ "LOCAL_ESCAPE\0"	9075	/* 13408 */ "LOCAL_ESCAPE\0"
9076	/* 13421 */ "DVPE\0"	9076	/* 13421 */ "DVPE\0"
9077	/* 13426 */ "EVPE\0"	9077	/* 13426 */ "EVPE\0"
9078	/* 13431 */ "G_INDEXED_STORE\0"	9078	/* 13431 */ "G_INDEXED_STORE\0"
9079	/* 13447 */ "G_STORE\0"	9079	/* 13447 */ "G_STORE\0"
9080	/* 13455 */ "LWRE\0"	9080	/* 13455 */ "LWRE\0"
9081	/* 13460 */ "SWRE\0"	9081	/* 13460 */ "SWRE\0"
9082	/* 13465 */ "G_BITREVERSE\0"	9082	/* 13465 */ "G_BITREVERSE\0"
9083	/* 13478 */ "PAUSE\0"	9083	/* 13478 */ "PAUSE\0"
9084	/* 13484 */ "DBG_VALUE\0"	9084	/* 13484 */ "DBG_VALUE\0"
9085	/* 13494 */ "G_GLOBAL_VALUE\0"	9085	/* 13494 */ "G_GLOBAL_VALUE\0"
9086	/* 13509 */ "G_MEMMOVE\0"	9086	/* 13509 */ "G_MEMMOVE\0"
9087	/* 13519 */ "LWE\0"	9087	/* 13519 */ "LWE\0"
9088	/* 13523 */ "SWE\0"	9088	/* 13523 */ "SWE\0"
9089	/* 13527 */ "G_FREEZE\0"	9089	/* 13527 */ "G_FREEZE\0"
9090	/* 13536 */ "G_FCANONICALIZE\0"	9090	/* 13536 */ "G_FCANONICALIZE\0"
9091	/* 13552 */ "LBuE\0"	9091	/* 13552 */ "LBuE\0"
9092	/* 13557 */ "LHuE\0"	9092	/* 13557 */ "LHuE\0"
9093	/* 13562 */ "BC1F\0"	9093	/* 13562 */ "BC1F\0"
9094	/* 13567 */ "G_CTLZ_ZERO_UNDEF\0"	9094	/* 13567 */ "G_CTLZ_ZERO_UNDEF\0"
9095	/* 13585 */ "G_CTTZ_ZERO_UNDEF\0"	9095	/* 13585 */ "G_CTTZ_ZERO_UNDEF\0"
9096	/* 13603 */ "G_IMPLICIT_DEF\0"	9096	/* 13603 */ "G_IMPLICIT_DEF\0"
9097	/* 13618 */ "PREF\0"	9097	/* 13618 */ "PREF\0"
9098	/* 13623 */ "DBG_INSTR_REF\0"	9098	/* 13623 */ "DBG_INSTR_REF\0"
9099	/* 13637 */ "TLBINVF\0"	9099	/* 13637 */ "TLBINVF\0"
9100	/* 13645 */ "TLBGINVF\0"	9100	/* 13645 */ "TLBGINVF\0"
9101	/* 13654 */ "G_FNEG\0"	9101	/* 13654 */ "G_FNEG\0"
9102	/* 13661 */ "TAILCALLHB64R6REG\0"	9102	/* 13661 */ "TAILCALLHB64R6REG\0"
9103	/* 13679 */ "TAILCALL64R6REG\0"	9103	/* 13679 */ "TAILCALL64R6REG\0"
9104	/* 13695 */ "TAILCALLHBR6REG\0"	9104	/* 13695 */ "TAILCALLHBR6REG\0"
9105	/* 13711 */ "TAILCALLR6REG\0"	9105	/* 13711 */ "TAILCALLR6REG\0"
9106	/* 13725 */ "EXTRACT_SUBREG\0"	9106	/* 13725 */ "EXTRACT_SUBREG\0"
9107	/* 13740 */ "INSERT_SUBREG\0"	9107	/* 13740 */ "INSERT_SUBREG\0"
9108	/* 13754 */ "TAILCALLREG\0"	9108	/* 13754 */ "TAILCALLREG\0"
9109	/* 13766 */ "G_SEXT_INREG\0"	9109	/* 13766 */ "G_SEXT_INREG\0"
9110	/* 13779 */ "SUBREG_TO_REG\0"	9110	/* 13779 */ "SUBREG_TO_REG\0"
9111	/* 13793 */ "G_ATOMIC_CMPXCHG\0"	9111	/* 13793 */ "G_ATOMIC_CMPXCHG\0"
9112	/* 13810 */ "G_ATOMICRMW_XCHG\0"	9112	/* 13810 */ "G_ATOMICRMW_XCHG\0"
9113	/* 13827 */ "G_FLOG\0"	9113	/* 13827 */ "G_FLOG\0"
9114	/* 13834 */ "G_VAARG\0"	9114	/* 13834 */ "G_VAARG\0"
9115	/* 13842 */ "PREALLOCATED_ARG\0"	9115	/* 13842 */ "PREALLOCATED_ARG\0"
9116	/* 13859 */ "CRC32H\0"	9116	/* 13859 */ "CRC32H\0"
9117	/* 13866 */ "DSBH\0"	9117	/* 13866 */ "DSBH\0"
9118	/* 13871 */ "WSBH\0"	9118	/* 13871 */ "WSBH\0"
9119	/* 13876 */ "CRC32CH\0"	9119	/* 13876 */ "CRC32CH\0"
9120	/* 13884 */ "SEH\0"	9120	/* 13884 */ "SEH\0"
9121	/* 13888 */ "G_SMULH\0"	9121	/* 13888 */ "G_SMULH\0"
9122	/* 13896 */ "G_UMULH\0"	9122	/* 13896 */ "G_UMULH\0"
9123	/* 13904 */ "SHRA_PH\0"	9123	/* 13904 */ "SHRA_PH\0"
9124	/* 13912 */ "PRECRQ_QB_PH\0"	9124	/* 13912 */ "PRECRQ_QB_PH\0"
9125	/* 13925 */ "PRECR_QB_PH\0"	9125	/* 13925 */ "PRECR_QB_PH\0"
9126	/* 13937 */ "PRECRQU_S_QB_PH\0"	9126	/* 13937 */ "PRECRQU_S_QB_PH\0"
9127	/* 13953 */ "PseudoCMP_LE_PH\0"	9127	/* 13953 */ "PseudoCMP_LE_PH\0"
9128	/* 13969 */ "SUBQH_PH\0"	9128	/* 13969 */ "SUBQH_PH\0"
9129	/* 13978 */ "ADDQH_PH\0"	9129	/* 13978 */ "ADDQH_PH\0"
9130	/* 13987 */ "PseudoPICK_PH\0"	9130	/* 13987 */ "PseudoPICK_PH\0"
9131	/* 14001 */ "SHLL_PH\0"	9131	/* 14001 */ "SHLL_PH\0"
9132	/* 14009 */ "REPL_PH\0"	9132	/* 14009 */ "REPL_PH\0"
9133	/* 14017 */ "SHRL_PH\0"	9133	/* 14017 */ "SHRL_PH\0"
9134	/* 14025 */ "PACKRL_PH\0"	9134	/* 14025 */ "PACKRL_PH\0"
9135	/* 14035 */ "MUL_PH\0"	9135	/* 14035 */ "MUL_PH\0"
9136	/* 14042 */ "SUBQ_PH\0"	9136	/* 14042 */ "SUBQ_PH\0"
9137	/* 14050 */ "ADDQ_PH\0"	9137	/* 14050 */ "ADDQ_PH\0"
9138	/* 14058 */ "PseudoCMP_EQ_PH\0"	9138	/* 14058 */ "PseudoCMP_EQ_PH\0"
9139	/* 14074 */ "SHRA_R_PH\0"	9139	/* 14074 */ "SHRA_R_PH\0"
9140	/* 14084 */ "SUBQH_R_PH\0"	9140	/* 14084 */ "SUBQH_R_PH\0"
9141	/* 14095 */ "ADDQH_R_PH\0"	9141	/* 14095 */ "ADDQH_R_PH\0"
9142	/* 14106 */ "SHRAV_R_PH\0"	9142	/* 14106 */ "SHRAV_R_PH\0"
9143	/* 14117 */ "MULQ_RS_PH\0"	9143	/* 14117 */ "MULQ_RS_PH\0"
9144	/* 14128 */ "SHLL_S_PH\0"	9144	/* 14128 */ "SHLL_S_PH\0"
9145	/* 14138 */ "MUL_S_PH\0"	9145	/* 14138 */ "MUL_S_PH\0"
9146	/* 14147 */ "SUBQ_S_PH\0"	9146	/* 14147 */ "SUBQ_S_PH\0"
9147	/* 14157 */ "ADDQ_S_PH\0"	9147	/* 14157 */ "ADDQ_S_PH\0"
9148	/* 14167 */ "MULQ_S_PH\0"	9148	/* 14167 */ "MULQ_S_PH\0"
9149	/* 14177 */ "ABSQ_S_PH\0"	9149	/* 14177 */ "ABSQ_S_PH\0"
9150	/* 14187 */ "SUBU_S_PH\0"	9150	/* 14187 */ "SUBU_S_PH\0"
9151	/* 14197 */ "ADDU_S_PH\0"	9151	/* 14197 */ "ADDU_S_PH\0"
9152	/* 14207 */ "SHLLV_S_PH\0"	9152	/* 14207 */ "SHLLV_S_PH\0"
9153	/* 14218 */ "PseudoCMP_LT_PH\0"	9153	/* 14218 */ "PseudoCMP_LT_PH\0"
9154	/* 14234 */ "SUBU_PH\0"	9154	/* 14234 */ "SUBU_PH\0"
9155	/* 14242 */ "ADDU_PH\0"	9155	/* 14242 */ "ADDU_PH\0"
9156	/* 14250 */ "SHRAV_PH\0"	9156	/* 14250 */ "SHRAV_PH\0"
9157	/* 14259 */ "SHLLV_PH\0"	9157	/* 14259 */ "SHLLV_PH\0"
9158	/* 14268 */ "REPLV_PH\0"	9158	/* 14268 */ "REPLV_PH\0"
9159	/* 14277 */ "SHRLV_PH\0"	9159	/* 14277 */ "SHRLV_PH\0"
9160	/* 14286 */ "DPA_W_PH\0"	9160	/* 14286 */ "DPA_W_PH\0"
9161	/* 14295 */ "MULSA_W_PH\0"	9161	/* 14295 */ "MULSA_W_PH\0"
9162	/* 14306 */ "DPAQX_SA_W_PH\0"	9162	/* 14306 */ "DPAQX_SA_W_PH\0"
9163	/* 14320 */ "DPSQX_SA_W_PH\0"	9163	/* 14320 */ "DPSQX_SA_W_PH\0"
9164	/* 14334 */ "DPS_W_PH\0"	9164	/* 14334 */ "DPS_W_PH\0"
9165	/* 14343 */ "DPAQ_S_W_PH\0"	9165	/* 14343 */ "DPAQ_S_W_PH\0"
9166	/* 14355 */ "MULSAQ_S_W_PH\0"	9166	/* 14355 */ "MULSAQ_S_W_PH\0"
9167	/* 14369 */ "DPSQ_S_W_PH\0"	9167	/* 14369 */ "DPSQ_S_W_PH\0"
9168	/* 14381 */ "DPAQX_S_W_PH\0"	9168	/* 14381 */ "DPAQX_S_W_PH\0"
9169	/* 14394 */ "DPSQX_S_W_PH\0"	9169	/* 14394 */ "DPSQX_S_W_PH\0"
9170	/* 14407 */ "DPAX_W_PH\0"	9170	/* 14407 */ "DPAX_W_PH\0"
9171	/* 14417 */ "DPSX_W_PH\0"	9171	/* 14417 */ "DPSX_W_PH\0"
9172	/* 14427 */ "SH\0"	9172	/* 14427 */ "SH\0"
9173	/* 14430 */ "DMUH\0"	9173	/* 14430 */ "DMUH\0"
9174	/* 14435 */ "SRA_H\0"	9174	/* 14435 */ "SRA_H\0"
9175	/* 14441 */ "ADD_A_H\0"	9175	/* 14441 */ "ADD_A_H\0"
9176	/* 14449 */ "MIN_A_H\0"	9176	/* 14449 */ "MIN_A_H\0"
9177	/* 14457 */ "ADDS_A_H\0"	9177	/* 14457 */ "ADDS_A_H\0"
9178	/* 14466 */ "MAX_A_H\0"	9178	/* 14466 */ "MAX_A_H\0"
9179	/* 14474 */ "NLOC_H\0"	9179	/* 14474 */ "NLOC_H\0"
9180	/* 14481 */ "NLZC_H\0"	9180	/* 14481 */ "NLZC_H\0"
9181	/* 14488 */ "SLD_H\0"	9181	/* 14488 */ "SLD_H\0"
9182	/* 14494 */ "PCKOD_H\0"	9182	/* 14494 */ "PCKOD_H\0"
9183	/* 14502 */ "ILVOD_H\0"	9183	/* 14502 */ "ILVOD_H\0"
9184	/* 14510 */ "INSVE_H\0"	9184	/* 14510 */ "INSVE_H\0"
9185	/* 14518 */ "VSHF_H\0"	9185	/* 14518 */ "VSHF_H\0"
9186	/* 14525 */ "BNEG_H\0"	9186	/* 14525 */ "BNEG_H\0"
9187	/* 14532 */ "SRAI_H\0"	9187	/* 14532 */ "SRAI_H\0"
9188	/* 14539 */ "SLDI_H\0"	9188	/* 14539 */ "SLDI_H\0"
9189	/* 14546 */ "BNEGI_H\0"	9189	/* 14546 */ "BNEGI_H\0"
9190	/* 14554 */ "SLLI_H\0"	9190	/* 14554 */ "SLLI_H\0"
9191	/* 14561 */ "SRLI_H\0"	9191	/* 14561 */ "SRLI_H\0"
9192	/* 14568 */ "BINSLI_H\0"	9192	/* 14568 */ "BINSLI_H\0"
9193	/* 14577 */ "CEQI_H\0"	9193	/* 14577 */ "CEQI_H\0"
9194	/* 14584 */ "SRARI_H\0"	9194	/* 14584 */ "SRARI_H\0"
9195	/* 14592 */ "BCLRI_H\0"	9195	/* 14592 */ "BCLRI_H\0"
9196	/* 14600 */ "SRLRI_H\0"	9196	/* 14600 */ "SRLRI_H\0"
9197	/* 14608 */ "BINSRI_H\0"	9197	/* 14608 */ "BINSRI_H\0"
9198	/* 14617 */ "SPLATI_H\0"	9198	/* 14617 */ "SPLATI_H\0"
9199	/* 14626 */ "BSETI_H\0"	9199	/* 14626 */ "BSETI_H\0"
9200	/* 14634 */ "SUBVI_H\0"	9200	/* 14634 */ "SUBVI_H\0"
9201	/* 14642 */ "ADDVI_H\0"	9201	/* 14642 */ "ADDVI_H\0"
9202	/* 14650 */ "FILL_H\0"	9202	/* 14650 */ "FILL_H\0"
9203	/* 14657 */ "SLL_H\0"	9203	/* 14657 */ "SLL_H\0"
9204	/* 14663 */ "SRL_H\0"	9204	/* 14663 */ "SRL_H\0"
9205	/* 14669 */ "BINSL_H\0"	9205	/* 14669 */ "BINSL_H\0"
9206	/* 14677 */ "ILVL_H\0"	9206	/* 14677 */ "ILVL_H\0"
9207	/* 14684 */ "FEXDO_H\0"	9207	/* 14684 */ "FEXDO_H\0"
9208	/* 14692 */ "CEQ_H\0"	9208	/* 14692 */ "CEQ_H\0"
9209	/* 14698 */ "FTQ_H\0"	9209	/* 14698 */ "FTQ_H\0"
9210	/* 14704 */ "MSUB_Q_H\0"	9210	/* 14704 */ "MSUB_Q_H\0"
9211	/* 14713 */ "MADD_Q_H\0"	9211	/* 14713 */ "MADD_Q_H\0"
9212	/* 14722 */ "MUL_Q_H\0"	9212	/* 14722 */ "MUL_Q_H\0"
9213	/* 14730 */ "MSUBR_Q_H\0"	9213	/* 14730 */ "MSUBR_Q_H\0"
9214	/* 14740 */ "MADDR_Q_H\0"	9214	/* 14740 */ "MADDR_Q_H\0"
9215	/* 14750 */ "MULR_Q_H\0"	9215	/* 14750 */ "MULR_Q_H\0"
9216	/* 14759 */ "SRAR_H\0"	9216	/* 14759 */ "SRAR_H\0"
9217	/* 14766 */ "BCLR_H\0"	9217	/* 14766 */ "BCLR_H\0"
9218	/* 14773 */ "SRLR_H\0"	9218	/* 14773 */ "SRLR_H\0"
9219	/* 14780 */ "BINSR_H\0"	9219	/* 14780 */ "BINSR_H\0"
9220	/* 14788 */ "ILVR_H\0"	9220	/* 14788 */ "ILVR_H\0"
9221	/* 14795 */ "ASUB_S_H\0"	9221	/* 14795 */ "ASUB_S_H\0"
9222	/* 14804 */ "HSUB_S_H\0"	9222	/* 14804 */ "HSUB_S_H\0"
9223	/* 14813 */ "DPSUB_S_H\0"	9223	/* 14813 */ "DPSUB_S_H\0"
9224	/* 14823 */ "HADD_S_H\0"	9224	/* 14823 */ "HADD_S_H\0"
9225	/* 14832 */ "DPADD_S_H\0"	9225	/* 14832 */ "DPADD_S_H\0"
9226	/* 14842 */ "MOD_S_H\0"	9226	/* 14842 */ "MOD_S_H\0"
9227	/* 14850 */ "CLE_S_H\0"	9227	/* 14850 */ "CLE_S_H\0"
9228	/* 14858 */ "AVE_S_H\0"	9228	/* 14858 */ "AVE_S_H\0"
9229	/* 14866 */ "CLEI_S_H\0"	9229	/* 14866 */ "CLEI_S_H\0"
9230	/* 14875 */ "MINI_S_H\0"	9230	/* 14875 */ "MINI_S_H\0"
9231	/* 14884 */ "CLTI_S_H\0"	9231	/* 14884 */ "CLTI_S_H\0"
9232	/* 14893 */ "MAXI_S_H\0"	9232	/* 14893 */ "MAXI_S_H\0"
9233	/* 14902 */ "MIN_S_H\0"	9233	/* 14902 */ "MIN_S_H\0"
9234	/* 14910 */ "DOTP_S_H\0"	9234	/* 14910 */ "DOTP_S_H\0"
9235	/* 14919 */ "AVER_S_H\0"	9235	/* 14919 */ "AVER_S_H\0"
9236	/* 14928 */ "EXTR_S_H\0"	9236	/* 14928 */ "EXTR_S_H\0"
9237	/* 14937 */ "SUBS_S_H\0"	9237	/* 14937 */ "SUBS_S_H\0"
9238	/* 14946 */ "ADDS_S_H\0"	9238	/* 14946 */ "ADDS_S_H\0"
9239	/* 14955 */ "SAT_S_H\0"	9239	/* 14955 */ "SAT_S_H\0"
9240	/* 14963 */ "CLT_S_H\0"	9240	/* 14963 */ "CLT_S_H\0"
9241	/* 14971 */ "SUBSUU_S_H\0"	9241	/* 14971 */ "SUBSUU_S_H\0"
9242	/* 14982 */ "DIV_S_H\0"	9242	/* 14982 */ "DIV_S_H\0"
9243	/* 14990 */ "EXTRV_S_H\0"	9243	/* 14990 */ "EXTRV_S_H\0"
9244	/* 15000 */ "MAX_S_H\0"	9244	/* 15000 */ "MAX_S_H\0"
9245	/* 15008 */ "COPY_S_H\0"	9245	/* 15008 */ "COPY_S_H\0"
9246	/* 15017 */ "SPLAT_H\0"	9246	/* 15017 */ "SPLAT_H\0"
9247	/* 15025 */ "BSET_H\0"	9247	/* 15025 */ "BSET_H\0"
9248	/* 15032 */ "PCNT_H\0"	9248	/* 15032 */ "PCNT_H\0"
9249	/* 15039 */ "INSERT_H\0"	9249	/* 15039 */ "INSERT_H\0"
9250	/* 15048 */ "ST_H\0"	9250	/* 15048 */ "ST_H\0"
9251	/* 15053 */ "ASUB_U_H\0"	9251	/* 15053 */ "ASUB_U_H\0"
9252	/* 15062 */ "HSUB_U_H\0"	9252	/* 15062 */ "HSUB_U_H\0"
9253	/* 15071 */ "DPSUB_U_H\0"	9253	/* 15071 */ "DPSUB_U_H\0"
9254	/* 15081 */ "HADD_U_H\0"	9254	/* 15081 */ "HADD_U_H\0"
9255	/* 15090 */ "DPADD_U_H\0"	9255	/* 15090 */ "DPADD_U_H\0"
9256	/* 15100 */ "MOD_U_H\0"	9256	/* 15100 */ "MOD_U_H\0"
9257	/* 15108 */ "CLE_U_H\0"	9257	/* 15108 */ "CLE_U_H\0"
9258	/* 15116 */ "AVE_U_H\0"	9258	/* 15116 */ "AVE_U_H\0"
9259	/* 15124 */ "CLEI_U_H\0"	9259	/* 15124 */ "CLEI_U_H\0"
9260	/* 15133 */ "MINI_U_H\0"	9260	/* 15133 */ "MINI_U_H\0"
9261	/* 15142 */ "CLTI_U_H\0"	9261	/* 15142 */ "CLTI_U_H\0"
9262	/* 15151 */ "MAXI_U_H\0"	9262	/* 15151 */ "MAXI_U_H\0"
9263	/* 15160 */ "MIN_U_H\0"	9263	/* 15160 */ "MIN_U_H\0"
9264	/* 15168 */ "DOTP_U_H\0"	9264	/* 15168 */ "DOTP_U_H\0"
9265	/* 15177 */ "AVER_U_H\0"	9265	/* 15177 */ "AVER_U_H\0"
9266	/* 15186 */ "SUBS_U_H\0"	9266	/* 15186 */ "SUBS_U_H\0"
9267	/* 15195 */ "ADDS_U_H\0"	9267	/* 15195 */ "ADDS_U_H\0"
9268	/* 15204 */ "SUBSUS_U_H\0"	9268	/* 15204 */ "SUBSUS_U_H\0"
9269	/* 15215 */ "SAT_U_H\0"	9269	/* 15215 */ "SAT_U_H\0"
9270	/* 15223 */ "CLT_U_H\0"	9270	/* 15223 */ "CLT_U_H\0"
9271	/* 15231 */ "DIV_U_H\0"	9271	/* 15231 */ "DIV_U_H\0"
9272	/* 15239 */ "MAX_U_H\0"	9272	/* 15239 */ "MAX_U_H\0"
9273	/* 15247 */ "COPY_U_H\0"	9273	/* 15247 */ "COPY_U_H\0"
9274	/* 15256 */ "MSUBV_H\0"	9274	/* 15256 */ "MSUBV_H\0"
9275	/* 15264 */ "MADDV_H\0"	9275	/* 15264 */ "MADDV_H\0"
9276	/* 15272 */ "PCKEV_H\0"	9276	/* 15272 */ "PCKEV_H\0"
9277	/* 15280 */ "ILVEV_H\0"	9277	/* 15280 */ "ILVEV_H\0"
9278	/* 15288 */ "MULV_H\0"	9278	/* 15288 */ "MULV_H\0"
9279	/* 15295 */ "BZ_H\0"	9279	/* 15295 */ "BZ_H\0"
9280	/* 15300 */ "BNZ_H\0"	9280	/* 15300 */ "BNZ_H\0"
9281	/* 15306 */ "SYNCI\0"	9281	/* 15306 */ "SYNCI\0"
9282	/* 15312 */ "DI\0"	9282	/* 15312 */ "DI\0"
9283	/* 15315 */ "TGEI\0"	9283	/* 15315 */ "TGEI\0"
9284	/* 15320 */ "TNEI\0"	9284	/* 15320 */ "TNEI\0"
9285	/* 15325 */ "DAHI\0"	9285	/* 15325 */ "DAHI\0"
9286	/* 15330 */ "PseudoMFHI\0"	9286	/* 15330 */ "PseudoMFHI\0"
9287	/* 15341 */ "PseudoMTLOHI\0"	9287	/* 15341 */ "PseudoMTLOHI\0"
9288	/* 15354 */ "DBG_PHI\0"	9288	/* 15354 */ "DBG_PHI\0"
9289	/* 15362 */ "MFTHI\0"	9289	/* 15362 */ "MFTHI\0"
9290	/* 15368 */ "MTHI\0"	9290	/* 15368 */ "MTHI\0"
9291	/* 15373 */ "MTTHI\0"	9291	/* 15373 */ "MTTHI\0"
9292	/* 15379 */ "TEQI\0"	9292	/* 15379 */ "TEQI\0"
9293	/* 15384 */ "G_FPTOSI\0"	9293	/* 15384 */ "G_FPTOSI\0"
9294	/* 15393 */ "DATI\0"	9294	/* 15393 */ "DATI\0"
9295	/* 15398 */ "TLTI\0"	9295	/* 15398 */ "TLTI\0"
9296	/* 15403 */ "DAUI\0"	9296	/* 15403 */ "DAUI\0"
9297	/* 15408 */ "G_FPTOUI\0"	9297	/* 15408 */ "G_FPTOUI\0"
9298	/* 15417 */ "GINVI\0"	9298	/* 15417 */ "GINVI\0"
9299	/* 15423 */ "TLBWI\0"	9299	/* 15423 */ "TLBWI\0"
9300	/* 15429 */ "TLBGWI\0"	9300	/* 15429 */ "TLBGWI\0"
9301	/* 15436 */ "G_FPOWI\0"	9301	/* 15436 */ "G_FPOWI\0"
9302	/* 15444 */ "MOVN_I64_I\0"	9302	/* 15444 */ "MOVN_I64_I\0"
9303	/* 15455 */ "MOVZ_I64_I\0"	9303	/* 15455 */ "MOVZ_I64_I\0"
9304	/* 15466 */ "MOVF_I\0"	9304	/* 15466 */ "MOVF_I\0"
9305	/* 15473 */ "PseudoSELECTFP_F_I\0"	9305	/* 15473 */ "PseudoSELECTFP_F_I\0"
9306	/* 15492 */ "MOVN_I_I\0"	9306	/* 15492 */ "MOVN_I_I\0"
9307	/* 15501 */ "MOVZ_I_I\0"	9307	/* 15501 */ "MOVZ_I_I\0"
9308	/* 15510 */ "PseudoD_SELECT_I\0"	9308	/* 15510 */ "PseudoD_SELECT_I\0"
9309	/* 15527 */ "PseudoSELECT_I\0"	9309	/* 15527 */ "PseudoSELECT_I\0"
9310	/* 15542 */ "MOVT_I\0"	9310	/* 15542 */ "MOVT_I\0"
9311	/* 15549 */ "PseudoSELECTFP_T_I\0"	9311	/* 15549 */ "PseudoSELECTFP_T_I\0"
9312	/* 15568 */ "J\0"	9312	/* 15568 */ "J\0"
9313	/* 15570 */ "BREAK\0"	9313	/* 15570 */ "BREAK\0"
9314	/* 15576 */ "FORK\0"	9314	/* 15576 */ "FORK\0"
9315	/* 15581 */ "G_PTRMASK\0"	9315	/* 15581 */ "G_PTRMASK\0"
9316	/* 15591 */ "BAL\0"	9316	/* 15591 */ "BAL\0"
9317	/* 15595 */ "JAL\0"	9317	/* 15595 */ "JAL\0"
9318	/* 15599 */ "BGEZAL\0"	9318	/* 15599 */ "BGEZAL\0"
9319	/* 15606 */ "BLTZAL\0"	9319	/* 15606 */ "BLTZAL\0"
9320	/* 15613 */ "MULEU_S_PH_QBL\0"	9320	/* 15613 */ "MULEU_S_PH_QBL\0"
9321	/* 15628 */ "PRECEU_PH_QBL\0"	9321	/* 15628 */ "PRECEU_PH_QBL\0"
9322	/* 15642 */ "PRECEQU_PH_QBL\0"	9322	/* 15642 */ "PRECEQU_PH_QBL\0"
9323	/* 15657 */ "DPAU_H_QBL\0"	9323	/* 15657 */ "DPAU_H_QBL\0"
9324	/* 15668 */ "DPSU_H_QBL\0"	9324	/* 15668 */ "DPSU_H_QBL\0"
9325	/* 15679 */ "LDL\0"	9325	/* 15679 */ "LDL\0"
9326	/* 15683 */ "SDL\0"	9326	/* 15683 */ "SDL\0"
9327	/* 15687 */ "GC_LABEL\0"	9327	/* 15687 */ "GC_LABEL\0"
9328	/* 15696 */ "DBG_LABEL\0"	9328	/* 15696 */ "DBG_LABEL\0"
9329	/* 15706 */ "EH_LABEL\0"	9329	/* 15706 */ "EH_LABEL\0"
9330	/* 15715 */ "ANNOTATION_LABEL\0"	9330	/* 15715 */ "ANNOTATION_LABEL\0"
9331	/* 15732 */ "BGEL\0"	9331	/* 15732 */ "BGEL\0"
9332	/* 15737 */ "BLEL\0"	9332	/* 15737 */ "BLEL\0"
9333	/* 15742 */ "BNEL\0"	9333	/* 15742 */ "BNEL\0"
9334	/* 15747 */ "ICALL_BRANCH_FUNNEL\0"	9334	/* 15747 */ "ICALL_BRANCH_FUNNEL\0"
9335	/* 15767 */ "BC1FL\0"	9335	/* 15767 */ "BC1FL\0"
9336	/* 15773 */ "MAQ_SA_W_PHL\0"	9336	/* 15773 */ "MAQ_SA_W_PHL\0"
9337	/* 15786 */ "PRECEQ_W_PHL\0"	9337	/* 15786 */ "PRECEQ_W_PHL\0"
9338	/* 15799 */ "MAQ_S_W_PHL\0"	9338	/* 15799 */ "MAQ_S_W_PHL\0"
9339	/* 15811 */ "MULEQ_S_W_PHL\0"	9339	/* 15811 */ "MULEQ_S_W_PHL\0"
9340	/* 15825 */ "G_FSHL\0"	9340	/* 15825 */ "G_FSHL\0"
9341	/* 15832 */ "G_SHL\0"	9341	/* 15832 */ "G_SHL\0"
9342	/* 15838 */ "G_FCEIL\0"	9342	/* 15838 */ "G_FCEIL\0"
9343	/* 15846 */ "TAILCALL\0"	9343	/* 15846 */ "TAILCALL\0"
9344	/* 15855 */ "HYPCALL\0"	9344	/* 15855 */ "HYPCALL\0"
9345	/* 15863 */ "SYSCALL\0"	9345	/* 15863 */ "SYSCALL\0"
9346	/* 15871 */ "PATCHABLE_TAIL_CALL\0"	9346	/* 15871 */ "PATCHABLE_TAIL_CALL\0"
9347	/* 15891 */ "PATCHABLE_TYPED_EVENT_CALL\0"	9347	/* 15891 */ "PATCHABLE_TYPED_EVENT_CALL\0"
9348	/* 15918 */ "PATCHABLE_EVENT_CALL\0"	9348	/* 15918 */ "PATCHABLE_EVENT_CALL\0"
9349	/* 15939 */ "FENTRY_CALL\0"	9349	/* 15939 */ "FENTRY_CALL\0"
9350	/* 15951 */ "BGEZALL\0"	9350	/* 15951 */ "BGEZALL\0"
9351	/* 15959 */ "BLTZALL\0"	9351	/* 15959 */ "BLTZALL\0"
9352	/* 15967 */ "KILL\0"	9352	/* 15967 */ "KILL\0"
9353	/* 15972 */ "DSLL\0"	9353	/* 15972 */ "DSLL\0"
9354	/* 15977 */ "G_CONSTANT_POOL\0"	9354	/* 15977 */ "G_CONSTANT_POOL\0"
9355	/* 15993 */ "DROL\0"	9355	/* 15993 */ "DROL\0"
9356	/* 15998 */ "BEQL\0"	9356	/* 15998 */ "BEQL\0"
9357	/* 16003 */ "DSRL\0"	9357	/* 16003 */ "DSRL\0"
9358	/* 16008 */ "BC1TL\0"	9358	/* 16008 */ "BC1TL\0"
9359	/* 16014 */ "BGTL\0"	9359	/* 16014 */ "BGTL\0"
9360	/* 16019 */ "BLTL\0"	9360	/* 16019 */ "BLTL\0"
9361	/* 16024 */ "G_ROTL\0"	9361	/* 16024 */ "G_ROTL\0"
9362	/* 16031 */ "BGEUL\0"	9362	/* 16031 */ "BGEUL\0"
9363	/* 16037 */ "BLEUL\0"	9363	/* 16037 */ "BLEUL\0"
9364	/* 16043 */ "DMUL\0"	9364	/* 16043 */ "DMUL\0"
9365	/* 16048 */ "G_VECREDUCE_FMUL\0"	9365	/* 16048 */ "G_VECREDUCE_FMUL\0"
9366	/* 16065 */ "G_FMUL\0"	9366	/* 16065 */ "G_FMUL\0"
9367	/* 16072 */ "G_VECREDUCE_SEQ_FMUL\0"	9367	/* 16072 */ "G_VECREDUCE_SEQ_FMUL\0"
9368	/* 16093 */ "G_STRICT_FMUL\0"	9368	/* 16093 */ "G_STRICT_FMUL\0"
9369	/* 16107 */ "G_VECREDUCE_MUL\0"	9369	/* 16107 */ "G_VECREDUCE_MUL\0"
9370	/* 16123 */ "G_MUL\0"	9370	/* 16123 */ "G_MUL\0"
9371	/* 16129 */ "BGTUL\0"	9371	/* 16129 */ "BGTUL\0"
9372	/* 16135 */ "BLTUL\0"	9372	/* 16135 */ "BLTUL\0"
9373	/* 16141 */ "LWL\0"	9373	/* 16141 */ "LWL\0"
9374	/* 16145 */ "SWL\0"	9374	/* 16145 */ "SWL\0"
9375	/* 16149 */ "BGEZL\0"	9375	/* 16149 */ "BGEZL\0"
9376	/* 16155 */ "BLEZL\0"	9376	/* 16155 */ "BLEZL\0"
9377	/* 16161 */ "BGTZL\0"	9377	/* 16161 */ "BGTZL\0"
9378	/* 16167 */ "BLTZL\0"	9378	/* 16167 */ "BLTZL\0"
9379	/* 16173 */ "PseudoCVT_D64_L\0"	9379	/* 16173 */ "PseudoCVT_D64_L\0"
9380	/* 16189 */ "PseudoCVT_S_L\0"	9380	/* 16189 */ "PseudoCVT_S_L\0"
9381	/* 16203 */ "G_FREM\0"	9381	/* 16203 */ "G_FREM\0"
9382	/* 16210 */ "G_STRICT_FREM\0"	9382	/* 16210 */ "G_STRICT_FREM\0"
9383	/* 16224 */ "G_SREM\0"	9383	/* 16224 */ "G_SREM\0"
9384	/* 16231 */ "G_UREM\0"	9384	/* 16231 */ "G_UREM\0"
9385	/* 16238 */ "G_SDIVREM\0"	9385	/* 16238 */ "G_SDIVREM\0"
9386	/* 16248 */ "G_UDIVREM\0"	9386	/* 16248 */ "G_UDIVREM\0"
9387	/* 16258 */ "MFGC0_MM\0"	9387	/* 16258 */ "MFGC0_MM\0"
9388	/* 16267 */ "MFHGC0_MM\0"	9388	/* 16267 */ "MFHGC0_MM\0"
9389	/* 16277 */ "MTHGC0_MM\0"	9389	/* 16277 */ "MTHGC0_MM\0"
9390	/* 16287 */ "MTGC0_MM\0"	9390	/* 16287 */ "MTGC0_MM\0"
9391	/* 16296 */ "CFC1_MM\0"	9391	/* 16296 */ "CFC1_MM\0"
9392	/* 16304 */ "MFC1_MM\0"	9392	/* 16304 */ "MFC1_MM\0"
9393	/* 16312 */ "CTC1_MM\0"	9393	/* 16312 */ "CTC1_MM\0"
9394	/* 16320 */ "MTC1_MM\0"	9394	/* 16320 */ "MTC1_MM\0"
9395	/* 16328 */ "LWC1_MM\0"	9395	/* 16328 */ "LWC1_MM\0"
9396	/* 16336 */ "SWC1_MM\0"	9396	/* 16336 */ "SWC1_MM\0"
9397	/* 16344 */ "LUXC1_MM\0"	9397	/* 16344 */ "LUXC1_MM\0"
9398	/* 16353 */ "SUXC1_MM\0"	9398	/* 16353 */ "SUXC1_MM\0"
9399	/* 16362 */ "LWXC1_MM\0"	9399	/* 16362 */ "LWXC1_MM\0"
9400	/* 16371 */ "SWXC1_MM\0"	9400	/* 16371 */ "SWXC1_MM\0"
9401	/* 16380 */ "MFHC1_D32_MM\0"	9401	/* 16380 */ "MFHC1_D32_MM\0"
9402	/* 16393 */ "MTHC1_D32_MM\0"	9402	/* 16393 */ "MTHC1_D32_MM\0"
9403	/* 16406 */ "FSUB_D32_MM\0"	9403	/* 16406 */ "FSUB_D32_MM\0"
9404	/* 16418 */ "NMSUB_D32_MM\0"	9404	/* 16418 */ "NMSUB_D32_MM\0"
9405	/* 16431 */ "FADD_D32_MM\0"	9405	/* 16431 */ "FADD_D32_MM\0"
9406	/* 16443 */ "NMADD_D32_MM\0"	9406	/* 16443 */ "NMADD_D32_MM\0"
9407	/* 16456 */ "C_NGE_D32_MM\0"	9407	/* 16456 */ "C_NGE_D32_MM\0"
9408	/* 16469 */ "C_NGLE_D32_MM\0"	9408	/* 16469 */ "C_NGLE_D32_MM\0"
9409	/* 16483 */ "C_OLE_D32_MM\0"	9409	/* 16483 */ "C_OLE_D32_MM\0"
9410	/* 16496 */ "C_ULE_D32_MM\0"	9410	/* 16496 */ "C_ULE_D32_MM\0"
9411	/* 16509 */ "C_LE_D32_MM\0"	9411	/* 16509 */ "C_LE_D32_MM\0"
9412	/* 16521 */ "C_SF_D32_MM\0"	9412	/* 16521 */ "C_SF_D32_MM\0"
9413	/* 16533 */ "MOVF_D32_MM\0"	9413	/* 16533 */ "MOVF_D32_MM\0"
9414	/* 16545 */ "C_F_D32_MM\0"	9414	/* 16545 */ "C_F_D32_MM\0"
9415	/* 16556 */ "FNEG_D32_MM\0"	9415	/* 16556 */ "FNEG_D32_MM\0"
9416	/* 16568 */ "MOVN_I_D32_MM\0"	9416	/* 16568 */ "MOVN_I_D32_MM\0"
9417	/* 16582 */ "MOVZ_I_D32_MM\0"	9417	/* 16582 */ "MOVZ_I_D32_MM\0"
9418	/* 16596 */ "C_NGL_D32_MM\0"	9418	/* 16596 */ "C_NGL_D32_MM\0"
9419	/* 16609 */ "FMUL_D32_MM\0"	9419	/* 16609 */ "FMUL_D32_MM\0"
9420	/* 16621 */ "C_UN_D32_MM\0"	9420	/* 16621 */ "C_UN_D32_MM\0"
9421	/* 16633 */ "RECIP_D32_MM\0"	9421	/* 16633 */ "RECIP_D32_MM\0"
9422	/* 16646 */ "FCMP_D32_MM\0"	9422	/* 16646 */ "FCMP_D32_MM\0"
9423	/* 16658 */ "C_SEQ_D32_MM\0"	9423	/* 16658 */ "C_SEQ_D32_MM\0"
9424	/* 16671 */ "C_UEQ_D32_MM\0"	9424	/* 16671 */ "C_UEQ_D32_MM\0"
9425	/* 16684 */ "C_EQ_D32_MM\0"	9425	/* 16684 */ "C_EQ_D32_MM\0"
9426	/* 16696 */ "FABS_D32_MM\0"	9426	/* 16696 */ "FABS_D32_MM\0"
9427	/* 16708 */ "CVT_S_D32_MM\0"	9427	/* 16708 */ "CVT_S_D32_MM\0"
9428	/* 16721 */ "C_NGT_D32_MM\0"	9428	/* 16721 */ "C_NGT_D32_MM\0"
9429	/* 16734 */ "C_OLT_D32_MM\0"	9429	/* 16734 */ "C_OLT_D32_MM\0"
9430	/* 16747 */ "C_ULT_D32_MM\0"	9430	/* 16747 */ "C_ULT_D32_MM\0"
9431	/* 16760 */ "C_LT_D32_MM\0"	9431	/* 16760 */ "C_LT_D32_MM\0"
9432	/* 16772 */ "FSQRT_D32_MM\0"	9432	/* 16772 */ "FSQRT_D32_MM\0"
9433	/* 16785 */ "RSQRT_D32_MM\0"	9433	/* 16785 */ "RSQRT_D32_MM\0"
9434	/* 16798 */ "MOVT_D32_MM\0"	9434	/* 16798 */ "MOVT_D32_MM\0"
9435	/* 16810 */ "FDIV_D32_MM\0"	9435	/* 16810 */ "FDIV_D32_MM\0"
9436	/* 16822 */ "FMOV_D32_MM\0"	9436	/* 16822 */ "FMOV_D32_MM\0"
9437	/* 16834 */ "CVT_W_D32_MM\0"	9437	/* 16834 */ "CVT_W_D32_MM\0"
9438	/* 16847 */ "BPOSGE32_MM\0"	9438	/* 16847 */ "BPOSGE32_MM\0"
9439	/* 16859 */ "LWM32_MM\0"	9439	/* 16859 */ "LWM32_MM\0"
9440	/* 16868 */ "SWM32_MM\0"	9440	/* 16868 */ "SWM32_MM\0"
9441	/* 16877 */ "FCMP_S32_MM\0"	9441	/* 16877 */ "FCMP_S32_MM\0"
9442	/* 16889 */ "CFC2_MM\0"	9442	/* 16889 */ "CFC2_MM\0"
9443	/* 16897 */ "CTC2_MM\0"	9443	/* 16897 */ "CTC2_MM\0"
9444	/* 16905 */ "ADDIUR2_MM\0"	9444	/* 16905 */ "ADDIUR2_MM\0"
9445	/* 16916 */ "MFHC1_D64_MM\0"	9445	/* 16916 */ "MFHC1_D64_MM\0"
9446	/* 16929 */ "MTHC1_D64_MM\0"	9446	/* 16929 */ "MTHC1_D64_MM\0"
9447	/* 16942 */ "MTC1_D64_MM\0"	9447	/* 16942 */ "MTC1_D64_MM\0"
9448	/* 16954 */ "FSUB_D64_MM\0"	9448	/* 16954 */ "FSUB_D64_MM\0"
9449	/* 16966 */ "FADD_D64_MM\0"	9449	/* 16966 */ "FADD_D64_MM\0"
9450	/* 16978 */ "C_NGE_D64_MM\0"	9450	/* 16978 */ "C_NGE_D64_MM\0"
9451	/* 16991 */ "C_NGLE_D64_MM\0"	9451	/* 16991 */ "C_NGLE_D64_MM\0"
9452	/* 17005 */ "C_OLE_D64_MM\0"	9452	/* 17005 */ "C_OLE_D64_MM\0"
9453	/* 17018 */ "C_ULE_D64_MM\0"	9453	/* 17018 */ "C_ULE_D64_MM\0"
9454	/* 17031 */ "C_LE_D64_MM\0"	9454	/* 17031 */ "C_LE_D64_MM\0"
9455	/* 17043 */ "C_SF_D64_MM\0"	9455	/* 17043 */ "C_SF_D64_MM\0"
9456	/* 17055 */ "C_F_D64_MM\0"	9456	/* 17055 */ "C_F_D64_MM\0"
9457	/* 17066 */ "FNEG_D64_MM\0"	9457	/* 17066 */ "FNEG_D64_MM\0"
9458	/* 17078 */ "C_NGL_D64_MM\0"	9458	/* 17078 */ "C_NGL_D64_MM\0"
9459	/* 17091 */ "FMUL_D64_MM\0"	9459	/* 17091 */ "FMUL_D64_MM\0"
9460	/* 17103 */ "CVT_L_D64_MM\0"	9460	/* 17103 */ "CVT_L_D64_MM\0"
9461	/* 17116 */ "C_UN_D64_MM\0"	9461	/* 17116 */ "C_UN_D64_MM\0"
9462	/* 17128 */ "RECIP_D64_MM\0"	9462	/* 17128 */ "RECIP_D64_MM\0"
9463	/* 17141 */ "C_SEQ_D64_MM\0"	9463	/* 17141 */ "C_SEQ_D64_MM\0"
9464	/* 17154 */ "C_UEQ_D64_MM\0"	9464	/* 17154 */ "C_UEQ_D64_MM\0"
9465	/* 17167 */ "C_EQ_D64_MM\0"	9465	/* 17167 */ "C_EQ_D64_MM\0"
9466	/* 17179 */ "FABS_D64_MM\0"	9466	/* 17179 */ "FABS_D64_MM\0"
9467	/* 17191 */ "CVT_S_D64_MM\0"	9467	/* 17191 */ "CVT_S_D64_MM\0"
9468	/* 17204 */ "C_NGT_D64_MM\0"	9468	/* 17204 */ "C_NGT_D64_MM\0"
9469	/* 17217 */ "C_OLT_D64_MM\0"	9469	/* 17217 */ "C_OLT_D64_MM\0"
9470	/* 17230 */ "C_ULT_D64_MM\0"	9470	/* 17230 */ "C_ULT_D64_MM\0"
9471	/* 17243 */ "C_LT_D64_MM\0"	9471	/* 17243 */ "C_LT_D64_MM\0"
9472	/* 17255 */ "FSQRT_D64_MM\0"	9472	/* 17255 */ "FSQRT_D64_MM\0"
9473	/* 17268 */ "RSQRT_D64_MM\0"	9473	/* 17268 */ "RSQRT_D64_MM\0"
9474	/* 17281 */ "FDIV_D64_MM\0"	9474	/* 17281 */ "FDIV_D64_MM\0"
9475	/* 17293 */ "FMOV_D64_MM\0"	9475	/* 17293 */ "FMOV_D64_MM\0"
9476	/* 17305 */ "CVT_W_D64_MM\0"	9476	/* 17305 */ "CVT_W_D64_MM\0"
9477	/* 17318 */ "ADDIUS5_MM\0"	9477	/* 17318 */ "ADDIUS5_MM\0"
9478	/* 17329 */ "SB16_MM\0"	9478	/* 17329 */ "SB16_MM\0"
9479	/* 17337 */ "JRC16_MM\0"	9479	/* 17337 */ "JRC16_MM\0"
9480	/* 17346 */ "AND16_MM\0"	9480	/* 17346 */ "AND16_MM\0"
9481	/* 17355 */ "MOVE16_MM\0"	9481	/* 17355 */ "MOVE16_MM\0"
9482	/* 17365 */ "SH16_MM\0"	9482	/* 17365 */ "SH16_MM\0"
9483	/* 17373 */ "ANDI16_MM\0"	9483	/* 17373 */ "ANDI16_MM\0"
9484	/* 17383 */ "MFHI16_MM\0"	9484	/* 17383 */ "MFHI16_MM\0"
9485	/* 17393 */ "LI16_MM\0"	9485	/* 17393 */ "LI16_MM\0"
9486	/* 17401 */ "BREAK16_MM\0"	9486	/* 17401 */ "BREAK16_MM\0"
9487	/* 17412 */ "SLL16_MM\0"	9487	/* 17412 */ "SLL16_MM\0"
9488	/* 17421 */ "SRL16_MM\0"	9488	/* 17421 */ "SRL16_MM\0"
9489	/* 17430 */ "LWM16_MM\0"	9489	/* 17430 */ "LWM16_MM\0"
9490	/* 17439 */ "SWM16_MM\0"	9490	/* 17439 */ "SWM16_MM\0"
9491	/* 17448 */ "MFLO16_MM\0"	9491	/* 17448 */ "MFLO16_MM\0"
9492	/* 17458 */ "SDBBP16_MM\0"	9492	/* 17458 */ "SDBBP16_MM\0"
9493	/* 17469 */ "JR16_MM\0"	9493	/* 17469 */ "JR16_MM\0"
9494	/* 17477 */ "JALR16_MM\0"	9494	/* 17477 */ "JALR16_MM\0"
9495	/* 17487 */ "XOR16_MM\0"	9495	/* 17487 */ "XOR16_MM\0"
9496	/* 17496 */ "JALRS16_MM\0"	9496	/* 17496 */ "JALRS16_MM\0"
9497	/* 17507 */ "NOT16_MM\0"	9497	/* 17507 */ "NOT16_MM\0"
9498	/* 17516 */ "LBU16_MM\0"	9498	/* 17516 */ "LBU16_MM\0"
9499	/* 17525 */ "SUBU16_MM\0"	9499	/* 17525 */ "SUBU16_MM\0"
9500	/* 17535 */ "ADDU16_MM\0"	9500	/* 17535 */ "ADDU16_MM\0"
9501	/* 17545 */ "LHU16_MM\0"	9501	/* 17545 */ "LHU16_MM\0"
9502	/* 17554 */ "LW16_MM\0"	9502	/* 17554 */ "LW16_MM\0"
9503	/* 17562 */ "SW16_MM\0"	9503	/* 17562 */ "SW16_MM\0"
9504	/* 17570 */ "BNEZ16_MM\0"	9504	/* 17570 */ "BNEZ16_MM\0"
9505	/* 17580 */ "BEQZ16_MM\0"	9505	/* 17580 */ "BEQZ16_MM\0"
9506	/* 17590 */ "PRECEU_PH_QBLA_MM\0"	9506	/* 17590 */ "PRECEU_PH_QBLA_MM\0"
9507	/* 17608 */ "PRECEQU_PH_QBLA_MM\0"	9507	/* 17608 */ "PRECEQU_PH_QBLA_MM\0"
9508	/* 17627 */ "PRECEU_PH_QBRA_MM\0"	9508	/* 17627 */ "PRECEU_PH_QBRA_MM\0"
9509	/* 17645 */ "PRECEQU_PH_QBRA_MM\0"	9509	/* 17645 */ "PRECEQU_PH_QBRA_MM\0"
9510	/* 17664 */ "SRA_MM\0"	9510	/* 17664 */ "SRA_MM\0"
9511	/* 17671 */ "SEB_MM\0"	9511	/* 17671 */ "SEB_MM\0"
9512	/* 17678 */ "EHB_MM\0"	9512	/* 17678 */ "EHB_MM\0"
9513	/* 17685 */ "LB_MM\0"	9513	/* 17685 */ "LB_MM\0"
9514	/* 17691 */ "CMPGU_LE_QB_MM\0"	9514	/* 17691 */ "CMPGU_LE_QB_MM\0"
9515	/* 17706 */ "CMPU_LE_QB_MM\0"	9515	/* 17706 */ "CMPU_LE_QB_MM\0"
9516	/* 17720 */ "PICK_QB_MM\0"	9516	/* 17720 */ "PICK_QB_MM\0"
9517	/* 17731 */ "SHLL_QB_MM\0"	9517	/* 17731 */ "SHLL_QB_MM\0"
9518	/* 17742 */ "REPL_QB_MM\0"	9518	/* 17742 */ "REPL_QB_MM\0"
9519	/* 17753 */ "SHRL_QB_MM\0"	9519	/* 17753 */ "SHRL_QB_MM\0"
9520	/* 17764 */ "CMPGU_EQ_QB_MM\0"	9520	/* 17764 */ "CMPGU_EQ_QB_MM\0"
9521	/* 17779 */ "CMPU_EQ_QB_MM\0"	9521	/* 17779 */ "CMPU_EQ_QB_MM\0"
9522	/* 17793 */ "SUBU_S_QB_MM\0"	9522	/* 17793 */ "SUBU_S_QB_MM\0"
9523	/* 17806 */ "ADDU_S_QB_MM\0"	9523	/* 17806 */ "ADDU_S_QB_MM\0"
9524	/* 17819 */ "CMPGU_LT_QB_MM\0"	9524	/* 17819 */ "CMPGU_LT_QB_MM\0"
9525	/* 17834 */ "CMPU_LT_QB_MM\0"	9525	/* 17834 */ "CMPU_LT_QB_MM\0"
9526	/* 17848 */ "SUBU_QB_MM\0"	9526	/* 17848 */ "SUBU_QB_MM\0"
9527	/* 17859 */ "ADDU_QB_MM\0"	9527	/* 17859 */ "ADDU_QB_MM\0"
9528	/* 17870 */ "SHLLV_QB_MM\0"	9528	/* 17870 */ "SHLLV_QB_MM\0"
9529	/* 17882 */ "REPLV_QB_MM\0"	9529	/* 17882 */ "REPLV_QB_MM\0"
9530	/* 17894 */ "SHRLV_QB_MM\0"	9530	/* 17894 */ "SHRLV_QB_MM\0"
9531	/* 17906 */ "RADDU_W_QB_MM\0"	9531	/* 17906 */ "RADDU_W_QB_MM\0"
9532	/* 17920 */ "SB_MM\0"	9532	/* 17920 */ "SB_MM\0"
9533	/* 17926 */ "MODSUB_MM\0"	9533	/* 17926 */ "MODSUB_MM\0"
9534	/* 17936 */ "PseudoMSUB_MM\0"	9534	/* 17936 */ "PseudoMSUB_MM\0"
9535	/* 17950 */ "SYNC_MM\0"	9535	/* 17950 */ "SYNC_MM\0"
9536	/* 17958 */ "ADDIUPC_MM\0"	9536	/* 17958 */ "ADDIUPC_MM\0"
9537	/* 17969 */ "ADDSC_MM\0"	9537	/* 17969 */ "ADDSC_MM\0"
9538	/* 17978 */ "ADDWC_MM\0"	9538	/* 17978 */ "ADDWC_MM\0"
9539	/* 17987 */ "BNEZC_MM\0"	9539	/* 17987 */ "BNEZC_MM\0"
9540	/* 17996 */ "BEQZC_MM\0"	9540	/* 17996 */ "BEQZC_MM\0"
9541	/* 18005 */ "PseudoMADD_MM\0"	9541	/* 18005 */ "PseudoMADD_MM\0"
9542	/* 18019 */ "AND_MM\0"	9542	/* 18019 */ "AND_MM\0"
9543	/* 18026 */ "LBE_MM\0"	9543	/* 18026 */ "LBE_MM\0"
9544	/* 18033 */ "SBE_MM\0"	9544	/* 18033 */ "SBE_MM\0"
9545	/* 18040 */ "SCE_MM\0"	9545	/* 18040 */ "SCE_MM\0"
9546	/* 18047 */ "CACHEE_MM\0"	9546	/* 18047 */ "CACHEE_MM\0"
9547	/* 18057 */ "PREFE_MM\0"	9547	/* 18057 */ "PREFE_MM\0"
9548	/* 18066 */ "TGE_MM\0"	9548	/* 18066 */ "TGE_MM\0"
9549	/* 18073 */ "CACHE_MM\0"	9549	/* 18073 */ "CACHE_MM\0"
9550	/* 18082 */ "LHE_MM\0"	9550	/* 18082 */ "LHE_MM\0"
9551	/* 18089 */ "SHE_MM\0"	9551	/* 18089 */ "SHE_MM\0"
9552	/* 18096 */ "LLE_MM\0"	9552	/* 18096 */ "LLE_MM\0"
9553	/* 18103 */ "LWLE_MM\0"	9553	/* 18103 */ "LWLE_MM\0"
9554	/* 18111 */ "SWLE_MM\0"	9554	/* 18111 */ "SWLE_MM\0"
9555	/* 18119 */ "BNE_MM\0"	9555	/* 18119 */ "BNE_MM\0"
9556	/* 18126 */ "TNE_MM\0"	9556	/* 18126 */ "TNE_MM\0"
9557	/* 18133 */ "LWRE_MM\0"	9557	/* 18133 */ "LWRE_MM\0"
9558	/* 18141 */ "SWRE_MM\0"	9558	/* 18141 */ "SWRE_MM\0"
9559	/* 18149 */ "PAUSE_MM\0"	9559	/* 18149 */ "PAUSE_MM\0"
9560	/* 18158 */ "LWE_MM\0"	9560	/* 18158 */ "LWE_MM\0"
9561	/* 18165 */ "SWE_MM\0"	9561	/* 18165 */ "SWE_MM\0"
9562	/* 18172 */ "LBuE_MM\0"	9562	/* 18172 */ "LBuE_MM\0"
9563	/* 18180 */ "LHuE_MM\0"	9563	/* 18180 */ "LHuE_MM\0"
9564	/* 18188 */ "BC1F_MM\0"	9564	/* 18188 */ "BC1F_MM\0"
9565	/* 18196 */ "PREF_MM\0"	9565	/* 18196 */ "PREF_MM\0"
9566	/* 18204 */ "TLBGINVF_MM\0"	9566	/* 18204 */ "TLBGINVF_MM\0"
9567	/* 18216 */ "TAILCALLREG_MM\0"	9567	/* 18216 */ "TAILCALLREG_MM\0"
9568	/* 18231 */ "WSBH_MM\0"	9568	/* 18231 */ "WSBH_MM\0"
9569	/* 18239 */ "SEH_MM\0"	9569	/* 18239 */ "SEH_MM\0"
9570	/* 18246 */ "LH_MM\0"	9570	/* 18246 */ "LH_MM\0"
9571	/* 18252 */ "SHRA_PH_MM\0"	9571	/* 18252 */ "SHRA_PH_MM\0"
9572	/* 18263 */ "PRECRQ_QB_PH_MM\0"	9572	/* 18263 */ "PRECRQ_QB_PH_MM\0"
9573	/* 18279 */ "PRECRQU_S_QB_PH_MM\0"	9573	/* 18279 */ "PRECRQU_S_QB_PH_MM\0"
9574	/* 18298 */ "CMP_LE_PH_MM\0"	9574	/* 18298 */ "CMP_LE_PH_MM\0"
9575	/* 18311 */ "PICK_PH_MM\0"	9575	/* 18311 */ "PICK_PH_MM\0"
9576	/* 18322 */ "SHLL_PH_MM\0"	9576	/* 18322 */ "SHLL_PH_MM\0"
9577	/* 18333 */ "REPL_PH_MM\0"	9577	/* 18333 */ "REPL_PH_MM\0"
9578	/* 18344 */ "PACKRL_PH_MM\0"	9578	/* 18344 */ "PACKRL_PH_MM\0"
9579	/* 18357 */ "SUBQ_PH_MM\0"	9579	/* 18357 */ "SUBQ_PH_MM\0"
9580	/* 18368 */ "ADDQ_PH_MM\0"	9580	/* 18368 */ "ADDQ_PH_MM\0"
9581	/* 18379 */ "CMP_EQ_PH_MM\0"	9581	/* 18379 */ "CMP_EQ_PH_MM\0"
9582	/* 18392 */ "SHRA_R_PH_MM\0"	9582	/* 18392 */ "SHRA_R_PH_MM\0"
9583	/* 18405 */ "SHRAV_R_PH_MM\0"	9583	/* 18405 */ "SHRAV_R_PH_MM\0"
9584	/* 18419 */ "MULQ_RS_PH_MM\0"	9584	/* 18419 */ "MULQ_RS_PH_MM\0"
9585	/* 18433 */ "SHLL_S_PH_MM\0"	9585	/* 18433 */ "SHLL_S_PH_MM\0"
9586	/* 18446 */ "SUBQ_S_PH_MM\0"	9586	/* 18446 */ "SUBQ_S_PH_MM\0"
9587	/* 18459 */ "ADDQ_S_PH_MM\0"	9587	/* 18459 */ "ADDQ_S_PH_MM\0"
9588	/* 18472 */ "ABSQ_S_PH_MM\0"	9588	/* 18472 */ "ABSQ_S_PH_MM\0"
9589	/* 18485 */ "SHLLV_S_PH_MM\0"	9589	/* 18485 */ "SHLLV_S_PH_MM\0"
9590	/* 18499 */ "CMP_LT_PH_MM\0"	9590	/* 18499 */ "CMP_LT_PH_MM\0"
9591	/* 18512 */ "SHRAV_PH_MM\0"	9591	/* 18512 */ "SHRAV_PH_MM\0"
9592	/* 18524 */ "SHLLV_PH_MM\0"	9592	/* 18524 */ "SHLLV_PH_MM\0"
9593	/* 18536 */ "REPLV_PH_MM\0"	9593	/* 18536 */ "REPLV_PH_MM\0"
9594	/* 18548 */ "DPAQ_S_W_PH_MM\0"	9594	/* 18548 */ "DPAQ_S_W_PH_MM\0"
9595	/* 18563 */ "MULSAQ_S_W_PH_MM\0"	9595	/* 18563 */ "MULSAQ_S_W_PH_MM\0"
9596	/* 18580 */ "DPSQ_S_W_PH_MM\0"	9596	/* 18580 */ "DPSQ_S_W_PH_MM\0"
9597	/* 18595 */ "SH_MM\0"	9597	/* 18595 */ "SH_MM\0"
9598	/* 18601 */ "EXTR_S_H_MM\0"	9598	/* 18601 */ "EXTR_S_H_MM\0"
9599	/* 18613 */ "EXTRV_S_H_MM\0"	9599	/* 18613 */ "EXTRV_S_H_MM\0"
9600	/* 18626 */ "SYNCI_MM\0"	9600	/* 18626 */ "SYNCI_MM\0"
9601	/* 18635 */ "DI_MM\0"	9601	/* 18635 */ "DI_MM\0"
9602	/* 18641 */ "TGEI_MM\0"	9602	/* 18641 */ "TGEI_MM\0"
9603	/* 18649 */ "TNEI_MM\0"	9603	/* 18649 */ "TNEI_MM\0"
9604	/* 18657 */ "PseudoMFHI_MM\0"	9604	/* 18657 */ "PseudoMFHI_MM\0"
9605	/* 18671 */ "PseudoMTLOHI_MM\0"	9605	/* 18671 */ "PseudoMTLOHI_MM\0"
9606	/* 18687 */ "MTHI_MM\0"	9606	/* 18687 */ "MTHI_MM\0"
9607	/* 18695 */ "TEQI_MM\0"	9607	/* 18695 */ "TEQI_MM\0"
9608	/* 18703 */ "TLTI_MM\0"	9608	/* 18703 */ "TLTI_MM\0"
9609	/* 18711 */ "TLBWI_MM\0"	9609	/* 18711 */ "TLBWI_MM\0"
9610	/* 18720 */ "TLBGWI_MM\0"	9610	/* 18720 */ "TLBGWI_MM\0"
9611	/* 18730 */ "MOVF_I_MM\0"	9611	/* 18730 */ "MOVF_I_MM\0"
9612	/* 18740 */ "MOVN_I_MM\0"	9612	/* 18740 */ "MOVN_I_MM\0"
9613	/* 18750 */ "MOVT_I_MM\0"	9613	/* 18750 */ "MOVT_I_MM\0"
9614	/* 18760 */ "MOVZ_I_MM\0"	9614	/* 18760 */ "MOVZ_I_MM\0"
9615	/* 18770 */ "J_MM\0"	9615	/* 18770 */ "J_MM\0"
9616	/* 18775 */ "BREAK_MM\0"	9616	/* 18775 */ "BREAK_MM\0"
9617	/* 18784 */ "JAL_MM\0"	9617	/* 18784 */ "JAL_MM\0"
9618	/* 18791 */ "BGEZAL_MM\0"	9618	/* 18791 */ "BGEZAL_MM\0"
9619	/* 18801 */ "BLTZAL_MM\0"	9619	/* 18801 */ "BLTZAL_MM\0"
9620	/* 18811 */ "MULEU_S_PH_QBL_MM\0"	9620	/* 18811 */ "MULEU_S_PH_QBL_MM\0"
9621	/* 18829 */ "PRECEU_PH_QBL_MM\0"	9621	/* 18829 */ "PRECEU_PH_QBL_MM\0"
9622	/* 18846 */ "PRECEQU_PH_QBL_MM\0"	9622	/* 18846 */ "PRECEQU_PH_QBL_MM\0"
9623	/* 18864 */ "DPAU_H_QBL_MM\0"	9623	/* 18864 */ "DPAU_H_QBL_MM\0"
9624	/* 18878 */ "DPSU_H_QBL_MM\0"	9624	/* 18878 */ "DPSU_H_QBL_MM\0"
9625	/* 18892 */ "MAQ_SA_W_PHL_MM\0"	9625	/* 18892 */ "MAQ_SA_W_PHL_MM\0"
9626	/* 18908 */ "PRECEQ_W_PHL_MM\0"	9626	/* 18908 */ "PRECEQ_W_PHL_MM\0"
9627	/* 18924 */ "MAQ_S_W_PHL_MM\0"	9627	/* 18924 */ "MAQ_S_W_PHL_MM\0"
9628	/* 18939 */ "MULEQ_S_W_PHL_MM\0"	9628	/* 18939 */ "MULEQ_S_W_PHL_MM\0"
9629	/* 18956 */ "TAILCALL_MM\0"	9629	/* 18956 */ "TAILCALL_MM\0"
9630	/* 18968 */ "HYPCALL_MM\0"	9630	/* 18968 */ "HYPCALL_MM\0"
9631	/* 18979 */ "SYSCALL_MM\0"	9631	/* 18979 */ "SYSCALL_MM\0"
9632	/* 18990 */ "SLL_MM\0"	9632	/* 18990 */ "SLL_MM\0"
9633	/* 18997 */ "SRL_MM\0"	9633	/* 18997 */ "SRL_MM\0"
9634	/* 19004 */ "MUL_MM\0"	9634	/* 19004 */ "MUL_MM\0"
9635	/* 19011 */ "LWL_MM\0"	9635	/* 19011 */ "LWL_MM\0"
9636	/* 19018 */ "SWL_MM\0"	9636	/* 19018 */ "SWL_MM\0"
9637	/* 19025 */ "LWM_MM\0"	9637	/* 19025 */ "LWM_MM\0"
9638	/* 19032 */ "SWM_MM\0"	9638	/* 19032 */ "SWM_MM\0"
9639	/* 19039 */ "CLO_MM\0"	9639	/* 19039 */ "CLO_MM\0"
9640	/* 19046 */ "PseudoMFLO_MM\0"	9640	/* 19046 */ "PseudoMFLO_MM\0"
9641	/* 19060 */ "SHILO_MM\0"	9641	/* 19060 */ "SHILO_MM\0"
9642	/* 19069 */ "MTLO_MM\0"	9642	/* 19069 */ "MTLO_MM\0"
9643	/* 19077 */ "TRAP_MM\0"	9643	/* 19077 */ "TRAP_MM\0"
9644	/* 19085 */ "SDBBP_MM\0"	9644	/* 19085 */ "SDBBP_MM\0"
9645	/* 19094 */ "TLBP_MM\0"	9645	/* 19094 */ "TLBP_MM\0"
9646	/* 19102 */ "EXTPDP_MM\0"	9646	/* 19102 */ "EXTPDP_MM\0"
9647	/* 19112 */ "MOVEP_MM\0"	9647	/* 19112 */ "MOVEP_MM\0"
9648	/* 19121 */ "TLBGP_MM\0"	9648	/* 19121 */ "TLBGP_MM\0"
9649	/* 19130 */ "LWGP_MM\0"	9649	/* 19130 */ "LWGP_MM\0"
9650	/* 19138 */ "MTHLIP_MM\0"	9650	/* 19138 */ "MTHLIP_MM\0"
9651	/* 19148 */ "SSNOP_MM\0"	9651	/* 19148 */ "SSNOP_MM\0"
9652	/* 19157 */ "ADDIUR1SP_MM\0"	9652	/* 19157 */ "ADDIUR1SP_MM\0"
9653	/* 19170 */ "RDDSP_MM\0"	9653	/* 19170 */ "RDDSP_MM\0"
9654	/* 19179 */ "WRDSP_MM\0"	9654	/* 19179 */ "WRDSP_MM\0"
9655	/* 19188 */ "LWDSP_MM\0"	9655	/* 19188 */ "LWDSP_MM\0"
9656	/* 19197 */ "SWDSP_MM\0"	9656	/* 19197 */ "SWDSP_MM\0"
9657	/* 19206 */ "MSUB_DSP_MM\0"	9657	/* 19206 */ "MSUB_DSP_MM\0"
9658	/* 19218 */ "MADD_DSP_MM\0"	9658	/* 19218 */ "MADD_DSP_MM\0"
9659	/* 19230 */ "MFHI_DSP_MM\0"	9659	/* 19230 */ "MFHI_DSP_MM\0"
9660	/* 19242 */ "MTHI_DSP_MM\0"	9660	/* 19242 */ "MTHI_DSP_MM\0"
9661	/* 19254 */ "MFLO_DSP_MM\0"	9661	/* 19254 */ "MFLO_DSP_MM\0"
9662	/* 19266 */ "MTLO_DSP_MM\0"	9662	/* 19266 */ "MTLO_DSP_MM\0"
9663	/* 19278 */ "MULT_DSP_MM\0"	9663	/* 19278 */ "MULT_DSP_MM\0"
9664	/* 19290 */ "MSUBU_DSP_MM\0"	9664	/* 19290 */ "MSUBU_DSP_MM\0"
9665	/* 19303 */ "MADDU_DSP_MM\0"	9665	/* 19303 */ "MADDU_DSP_MM\0"
9666	/* 19316 */ "MULTU_DSP_MM\0"	9666	/* 19316 */ "MULTU_DSP_MM\0"
9667	/* 19329 */ "ADDIUSP_MM\0"	9667	/* 19329 */ "ADDIUSP_MM\0"
9668	/* 19340 */ "LWSP_MM\0"	9668	/* 19340 */ "LWSP_MM\0"
9669	/* 19348 */ "SWSP_MM\0"	9669	/* 19348 */ "SWSP_MM\0"
9670	/* 19356 */ "EXTP_MM\0"	9670	/* 19356 */ "EXTP_MM\0"
9671	/* 19364 */ "LWP_MM\0"	9671	/* 19364 */ "LWP_MM\0"
9672	/* 19371 */ "SWP_MM\0"	9672	/* 19371 */ "SWP_MM\0"
9673	/* 19378 */ "BEQ_MM\0"	9673	/* 19378 */ "BEQ_MM\0"
9674	/* 19385 */ "TEQ_MM\0"	9674	/* 19385 */ "TEQ_MM\0"
9675	/* 19392 */ "TLBR_MM\0"	9675	/* 19392 */ "TLBR_MM\0"
9676	/* 19400 */ "MULEU_S_PH_QBR_MM\0"	9676	/* 19400 */ "MULEU_S_PH_QBR_MM\0"
9677	/* 19418 */ "PRECEU_PH_QBR_MM\0"	9677	/* 19418 */ "PRECEU_PH_QBR_MM\0"
9678	/* 19435 */ "PRECEQU_PH_QBR_MM\0"	9678	/* 19435 */ "PRECEQU_PH_QBR_MM\0"
9679	/* 19453 */ "DPAU_H_QBR_MM\0"	9679	/* 19453 */ "DPAU_H_QBR_MM\0"
9680	/* 19467 */ "DPSU_H_QBR_MM\0"	9680	/* 19467 */ "DPSU_H_QBR_MM\0"
9681	/* 19481 */ "BAL_BR_MM\0"	9681	/* 19481 */ "BAL_BR_MM\0"
9682	/* 19491 */ "TLBGR_MM\0"	9682	/* 19491 */ "TLBGR_MM\0"
9683	/* 19500 */ "MAQ_SA_W_PHR_MM\0"	9683	/* 19500 */ "MAQ_SA_W_PHR_MM\0"
9684	/* 19516 */ "PRECEQ_W_PHR_MM\0"	9684	/* 19516 */ "PRECEQ_W_PHR_MM\0"
9685	/* 19532 */ "MAQ_S_W_PHR_MM\0"	9685	/* 19532 */ "MAQ_S_W_PHR_MM\0"
9686	/* 19547 */ "MULEQ_S_W_PHR_MM\0"	9686	/* 19547 */ "MULEQ_S_W_PHR_MM\0"
9687	/* 19564 */ "JR_MM\0"	9687	/* 19564 */ "JR_MM\0"
9688	/* 19570 */ "JALR_MM\0"	9688	/* 19570 */ "JALR_MM\0"
9689	/* 19578 */ "NOR_MM\0"	9689	/* 19578 */ "NOR_MM\0"
9690	/* 19585 */ "XOR_MM\0"	9690	/* 19585 */ "XOR_MM\0"
9691	/* 19592 */ "ROTR_MM\0"	9691	/* 19592 */ "ROTR_MM\0"
9692	/* 19600 */ "TLBWR_MM\0"	9692	/* 19600 */ "TLBWR_MM\0"
9693	/* 19609 */ "TLBGWR_MM\0"	9693	/* 19609 */ "TLBGWR_MM\0"
9694	/* 19619 */ "RDHWR_MM\0"	9694	/* 19619 */ "RDHWR_MM\0"
9695	/* 19628 */ "LWR_MM\0"	9695	/* 19628 */ "LWR_MM\0"
9696	/* 19635 */ "SWR_MM\0"	9696	/* 19635 */ "SWR_MM\0"
9697	/* 19642 */ "JALS_MM\0"	9697	/* 19642 */ "JALS_MM\0"
9698	/* 19650 */ "BGEZALS_MM\0"	9698	/* 19650 */ "BGEZALS_MM\0"
9699	/* 19661 */ "BLTZALS_MM\0"	9699	/* 19661 */ "BLTZALS_MM\0"
9700	/* 19672 */ "INS_MM\0"	9700	/* 19672 */ "INS_MM\0"
9701	/* 19679 */ "JALRS_MM\0"	9701	/* 19679 */ "JALRS_MM\0"
9702	/* 19688 */ "LWXS_MM\0"	9702	/* 19688 */ "LWXS_MM\0"
9703	/* 19696 */ "CVT_D32_S_MM\0"	9703	/* 19696 */ "CVT_D32_S_MM\0"
9704	/* 19709 */ "CVT_D64_S_MM\0"	9704	/* 19709 */ "CVT_D64_S_MM\0"
9705	/* 19722 */ "FSUB_S_MM\0"	9705	/* 19722 */ "FSUB_S_MM\0"
9706	/* 19732 */ "NMSUB_S_MM\0"	9706	/* 19732 */ "NMSUB_S_MM\0"
9707	/* 19743 */ "FADD_S_MM\0"	9707	/* 19743 */ "FADD_S_MM\0"
9708	/* 19753 */ "NMADD_S_MM\0"	9708	/* 19753 */ "NMADD_S_MM\0"
9709	/* 19764 */ "C_NGE_S_MM\0"	9709	/* 19764 */ "C_NGE_S_MM\0"
9710	/* 19775 */ "C_NGLE_S_MM\0"	9710	/* 19775 */ "C_NGLE_S_MM\0"
9711	/* 19787 */ "C_OLE_S_MM\0"	9711	/* 19787 */ "C_OLE_S_MM\0"
9712	/* 19798 */ "C_ULE_S_MM\0"	9712	/* 19798 */ "C_ULE_S_MM\0"
9713	/* 19809 */ "C_LE_S_MM\0"	9713	/* 19809 */ "C_LE_S_MM\0"
9714	/* 19819 */ "C_SF_S_MM\0"	9714	/* 19819 */ "C_SF_S_MM\0"
9715	/* 19829 */ "MOVF_S_MM\0"	9715	/* 19829 */ "MOVF_S_MM\0"
9716	/* 19839 */ "C_F_S_MM\0"	9716	/* 19839 */ "C_F_S_MM\0"
9717	/* 19848 */ "FNEG_S_MM\0"	9717	/* 19848 */ "FNEG_S_MM\0"
9718	/* 19858 */ "MOVN_I_S_MM\0"	9718	/* 19858 */ "MOVN_I_S_MM\0"
9719	/* 19870 */ "MOVZ_I_S_MM\0"	9719	/* 19870 */ "MOVZ_I_S_MM\0"
9720	/* 19882 */ "C_NGL_S_MM\0"	9720	/* 19882 */ "C_NGL_S_MM\0"
9721	/* 19893 */ "FMUL_S_MM\0"	9721	/* 19893 */ "FMUL_S_MM\0"
9722	/* 19903 */ "CVT_L_S_MM\0"	9722	/* 19903 */ "CVT_L_S_MM\0"
9723	/* 19914 */ "C_UN_S_MM\0"	9723	/* 19914 */ "C_UN_S_MM\0"
9724	/* 19924 */ "RECIP_S_MM\0"	9724	/* 19924 */ "RECIP_S_MM\0"
9725	/* 19935 */ "C_SEQ_S_MM\0"	9725	/* 19935 */ "C_SEQ_S_MM\0"
9726	/* 19946 */ "C_UEQ_S_MM\0"	9726	/* 19946 */ "C_UEQ_S_MM\0"
9727	/* 19957 */ "C_EQ_S_MM\0"	9727	/* 19957 */ "C_EQ_S_MM\0"
9728	/* 19967 */ "FABS_S_MM\0"	9728	/* 19967 */ "FABS_S_MM\0"
9729	/* 19977 */ "C_NGT_S_MM\0"	9729	/* 19977 */ "C_NGT_S_MM\0"
9730	/* 19988 */ "C_OLT_S_MM\0"	9730	/* 19988 */ "C_OLT_S_MM\0"
9731	/* 19999 */ "C_ULT_S_MM\0"	9731	/* 19999 */ "C_ULT_S_MM\0"
9732	/* 20010 */ "C_LT_S_MM\0"	9732	/* 20010 */ "C_LT_S_MM\0"
9733	/* 20020 */ "FSQRT_S_MM\0"	9733	/* 20020 */ "FSQRT_S_MM\0"
9734	/* 20031 */ "RSQRT_S_MM\0"	9734	/* 20031 */ "RSQRT_S_MM\0"
9735	/* 20042 */ "MOVT_S_MM\0"	9735	/* 20042 */ "MOVT_S_MM\0"
9736	/* 20052 */ "FDIV_S_MM\0"	9736	/* 20052 */ "FDIV_S_MM\0"
9737	/* 20062 */ "FMOV_S_MM\0"	9737	/* 20062 */ "FMOV_S_MM\0"
9738	/* 20072 */ "TRUNC_W_S_MM\0"	9738	/* 20072 */ "TRUNC_W_S_MM\0"
9739	/* 20085 */ "ROUND_W_S_MM\0"	9739	/* 20085 */ "ROUND_W_S_MM\0"
9740	/* 20098 */ "CEIL_W_S_MM\0"	9740	/* 20098 */ "CEIL_W_S_MM\0"
9741	/* 20110 */ "FLOOR_W_S_MM\0"	9741	/* 20110 */ "FLOOR_W_S_MM\0"
9742	/* 20123 */ "CVT_W_S_MM\0"	9742	/* 20123 */ "CVT_W_S_MM\0"
9743	/* 20134 */ "BC1T_MM\0"	9743	/* 20134 */ "BC1T_MM\0"
9744	/* 20142 */ "DERET_MM\0"	9744	/* 20142 */ "DERET_MM\0"
9745	/* 20151 */ "WAIT_MM\0"	9745	/* 20151 */ "WAIT_MM\0"
9746	/* 20159 */ "SLT_MM\0"	9746	/* 20159 */ "SLT_MM\0"
9747	/* 20166 */ "TLT_MM\0"	9747	/* 20166 */ "TLT_MM\0"
9748	/* 20173 */ "PseudoMULT_MM\0"	9748	/* 20173 */ "PseudoMULT_MM\0"
9749	/* 20187 */ "EXT_MM\0"	9749	/* 20187 */ "EXT_MM\0"
9750	/* 20194 */ "PseudoMSUBU_MM\0"	9750	/* 20194 */ "PseudoMSUBU_MM\0"
9751	/* 20209 */ "PseudoMADDU_MM\0"	9751	/* 20209 */ "PseudoMADDU_MM\0"
9752	/* 20224 */ "TGEU_MM\0"	9752	/* 20224 */ "TGEU_MM\0"
9753	/* 20232 */ "TGEIU_MM\0"	9753	/* 20232 */ "TGEIU_MM\0"
9754	/* 20241 */ "TLTIU_MM\0"	9754	/* 20241 */ "TLTIU_MM\0"
9755	/* 20250 */ "TLTU_MM\0"	9755	/* 20250 */ "TLTU_MM\0"
9756	/* 20258 */ "LWU_MM\0"	9756	/* 20258 */ "LWU_MM\0"
9757	/* 20265 */ "SRAV_MM\0"	9757	/* 20265 */ "SRAV_MM\0"
9758	/* 20273 */ "BITREV_MM\0"	9758	/* 20273 */ "BITREV_MM\0"
9759	/* 20283 */ "SDIV_MM\0"	9759	/* 20283 */ "SDIV_MM\0"
9760	/* 20291 */ "UDIV_MM\0"	9760	/* 20291 */ "UDIV_MM\0"
9761	/* 20299 */ "SLLV_MM\0"	9761	/* 20299 */ "SLLV_MM\0"
9762	/* 20307 */ "SRLV_MM\0"	9762	/* 20307 */ "SRLV_MM\0"
9763	/* 20315 */ "TLBGINV_MM\0"	9763	/* 20315 */ "TLBGINV_MM\0"
9764	/* 20326 */ "SHILOV_MM\0"	9764	/* 20326 */ "SHILOV_MM\0"
9765	/* 20336 */ "EXTPDPV_MM\0"	9765	/* 20336 */ "EXTPDPV_MM\0"
9766	/* 20347 */ "EXTPV_MM\0"	9766	/* 20347 */ "EXTPV_MM\0"
9767	/* 20356 */ "ROTRV_MM\0"	9767	/* 20356 */ "ROTRV_MM\0"
9768	/* 20365 */ "INSV_MM\0"	9768	/* 20365 */ "INSV_MM\0"
9769	/* 20373 */ "LW_MM\0"	9769	/* 20373 */ "LW_MM\0"
9770	/* 20379 */ "SW_MM\0"	9770	/* 20379 */ "SW_MM\0"
9771	/* 20385 */ "CVT_D32_W_MM\0"	9771	/* 20385 */ "CVT_D32_W_MM\0"
9772	/* 20398 */ "CVT_D64_W_MM\0"	9772	/* 20398 */ "CVT_D64_W_MM\0"
9773	/* 20411 */ "TRUNC_W_MM\0"	9773	/* 20411 */ "TRUNC_W_MM\0"
9774	/* 20422 */ "ROUND_W_MM\0"	9774	/* 20422 */ "ROUND_W_MM\0"
9775	/* 20433 */ "PRECRQ_PH_W_MM\0"	9775	/* 20433 */ "PRECRQ_PH_W_MM\0"
9776	/* 20448 */ "PRECRQ_RS_PH_W_MM\0"	9776	/* 20448 */ "PRECRQ_RS_PH_W_MM\0"
9777	/* 20466 */ "CEIL_W_MM\0"	9777	/* 20466 */ "CEIL_W_MM\0"
9778	/* 20476 */ "DPAQ_SA_L_W_MM\0"	9778	/* 20476 */ "DPAQ_SA_L_W_MM\0"
9779	/* 20491 */ "DPSQ_SA_L_W_MM\0"	9779	/* 20491 */ "DPSQ_SA_L_W_MM\0"
9780	/* 20506 */ "FLOOR_W_MM\0"	9780	/* 20506 */ "FLOOR_W_MM\0"
9781	/* 20517 */ "EXTR_W_MM\0"	9781	/* 20517 */ "EXTR_W_MM\0"
9782	/* 20527 */ "SHRA_R_W_MM\0"	9782	/* 20527 */ "SHRA_R_W_MM\0"
9783	/* 20539 */ "EXTR_R_W_MM\0"	9783	/* 20539 */ "EXTR_R_W_MM\0"
9784	/* 20551 */ "SHRAV_R_W_MM\0"	9784	/* 20551 */ "SHRAV_R_W_MM\0"
9785	/* 20564 */ "EXTRV_R_W_MM\0"	9785	/* 20564 */ "EXTRV_R_W_MM\0"
9786	/* 20577 */ "EXTR_RS_W_MM\0"	9786	/* 20577 */ "EXTR_RS_W_MM\0"
9787	/* 20590 */ "EXTRV_RS_W_MM\0"	9787	/* 20590 */ "EXTRV_RS_W_MM\0"
9788	/* 20604 */ "SHLL_S_W_MM\0"	9788	/* 20604 */ "SHLL_S_W_MM\0"
9789	/* 20616 */ "SUBQ_S_W_MM\0"	9789	/* 20616 */ "SUBQ_S_W_MM\0"
9790	/* 20628 */ "ADDQ_S_W_MM\0"	9790	/* 20628 */ "ADDQ_S_W_MM\0"
9791	/* 20640 */ "ABSQ_S_W_MM\0"	9791	/* 20640 */ "ABSQ_S_W_MM\0"
9792	/* 20652 */ "CVT_S_W_MM\0"	9792	/* 20652 */ "CVT_S_W_MM\0"
9793	/* 20663 */ "SHLLV_S_W_MM\0"	9793	/* 20663 */ "SHLLV_S_W_MM\0"
9794	/* 20676 */ "EXTRV_W_MM\0"	9794	/* 20676 */ "EXTRV_W_MM\0"
9795	/* 20687 */ "PREFX_MM\0"	9795	/* 20687 */ "PREFX_MM\0"
9796	/* 20696 */ "LHX_MM\0"	9796	/* 20696 */ "LHX_MM\0"
9797	/* 20703 */ "JALX_MM\0"	9797	/* 20703 */ "JALX_MM\0"
9798	/* 20711 */ "LBUX_MM\0"	9798	/* 20711 */ "LBUX_MM\0"
9799	/* 20719 */ "LWX_MM\0"	9799	/* 20719 */ "LWX_MM\0"
9800	/* 20726 */ "BGEZ_MM\0"	9800	/* 20726 */ "BGEZ_MM\0"
9801	/* 20734 */ "BLEZ_MM\0"	9801	/* 20734 */ "BLEZ_MM\0"
9802	/* 20742 */ "CLZ_MM\0"	9802	/* 20742 */ "CLZ_MM\0"
9803	/* 20749 */ "BGTZ_MM\0"	9803	/* 20749 */ "BGTZ_MM\0"
9804	/* 20757 */ "BLTZ_MM\0"	9804	/* 20757 */ "BLTZ_MM\0"
9805	/* 20765 */ "PseudoIndirectBranch_MM\0"	9805	/* 20765 */ "PseudoIndirectBranch_MM\0"
9806	/* 20789 */ "ADDi_MM\0"	9806	/* 20789 */ "ADDi_MM\0"
9807	/* 20797 */ "ANDi_MM\0"	9807	/* 20797 */ "ANDi_MM\0"
9808	/* 20805 */ "XORi_MM\0"	9808	/* 20805 */ "XORi_MM\0"
9809	/* 20813 */ "SLTi_MM\0"	9809	/* 20813 */ "SLTi_MM\0"
9810	/* 20821 */ "LUi_MM\0"	9810	/* 20821 */ "LUi_MM\0"
9811	/* 20828 */ "LBu_MM\0"	9811	/* 20828 */ "LBu_MM\0"
9812	/* 20835 */ "SUBu_MM\0"	9812	/* 20835 */ "SUBu_MM\0"
9813	/* 20843 */ "ADDu_MM\0"	9813	/* 20843 */ "ADDu_MM\0"
9814	/* 20851 */ "LHu_MM\0"	9814	/* 20851 */ "LHu_MM\0"
9815	/* 20858 */ "SLTu_MM\0"	9815	/* 20858 */ "SLTu_MM\0"
9816	/* 20866 */ "PseudoMULTu_MM\0"	9816	/* 20866 */ "PseudoMULTu_MM\0"
9817	/* 20881 */ "LEA_ADDiu_MM\0"	9817	/* 20881 */ "LEA_ADDiu_MM\0"
9818	/* 20894 */ "SLTiu_MM\0"	9818	/* 20894 */ "SLTiu_MM\0"
9819	/* 20903 */ "INLINEASM\0"	9819	/* 20903 */ "INLINEASM\0"
9820	/* 20913 */ "DINSM\0"	9820	/* 20913 */ "DINSM\0"
9821	/* 20919 */ "DEXTM\0"	9821	/* 20919 */ "DEXTM\0"
9822	/* 20925 */ "G_FMINIMUM\0"	9822	/* 20925 */ "G_FMINIMUM\0"
9823	/* 20936 */ "G_FMAXIMUM\0"	9823	/* 20936 */ "G_FMAXIMUM\0"
9824	/* 20947 */ "G_FMINNUM\0"	9824	/* 20947 */ "G_FMINNUM\0"
9825	/* 20957 */ "G_FMAXNUM\0"	9825	/* 20957 */ "G_FMAXNUM\0"
9826	/* 20967 */ "G_INTRINSIC_ROUNDEVEN\0"	9826	/* 20967 */ "G_INTRINSIC_ROUNDEVEN\0"
9827	/* 20989 */ "BALIGN\0"	9827	/* 20989 */ "BALIGN\0"
9828	/* 20996 */ "DALIGN\0"	9828	/* 20996 */ "DALIGN\0"
9829	/* 21003 */ "G_ASSERT_ALIGN\0"	9829	/* 21003 */ "G_ASSERT_ALIGN\0"
9830	/* 21018 */ "G_FCOPYSIGN\0"	9830	/* 21018 */ "G_FCOPYSIGN\0"
9831	/* 21030 */ "G_VECREDUCE_FMIN\0"	9831	/* 21030 */ "G_VECREDUCE_FMIN\0"
9832	/* 21047 */ "G_ATOMICRMW_FMIN\0"	9832	/* 21047 */ "G_ATOMICRMW_FMIN\0"
9833	/* 21064 */ "G_VECREDUCE_SMIN\0"	9833	/* 21064 */ "G_VECREDUCE_SMIN\0"
9834	/* 21081 */ "G_SMIN\0"	9834	/* 21081 */ "G_SMIN\0"
9835	/* 21088 */ "G_VECREDUCE_UMIN\0"	9835	/* 21088 */ "G_VECREDUCE_UMIN\0"
9836	/* 21105 */ "G_UMIN\0"	9836	/* 21105 */ "G_UMIN\0"
9837	/* 21112 */ "G_ATOMICRMW_UMIN\0"	9837	/* 21112 */ "G_ATOMICRMW_UMIN\0"
9838	/* 21129 */ "G_ATOMICRMW_MIN\0"	9838	/* 21129 */ "G_ATOMICRMW_MIN\0"
9839	/* 21145 */ "G_FSIN\0"	9839	/* 21145 */ "G_FSIN\0"
9840	/* 21152 */ "DMFC2_OCTEON\0"	9840	/* 21152 */ "DMFC2_OCTEON\0"
9841	/* 21165 */ "DMTC2_OCTEON\0"	9841	/* 21165 */ "DMTC2_OCTEON\0"
9842	/* 21178 */ "CFI_INSTRUCTION\0"	9842	/* 21178 */ "CFI_INSTRUCTION\0"
9843	/* 21194 */ "ADJCALLSTACKDOWN\0"	9843	/* 21194 */ "ADJCALLSTACKDOWN\0"
9844	/* 21211 */ "G_SSUBO\0"	9844	/* 21211 */ "G_SSUBO\0"
9845	/* 21219 */ "G_USUBO\0"	9845	/* 21219 */ "G_USUBO\0"
9846	/* 21227 */ "G_SADDO\0"	9846	/* 21227 */ "G_SADDO\0"
9847	/* 21235 */ "G_UADDO\0"	9847	/* 21235 */ "G_UADDO\0"
9848	/* 21243 */ "FEXP2_D_1_PSEUDO\0"	9848	/* 21243 */ "FEXP2_D_1_PSEUDO\0"
9849	/* 21260 */ "FEXP2_W_1_PSEUDO\0"	9849	/* 21260 */ "FEXP2_W_1_PSEUDO\0"
9850	/* 21277 */ "BPOSGE32_PSEUDO\0"	9850	/* 21277 */ "BPOSGE32_PSEUDO\0"
9851	/* 21293 */ "INSERT_B_VIDX64_PSEUDO\0"	9851	/* 21293 */ "INSERT_B_VIDX64_PSEUDO\0"
9852	/* 21316 */ "INSERT_FD_VIDX64_PSEUDO\0"	9852	/* 21316 */ "INSERT_FD_VIDX64_PSEUDO\0"
9853	/* 21340 */ "INSERT_D_VIDX64_PSEUDO\0"	9853	/* 21340 */ "INSERT_D_VIDX64_PSEUDO\0"
9854	/* 21363 */ "INSERT_H_VIDX64_PSEUDO\0"	9854	/* 21363 */ "INSERT_H_VIDX64_PSEUDO\0"
9855	/* 21386 */ "INSERT_FW_VIDX64_PSEUDO\0"	9855	/* 21386 */ "INSERT_FW_VIDX64_PSEUDO\0"
9856	/* 21410 */ "INSERT_W_VIDX64_PSEUDO\0"	9856	/* 21410 */ "INSERT_W_VIDX64_PSEUDO\0"
9857	/* 21433 */ "SNZ_B_PSEUDO\0"	9857	/* 21433 */ "SNZ_B_PSEUDO\0"
9858	/* 21446 */ "SZ_B_PSEUDO\0"	9858	/* 21446 */ "SZ_B_PSEUDO\0"
9859	/* 21458 */ "BSEL_FD_PSEUDO\0"	9859	/* 21458 */ "BSEL_FD_PSEUDO\0"
9860	/* 21473 */ "FILL_FD_PSEUDO\0"	9860	/* 21473 */ "FILL_FD_PSEUDO\0"
9861	/* 21488 */ "INSERT_FD_PSEUDO\0"	9861	/* 21488 */ "INSERT_FD_PSEUDO\0"
9862	/* 21505 */ "COPY_FD_PSEUDO\0"	9862	/* 21505 */ "COPY_FD_PSEUDO\0"
9863	/* 21520 */ "MSA_FP_EXTEND_D_PSEUDO\0"	9863	/* 21520 */ "MSA_FP_EXTEND_D_PSEUDO\0"
9864	/* 21543 */ "MSA_FP_ROUND_D_PSEUDO\0"	9864	/* 21543 */ "MSA_FP_ROUND_D_PSEUDO\0"
9865	/* 21565 */ "BSEL_D_PSEUDO\0"	9865	/* 21565 */ "BSEL_D_PSEUDO\0"
9866	/* 21579 */ "AND_V_D_PSEUDO\0"	9866	/* 21579 */ "AND_V_D_PSEUDO\0"
9867	/* 21594 */ "NOR_V_D_PSEUDO\0"	9867	/* 21594 */ "NOR_V_D_PSEUDO\0"
9868	/* 21609 */ "XOR_V_D_PSEUDO\0"	9868	/* 21609 */ "XOR_V_D_PSEUDO\0"
9869	/* 21624 */ "SNZ_D_PSEUDO\0"	9869	/* 21624 */ "SNZ_D_PSEUDO\0"
9870	/* 21637 */ "SZ_D_PSEUDO\0"	9870	/* 21637 */ "SZ_D_PSEUDO\0"
9871	/* 21649 */ "BSEL_H_PSEUDO\0"	9871	/* 21649 */ "BSEL_H_PSEUDO\0"
9872	/* 21663 */ "AND_V_H_PSEUDO\0"	9872	/* 21663 */ "AND_V_H_PSEUDO\0"
9873	/* 21678 */ "NOR_V_H_PSEUDO\0"	9873	/* 21678 */ "NOR_V_H_PSEUDO\0"
9874	/* 21693 */ "XOR_V_H_PSEUDO\0"	9874	/* 21693 */ "XOR_V_H_PSEUDO\0"
9875	/* 21708 */ "SNZ_H_PSEUDO\0"	9875	/* 21708 */ "SNZ_H_PSEUDO\0"
9876	/* 21721 */ "SZ_H_PSEUDO\0"	9876	/* 21721 */ "SZ_H_PSEUDO\0"
9877	/* 21733 */ "SNZ_V_PSEUDO\0"	9877	/* 21733 */ "SNZ_V_PSEUDO\0"
9878	/* 21746 */ "SZ_V_PSEUDO\0"	9878	/* 21746 */ "SZ_V_PSEUDO\0"
9879	/* 21758 */ "BSEL_FW_PSEUDO\0"	9879	/* 21758 */ "BSEL_FW_PSEUDO\0"
9880	/* 21773 */ "FILL_FW_PSEUDO\0"	9880	/* 21773 */ "FILL_FW_PSEUDO\0"
9881	/* 21788 */ "INSERT_FW_PSEUDO\0"	9881	/* 21788 */ "INSERT_FW_PSEUDO\0"
9882	/* 21805 */ "COPY_FW_PSEUDO\0"	9882	/* 21805 */ "COPY_FW_PSEUDO\0"
9883	/* 21820 */ "MSA_FP_EXTEND_W_PSEUDO\0"	9883	/* 21820 */ "MSA_FP_EXTEND_W_PSEUDO\0"
9884	/* 21843 */ "MSA_FP_ROUND_W_PSEUDO\0"	9884	/* 21843 */ "MSA_FP_ROUND_W_PSEUDO\0"
9885	/* 21865 */ "BSEL_W_PSEUDO\0"	9885	/* 21865 */ "BSEL_W_PSEUDO\0"
9886	/* 21879 */ "AND_V_W_PSEUDO\0"	9886	/* 21879 */ "AND_V_W_PSEUDO\0"
9887	/* 21894 */ "NOR_V_W_PSEUDO\0"	9887	/* 21894 */ "NOR_V_W_PSEUDO\0"
9888	/* 21909 */ "XOR_V_W_PSEUDO\0"	9888	/* 21909 */ "XOR_V_W_PSEUDO\0"
9889	/* 21924 */ "SNZ_W_PSEUDO\0"	9889	/* 21924 */ "SNZ_W_PSEUDO\0"
9890	/* 21937 */ "SZ_W_PSEUDO\0"	9890	/* 21937 */ "SZ_W_PSEUDO\0"
9891	/* 21949 */ "INSERT_B_VIDX_PSEUDO\0"	9891	/* 21949 */ "INSERT_B_VIDX_PSEUDO\0"
9892	/* 21970 */ "INSERT_FD_VIDX_PSEUDO\0"	9892	/* 21970 */ "INSERT_FD_VIDX_PSEUDO\0"
9893	/* 21992 */ "INSERT_D_VIDX_PSEUDO\0"	9893	/* 21992 */ "INSERT_D_VIDX_PSEUDO\0"
9894	/* 22013 */ "INSERT_H_VIDX_PSEUDO\0"	9894	/* 22013 */ "INSERT_H_VIDX_PSEUDO\0"
9895	/* 22034 */ "INSERT_FW_VIDX_PSEUDO\0"	9895	/* 22034 */ "INSERT_FW_VIDX_PSEUDO\0"
9896	/* 22056 */ "INSERT_W_VIDX_PSEUDO\0"	9896	/* 22056 */ "INSERT_W_VIDX_PSEUDO\0"
9897	/* 22077 */ "DCLO\0"	9897	/* 22077 */ "DCLO\0"
9898	/* 22082 */ "PseudoMFLO\0"	9898	/* 22082 */ "PseudoMFLO\0"
9899	/* 22093 */ "SHILO\0"	9899	/* 22093 */ "SHILO\0"
9900	/* 22099 */ "MFTLO\0"	9900	/* 22099 */ "MFTLO\0"
9901	/* 22105 */ "MTLO\0"	9901	/* 22105 */ "MTLO\0"
9902	/* 22110 */ "MTTLO\0"	9902	/* 22110 */ "MTTLO\0"
9903	/* 22116 */ "G_SMULO\0"	9903	/* 22116 */ "G_SMULO\0"
9904	/* 22124 */ "G_UMULO\0"	9904	/* 22124 */ "G_UMULO\0"
9905	/* 22132 */ "G_BZERO\0"	9905	/* 22132 */ "G_BZERO\0"
9906	/* 22140 */ "STACKMAP\0"	9906	/* 22140 */ "STACKMAP\0"
9907	/* 22149 */ "TRAP\0"	9907	/* 22149 */ "TRAP\0"
9908	/* 22154 */ "G_ATOMICRMW_UDEC_WRAP\0"	9908	/* 22154 */ "G_ATOMICRMW_UDEC_WRAP\0"
9909	/* 22176 */ "G_ATOMICRMW_UINC_WRAP\0"	9909	/* 22176 */ "G_ATOMICRMW_UINC_WRAP\0"
9910	/* 22198 */ "G_BSWAP\0"	9910	/* 22198 */ "G_BSWAP\0"
9911	/* 22206 */ "DBITSWAP\0"	9911	/* 22206 */ "DBITSWAP\0"
9912	/* 22215 */ "SDBBP\0"	9912	/* 22215 */ "SDBBP\0"
9913	/* 22221 */ "TLBP\0"	9913	/* 22221 */ "TLBP\0"
9914	/* 22226 */ "EXTPDP\0"	9914	/* 22226 */ "EXTPDP\0"
9915	/* 22233 */ "G_SITOFP\0"	9915	/* 22233 */ "G_SITOFP\0"
9916	/* 22242 */ "G_UITOFP\0"	9916	/* 22242 */ "G_UITOFP\0"
9917	/* 22251 */ "TLBGP\0"	9917	/* 22251 */ "TLBGP\0"
9918	/* 22257 */ "MTHLIP\0"	9918	/* 22257 */ "MTHLIP\0"
9919	/* 22264 */ "G_FCMP\0"	9919	/* 22264 */ "G_FCMP\0"
9920	/* 22271 */ "G_ICMP\0"	9920	/* 22271 */ "G_ICMP\0"
9921	/* 22278 */ "SSNOP\0"	9921	/* 22278 */ "SSNOP\0"
9922	/* 22284 */ "DPOP\0"	9922	/* 22284 */ "DPOP\0"
9923	/* 22289 */ "G_CTPOP\0"	9923	/* 22289 */ "G_CTPOP\0"
9924	/* 22297 */ "PATCHABLE_OP\0"	9924	/* 22297 */ "PATCHABLE_OP\0"
9925	/* 22310 */ "FAULTING_OP\0"	9925	/* 22310 */ "FAULTING_OP\0"
9926	/* 22322 */ "LOAD_ACC64DSP\0"	9926	/* 22322 */ "LOAD_ACC64DSP\0"
9927	/* 22336 */ "STORE_ACC64DSP\0"	9927	/* 22336 */ "STORE_ACC64DSP\0"
9928	/* 22351 */ "RDDSP\0"	9928	/* 22351 */ "RDDSP\0"
9929	/* 22357 */ "WRDSP\0"	9929	/* 22357 */ "WRDSP\0"
9930	/* 22363 */ "MFTDSP\0"	9930	/* 22363 */ "MFTDSP\0"
9931	/* 22370 */ "MTTDSP\0"	9931	/* 22370 */ "MTTDSP\0"
9932	/* 22377 */ "LWDSP\0"	9932	/* 22377 */ "LWDSP\0"
9933	/* 22383 */ "SWDSP\0"	9933	/* 22383 */ "SWDSP\0"
9934	/* 22389 */ "MSUB_DSP\0"	9934	/* 22389 */ "MSUB_DSP\0"
9935	/* 22398 */ "MADD_DSP\0"	9935	/* 22398 */ "MADD_DSP\0"
9936	/* 22407 */ "LOAD_CCOND_DSP\0"	9936	/* 22407 */ "LOAD_CCOND_DSP\0"
9937	/* 22422 */ "STORE_CCOND_DSP\0"	9937	/* 22422 */ "STORE_CCOND_DSP\0"
9938	/* 22438 */ "MFHI_DSP\0"	9938	/* 22438 */ "MFHI_DSP\0"
9939	/* 22447 */ "PseudoMTLOHI_DSP\0"	9939	/* 22447 */ "PseudoMTLOHI_DSP\0"
9940	/* 22464 */ "MTHI_DSP\0"	9940	/* 22464 */ "MTHI_DSP\0"
9941	/* 22473 */ "MFLO_DSP\0"	9941	/* 22473 */ "MFLO_DSP\0"
9942	/* 22482 */ "MTLO_DSP\0"	9942	/* 22482 */ "MTLO_DSP\0"
9943	/* 22491 */ "MULT_DSP\0"	9943	/* 22491 */ "MULT_DSP\0"
9944	/* 22500 */ "MSUBU_DSP\0"	9944	/* 22500 */ "MSUBU_DSP\0"
9945	/* 22510 */ "MADDU_DSP\0"	9945	/* 22510 */ "MADDU_DSP\0"
9946	/* 22520 */ "MULTU_DSP\0"	9946	/* 22520 */ "MULTU_DSP\0"
9947	/* 22530 */ "JRADDIUSP\0"	9947	/* 22530 */ "JRADDIUSP\0"
9948	/* 22540 */ "EXTP\0"	9948	/* 22540 */ "EXTP\0"
9949	/* 22545 */ "ADJCALLSTACKUP\0"	9949	/* 22545 */ "ADJCALLSTACKUP\0"
9950	/* 22560 */ "PREALLOCATED_SETUP\0"	9950	/* 22560 */ "PREALLOCATED_SETUP\0"
9951	/* 22579 */ "DVP\0"	9951	/* 22579 */ "DVP\0"
9952	/* 22583 */ "EVP\0"	9952	/* 22583 */ "EVP\0"
9953	/* 22587 */ "G_FLDEXP\0"	9953	/* 22587 */ "G_FLDEXP\0"
9954	/* 22596 */ "G_STRICT_FLDEXP\0"	9954	/* 22596 */ "G_STRICT_FLDEXP\0"
9955	/* 22612 */ "G_FEXP\0"	9955	/* 22612 */ "G_FEXP\0"
9956	/* 22619 */ "G_FFREXP\0"	9956	/* 22619 */ "G_FFREXP\0"
9957	/* 22628 */ "BEQ\0"	9957	/* 22628 */ "BEQ\0"
9958	/* 22632 */ "SEQ\0"	9958	/* 22632 */ "SEQ\0"
9959	/* 22636 */ "TEQ\0"	9959	/* 22636 */ "TEQ\0"
9960	/* 22640 */ "TLBR\0"	9960	/* 22640 */ "TLBR\0"
9961	/* 22645 */ "MULEU_S_PH_QBR\0"	9961	/* 22645 */ "MULEU_S_PH_QBR\0"
9962	/* 22660 */ "PRECEU_PH_QBR\0"	9962	/* 22660 */ "PRECEU_PH_QBR\0"
9963	/* 22674 */ "PRECEQU_PH_QBR\0"	9963	/* 22674 */ "PRECEQU_PH_QBR\0"
9964	/* 22689 */ "DPAU_H_QBR\0"	9964	/* 22689 */ "DPAU_H_QBR\0"
9965	/* 22700 */ "DPSU_H_QBR\0"	9965	/* 22700 */ "DPSU_H_QBR\0"
9966	/* 22711 */ "G_BR\0"	9966	/* 22711 */ "G_BR\0"
9967	/* 22716 */ "BAL_BR\0"	9967	/* 22716 */ "BAL_BR\0"
9968	/* 22723 */ "INLINEASM_BR\0"	9968	/* 22723 */ "INLINEASM_BR\0"
9969	/* 22736 */ "G_BLOCK_ADDR\0"	9969	/* 22736 */ "G_BLOCK_ADDR\0"
9970	/* 22749 */ "LDR\0"	9970	/* 22749 */ "LDR\0"
9971	/* 22753 */ "SDR\0"	9971	/* 22753 */ "SDR\0"
9972	/* 22757 */ "MEMBARRIER\0"	9972	/* 22757 */ "MEMBARRIER\0"
9973	/* 22768 */ "G_CONSTANT_FOLD_BARRIER\0"	9973	/* 22768 */ "G_CONSTANT_FOLD_BARRIER\0"
9974	/* 22792 */ "PATCHABLE_FUNCTION_ENTER\0"	9974	/* 22792 */ "PATCHABLE_FUNCTION_ENTER\0"
9975	/* 22817 */ "G_READCYCLECOUNTER\0"	9975	/* 22817 */ "G_READCYCLECOUNTER\0"
9976	/* 22836 */ "G_READ_REGISTER\0"	9976	/* 22836 */ "G_READ_REGISTER\0"
9977	/* 22852 */ "G_WRITE_REGISTER\0"	9977	/* 22852 */ "G_WRITE_REGISTER\0"
9978	/* 22869 */ "TLBGR\0"	9978	/* 22869 */ "TLBGR\0"
9979	/* 22875 */ "LoadImmDoubleFGR\0"	9979	/* 22875 */ "LoadImmDoubleFGR\0"
9980	/* 22892 */ "LoadImmSingleFGR\0"	9980	/* 22892 */ "LoadImmSingleFGR\0"
9981	/* 22909 */ "MAQ_SA_W_PHR\0"	9981	/* 22909 */ "MAQ_SA_W_PHR\0"
9982	/* 22922 */ "PRECEQ_W_PHR\0"	9982	/* 22922 */ "PRECEQ_W_PHR\0"
9983	/* 22935 */ "MAQ_S_W_PHR\0"	9983	/* 22935 */ "MAQ_S_W_PHR\0"
9984	/* 22947 */ "MULEQ_S_W_PHR\0"	9984	/* 22947 */ "MULEQ_S_W_PHR\0"
9985	/* 22961 */ "G_ASHR\0"	9985	/* 22961 */ "G_ASHR\0"
9986	/* 22968 */ "G_FSHR\0"	9986	/* 22968 */ "G_FSHR\0"
9987	/* 22975 */ "G_LSHR\0"	9987	/* 22975 */ "G_LSHR\0"
9988	/* 22982 */ "JR\0"	9988	/* 22982 */ "JR\0"
9989	/* 22985 */ "JALR\0"	9989	/* 22985 */ "JALR\0"
9990	/* 22990 */ "NOR\0"	9990	/* 22990 */ "NOR\0"
9991	/* 22994 */ "G_FFLOOR\0"	9991	/* 22994 */ "G_FFLOOR\0"
9992	/* 23003 */ "DROR\0"	9992	/* 23003 */ "DROR\0"
9993	/* 23008 */ "G_BUILD_VECTOR\0"	9993	/* 23008 */ "G_BUILD_VECTOR\0"
9994	/* 23023 */ "G_SHUFFLE_VECTOR\0"	9994	/* 23023 */ "G_SHUFFLE_VECTOR\0"
9995	/* 23040 */ "G_VECREDUCE_XOR\0"	9995	/* 23040 */ "G_VECREDUCE_XOR\0"
9996	/* 23056 */ "G_XOR\0"	9996	/* 23056 */ "G_XOR\0"
9997	/* 23062 */ "G_ATOMICRMW_XOR\0"	9997	/* 23062 */ "G_ATOMICRMW_XOR\0"
9998	/* 23078 */ "G_VECREDUCE_OR\0"	9998	/* 23078 */ "G_VECREDUCE_OR\0"
9999	/* 23093 */ "G_OR\0"	9999	/* 23093 */ "G_OR\0"
10000	/* 23098 */ "G_ATOMICRMW_OR\0"	10000	/* 23098 */ "G_ATOMICRMW_OR\0"
10001	/* 23113 */ "MFTGPR\0"	10001	/* 23113 */ "MFTGPR\0"
10002	/* 23120 */ "MTTGPR\0"	10002	/* 23120 */ "MTTGPR\0"
10003	/* 23127 */ "LoadImmDoubleGPR\0"	10003	/* 23127 */ "LoadImmDoubleGPR\0"
10004	/* 23144 */ "LoadImmSingleGPR\0"	10004	/* 23144 */ "LoadImmSingleGPR\0"
10005	/* 23161 */ "MFTR\0"	10005	/* 23161 */ "MFTR\0"
10006	/* 23166 */ "DROTR\0"	10006	/* 23166 */ "DROTR\0"
10007	/* 23172 */ "G_ROTR\0"	10007	/* 23172 */ "G_ROTR\0"
10008	/* 23179 */ "G_INTTOPTR\0"	10008	/* 23179 */ "G_INTTOPTR\0"
10009	/* 23190 */ "MTTR\0"	10009	/* 23190 */ "MTTR\0"
10010	/* 23195 */ "TLBWR\0"	10010	/* 23195 */ "TLBWR\0"
10011	/* 23201 */ "TLBGWR\0"	10011	/* 23201 */ "TLBGWR\0"
10012	/* 23208 */ "RDHWR\0"	10012	/* 23208 */ "RDHWR\0"
10013	/* 23214 */ "LWR\0"	10013	/* 23214 */ "LWR\0"
10014	/* 23218 */ "SWR\0"	10014	/* 23218 */ "SWR\0"
10015	/* 23222 */ "G_FABS\0"	10015	/* 23222 */ "G_FABS\0"
10016	/* 23229 */ "G_ABS\0"	10016	/* 23229 */ "G_ABS\0"
10017	/* 23235 */ "G_UNMERGE_VALUES\0"	10017	/* 23235 */ "G_UNMERGE_VALUES\0"
10018	/* 23252 */ "G_MERGE_VALUES\0"	10018	/* 23252 */ "G_MERGE_VALUES\0"
10019	/* 23267 */ "CINS\0"	10019	/* 23267 */ "CINS\0"
10020	/* 23272 */ "DINS\0"	10020	/* 23272 */ "DINS\0"
10021	/* 23277 */ "G_FCOS\0"	10021	/* 23277 */ "G_FCOS\0"
10022	/* 23284 */ "G_CONCAT_VECTORS\0"	10022	/* 23284 */ "G_CONCAT_VECTORS\0"
10023	/* 23301 */ "COPY_TO_REGCLASS\0"	10023	/* 23301 */ "COPY_TO_REGCLASS\0"
10024	/* 23318 */ "G_IS_FPCLASS\0"	10024	/* 23318 */ "G_IS_FPCLASS\0"
10025	/* 23331 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"	10025	/* 23331 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
10026	/* 23361 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"	10026	/* 23361 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
10027	/* 23388 */ "EXTS\0"	10027	/* 23388 */ "EXTS\0"
10028	/* 23393 */ "CVT_D32_S\0"	10028	/* 23393 */ "CVT_D32_S\0"
10029	/* 23403 */ "CVT_D64_S\0"	10029	/* 23403 */ "CVT_D64_S\0"
10030	/* 23413 */ "MOVN_I64_S\0"	10030	/* 23413 */ "MOVN_I64_S\0"
10031	/* 23424 */ "MOVZ_I64_S\0"	10031	/* 23424 */ "MOVZ_I64_S\0"
10032	/* 23435 */ "MINA_S\0"	10032	/* 23435 */ "MINA_S\0"
10033	/* 23442 */ "MAXA_S\0"	10033	/* 23442 */ "MAXA_S\0"
10034	/* 23449 */ "FSUB_S\0"	10034	/* 23449 */ "FSUB_S\0"
10035	/* 23456 */ "NMSUB_S\0"	10035	/* 23456 */ "NMSUB_S\0"
10036	/* 23464 */ "FADD_S\0"	10036	/* 23464 */ "FADD_S\0"
10037	/* 23471 */ "NMADD_S\0"	10037	/* 23471 */ "NMADD_S\0"
10038	/* 23479 */ "C_NGE_S\0"	10038	/* 23479 */ "C_NGE_S\0"
10039	/* 23487 */ "C_NGLE_S\0"	10039	/* 23487 */ "C_NGLE_S\0"
10040	/* 23496 */ "C_OLE_S\0"	10040	/* 23496 */ "C_OLE_S\0"
10041	/* 23504 */ "CMP_SLE_S\0"	10041	/* 23504 */ "CMP_SLE_S\0"
10042	/* 23514 */ "CMP_SULE_S\0"	10042	/* 23514 */ "CMP_SULE_S\0"
10043	/* 23525 */ "C_ULE_S\0"	10043	/* 23525 */ "C_ULE_S\0"
10044	/* 23533 */ "CMP_ULE_S\0"	10044	/* 23533 */ "CMP_ULE_S\0"
10045	/* 23543 */ "C_LE_S\0"	10045	/* 23543 */ "C_LE_S\0"
10046	/* 23550 */ "CMP_LE_S\0"	10046	/* 23550 */ "CMP_LE_S\0"
10047	/* 23559 */ "CMP_SAF_S\0"	10047	/* 23559 */ "CMP_SAF_S\0"
10048	/* 23569 */ "MSUBF_S\0"	10048	/* 23569 */ "MSUBF_S\0"
10049	/* 23577 */ "MADDF_S\0"	10049	/* 23577 */ "MADDF_S\0"
10050	/* 23585 */ "C_SF_S\0"	10050	/* 23585 */ "C_SF_S\0"
10051	/* 23592 */ "MOVF_S\0"	10051	/* 23592 */ "MOVF_S\0"
10052	/* 23599 */ "C_F_S\0"	10052	/* 23599 */ "C_F_S\0"
10053	/* 23605 */ "PseudoSELECTFP_F_S\0"	10053	/* 23605 */ "PseudoSELECTFP_F_S\0"
10054	/* 23624 */ "CMP_F_S\0"	10054	/* 23624 */ "CMP_F_S\0"
10055	/* 23632 */ "FNEG_S\0"	10055	/* 23632 */ "FNEG_S\0"
10056	/* 23639 */ "MOVN_I_S\0"	10056	/* 23639 */ "MOVN_I_S\0"
10057	/* 23648 */ "MOVZ_I_S\0"	10057	/* 23648 */ "MOVZ_I_S\0"
10058	/* 23657 */ "SEL_S\0"	10058	/* 23657 */ "SEL_S\0"
10059	/* 23663 */ "C_NGL_S\0"	10059	/* 23663 */ "C_NGL_S\0"
10060	/* 23671 */ "FMUL_S\0"	10060	/* 23671 */ "FMUL_S\0"
10061	/* 23678 */ "TRUNC_L_S\0"	10061	/* 23678 */ "TRUNC_L_S\0"
10062	/* 23688 */ "ROUND_L_S\0"	10062	/* 23688 */ "ROUND_L_S\0"
10063	/* 23698 */ "CEIL_L_S\0"	10063	/* 23698 */ "CEIL_L_S\0"
10064	/* 23707 */ "FLOOR_L_S\0"	10064	/* 23707 */ "FLOOR_L_S\0"
10065	/* 23717 */ "CVT_L_S\0"	10065	/* 23717 */ "CVT_L_S\0"
10066	/* 23725 */ "MIN_S\0"	10066	/* 23725 */ "MIN_S\0"
10067	/* 23731 */ "CMP_SUN_S\0"	10067	/* 23731 */ "CMP_SUN_S\0"
10068	/* 23741 */ "C_UN_S\0"	10068	/* 23741 */ "C_UN_S\0"
10069	/* 23748 */ "CMP_UN_S\0"	10069	/* 23748 */ "CMP_UN_S\0"
10070	/* 23757 */ "RECIP_S\0"	10070	/* 23757 */ "RECIP_S\0"
10071	/* 23765 */ "C_SEQ_S\0"	10071	/* 23765 */ "C_SEQ_S\0"
10072	/* 23773 */ "CMP_SEQ_S\0"	10072	/* 23773 */ "CMP_SEQ_S\0"
10073	/* 23783 */ "CMP_SUEQ_S\0"	10073	/* 23783 */ "CMP_SUEQ_S\0"
10074	/* 23794 */ "C_UEQ_S\0"	10074	/* 23794 */ "C_UEQ_S\0"
10075	/* 23802 */ "CMP_UEQ_S\0"	10075	/* 23802 */ "CMP_UEQ_S\0"
10076	/* 23812 */ "C_EQ_S\0"	10076	/* 23812 */ "C_EQ_S\0"
10077	/* 23819 */ "CMP_EQ_S\0"	10077	/* 23819 */ "CMP_EQ_S\0"
10078	/* 23828 */ "FABS_S\0"	10078	/* 23828 */ "FABS_S\0"
10079	/* 23835 */ "CLASS_S\0"	10079	/* 23835 */ "CLASS_S\0"
10080	/* 23843 */ "PseudoSELECT_S\0"	10080	/* 23843 */ "PseudoSELECT_S\0"
10081	/* 23858 */ "C_NGT_S\0"	10081	/* 23858 */ "C_NGT_S\0"
10082	/* 23866 */ "C_OLT_S\0"	10082	/* 23866 */ "C_OLT_S\0"
10083	/* 23874 */ "CMP_SLT_S\0"	10083	/* 23874 */ "CMP_SLT_S\0"
10084	/* 23884 */ "CMP_SULT_S\0"	10084	/* 23884 */ "CMP_SULT_S\0"
10085	/* 23895 */ "C_ULT_S\0"	10085	/* 23895 */ "C_ULT_S\0"
10086	/* 23903 */ "CMP_ULT_S\0"	10086	/* 23903 */ "CMP_ULT_S\0"
10087	/* 23913 */ "C_LT_S\0"	10087	/* 23913 */ "C_LT_S\0"
10088	/* 23920 */ "CMP_LT_S\0"	10088	/* 23920 */ "CMP_LT_S\0"
10089	/* 23929 */ "RINT_S\0"	10089	/* 23929 */ "RINT_S\0"
10090	/* 23936 */ "FSQRT_S\0"	10090	/* 23936 */ "FSQRT_S\0"
10091	/* 23944 */ "RSQRT_S\0"	10091	/* 23944 */ "RSQRT_S\0"
10092	/* 23952 */ "MOVT_S\0"	10092	/* 23952 */ "MOVT_S\0"
10093	/* 23959 */ "PseudoSELECTFP_T_S\0"	10093	/* 23959 */ "PseudoSELECTFP_T_S\0"
10094	/* 23978 */ "FDIV_S\0"	10094	/* 23978 */ "FDIV_S\0"
10095	/* 23985 */ "FMOV_S\0"	10095	/* 23985 */ "FMOV_S\0"
10096	/* 23992 */ "PseudoTRUNC_W_S\0"	10096	/* 23992 */ "PseudoTRUNC_W_S\0"
10097	/* 24008 */ "ROUND_W_S\0"	10097	/* 24008 */ "ROUND_W_S\0"
10098	/* 24018 */ "CEIL_W_S\0"	10098	/* 24018 */ "CEIL_W_S\0"
10099	/* 24027 */ "FLOOR_W_S\0"	10099	/* 24027 */ "FLOOR_W_S\0"
10100	/* 24037 */ "CVT_W_S\0"	10100	/* 24037 */ "CVT_W_S\0"
10101	/* 24045 */ "MAX_S\0"	10101	/* 24045 */ "MAX_S\0"
10102	/* 24051 */ "SELNEZ_S\0"	10102	/* 24051 */ "SELNEZ_S\0"
10103	/* 24060 */ "SELEQZ_S\0"	10103	/* 24060 */ "SELEQZ_S\0"
10104	/* 24069 */ "BC1T\0"	10104	/* 24069 */ "BC1T\0"
10105	/* 24074 */ "G_SSUBSAT\0"	10105	/* 24074 */ "G_SSUBSAT\0"
10106	/* 24084 */ "G_USUBSAT\0"	10106	/* 24084 */ "G_USUBSAT\0"
10107	/* 24094 */ "G_SADDSAT\0"	10107	/* 24094 */ "G_SADDSAT\0"
10108	/* 24104 */ "G_UADDSAT\0"	10108	/* 24104 */ "G_UADDSAT\0"
10109	/* 24114 */ "G_SSHLSAT\0"	10109	/* 24114 */ "G_SSHLSAT\0"
10110	/* 24124 */ "G_USHLSAT\0"	10110	/* 24124 */ "G_USHLSAT\0"
10111	/* 24134 */ "G_SMULFIXSAT\0"	10111	/* 24134 */ "G_SMULFIXSAT\0"
10112	/* 24147 */ "G_UMULFIXSAT\0"	10112	/* 24147 */ "G_UMULFIXSAT\0"
10113	/* 24160 */ "G_SDIVFIXSAT\0"	10113	/* 24160 */ "G_SDIVFIXSAT\0"
10114	/* 24173 */ "G_UDIVFIXSAT\0"	10114	/* 24173 */ "G_UDIVFIXSAT\0"
10115	/* 24186 */ "G_EXTRACT\0"	10115	/* 24186 */ "G_EXTRACT\0"
10116	/* 24196 */ "G_SELECT\0"	10116	/* 24196 */ "G_SELECT\0"
10117	/* 24205 */ "G_BRINDIRECT\0"	10117	/* 24205 */ "G_BRINDIRECT\0"
10118	/* 24218 */ "DERET\0"	10118	/* 24218 */ "DERET\0"
10119	/* 24224 */ "PATCHABLE_RET\0"	10119	/* 24224 */ "PATCHABLE_RET\0"
10120	/* 24238 */ "G_MEMSET\0"	10120	/* 24238 */ "G_MEMSET\0"
10121	/* 24247 */ "BGT\0"	10121	/* 24247 */ "BGT\0"
10122	/* 24251 */ "WAIT\0"	10122	/* 24251 */ "WAIT\0"
10123	/* 24256 */ "PATCHABLE_FUNCTION_EXIT\0"	10123	/* 24256 */ "PATCHABLE_FUNCTION_EXIT\0"
10124	/* 24280 */ "G_BRJT\0"	10124	/* 24280 */ "G_BRJT\0"
10125	/* 24287 */ "BLT\0"	10125	/* 24287 */ "BLT\0"
10126	/* 24291 */ "G_EXTRACT_VECTOR_ELT\0"	10126	/* 24291 */ "G_EXTRACT_VECTOR_ELT\0"
10127	/* 24312 */ "G_INSERT_VECTOR_ELT\0"	10127	/* 24312 */ "G_INSERT_VECTOR_ELT\0"
10128	/* 24332 */ "SLT\0"	10128	/* 24332 */ "SLT\0"
10129	/* 24336 */ "TLT\0"	10129	/* 24336 */ "TLT\0"
10130	/* 24340 */ "PseudoDMULT\0"	10130	/* 24340 */ "PseudoDMULT\0"
10131	/* 24352 */ "PseudoMULT\0"	10131	/* 24352 */ "PseudoMULT\0"
10132	/* 24363 */ "DMT\0"	10132	/* 24363 */ "DMT\0"
10133	/* 24367 */ "EMT\0"	10133	/* 24367 */ "EMT\0"
10134	/* 24371 */ "G_FCONSTANT\0"	10134	/* 24371 */ "G_FCONSTANT\0"
10135	/* 24383 */ "G_CONSTANT\0"	10135	/* 24383 */ "G_CONSTANT\0"
10136	/* 24394 */ "STATEPOINT\0"	10136	/* 24394 */ "STATEPOINT\0"
10137	/* 24405 */ "PATCHPOINT\0"	10137	/* 24405 */ "PATCHPOINT\0"
10138	/* 24416 */ "G_PTRTOINT\0"	10138	/* 24416 */ "G_PTRTOINT\0"
10139	/* 24427 */ "G_FRINT\0"	10139	/* 24427 */ "G_FRINT\0"
10140	/* 24435 */ "G_INTRINSIC_LRINT\0"	10140	/* 24435 */ "G_INTRINSIC_LRINT\0"
10141	/* 24453 */ "G_FNEARBYINT\0"	10141	/* 24453 */ "G_FNEARBYINT\0"
10142	/* 24466 */ "G_VASTART\0"	10142	/* 24466 */ "G_VASTART\0"
10143	/* 24476 */ "LIFETIME_START\0"	10143	/* 24476 */ "LIFETIME_START\0"
10144	/* 24491 */ "G_INVOKE_REGION_START\0"	10144	/* 24491 */ "G_INVOKE_REGION_START\0"
10145	/* 24513 */ "G_INSERT\0"	10145	/* 24513 */ "G_INSERT\0"
10146	/* 24522 */ "G_FSQRT\0"	10146	/* 24522 */ "G_FSQRT\0"
10147	/* 24530 */ "G_STRICT_FSQRT\0"	10147	/* 24530 */ "G_STRICT_FSQRT\0"
10148	/* 24545 */ "G_BITCAST\0"	10148	/* 24545 */ "G_BITCAST\0"
10149	/* 24555 */ "G_ADDRSPACE_CAST\0"	10149	/* 24555 */ "G_ADDRSPACE_CAST\0"
10150	/* 24572 */ "DBG_VALUE_LIST\0"	10150	/* 24572 */ "DBG_VALUE_LIST\0"
10151	/* 24587 */ "GINVT\0"	10151	/* 24587 */ "GINVT\0"
10152	/* 24593 */ "DEXT\0"	10152	/* 24593 */ "DEXT\0"
10153	/* 24598 */ "G_FPEXT\0"	10153	/* 24598 */ "G_FPEXT\0"
10154	/* 24606 */ "G_SEXT\0"	10154	/* 24606 */ "G_SEXT\0"
10155	/* 24613 */ "G_ASSERT_SEXT\0"	10155	/* 24613 */ "G_ASSERT_SEXT\0"
10156	/* 24627 */ "G_ANYEXT\0"	10156	/* 24627 */ "G_ANYEXT\0"
10157	/* 24636 */ "G_ZEXT\0"	10157	/* 24636 */ "G_ZEXT\0"
10158	/* 24643 */ "G_ASSERT_ZEXT\0"	10158	/* 24643 */ "G_ASSERT_ZEXT\0"
10159	/* 24657 */ "PseudoMSUBU\0"	10159	/* 24657 */ "PseudoMSUBU\0"
10160	/* 24669 */ "PseudoMADDU\0"	10160	/* 24669 */ "PseudoMADDU\0"
10161	/* 24681 */ "DMODU\0"	10161	/* 24681 */ "DMODU\0"
10162	/* 24687 */ "BGEU\0"	10162	/* 24687 */ "BGEU\0"
10163	/* 24692 */ "SGEU\0"	10163	/* 24692 */ "SGEU\0"
10164	/* 24697 */ "TGEU\0"	10164	/* 24697 */ "TGEU\0"
10165	/* 24702 */ "BLEU\0"	10165	/* 24702 */ "BLEU\0"
10166	/* 24707 */ "SLEU\0"	10166	/* 24707 */ "SLEU\0"
10167	/* 24712 */ "DMUHU\0"	10167	/* 24712 */ "DMUHU\0"
10168	/* 24718 */ "TGEIU\0"	10168	/* 24718 */ "TGEIU\0"
10169	/* 24724 */ "TTLTIU\0"	10169	/* 24724 */ "TTLTIU\0"
10170	/* 24731 */ "V3MULU\0"	10170	/* 24731 */ "V3MULU\0"
10171	/* 24738 */ "DMULU\0"	10171	/* 24738 */ "DMULU\0"
10172	/* 24744 */ "VMULU\0"	10172	/* 24744 */ "VMULU\0"
10173	/* 24750 */ "DINSU\0"	10173	/* 24750 */ "DINSU\0"
10174	/* 24756 */ "BGTU\0"	10174	/* 24756 */ "BGTU\0"
10175	/* 24761 */ "BLTU\0"	10175	/* 24761 */ "BLTU\0"
10176	/* 24766 */ "TLTU\0"	10176	/* 24766 */ "TLTU\0"
10177	/* 24771 */ "DEXTU\0"	10177	/* 24771 */ "DEXTU\0"
10178	/* 24777 */ "DDIVU\0"	10178	/* 24777 */ "DDIVU\0"
10179	/* 24783 */ "DSRAV\0"	10179	/* 24783 */ "DSRAV\0"
10180	/* 24789 */ "BITREV\0"	10180	/* 24789 */ "BITREV\0"
10181	/* 24796 */ "DDIV\0"	10181	/* 24796 */ "DDIV\0"
10182	/* 24801 */ "G_FDIV\0"	10182	/* 24801 */ "G_FDIV\0"
10183	/* 24808 */ "G_STRICT_FDIV\0"	10183	/* 24808 */ "G_STRICT_FDIV\0"
10184	/* 24822 */ "PseudoDSDIV\0"	10184	/* 24822 */ "PseudoDSDIV\0"
10185	/* 24834 */ "G_SDIV\0"	10185	/* 24834 */ "G_SDIV\0"
10186	/* 24841 */ "PseudoSDIV\0"	10186	/* 24841 */ "PseudoSDIV\0"
10187	/* 24852 */ "PseudoDUDIV\0"	10187	/* 24852 */ "PseudoDUDIV\0"
10188	/* 24864 */ "G_UDIV\0"	10188	/* 24864 */ "G_UDIV\0"
10189	/* 24871 */ "PseudoUDIV\0"	10189	/* 24871 */ "PseudoUDIV\0"
10190	/* 24882 */ "DSLLV\0"	10190	/* 24882 */ "DSLLV\0"
10191	/* 24888 */ "DSRLV\0"	10191	/* 24888 */ "DSRLV\0"
10192	/* 24894 */ "TLBINV\0"	10192	/* 24894 */ "TLBINV\0"
10193	/* 24901 */ "TLBGINV\0"	10193	/* 24901 */ "TLBGINV\0"
10194	/* 24909 */ "SHILOV\0"	10194	/* 24909 */ "SHILOV\0"
10195	/* 24916 */ "EXTPDPV\0"	10195	/* 24916 */ "EXTPDPV\0"
10196	/* 24924 */ "EXTPV\0"	10196	/* 24924 */ "EXTPV\0"
10197	/* 24930 */ "DROTRV\0"	10197	/* 24930 */ "DROTRV\0"
10198	/* 24937 */ "INSV\0"	10198	/* 24937 */ "INSV\0"
10199	/* 24942 */ "AND_V\0"	10199	/* 24942 */ "AND_V\0"
10200	/* 24948 */ "MOVE_V\0"	10200	/* 24948 */ "MOVE_V\0"
10201	/* 24955 */ "BSEL_V\0"	10201	/* 24955 */ "BSEL_V\0"
10202	/* 24962 */ "NOR_V\0"	10202	/* 24962 */ "NOR_V\0"
10203	/* 24968 */ "XOR_V\0"	10203	/* 24968 */ "XOR_V\0"
10204	/* 24974 */ "BZ_V\0"	10204	/* 24974 */ "BZ_V\0"
10205	/* 24979 */ "BMZ_V\0"	10205	/* 24979 */ "BMZ_V\0"
10206	/* 24985 */ "BNZ_V\0"	10206	/* 24985 */ "BNZ_V\0"
10207	/* 24991 */ "BMNZ_V\0"	10207	/* 24991 */ "BMNZ_V\0"
10208	/* 24998 */ "CRC32W\0"	10208	/* 24998 */ "CRC32W\0"
10209	/* 25005 */ "CRC32CW\0"	10209	/* 25005 */ "CRC32CW\0"
10210	/* 25013 */ "LW\0"	10210	/* 25013 */ "LW\0"
10211	/* 25016 */ "G_FPOW\0"	10211	/* 25016 */ "G_FPOW\0"
10212	/* 25023 */ "SW\0"	10212	/* 25023 */ "SW\0"
10213	/* 25026 */ "PseudoCVT_D32_W\0"	10213	/* 25026 */ "PseudoCVT_D32_W\0"
10214	/* 25042 */ "FLOG2_W\0"	10214	/* 25042 */ "FLOG2_W\0"
10215	/* 25050 */ "FEXP2_W\0"	10215	/* 25050 */ "FEXP2_W\0"
10216	/* 25058 */ "PseudoCVT_D64_W\0"	10216	/* 25058 */ "PseudoCVT_D64_W\0"
10217	/* 25074 */ "SRA_W\0"	10217	/* 25074 */ "SRA_W\0"
10218	/* 25080 */ "ADD_A_W\0"	10218	/* 25080 */ "ADD_A_W\0"
10219	/* 25088 */ "FMIN_A_W\0"	10219	/* 25088 */ "FMIN_A_W\0"
10220	/* 25097 */ "ADDS_A_W\0"	10220	/* 25097 */ "ADDS_A_W\0"
10221	/* 25106 */ "FMAX_A_W\0"	10221	/* 25106 */ "FMAX_A_W\0"
10222	/* 25115 */ "FSUB_W\0"	10222	/* 25115 */ "FSUB_W\0"
10223	/* 25122 */ "FMSUB_W\0"	10223	/* 25122 */ "FMSUB_W\0"
10224	/* 25130 */ "NLOC_W\0"	10224	/* 25130 */ "NLOC_W\0"
10225	/* 25137 */ "NLZC_W\0"	10225	/* 25137 */ "NLZC_W\0"
10226	/* 25144 */ "FADD_W\0"	10226	/* 25144 */ "FADD_W\0"
10227	/* 25151 */ "FMADD_W\0"	10227	/* 25151 */ "FMADD_W\0"
10228	/* 25159 */ "SLD_W\0"	10228	/* 25159 */ "SLD_W\0"
10229	/* 25165 */ "PCKOD_W\0"	10229	/* 25165 */ "PCKOD_W\0"
10230	/* 25173 */ "ILVOD_W\0"	10230	/* 25173 */ "ILVOD_W\0"
10231	/* 25181 */ "FCLE_W\0"	10231	/* 25181 */ "FCLE_W\0"
10232	/* 25188 */ "FSLE_W\0"	10232	/* 25188 */ "FSLE_W\0"
10233	/* 25195 */ "FCULE_W\0"	10233	/* 25195 */ "FCULE_W\0"
10234	/* 25203 */ "FSULE_W\0"	10234	/* 25203 */ "FSULE_W\0"
10235	/* 25211 */ "FCNE_W\0"	10235	/* 25211 */ "FCNE_W\0"
10236	/* 25218 */ "FSNE_W\0"	10236	/* 25218 */ "FSNE_W\0"
10237	/* 25225 */ "FCUNE_W\0"	10237	/* 25225 */ "FCUNE_W\0"
10238	/* 25233 */ "FSUNE_W\0"	10238	/* 25233 */ "FSUNE_W\0"
10239	/* 25241 */ "INSVE_W\0"	10239	/* 25241 */ "INSVE_W\0"
10240	/* 25249 */ "FCAF_W\0"	10240	/* 25249 */ "FCAF_W\0"
10241	/* 25256 */ "FSAF_W\0"	10241	/* 25256 */ "FSAF_W\0"
10242	/* 25263 */ "VSHF_W\0"	10242	/* 25263 */ "VSHF_W\0"
10243	/* 25270 */ "BNEG_W\0"	10243	/* 25270 */ "BNEG_W\0"
10244	/* 25277 */ "PRECR_SRA_PH_W\0"	10244	/* 25277 */ "PRECR_SRA_PH_W\0"
10245	/* 25292 */ "PRECRQ_PH_W\0"	10245	/* 25292 */ "PRECRQ_PH_W\0"
10246	/* 25304 */ "PRECR_SRA_R_PH_W\0"	10246	/* 25304 */ "PRECR_SRA_R_PH_W\0"
10247	/* 25321 */ "PRECRQ_RS_PH_W\0"	10247	/* 25321 */ "PRECRQ_RS_PH_W\0"
10248	/* 25336 */ "SUBQH_W\0"	10248	/* 25336 */ "SUBQH_W\0"
10249	/* 25344 */ "ADDQH_W\0"	10249	/* 25344 */ "ADDQH_W\0"
10250	/* 25352 */ "SRAI_W\0"	10250	/* 25352 */ "SRAI_W\0"
10251	/* 25359 */ "SLDI_W\0"	10251	/* 25359 */ "SLDI_W\0"
10252	/* 25366 */ "BNEGI_W\0"	10252	/* 25366 */ "BNEGI_W\0"
10253	/* 25374 */ "SLLI_W\0"	10253	/* 25374 */ "SLLI_W\0"
10254	/* 25381 */ "SRLI_W\0"	10254	/* 25381 */ "SRLI_W\0"
10255	/* 25388 */ "BINSLI_W\0"	10255	/* 25388 */ "BINSLI_W\0"
10256	/* 25397 */ "CEQI_W\0"	10256	/* 25397 */ "CEQI_W\0"
10257	/* 25404 */ "SRARI_W\0"	10257	/* 25404 */ "SRARI_W\0"
10258	/* 25412 */ "BCLRI_W\0"	10258	/* 25412 */ "BCLRI_W\0"
10259	/* 25420 */ "SRLRI_W\0"	10259	/* 25420 */ "SRLRI_W\0"
10260	/* 25428 */ "BINSRI_W\0"	10260	/* 25428 */ "BINSRI_W\0"
10261	/* 25437 */ "SPLATI_W\0"	10261	/* 25437 */ "SPLATI_W\0"
10262	/* 25446 */ "BSETI_W\0"	10262	/* 25446 */ "BSETI_W\0"
10263	/* 25454 */ "SUBVI_W\0"	10263	/* 25454 */ "SUBVI_W\0"
10264	/* 25462 */ "ADDVI_W\0"	10264	/* 25462 */ "ADDVI_W\0"
10265	/* 25470 */ "FILL_W\0"	10265	/* 25470 */ "FILL_W\0"
10266	/* 25477 */ "SLL_W\0"	10266	/* 25477 */ "SLL_W\0"
10267	/* 25483 */ "FEXUPL_W\0"	10267	/* 25483 */ "FEXUPL_W\0"
10268	/* 25492 */ "FFQL_W\0"	10268	/* 25492 */ "FFQL_W\0"
10269	/* 25499 */ "SRL_W\0"	10269	/* 25499 */ "SRL_W\0"
10270	/* 25505 */ "BINSL_W\0"	10270	/* 25505 */ "BINSL_W\0"
10271	/* 25513 */ "FMUL_W\0"	10271	/* 25513 */ "FMUL_W\0"
10272	/* 25520 */ "ILVL_W\0"	10272	/* 25520 */ "ILVL_W\0"
10273	/* 25527 */ "DPAQ_SA_L_W\0"	10273	/* 25527 */ "DPAQ_SA_L_W\0"
10274	/* 25539 */ "DPSQ_SA_L_W\0"	10274	/* 25539 */ "DPSQ_SA_L_W\0"
10275	/* 25551 */ "FMIN_W\0"	10275	/* 25551 */ "FMIN_W\0"
10276	/* 25558 */ "FCUN_W\0"	10276	/* 25558 */ "FCUN_W\0"
10277	/* 25565 */ "FSUN_W\0"	10277	/* 25565 */ "FSUN_W\0"
10278	/* 25572 */ "FEXDO_W\0"	10278	/* 25572 */ "FEXDO_W\0"
10279	/* 25580 */ "FRCP_W\0"	10279	/* 25580 */ "FRCP_W\0"
10280	/* 25587 */ "FCEQ_W\0"	10280	/* 25587 */ "FCEQ_W\0"
10281	/* 25594 */ "FSEQ_W\0"	10281	/* 25594 */ "FSEQ_W\0"
10282	/* 25601 */ "FCUEQ_W\0"	10282	/* 25601 */ "FCUEQ_W\0"
10283	/* 25609 */ "FSUEQ_W\0"	10283	/* 25609 */ "FSUEQ_W\0"
10284	/* 25617 */ "FTQ_W\0"	10284	/* 25617 */ "FTQ_W\0"
10285	/* 25623 */ "MSUB_Q_W\0"	10285	/* 25623 */ "MSUB_Q_W\0"
10286	/* 25632 */ "MADD_Q_W\0"	10286	/* 25632 */ "MADD_Q_W\0"
10287	/* 25641 */ "MUL_Q_W\0"	10287	/* 25641 */ "MUL_Q_W\0"
10288	/* 25649 */ "MSUBR_Q_W\0"	10288	/* 25649 */ "MSUBR_Q_W\0"
10289	/* 25659 */ "MADDR_Q_W\0"	10289	/* 25659 */ "MADDR_Q_W\0"
10290	/* 25669 */ "MULR_Q_W\0"	10290	/* 25669 */ "MULR_Q_W\0"
10291	/* 25678 */ "SRAR_W\0"	10291	/* 25678 */ "SRAR_W\0"
10292	/* 25685 */ "LDR_W\0"	10292	/* 25685 */ "LDR_W\0"
10293	/* 25691 */ "BCLR_W\0"	10293	/* 25691 */ "BCLR_W\0"
10294	/* 25698 */ "SRLR_W\0"	10294	/* 25698 */ "SRLR_W\0"
10295	/* 25705 */ "FCOR_W\0"	10295	/* 25705 */ "FCOR_W\0"
10296	/* 25712 */ "FSOR_W\0"	10296	/* 25712 */ "FSOR_W\0"
10297	/* 25719 */ "FEXUPR_W\0"	10297	/* 25719 */ "FEXUPR_W\0"
10298	/* 25728 */ "FFQR_W\0"	10298	/* 25728 */ "FFQR_W\0"
10299	/* 25735 */ "BINSR_W\0"	10299	/* 25735 */ "BINSR_W\0"
10300	/* 25743 */ "STR_W\0"	10300	/* 25743 */ "STR_W\0"
10301	/* 25749 */ "EXTR_W\0"	10301	/* 25749 */ "EXTR_W\0"
10302	/* 25756 */ "ILVR_W\0"	10302	/* 25756 */ "ILVR_W\0"
10303	/* 25763 */ "SHRA_R_W\0"	10303	/* 25763 */ "SHRA_R_W\0"
10304	/* 25772 */ "SUBQH_R_W\0"	10304	/* 25772 */ "SUBQH_R_W\0"
10305	/* 25782 */ "ADDQH_R_W\0"	10305	/* 25782 */ "ADDQH_R_W\0"
10306	/* 25792 */ "EXTR_R_W\0"	10306	/* 25792 */ "EXTR_R_W\0"
10307	/* 25801 */ "SHRAV_R_W\0"	10307	/* 25801 */ "SHRAV_R_W\0"
10308	/* 25811 */ "EXTRV_R_W\0"	10308	/* 25811 */ "EXTRV_R_W\0"
10309	/* 25821 */ "FABS_W\0"	10309	/* 25821 */ "FABS_W\0"
10310	/* 25828 */ "MULQ_RS_W\0"	10310	/* 25828 */ "MULQ_RS_W\0"
10311	/* 25838 */ "EXTR_RS_W\0"	10311	/* 25838 */ "EXTR_RS_W\0"
10312	/* 25848 */ "EXTRV_RS_W\0"	10312	/* 25848 */ "EXTRV_RS_W\0"
10313	/* 25859 */ "FCLASS_W\0"	10313	/* 25859 */ "FCLASS_W\0"
10314	/* 25868 */ "ASUB_S_W\0"	10314	/* 25868 */ "ASUB_S_W\0"
10315	/* 25877 */ "HSUB_S_W\0"	10315	/* 25877 */ "HSUB_S_W\0"
10316	/* 25886 */ "DPSUB_S_W\0"	10316	/* 25886 */ "DPSUB_S_W\0"
10317	/* 25896 */ "FTRUNC_S_W\0"	10317	/* 25896 */ "FTRUNC_S_W\0"
10318	/* 25907 */ "HADD_S_W\0"	10318	/* 25907 */ "HADD_S_W\0"
10319	/* 25916 */ "DPADD_S_W\0"	10319	/* 25916 */ "DPADD_S_W\0"
10320	/* 25926 */ "MOD_S_W\0"	10320	/* 25926 */ "MOD_S_W\0"
10321	/* 25934 */ "CLE_S_W\0"	10321	/* 25934 */ "CLE_S_W\0"
10322	/* 25942 */ "AVE_S_W\0"	10322	/* 25942 */ "AVE_S_W\0"
10323	/* 25950 */ "CLEI_S_W\0"	10323	/* 25950 */ "CLEI_S_W\0"
10324	/* 25959 */ "MINI_S_W\0"	10324	/* 25959 */ "MINI_S_W\0"
10325	/* 25968 */ "CLTI_S_W\0"	10325	/* 25968 */ "CLTI_S_W\0"
10326	/* 25977 */ "MAXI_S_W\0"	10326	/* 25977 */ "MAXI_S_W\0"
10327	/* 25986 */ "SHLL_S_W\0"	10327	/* 25986 */ "SHLL_S_W\0"
10328	/* 25995 */ "MIN_S_W\0"	10328	/* 25995 */ "MIN_S_W\0"
10329	/* 26003 */ "DOTP_S_W\0"	10329	/* 26003 */ "DOTP_S_W\0"
10330	/* 26012 */ "SUBQ_S_W\0"	10330	/* 26012 */ "SUBQ_S_W\0"
10331	/* 26021 */ "ADDQ_S_W\0"	10331	/* 26021 */ "ADDQ_S_W\0"
10332	/* 26030 */ "MULQ_S_W\0"	10332	/* 26030 */ "MULQ_S_W\0"
10333	/* 26039 */ "ABSQ_S_W\0"	10333	/* 26039 */ "ABSQ_S_W\0"
10334	/* 26048 */ "AVER_S_W\0"	10334	/* 26048 */ "AVER_S_W\0"
10335	/* 26057 */ "SUBS_S_W\0"	10335	/* 26057 */ "SUBS_S_W\0"
10336	/* 26066 */ "ADDS_S_W\0"	10336	/* 26066 */ "ADDS_S_W\0"
10337	/* 26075 */ "SAT_S_W\0"	10337	/* 26075 */ "SAT_S_W\0"
10338	/* 26083 */ "CLT_S_W\0"	10338	/* 26083 */ "CLT_S_W\0"
10339	/* 26091 */ "FFINT_S_W\0"	10339	/* 26091 */ "FFINT_S_W\0"
10340	/* 26101 */ "FTINT_S_W\0"	10340	/* 26101 */ "FTINT_S_W\0"
10341	/* 26111 */ "PseudoCVT_S_W\0"	10341	/* 26111 */ "PseudoCVT_S_W\0"
10342	/* 26125 */ "SUBSUU_S_W\0"	10342	/* 26125 */ "SUBSUU_S_W\0"
10343	/* 26136 */ "DIV_S_W\0"	10343	/* 26136 */ "DIV_S_W\0"
10344	/* 26144 */ "SHLLV_S_W\0"	10344	/* 26144 */ "SHLLV_S_W\0"
10345	/* 26154 */ "MAX_S_W\0"	10345	/* 26154 */ "MAX_S_W\0"
10346	/* 26162 */ "COPY_S_W\0"	10346	/* 26162 */ "COPY_S_W\0"
10347	/* 26171 */ "SPLAT_W\0"	10347	/* 26171 */ "SPLAT_W\0"
10348	/* 26179 */ "BSET_W\0"	10348	/* 26179 */ "BSET_W\0"
10349	/* 26186 */ "FCLT_W\0"	10349	/* 26186 */ "FCLT_W\0"
10350	/* 26193 */ "FSLT_W\0"	10350	/* 26193 */ "FSLT_W\0"
10351	/* 26200 */ "FCULT_W\0"	10351	/* 26200 */ "FCULT_W\0"
10352	/* 26208 */ "FSULT_W\0"	10352	/* 26208 */ "FSULT_W\0"
10353	/* 26216 */ "PCNT_W\0"	10353	/* 26216 */ "PCNT_W\0"
10354	/* 26223 */ "FRINT_W\0"	10354	/* 26223 */ "FRINT_W\0"
10355	/* 26231 */ "INSERT_W\0"	10355	/* 26231 */ "INSERT_W\0"
10356	/* 26240 */ "FSQRT_W\0"	10356	/* 26240 */ "FSQRT_W\0"
10357	/* 26248 */ "FRSQRT_W\0"	10357	/* 26248 */ "FRSQRT_W\0"
10358	/* 26257 */ "ST_W\0"	10358	/* 26257 */ "ST_W\0"
10359	/* 26262 */ "ASUB_U_W\0"	10359	/* 26262 */ "ASUB_U_W\0"
10360	/* 26271 */ "HSUB_U_W\0"	10360	/* 26271 */ "HSUB_U_W\0"
10361	/* 26280 */ "DPSUB_U_W\0"	10361	/* 26280 */ "DPSUB_U_W\0"
10362	/* 26290 */ "FTRUNC_U_W\0"	10362	/* 26290 */ "FTRUNC_U_W\0"
10363	/* 26301 */ "HADD_U_W\0"	10363	/* 26301 */ "HADD_U_W\0"
10364	/* 26310 */ "DPADD_U_W\0"	10364	/* 26310 */ "DPADD_U_W\0"
10365	/* 26320 */ "MOD_U_W\0"	10365	/* 26320 */ "MOD_U_W\0"
10366	/* 26328 */ "CLE_U_W\0"	10366	/* 26328 */ "CLE_U_W\0"
10367	/* 26336 */ "AVE_U_W\0"	10367	/* 26336 */ "AVE_U_W\0"
10368	/* 26344 */ "CLEI_U_W\0"	10368	/* 26344 */ "CLEI_U_W\0"
10369	/* 26353 */ "MINI_U_W\0"	10369	/* 26353 */ "MINI_U_W\0"
10370	/* 26362 */ "CLTI_U_W\0"	10370	/* 26362 */ "CLTI_U_W\0"
10371	/* 26371 */ "MAXI_U_W\0"	10371	/* 26371 */ "MAXI_U_W\0"
10372	/* 26380 */ "MIN_U_W\0"	10372	/* 26380 */ "MIN_U_W\0"
10373	/* 26388 */ "DOTP_U_W\0"	10373	/* 26388 */ "DOTP_U_W\0"
10374	/* 26397 */ "AVER_U_W\0"	10374	/* 26397 */ "AVER_U_W\0"
10375	/* 26406 */ "SUBS_U_W\0"	10375	/* 26406 */ "SUBS_U_W\0"
10376	/* 26415 */ "ADDS_U_W\0"	10376	/* 26415 */ "ADDS_U_W\0"
10377	/* 26424 */ "SUBSUS_U_W\0"	10377	/* 26424 */ "SUBSUS_U_W\0"
10378	/* 26435 */ "SAT_U_W\0"	10378	/* 26435 */ "SAT_U_W\0"
10379	/* 26443 */ "CLT_U_W\0"	10379	/* 26443 */ "CLT_U_W\0"
10380	/* 26451 */ "FFINT_U_W\0"	10380	/* 26451 */ "FFINT_U_W\0"
10381	/* 26461 */ "FTINT_U_W\0"	10381	/* 26461 */ "FTINT_U_W\0"
10382	/* 26471 */ "DIV_U_W\0"	10382	/* 26471 */ "DIV_U_W\0"
10383	/* 26479 */ "MAX_U_W\0"	10383	/* 26479 */ "MAX_U_W\0"
10384	/* 26487 */ "COPY_U_W\0"	10384	/* 26487 */ "COPY_U_W\0"
10385	/* 26496 */ "MSUBV_W\0"	10385	/* 26496 */ "MSUBV_W\0"
10386	/* 26504 */ "MADDV_W\0"	10386	/* 26504 */ "MADDV_W\0"
10387	/* 26512 */ "PCKEV_W\0"	10387	/* 26512 */ "PCKEV_W\0"
10388	/* 26520 */ "ILVEV_W\0"	10388	/* 26520 */ "ILVEV_W\0"
10389	/* 26528 */ "FDIV_W\0"	10389	/* 26528 */ "FDIV_W\0"
10390	/* 26535 */ "MULV_W\0"	10390	/* 26535 */ "MULV_W\0"
10391	/* 26542 */ "EXTRV_W\0"	10391	/* 26542 */ "EXTRV_W\0"
10392	/* 26550 */ "FMAX_W\0"	10392	/* 26550 */ "FMAX_W\0"
10393	/* 26557 */ "BZ_W\0"	10393	/* 26557 */ "BZ_W\0"
10394	/* 26562 */ "BNZ_W\0"	10394	/* 26562 */ "BNZ_W\0"
10395	/* 26568 */ "G_VECREDUCE_FMAX\0"	10395	/* 26568 */ "G_VECREDUCE_FMAX\0"
10396	/* 26585 */ "G_ATOMICRMW_FMAX\0"	10396	/* 26585 */ "G_ATOMICRMW_FMAX\0"
10397	/* 26602 */ "G_VECREDUCE_SMAX\0"	10397	/* 26602 */ "G_VECREDUCE_SMAX\0"
10398	/* 26619 */ "G_SMAX\0"	10398	/* 26619 */ "G_SMAX\0"
10399	/* 26626 */ "G_VECREDUCE_UMAX\0"	10399	/* 26626 */ "G_VECREDUCE_UMAX\0"
10400	/* 26643 */ "G_UMAX\0"	10400	/* 26643 */ "G_UMAX\0"
10401	/* 26650 */ "G_ATOMICRMW_UMAX\0"	10401	/* 26650 */ "G_ATOMICRMW_UMAX\0"
10402	/* 26667 */ "G_ATOMICRMW_MAX\0"	10402	/* 26667 */ "G_ATOMICRMW_MAX\0"
10403	/* 26683 */ "MFTACX\0"	10403	/* 26683 */ "MFTACX\0"
10404	/* 26690 */ "MTTACX\0"	10404	/* 26690 */ "MTTACX\0"
10405	/* 26697 */ "G_FRAME_INDEX\0"	10405	/* 26697 */ "G_FRAME_INDEX\0"
10406	/* 26711 */ "G_SBFX\0"	10406	/* 26711 */ "G_SBFX\0"
10407	/* 26718 */ "G_UBFX\0"	10407	/* 26718 */ "G_UBFX\0"
10408	/* 26725 */ "LHX\0"	10408	/* 26725 */ "LHX\0"
10409	/* 26729 */ "G_SMULFIX\0"	10409	/* 26729 */ "G_SMULFIX\0"
10410	/* 26739 */ "G_UMULFIX\0"	10410	/* 26739 */ "G_UMULFIX\0"
10411	/* 26749 */ "G_SDIVFIX\0"	10411	/* 26749 */ "G_SDIVFIX\0"
10412	/* 26759 */ "G_UDIVFIX\0"	10412	/* 26759 */ "G_UDIVFIX\0"
10413	/* 26769 */ "JALX\0"	10413	/* 26769 */ "JALX\0"
10414	/* 26774 */ "LBUX\0"	10414	/* 26774 */ "LBUX\0"
10415	/* 26779 */ "LWX\0"	10415	/* 26779 */ "LWX\0"
10416	/* 26783 */ "G_MEMCPY\0"	10416	/* 26783 */ "G_MEMCPY\0"
10417	/* 26792 */ "COPY\0"	10417	/* 26792 */ "COPY\0"
10418	/* 26797 */ "CONSTPOOL_ENTRY\0"	10418	/* 26797 */ "CONSTPOOL_ENTRY\0"
10419	/* 26813 */ "BGEZ\0"	10419	/* 26813 */ "BGEZ\0"
10420	/* 26818 */ "BLEZ\0"	10420	/* 26818 */ "BLEZ\0"
10421	/* 26823 */ "BC1NEZ\0"	10421	/* 26823 */ "BC1NEZ\0"
10422	/* 26830 */ "BC2NEZ\0"	10422	/* 26830 */ "BC2NEZ\0"
10423	/* 26837 */ "SELNEZ\0"	10423	/* 26837 */ "SELNEZ\0"
10424	/* 26844 */ "DCLZ\0"	10424	/* 26844 */ "DCLZ\0"
10425	/* 26849 */ "G_CTLZ\0"	10425	/* 26849 */ "G_CTLZ\0"
10426	/* 26856 */ "BC1EQZ\0"	10426	/* 26856 */ "BC1EQZ\0"
10427	/* 26863 */ "BC2EQZ\0"	10427	/* 26863 */ "BC2EQZ\0"
10428	/* 26870 */ "SELEQZ\0"	10428	/* 26870 */ "SELEQZ\0"
10429	/* 26877 */ "BGTZ\0"	10429	/* 26877 */ "BGTZ\0"
10430	/* 26882 */ "BLTZ\0"	10430	/* 26882 */ "BLTZ\0"
10431	/* 26887 */ "G_CTTZ\0"	10431	/* 26887 */ "G_CTTZ\0"
10432	/* 26894 */ "SelBneZ\0"	10432	/* 26894 */ "SelBneZ\0"
10433	/* 26902 */ "SelBeqZ\0"	10433	/* 26902 */ "SelBeqZ\0"
10434	/* 26910 */ "JalOneReg\0"	10434	/* 26910 */ "JalOneReg\0"
10435	/* 26920 */ "JalTwoReg\0"	10435	/* 26920 */ "JalTwoReg\0"
10436	/* 26930 */ "PseudoIndirectHazardBranch\0"	10436	/* 26930 */ "PseudoIndirectHazardBranch\0"
10437	/* 26957 */ "PseudoIndirectBranch\0"	10437	/* 26957 */ "PseudoIndirectBranch\0"
10438	/* 26978 */ "Ulh\0"	10438	/* 26978 */ "Ulh\0"
10439	/* 26982 */ "Ush\0"	10439	/* 26982 */ "Ush\0"
10440	/* 26986 */ "DADDi\0"	10440	/* 26986 */ "DADDi\0"
10441	/* 26992 */ "ANDi\0"	10441	/* 26992 */ "ANDi\0"
10442	/* 26997 */ "SNEi\0"	10442	/* 26997 */ "SNEi\0"
10443	/* 27002 */ "SEQi\0"	10443	/* 27002 */ "SEQi\0"
10444	/* 27007 */ "XORi\0"	10444	/* 27007 */ "XORi\0"
10445	/* 27012 */ "SLTi\0"	10445	/* 27012 */ "SLTi\0"
10446	/* 27017 */ "LONG_BRANCH_LUi\0"	10446	/* 27017 */ "LONG_BRANCH_LUi\0"
10447	/* 27033 */ "SelTBtneZCmpi\0"	10447	/* 27033 */ "SelTBtneZCmpi\0"
10448	/* 27047 */ "SelTBteqZCmpi\0"	10448	/* 27047 */ "SelTBteqZCmpi\0"
10449	/* 27061 */ "SelTBtneZSlti\0"	10449	/* 27061 */ "SelTBtneZSlti\0"
10450	/* 27075 */ "SelTBteqZSlti\0"	10450	/* 27075 */ "SelTBteqZSlti\0"
10451	/* 27089 */ "SGEImm\0"	10451	/* 27089 */ "SGEImm\0"
10452	/* 27096 */ "SLEImm\0"	10452	/* 27096 */ "SLEImm\0"
10453	/* 27103 */ "DROLImm\0"	10453	/* 27103 */ "DROLImm\0"
10454	/* 27111 */ "NORImm\0"	10454	/* 27111 */ "NORImm\0"
10455	/* 27118 */ "DRORImm\0"	10455	/* 27118 */ "DRORImm\0"
10456	/* 27126 */ "SGTImm\0"	10456	/* 27126 */ "SGTImm\0"
10457	/* 27133 */ "SGEUImm\0"	10457	/* 27133 */ "SGEUImm\0"
10458	/* 27141 */ "SLEUImm\0"	10458	/* 27141 */ "SLEUImm\0"
10459	/* 27149 */ "SGTUImm\0"	10459	/* 27149 */ "SGTUImm\0"
10460	/* 27157 */ "BneImm\0"	10460	/* 27157 */ "BneImm\0"
10461	/* 27164 */ "BeqImm\0"	10461	/* 27164 */ "BeqImm\0"
10462	/* 27171 */ "PseudoReturn\0"	10462	/* 27171 */ "PseudoReturn\0"
10463	/* 27184 */ "JALRHB64Pseudo\0"	10463	/* 27184 */ "JALRHB64Pseudo\0"
10464	/* 27199 */ "JALR64Pseudo\0"	10464	/* 27199 */ "JALR64Pseudo\0"
10465	/* 27212 */ "JALRHBPseudo\0"	10465	/* 27212 */ "JALRHBPseudo\0"
10466	/* 27225 */ "JALRPseudo\0"	10466	/* 27225 */ "JALRPseudo\0"
10467	/* 27236 */ "B_MMR6_Pseudo\0"	10467	/* 27236 */ "B_MMR6_Pseudo\0"
10468	/* 27250 */ "B_MM_Pseudo\0"	10468	/* 27250 */ "B_MM_Pseudo\0"
10469	/* 27262 */ "SDIV_MM_Pseudo\0"	10469	/* 27262 */ "SDIV_MM_Pseudo\0"
10470	/* 27277 */ "UDIV_MM_Pseudo\0"	10470	/* 27277 */ "UDIV_MM_Pseudo\0"
10471	/* 27292 */ "LDMacro\0"	10471	/* 27292 */ "LDMacro\0"
10472	/* 27300 */ "SDMacro\0"	10472	/* 27300 */ "SDMacro\0"
10473	/* 27308 */ "SNEMacro\0"	10473	/* 27308 */ "SNEMacro\0"
10474	/* 27317 */ "SNEIMacro\0"	10474	/* 27317 */ "SNEIMacro\0"
10475	/* 27327 */ "SEQIMacro\0"	10475	/* 27327 */ "SEQIMacro\0"
10476	/* 27337 */ "DSRemIMacro\0"	10476	/* 27337 */ "DSRemIMacro\0"
10477	/* 27349 */ "DURemIMacro\0"	10477	/* 27349 */ "DURemIMacro\0"
10478	/* 27361 */ "DSDivIMacro\0"	10478	/* 27361 */ "DSDivIMacro\0"
10479	/* 27373 */ "DUDivIMacro\0"	10479	/* 27373 */ "DUDivIMacro\0"
10480	/* 27385 */ "DMULMacro\0"	10480	/* 27385 */ "DMULMacro\0"
10481	/* 27395 */ "DMULOMacro\0"	10481	/* 27395 */ "DMULOMacro\0"
10482	/* 27406 */ "SEQMacro\0"	10482	/* 27406 */ "SEQMacro\0"
10483	/* 27415 */ "ABSMacro\0"	10483	/* 27415 */ "ABSMacro\0"
10484	/* 27424 */ "DMULOUMacro\0"	10484	/* 27424 */ "DMULOUMacro\0"
10485	/* 27436 */ "DSRemMacro\0"	10485	/* 27436 */ "DSRemMacro\0"
10486	/* 27447 */ "DURemMacro\0"	10486	/* 27447 */ "DURemMacro\0"
10487	/* 27458 */ "BGEImmMacro\0"	10487	/* 27458 */ "BGEImmMacro\0"
10488	/* 27470 */ "BLEImmMacro\0"	10488	/* 27470 */ "BLEImmMacro\0"
10489	/* 27482 */ "BGELImmMacro\0"	10489	/* 27482 */ "BGELImmMacro\0"
10490	/* 27495 */ "BLELImmMacro\0"	10490	/* 27495 */ "BLELImmMacro\0"
10491	/* 27508 */ "BNELImmMacro\0"	10491	/* 27508 */ "BNELImmMacro\0"
10492	/* 27521 */ "BEQLImmMacro\0"	10492	/* 27521 */ "BEQLImmMacro\0"
10493	/* 27534 */ "BGTLImmMacro\0"	10493	/* 27534 */ "BGTLImmMacro\0"
10494	/* 27547 */ "BLTLImmMacro\0"	10494	/* 27547 */ "BLTLImmMacro\0"
10495	/* 27560 */ "BGEULImmMacro\0"	10495	/* 27560 */ "BGEULImmMacro\0"
10496	/* 27574 */ "BLEULImmMacro\0"	10496	/* 27574 */ "BLEULImmMacro\0"
10497	/* 27588 */ "DMULImmMacro\0"	10497	/* 27588 */ "DMULImmMacro\0"
10498	/* 27601 */ "BGTULImmMacro\0"	10498	/* 27601 */ "BGTULImmMacro\0"
10499	/* 27615 */ "BLTULImmMacro\0"	10499	/* 27615 */ "BLTULImmMacro\0"
10500	/* 27629 */ "BGTImmMacro\0"	10500	/* 27629 */ "BGTImmMacro\0"
10501	/* 27641 */ "BLTImmMacro\0"	10501	/* 27641 */ "BLTImmMacro\0"
10502	/* 27653 */ "BGEUImmMacro\0"	10502	/* 27653 */ "BGEUImmMacro\0"
10503	/* 27666 */ "BLEUImmMacro\0"	10503	/* 27666 */ "BLEUImmMacro\0"
10504	/* 27679 */ "BGTUImmMacro\0"	10504	/* 27679 */ "BGTUImmMacro\0"
10505	/* 27692 */ "BLTUImmMacro\0"	10505	/* 27692 */ "BLTUImmMacro\0"
10506	/* 27705 */ "DSDivMacro\0"	10506	/* 27705 */ "DSDivMacro\0"
10507	/* 27716 */ "DUDivMacro\0"	10507	/* 27716 */ "DUDivMacro\0"
10508	/* 27727 */ "LONG_BRANCH_LUi2Op\0"	10508	/* 27727 */ "LONG_BRANCH_LUi2Op\0"
10509	/* 27746 */ "LONG_BRANCH_DADDiu2Op\0"	10509	/* 27746 */ "LONG_BRANCH_DADDiu2Op\0"
10510	/* 27768 */ "LONG_BRANCH_ADDiu2Op\0"	10510	/* 27768 */ "LONG_BRANCH_ADDiu2Op\0"
10511	/* 27789 */ "SelTBtneZCmp\0"	10511	/* 27789 */ "SelTBtneZCmp\0"
10512	/* 27802 */ "SelTBteqZCmp\0"	10512	/* 27802 */ "SelTBteqZCmp\0"
10513	/* 27815 */ "SaaAddr\0"	10513	/* 27815 */ "SaaAddr\0"
10514	/* 27823 */ "SaadAddr\0"	10514	/* 27823 */ "SaadAddr\0"
10515	/* 27832 */ "ERet\0"	10515	/* 27832 */ "ERet\0"
10516	/* 27837 */ "SelTBtneZSlt\0"	10516	/* 27837 */ "SelTBtneZSlt\0"
10517	/* 27850 */ "SelTBteqZSlt\0"	10517	/* 27850 */ "SelTBteqZSlt\0"
10518	/* 27863 */ "LBu\0"	10518	/* 27863 */ "LBu\0"
10519	/* 27867 */ "DSUBu\0"	10519	/* 27867 */ "DSUBu\0"
10520	/* 27873 */ "BADDu\0"	10520	/* 27873 */ "BADDu\0"
10521	/* 27879 */ "DADDu\0"	10521	/* 27879 */ "DADDu\0"
10522	/* 27885 */ "LHu\0"	10522	/* 27885 */ "LHu\0"
10523	/* 27889 */ "SLTu\0"	10523	/* 27889 */ "SLTu\0"
10524	/* 27894 */ "PseudoDMULTu\0"	10524	/* 27894 */ "PseudoDMULTu\0"
10525	/* 27907 */ "PseudoMULTu\0"	10525	/* 27907 */ "PseudoMULTu\0"
10526	/* 27919 */ "LWu\0"	10526	/* 27919 */ "LWu\0"
10527	/* 27923 */ "Ulhu\0"	10527	/* 27923 */ "Ulhu\0"
10528	/* 27928 */ "LONG_BRANCH_DADDiu\0"	10528	/* 27928 */ "LONG_BRANCH_DADDiu\0"
10529	/* 27947 */ "LEA_ADDiu\0"	10529	/* 27947 */ "LEA_ADDiu\0"
10530	/* 27957 */ "LONG_BRANCH_ADDiu\0"	10530	/* 27957 */ "LONG_BRANCH_ADDiu\0"
10531	/* 27975 */ "SLTiu\0"	10531	/* 27975 */ "SLTiu\0"
10532	/* 27981 */ "SelTBtneZSltiu\0"	10532	/* 27981 */ "SelTBtneZSltiu\0"
10533	/* 27996 */ "SelTBteqZSltiu\0"	10533	/* 27996 */ "SelTBteqZSltiu\0"
10534	/* 28011 */ "SelTBtneZSltu\0"	10534	/* 28011 */ "SelTBtneZSltu\0"
10535	/* 28025 */ "SelTBteqZSltu\0"	10535	/* 28025 */ "SelTBteqZSltu\0"
10536	/* 28039 */ "Ulw\0"	10536	/* 28039 */ "Ulw\0"
10537	/* 28043 */ "Usw\0"	10537	/* 28043 */ "Usw\0"
10538	};	10538	};
10539	#ifdef __GNUC__	10539	#ifdef __GNUC__
10540	#pragma GCC diagnostic pop	10540	#pragma GCC diagnostic pop
10541	#endif	10541	#endif
10542		10542
10543	extern const unsigned MipsInstrNameIndices[] = {	10543	extern const unsigned MipsInstrNameIndices[] = {
10544	15358U, 20903U, 22723U, 21178U, 15706U, 15687U, 15715U, 15967U,	10544	15358U, 20903U, 22723U, 21178U, 15706U, 15687U, 15715U, 15967U,
10545	13725U, 13740U, 13605U, 13779U, 23301U, 13484U, 24572U, 13623U,	10545	13725U, 13740U, 13605U, 13779U, 23301U, 13484U, 24572U, 13623U,
10546	15354U, 15696U, 13233U, 26792U, 13355U, 24476U, 11679U, 13180U,	10546	15354U, 15696U, 13233U, 26792U, 13355U, 24476U, 11679U, 13180U,
10547	13221U, 22140U, 15939U, 24405U, 11769U, 22560U, 13842U, 24394U,	10547	13221U, 22140U, 15939U, 24405U, 11769U, 22560U, 13842U, 24394U,
10548	13408U, 22310U, 22297U, 22792U, 24224U, 24256U, 15871U, 15918U,	10548	13408U, 22310U, 22297U, 22792U, 24224U, 24256U, 15871U, 15918U,
10549	15891U, 15747U, 22757U, 24613U, 24643U, 21003U, 11562U, 10295U,	10549	15891U, 15747U, 22757U, 24613U, 24643U, 21003U, 11562U, 10295U,
10550	16123U, 24834U, 24864U, 16224U, 16231U, 16238U, 16248U, 11642U,	10550	16123U, 24834U, 24864U, 16224U, 16231U, 16238U, 16248U, 11642U,
10551	23093U, 23056U, 13603U, 15356U, 26697U, 13494U, 15977U, 24186U,	10551	23093U, 23056U, 13603U, 15356U, 26697U, 13494U, 15977U, 24186U,
10552	23235U, 24513U, 23252U, 23008U, 11181U, 23284U, 24416U, 23179U,	10552	23235U, 24513U, 23252U, 23008U, 11181U, 23284U, 24416U, 23179U,
10553	24545U, 13527U, 22768U, 11738U, 11155U, 11720U, 24435U, 20967U,	10553	24545U, 13527U, 22768U, 11738U, 11155U, 11720U, 24435U, 20967U,
10554	22817U, 11435U, 11379U, 11409U, 11420U, 11360U, 11390U, 13447U,	10554	22817U, 11435U, 11379U, 11409U, 11420U, 11360U, 11390U, 13447U,
10555	13431U, 23331U, 13793U, 13810U, 11578U, 10301U, 11648U, 11609U,	10555	13431U, 23331U, 13793U, 13810U, 11578U, 10301U, 11648U, 11609U,
10556	23098U, 23062U, 26667U, 21129U, 26650U, 21112U, 11518U, 10267U,	10556	23098U, 23062U, 26667U, 21129U, 26650U, 21112U, 11518U, 10267U,
10557	26585U, 21047U, 22176U, 22154U, 13213U, 11692U, 24205U, 24491U,	10557	26585U, 21047U, 22176U, 22154U, 13213U, 11692U, 24205U, 24491U,
10558	11067U, 23361U, 24627U, 11173U, 24383U, 24371U, 24466U, 13834U,	10558	11067U, 23361U, 24627U, 11173U, 24383U, 24371U, 24466U, 13834U,
10559	24606U, 13766U, 24636U, 15832U, 22975U, 22961U, 15825U, 22968U,	10559	24606U, 13766U, 24636U, 15832U, 22975U, 22961U, 15825U, 22968U,
10560	23172U, 16024U, 22271U, 22264U, 24196U, 21235U, 13258U, 21219U,	10560	23172U, 16024U, 22271U, 22264U, 24196U, 21235U, 13258U, 21219U,
10561	13205U, 21227U, 13250U, 21211U, 13197U, 22124U, 22116U, 13896U,	10561	13205U, 21227U, 13250U, 21211U, 13197U, 22124U, 22116U, 13896U,
10562	13888U, 24104U, 24094U, 24084U, 24074U, 24124U, 24114U, 26729U,	10562	13888U, 24104U, 24094U, 24084U, 24074U, 24124U, 24114U, 26729U,
10563	26739U, 24134U, 24147U, 26749U, 26759U, 24160U, 24173U, 11476U,	10563	26739U, 24134U, 24147U, 26749U, 26759U, 24160U, 24173U, 11476U,
10564	10246U, 16065U, 8500U, 11353U, 24801U, 16203U, 25016U, 15436U,	10564	10246U, 16065U, 8500U, 11353U, 24801U, 16203U, 25016U, 15436U,
10565	22612U, 1205U, 13827U, 1187U, 0U, 22587U, 22619U, 13654U,	10565	22612U, 1205U, 13827U, 1187U, 0U, 22587U, 22619U, 13654U,
10566	24598U, 11145U, 15384U, 15408U, 22233U, 22242U, 23222U, 21018U,	10566	24598U, 11145U, 15384U, 15408U, 22233U, 22242U, 23222U, 21018U,
10567	23318U, 13536U, 20947U, 20957U, 13266U, 13281U, 20925U, 20936U,	10567	23318U, 13536U, 20947U, 20957U, 13266U, 13281U, 20925U, 20936U,
10568	11568U, 15581U, 21081U, 26619U, 21105U, 26643U, 23229U, 11711U,	10568	11568U, 15581U, 21081U, 26619U, 21105U, 26643U, 23229U, 11711U,
10569	11701U, 22711U, 24280U, 24312U, 24291U, 23023U, 26887U, 13585U,	10569	11701U, 22711U, 24280U, 24312U, 24291U, 23023U, 26887U, 13585U,
10570	26849U, 13567U, 22289U, 22198U, 13465U, 15838U, 23277U, 21145U,	10570	26849U, 13567U, 22289U, 22198U, 13465U, 15838U, 23277U, 21145U,
10571	24522U, 22994U, 24427U, 24453U, 24555U, 22736U, 13342U, 11207U,	10571	24522U, 22994U, 24427U, 24453U, 24555U, 22736U, 13342U, 11207U,
10572	11504U, 10253U, 16093U, 24808U, 16210U, 8506U, 24530U, 22596U,	10572	11504U, 10253U, 16093U, 24808U, 16210U, 8506U, 24530U, 22596U,
10573	22836U, 22852U, 26783U, 13384U, 13509U, 24238U, 22132U, 11483U,	10573	22836U, 22852U, 26783U, 13384U, 13509U, 24238U, 22132U, 11483U,
10574	16072U, 11459U, 16048U, 26568U, 21030U, 11546U, 16107U, 11626U,	10574	16072U, 11459U, 16048U, 26568U, 21030U, 11546U, 16107U, 11626U,
10575	23078U, 23040U, 26602U, 21064U, 26626U, 21088U, 26711U, 26718U,	10575	23078U, 23040U, 26602U, 21064U, 26626U, 21088U, 26711U, 26718U,
10576	27415U, 21194U, 22545U, 21579U, 21663U, 21879U, 4064U, 9386U,	10576	27415U, 21194U, 22545U, 21579U, 21663U, 21879U, 4064U, 9386U,
10577	884U, 8742U, 3089U, 9064U, 8370U, 9701U, 3946U, 9226U,	10577	884U, 8742U, 3089U, 9064U, 8370U, 9701U, 3946U, 9226U,
10578	766U, 8582U, 2919U, 8904U, 8258U, 9547U, 3987U, 9281U,	10578	766U, 8582U, 2919U, 8904U, 8258U, 9547U, 3987U, 9281U,
10579	807U, 8637U, 2960U, 8959U, 8297U, 9600U, 4144U, 9494U,	10579	807U, 8637U, 2960U, 8959U, 8297U, 9600U, 4144U, 9494U,
10580	964U, 8850U, 3235U, 9172U, 8446U, 9805U, 4028U, 9336U,	10580	964U, 8850U, 3235U, 9172U, 8446U, 9805U, 4028U, 9336U,
10581	848U, 8692U, 3053U, 9014U, 8336U, 9653U, 3966U, 9253U,	10581	848U, 8692U, 3053U, 9014U, 8336U, 9653U, 3966U, 9253U,
10582	786U, 8609U, 2939U, 8931U, 8277U, 9573U, 4104U, 9440U,	10582	786U, 8609U, 2939U, 8931U, 8277U, 9573U, 4104U, 9440U,
10583	924U, 8796U, 3129U, 9118U, 8408U, 9753U, 3926U, 9199U,	10583	924U, 8796U, 3129U, 9118U, 8408U, 9753U, 3926U, 9199U,
10584	746U, 8555U, 2899U, 8877U, 8239U, 9521U, 4123U, 9466U,	10584	746U, 8555U, 2899U, 8877U, 8239U, 9521U, 4123U, 9466U,
10585	943U, 8822U, 3214U, 9144U, 8426U, 9778U, 4007U, 9308U,	10585	943U, 8822U, 3214U, 9144U, 8426U, 9778U, 4007U, 9308U,
10586	827U, 8664U, 3032U, 8986U, 8316U, 9626U, 4084U, 9413U,	10586	827U, 8664U, 3032U, 8986U, 8316U, 9626U, 4084U, 9413U,
10587	904U, 8769U, 3109U, 9091U, 8389U, 9727U, 4048U, 9363U,	10587	904U, 8769U, 3109U, 9091U, 8389U, 9727U, 4048U, 9363U,
10588	868U, 8719U, 3073U, 9041U, 8355U, 9679U, 9861U, 22716U,	10588	868U, 8719U, 3073U, 9041U, 8355U, 9679U, 9861U, 22716U,
10589	19481U, 27521U, 13309U, 27458U, 15732U, 27482U, 24687U, 27653U,	10589	19481U, 27521U, 13309U, 27458U, 15732U, 27482U, 24687U, 27653U,
10590	16031U, 27560U, 24247U, 27629U, 16014U, 27534U, 24756U, 27679U,	10590	16031U, 27560U, 24247U, 27629U, 16014U, 27534U, 24756U, 27679U,
10591	16129U, 27601U, 13351U, 27470U, 15737U, 27495U, 24702U, 27666U,	10591	16129U, 27601U, 13351U, 27470U, 15737U, 27495U, 24702U, 27666U,
10592	16037U, 27574U, 24287U, 27641U, 16019U, 27547U, 24761U, 27692U,	10592	16037U, 27574U, 24287U, 27641U, 16019U, 27547U, 24761U, 27692U,
10593	16135U, 27615U, 27508U, 21277U, 21565U, 21458U, 21758U, 21649U,	10593	16135U, 27615U, 27508U, 21277U, 21565U, 21458U, 21758U, 21649U,
10594	21865U, 17673U, 27236U, 27250U, 27164U, 27157U, 4668U, 4215U,	10594	21865U, 17673U, 27236U, 27250U, 27164U, 27157U, 4668U, 4215U,
10595	4696U, 4245U, 4726U, 4757U, 4654U, 4200U, 4682U, 4230U,	10595	4696U, 4245U, 4726U, 4757U, 4654U, 4200U, 4682U, 4230U,
10596	4710U, 4742U, 2777U, 3547U, 122U, 26797U, 21505U, 21805U,	10596	4710U, 4742U, 2777U, 3547U, 122U, 26797U, 21505U, 21805U,
10597	140U, 1144U, 27588U, 27385U, 27395U, 27424U, 15993U, 27103U,	10597	140U, 1144U, 27588U, 27385U, 27395U, 27424U, 15993U, 27103U,
10598	23003U, 27118U, 27361U, 27705U, 27337U, 27436U, 27373U, 27716U,	10598	23003U, 27118U, 27361U, 27705U, 27337U, 27436U, 27373U, 27716U,
10599	27349U, 27447U, 27832U, 2790U, 3563U, 12472U, 25821U, 21243U,	10599	27349U, 27447U, 27832U, 2790U, 3563U, 12472U, 25821U, 21243U,
10600	21260U, 21473U, 21773U, 4815U, 21293U, 21949U, 21340U, 21992U,	10600	21260U, 21473U, 21773U, 4815U, 21293U, 21949U, 21340U, 21992U,
10601	21488U, 21316U, 21970U, 21788U, 21386U, 22034U, 21363U, 22013U,	10601	21488U, 21316U, 21970U, 21788U, 21386U, 22034U, 21363U, 22013U,
10602	21410U, 22056U, 27199U, 27184U, 27212U, 27225U, 6952U, 26910U,	10602	21410U, 22056U, 27199U, 27184U, 27212U, 27225U, 6952U, 26910U,
10603	26920U, 27292U, 12401U, 25685U, 3912U, 8214U, 2044U, 22322U,	10603	26920U, 27292U, 12401U, 25685U, 3912U, 8214U, 2044U, 22322U,
10604	22407U, 27957U, 27768U, 27928U, 27746U, 27017U, 27727U, 3593U,	10604	22407U, 27957U, 27768U, 27928U, 27746U, 27017U, 27727U, 3593U,
10605	19025U, 1112U, 3803U, 1079U, 3615U, 1102U, 3793U, 22875U,	10605	19025U, 1112U, 3803U, 1079U, 3615U, 1102U, 3793U, 22875U,
10606	1059U, 23127U, 22892U, 23144U, 1142U, 26683U, 43U, 128U,	10606	1059U, 23127U, 22892U, 23144U, 1142U, 26683U, 43U, 128U,
10607	22363U, 23113U, 103U, 15362U, 22099U, 1126U, 3832U, 21520U,	10607	22363U, 23113U, 103U, 15362U, 22099U, 1126U, 3832U, 21520U,
10608	21820U, 21543U, 21843U, 26690U, 55U, 146U, 22370U, 23120U,	10608	21820U, 21543U, 21843U, 26690U, 55U, 146U, 22370U, 23120U,
10609	110U, 15373U, 22110U, 27589U, 27396U, 27425U, 5075U, 5208U,	10609	110U, 15373U, 22110U, 27589U, 27396U, 27425U, 5075U, 5208U,
10610	5107U, 5260U, 22280U, 27111U, 3726U, 21594U, 21678U, 21894U,	10610	5107U, 5260U, 22280U, 27111U, 3726U, 21594U, 21678U, 21894U,
10611	21595U, 21679U, 21895U, 10041U, 9943U, 10156U, 14058U, 13953U,	10611	21595U, 21679U, 21895U, 10041U, 9943U, 10156U, 14058U, 13953U,
10612	14218U, 25026U, 16173U, 25058U, 16189U, 26111U, 24340U, 27894U,	10612	14218U, 25026U, 16173U, 25058U, 16189U, 26111U, 24340U, 27894U,
10613	24822U, 24852U, 15510U, 3148U, 26957U, 3658U, 5320U, 8191U,	10613	24822U, 24852U, 15510U, 3148U, 26957U, 3658U, 5320U, 8191U,
10614	20765U, 7985U, 26930U, 3629U, 5290U, 8163U, 11535U, 24669U,	10614	20765U, 7985U, 26930U, 3629U, 5290U, 8163U, 11535U, 24669U,
10615	20209U, 18005U, 15330U, 2838U, 18657U, 22082U, 3283U, 19046U,	10615	20209U, 18005U, 15330U, 2838U, 18657U, 22082U, 3283U, 19046U,
10616	10284U, 24657U, 20194U, 17936U, 15341U, 2851U, 22447U, 18671U,	10616	10284U, 24657U, 20194U, 17936U, 15341U, 2851U, 22447U, 18671U,
10617	24352U, 20173U, 27907U, 20866U, 13987U, 9978U, 27171U, 3817U,	10617	24352U, 20173U, 27907U, 20866U, 13987U, 9978U, 27171U, 3817U,
10618	24841U, 379U, 2362U, 15473U, 2989U, 23605U, 635U, 2675U,	10618	24841U, 379U, 2362U, 15473U, 2989U, 23605U, 635U, 2675U,
10619	15549U, 3193U, 23959U, 550U, 2590U, 15527U, 3167U, 23843U,	10619	15549U, 3193U, 23959U, 550U, 2590U, 15527U, 3167U, 23843U,
10620	13124U, 674U, 23992U, 24871U, 15994U, 27104U, 23004U, 27119U,	10620	13124U, 674U, 23992U, 24871U, 15994U, 27104U, 23004U, 27119U,
10621	9831U, 3897U, 203U, 27262U, 27300U, 27362U, 27706U, 27327U,	10621	9831U, 3897U, 203U, 27262U, 27300U, 27362U, 27706U, 27327U,
10622	27406U, 13313U, 27089U, 3708U, 24692U, 27133U, 3753U, 27126U,	10622	27406U, 13313U, 27089U, 3708U, 24692U, 27133U, 3753U, 27126U,
10623	3735U, 27149U, 3773U, 13366U, 27096U, 3717U, 24707U, 27141U,	10623	3735U, 27149U, 3773U, 13366U, 27096U, 3717U, 24707U, 27141U,
10624	3763U, 3744U, 3783U, 27317U, 27308U, 21433U, 21624U, 21708U,	10624	3763U, 3744U, 3783U, 27317U, 27308U, 21433U, 21624U, 21708U,
10625	21733U, 21924U, 27338U, 27437U, 8226U, 2055U, 22336U, 22422U,	10625	21733U, 21924U, 27338U, 27437U, 8226U, 2055U, 22336U, 22422U,
10626	12459U, 25743U, 3919U, 19032U, 21446U, 21637U, 21721U, 21746U,	10626	12459U, 25743U, 3919U, 19032U, 21446U, 21637U, 21721U, 21746U,
10627	21937U, 27815U, 27823U, 26902U, 26894U, 27802U, 27047U, 27850U,	10627	21937U, 27815U, 27823U, 26902U, 26894U, 27802U, 27047U, 27850U,
10628	27075U, 27996U, 28025U, 27789U, 27033U, 27837U, 27061U, 27981U,	10628	27075U, 27996U, 28025U, 27789U, 27033U, 27837U, 27061U, 27981U,
10629	28011U, 5020U, 4479U, 4494U, 5032U, 5247U, 15846U, 13679U,	10629	28011U, 5020U, 4479U, 4494U, 5032U, 5247U, 15846U, 13679U,
10630	13661U, 13695U, 13711U, 13754U, 2808U, 9879U, 2000U, 18216U,	10630	13661U, 13695U, 13711U, 13754U, 2808U, 9879U, 2000U, 18216U,
10631	6829U, 18956U, 6961U, 22149U, 19077U, 27277U, 27374U, 27717U,	10631	6829U, 18956U, 6961U, 22149U, 19077U, 27277U, 27374U, 27717U,
10632	27350U, 27448U, 26978U, 27923U, 28039U, 26982U, 28043U, 21609U,	10632	27350U, 27448U, 26978U, 27923U, 28039U, 26982U, 28043U, 21609U,
10633	21693U, 21909U, 14177U, 18472U, 10101U, 1353U, 26039U, 20640U,	10633	21693U, 21909U, 14177U, 18472U, 10101U, 1353U, 26039U, 20640U,
10634	11455U, 11242U, 17958U, 6006U, 19157U, 16905U, 17318U, 19329U,	10634	11455U, 11242U, 17958U, 6006U, 19157U, 16905U, 17318U, 19329U,
10635	7871U, 13978U, 1456U, 14095U, 1511U, 25782U, 1869U, 25344U,	10635	7871U, 13978U, 1456U, 14095U, 1511U, 25782U, 1869U, 25344U,
10636	1841U, 14050U, 18368U, 14157U, 18459U, 26021U, 20628U, 3401U,	10636	1841U, 14050U, 18368U, 14157U, 18459U, 26021U, 20628U, 3401U,
10637	11266U, 17969U, 10339U, 11842U, 14457U, 25097U, 10747U, 12641U,	10637	11266U, 17969U, 10339U, 11842U, 14457U, 25097U, 10747U, 12641U,
10638	14946U, 26066U, 10939U, 13006U, 15195U, 26415U, 17535U, 5746U,	10638	14946U, 26066U, 10939U, 13006U, 15195U, 26415U, 17535U, 5746U,
10639	9969U, 1258U, 10079U, 1321U, 7841U, 14242U, 1599U, 10181U,	10639	9969U, 1258U, 10079U, 1321U, 7841U, 14242U, 1599U, 10181U,
10640	17859U, 14197U, 1571U, 10121U, 17806U, 10553U, 12206U, 14642U,	10640	17859U, 14197U, 1571U, 10121U, 17806U, 10553U, 12206U, 14642U,
10641	25462U, 11009U, 13087U, 15265U, 26505U, 11299U, 17978U, 10323U,	10641	25462U, 11009U, 13087U, 15265U, 26505U, 11299U, 17978U, 10323U,
10642	11825U, 14441U, 25080U, 18012U, 6228U, 26987U, 20789U, 27941U,	10642	11825U, 14441U, 25080U, 18012U, 6228U, 26987U, 20789U, 27941U,
10643	20885U, 27874U, 20843U, 20990U, 7019U, 11235U, 5994U, 11622U,	10643	20885U, 27874U, 20843U, 20990U, 7019U, 11235U, 5994U, 11622U,
10644	17346U, 5587U, 2178U, 17373U, 5620U, 10428U, 6884U, 18019U,	10644	17346U, 5587U, 2178U, 17373U, 5620U, 10428U, 6884U, 18019U,
10645	6237U, 24942U, 26992U, 3681U, 20797U, 11672U, 1413U, 10652U,	10645	6237U, 24942U, 26992U, 3681U, 20797U, 11672U, 1413U, 10652U,
10646	12488U, 14795U, 25868U, 10844U, 12853U, 15053U, 26262U, 15404U,	10646	12488U, 14795U, 25868U, 10844U, 12853U, 15053U, 26262U, 15404U,
10647	11229U, 5983U, 6912U, 10729U, 12623U, 14919U, 26048U, 10921U,	10647	11229U, 5983U, 6912U, 10729U, 12623U, 14919U, 26048U, 10921U,
10648	12988U, 15177U, 26397U, 10677U, 12562U, 14858U, 25942U, 10869U,	10648	12988U, 15177U, 26397U, 10677U, 12562U, 14858U, 25942U, 10869U,
10649	12927U, 15116U, 26336U, 4547U, 4423U, 4931U, 4575U, 4372U,	10649	12927U, 15116U, 26336U, 4547U, 4423U, 4931U, 4575U, 4372U,
10650	4871U, 4439U, 5234U, 5173U, 17330U, 27873U, 15591U, 11079U,	10650	4871U, 4439U, 5234U, 5173U, 17330U, 27873U, 15591U, 11079U,
10651	5862U, 20989U, 1774U, 76U, 222U, 216U, 230U, 11050U,	10651	5862U, 20989U, 1774U, 76U, 222U, 216U, 230U, 11050U,
10652	5527U, 26856U, 6169U, 13562U, 15767U, 18188U, 26823U, 6132U,	10652	5527U, 26856U, 6169U, 13562U, 15767U, 18188U, 26823U, 6132U,
10653	24069U, 16008U, 20134U, 26863U, 6182U, 26830U, 6145U, 10489U,	10653	24069U, 16008U, 20134U, 26863U, 6182U, 26830U, 6145U, 10489U,
10654	12156U, 14592U, 25412U, 10623U, 12407U, 14766U, 25691U, 5825U,	10654	12156U, 14592U, 25412U, 10623U, 12407U, 14766U, 25691U, 5825U,
10655	22628U, 3303U, 11261U, 2095U, 6029U, 15998U, 17580U, 11114U,	10655	22628U, 3303U, 11261U, 2095U, 6029U, 15998U, 17580U, 11114U,
10656	5922U, 11323U, 5574U, 2154U, 17996U, 6195U, 19378U, 11053U,	10656	5922U, 11323U, 5574U, 2154U, 17996U, 6195U, 19378U, 11053U,
10657	2067U, 5833U, 11277U, 2114U, 6068U, 26813U, 3501U, 15599U,	10657	2067U, 5833U, 11277U, 2114U, 6068U, 26813U, 3501U, 15599U,
10658	11090U, 5883U, 15951U, 19650U, 18791U, 11305U, 2130U, 6110U,	10658	11090U, 5883U, 15951U, 19650U, 18791U, 11305U, 2130U, 6110U,
10659	16149U, 20726U, 26877U, 3533U, 11122U, 5935U, 11329U, 2162U,	10659	16149U, 20726U, 26877U, 3533U, 11122U, 5935U, 11329U, 2162U,
10660	6206U, 16161U, 20749U, 10465U, 12132U, 14568U, 25388U, 10595U,	10660	6206U, 16161U, 20749U, 10465U, 12132U, 14568U, 25388U, 10595U,
10661	12255U, 14669U, 25505U, 10519U, 12172U, 14608U, 25428U, 10637U,	10661	12255U, 14669U, 25505U, 10519U, 12172U, 14608U, 25428U, 10637U,
10662	12451U, 14780U, 25735U, 24789U, 20273U, 22207U, 7039U, 26818U,	10662	12451U, 14780U, 25735U, 24789U, 20273U, 22207U, 7039U, 26818U,
10663	3508U, 11098U, 5896U, 11311U, 2138U, 6121U, 16155U, 20734U,	10663	3508U, 11098U, 5896U, 11311U, 2138U, 6121U, 16155U, 20734U,
10664	11272U, 2107U, 6058U, 11283U, 2122U, 6079U, 26882U, 3540U,	10664	11272U, 2107U, 6058U, 11283U, 2122U, 6079U, 26882U, 3540U,
10665	15606U, 11130U, 5948U, 15959U, 19661U, 18801U, 11335U, 2170U,	10665	15606U, 11130U, 5948U, 15959U, 19661U, 18801U, 11335U, 2170U,
10666	6217U, 16167U, 20757U, 10568U, 24991U, 10561U, 24979U, 13380U,	10666	6217U, 16167U, 20757U, 10568U, 24991U, 10561U, 24979U, 13380U,
10667	2771U, 11058U, 2074U, 5843U, 10435U, 12110U, 14546U, 25366U,	10667	2771U, 11058U, 2074U, 5843U, 10435U, 12110U, 14546U, 25366U,
10668	10407U, 12089U, 14525U, 25270U, 15742U, 17570U, 11106U, 5909U,	10668	10407U, 12089U, 14525U, 25270U, 15742U, 17570U, 11106U, 5909U,
10669	11317U, 5561U, 2146U, 17987U, 6158U, 18119U, 11289U, 6090U,	10669	11317U, 5561U, 2146U, 17987U, 6158U, 18119U, 11289U, 6090U,
10670	11044U, 13161U, 15300U, 24985U, 26562U, 11294U, 6100U, 737U,	10670	11044U, 13161U, 15300U, 24985U, 26562U, 11294U, 6100U, 737U,
10671	1933U, 16847U, 15570U, 17401U, 5642U, 18775U, 6941U, 10443U,	10671	1933U, 16847U, 15570U, 17401U, 5642U, 18775U, 6941U, 10443U,
10672	24955U, 10537U, 12190U, 14626U, 25446U, 10816U, 12730U, 15025U,	10672	24955U, 10537U, 12190U, 14626U, 25446U, 10816U, 12730U, 15025U,
10673	26179U, 11039U, 13147U, 15295U, 24974U, 26557U, 4958U, 4604U,	10673	26179U, 11039U, 13147U, 15295U, 24974U, 26557U, 4958U, 4604U,
10674	4970U, 4617U, 4946U, 4591U, 4857U, 5282U, 4781U, 5274U,	10674	4970U, 4617U, 4946U, 4591U, 4857U, 5282U, 4781U, 5274U,
10675	4772U, 13321U, 13296U, 18047U, 18073U, 6772U, 8107U, 2457U,	10675	4772U, 13321U, 13296U, 18047U, 18073U, 6772U, 8107U, 2457U,
10676	6435U, 23698U, 7419U, 704U, 2738U, 6704U, 20466U, 24018U,	10676	6435U, 23698U, 7419U, 704U, 2738U, 6704U, 20466U, 24018U,
10677	20098U, 7700U, 10474U, 12141U, 14577U, 25397U, 10610U, 12325U,	10677	20098U, 7700U, 10474U, 12141U, 14577U, 25397U, 10610U, 12325U,
10678	14692U, 25588U, 92U, 16296U, 16889U, 9842U, 23267U, 1006U,	10678	14692U, 25588U, 92U, 16296U, 16889U, 9842U, 23267U, 1006U,
10679	1039U, 1093U, 12480U, 6577U, 23835U, 7561U, 10685U, 12570U,	10679	1039U, 1093U, 12480U, 6577U, 23835U, 7561U, 10685U, 12570U,
10680	14866U, 25950U, 10877U, 12935U, 15124U, 26344U, 10669U, 12554U,	10680	14866U, 25950U, 10877U, 12935U, 15124U, 26344U, 10669U, 12554U,
10681	14850U, 25934U, 10861U, 12919U, 15108U, 26328U, 22078U, 19039U,	10681	14850U, 25934U, 10861U, 12919U, 15108U, 26328U, 22078U, 19039U,
10682	7030U, 8139U, 10703U, 12588U, 14884U, 25968U, 10895U, 12953U,	10682	7030U, 8139U, 10703U, 12588U, 14884U, 25968U, 10895U, 12953U,
10683	15142U, 26362U, 10764U, 12658U, 14963U, 26083U, 10967U, 13034U,	10683	15142U, 26362U, 10764U, 12658U, 14963U, 26083U, 10967U, 13034U,
10684	15223U, 26443U, 26845U, 20742U, 7964U, 8156U, 10016U, 1272U,	10684	15223U, 26443U, 26845U, 20742U, 7964U, 8156U, 10016U, 1272U,
10685	9918U, 1226U, 10131U, 1368U, 10029U, 17764U, 9931U, 17691U,	10685	9918U, 1226U, 10131U, 1368U, 10029U, 17764U, 9931U, 17691U,
10686	10144U, 17819U, 10047U, 17779U, 9949U, 17706U, 10162U, 17834U,	10686	10144U, 17819U, 10047U, 17779U, 9949U, 17706U, 10162U, 17834U,
10687	6354U, 7314U, 12385U, 6563U, 14064U, 18379U, 23819U, 7547U,	10687	6354U, 7314U, 12385U, 6563U, 14064U, 18379U, 23819U, 7547U,
10688	12081U, 23624U, 11987U, 6325U, 13959U, 18298U, 23550U, 7285U,	10688	12081U, 23624U, 11987U, 6325U, 13959U, 18298U, 23550U, 7285U,
10689	12798U, 6636U, 14224U, 18499U, 23920U, 7620U, 12048U, 6339U,	10689	12798U, 6636U, 14224U, 18499U, 23920U, 7620U, 12048U, 6339U,
10690	23559U, 7299U, 12338U, 6517U, 23773U, 7501U, 11940U, 6279U,	10690	23559U, 7299U, 12338U, 6517U, 23773U, 7501U, 11940U, 6279U,
10691	23504U, 7239U, 12751U, 6590U, 23874U, 7574U, 12364U, 6532U,	10691	23504U, 7239U, 12751U, 6590U, 23874U, 7574U, 12364U, 6532U,
10692	23783U, 7516U, 11966U, 6294U, 23514U, 7254U, 12777U, 6605U,	10692	23783U, 7516U, 11966U, 6294U, 23514U, 7254U, 12777U, 6605U,
10693	23884U, 7589U, 12298U, 6488U, 23731U, 7472U, 12375U, 6548U,	10693	23884U, 7589U, 12298U, 6488U, 23731U, 7472U, 12375U, 6548U,
10694	23802U, 7532U, 11977U, 6310U, 23533U, 7270U, 12788U, 6621U,	10694	23802U, 7532U, 11977U, 6310U, 23533U, 7270U, 12788U, 6621U,
10695	23903U, 7605U, 12308U, 6503U, 23748U, 7487U, 10799U, 12713U,	10695	23903U, 7605U, 12308U, 6503U, 23748U, 7487U, 10799U, 12713U,
10696	15008U, 26162U, 10991U, 15247U, 26487U, 9856U, 9863U, 11442U,	10696	15008U, 26162U, 10991U, 15247U, 26487U, 9856U, 9863U, 11442U,
10697	13876U, 25005U, 11341U, 13859U, 24998U, 117U, 16312U, 16897U,	10697	13876U, 25005U, 11341U, 13859U, 24998U, 117U, 16312U, 16897U,
10698	9849U, 23393U, 19696U, 25032U, 20385U, 16179U, 23403U, 19709U,	10698	9849U, 23393U, 19696U, 25032U, 20385U, 16179U, 23403U, 19709U,
10699	25064U, 20398U, 6993U, 2480U, 17103U, 6464U, 23717U, 19903U,	10699	25064U, 20398U, 6993U, 2480U, 17103U, 6464U, 23717U, 19903U,
10700	7448U, 3484U, 3451U, 3439U, 540U, 16708U, 2580U, 17191U,	10700	7448U, 3484U, 3451U, 3439U, 540U, 16708U, 2580U, 17191U,
10701	16195U, 7006U, 3260U, 3468U, 26117U, 20652U, 7939U, 727U,	10701	16195U, 7006U, 3260U, 3468U, 26117U, 20652U, 7939U, 727U,
10702	16834U, 2761U, 17305U, 24037U, 20123U, 7729U, 522U, 16684U,	10702	16834U, 2761U, 17305U, 24037U, 20123U, 7729U, 522U, 16684U,
10703	2562U, 17167U, 23812U, 19957U, 371U, 16545U, 2354U, 17055U,	10703	2562U, 17167U, 23812U, 19957U, 371U, 16545U, 2354U, 17055U,
10704	23599U, 19839U, 344U, 16509U, 2327U, 17031U, 23543U, 19809U,	10704	23599U, 19839U, 344U, 16509U, 2327U, 17031U, 23543U, 19809U,
10705	597U, 16760U, 2637U, 17243U, 23913U, 20010U, 303U, 16456U,	10705	597U, 16760U, 2637U, 17243U, 23913U, 20010U, 303U, 16456U,
10706	2286U, 16978U, 23479U, 19764U, 313U, 16469U, 2296U, 16991U,	10706	2286U, 16978U, 23479U, 19764U, 313U, 16469U, 2296U, 16991U,
10707	23487U, 19775U, 431U, 16596U, 2414U, 17078U, 23663U, 19882U,	10707	23487U, 19775U, 431U, 16596U, 2414U, 17078U, 23663U, 19882U,
10708	567U, 16721U, 2607U, 17204U, 23858U, 19977U, 324U, 16483U,	10708	567U, 16721U, 2607U, 17204U, 23858U, 19977U, 324U, 16483U,
10709	2307U, 17005U, 23496U, 19787U, 577U, 16734U, 2617U, 17217U,	10709	2307U, 17005U, 23496U, 19787U, 577U, 16734U, 2617U, 17217U,
10710	23866U, 19988U, 502U, 16658U, 2542U, 17141U, 23765U, 19935U,	10710	23866U, 19988U, 502U, 16658U, 2542U, 17141U, 23765U, 19935U,
10711	353U, 16521U, 2336U, 17043U, 23585U, 19819U, 512U, 16671U,	10711	353U, 16521U, 2336U, 17043U, 23585U, 19819U, 512U, 16671U,
10712	2552U, 17154U, 23794U, 19946U, 334U, 16496U, 2317U, 17018U,	10712	2552U, 17154U, 23794U, 19946U, 334U, 16496U, 2317U, 17018U,
10713	23525U, 19798U, 587U, 16747U, 2627U, 17230U, 23895U, 19999U,	10713	23525U, 19798U, 587U, 16747U, 2627U, 17230U, 23895U, 19999U,
10714	474U, 16621U, 2514U, 17116U, 23741U, 19914U, 5055U, 4894U,	10714	474U, 16621U, 2514U, 17116U, 23741U, 19914U, 5055U, 4894U,
10715	4521U, 11454U, 26986U, 27940U, 27879U, 15325U, 20996U, 15393U,	10715	4521U, 11454U, 26986U, 27940U, 27879U, 15325U, 20996U, 15393U,
10716	15403U, 22206U, 22077U, 8138U, 26844U, 8155U, 24796U, 24777U,	10716	15403U, 22206U, 22077U, 8138U, 26844U, 8155U, 24796U, 24777U,
10717	24218U, 20142U, 7781U, 24593U, 1049U, 20919U, 24771U, 15312U,	10717	24218U, 20142U, 7781U, 24593U, 1049U, 20919U, 24771U, 15312U,
10718	23272U, 20913U, 24750U, 24797U, 24778U, 7892U, 7902U, 10783U,	10718	23272U, 20913U, 24750U, 24797U, 24778U, 7892U, 7902U, 10783U,
10719	12697U, 14982U, 26136U, 10975U, 13062U, 15231U, 26471U, 18635U,	10719	12697U, 14982U, 26136U, 10975U, 13062U, 15231U, 26471U, 18635U,
10720	6886U, 9837U, 8070U, 9U, 97U, 1165U, 21152U, 15U,	10720	6886U, 9837U, 8070U, 9U, 97U, 1165U, 21152U, 15U,
10721	11764U, 24681U, 24363U, 49U, 134U, 1171U, 21165U, 36U,	10721	11764U, 24681U, 24363U, 49U, 134U, 1171U, 21165U, 36U,
10722	14430U, 24712U, 16043U, 24346U, 27900U, 24738U, 8130U, 12614U,	10722	14430U, 24712U, 16043U, 24346U, 27900U, 24738U, 8130U, 12614U,
10723	14910U, 26003U, 12979U, 15168U, 26388U, 12536U, 14832U, 25916U,	10723	14910U, 26003U, 12979U, 15168U, 26388U, 12536U, 14832U, 25916U,
10724	12901U, 15090U, 26310U, 14306U, 1656U, 14381U, 1708U, 25527U,	10724	12901U, 15090U, 26310U, 14306U, 1656U, 14381U, 1708U, 25527U,
10725	20476U, 14343U, 18548U, 15657U, 18864U, 22689U, 19453U, 14407U,	10725	20476U, 14343U, 18548U, 15657U, 18864U, 22689U, 19453U, 14407U,
10726	1744U, 14286U, 1626U, 22284U, 14320U, 1675U, 14394U, 1726U,	10726	1744U, 14286U, 1626U, 22284U, 14320U, 1675U, 14394U, 1726U,
10727	25539U, 20491U, 14369U, 18580U, 12506U, 14813U, 25886U, 12871U,	10727	25539U, 20491U, 14369U, 18580U, 12506U, 14813U, 25886U, 12871U,
10728	15071U, 26280U, 15668U, 18878U, 22700U, 19467U, 14417U, 1759U,	10728	15071U, 26280U, 15668U, 18878U, 22700U, 19467U, 14417U, 1759U,
10729	14334U, 1694U, 23166U, 998U, 24930U, 13866U, 24828U, 11594U,	10729	14334U, 1694U, 23166U, 998U, 24930U, 13866U, 24828U, 11594U,
10730	15972U, 984U, 1029U, 24882U, 8550U, 238U, 24783U, 16003U,	10730	15972U, 984U, 1029U, 24882U, 8550U, 238U, 24783U, 16003U,
10731	991U, 24888U, 10241U, 27867U, 24858U, 22579U, 13421U, 7111U,	10731	991U, 24888U, 10241U, 27867U, 24858U, 22579U, 13421U, 7111U,
10732	5141U, 5119U, 9875U, 17678U, 5777U, 15317U, 18643U, 6894U,	10732	5141U, 5119U, 9875U, 17678U, 5777U, 15317U, 18643U, 6894U,
10733	24367U, 24219U, 11138U, 5961U, 20143U, 7782U, 22583U, 13426U,	10733	24367U, 24219U, 11138U, 5961U, 20143U, 7782U, 22583U, 13426U,
10734	7120U, 24594U, 22540U, 22226U, 24916U, 20336U, 19102U, 24924U,	10734	7120U, 24594U, 22540U, 22226U, 24916U, 20336U, 19102U, 24924U,
10735	20347U, 19356U, 25848U, 20590U, 25811U, 20564U, 14990U, 18613U,	10735	20347U, 19356U, 25848U, 20590U, 25811U, 20564U, 14990U, 18613U,
10736	26542U, 20676U, 25838U, 20577U, 25792U, 20539U, 14928U, 18601U,	10736	26542U, 20676U, 25838U, 20577U, 25792U, 20539U, 14928U, 18601U,
10737	25749U, 20517U, 23388U, 1013U, 20187U, 7813U, 531U, 16696U,	10737	25749U, 20517U, 23388U, 1013U, 20187U, 7813U, 531U, 16696U,
10738	2571U, 17179U, 23828U, 19967U, 11889U, 284U, 16431U, 2267U,	10738	2571U, 17179U, 23828U, 19967U, 11889U, 284U, 16431U, 2267U,
10739	16966U, 3363U, 23464U, 19743U, 7227U, 25144U, 12034U, 25249U,	10739	16966U, 3363U, 23464U, 19743U, 7227U, 25144U, 12034U, 25249U,
10740	12324U, 25587U, 12479U, 25859U, 11926U, 25181U, 12737U, 26186U,	10740	12324U, 25587U, 12479U, 25859U, 11926U, 25181U, 12737U, 26186U,
10741	493U, 16646U, 2533U, 1020U, 16877U, 11996U, 25211U, 12421U,	10741	493U, 16646U, 2533U, 1020U, 16877U, 11996U, 25211U, 12421U,
10742	25705U, 12348U, 25601U, 11950U, 25195U, 12761U, 26200U, 12010U,	10742	25705U, 12348U, 25601U, 11950U, 25195U, 12761U, 26200U, 12010U,
10743	25225U, 12284U, 25558U, 13110U, 656U, 16810U, 2696U, 17281U,	10743	25225U, 12284U, 25558U, 13110U, 656U, 16810U, 2696U, 17281U,
10744	23978U, 20052U, 7646U, 26528U, 14684U, 25572U, 11797U, 25050U,	10744	23978U, 20052U, 7646U, 26528U, 14684U, 25572U, 11797U, 25050U,
10745	12233U, 25483U, 12435U, 25719U, 12666U, 26091U, 13042U, 26451U,	10745	12233U, 25483U, 12435U, 25719U, 12666U, 26091U, 13042U, 26451U,
10746	12242U, 25492U, 12444U, 25728U, 10576U, 12220U, 14650U, 25470U,	10746	12242U, 25492U, 12444U, 25728U, 10576U, 12220U, 14650U, 25470U,
10747	11789U, 25042U, 2468U, 6449U, 23707U, 7433U, 715U, 2749U,	10747	11789U, 25042U, 2468U, 6449U, 23707U, 7433U, 715U, 2749U,
10748	6718U, 20506U, 24027U, 20110U, 7714U, 11896U, 25151U, 11851U,	10748	6718U, 20506U, 24027U, 20110U, 7714U, 11896U, 25151U, 11851U,
10749	25106U, 13140U, 26550U, 11833U, 25088U, 12277U, 25551U, 665U,	10749	25106U, 13140U, 26550U, 11833U, 25088U, 12277U, 25551U, 665U,
10750	16822U, 2705U, 17293U, 6662U, 23985U, 20062U, 7658U, 11867U,	10750	16822U, 2705U, 17293U, 6662U, 23985U, 20062U, 7658U, 11867U,
10751	25122U, 12263U, 441U, 16609U, 2424U, 17091U, 3382U, 23671U,	10751	25122U, 12263U, 441U, 16609U, 2424U, 17091U, 3382U, 23671U,
10752	19893U, 7377U, 25513U, 400U, 16556U, 2383U, 17066U, 23632U,	10752	19893U, 7377U, 25513U, 400U, 16556U, 2383U, 17066U, 23632U,
10753	19848U, 7354U, 15576U, 12317U, 25580U, 12814U, 26223U, 12839U,	10753	19848U, 7354U, 15576U, 12317U, 25580U, 12814U, 26223U, 12839U,
10754	26248U, 12041U, 25256U, 12331U, 25594U, 11933U, 25188U, 12744U,	10754	26248U, 12041U, 25256U, 12331U, 25594U, 11933U, 25188U, 12744U,
10755	26193U, 12003U, 25218U, 12428U, 25712U, 12831U, 606U, 16772U,	10755	26193U, 12003U, 25218U, 12428U, 25712U, 12831U, 606U, 16772U,
10756	2646U, 17255U, 23936U, 20020U, 26240U, 11860U, 265U, 16406U,	10756	2646U, 17255U, 23936U, 20020U, 26240U, 11860U, 265U, 16406U,
10757	2248U, 16954U, 3353U, 23449U, 19722U, 7215U, 25115U, 12356U,	10757	2248U, 16954U, 3353U, 23449U, 19722U, 7215U, 25115U, 12356U,
10758	25609U, 11958U, 25203U, 12769U, 26208U, 12018U, 25233U, 12291U,	10758	25609U, 11958U, 25203U, 12769U, 26208U, 12018U, 25233U, 12291U,
10759	25565U, 12676U, 26101U, 13052U, 26461U, 14698U, 25617U, 12516U,	10759	25565U, 12676U, 26101U, 13052U, 26461U, 14698U, 25617U, 12516U,
10760	25896U, 12881U, 26290U, 15417U, 6930U, 24587U, 7802U, 12527U,	10760	25896U, 12881U, 26290U, 15417U, 6930U, 24587U, 7802U, 12527U,
10761	14823U, 25907U, 12892U, 15081U, 26301U, 12497U, 14804U, 25877U,	10761	14823U, 25907U, 12892U, 15081U, 26301U, 12497U, 14804U, 25877U,
10762	12862U, 15062U, 26271U, 15855U, 18968U, 11024U, 13102U, 15280U,	10762	12862U, 15062U, 26271U, 15855U, 18968U, 11024U, 13102U, 15280U,
10763	26520U, 10603U, 12270U, 14677U, 25520U, 10384U, 11918U, 14502U,	10763	26520U, 10603U, 12270U, 14677U, 25520U, 10384U, 11918U, 14502U,
10764	25173U, 10645U, 12465U, 14788U, 25756U, 23268U, 10830U, 12822U,	10764	25173U, 10645U, 12465U, 14788U, 25756U, 23268U, 10830U, 12822U,
10765	15039U, 26231U, 24937U, 10392U, 12026U, 14510U, 25241U, 20365U,	10765	15039U, 26231U, 24937U, 10392U, 12026U, 14510U, 25241U, 20365U,
10766	19672U, 7182U, 15568U, 15595U, 22985U, 17477U, 3314U, 5548U,	10766	19672U, 7182U, 15568U, 15595U, 22985U, 17477U, 3314U, 5548U,
10767	5786U, 6039U, 17496U, 19679U, 9899U, 2024U, 19570U, 19642U,	10767	5786U, 6039U, 17496U, 19679U, 9899U, 2024U, 19570U, 19642U,
10768	26769U, 20703U, 18784U, 11084U, 2087U, 5872U, 11063U, 2081U,	10768	26769U, 20703U, 18784U, 11084U, 2087U, 5872U, 11063U, 2081U,
10769	5853U, 22982U, 17469U, 3309U, 22530U, 17337U, 5537U, 7085U,	10769	5853U, 22982U, 17469U, 3309U, 22530U, 17337U, 5537U, 7085U,
10770	9893U, 2016U, 8043U, 8078U, 19564U, 18770U, 4865U, 3905U,	10770	9893U, 2016U, 8043U, 8078U, 19564U, 18770U, 4865U, 3905U,
10771	4798U, 4790U, 5004U, 4836U, 9907U, 2034U, 13176U, 18026U,	10771	4798U, 4790U, 5004U, 4836U, 9907U, 2034U, 13176U, 18026U,
10772	17516U, 26774U, 20711U, 7822U, 17685U, 5800U, 27863U, 3848U,	10772	17516U, 26774U, 20711U, 7822U, 17685U, 5800U, 27863U, 3848U,
10773	13552U, 18172U, 20828U, 11602U, 82U, 1948U, 5489U, 450U,	10773	13552U, 18172U, 20828U, 11602U, 82U, 1948U, 5489U, 450U,
10774	2490U, 1155U, 5407U, 8011U, 1913U, 10422U, 12104U, 14540U,	10774	2490U, 1155U, 5407U, 8011U, 1913U, 10422U, 12104U, 14540U,
10775	25360U, 15679U, 11224U, 22749U, 162U, 1962U, 10371U, 11905U,	10775	25360U, 15679U, 11224U, 22749U, 162U, 1962U, 10371U, 11905U,
10776	14489U, 25160U, 27947U, 3867U, 20881U, 13893U, 2828U, 13327U,	10776	14489U, 25160U, 27947U, 3867U, 20881U, 13893U, 2828U, 13327U,
10777	18082U, 17545U, 26725U, 20696U, 18246U, 27885U, 3854U, 13557U,	10777	18082U, 17545U, 26725U, 20696U, 18246U, 27885U, 3854U, 13557U,
10778	18180U, 20851U, 17393U, 5632U, 15852U, 3255U, 8062U, 11605U,	10778	18180U, 20851U, 17393U, 5632U, 15852U, 3255U, 8062U, 11605U,
10779	8100U, 13362U, 18096U, 18962U, 6967U, 8124U, 9838U, 5768U,	10779	8100U, 13362U, 18096U, 18962U, 6967U, 8124U, 9838U, 5768U,
10780	8071U, 6921U, 174U, 1978U, 16344U, 27029U, 3702U, 20821U,	10780	8071U, 6921U, 174U, 1978U, 16344U, 27029U, 3702U, 20821U,
10781	25013U, 17554U, 3479U, 152U, 16328U, 1177U, 5469U, 8027U,	10781	25013U, 17554U, 3479U, 152U, 16328U, 1177U, 5469U, 8027U,
10782	1923U, 22377U, 19188U, 13519U, 18158U, 19130U, 16141U, 3271U,	10782	1923U, 22377U, 19188U, 13519U, 18158U, 19130U, 16141U, 3271U,
10783	13370U, 18103U, 19011U, 17430U, 5677U, 16859U, 11256U, 6019U,	10783	13370U, 18103U, 19011U, 17430U, 5677U, 16859U, 11256U, 6019U,
10784	19364U, 23214U, 3341U, 13455U, 18133U, 19628U, 19340U, 11250U,	10784	19364U, 23214U, 3341U, 13455U, 18133U, 19628U, 19340U, 11250U,
10785	20258U, 26779U, 186U, 16362U, 19688U, 20719U, 20373U, 7923U,	10785	20258U, 26779U, 186U, 16362U, 19688U, 20719U, 20373U, 7923U,
10786	27919U, 4274U, 4338U, 4306U, 4355U, 4884U, 4625U, 4510U,	10786	27919U, 4274U, 4338U, 4306U, 4355U, 4884U, 4625U, 4510U,
10787	4984U, 4641U, 4391U, 4453U, 11541U, 12066U, 6381U, 23577U,	10787	4984U, 4641U, 4391U, 4453U, 11541U, 12066U, 6381U, 23577U,
10788	7341U, 14740U, 25659U, 24675U, 22510U, 19303U, 20215U, 11008U,	10788	7341U, 14740U, 25659U, 24675U, 22510U, 19303U, 20215U, 11008U,
10789	13086U, 15264U, 26504U, 294U, 16444U, 2277U, 22398U, 19218U,	10789	13086U, 15264U, 26504U, 294U, 16444U, 2277U, 22398U, 19218U,
10790	18011U, 14713U, 25632U, 23472U, 19754U, 15773U, 18892U, 22909U,	10790	18011U, 14713U, 25632U, 23472U, 19754U, 15773U, 18892U, 22909U,
10791	19500U, 15799U, 18924U, 22935U, 19532U, 11818U, 6267U, 23442U,	10791	19500U, 15799U, 18924U, 22935U, 19532U, 11818U, 6267U, 23442U,
10792	7203U, 10712U, 12597U, 14893U, 25977U, 10904U, 12962U, 15151U,	10792	7203U, 10712U, 12597U, 14893U, 25977U, 10904U, 12962U, 15151U,
10793	26371U, 10348U, 11852U, 14466U, 25107U, 13141U, 6733U, 24045U,	10793	26371U, 10348U, 11852U, 14466U, 25107U, 13141U, 6733U, 24045U,
10794	10791U, 12705U, 15000U, 7742U, 26154U, 10983U, 13070U, 15239U,	10794	10791U, 12705U, 15000U, 7742U, 26154U, 10983U, 13070U, 15239U,
10795	26479U, 10U, 5345U, 98U, 2184U, 16304U, 5387U, 1166U,	10795	26479U, 10U, 5345U, 98U, 2184U, 16304U, 5387U, 1166U,
10796	5427U, 16U, 16258U, 5355U, 245U, 16380U, 2193U, 16916U,	10796	5427U, 16U, 16258U, 5355U, 245U, 16380U, 2193U, 16916U,
10797	5437U, 22U, 16267U, 15336U, 17383U, 2844U, 22438U, 19230U,	10797	5437U, 22U, 16267U, 15336U, 17383U, 2844U, 22438U, 19230U,
10798	18663U, 22088U, 17448U, 3289U, 22473U, 19254U, 19052U, 23161U,	10798	18663U, 22088U, 17448U, 3289U, 22473U, 19254U, 19052U, 23161U,
10799	11805U, 6255U, 23435U, 7191U, 10694U, 12579U, 14875U, 25959U,	10799	11805U, 6255U, 23435U, 7191U, 10694U, 12579U, 14875U, 25959U,
10800	10886U, 12944U, 15133U, 26353U, 10331U, 11834U, 14449U, 25089U,	10800	10886U, 12944U, 15133U, 26353U, 10331U, 11834U, 14449U, 25089U,
10801	12278U, 6477U, 23725U, 10721U, 12606U, 14902U, 7461U, 25995U,	10801	12278U, 6477U, 23725U, 10721U, 12606U, 14902U, 7461U, 25995U,
10802	10913U, 12971U, 15160U, 26380U, 11765U, 10239U, 17926U, 24682U,	10802	10913U, 12971U, 15160U, 26380U, 11765U, 10239U, 17926U, 24682U,
10803	7851U, 6246U, 10661U, 12546U, 14842U, 25926U, 10853U, 12911U,	10803	7851U, 6246U, 10661U, 12546U, 14842U, 25926U, 10853U, 12911U,
10804	15100U, 26320U, 17355U, 5598U, 19112U, 7063U, 24948U, 362U,	10804	15100U, 26320U, 17355U, 5598U, 19112U, 7063U, 24948U, 362U,
10805	16533U, 2345U, 15466U, 2980U, 18730U, 23592U, 19829U, 2222U,	10805	16533U, 2345U, 15466U, 2980U, 18730U, 23592U, 19829U, 2222U,
10806	15444U, 2873U, 23413U, 409U, 16568U, 2392U, 15492U, 3010U,	10806	15444U, 2873U, 23413U, 409U, 16568U, 2392U, 15492U, 3010U,
10807	18740U, 23639U, 19858U, 626U, 16798U, 2666U, 15542U, 3184U,	10807	18740U, 23639U, 19858U, 626U, 16798U, 2666U, 15542U, 3184U,
10808	18750U, 23952U, 20042U, 2235U, 15455U, 2886U, 23424U, 420U,	10808	18750U, 23952U, 20042U, 2235U, 15455U, 2886U, 23424U, 420U,
10809	16582U, 2403U, 15501U, 3021U, 18760U, 23648U, 19870U, 10290U,	10809	16582U, 2403U, 15501U, 3021U, 18760U, 23648U, 19870U, 10290U,
10810	12058U, 6368U, 23569U, 7328U, 14730U, 25649U, 24663U, 22500U,	10810	12058U, 6368U, 23569U, 7328U, 14730U, 25649U, 24663U, 22500U,
10811	19290U, 20200U, 11000U, 13078U, 15256U, 26496U, 275U, 16419U,	10811	19290U, 20200U, 11000U, 13078U, 15256U, 26496U, 275U, 16419U,
10812	2258U, 22389U, 19206U, 17942U, 14704U, 25623U, 23457U, 19733U,	10812	2258U, 22389U, 19206U, 17942U, 14704U, 25623U, 23457U, 19733U,
10813	50U, 5377U, 135U, 2213U, 16942U, 16320U, 5397U, 1172U,	10813	50U, 5377U, 135U, 2213U, 16942U, 16320U, 5397U, 1172U,
10814	5459U, 37U, 16287U, 5366U, 255U, 16393U, 2203U, 16929U,	10814	5459U, 37U, 16287U, 5366U, 255U, 16393U, 2203U, 16929U,
10815	5448U, 29U, 16277U, 15368U, 2866U, 22464U, 19242U, 18687U,	10815	5448U, 29U, 16277U, 15368U, 2866U, 22464U, 19242U, 18687U,
10816	22257U, 19138U, 22105U, 3296U, 22482U, 19266U, 19069U, 66U,	10816	22257U, 19138U, 22105U, 3296U, 22482U, 19266U, 19069U, 66U,
10817	198U, 1195U, 71U, 211U, 1200U, 23190U, 14431U, 24713U,	10817	198U, 1195U, 71U, 211U, 1200U, 23190U, 14431U, 24713U,
10818	7861U, 6864U, 16044U, 15811U, 18939U, 22947U, 19547U, 15613U,	10818	7861U, 6864U, 16044U, 15811U, 18939U, 22947U, 19547U, 15613U,
10819	18811U, 22645U, 19400U, 14117U, 18419U, 25828U, 1884U, 14167U,	10819	18811U, 22645U, 19400U, 14117U, 18419U, 25828U, 1884U, 14167U,
10820	1541U, 26030U, 1899U, 3411U, 14750U, 25669U, 14355U, 18563U,	10820	1541U, 26030U, 1899U, 3411U, 14750U, 25669U, 14355U, 18563U,
10821	14295U, 1640U, 24347U, 22520U, 19316U, 22491U, 19278U, 20179U,	10821	14295U, 1640U, 24347U, 22520U, 19316U, 22491U, 19278U, 20179U,
10822	27901U, 20872U, 24733U, 7882U, 11032U, 13117U, 15288U, 26535U,	10822	27901U, 20872U, 24733U, 7882U, 11032U, 13117U, 15288U, 26535U,
10823	19004U, 6984U, 14035U, 1483U, 14722U, 25641U, 8131U, 14138U,	10823	19004U, 6984U, 14035U, 1483U, 14722U, 25641U, 8131U, 14138U,
10824	1527U, 4850U, 4977U, 4164U, 3887U, 10356U, 11875U, 14474U,	10824	1527U, 4850U, 4977U, 4164U, 3887U, 10356U, 11875U, 14474U,
10825	25130U, 10363U, 11882U, 14481U, 25137U, 293U, 16443U, 2276U,	10825	25130U, 10363U, 11882U, 14481U, 25137U, 293U, 16443U, 2276U,
10826	23471U, 19753U, 274U, 16418U, 2257U, 23456U, 19732U, 22990U,	10826	23471U, 19753U, 274U, 16418U, 2257U, 23456U, 19732U, 22990U,
10827	3321U, 10505U, 19578U, 7129U, 24962U, 17507U, 5723U, 5045U,	10827	3321U, 10505U, 19578U, 7129U, 24962U, 17507U, 5723U, 5045U,
10828	5086U, 22991U, 17488U, 5713U, 3322U, 10506U, 6903U, 19579U,	10828	5086U, 22991U, 17488U, 5713U, 3322U, 10506U, 6903U, 19579U,
10829	7130U, 24963U, 27008U, 3689U, 20806U, 5185U, 14025U, 18344U,	10829	7130U, 24963U, 27008U, 3689U, 20806U, 5185U, 14025U, 18344U,
10830	13478U, 18149U, 6795U, 11016U, 13094U, 15272U, 26512U, 10376U,	10830	13478U, 18149U, 6795U, 11016U, 13094U, 15272U, 26512U, 10376U,
10831	11910U, 14494U, 25165U, 10823U, 12807U, 15032U, 26216U, 13993U,	10831	11910U, 14494U, 25165U, 10823U, 12807U, 15032U, 26216U, 13993U,
10832	18311U, 9984U, 17720U, 3373U, 3421U, 22285U, 15642U, 8484U,	10832	18311U, 9984U, 17720U, 3373U, 3421U, 22285U, 15642U, 8484U,
10833	17608U, 18846U, 22674U, 8534U, 17645U, 19435U, 15786U, 18908U,	10833	17608U, 18846U, 22674U, 8534U, 17645U, 19435U, 15786U, 18908U,
10834	22922U, 19516U, 15628U, 8469U, 17590U, 18829U, 22660U, 8519U,	10834	22922U, 19516U, 15628U, 8469U, 17590U, 18829U, 22660U, 8519U,
10835	17627U, 19418U, 13937U, 18279U, 25292U, 20433U, 13912U, 18263U,	10835	17627U, 19418U, 13937U, 18279U, 25292U, 20433U, 13912U, 18263U,
10836	25321U, 20448U, 13925U, 1425U, 25277U, 1786U, 25304U, 1806U,	10836	25321U, 20448U, 13925U, 1425U, 25277U, 1786U, 25304U, 1806U,
10837	13618U, 13303U, 18057U, 20687U, 18196U, 6806U, 8116U, 11664U,	10837	13618U, 13303U, 18057U, 20687U, 18196U, 6806U, 8116U, 11664U,
10838	1400U, 3392U, 3430U, 10225U, 17906U, 22351U, 19170U, 23208U,	10838	1400U, 3392U, 3430U, 10225U, 17906U, 22351U, 19170U, 23208U,
10839	3333U, 19619U, 7171U, 7147U, 483U, 16633U, 2523U, 17128U,	10839	3333U, 19619U, 7171U, 7147U, 483U, 16633U, 2523U, 17128U,
10840	23757U, 19924U, 14268U, 18536U, 10207U, 17882U, 14009U, 18333U,	10840	23757U, 19924U, 14268U, 18536U, 10207U, 17882U, 14009U, 18333U,
10841	10000U, 17742U, 12815U, 6650U, 23929U, 7634U, 23167U, 24931U,	10841	10000U, 17742U, 12815U, 6650U, 23929U, 7634U, 23167U, 24931U,
10842	20356U, 19592U, 2445U, 6420U, 23688U, 7404U, 692U, 2726U,	10842	20356U, 19592U, 2445U, 6420U, 23688U, 7404U, 692U, 2726U,
10843	6689U, 20422U, 24008U, 20085U, 7685U, 616U, 16785U, 2656U,	10843	6689U, 20422U, 24008U, 20085U, 7685U, 616U, 16785U, 2656U,
10844	17268U, 23944U, 20031U, 4805U, 4181U, 8465U, 11348U, 10756U,	10844	17268U, 23944U, 20031U, 4805U, 4181U, 8465U, 11348U, 10756U,
10845	12650U, 14955U, 26075U, 10959U, 13026U, 15215U, 26435U, 10236U,	10845	12650U, 14955U, 26075U, 10959U, 13026U, 15215U, 26435U, 10236U,
10846	17329U, 5517U, 2039U, 13193U, 18033U, 17920U, 5808U, 11269U,	10846	17329U, 5517U, 2039U, 13193U, 18033U, 17920U, 5808U, 11269U,
10847	2102U, 8054U, 11450U, 8093U, 13246U, 18040U, 17972U, 6050U,	10847	2102U, 8054U, 11450U, 8093U, 13246U, 18040U, 17972U, 6050U,
10848	8087U, 11786U, 22215U, 17458U, 5699U, 19085U, 7052U, 8146U,	10848	8087U, 11786U, 22215U, 17458U, 5699U, 19085U, 7052U, 8146U,
10849	87U, 1955U, 5503U, 462U, 2502U, 1160U, 5417U, 8019U,	10849	87U, 1955U, 5503U, 462U, 2502U, 1160U, 5417U, 8019U,
10850	1918U, 24829U, 20283U, 15683U, 22753U, 168U, 1970U, 9871U,	10850	1918U, 24829U, 20283U, 15683U, 22753U, 168U, 1970U, 9871U,
10851	1994U, 17671U, 13884U, 2822U, 18239U, 26870U, 3524U, 13167U,	10851	1994U, 17671U, 13884U, 2822U, 18239U, 26870U, 3524U, 13167U,
10852	6758U, 7973U, 24060U, 7767U, 26837U, 3515U, 13152U, 6744U,	10852	6758U, 7973U, 24060U, 7767U, 26837U, 3515U, 13152U, 6744U,
10853	7952U, 24051U, 7753U, 12214U, 6394U, 23657U, 7366U, 22632U,	10853	7952U, 24051U, 7753U, 12214U, 6394U, 23657U, 7366U, 22632U,
10854	27002U, 14427U, 17365U, 5610U, 2833U, 13331U, 18089U, 10401U,	10854	27002U, 14427U, 17365U, 5610U, 2833U, 13331U, 18089U, 10401U,
10855	14519U, 25264U, 22093U, 24909U, 20326U, 19060U, 14259U, 18524U,	10855	14519U, 25264U, 22093U, 24909U, 20326U, 19060U, 14259U, 18524U,
10856	10198U, 17870U, 14207U, 18485U, 26144U, 20663U, 14001U, 18322U,	10856	10198U, 17870U, 14207U, 18485U, 26144U, 20663U, 14001U, 18322U,
10857	9992U, 17731U, 14128U, 18433U, 25986U, 20604U, 14250U, 18512U,	10857	9992U, 17731U, 14128U, 18433U, 25986U, 20604U, 14250U, 18512U,
10858	10189U, 1386U, 14106U, 18405U, 10090U, 1337U, 25801U, 20551U,	10858	10189U, 1386U, 14106U, 18405U, 10090U, 1337U, 25801U, 20551U,
10859	13904U, 18252U, 9910U, 1213U, 14074U, 18392U, 10058U, 1290U,	10859	13904U, 18252U, 9910U, 1213U, 14074U, 18392U, 10058U, 1290U,
10860	25763U, 20527U, 14277U, 1612U, 10216U, 17894U, 14017U, 1470U,	10860	25763U, 20527U, 14277U, 1612U, 10216U, 17894U, 14017U, 1470U,
10861	10008U, 17753U, 18595U, 6856U, 13335U, 6783U, 10421U, 12103U,	10861	10008U, 17753U, 18595U, 6856U, 13335U, 6783U, 10421U, 12103U,
10862	14539U, 25359U, 10370U, 11904U, 14488U, 25159U, 15973U, 17412U,	10862	14539U, 25359U, 10370U, 11904U, 14488U, 25159U, 15973U, 17412U,
10863	5655U, 1030U, 3584U, 10451U, 12118U, 14554U, 25374U, 24883U,	10863	5655U, 1030U, 3584U, 10451U, 12118U, 14554U, 25374U, 24883U,
10864	20299U, 10583U, 12227U, 14657U, 18990U, 6975U, 25477U, 24332U,	10864	20299U, 10583U, 12227U, 14657U, 18990U, 6975U, 25477U, 24332U,
10865	3462U, 20159U, 27012U, 3695U, 20813U, 27975U, 3879U, 20894U,	10865	3462U, 20159U, 27012U, 3695U, 20813U, 27975U, 3879U, 20894U,
10866	27889U, 3860U, 20858U, 13400U, 26997U, 10528U, 12181U, 14617U,	10866	27889U, 3860U, 20858U, 13400U, 26997U, 10528U, 12181U, 14617U,
10867	25437U, 10808U, 12722U, 15017U, 26171U, 8551U, 10414U, 12096U,	10867	25437U, 10808U, 12722U, 15017U, 26171U, 8551U, 10414U, 12096U,
10868	14532U, 25352U, 10481U, 12148U, 14584U, 25404U, 10616U, 12394U,	10868	14532U, 25352U, 10481U, 12148U, 14584U, 25404U, 10616U, 12394U,
10869	14759U, 25678U, 24784U, 20265U, 10317U, 11812U, 14435U, 17664U,	10869	14759U, 25678U, 24784U, 20265U, 10317U, 11812U, 14435U, 17664U,
10870	25074U, 16004U, 17421U, 5666U, 10458U, 12125U, 14561U, 25381U,	10870	25074U, 16004U, 17421U, 5666U, 10458U, 12125U, 14561U, 25381U,
10871	10497U, 12164U, 14600U, 25420U, 10630U, 12414U, 14773U, 25698U,	10871	10497U, 12164U, 14600U, 25420U, 10630U, 12414U, 14773U, 25698U,
10872	24889U, 20307U, 10589U, 12249U, 14663U, 18997U, 25499U, 22278U,	10872	24889U, 20307U, 10589U, 12249U, 14663U, 18997U, 25499U, 22278U,
10873	19148U, 7074U, 10839U, 12848U, 15048U, 26257U, 10242U, 13969U,	10873	19148U, 7074U, 10839U, 12848U, 15048U, 26257U, 10242U, 13969U,
10874	1442U, 14084U, 1495U, 25772U, 1854U, 25336U, 1828U, 14042U,	10874	1442U, 14084U, 1495U, 25772U, 1854U, 25336U, 1828U, 14042U,
10875	18357U, 14147U, 18446U, 26012U, 20616U, 10948U, 13015U, 15204U,	10875	18357U, 14147U, 18446U, 26012U, 20616U, 10948U, 13015U, 15204U,
10876	26424U, 10772U, 12686U, 14971U, 26125U, 10738U, 12632U, 14937U,	10876	26424U, 10772U, 12686U, 14971U, 26125U, 10738U, 12632U, 14937U,
10877	26057U, 10930U, 12997U, 15186U, 26406U, 17525U, 5734U, 9960U,	10877	26057U, 10930U, 12997U, 15186U, 26406U, 17525U, 5734U, 9960U,
10878	1244U, 10068U, 1305U, 7831U, 14234U, 1586U, 10173U, 17848U,	10878	1244U, 10068U, 1305U, 7831U, 14234U, 1586U, 10173U, 17848U,
10879	14187U, 1556U, 10111U, 17793U, 10545U, 12198U, 14634U, 25454U,	10879	14187U, 1556U, 10111U, 17793U, 10545U, 12198U, 14634U, 25454U,
10880	11001U, 13079U, 15257U, 26497U, 17929U, 5816U, 27868U, 20835U,	10880	11001U, 13079U, 15257U, 26497U, 17929U, 5816U, 27868U, 20835U,
10881	180U, 1986U, 16353U, 25023U, 17562U, 5758U, 3496U, 157U,	10881	180U, 1986U, 16353U, 25023U, 17562U, 5758U, 3496U, 157U,
10882	16336U, 1182U, 5479U, 8035U, 1928U, 22383U, 19197U, 13523U,	10882	16336U, 1182U, 5479U, 8035U, 1928U, 22383U, 19197U, 13523U,
10883	18165U, 16145U, 3277U, 13375U, 18111U, 19018U, 17439U, 5688U,	10883	18165U, 16145U, 3277U, 13375U, 18111U, 19018U, 17439U, 5688U,
10884	16868U, 19371U, 23218U, 3347U, 13460U, 18141U, 19635U, 19348U,	10884	16868U, 19371U, 23218U, 3347U, 13460U, 18141U, 19635U, 19348U,
10885	7101U, 192U, 16371U, 20379U, 7931U, 11202U, 15306U, 18626U,	10885	7101U, 192U, 16371U, 20379U, 7931U, 11202U, 15306U, 18626U,
10886	6873U, 17950U, 5973U, 15863U, 18979U, 4829U, 4192U, 4290U,	10886	6873U, 17950U, 5973U, 15863U, 18979U, 4829U, 4192U, 4290U,
10887	4996U, 5012U, 4322U, 4260U, 5151U, 5065U, 4906U, 4534U,	10887	4996U, 5012U, 4322U, 4260U, 5151U, 5065U, 4906U, 4534U,
10888	4918U, 4561U, 5096U, 4174U, 5130U, 4267U, 5162U, 5221U,	10888	4918U, 4561U, 5096U, 4174U, 5130U, 4267U, 5162U, 5221U,
10889	4407U, 4466U, 22636U, 15379U, 18695U, 19385U, 13317U, 15315U,	10889	4407U, 4466U, 22636U, 15379U, 18695U, 19385U, 13317U, 15315U,
10890	24718U, 20232U, 18641U, 24697U, 20224U, 18066U, 24901U, 13645U,	10890	24718U, 20232U, 18641U, 24697U, 20224U, 18066U, 24901U, 13645U,
10891	18204U, 20315U, 22251U, 19121U, 22869U, 19491U, 15429U, 18720U,	10891	18204U, 20315U, 22251U, 19121U, 22869U, 19491U, 15429U, 18720U,
10892	23201U, 19609U, 24894U, 13637U, 6816U, 7911U, 22221U, 19094U,	10892	23201U, 19609U, 24894U, 13637U, 6816U, 7911U, 22221U, 19094U,
10893	22640U, 19392U, 15423U, 18711U, 23195U, 19600U, 24336U, 15398U,	10893	22640U, 19392U, 15423U, 18711U, 23195U, 19600U, 24336U, 15398U,
10894	20241U, 18703U, 24766U, 20250U, 20166U, 13404U, 15320U, 18649U,	10894	20241U, 18703U, 24766U, 20250U, 20166U, 13404U, 15320U, 18649U,
10895	18126U, 2433U, 6405U, 23678U, 7389U, 680U, 2714U, 6674U,	10895	18126U, 2433U, 6405U, 23678U, 7389U, 680U, 2714U, 6674U,
10896	20411U, 23998U, 20072U, 7670U, 24724U, 24859U, 20291U, 24731U,	10896	20411U, 23998U, 20072U, 7670U, 24724U, 24859U, 20291U, 24731U,
10897	61U, 24744U, 10400U, 12074U, 14518U, 25263U, 24251U, 20151U,	10897	61U, 24744U, 10400U, 12074U, 14518U, 25263U, 24251U, 20151U,
10898	7792U, 22357U, 19179U, 7159U, 13871U, 18231U, 6846U, 23052U,	10898	7792U, 22357U, 19179U, 7159U, 13871U, 18231U, 6846U, 23052U,
10899	17487U, 5712U, 3327U, 10512U, 6902U, 19585U, 7138U, 24968U,	10899	17487U, 5712U, 3327U, 10512U, 6902U, 19585U, 7138U, 24968U,
10900	27007U, 3688U, 20805U, 5196U, 11599U,	10900	27007U, 3688U, 20805U, 5196U, 11599U,
10901	};	10901	};
10902		10902
10903	static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {	10903	static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {
10904	II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	10904	II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);
10905	}	10905	}
10906		10906
10907	} // end namespace llvm	10907	} // end namespace llvm
10908	#endif // GET_INSTRINFO_MC_DESC	10908	#endif // GET_INSTRINFO_MC_DESC
10909		10909
10910	#ifdef GET_INSTRINFO_HEADER	10910	#ifdef GET_INSTRINFO_HEADER
10911	#undef GET_INSTRINFO_HEADER	10911	#undef GET_INSTRINFO_HEADER
10912	namespace llvm {	10912	namespace llvm {
10913	struct MipsGenInstrInfo : public TargetInstrInfo {	10913	struct MipsGenInstrInfo : public TargetInstrInfo {
10914	explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);	10914	explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
10915	~MipsGenInstrInfo() override = default;	10915	~MipsGenInstrInfo() override = default;
10916		10916
10917	};	10917	};
10918	} // end namespace llvm	10918	} // end namespace llvm
10919	#endif // GET_INSTRINFO_HEADER	10919	#endif // GET_INSTRINFO_HEADER
10920		10920
10921	#ifdef GET_INSTRINFO_HELPER_DECLS	10921	#ifdef GET_INSTRINFO_HELPER_DECLS
10922	#undef GET_INSTRINFO_HELPER_DECLS	10922	#undef GET_INSTRINFO_HELPER_DECLS
10923		10923
10924		10924
10925	#endif // GET_INSTRINFO_HELPER_DECLS	10925	#endif // GET_INSTRINFO_HELPER_DECLS
10926		10926
10927	#ifdef GET_INSTRINFO_HELPERS	10927	#ifdef GET_INSTRINFO_HELPERS
10928	#undef GET_INSTRINFO_HELPERS	10928	#undef GET_INSTRINFO_HELPERS
10929		10929
10930	#endif // GET_INSTRINFO_HELPERS	10930	#endif // GET_INSTRINFO_HELPERS
10931		10931
10932	#ifdef GET_INSTRINFO_CTOR_DTOR	10932	#ifdef GET_INSTRINFO_CTOR_DTOR
10933	#undef GET_INSTRINFO_CTOR_DTOR	10933	#undef GET_INSTRINFO_CTOR_DTOR
10934	namespace llvm {	10934	namespace llvm {
10935	extern const MipsInstrTable MipsDescs;	10935	extern const MipsInstrTable MipsDescs;
10936	extern const unsigned MipsInstrNameIndices[];	10936	extern const unsigned MipsInstrNameIndices[];
10937	extern const char MipsInstrNameData[];	10937	extern const char MipsInstrNameData[];
10938	MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)	10938	MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
10939	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {	10939	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
10940	InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	10940	InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);
10941	}	10941	}
10942	} // end namespace llvm	10942	} // end namespace llvm
10943	#endif // GET_INSTRINFO_CTOR_DTOR	10943	#endif // GET_INSTRINFO_CTOR_DTOR
10944		10944
10945	#ifdef GET_INSTRINFO_OPERAND_ENUM	10945	#ifdef GET_INSTRINFO_OPERAND_ENUM
10946	#undef GET_INSTRINFO_OPERAND_ENUM	10946	#undef GET_INSTRINFO_OPERAND_ENUM
10947	namespace llvm {	10947	namespace llvm {
10948	namespace Mips {	10948	namespace Mips {
10949	namespace OpName {	10949	namespace OpName {
10950	enum {	10950	enum {
10951	OPERAND_LAST	10951	OPERAND_LAST
10952	};	10952	};
10953	} // end namespace OpName	10953	} // end namespace OpName
10954	} // end namespace Mips	10954	} // end namespace Mips
10955	} // end namespace llvm	10955	} // end namespace llvm
10956	#endif //GET_INSTRINFO_OPERAND_ENUM	10956	#endif //GET_INSTRINFO_OPERAND_ENUM
10957		10957
10958	#ifdef GET_INSTRINFO_NAMED_OPS	10958	#ifdef GET_INSTRINFO_NAMED_OPS
10959	#undef GET_INSTRINFO_NAMED_OPS	10959	#undef GET_INSTRINFO_NAMED_OPS
10960	namespace llvm {	10960	namespace llvm {
10961	namespace Mips {	10961	namespace Mips {
10962	LLVM_READONLY	10962	LLVM_READONLY
10963	int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {	10963	int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
10964	return -1;	10964	return -1;
10965	}	10965	}
10966	} // end namespace Mips	10966	} // end namespace Mips
10967	} // end namespace llvm	10967	} // end namespace llvm
10968	#endif //GET_INSTRINFO_NAMED_OPS	10968	#endif //GET_INSTRINFO_NAMED_OPS
10969		10969
10970	#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM	10970	#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
10971	#undef GET_INSTRINFO_OPERAND_TYPES_ENUM	10971	#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
10972	namespace llvm {	10972	namespace llvm {
10973	namespace Mips {	10973	namespace Mips {
10974	namespace OpTypes {	10974	namespace OpTypes {
10975	enum OperandType {	10975	enum OperandType {
10976	InvertedImOperand = 0,	10976	InvertedImOperand = 0,
10977	InvertedImOperand64 = 1,	10977	InvertedImOperand64 = 1,
10978	PtrRC = 2,	10978	PtrRC = 2,
10979	brtarget = 3,	10979	brtarget = 3,
10980	brtarget1SImm16 = 4,	10980	brtarget1SImm16 = 4,
10981	brtarget7_mm = 5,	10981	brtarget7_mm = 5,
10982	brtarget10_mm = 6,	10982	brtarget10_mm = 6,
10983	brtarget21 = 7,	10983	brtarget21 = 7,
10984	brtarget21_mm = 8,	10984	brtarget21_mm = 8,
10985	brtarget26 = 9,	10985	brtarget26 = 9,
10986	brtarget26_mm = 10,	10986	brtarget26_mm = 10,
10987	brtarget_lsl2_mm = 11,	10987	brtarget_lsl2_mm = 11,
10988	brtarget_mm = 12,	10988	brtarget_mm = 12,
10989	brtargetr6 = 13,	10989	brtargetr6 = 13,
10990	calloffset16 = 14,	10990	calloffset16 = 14,
10991	calltarget = 15,	10991	calltarget = 15,
10992	calltarget_mm = 16,	10992	calltarget_mm = 16,
10993	condcode = 17,	10993	condcode = 17,
10994	cpinst_operand = 18,	10994	cpinst_operand = 18,
10995	f32imm = 19,	10995	f32imm = 19,
10996	f64imm = 20,	10996	f64imm = 20,
10997	i1imm = 21,	10997	i1imm = 21,
10998	i8imm = 22,	10998	i8imm = 22,
10999	i16imm = 23,	10999	i16imm = 23,
11000	i32imm = 24,	11000	i32imm = 24,
11001	i64imm = 25,	11001	i64imm = 25,
11002	imm64 = 26,	11002	imm64 = 26,
11003	jmpoffset16 = 27,	11003	jmpoffset16 = 27,
11004	jmptarget = 28,	11004	jmptarget = 28,
11005	jmptarget_mm = 29,	11005	jmptarget_mm = 29,
11006	li16_imm = 30,	11006	li16_imm = 30,
11007	mem = 31,	11007	mem = 31,
11008	mem16 = 32,	11008	mem16 = 32,
11009	mem16_ea = 33,	11009	mem16_ea = 33,
11010	mem16sp = 34,	11010	mem16sp = 34,
11011	mem_ea = 35,	11011	mem_ea = 35,
11012	mem_mm_4 = 36,	11012	mem_mm_4 = 36,
11013	mem_mm_4_lsl1 = 37,	11013	mem_mm_4_lsl1 = 37,
11014	mem_mm_4_lsl2 = 38,	11014	mem_mm_4_lsl2 = 38,
11015	mem_mm_4sp = 39,	11015	mem_mm_4sp = 39,
11016	mem_mm_9 = 40,	11016	mem_mm_9 = 40,
11017	mem_mm_11 = 41,	11017	mem_mm_11 = 41,
11018	mem_mm_12 = 42,	11018	mem_mm_12 = 42,
11019	mem_mm_16 = 43,	11019	mem_mm_16 = 43,
11020	mem_mm_gp_simm7_lsl2 = 44,	11020	mem_mm_gp_simm7_lsl2 = 44,
11021	mem_mm_sp_imm5_lsl2 = 45,	11021	mem_mm_sp_imm5_lsl2 = 45,
11022	mem_msa = 46,	11022	mem_msa = 46,
11023	mem_simm9 = 47,	11023	mem_simm9 = 47,
11024	mem_simm9_exp = 48,	11024	mem_simm9_exp = 48,
11025	mem_simm10 = 49,	11025	mem_simm10 = 49,
11026	mem_simm10_lsl1 = 50,	11026	mem_simm10_lsl1 = 50,
11027	mem_simm10_lsl2 = 51,	11027	mem_simm10_lsl2 = 51,
11028	mem_simm10_lsl3 = 52,	11028	mem_simm10_lsl3 = 52,
11029	mem_simm11 = 53,	11029	mem_simm11 = 53,
11030	mem_simm12 = 54,	11030	mem_simm12 = 54,
11031	mem_simm16 = 55,	11031	mem_simm16 = 55,
11032	mem_simmptr = 56,	11032	mem_simmptr = 56,
11033	pcrel16 = 57,	11033	pcrel16 = 57,
11034	ptype0 = 58,	11034	ptype0 = 58,
11035	ptype1 = 59,	11035	ptype1 = 59,
11036	ptype2 = 60,	11036	ptype2 = 60,
11037	ptype3 = 61,	11037	ptype3 = 61,
11038	ptype4 = 62,	11038	ptype4 = 62,
11039	ptype5 = 63,	11039	ptype5 = 63,
11040	reglist = 64,	11040	reglist = 64,
11041	reglist16 = 65,	11041	reglist16 = 65,
11042	simm3_lsa2 = 66,	11042	simm3_lsa2 = 66,
11043	simm4 = 67,	11043	simm4 = 67,
11044	simm5 = 68,	11044	simm5 = 68,
11045	simm6 = 69,	11045	simm6 = 69,
11046	simm7_lsl2 = 70,	11046	simm7_lsl2 = 70,
11047	simm9 = 71,	11047	simm9 = 71,
11048	simm9_addiusp = 72,	11048	simm9_addiusp = 72,
11049	simm10 = 73,	11049	simm10 = 73,
11050	simm10_64 = 74,	11050	simm10_64 = 74,
11051	simm10_lsl1 = 75,	11051	simm10_lsl1 = 75,
11052	simm10_lsl2 = 76,	11052	simm10_lsl2 = 76,
11053	simm10_lsl3 = 77,	11053	simm10_lsl3 = 77,
11054	simm11 = 78,	11054	simm11 = 78,
11055	simm12 = 79,	11055	simm12 = 79,
11056	simm16 = 80,	11056	simm16 = 80,
11057	simm16_64 = 81,	11057	simm16_64 = 81,
11058	simm16_relaxed = 82,	11058	simm16_relaxed = 82,
11059	simm18_lsl3 = 83,	11059	simm18_lsl3 = 83,
11060	simm19_lsl2 = 84,	11060	simm19_lsl2 = 84,
11061	simm23_lsl2 = 85,	11061	simm23_lsl2 = 85,
11062	simm32 = 86,	11062	simm32 = 86,
11063	simm32_relaxed = 87,	11063	simm32_relaxed = 87,
11064	size_ins = 88,	11064	size_ins = 88,
11065	type0 = 89,	11065	type0 = 89,
11066	type1 = 90,	11066	type1 = 90,
11067	type2 = 91,	11067	type2 = 91,
11068	type3 = 92,	11068	type3 = 92,
11069	type4 = 93,	11069	type4 = 93,
11070	type5 = 94,	11070	type5 = 94,
11071	uimm1 = 95,	11071	uimm1 = 95,
11072	uimm1_ptr = 96,	11072	uimm1_ptr = 96,
11073	uimm2 = 97,	11073	uimm2 = 97,
11074	uimm2_plus1 = 98,	11074	uimm2_plus1 = 98,
11075	uimm2_ptr = 99,	11075	uimm2_ptr = 99,
11076	uimm3 = 100,	11076	uimm3 = 100,
11077	uimm3_ptr = 101,	11077	uimm3_ptr = 101,
11078	uimm3_shift = 102,	11078	uimm3_shift = 102,
11079	uimm4 = 103,	11079	uimm4 = 103,
11080	uimm4_andi = 104,	11080	uimm4_andi = 104,
11081	uimm4_ptr = 105,	11081	uimm4_ptr = 105,
11082	uimm5 = 106,	11082	uimm5 = 106,
11083	uimm5_64 = 107,	11083	uimm5_64 = 107,
11084	uimm5_64_report_uimm6 = 108,	11084	uimm5_64_report_uimm6 = 108,
11085	uimm5_inssize_plus1 = 109,	11085	uimm5_inssize_plus1 = 109,
11086	uimm5_lsl2 = 110,	11086	uimm5_lsl2 = 110,
11087	uimm5_plus1 = 111,	11087	uimm5_plus1 = 111,
11088	uimm5_plus1_report_uimm6 = 112,	11088	uimm5_plus1_report_uimm6 = 112,
11089	uimm5_plus32 = 113,	11089	uimm5_plus32 = 113,
11090	uimm5_plus32_normalize = 114,	11090	uimm5_plus32_normalize = 114,
11091	uimm5_plus32_normalize_64 = 115,	11091	uimm5_plus32_normalize_64 = 115,
11092	uimm5_plus33 = 116,	11092	uimm5_plus33 = 116,
11093	uimm5_report_uimm6 = 117,	11093	uimm5_report_uimm6 = 117,
11094	uimm6 = 118,	11094	uimm6 = 118,
11095	uimm6_lsl2 = 119,	11095	uimm6_lsl2 = 119,
11096	uimm7 = 120,	11096	uimm7 = 120,
11097	uimm8 = 121,	11097	uimm8 = 121,
11098	uimm10 = 122,	11098	uimm10 = 122,
11099	uimm16 = 123,	11099	uimm16 = 123,
11100	uimm16_64 = 124,	11100	uimm16_64 = 124,
11101	uimm16_64_relaxed = 125,	11101	uimm16_64_relaxed = 125,
11102	uimm16_altrelaxed = 126,	11102	uimm16_altrelaxed = 126,
11103	uimm16_relaxed = 127,	11103	uimm16_relaxed = 127,
11104	uimm20 = 128,	11104	uimm20 = 128,
11105	uimm26 = 129,	11105	uimm26 = 129,
11106	uimm32_coerced = 130,	11106	uimm32_coerced = 130,
11107	uimm_range_2_64 = 131,	11107	uimm_range_2_64 = 131,
11108	uimmz = 132,	11108	uimmz = 132,
11109	untyped_imm_0 = 133,	11109	untyped_imm_0 = 133,
11110	vsplat_simm5 = 134,	11110	vsplat_simm5 = 134,
11111	vsplat_simm10 = 135,	11111	vsplat_simm10 = 135,
11112	vsplat_uimm1 = 136,	11112	vsplat_uimm1 = 136,
11113	vsplat_uimm2 = 137,	11113	vsplat_uimm2 = 137,
11114	vsplat_uimm3 = 138,	11114	vsplat_uimm3 = 138,
11115	vsplat_uimm4 = 139,	11115	vsplat_uimm4 = 139,
11116	vsplat_uimm5 = 140,	11116	vsplat_uimm5 = 140,
11117	vsplat_uimm6 = 141,	11117	vsplat_uimm6 = 141,
11118	vsplat_uimm8 = 142,	11118	vsplat_uimm8 = 142,
11119	ACC64DSPOpnd = 143,	11119	ACC64DSPOpnd = 143,
11120	AFGR64Opnd = 144,	11120	AFGR64Opnd = 144,
11121	CCROpnd = 145,	11121	CCROpnd = 145,
11122	COP0Opnd = 146,	11122	COP0Opnd = 146,
11123	COP2Opnd = 147,	11123	COP2Opnd = 147,
11124	COP3Opnd = 148,	11124	COP3Opnd = 148,
11125	DSPROpnd = 149,	11125	DSPROpnd = 149,
11126	FCCRegsOpnd = 150,	11126	FCCRegsOpnd = 150,
11127	FGR32Opnd = 151,	11127	FGR32Opnd = 151,
11128	FGR64Opnd = 152,	11128	FGR64Opnd = 152,
11129	FGRCCOpnd = 153,	11129	FGRCCOpnd = 153,
11130	GPR32NonZeroOpnd = 154,	11130	GPR32NonZeroOpnd = 154,
11131	GPR32Opnd = 155,	11131	GPR32Opnd = 155,
11132	GPR32ZeroOpnd = 156,	11132	GPR32ZeroOpnd = 156,
11133	GPR64Opnd = 157,	11133	GPR64Opnd = 157,
11134	GPRMM16Opnd = 158,	11134	GPRMM16Opnd = 158,
11135	GPRMM16OpndMoveP = 159,	11135	GPRMM16OpndMoveP = 159,
11136	GPRMM16OpndMovePPairFirst = 160,	11136	GPRMM16OpndMovePPairFirst = 160,
11137	GPRMM16OpndMovePPairSecond = 161,	11137	GPRMM16OpndMovePPairSecond = 161,
11138	GPRMM16OpndZero = 162,	11138	GPRMM16OpndZero = 162,
11139	HI32DSPOpnd = 163,	11139	HI32DSPOpnd = 163,
11140	HWRegsOpnd = 164,	11140	HWRegsOpnd = 164,
11141	LO32DSPOpnd = 165,	11141	LO32DSPOpnd = 165,
11142	MSA128BOpnd = 166,	11142	MSA128BOpnd = 166,
11143	MSA128CROpnd = 167,	11143	MSA128CROpnd = 167,
11144	MSA128DOpnd = 168,	11144	MSA128DOpnd = 168,
11145	MSA128F16Opnd = 169,	11145	MSA128F16Opnd = 169,
11146	MSA128HOpnd = 170,	11146	MSA128HOpnd = 170,
11147	MSA128WOpnd = 171,	11147	MSA128WOpnd = 171,
11148	StrictlyAFGR64Opnd = 172,	11148	StrictlyAFGR64Opnd = 172,
11149	StrictlyFGR32Opnd = 173,	11149	StrictlyFGR32Opnd = 173,
11150	StrictlyFGR64Opnd = 174,	11150	StrictlyFGR64Opnd = 174,
11151	ACC64 = 175,	11151	ACC64 = 175,
11152	ACC64DSP = 176,	11152	ACC64DSP = 176,
11153	ACC128 = 177,	11153	ACC128 = 177,
11154	AFGR64 = 178,	11154	AFGR64 = 178,
11155	CCR = 179,	11155	CCR = 179,
11156	COP0 = 180,	11156	COP0 = 180,
11157	COP2 = 181,	11157	COP2 = 181,
11158	COP3 = 182,	11158	COP3 = 182,
11159	CPU16Regs = 183,	11159	CPU16Regs = 183,
11160	CPU16RegsPlusSP = 184,	11160	CPU16RegsPlusSP = 184,
11161	CPURAReg = 185,	11161	CPURAReg = 185,
11162	CPUSPReg = 186,	11162	CPUSPReg = 186,
11163	DSPCC = 187,	11163	DSPCC = 187,
11164	DSPR = 188,	11164	DSPR = 188,
11165	FCC = 189,	11165	FCC = 189,
11166	FGR32 = 190,	11166	FGR32 = 190,
11167	FGR64 = 191,	11167	FGR64 = 191,
11168	FGRCC = 192,	11168	FGRCC = 192,
11169	GP32 = 193,	11169	GP32 = 193,
11170	GP64 = 194,	11170	GP64 = 194,
11171	GPR32 = 195,	11171	GPR32 = 195,
11172	GPR32NONZERO = 196,	11172	GPR32NONZERO = 196,
11173	GPR32ZERO = 197,	11173	GPR32ZERO = 197,
11174	GPR64 = 198,	11174	GPR64 = 198,
11175	GPRMM16 = 199,	11175	GPRMM16 = 199,
11176	GPRMM16MoveP = 200,	11176	GPRMM16MoveP = 200,
11177	GPRMM16MovePPairFirst = 201,	11177	GPRMM16MovePPairFirst = 201,
11178	GPRMM16MovePPairSecond = 202,	11178	GPRMM16MovePPairSecond = 202,
11179	GPRMM16Zero = 203,	11179	GPRMM16Zero = 203,
11180	HI32 = 204,	11180	HI32 = 204,
11181	HI32DSP = 205,	11181	HI32DSP = 205,
11182	HI64 = 206,	11182	HI64 = 206,
11183	HWRegs = 207,	11183	HWRegs = 207,
11184	LO32 = 208,	11184	LO32 = 208,
11185	LO32DSP = 209,	11185	LO32DSP = 209,
11186	LO64 = 210,	11186	LO64 = 210,
11187	MSA128B = 211,	11187	MSA128B = 211,
11188	MSA128D = 212,	11188	MSA128D = 212,
11189	MSA128F16 = 213,	11189	MSA128F16 = 213,
11190	MSA128H = 214,	11190	MSA128H = 214,
11191	MSA128W = 215,	11191	MSA128W = 215,
11192	MSA128WEvens = 216,	11192	MSA128WEvens = 216,
11193	MSACtrl = 217,	11193	MSACtrl = 217,
11194	OCTEON_MPL = 218,	11194	OCTEON_MPL = 218,
11195	OCTEON_P = 219,	11195	OCTEON_P = 219,
11196	SP32 = 220,	11196	SP32 = 220,
11197	SP64 = 221,	11197	SP64 = 221,
11198	OPERAND_TYPE_LIST_END	11198	OPERAND_TYPE_LIST_END
11199	};	11199	};
11200	} // end namespace OpTypes	11200	} // end namespace OpTypes
11201	} // end namespace Mips	11201	} // end namespace Mips
11202	} // end namespace llvm	11202	} // end namespace llvm
11203	#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM	11203	#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
11204		11204
11205	#ifdef GET_INSTRINFO_OPERAND_TYPE	11205	#ifdef GET_INSTRINFO_OPERAND_TYPE
11206	#undef GET_INSTRINFO_OPERAND_TYPE	11206	#undef GET_INSTRINFO_OPERAND_TYPE
11207	namespace llvm {	11207	namespace llvm {
11208	namespace Mips {	11208	namespace Mips {
11209	LLVM_READONLY	11209	LLVM_READONLY
11210	static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {	11210	static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
11211	static const uint16_t Offsets[] = {	11211	static const uint16_t Offsets[] = {
11212	/* PHI */	11212	/* PHI */
11213	0,	11213	0,
11214	/* INLINEASM */	11214	/* INLINEASM */
11215	1,	11215	1,
11216	/* INLINEASM_BR */	11216	/* INLINEASM_BR */
11217	1,	11217	1,
11218	/* CFI_INSTRUCTION */	11218	/* CFI_INSTRUCTION */
11219	1,	11219	1,
11220	/* EH_LABEL */	11220	/* EH_LABEL */
11221	2,	11221	2,
11222	/* GC_LABEL */	11222	/* GC_LABEL */
11223	3,	11223	3,
11224	/* ANNOTATION_LABEL */	11224	/* ANNOTATION_LABEL */
11225	4,	11225	4,
11226	/* KILL */	11226	/* KILL */
11227	5,	11227	5,
11228	/* EXTRACT_SUBREG */	11228	/* EXTRACT_SUBREG */
11229	5,	11229	5,
11230	/* INSERT_SUBREG */	11230	/* INSERT_SUBREG */
11231	8,	11231	8,
11232	/* IMPLICIT_DEF */	11232	/* IMPLICIT_DEF */
11233	12,	11233	12,
11234	/* SUBREG_TO_REG */	11234	/* SUBREG_TO_REG */
11235	13,	11235	13,
11236	/* COPY_TO_REGCLASS */	11236	/* COPY_TO_REGCLASS */
11237	17,	11237	17,
11238	/* DBG_VALUE */	11238	/* DBG_VALUE */
11239	20,	11239	20,
11240	/* DBG_VALUE_LIST */	11240	/* DBG_VALUE_LIST */
11241	20,	11241	20,
11242	/* DBG_INSTR_REF */	11242	/* DBG_INSTR_REF */
11243	20,	11243	20,
11244	/* DBG_PHI */	11244	/* DBG_PHI */
11245	20,	11245	20,
11246	/* DBG_LABEL */	11246	/* DBG_LABEL */
11247	20,	11247	20,
11248	/* REG_SEQUENCE */	11248	/* REG_SEQUENCE */
11249	21,	11249	21,
11250	/* COPY */	11250	/* COPY */
11251	23,	11251	23,
11252	/* BUNDLE */	11252	/* BUNDLE */
11253	25,	11253	25,
11254	/* LIFETIME_START */	11254	/* LIFETIME_START */
11255	25,	11255	25,
11256	/* LIFETIME_END */	11256	/* LIFETIME_END */
11257	26,	11257	26,
11258	/* PSEUDO_PROBE */	11258	/* PSEUDO_PROBE */
11259	27,	11259	27,
11260	/* ARITH_FENCE */	11260	/* ARITH_FENCE */
11261	31,	11261	31,
11262	/* STACKMAP */	11262	/* STACKMAP */
11263	33,	11263	33,
11264	/* FENTRY_CALL */	11264	/* FENTRY_CALL */
11265	35,	11265	35,
11266	/* PATCHPOINT */	11266	/* PATCHPOINT */
11267	35,	11267	35,
11268	/* LOAD_STACK_GUARD */	11268	/* LOAD_STACK_GUARD */
11269	41,	11269	41,
11270	/* PREALLOCATED_SETUP */	11270	/* PREALLOCATED_SETUP */
11271	42,	11271	42,
11272	/* PREALLOCATED_ARG */	11272	/* PREALLOCATED_ARG */
11273	43,	11273	43,
11274	/* STATEPOINT */	11274	/* STATEPOINT */
11275	46,	11275	46,
11276	/* LOCAL_ESCAPE */	11276	/* LOCAL_ESCAPE */
11277	46,	11277	46,
11278	/* FAULTING_OP */	11278	/* FAULTING_OP */
11279	48,	11279	48,
11280	/* PATCHABLE_OP */	11280	/* PATCHABLE_OP */
11281	49,	11281	49,
11282	/* PATCHABLE_FUNCTION_ENTER */	11282	/* PATCHABLE_FUNCTION_ENTER */
11283	49,	11283	49,
11284	/* PATCHABLE_RET */	11284	/* PATCHABLE_RET */
11285	49,	11285	49,
11286	/* PATCHABLE_FUNCTION_EXIT */	11286	/* PATCHABLE_FUNCTION_EXIT */
11287	49,	11287	49,
11288	/* PATCHABLE_TAIL_CALL */	11288	/* PATCHABLE_TAIL_CALL */
11289	49,	11289	49,
11290	/* PATCHABLE_EVENT_CALL */	11290	/* PATCHABLE_EVENT_CALL */
11291	49,	11291	49,
11292	/* PATCHABLE_TYPED_EVENT_CALL */	11292	/* PATCHABLE_TYPED_EVENT_CALL */
11293	51,	11293	51,
11294	/* ICALL_BRANCH_FUNNEL */	11294	/* ICALL_BRANCH_FUNNEL */
11295	54,	11295	54,
11296	/* MEMBARRIER */	11296	/* MEMBARRIER */
11297	54,	11297	54,
11298	/* G_ASSERT_SEXT */	11298	/* G_ASSERT_SEXT */
11299	54,	11299	54,
11300	/* G_ASSERT_ZEXT */	11300	/* G_ASSERT_ZEXT */
11301	57,	11301	57,
11302	/* G_ASSERT_ALIGN */	11302	/* G_ASSERT_ALIGN */
11303	60,	11303	60,
11304	/* G_ADD */	11304	/* G_ADD */
11305	63,	11305	63,
11306	/* G_SUB */	11306	/* G_SUB */
11307	66,	11307	66,
11308	/* G_MUL */	11308	/* G_MUL */
11309	69,	11309	69,
11310	/* G_SDIV */	11310	/* G_SDIV */
11311	72,	11311	72,
11312	/* G_UDIV */	11312	/* G_UDIV */
11313	75,	11313	75,
11314	/* G_SREM */	11314	/* G_SREM */
11315	78,	11315	78,
11316	/* G_UREM */	11316	/* G_UREM */
11317	81,	11317	81,
11318	/* G_SDIVREM */	11318	/* G_SDIVREM */
11319	84,	11319	84,
11320	/* G_UDIVREM */	11320	/* G_UDIVREM */
11321	88,	11321	88,
11322	/* G_AND */	11322	/* G_AND */
11323	92,	11323	92,
11324	/* G_OR */	11324	/* G_OR */
11325	95,	11325	95,
11326	/* G_XOR */	11326	/* G_XOR */
11327	98,	11327	98,
11328	/* G_IMPLICIT_DEF */	11328	/* G_IMPLICIT_DEF */
11329	101,	11329	101,
11330	/* G_PHI */	11330	/* G_PHI */
11331	102,	11331	102,
11332	/* G_FRAME_INDEX */	11332	/* G_FRAME_INDEX */
11333	103,	11333	103,
11334	/* G_GLOBAL_VALUE */	11334	/* G_GLOBAL_VALUE */
11335	105,	11335	105,
11336	/* G_CONSTANT_POOL */	11336	/* G_CONSTANT_POOL */
11337	107,	11337	107,
11338	/* G_EXTRACT */	11338	/* G_EXTRACT */
11339	109,	11339	109,
11340	/* G_UNMERGE_VALUES */	11340	/* G_UNMERGE_VALUES */
11341	112,	11341	112,
11342	/* G_INSERT */	11342	/* G_INSERT */
11343	114,	11343	114,
11344	/* G_MERGE_VALUES */	11344	/* G_MERGE_VALUES */
11345	118,	11345	118,
11346	/* G_BUILD_VECTOR */	11346	/* G_BUILD_VECTOR */
11347	120,	11347	120,
11348	/* G_BUILD_VECTOR_TRUNC */	11348	/* G_BUILD_VECTOR_TRUNC */
11349	122,	11349	122,
11350	/* G_CONCAT_VECTORS */	11350	/* G_CONCAT_VECTORS */
11351	124,	11351	124,
11352	/* G_PTRTOINT */	11352	/* G_PTRTOINT */
11353	126,	11353	126,
11354	/* G_INTTOPTR */	11354	/* G_INTTOPTR */
11355	128,	11355	128,
11356	/* G_BITCAST */	11356	/* G_BITCAST */
11357	130,	11357	130,
11358	/* G_FREEZE */	11358	/* G_FREEZE */
11359	132,	11359	132,
11360	/* G_CONSTANT_FOLD_BARRIER */	11360	/* G_CONSTANT_FOLD_BARRIER */
11361	134,	11361	134,
11362	/* G_INTRINSIC_FPTRUNC_ROUND */	11362	/* G_INTRINSIC_FPTRUNC_ROUND */
11363	136,	11363	136,
11364	/* G_INTRINSIC_TRUNC */	11364	/* G_INTRINSIC_TRUNC */
11365	139,	11365	139,
11366	/* G_INTRINSIC_ROUND */	11366	/* G_INTRINSIC_ROUND */
11367	141,	11367	141,
11368	/* G_INTRINSIC_LRINT */	11368	/* G_INTRINSIC_LRINT */
11369	143,	11369	143,
11370	/* G_INTRINSIC_ROUNDEVEN */	11370	/* G_INTRINSIC_ROUNDEVEN */
11371	145,	11371	145,
11372	/* G_READCYCLECOUNTER */	11372	/* G_READCYCLECOUNTER */
11373	147,	11373	147,
11374	/* G_LOAD */	11374	/* G_LOAD */
11375	148,	11375	148,
11376	/* G_SEXTLOAD */	11376	/* G_SEXTLOAD */
11377	150,	11377	150,
11378	/* G_ZEXTLOAD */	11378	/* G_ZEXTLOAD */
11379	152,	11379	152,
11380	/* G_INDEXED_LOAD */	11380	/* G_INDEXED_LOAD */
11381	154,	11381	154,
11382	/* G_INDEXED_SEXTLOAD */	11382	/* G_INDEXED_SEXTLOAD */
11383	159,	11383	159,
11384	/* G_INDEXED_ZEXTLOAD */	11384	/* G_INDEXED_ZEXTLOAD */
11385	164,	11385	164,
11386	/* G_STORE */	11386	/* G_STORE */
11387	169,	11387	169,
11388	/* G_INDEXED_STORE */	11388	/* G_INDEXED_STORE */
11389	171,	11389	171,
11390	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	11390	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
11391	176,	11391	176,
11392	/* G_ATOMIC_CMPXCHG */	11392	/* G_ATOMIC_CMPXCHG */
11393	181,	11393	181,
11394	/* G_ATOMICRMW_XCHG */	11394	/* G_ATOMICRMW_XCHG */
11395	185,	11395	185,
11396	/* G_ATOMICRMW_ADD */	11396	/* G_ATOMICRMW_ADD */
11397	188,	11397	188,
11398	/* G_ATOMICRMW_SUB */	11398	/* G_ATOMICRMW_SUB */
11399	191,	11399	191,
11400	/* G_ATOMICRMW_AND */	11400	/* G_ATOMICRMW_AND */
11401	194,	11401	194,
11402	/* G_ATOMICRMW_NAND */	11402	/* G_ATOMICRMW_NAND */
11403	197,	11403	197,
11404	/* G_ATOMICRMW_OR */	11404	/* G_ATOMICRMW_OR */
11405	200,	11405	200,
11406	/* G_ATOMICRMW_XOR */	11406	/* G_ATOMICRMW_XOR */
11407	203,	11407	203,
11408	/* G_ATOMICRMW_MAX */	11408	/* G_ATOMICRMW_MAX */
11409	206,	11409	206,
11410	/* G_ATOMICRMW_MIN */	11410	/* G_ATOMICRMW_MIN */
11411	209,	11411	209,
11412	/* G_ATOMICRMW_UMAX */	11412	/* G_ATOMICRMW_UMAX */
11413	212,	11413	212,
11414	/* G_ATOMICRMW_UMIN */	11414	/* G_ATOMICRMW_UMIN */
11415	215,	11415	215,
11416	/* G_ATOMICRMW_FADD */	11416	/* G_ATOMICRMW_FADD */
11417	218,	11417	218,
11418	/* G_ATOMICRMW_FSUB */	11418	/* G_ATOMICRMW_FSUB */
11419	221,	11419	221,
11420	/* G_ATOMICRMW_FMAX */	11420	/* G_ATOMICRMW_FMAX */
11421	224,	11421	224,
11422	/* G_ATOMICRMW_FMIN */	11422	/* G_ATOMICRMW_FMIN */
11423	227,	11423	227,
11424	/* G_ATOMICRMW_UINC_WRAP */	11424	/* G_ATOMICRMW_UINC_WRAP */
11425	230,	11425	230,
11426	/* G_ATOMICRMW_UDEC_WRAP */	11426	/* G_ATOMICRMW_UDEC_WRAP */
11427	233,	11427	233,
11428	/* G_FENCE */	11428	/* G_FENCE */
11429	236,	11429	236,
11430	/* G_BRCOND */	11430	/* G_BRCOND */
11431	238,	11431	238,
11432	/* G_BRINDIRECT */	11432	/* G_BRINDIRECT */
11433	240,	11433	240,
11434	/* G_INVOKE_REGION_START */	11434	/* G_INVOKE_REGION_START */
11435	241,	11435	241,
11436	/* G_INTRINSIC */	11436	/* G_INTRINSIC */
11437	241,	11437	241,
11438	/* G_INTRINSIC_W_SIDE_EFFECTS */	11438	/* G_INTRINSIC_W_SIDE_EFFECTS */
11439	242,	11439	242,
11440	/* G_ANYEXT */	11440	/* G_ANYEXT */
11441	243,	11441	243,
11442	/* G_TRUNC */	11442	/* G_TRUNC */
11443	245,	11443	245,
11444	/* G_CONSTANT */	11444	/* G_CONSTANT */
11445	247,	11445	247,
11446	/* G_FCONSTANT */	11446	/* G_FCONSTANT */
11447	249,	11447	249,
11448	/* G_VASTART */	11448	/* G_VASTART */
11449	251,	11449	251,
11450	/* G_VAARG */	11450	/* G_VAARG */
11451	252,	11451	252,
11452	/* G_SEXT */	11452	/* G_SEXT */
11453	255,	11453	255,
11454	/* G_SEXT_INREG */	11454	/* G_SEXT_INREG */
11455	257,	11455	257,
11456	/* G_ZEXT */	11456	/* G_ZEXT */
11457	260,	11457	260,
11458	/* G_SHL */	11458	/* G_SHL */
11459	262,	11459	262,
11460	/* G_LSHR */	11460	/* G_LSHR */
11461	265,	11461	265,
11462	/* G_ASHR */	11462	/* G_ASHR */
11463	268,	11463	268,
11464	/* G_FSHL */	11464	/* G_FSHL */
11465	271,	11465	271,
11466	/* G_FSHR */	11466	/* G_FSHR */
11467	275,	11467	275,
11468	/* G_ROTR */	11468	/* G_ROTR */
11469	279,	11469	279,
11470	/* G_ROTL */	11470	/* G_ROTL */
11471	282,	11471	282,
11472	/* G_ICMP */	11472	/* G_ICMP */
11473	285,	11473	285,
11474	/* G_FCMP */	11474	/* G_FCMP */
11475	289,	11475	289,
11476	/* G_SELECT */	11476	/* G_SELECT */
11477	293,	11477	293,
11478	/* G_UADDO */	11478	/* G_UADDO */
11479	297,	11479	297,
11480	/* G_UADDE */	11480	/* G_UADDE */
11481	301,	11481	301,
11482	/* G_USUBO */	11482	/* G_USUBO */
11483	306,	11483	306,
11484	/* G_USUBE */	11484	/* G_USUBE */
11485	310,	11485	310,
11486	/* G_SADDO */	11486	/* G_SADDO */
11487	315,	11487	315,
11488	/* G_SADDE */	11488	/* G_SADDE */
11489	319,	11489	319,
11490	/* G_SSUBO */	11490	/* G_SSUBO */
11491	324,	11491	324,
11492	/* G_SSUBE */	11492	/* G_SSUBE */
11493	328,	11493	328,
11494	/* G_UMULO */	11494	/* G_UMULO */
11495	333,	11495	333,
11496	/* G_SMULO */	11496	/* G_SMULO */
11497	337,	11497	337,
11498	/* G_UMULH */	11498	/* G_UMULH */
11499	341,	11499	341,
11500	/* G_SMULH */	11500	/* G_SMULH */
11501	344,	11501	344,
11502	/* G_UADDSAT */	11502	/* G_UADDSAT */
11503	347,	11503	347,
11504	/* G_SADDSAT */	11504	/* G_SADDSAT */
11505	350,	11505	350,
11506	/* G_USUBSAT */	11506	/* G_USUBSAT */
11507	353,	11507	353,
11508	/* G_SSUBSAT */	11508	/* G_SSUBSAT */
11509	356,	11509	356,
11510	/* G_USHLSAT */	11510	/* G_USHLSAT */
11511	359,	11511	359,
11512	/* G_SSHLSAT */	11512	/* G_SSHLSAT */
11513	362,	11513	362,
11514	/* G_SMULFIX */	11514	/* G_SMULFIX */
11515	365,	11515	365,
11516	/* G_UMULFIX */	11516	/* G_UMULFIX */
11517	369,	11517	369,
11518	/* G_SMULFIXSAT */	11518	/* G_SMULFIXSAT */
11519	373,	11519	373,
11520	/* G_UMULFIXSAT */	11520	/* G_UMULFIXSAT */
11521	377,	11521	377,
11522	/* G_SDIVFIX */	11522	/* G_SDIVFIX */
11523	381,	11523	381,
11524	/* G_UDIVFIX */	11524	/* G_UDIVFIX */
11525	385,	11525	385,
11526	/* G_SDIVFIXSAT */	11526	/* G_SDIVFIXSAT */
11527	389,	11527	389,
11528	/* G_UDIVFIXSAT */	11528	/* G_UDIVFIXSAT */
11529	393,	11529	393,
11530	/* G_FADD */	11530	/* G_FADD */
11531	397,	11531	397,
11532	/* G_FSUB */	11532	/* G_FSUB */
11533	400,	11533	400,
11534	/* G_FMUL */	11534	/* G_FMUL */
11535	403,	11535	403,
11536	/* G_FMA */	11536	/* G_FMA */
11537	406,	11537	406,
11538	/* G_FMAD */	11538	/* G_FMAD */
11539	410,	11539	410,
11540	/* G_FDIV */	11540	/* G_FDIV */
11541	414,	11541	414,
11542	/* G_FREM */	11542	/* G_FREM */
11543	417,	11543	417,
11544	/* G_FPOW */	11544	/* G_FPOW */
11545	420,	11545	420,
11546	/* G_FPOWI */	11546	/* G_FPOWI */
11547	423,	11547	423,
11548	/* G_FEXP */	11548	/* G_FEXP */
11549	426,	11549	426,
11550	/* G_FEXP2 */	11550	/* G_FEXP2 */
11551	428,	11551	428,
11552	/* G_FLOG */	11552	/* G_FLOG */
11553	430,	11553	430,
11554	/* G_FLOG2 */	11554	/* G_FLOG2 */
11555	432,	11555	432,
11556	/* G_FLOG10 */	11556	/* G_FLOG10 */
11557	434,	11557	434,
11558	/* G_FLDEXP */	11558	/* G_FLDEXP */
11559	436,	11559	436,
11560	/* G_FFREXP */	11560	/* G_FFREXP */
11561	439,	11561	439,
11562	/* G_FNEG */	11562	/* G_FNEG */
11563	442,	11563	442,
11564	/* G_FPEXT */	11564	/* G_FPEXT */
11565	444,	11565	444,
11566	/* G_FPTRUNC */	11566	/* G_FPTRUNC */
11567	446,	11567	446,
11568	/* G_FPTOSI */	11568	/* G_FPTOSI */
11569	448,	11569	448,
11570	/* G_FPTOUI */	11570	/* G_FPTOUI */
11571	450,	11571	450,
11572	/* G_SITOFP */	11572	/* G_SITOFP */
11573	452,	11573	452,
11574	/* G_UITOFP */	11574	/* G_UITOFP */
11575	454,	11575	454,
11576	/* G_FABS */	11576	/* G_FABS */
11577	456,	11577	456,
11578	/* G_FCOPYSIGN */	11578	/* G_FCOPYSIGN */
11579	458,	11579	458,
11580	/* G_IS_FPCLASS */	11580	/* G_IS_FPCLASS */
11581	461,	11581	461,
11582	/* G_FCANONICALIZE */	11582	/* G_FCANONICALIZE */
11583	464,	11583	464,
11584	/* G_FMINNUM */	11584	/* G_FMINNUM */
11585	466,	11585	466,
11586	/* G_FMAXNUM */	11586	/* G_FMAXNUM */
11587	469,	11587	469,
11588	/* G_FMINNUM_IEEE */	11588	/* G_FMINNUM_IEEE */
11589	472,	11589	472,
11590	/* G_FMAXNUM_IEEE */	11590	/* G_FMAXNUM_IEEE */
11591	475,	11591	475,
11592	/* G_FMINIMUM */	11592	/* G_FMINIMUM */
11593	478,	11593	478,
11594	/* G_FMAXIMUM */	11594	/* G_FMAXIMUM */
11595	481,	11595	481,
11596	/* G_PTR_ADD */	11596	/* G_PTR_ADD */
11597	484,	11597	484,
11598	/* G_PTRMASK */	11598	/* G_PTRMASK */
11599	487,	11599	487,
11600	/* G_SMIN */	11600	/* G_SMIN */
11601	490,	11601	490,
11602	/* G_SMAX */	11602	/* G_SMAX */
11603	493,	11603	493,
11604	/* G_UMIN */	11604	/* G_UMIN */
11605	496,	11605	496,
11606	/* G_UMAX */	11606	/* G_UMAX */
11607	499,	11607	499,
11608	/* G_ABS */	11608	/* G_ABS */
11609	502,	11609	502,
11610	/* G_LROUND */	11610	/* G_LROUND */
11611	504,	11611	504,
11612	/* G_LLROUND */	11612	/* G_LLROUND */
11613	506,	11613	506,
11614	/* G_BR */	11614	/* G_BR */
11615	508,	11615	508,
11616	/* G_BRJT */	11616	/* G_BRJT */
11617	509,	11617	509,
11618	/* G_INSERT_VECTOR_ELT */	11618	/* G_INSERT_VECTOR_ELT */
11619	512,	11619	512,
11620	/* G_EXTRACT_VECTOR_ELT */	11620	/* G_EXTRACT_VECTOR_ELT */
11621	516,	11621	516,
11622	/* G_SHUFFLE_VECTOR */	11622	/* G_SHUFFLE_VECTOR */
11623	519,	11623	519,
11624	/* G_CTTZ */	11624	/* G_CTTZ */
11625	523,	11625	523,
11626	/* G_CTTZ_ZERO_UNDEF */	11626	/* G_CTTZ_ZERO_UNDEF */
11627	525,	11627	525,
11628	/* G_CTLZ */	11628	/* G_CTLZ */
11629	527,	11629	527,
11630	/* G_CTLZ_ZERO_UNDEF */	11630	/* G_CTLZ_ZERO_UNDEF */
11631	529,	11631	529,
11632	/* G_CTPOP */	11632	/* G_CTPOP */
11633	531,	11633	531,
11634	/* G_BSWAP */	11634	/* G_BSWAP */
11635	533,	11635	533,
11636	/* G_BITREVERSE */	11636	/* G_BITREVERSE */
11637	535,	11637	535,
11638	/* G_FCEIL */	11638	/* G_FCEIL */
11639	537,	11639	537,
11640	/* G_FCOS */	11640	/* G_FCOS */
11641	539,	11641	539,
11642	/* G_FSIN */	11642	/* G_FSIN */
11643	541,	11643	541,
11644	/* G_FSQRT */	11644	/* G_FSQRT */
11645	543,	11645	543,
11646	/* G_FFLOOR */	11646	/* G_FFLOOR */
11647	545,	11647	545,
11648	/* G_FRINT */	11648	/* G_FRINT */
11649	547,	11649	547,
11650	/* G_FNEARBYINT */	11650	/* G_FNEARBYINT */
11651	549,	11651	549,
11652	/* G_ADDRSPACE_CAST */	11652	/* G_ADDRSPACE_CAST */
11653	551,	11653	551,
11654	/* G_BLOCK_ADDR */	11654	/* G_BLOCK_ADDR */
11655	553,	11655	553,
11656	/* G_JUMP_TABLE */	11656	/* G_JUMP_TABLE */
11657	555,	11657	555,
11658	/* G_DYN_STACKALLOC */	11658	/* G_DYN_STACKALLOC */
11659	557,	11659	557,
11660	/* G_STRICT_FADD */	11660	/* G_STRICT_FADD */
11661	560,	11661	560,
11662	/* G_STRICT_FSUB */	11662	/* G_STRICT_FSUB */
11663	563,	11663	563,
11664	/* G_STRICT_FMUL */	11664	/* G_STRICT_FMUL */
11665	566,	11665	566,
11666	/* G_STRICT_FDIV */	11666	/* G_STRICT_FDIV */
11667	569,	11667	569,
11668	/* G_STRICT_FREM */	11668	/* G_STRICT_FREM */
11669	572,	11669	572,
11670	/* G_STRICT_FMA */	11670	/* G_STRICT_FMA */
11671	575,	11671	575,
11672	/* G_STRICT_FSQRT */	11672	/* G_STRICT_FSQRT */
11673	579,	11673	579,
11674	/* G_STRICT_FLDEXP */	11674	/* G_STRICT_FLDEXP */
11675	581,	11675	581,
11676	/* G_READ_REGISTER */	11676	/* G_READ_REGISTER */
11677	584,	11677	584,
11678	/* G_WRITE_REGISTER */	11678	/* G_WRITE_REGISTER */
11679	586,	11679	586,
11680	/* G_MEMCPY */	11680	/* G_MEMCPY */
11681	588,	11681	588,
11682	/* G_MEMCPY_INLINE */	11682	/* G_MEMCPY_INLINE */
11683	592,	11683	592,
11684	/* G_MEMMOVE */	11684	/* G_MEMMOVE */
11685	595,	11685	595,
11686	/* G_MEMSET */	11686	/* G_MEMSET */
11687	599,	11687	599,
11688	/* G_BZERO */	11688	/* G_BZERO */
11689	603,	11689	603,
11690	/* G_VECREDUCE_SEQ_FADD */	11690	/* G_VECREDUCE_SEQ_FADD */
11691	606,	11691	606,
11692	/* G_VECREDUCE_SEQ_FMUL */	11692	/* G_VECREDUCE_SEQ_FMUL */
11693	609,	11693	609,
11694	/* G_VECREDUCE_FADD */	11694	/* G_VECREDUCE_FADD */
11695	612,	11695	612,
11696	/* G_VECREDUCE_FMUL */	11696	/* G_VECREDUCE_FMUL */
11697	614,	11697	614,
11698	/* G_VECREDUCE_FMAX */	11698	/* G_VECREDUCE_FMAX */
11699	616,	11699	616,
11700	/* G_VECREDUCE_FMIN */	11700	/* G_VECREDUCE_FMIN */
11701	618,	11701	618,
11702	/* G_VECREDUCE_ADD */	11702	/* G_VECREDUCE_ADD */
11703	620,	11703	620,
11704	/* G_VECREDUCE_MUL */	11704	/* G_VECREDUCE_MUL */
11705	622,	11705	622,
11706	/* G_VECREDUCE_AND */	11706	/* G_VECREDUCE_AND */
11707	624,	11707	624,
11708	/* G_VECREDUCE_OR */	11708	/* G_VECREDUCE_OR */
11709	626,	11709	626,
11710	/* G_VECREDUCE_XOR */	11710	/* G_VECREDUCE_XOR */
11711	628,	11711	628,
11712	/* G_VECREDUCE_SMAX */	11712	/* G_VECREDUCE_SMAX */
11713	630,	11713	630,
11714	/* G_VECREDUCE_SMIN */	11714	/* G_VECREDUCE_SMIN */
11715	632,	11715	632,
11716	/* G_VECREDUCE_UMAX */	11716	/* G_VECREDUCE_UMAX */
11717	634,	11717	634,
11718	/* G_VECREDUCE_UMIN */	11718	/* G_VECREDUCE_UMIN */
11719	636,	11719	636,
11720	/* G_SBFX */	11720	/* G_SBFX */
11721	638,	11721	638,
11722	/* G_UBFX */	11722	/* G_UBFX */
11723	642,	11723	642,
11724	/* ABSMacro */	11724	/* ABSMacro */
11725	646,	11725	646,
11726	/* ADJCALLSTACKDOWN */	11726	/* ADJCALLSTACKDOWN */
11727	648,	11727	648,
11728	/* ADJCALLSTACKUP */	11728	/* ADJCALLSTACKUP */
11729	650,	11729	650,
11730	/* AND_V_D_PSEUDO */	11730	/* AND_V_D_PSEUDO */
11731	652,	11731	652,
11732	/* AND_V_H_PSEUDO */	11732	/* AND_V_H_PSEUDO */
11733	655,	11733	655,
11734	/* AND_V_W_PSEUDO */	11734	/* AND_V_W_PSEUDO */
11735	658,	11735	658,
11736	/* ATOMIC_CMP_SWAP_I16 */	11736	/* ATOMIC_CMP_SWAP_I16 */
11737	661,	11737	661,
11738	/* ATOMIC_CMP_SWAP_I16_POSTRA */	11738	/* ATOMIC_CMP_SWAP_I16_POSTRA */
11739	665,	11739	665,
11740	/* ATOMIC_CMP_SWAP_I32 */	11740	/* ATOMIC_CMP_SWAP_I32 */
11741	672,	11741	672,
11742	/* ATOMIC_CMP_SWAP_I32_POSTRA */	11742	/* ATOMIC_CMP_SWAP_I32_POSTRA */
11743	676,	11743	676,
11744	/* ATOMIC_CMP_SWAP_I64 */	11744	/* ATOMIC_CMP_SWAP_I64 */
11745	680,	11745	680,
11746	/* ATOMIC_CMP_SWAP_I64_POSTRA */	11746	/* ATOMIC_CMP_SWAP_I64_POSTRA */
11747	684,	11747	684,
11748	/* ATOMIC_CMP_SWAP_I8 */	11748	/* ATOMIC_CMP_SWAP_I8 */
11749	688,	11749	688,
11750	/* ATOMIC_CMP_SWAP_I8_POSTRA */	11750	/* ATOMIC_CMP_SWAP_I8_POSTRA */
11751	692,	11751	692,
11752	/* ATOMIC_LOAD_ADD_I16 */	11752	/* ATOMIC_LOAD_ADD_I16 */
11753	699,	11753	699,
11754	/* ATOMIC_LOAD_ADD_I16_POSTRA */	11754	/* ATOMIC_LOAD_ADD_I16_POSTRA */
11755	702,	11755	702,
11756	/* ATOMIC_LOAD_ADD_I32 */	11756	/* ATOMIC_LOAD_ADD_I32 */
11757	708,	11757	708,
11758	/* ATOMIC_LOAD_ADD_I32_POSTRA */	11758	/* ATOMIC_LOAD_ADD_I32_POSTRA */
11759	711,	11759	711,
11760	/* ATOMIC_LOAD_ADD_I64 */	11760	/* ATOMIC_LOAD_ADD_I64 */
11761	714,	11761	714,
11762	/* ATOMIC_LOAD_ADD_I64_POSTRA */	11762	/* ATOMIC_LOAD_ADD_I64_POSTRA */
11763	717,	11763	717,
11764	/* ATOMIC_LOAD_ADD_I8 */	11764	/* ATOMIC_LOAD_ADD_I8 */
11765	720,	11765	720,
11766	/* ATOMIC_LOAD_ADD_I8_POSTRA */	11766	/* ATOMIC_LOAD_ADD_I8_POSTRA */
11767	723,	11767	723,
11768	/* ATOMIC_LOAD_AND_I16 */	11768	/* ATOMIC_LOAD_AND_I16 */
11769	729,	11769	729,
11770	/* ATOMIC_LOAD_AND_I16_POSTRA */	11770	/* ATOMIC_LOAD_AND_I16_POSTRA */
11771	732,	11771	732,
11772	/* ATOMIC_LOAD_AND_I32 */	11772	/* ATOMIC_LOAD_AND_I32 */
11773	738,	11773	738,
11774	/* ATOMIC_LOAD_AND_I32_POSTRA */	11774	/* ATOMIC_LOAD_AND_I32_POSTRA */
11775	741,	11775	741,
11776	/* ATOMIC_LOAD_AND_I64 */	11776	/* ATOMIC_LOAD_AND_I64 */
11777	744,	11777	744,
11778	/* ATOMIC_LOAD_AND_I64_POSTRA */	11778	/* ATOMIC_LOAD_AND_I64_POSTRA */
11779	747,	11779	747,
11780	/* ATOMIC_LOAD_AND_I8 */	11780	/* ATOMIC_LOAD_AND_I8 */
11781	750,	11781	750,
11782	/* ATOMIC_LOAD_AND_I8_POSTRA */	11782	/* ATOMIC_LOAD_AND_I8_POSTRA */
11783	753,	11783	753,
11784	/* ATOMIC_LOAD_MAX_I16 */	11784	/* ATOMIC_LOAD_MAX_I16 */
11785	759,	11785	759,
11786	/* ATOMIC_LOAD_MAX_I16_POSTRA */	11786	/* ATOMIC_LOAD_MAX_I16_POSTRA */
11787	762,	11787	762,
11788	/* ATOMIC_LOAD_MAX_I32 */	11788	/* ATOMIC_LOAD_MAX_I32 */
11789	768,	11789	768,
11790	/* ATOMIC_LOAD_MAX_I32_POSTRA */	11790	/* ATOMIC_LOAD_MAX_I32_POSTRA */
11791	771,	11791	771,
11792	/* ATOMIC_LOAD_MAX_I64 */	11792	/* ATOMIC_LOAD_MAX_I64 */
11793	774,	11793	774,
11794	/* ATOMIC_LOAD_MAX_I64_POSTRA */	11794	/* ATOMIC_LOAD_MAX_I64_POSTRA */
11795	777,	11795	777,
11796	/* ATOMIC_LOAD_MAX_I8 */	11796	/* ATOMIC_LOAD_MAX_I8 */
11797	780,	11797	780,
11798	/* ATOMIC_LOAD_MAX_I8_POSTRA */	11798	/* ATOMIC_LOAD_MAX_I8_POSTRA */
11799	783,	11799	783,
11800	/* ATOMIC_LOAD_MIN_I16 */	11800	/* ATOMIC_LOAD_MIN_I16 */
11801	789,	11801	789,
11802	/* ATOMIC_LOAD_MIN_I16_POSTRA */	11802	/* ATOMIC_LOAD_MIN_I16_POSTRA */
11803	792,	11803	792,
11804	/* ATOMIC_LOAD_MIN_I32 */	11804	/* ATOMIC_LOAD_MIN_I32 */
11805	798,	11805	798,
11806	/* ATOMIC_LOAD_MIN_I32_POSTRA */	11806	/* ATOMIC_LOAD_MIN_I32_POSTRA */
11807	801,	11807	801,
11808	/* ATOMIC_LOAD_MIN_I64 */	11808	/* ATOMIC_LOAD_MIN_I64 */
11809	804,	11809	804,
11810	/* ATOMIC_LOAD_MIN_I64_POSTRA */	11810	/* ATOMIC_LOAD_MIN_I64_POSTRA */
11811	807,	11811	807,
11812	/* ATOMIC_LOAD_MIN_I8 */	11812	/* ATOMIC_LOAD_MIN_I8 */
11813	810,	11813	810,
11814	/* ATOMIC_LOAD_MIN_I8_POSTRA */	11814	/* ATOMIC_LOAD_MIN_I8_POSTRA */
11815	813,	11815	813,
11816	/* ATOMIC_LOAD_NAND_I16 */	11816	/* ATOMIC_LOAD_NAND_I16 */
11817	819,	11817	819,
11818	/* ATOMIC_LOAD_NAND_I16_POSTRA */	11818	/* ATOMIC_LOAD_NAND_I16_POSTRA */
11819	822,	11819	822,
11820	/* ATOMIC_LOAD_NAND_I32 */	11820	/* ATOMIC_LOAD_NAND_I32 */
11821	828,	11821	828,
11822	/* ATOMIC_LOAD_NAND_I32_POSTRA */	11822	/* ATOMIC_LOAD_NAND_I32_POSTRA */
11823	831,	11823	831,
11824	/* ATOMIC_LOAD_NAND_I64 */	11824	/* ATOMIC_LOAD_NAND_I64 */
11825	834,	11825	834,
11826	/* ATOMIC_LOAD_NAND_I64_POSTRA */	11826	/* ATOMIC_LOAD_NAND_I64_POSTRA */
11827	837,	11827	837,
11828	/* ATOMIC_LOAD_NAND_I8 */	11828	/* ATOMIC_LOAD_NAND_I8 */
11829	840,	11829	840,
11830	/* ATOMIC_LOAD_NAND_I8_POSTRA */	11830	/* ATOMIC_LOAD_NAND_I8_POSTRA */
11831	843,	11831	843,
11832	/* ATOMIC_LOAD_OR_I16 */	11832	/* ATOMIC_LOAD_OR_I16 */
11833	849,	11833	849,
11834	/* ATOMIC_LOAD_OR_I16_POSTRA */	11834	/* ATOMIC_LOAD_OR_I16_POSTRA */
11835	852,	11835	852,
11836	/* ATOMIC_LOAD_OR_I32 */	11836	/* ATOMIC_LOAD_OR_I32 */
11837	858,	11837	858,
11838	/* ATOMIC_LOAD_OR_I32_POSTRA */	11838	/* ATOMIC_LOAD_OR_I32_POSTRA */
11839	861,	11839	861,
11840	/* ATOMIC_LOAD_OR_I64 */	11840	/* ATOMIC_LOAD_OR_I64 */
11841	864,	11841	864,
11842	/* ATOMIC_LOAD_OR_I64_POSTRA */	11842	/* ATOMIC_LOAD_OR_I64_POSTRA */
11843	867,	11843	867,
11844	/* ATOMIC_LOAD_OR_I8 */	11844	/* ATOMIC_LOAD_OR_I8 */
11845	870,	11845	870,
11846	/* ATOMIC_LOAD_OR_I8_POSTRA */	11846	/* ATOMIC_LOAD_OR_I8_POSTRA */
11847	873,	11847	873,
11848	/* ATOMIC_LOAD_SUB_I16 */	11848	/* ATOMIC_LOAD_SUB_I16 */
11849	879,	11849	879,
11850	/* ATOMIC_LOAD_SUB_I16_POSTRA */	11850	/* ATOMIC_LOAD_SUB_I16_POSTRA */
11851	882,	11851	882,
11852	/* ATOMIC_LOAD_SUB_I32 */	11852	/* ATOMIC_LOAD_SUB_I32 */
11853	888,	11853	888,
11854	/* ATOMIC_LOAD_SUB_I32_POSTRA */	11854	/* ATOMIC_LOAD_SUB_I32_POSTRA */
11855	891,	11855	891,
11856	/* ATOMIC_LOAD_SUB_I64 */	11856	/* ATOMIC_LOAD_SUB_I64 */
11857	894,	11857	894,
11858	/* ATOMIC_LOAD_SUB_I64_POSTRA */	11858	/* ATOMIC_LOAD_SUB_I64_POSTRA */
11859	897,	11859	897,
11860	/* ATOMIC_LOAD_SUB_I8 */	11860	/* ATOMIC_LOAD_SUB_I8 */
11861	900,	11861	900,
11862	/* ATOMIC_LOAD_SUB_I8_POSTRA */	11862	/* ATOMIC_LOAD_SUB_I8_POSTRA */
11863	903,	11863	903,
11864	/* ATOMIC_LOAD_UMAX_I16 */	11864	/* ATOMIC_LOAD_UMAX_I16 */
11865	909,	11865	909,
11866	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	11866	/* ATOMIC_LOAD_UMAX_I16_POSTRA */
11867	912,	11867	912,
11868	/* ATOMIC_LOAD_UMAX_I32 */	11868	/* ATOMIC_LOAD_UMAX_I32 */
11869	918,	11869	918,
11870	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	11870	/* ATOMIC_LOAD_UMAX_I32_POSTRA */
11871	921,	11871	921,
11872	/* ATOMIC_LOAD_UMAX_I64 */	11872	/* ATOMIC_LOAD_UMAX_I64 */
11873	924,	11873	924,
11874	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	11874	/* ATOMIC_LOAD_UMAX_I64_POSTRA */
11875	927,	11875	927,
11876	/* ATOMIC_LOAD_UMAX_I8 */	11876	/* ATOMIC_LOAD_UMAX_I8 */
11877	930,	11877	930,
11878	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	11878	/* ATOMIC_LOAD_UMAX_I8_POSTRA */
11879	933,	11879	933,
11880	/* ATOMIC_LOAD_UMIN_I16 */	11880	/* ATOMIC_LOAD_UMIN_I16 */
11881	939,	11881	939,
11882	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	11882	/* ATOMIC_LOAD_UMIN_I16_POSTRA */
11883	942,	11883	942,
11884	/* ATOMIC_LOAD_UMIN_I32 */	11884	/* ATOMIC_LOAD_UMIN_I32 */
11885	948,	11885	948,
11886	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	11886	/* ATOMIC_LOAD_UMIN_I32_POSTRA */
11887	951,	11887	951,
11888	/* ATOMIC_LOAD_UMIN_I64 */	11888	/* ATOMIC_LOAD_UMIN_I64 */
11889	954,	11889	954,
11890	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	11890	/* ATOMIC_LOAD_UMIN_I64_POSTRA */
11891	957,	11891	957,
11892	/* ATOMIC_LOAD_UMIN_I8 */	11892	/* ATOMIC_LOAD_UMIN_I8 */
11893	960,	11893	960,
11894	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	11894	/* ATOMIC_LOAD_UMIN_I8_POSTRA */
11895	963,	11895	963,
11896	/* ATOMIC_LOAD_XOR_I16 */	11896	/* ATOMIC_LOAD_XOR_I16 */
11897	969,	11897	969,
11898	/* ATOMIC_LOAD_XOR_I16_POSTRA */	11898	/* ATOMIC_LOAD_XOR_I16_POSTRA */
11899	972,	11899	972,
11900	/* ATOMIC_LOAD_XOR_I32 */	11900	/* ATOMIC_LOAD_XOR_I32 */
11901	978,	11901	978,
11902	/* ATOMIC_LOAD_XOR_I32_POSTRA */	11902	/* ATOMIC_LOAD_XOR_I32_POSTRA */
11903	981,	11903	981,
11904	/* ATOMIC_LOAD_XOR_I64 */	11904	/* ATOMIC_LOAD_XOR_I64 */
11905	984,	11905	984,
11906	/* ATOMIC_LOAD_XOR_I64_POSTRA */	11906	/* ATOMIC_LOAD_XOR_I64_POSTRA */
11907	987,	11907	987,
11908	/* ATOMIC_LOAD_XOR_I8 */	11908	/* ATOMIC_LOAD_XOR_I8 */
11909	990,	11909	990,
11910	/* ATOMIC_LOAD_XOR_I8_POSTRA */	11910	/* ATOMIC_LOAD_XOR_I8_POSTRA */
11911	993,	11911	993,
11912	/* ATOMIC_SWAP_I16 */	11912	/* ATOMIC_SWAP_I16 */
11913	999,	11913	999,
11914	/* ATOMIC_SWAP_I16_POSTRA */	11914	/* ATOMIC_SWAP_I16_POSTRA */
11915	1002,	11915	1002,
11916	/* ATOMIC_SWAP_I32 */	11916	/* ATOMIC_SWAP_I32 */
11917	1008,	11917	1008,
11918	/* ATOMIC_SWAP_I32_POSTRA */	11918	/* ATOMIC_SWAP_I32_POSTRA */
11919	1011,	11919	1011,
11920	/* ATOMIC_SWAP_I64 */	11920	/* ATOMIC_SWAP_I64 */
11921	1014,	11921	1014,
11922	/* ATOMIC_SWAP_I64_POSTRA */	11922	/* ATOMIC_SWAP_I64_POSTRA */
11923	1017,	11923	1017,
11924	/* ATOMIC_SWAP_I8 */	11924	/* ATOMIC_SWAP_I8 */
11925	1020,	11925	1020,
11926	/* ATOMIC_SWAP_I8_POSTRA */	11926	/* ATOMIC_SWAP_I8_POSTRA */
11927	1023,	11927	1023,
11928	/* B */	11928	/* B */
11929	1029,	11929	1029,
11930	/* BAL_BR */	11930	/* BAL_BR */
11931	1030,	11931	1030,
11932	/* BAL_BR_MM */	11932	/* BAL_BR_MM */
11933	1031,	11933	1031,
11934	/* BEQLImmMacro */	11934	/* BEQLImmMacro */
11935	1032,	11935	1032,
11936	/* BGE */	11936	/* BGE */
11937	1035,	11937	1035,
11938	/* BGEImmMacro */	11938	/* BGEImmMacro */
11939	1038,	11939	1038,
11940	/* BGEL */	11940	/* BGEL */
11941	1041,	11941	1041,
11942	/* BGELImmMacro */	11942	/* BGELImmMacro */
11943	1044,	11943	1044,
11944	/* BGEU */	11944	/* BGEU */
11945	1047,	11945	1047,
11946	/* BGEUImmMacro */	11946	/* BGEUImmMacro */
11947	1050,	11947	1050,
11948	/* BGEUL */	11948	/* BGEUL */
11949	1053,	11949	1053,
11950	/* BGEULImmMacro */	11950	/* BGEULImmMacro */
11951	1056,	11951	1056,
11952	/* BGT */	11952	/* BGT */
11953	1059,	11953	1059,
11954	/* BGTImmMacro */	11954	/* BGTImmMacro */
11955	1062,	11955	1062,
11956	/* BGTL */	11956	/* BGTL */
11957	1065,	11957	1065,
11958	/* BGTLImmMacro */	11958	/* BGTLImmMacro */
11959	1068,	11959	1068,
11960	/* BGTU */	11960	/* BGTU */
11961	1071,	11961	1071,
11962	/* BGTUImmMacro */	11962	/* BGTUImmMacro */
11963	1074,	11963	1074,
11964	/* BGTUL */	11964	/* BGTUL */
11965	1077,	11965	1077,
11966	/* BGTULImmMacro */	11966	/* BGTULImmMacro */
11967	1080,	11967	1080,
11968	/* BLE */	11968	/* BLE */
11969	1083,	11969	1083,
11970	/* BLEImmMacro */	11970	/* BLEImmMacro */
11971	1086,	11971	1086,
11972	/* BLEL */	11972	/* BLEL */
11973	1089,	11973	1089,
11974	/* BLELImmMacro */	11974	/* BLELImmMacro */
11975	1092,	11975	1092,
11976	/* BLEU */	11976	/* BLEU */
11977	1095,	11977	1095,
11978	/* BLEUImmMacro */	11978	/* BLEUImmMacro */
11979	1098,	11979	1098,
11980	/* BLEUL */	11980	/* BLEUL */
11981	1101,	11981	1101,
11982	/* BLEULImmMacro */	11982	/* BLEULImmMacro */
11983	1104,	11983	1104,
11984	/* BLT */	11984	/* BLT */
11985	1107,	11985	1107,
11986	/* BLTImmMacro */	11986	/* BLTImmMacro */
11987	1110,	11987	1110,
11988	/* BLTL */	11988	/* BLTL */
11989	1113,	11989	1113,
11990	/* BLTLImmMacro */	11990	/* BLTLImmMacro */
11991	1116,	11991	1116,
11992	/* BLTU */	11992	/* BLTU */
11993	1119,	11993	1119,
11994	/* BLTUImmMacro */	11994	/* BLTUImmMacro */
11995	1122,	11995	1122,
11996	/* BLTUL */	11996	/* BLTUL */
11997	1125,	11997	1125,
11998	/* BLTULImmMacro */	11998	/* BLTULImmMacro */
11999	1128,	11999	1128,
12000	/* BNELImmMacro */	12000	/* BNELImmMacro */
12001	1131,	12001	1131,
12002	/* BPOSGE32_PSEUDO */	12002	/* BPOSGE32_PSEUDO */
12003	1134,	12003	1134,
12004	/* BSEL_D_PSEUDO */	12004	/* BSEL_D_PSEUDO */
12005	1135,	12005	1135,
12006	/* BSEL_FD_PSEUDO */	12006	/* BSEL_FD_PSEUDO */
12007	1139,	12007	1139,
12008	/* BSEL_FW_PSEUDO */	12008	/* BSEL_FW_PSEUDO */
12009	1143,	12009	1143,
12010	/* BSEL_H_PSEUDO */	12010	/* BSEL_H_PSEUDO */
12011	1147,	12011	1147,
12012	/* BSEL_W_PSEUDO */	12012	/* BSEL_W_PSEUDO */
12013	1151,	12013	1151,
12014	/* B_MM */	12014	/* B_MM */
12015	1155,	12015	1155,
12016	/* B_MMR6_Pseudo */	12016	/* B_MMR6_Pseudo */
12017	1156,	12017	1156,
12018	/* B_MM_Pseudo */	12018	/* B_MM_Pseudo */
12019	1157,	12019	1157,
12020	/* BeqImm */	12020	/* BeqImm */
12021	1158,	12021	1158,
12022	/* BneImm */	12022	/* BneImm */
12023	1161,	12023	1161,
12024	/* BteqzT8CmpX16 */	12024	/* BteqzT8CmpX16 */
12025	1164,	12025	1164,
12026	/* BteqzT8CmpiX16 */	12026	/* BteqzT8CmpiX16 */
12027	1167,	12027	1167,
12028	/* BteqzT8SltX16 */	12028	/* BteqzT8SltX16 */
12029	1170,	12029	1170,
12030	/* BteqzT8SltiX16 */	12030	/* BteqzT8SltiX16 */
12031	1173,	12031	1173,
12032	/* BteqzT8SltiuX16 */	12032	/* BteqzT8SltiuX16 */
12033	1176,	12033	1176,
12034	/* BteqzT8SltuX16 */	12034	/* BteqzT8SltuX16 */
12035	1179,	12035	1179,
12036	/* BtnezT8CmpX16 */	12036	/* BtnezT8CmpX16 */
12037	1182,	12037	1182,
12038	/* BtnezT8CmpiX16 */	12038	/* BtnezT8CmpiX16 */
12039	1185,	12039	1185,
12040	/* BtnezT8SltX16 */	12040	/* BtnezT8SltX16 */
12041	1188,	12041	1188,
12042	/* BtnezT8SltiX16 */	12042	/* BtnezT8SltiX16 */
12043	1191,	12043	1191,
12044	/* BtnezT8SltiuX16 */	12044	/* BtnezT8SltiuX16 */
12045	1194,	12045	1194,
12046	/* BtnezT8SltuX16 */	12046	/* BtnezT8SltuX16 */
12047	1197,	12047	1197,
12048	/* BuildPairF64 */	12048	/* BuildPairF64 */
12049	1200,	12049	1200,
12050	/* BuildPairF64_64 */	12050	/* BuildPairF64_64 */
12051	1203,	12051	1203,
12052	/* CFTC1 */	12052	/* CFTC1 */
12053	1206,	12053	1206,
12054	/* CONSTPOOL_ENTRY */	12054	/* CONSTPOOL_ENTRY */
12055	1208,	12055	1208,
12056	/* COPY_FD_PSEUDO */	12056	/* COPY_FD_PSEUDO */
12057	1211,	12057	1211,
12058	/* COPY_FW_PSEUDO */	12058	/* COPY_FW_PSEUDO */
12059	1214,	12059	1214,
12060	/* CTTC1 */	12060	/* CTTC1 */
12061	1217,	12061	1217,
12062	/* Constant32 */	12062	/* Constant32 */
12063	1219,	12063	1219,
12064	/* DMULImmMacro */	12064	/* DMULImmMacro */
12065	1220,	12065	1220,
12066	/* DMULMacro */	12066	/* DMULMacro */
12067	1223,	12067	1223,
12068	/* DMULOMacro */	12068	/* DMULOMacro */
12069	1226,	12069	1226,
12070	/* DMULOUMacro */	12070	/* DMULOUMacro */
12071	1229,	12071	1229,
12072	/* DROL */	12072	/* DROL */
12073	1232,	12073	1232,
12074	/* DROLImm */	12074	/* DROLImm */
12075	1235,	12075	1235,
12076	/* DROR */	12076	/* DROR */
12077	1238,	12077	1238,
12078	/* DRORImm */	12078	/* DRORImm */
12079	1241,	12079	1241,
12080	/* DSDivIMacro */	12080	/* DSDivIMacro */
12081	1244,	12081	1244,
12082	/* DSDivMacro */	12082	/* DSDivMacro */
12083	1247,	12083	1247,
12084	/* DSRemIMacro */	12084	/* DSRemIMacro */
12085	1250,	12085	1250,
12086	/* DSRemMacro */	12086	/* DSRemMacro */
12087	1253,	12087	1253,
12088	/* DUDivIMacro */	12088	/* DUDivIMacro */
12089	1256,	12089	1256,
12090	/* DUDivMacro */	12090	/* DUDivMacro */
12091	1259,	12091	1259,
12092	/* DURemIMacro */	12092	/* DURemIMacro */
12093	1262,	12093	1262,
12094	/* DURemMacro */	12094	/* DURemMacro */
12095	1265,	12095	1265,
12096	/* ERet */	12096	/* ERet */
12097	1268,	12097	1268,
12098	/* ExtractElementF64 */	12098	/* ExtractElementF64 */
12099	1268,	12099	1268,
12100	/* ExtractElementF64_64 */	12100	/* ExtractElementF64_64 */
12101	1271,	12101	1271,
12102	/* FABS_D */	12102	/* FABS_D */
12103	1274,	12103	1274,
12104	/* FABS_W */	12104	/* FABS_W */
12105	1276,	12105	1276,
12106	/* FEXP2_D_1_PSEUDO */	12106	/* FEXP2_D_1_PSEUDO */
12107	1278,	12107	1278,
12108	/* FEXP2_W_1_PSEUDO */	12108	/* FEXP2_W_1_PSEUDO */
12109	1280,	12109	1280,
12110	/* FILL_FD_PSEUDO */	12110	/* FILL_FD_PSEUDO */
12111	1282,	12111	1282,
12112	/* FILL_FW_PSEUDO */	12112	/* FILL_FW_PSEUDO */
12113	1284,	12113	1284,
12114	/* GotPrologue16 */	12114	/* GotPrologue16 */
12115	1286,	12115	1286,
12116	/* INSERT_B_VIDX64_PSEUDO */	12116	/* INSERT_B_VIDX64_PSEUDO */
12117	1290,	12117	1290,
12118	/* INSERT_B_VIDX_PSEUDO */	12118	/* INSERT_B_VIDX_PSEUDO */
12119	1294,	12119	1294,
12120	/* INSERT_D_VIDX64_PSEUDO */	12120	/* INSERT_D_VIDX64_PSEUDO */
12121	1298,	12121	1298,
12122	/* INSERT_D_VIDX_PSEUDO */	12122	/* INSERT_D_VIDX_PSEUDO */
12123	1302,	12123	1302,
12124	/* INSERT_FD_PSEUDO */	12124	/* INSERT_FD_PSEUDO */
12125	1306,	12125	1306,
12126	/* INSERT_FD_VIDX64_PSEUDO */	12126	/* INSERT_FD_VIDX64_PSEUDO */
12127	1310,	12127	1310,
12128	/* INSERT_FD_VIDX_PSEUDO */	12128	/* INSERT_FD_VIDX_PSEUDO */
12129	1314,	12129	1314,
12130	/* INSERT_FW_PSEUDO */	12130	/* INSERT_FW_PSEUDO */
12131	1318,	12131	1318,
12132	/* INSERT_FW_VIDX64_PSEUDO */	12132	/* INSERT_FW_VIDX64_PSEUDO */
12133	1322,	12133	1322,
12134	/* INSERT_FW_VIDX_PSEUDO */	12134	/* INSERT_FW_VIDX_PSEUDO */
12135	1326,	12135	1326,
12136	/* INSERT_H_VIDX64_PSEUDO */	12136	/* INSERT_H_VIDX64_PSEUDO */
12137	1330,	12137	1330,
12138	/* INSERT_H_VIDX_PSEUDO */	12138	/* INSERT_H_VIDX_PSEUDO */
12139	1334,	12139	1334,
12140	/* INSERT_W_VIDX64_PSEUDO */	12140	/* INSERT_W_VIDX64_PSEUDO */
12141	1338,	12141	1338,
12142	/* INSERT_W_VIDX_PSEUDO */	12142	/* INSERT_W_VIDX_PSEUDO */
12143	1342,	12143	1342,
12144	/* JALR64Pseudo */	12144	/* JALR64Pseudo */
12145	1346,	12145	1346,
12146	/* JALRHB64Pseudo */	12146	/* JALRHB64Pseudo */
12147	1347,	12147	1347,
12148	/* JALRHBPseudo */	12148	/* JALRHBPseudo */
12149	1348,	12149	1348,
12150	/* JALRPseudo */	12150	/* JALRPseudo */
12151	1349,	12151	1349,
12152	/* JAL_MMR6 */	12152	/* JAL_MMR6 */
12153	1350,	12153	1350,
12154	/* JalOneReg */	12154	/* JalOneReg */
12155	1351,	12155	1351,
12156	/* JalTwoReg */	12156	/* JalTwoReg */
12157	1352,	12157	1352,
12158	/* LDMacro */	12158	/* LDMacro */
12159	1354,	12159	1354,
12160	/* LDR_D */	12160	/* LDR_D */
12161	1357,	12161	1357,
12162	/* LDR_W */	12162	/* LDR_W */
12163	1360,	12163	1360,
12164	/* LD_F16 */	12164	/* LD_F16 */
12165	1363,	12165	1363,
12166	/* LOAD_ACC128 */	12166	/* LOAD_ACC128 */
12167	1366,	12167	1366,
12168	/* LOAD_ACC64 */	12168	/* LOAD_ACC64 */
12169	1369,	12169	1369,
12170	/* LOAD_ACC64DSP */	12170	/* LOAD_ACC64DSP */
12171	1372,	12171	1372,
12172	/* LOAD_CCOND_DSP */	12172	/* LOAD_CCOND_DSP */
12173	1375,	12173	1375,
12174	/* LONG_BRANCH_ADDiu */	12174	/* LONG_BRANCH_ADDiu */
12175	1378,	12175	1378,
12176	/* LONG_BRANCH_ADDiu2Op */	12176	/* LONG_BRANCH_ADDiu2Op */
12177	1382,	12177	1382,
12178	/* LONG_BRANCH_DADDiu */	12178	/* LONG_BRANCH_DADDiu */
12179	1385,	12179	1385,
12180	/* LONG_BRANCH_DADDiu2Op */	12180	/* LONG_BRANCH_DADDiu2Op */
12181	1389,	12181	1389,
12182	/* LONG_BRANCH_LUi */	12182	/* LONG_BRANCH_LUi */
12183	1392,	12183	1392,
12184	/* LONG_BRANCH_LUi2Op */	12184	/* LONG_BRANCH_LUi2Op */
12185	1395,	12185	1395,
12186	/* LONG_BRANCH_LUi2Op_64 */	12186	/* LONG_BRANCH_LUi2Op_64 */
12187	1397,	12187	1397,
12188	/* LWM_MM */	12188	/* LWM_MM */
12189	1399,	12189	1399,
12190	/* LoadAddrImm32 */	12190	/* LoadAddrImm32 */
12191	1402,	12191	1402,
12192	/* LoadAddrImm64 */	12192	/* LoadAddrImm64 */
12193	1404,	12193	1404,
12194	/* LoadAddrReg32 */	12194	/* LoadAddrReg32 */
12195	1406,	12195	1406,
12196	/* LoadAddrReg64 */	12196	/* LoadAddrReg64 */
12197	1409,	12197	1409,
12198	/* LoadImm32 */	12198	/* LoadImm32 */
12199	1412,	12199	1412,
12200	/* LoadImm64 */	12200	/* LoadImm64 */
12201	1414,	12201	1414,
12202	/* LoadImmDoubleFGR */	12202	/* LoadImmDoubleFGR */
12203	1416,	12203	1416,
12204	/* LoadImmDoubleFGR_32 */	12204	/* LoadImmDoubleFGR_32 */
12205	1418,	12205	1418,
12206	/* LoadImmDoubleGPR */	12206	/* LoadImmDoubleGPR */
12207	1420,	12207	1420,
12208	/* LoadImmSingleFGR */	12208	/* LoadImmSingleFGR */
12209	1422,	12209	1422,
12210	/* LoadImmSingleGPR */	12210	/* LoadImmSingleGPR */
12211	1424,	12211	1424,
12212	/* LwConstant32 */	12212	/* LwConstant32 */
12213	1426,	12213	1426,
12214	/* MFTACX */	12214	/* MFTACX */
12215	1429,	12215	1429,
12216	/* MFTC0 */	12216	/* MFTC0 */
12217	1431,	12217	1431,
12218	/* MFTC1 */	12218	/* MFTC1 */
12219	1434,	12219	1434,
12220	/* MFTDSP */	12220	/* MFTDSP */
12221	1436,	12221	1436,
12222	/* MFTGPR */	12222	/* MFTGPR */
12223	1437,	12223	1437,
12224	/* MFTHC1 */	12224	/* MFTHC1 */
12225	1440,	12225	1440,
12226	/* MFTHI */	12226	/* MFTHI */
12227	1442,	12227	1442,
12228	/* MFTLO */	12228	/* MFTLO */
12229	1444,	12229	1444,
12230	/* MIPSeh_return32 */	12230	/* MIPSeh_return32 */
12231	1446,	12231	1446,
12232	/* MIPSeh_return64 */	12232	/* MIPSeh_return64 */
12233	1448,	12233	1448,
12234	/* MSA_FP_EXTEND_D_PSEUDO */	12234	/* MSA_FP_EXTEND_D_PSEUDO */
12235	1450,	12235	1450,
12236	/* MSA_FP_EXTEND_W_PSEUDO */	12236	/* MSA_FP_EXTEND_W_PSEUDO */
12237	1452,	12237	1452,
12238	/* MSA_FP_ROUND_D_PSEUDO */	12238	/* MSA_FP_ROUND_D_PSEUDO */
12239	1454,	12239	1454,
12240	/* MSA_FP_ROUND_W_PSEUDO */	12240	/* MSA_FP_ROUND_W_PSEUDO */
12241	1456,	12241	1456,
12242	/* MTTACX */	12242	/* MTTACX */
12243	1458,	12243	1458,
12244	/* MTTC0 */	12244	/* MTTC0 */
12245	1460,	12245	1460,
12246	/* MTTC1 */	12246	/* MTTC1 */
12247	1463,	12247	1463,
12248	/* MTTDSP */	12248	/* MTTDSP */
12249	1465,	12249	1465,
12250	/* MTTGPR */	12250	/* MTTGPR */
12251	1466,	12251	1466,
12252	/* MTTHC1 */	12252	/* MTTHC1 */
12253	1468,	12253	1468,
12254	/* MTTHI */	12254	/* MTTHI */
12255	1470,	12255	1470,
12256	/* MTTLO */	12256	/* MTTLO */
12257	1472,	12257	1472,
12258	/* MULImmMacro */	12258	/* MULImmMacro */
12259	1474,	12259	1474,
12260	/* MULOMacro */	12260	/* MULOMacro */
12261	1477,	12261	1477,
12262	/* MULOUMacro */	12262	/* MULOUMacro */
12263	1480,	12263	1480,
12264	/* MultRxRy16 */	12264	/* MultRxRy16 */
12265	1483,	12265	1483,
12266	/* MultRxRyRz16 */	12266	/* MultRxRyRz16 */
12267	1485,	12267	1485,
12268	/* MultuRxRy16 */	12268	/* MultuRxRy16 */
12269	1488,	12269	1488,
12270	/* MultuRxRyRz16 */	12270	/* MultuRxRyRz16 */
12271	1490,	12271	1490,
12272	/* NOP */	12272	/* NOP */
12273	1493,	12273	1493,
12274	/* NORImm */	12274	/* NORImm */
12275	1493,	12275	1493,
12276	/* NORImm64 */	12276	/* NORImm64 */
12277	1496,	12277	1496,
12278	/* NOR_V_D_PSEUDO */	12278	/* NOR_V_D_PSEUDO */
12279	1499,	12279	1499,
12280	/* NOR_V_H_PSEUDO */	12280	/* NOR_V_H_PSEUDO */
12281	1502,	12281	1502,
12282	/* NOR_V_W_PSEUDO */	12282	/* NOR_V_W_PSEUDO */
12283	1505,	12283	1505,
12284	/* OR_V_D_PSEUDO */	12284	/* OR_V_D_PSEUDO */
12285	1508,	12285	1508,
12286	/* OR_V_H_PSEUDO */	12286	/* OR_V_H_PSEUDO */
12287	1511,	12287	1511,
12288	/* OR_V_W_PSEUDO */	12288	/* OR_V_W_PSEUDO */
12289	1514,	12289	1514,
12290	/* PseudoCMPU_EQ_QB */	12290	/* PseudoCMPU_EQ_QB */
12291	1517,	12291	1517,
12292	/* PseudoCMPU_LE_QB */	12292	/* PseudoCMPU_LE_QB */
12293	1520,	12293	1520,
12294	/* PseudoCMPU_LT_QB */	12294	/* PseudoCMPU_LT_QB */
12295	1523,	12295	1523,
12296	/* PseudoCMP_EQ_PH */	12296	/* PseudoCMP_EQ_PH */
12297	1526,	12297	1526,
12298	/* PseudoCMP_LE_PH */	12298	/* PseudoCMP_LE_PH */
12299	1529,	12299	1529,
12300	/* PseudoCMP_LT_PH */	12300	/* PseudoCMP_LT_PH */
12301	1532,	12301	1532,
12302	/* PseudoCVT_D32_W */	12302	/* PseudoCVT_D32_W */
12303	1535,	12303	1535,
12304	/* PseudoCVT_D64_L */	12304	/* PseudoCVT_D64_L */
12305	1537,	12305	1537,
12306	/* PseudoCVT_D64_W */	12306	/* PseudoCVT_D64_W */
12307	1539,	12307	1539,
12308	/* PseudoCVT_S_L */	12308	/* PseudoCVT_S_L */
12309	1541,	12309	1541,
12310	/* PseudoCVT_S_W */	12310	/* PseudoCVT_S_W */
12311	1543,	12311	1543,
12312	/* PseudoDMULT */	12312	/* PseudoDMULT */
12313	1545,	12313	1545,
12314	/* PseudoDMULTu */	12314	/* PseudoDMULTu */
12315	1548,	12315	1548,
12316	/* PseudoDSDIV */	12316	/* PseudoDSDIV */
12317	1551,	12317	1551,
12318	/* PseudoDUDIV */	12318	/* PseudoDUDIV */
12319	1554,	12319	1554,
12320	/* PseudoD_SELECT_I */	12320	/* PseudoD_SELECT_I */
12321	1557,	12321	1557,
12322	/* PseudoD_SELECT_I64 */	12322	/* PseudoD_SELECT_I64 */
12323	1564,	12323	1564,
12324	/* PseudoIndirectBranch */	12324	/* PseudoIndirectBranch */
12325	1571,	12325	1571,
12326	/* PseudoIndirectBranch64 */	12326	/* PseudoIndirectBranch64 */
12327	1572,	12327	1572,
12328	/* PseudoIndirectBranch64R6 */	12328	/* PseudoIndirectBranch64R6 */
12329	1573,	12329	1573,
12330	/* PseudoIndirectBranchR6 */	12330	/* PseudoIndirectBranchR6 */
12331	1574,	12331	1574,
12332	/* PseudoIndirectBranch_MM */	12332	/* PseudoIndirectBranch_MM */
12333	1575,	12333	1575,
12334	/* PseudoIndirectBranch_MMR6 */	12334	/* PseudoIndirectBranch_MMR6 */
12335	1576,	12335	1576,
12336	/* PseudoIndirectHazardBranch */	12336	/* PseudoIndirectHazardBranch */
12337	1577,	12337	1577,
12338	/* PseudoIndirectHazardBranch64 */	12338	/* PseudoIndirectHazardBranch64 */
12339	1578,	12339	1578,
12340	/* PseudoIndrectHazardBranch64R6 */	12340	/* PseudoIndrectHazardBranch64R6 */
12341	1579,	12341	1579,
12342	/* PseudoIndrectHazardBranchR6 */	12342	/* PseudoIndrectHazardBranchR6 */
12343	1580,	12343	1580,
12344	/* PseudoMADD */	12344	/* PseudoMADD */
12345	1581,	12345	1581,
12346	/* PseudoMADDU */	12346	/* PseudoMADDU */
12347	1585,	12347	1585,
12348	/* PseudoMADDU_MM */	12348	/* PseudoMADDU_MM */
12349	1589,	12349	1589,
12350	/* PseudoMADD_MM */	12350	/* PseudoMADD_MM */
12351	1593,	12351	1593,
12352	/* PseudoMFHI */	12352	/* PseudoMFHI */
12353	1597,	12353	1597,
12354	/* PseudoMFHI64 */	12354	/* PseudoMFHI64 */
12355	1599,	12355	1599,
12356	/* PseudoMFHI_MM */	12356	/* PseudoMFHI_MM */
12357	1601,	12357	1601,
12358	/* PseudoMFLO */	12358	/* PseudoMFLO */
12359	1603,	12359	1603,
12360	/* PseudoMFLO64 */	12360	/* PseudoMFLO64 */
12361	1605,	12361	1605,
12362	/* PseudoMFLO_MM */	12362	/* PseudoMFLO_MM */
12363	1607,	12363	1607,
12364	/* PseudoMSUB */	12364	/* PseudoMSUB */
12365	1609,	12365	1609,
12366	/* PseudoMSUBU */	12366	/* PseudoMSUBU */
12367	1613,	12367	1613,
12368	/* PseudoMSUBU_MM */	12368	/* PseudoMSUBU_MM */
12369	1617,	12369	1617,
12370	/* PseudoMSUB_MM */	12370	/* PseudoMSUB_MM */
12371	1621,	12371	1621,
12372	/* PseudoMTLOHI */	12372	/* PseudoMTLOHI */
12373	1625,	12373	1625,
12374	/* PseudoMTLOHI64 */	12374	/* PseudoMTLOHI64 */
12375	1628,	12375	1628,
12376	/* PseudoMTLOHI_DSP */	12376	/* PseudoMTLOHI_DSP */
12377	1631,	12377	1631,
12378	/* PseudoMTLOHI_MM */	12378	/* PseudoMTLOHI_MM */
12379	1634,	12379	1634,
12380	/* PseudoMULT */	12380	/* PseudoMULT */
12381	1637,	12381	1637,
12382	/* PseudoMULT_MM */	12382	/* PseudoMULT_MM */
12383	1640,	12383	1640,
12384	/* PseudoMULTu */	12384	/* PseudoMULTu */
12385	1643,	12385	1643,
12386	/* PseudoMULTu_MM */	12386	/* PseudoMULTu_MM */
12387	1646,	12387	1646,
12388	/* PseudoPICK_PH */	12388	/* PseudoPICK_PH */
12389	1649,	12389	1649,
12390	/* PseudoPICK_QB */	12390	/* PseudoPICK_QB */
12391	1653,	12391	1653,
12392	/* PseudoReturn */	12392	/* PseudoReturn */
12393	1657,	12393	1657,
12394	/* PseudoReturn64 */	12394	/* PseudoReturn64 */
12395	1658,	12395	1658,
12396	/* PseudoSDIV */	12396	/* PseudoSDIV */
12397	1659,	12397	1659,
12398	/* PseudoSELECTFP_F_D32 */	12398	/* PseudoSELECTFP_F_D32 */
12399	1662,	12399	1662,
12400	/* PseudoSELECTFP_F_D64 */	12400	/* PseudoSELECTFP_F_D64 */
12401	1666,	12401	1666,
12402	/* PseudoSELECTFP_F_I */	12402	/* PseudoSELECTFP_F_I */
12403	1670,	12403	1670,
12404	/* PseudoSELECTFP_F_I64 */	12404	/* PseudoSELECTFP_F_I64 */
12405	1674,	12405	1674,
12406	/* PseudoSELECTFP_F_S */	12406	/* PseudoSELECTFP_F_S */
12407	1678,	12407	1678,
12408	/* PseudoSELECTFP_T_D32 */	12408	/* PseudoSELECTFP_T_D32 */
12409	1682,	12409	1682,
12410	/* PseudoSELECTFP_T_D64 */	12410	/* PseudoSELECTFP_T_D64 */
12411	1686,	12411	1686,
12412	/* PseudoSELECTFP_T_I */	12412	/* PseudoSELECTFP_T_I */
12413	1690,	12413	1690,
12414	/* PseudoSELECTFP_T_I64 */	12414	/* PseudoSELECTFP_T_I64 */
12415	1694,	12415	1694,
12416	/* PseudoSELECTFP_T_S */	12416	/* PseudoSELECTFP_T_S */
12417	1698,	12417	1698,
12418	/* PseudoSELECT_D32 */	12418	/* PseudoSELECT_D32 */
12419	1702,	12419	1702,
12420	/* PseudoSELECT_D64 */	12420	/* PseudoSELECT_D64 */
12421	1706,	12421	1706,
12422	/* PseudoSELECT_I */	12422	/* PseudoSELECT_I */
12423	1710,	12423	1710,
12424	/* PseudoSELECT_I64 */	12424	/* PseudoSELECT_I64 */
12425	1714,	12425	1714,
12426	/* PseudoSELECT_S */	12426	/* PseudoSELECT_S */
12427	1718,	12427	1718,
12428	/* PseudoTRUNC_W_D */	12428	/* PseudoTRUNC_W_D */
12429	1722,	12429	1722,
12430	/* PseudoTRUNC_W_D32 */	12430	/* PseudoTRUNC_W_D32 */
12431	1725,	12431	1725,
12432	/* PseudoTRUNC_W_S */	12432	/* PseudoTRUNC_W_S */
12433	1728,	12433	1728,
12434	/* PseudoUDIV */	12434	/* PseudoUDIV */
12435	1731,	12435	1731,
12436	/* ROL */	12436	/* ROL */
12437	1734,	12437	1734,
12438	/* ROLImm */	12438	/* ROLImm */
12439	1737,	12439	1737,
12440	/* ROR */	12440	/* ROR */
12441	1740,	12441	1740,
12442	/* RORImm */	12442	/* RORImm */
12443	1743,	12443	1743,
12444	/* RetRA */	12444	/* RetRA */
12445	1746,	12445	1746,
12446	/* RetRA16 */	12446	/* RetRA16 */
12447	1746,	12447	1746,
12448	/* SDC1_M1 */	12448	/* SDC1_M1 */
12449	1746,	12449	1746,
12450	/* SDIV_MM_Pseudo */	12450	/* SDIV_MM_Pseudo */
12451	1749,	12451	1749,
12452	/* SDMacro */	12452	/* SDMacro */
12453	1752,	12453	1752,
12454	/* SDivIMacro */	12454	/* SDivIMacro */
12455	1755,	12455	1755,
12456	/* SDivMacro */	12456	/* SDivMacro */
12457	1758,	12457	1758,
12458	/* SEQIMacro */	12458	/* SEQIMacro */
12459	1761,	12459	1761,
12460	/* SEQMacro */	12460	/* SEQMacro */
12461	1764,	12461	1764,
12462	/* SGE */	12462	/* SGE */
12463	1767,	12463	1767,
12464	/* SGEImm */	12464	/* SGEImm */
12465	1770,	12465	1770,
12466	/* SGEImm64 */	12466	/* SGEImm64 */
12467	1773,	12467	1773,
12468	/* SGEU */	12468	/* SGEU */
12469	1776,	12469	1776,
12470	/* SGEUImm */	12470	/* SGEUImm */
12471	1779,	12471	1779,
12472	/* SGEUImm64 */	12472	/* SGEUImm64 */
12473	1782,	12473	1782,
12474	/* SGTImm */	12474	/* SGTImm */
12475	1785,	12475	1785,
12476	/* SGTImm64 */	12476	/* SGTImm64 */
12477	1788,	12477	1788,
12478	/* SGTUImm */	12478	/* SGTUImm */
12479	1791,	12479	1791,
12480	/* SGTUImm64 */	12480	/* SGTUImm64 */
12481	1794,	12481	1794,
12482	/* SLE */	12482	/* SLE */
12483	1797,	12483	1797,
12484	/* SLEImm */	12484	/* SLEImm */
12485	1800,	12485	1800,
12486	/* SLEImm64 */	12486	/* SLEImm64 */
12487	1803,	12487	1803,
12488	/* SLEU */	12488	/* SLEU */
12489	1806,	12489	1806,
12490	/* SLEUImm */	12490	/* SLEUImm */
12491	1809,	12491	1809,
12492	/* SLEUImm64 */	12492	/* SLEUImm64 */
12493	1812,	12493	1812,
12494	/* SLTImm64 */	12494	/* SLTImm64 */
12495	1815,	12495	1815,
12496	/* SLTUImm64 */	12496	/* SLTUImm64 */
12497	1818,	12497	1818,
12498	/* SNEIMacro */	12498	/* SNEIMacro */
12499	1821,	12499	1821,
12500	/* SNEMacro */	12500	/* SNEMacro */
12501	1824,	12501	1824,
12502	/* SNZ_B_PSEUDO */	12502	/* SNZ_B_PSEUDO */
12503	1827,	12503	1827,
12504	/* SNZ_D_PSEUDO */	12504	/* SNZ_D_PSEUDO */
12505	1829,	12505	1829,
12506	/* SNZ_H_PSEUDO */	12506	/* SNZ_H_PSEUDO */
12507	1831,	12507	1831,
12508	/* SNZ_V_PSEUDO */	12508	/* SNZ_V_PSEUDO */
12509	1833,	12509	1833,
12510	/* SNZ_W_PSEUDO */	12510	/* SNZ_W_PSEUDO */
12511	1835,	12511	1835,
12512	/* SRemIMacro */	12512	/* SRemIMacro */
12513	1837,	12513	1837,
12514	/* SRemMacro */	12514	/* SRemMacro */
12515	1840,	12515	1840,
12516	/* STORE_ACC128 */	12516	/* STORE_ACC128 */
12517	1843,	12517	1843,
12518	/* STORE_ACC64 */	12518	/* STORE_ACC64 */
12519	1846,	12519	1846,
12520	/* STORE_ACC64DSP */	12520	/* STORE_ACC64DSP */
12521	1849,	12521	1849,
12522	/* STORE_CCOND_DSP */	12522	/* STORE_CCOND_DSP */
12523	1852,	12523	1852,
12524	/* STR_D */	12524	/* STR_D */
12525	1855,	12525	1855,
12526	/* STR_W */	12526	/* STR_W */
12527	1858,	12527	1858,
12528	/* ST_F16 */	12528	/* ST_F16 */
12529	1861,	12529	1861,
12530	/* SWM_MM */	12530	/* SWM_MM */
12531	1864,	12531	1864,
12532	/* SZ_B_PSEUDO */	12532	/* SZ_B_PSEUDO */
12533	1867,	12533	1867,
12534	/* SZ_D_PSEUDO */	12534	/* SZ_D_PSEUDO */
12535	1869,	12535	1869,
12536	/* SZ_H_PSEUDO */	12536	/* SZ_H_PSEUDO */
12537	1871,	12537	1871,
12538	/* SZ_V_PSEUDO */	12538	/* SZ_V_PSEUDO */
12539	1873,	12539	1873,
12540	/* SZ_W_PSEUDO */	12540	/* SZ_W_PSEUDO */
12541	1875,	12541	1875,
12542	/* SaaAddr */	12542	/* SaaAddr */
12543	1877,	12543	1877,
12544	/* SaadAddr */	12544	/* SaadAddr */
12545	1880,	12545	1880,
12546	/* SelBeqZ */	12546	/* SelBeqZ */
12547	1883,	12547	1883,
12548	/* SelBneZ */	12548	/* SelBneZ */
12549	1887,	12549	1887,
12550	/* SelTBteqZCmp */	12550	/* SelTBteqZCmp */
12551	1891,	12551	1891,
12552	/* SelTBteqZCmpi */	12552	/* SelTBteqZCmpi */
12553	1896,	12553	1896,
12554	/* SelTBteqZSlt */	12554	/* SelTBteqZSlt */
12555	1901,	12555	1901,
12556	/* SelTBteqZSlti */	12556	/* SelTBteqZSlti */
12557	1906,	12557	1906,
12558	/* SelTBteqZSltiu */	12558	/* SelTBteqZSltiu */
12559	1911,	12559	1911,
12560	/* SelTBteqZSltu */	12560	/* SelTBteqZSltu */
12561	1916,	12561	1916,
12562	/* SelTBtneZCmp */	12562	/* SelTBtneZCmp */
12563	1921,	12563	1921,
12564	/* SelTBtneZCmpi */	12564	/* SelTBtneZCmpi */
12565	1926,	12565	1926,
12566	/* SelTBtneZSlt */	12566	/* SelTBtneZSlt */
12567	1931,	12567	1931,
12568	/* SelTBtneZSlti */	12568	/* SelTBtneZSlti */
12569	1936,	12569	1936,
12570	/* SelTBtneZSltiu */	12570	/* SelTBtneZSltiu */
12571	1941,	12571	1941,
12572	/* SelTBtneZSltu */	12572	/* SelTBtneZSltu */
12573	1946,	12573	1946,
12574	/* SltCCRxRy16 */	12574	/* SltCCRxRy16 */
12575	1951,	12575	1951,
12576	/* SltiCCRxImmX16 */	12576	/* SltiCCRxImmX16 */
12577	1954,	12577	1954,
12578	/* SltiuCCRxImmX16 */	12578	/* SltiuCCRxImmX16 */
12579	1957,	12579	1957,
12580	/* SltuCCRxRy16 */	12580	/* SltuCCRxRy16 */
12581	1960,	12581	1960,
12582	/* SltuRxRyRz16 */	12582	/* SltuRxRyRz16 */
12583	1963,	12583	1963,
12584	/* TAILCALL */	12584	/* TAILCALL */
12585	1966,	12585	1966,
12586	/* TAILCALL64R6REG */	12586	/* TAILCALL64R6REG */
12587	1967,	12587	1967,
12588	/* TAILCALLHB64R6REG */	12588	/* TAILCALLHB64R6REG */
12589	1968,	12589	1968,
12590	/* TAILCALLHBR6REG */	12590	/* TAILCALLHBR6REG */
12591	1969,	12591	1969,
12592	/* TAILCALLR6REG */	12592	/* TAILCALLR6REG */
12593	1970,	12593	1970,
12594	/* TAILCALLREG */	12594	/* TAILCALLREG */
12595	1971,	12595	1971,
12596	/* TAILCALLREG64 */	12596	/* TAILCALLREG64 */
12597	1972,	12597	1972,
12598	/* TAILCALLREGHB */	12598	/* TAILCALLREGHB */
12599	1973,	12599	1973,
12600	/* TAILCALLREGHB64 */	12600	/* TAILCALLREGHB64 */
12601	1974,	12601	1974,
12602	/* TAILCALLREG_MM */	12602	/* TAILCALLREG_MM */
12603	1975,	12603	1975,
12604	/* TAILCALLREG_MMR6 */	12604	/* TAILCALLREG_MMR6 */
12605	1976,	12605	1976,
12606	/* TAILCALL_MM */	12606	/* TAILCALL_MM */
12607	1977,	12607	1977,
12608	/* TAILCALL_MMR6 */	12608	/* TAILCALL_MMR6 */
12609	1978,	12609	1978,
12610	/* TRAP */	12610	/* TRAP */
12611	1979,	12611	1979,
12612	/* TRAP_MM */	12612	/* TRAP_MM */
12613	1979,	12613	1979,
12614	/* UDIV_MM_Pseudo */	12614	/* UDIV_MM_Pseudo */
12615	1979,	12615	1979,
12616	/* UDivIMacro */	12616	/* UDivIMacro */
12617	1982,	12617	1982,
12618	/* UDivMacro */	12618	/* UDivMacro */
12619	1985,	12619	1985,
12620	/* URemIMacro */	12620	/* URemIMacro */
12621	1988,	12621	1988,
12622	/* URemMacro */	12622	/* URemMacro */
12623	1991,	12623	1991,
12624	/* Ulh */	12624	/* Ulh */
12625	1994,	12625	1994,
12626	/* Ulhu */	12626	/* Ulhu */
12627	1997,	12627	1997,
12628	/* Ulw */	12628	/* Ulw */
12629	2000,	12629	2000,
12630	/* Ush */	12630	/* Ush */
12631	2003,	12631	2003,
12632	/* Usw */	12632	/* Usw */
12633	2006,	12633	2006,
12634	/* XOR_V_D_PSEUDO */	12634	/* XOR_V_D_PSEUDO */
12635	2009,	12635	2009,
12636	/* XOR_V_H_PSEUDO */	12636	/* XOR_V_H_PSEUDO */
12637	2012,	12637	2012,
12638	/* XOR_V_W_PSEUDO */	12638	/* XOR_V_W_PSEUDO */
12639	2015,	12639	2015,
12640	/* ABSQ_S_PH */	12640	/* ABSQ_S_PH */
12641	2018,	12641	2018,
12642	/* ABSQ_S_PH_MM */	12642	/* ABSQ_S_PH_MM */
12643	2020,	12643	2020,
12644	/* ABSQ_S_QB */	12644	/* ABSQ_S_QB */
12645	2022,	12645	2022,
12646	/* ABSQ_S_QB_MMR2 */	12646	/* ABSQ_S_QB_MMR2 */
12647	2024,	12647	2024,
12648	/* ABSQ_S_W */	12648	/* ABSQ_S_W */
12649	2026,	12649	2026,
12650	/* ABSQ_S_W_MM */	12650	/* ABSQ_S_W_MM */
12651	2028,	12651	2028,
12652	/* ADD */	12652	/* ADD */
12653	2030,	12653	2030,
12654	/* ADDIUPC */	12654	/* ADDIUPC */
12655	2033,	12655	2033,
12656	/* ADDIUPC_MM */	12656	/* ADDIUPC_MM */
12657	2035,	12657	2035,
12658	/* ADDIUPC_MMR6 */	12658	/* ADDIUPC_MMR6 */
12659	2037,	12659	2037,
12660	/* ADDIUR1SP_MM */	12660	/* ADDIUR1SP_MM */
12661	2039,	12661	2039,
12662	/* ADDIUR2_MM */	12662	/* ADDIUR2_MM */
12663	2041,	12663	2041,
12664	/* ADDIUS5_MM */	12664	/* ADDIUS5_MM */
12665	2044,	12665	2044,
12666	/* ADDIUSP_MM */	12666	/* ADDIUSP_MM */
12667	2047,	12667	2047,
12668	/* ADDIU_MMR6 */	12668	/* ADDIU_MMR6 */
12669	2048,	12669	2048,
12670	/* ADDQH_PH */	12670	/* ADDQH_PH */
12671	2051,	12671	2051,
12672	/* ADDQH_PH_MMR2 */	12672	/* ADDQH_PH_MMR2 */
12673	2054,	12673	2054,
12674	/* ADDQH_R_PH */	12674	/* ADDQH_R_PH */
12675	2057,	12675	2057,
12676	/* ADDQH_R_PH_MMR2 */	12676	/* ADDQH_R_PH_MMR2 */
12677	2060,	12677	2060,
12678	/* ADDQH_R_W */	12678	/* ADDQH_R_W */
12679	2063,	12679	2063,
12680	/* ADDQH_R_W_MMR2 */	12680	/* ADDQH_R_W_MMR2 */
12681	2066,	12681	2066,
12682	/* ADDQH_W */	12682	/* ADDQH_W */
12683	2069,	12683	2069,
12684	/* ADDQH_W_MMR2 */	12684	/* ADDQH_W_MMR2 */
12685	2072,	12685	2072,
12686	/* ADDQ_PH */	12686	/* ADDQ_PH */
12687	2075,	12687	2075,
12688	/* ADDQ_PH_MM */	12688	/* ADDQ_PH_MM */
12689	2078,	12689	2078,
12690	/* ADDQ_S_PH */	12690	/* ADDQ_S_PH */
12691	2081,	12691	2081,
12692	/* ADDQ_S_PH_MM */	12692	/* ADDQ_S_PH_MM */
12693	2084,	12693	2084,
12694	/* ADDQ_S_W */	12694	/* ADDQ_S_W */
12695	2087,	12695	2087,
12696	/* ADDQ_S_W_MM */	12696	/* ADDQ_S_W_MM */
12697	2090,	12697	2090,
12698	/* ADDR_PS64 */	12698	/* ADDR_PS64 */
12699	2093,	12699	2093,
12700	/* ADDSC */	12700	/* ADDSC */
12701	2096,	12701	2096,
12702	/* ADDSC_MM */	12702	/* ADDSC_MM */
12703	2099,	12703	2099,
12704	/* ADDS_A_B */	12704	/* ADDS_A_B */
12705	2102,	12705	2102,
12706	/* ADDS_A_D */	12706	/* ADDS_A_D */
12707	2105,	12707	2105,
12708	/* ADDS_A_H */	12708	/* ADDS_A_H */
12709	2108,	12709	2108,
12710	/* ADDS_A_W */	12710	/* ADDS_A_W */
12711	2111,	12711	2111,
12712	/* ADDS_S_B */	12712	/* ADDS_S_B */
12713	2114,	12713	2114,
12714	/* ADDS_S_D */	12714	/* ADDS_S_D */
12715	2117,	12715	2117,
12716	/* ADDS_S_H */	12716	/* ADDS_S_H */
12717	2120,	12717	2120,
12718	/* ADDS_S_W */	12718	/* ADDS_S_W */
12719	2123,	12719	2123,
12720	/* ADDS_U_B */	12720	/* ADDS_U_B */
12721	2126,	12721	2126,
12722	/* ADDS_U_D */	12722	/* ADDS_U_D */
12723	2129,	12723	2129,
12724	/* ADDS_U_H */	12724	/* ADDS_U_H */
12725	2132,	12725	2132,
12726	/* ADDS_U_W */	12726	/* ADDS_U_W */
12727	2135,	12727	2135,
12728	/* ADDU16_MM */	12728	/* ADDU16_MM */
12729	2138,	12729	2138,
12730	/* ADDU16_MMR6 */	12730	/* ADDU16_MMR6 */
12731	2141,	12731	2141,
12732	/* ADDUH_QB */	12732	/* ADDUH_QB */
12733	2144,	12733	2144,
12734	/* ADDUH_QB_MMR2 */	12734	/* ADDUH_QB_MMR2 */
12735	2147,	12735	2147,
12736	/* ADDUH_R_QB */	12736	/* ADDUH_R_QB */
12737	2150,	12737	2150,
12738	/* ADDUH_R_QB_MMR2 */	12738	/* ADDUH_R_QB_MMR2 */
12739	2153,	12739	2153,
12740	/* ADDU_MMR6 */	12740	/* ADDU_MMR6 */
12741	2156,	12741	2156,
12742	/* ADDU_PH */	12742	/* ADDU_PH */
12743	2159,	12743	2159,
12744	/* ADDU_PH_MMR2 */	12744	/* ADDU_PH_MMR2 */
12745	2162,	12745	2162,
12746	/* ADDU_QB */	12746	/* ADDU_QB */
12747	2165,	12747	2165,
12748	/* ADDU_QB_MM */	12748	/* ADDU_QB_MM */
12749	2168,	12749	2168,
12750	/* ADDU_S_PH */	12750	/* ADDU_S_PH */
12751	2171,	12751	2171,
12752	/* ADDU_S_PH_MMR2 */	12752	/* ADDU_S_PH_MMR2 */
12753	2174,	12753	2174,
12754	/* ADDU_S_QB */	12754	/* ADDU_S_QB */
12755	2177,	12755	2177,
12756	/* ADDU_S_QB_MM */	12756	/* ADDU_S_QB_MM */
12757	2180,	12757	2180,
12758	/* ADDVI_B */	12758	/* ADDVI_B */
12759	2183,	12759	2183,
12760	/* ADDVI_D */	12760	/* ADDVI_D */
12761	2186,	12761	2186,
12762	/* ADDVI_H */	12762	/* ADDVI_H */
12763	2189,	12763	2189,
12764	/* ADDVI_W */	12764	/* ADDVI_W */
12765	2192,	12765	2192,
12766	/* ADDV_B */	12766	/* ADDV_B */
12767	2195,	12767	2195,
12768	/* ADDV_D */	12768	/* ADDV_D */
12769	2198,	12769	2198,
12770	/* ADDV_H */	12770	/* ADDV_H */
12771	2201,	12771	2201,
12772	/* ADDV_W */	12772	/* ADDV_W */
12773	2204,	12773	2204,
12774	/* ADDWC */	12774	/* ADDWC */
12775	2207,	12775	2207,
12776	/* ADDWC_MM */	12776	/* ADDWC_MM */
12777	2210,	12777	2210,
12778	/* ADD_A_B */	12778	/* ADD_A_B */
12779	2213,	12779	2213,
12780	/* ADD_A_D */	12780	/* ADD_A_D */
12781	2216,	12781	2216,
12782	/* ADD_A_H */	12782	/* ADD_A_H */
12783	2219,	12783	2219,
12784	/* ADD_A_W */	12784	/* ADD_A_W */
12785	2222,	12785	2222,
12786	/* ADD_MM */	12786	/* ADD_MM */
12787	2225,	12787	2225,
12788	/* ADD_MMR6 */	12788	/* ADD_MMR6 */
12789	2228,	12789	2228,
12790	/* ADDi */	12790	/* ADDi */
12791	2231,	12791	2231,
12792	/* ADDi_MM */	12792	/* ADDi_MM */
12793	2234,	12793	2234,
12794	/* ADDiu */	12794	/* ADDiu */
12795	2237,	12795	2237,
12796	/* ADDiu_MM */	12796	/* ADDiu_MM */
12797	2240,	12797	2240,
12798	/* ADDu */	12798	/* ADDu */
12799	2243,	12799	2243,
12800	/* ADDu_MM */	12800	/* ADDu_MM */
12801	2246,	12801	2246,
12802	/* ALIGN */	12802	/* ALIGN */
12803	2249,	12803	2249,
12804	/* ALIGN_MMR6 */	12804	/* ALIGN_MMR6 */
12805	2253,	12805	2253,
12806	/* ALUIPC */	12806	/* ALUIPC */
12807	2257,	12807	2257,
12808	/* ALUIPC_MMR6 */	12808	/* ALUIPC_MMR6 */
12809	2259,	12809	2259,
12810	/* AND */	12810	/* AND */
12811	2261,	12811	2261,
12812	/* AND16_MM */	12812	/* AND16_MM */
12813	2264,	12813	2264,
12814	/* AND16_MMR6 */	12814	/* AND16_MMR6 */
12815	2267,	12815	2267,
12816	/* AND64 */	12816	/* AND64 */
12817	2270,	12817	2270,
12818	/* ANDI16_MM */	12818	/* ANDI16_MM */
12819	2273,	12819	2273,
12820	/* ANDI16_MMR6 */	12820	/* ANDI16_MMR6 */
12821	2276,	12821	2276,
12822	/* ANDI_B */	12822	/* ANDI_B */
12823	2279,	12823	2279,
12824	/* ANDI_MMR6 */	12824	/* ANDI_MMR6 */
12825	2282,	12825	2282,
12826	/* AND_MM */	12826	/* AND_MM */
12827	2285,	12827	2285,
12828	/* AND_MMR6 */	12828	/* AND_MMR6 */
12829	2288,	12829	2288,
12830	/* AND_V */	12830	/* AND_V */
12831	2291,	12831	2291,
12832	/* ANDi */	12832	/* ANDi */
12833	2294,	12833	2294,
12834	/* ANDi64 */	12834	/* ANDi64 */
12835	2297,	12835	2297,
12836	/* ANDi_MM */	12836	/* ANDi_MM */
12837	2300,	12837	2300,
12838	/* APPEND */	12838	/* APPEND */
12839	2303,	12839	2303,
12840	/* APPEND_MMR2 */	12840	/* APPEND_MMR2 */
12841	2307,	12841	2307,
12842	/* ASUB_S_B */	12842	/* ASUB_S_B */
12843	2311,	12843	2311,
12844	/* ASUB_S_D */	12844	/* ASUB_S_D */
12845	2314,	12845	2314,
12846	/* ASUB_S_H */	12846	/* ASUB_S_H */
12847	2317,	12847	2317,
12848	/* ASUB_S_W */	12848	/* ASUB_S_W */
12849	2320,	12849	2320,
12850	/* ASUB_U_B */	12850	/* ASUB_U_B */
12851	2323,	12851	2323,
12852	/* ASUB_U_D */	12852	/* ASUB_U_D */
12853	2326,	12853	2326,
12854	/* ASUB_U_H */	12854	/* ASUB_U_H */
12855	2329,	12855	2329,
12856	/* ASUB_U_W */	12856	/* ASUB_U_W */
12857	2332,	12857	2332,
12858	/* AUI */	12858	/* AUI */
12859	2335,	12859	2335,
12860	/* AUIPC */	12860	/* AUIPC */
12861	2338,	12861	2338,
12862	/* AUIPC_MMR6 */	12862	/* AUIPC_MMR6 */
12863	2340,	12863	2340,
12864	/* AUI_MMR6 */	12864	/* AUI_MMR6 */
12865	2342,	12865	2342,
12866	/* AVER_S_B */	12866	/* AVER_S_B */
12867	2345,	12867	2345,
12868	/* AVER_S_D */	12868	/* AVER_S_D */
12869	2348,	12869	2348,
12870	/* AVER_S_H */	12870	/* AVER_S_H */
12871	2351,	12871	2351,
12872	/* AVER_S_W */	12872	/* AVER_S_W */
12873	2354,	12873	2354,
12874	/* AVER_U_B */	12874	/* AVER_U_B */
12875	2357,	12875	2357,
12876	/* AVER_U_D */	12876	/* AVER_U_D */
12877	2360,	12877	2360,
12878	/* AVER_U_H */	12878	/* AVER_U_H */
12879	2363,	12879	2363,
12880	/* AVER_U_W */	12880	/* AVER_U_W */
12881	2366,	12881	2366,
12882	/* AVE_S_B */	12882	/* AVE_S_B */
12883	2369,	12883	2369,
12884	/* AVE_S_D */	12884	/* AVE_S_D */
12885	2372,	12885	2372,
12886	/* AVE_S_H */	12886	/* AVE_S_H */
12887	2375,	12887	2375,
12888	/* AVE_S_W */	12888	/* AVE_S_W */
12889	2378,	12889	2378,
12890	/* AVE_U_B */	12890	/* AVE_U_B */
12891	2381,	12891	2381,
12892	/* AVE_U_D */	12892	/* AVE_U_D */
12893	2384,	12893	2384,
12894	/* AVE_U_H */	12894	/* AVE_U_H */
12895	2387,	12895	2387,
12896	/* AVE_U_W */	12896	/* AVE_U_W */
12897	2390,	12897	2390,
12898	/* AddiuRxImmX16 */	12898	/* AddiuRxImmX16 */
12899	2393,	12899	2393,
12900	/* AddiuRxPcImmX16 */	12900	/* AddiuRxPcImmX16 */
12901	2395,	12901	2395,
12902	/* AddiuRxRxImm16 */	12902	/* AddiuRxRxImm16 */
12903	2397,	12903	2397,
12904	/* AddiuRxRxImmX16 */	12904	/* AddiuRxRxImmX16 */
12905	2400,	12905	2400,
12906	/* AddiuRxRyOffMemX16 */	12906	/* AddiuRxRyOffMemX16 */
12907	2403,	12907	2403,
12908	/* AddiuSpImm16 */	12908	/* AddiuSpImm16 */
12909	2406,	12909	2406,
12910	/* AddiuSpImmX16 */	12910	/* AddiuSpImmX16 */
12911	2407,	12911	2407,
12912	/* AdduRxRyRz16 */	12912	/* AdduRxRyRz16 */
12913	2408,	12913	2408,
12914	/* AndRxRxRy16 */	12914	/* AndRxRxRy16 */
12915	2411,	12915	2411,
12916	/* B16_MM */	12916	/* B16_MM */
12917	2414,	12917	2414,
12918	/* BADDu */	12918	/* BADDu */
12919	2415,	12919	2415,
12920	/* BAL */	12920	/* BAL */
12921	2418,	12921	2418,
12922	/* BALC */	12922	/* BALC */
12923	2419,	12923	2419,
12924	/* BALC_MMR6 */	12924	/* BALC_MMR6 */
12925	2420,	12925	2420,
12926	/* BALIGN */	12926	/* BALIGN */
12927	2421,	12927	2421,
12928	/* BALIGN_MMR2 */	12928	/* BALIGN_MMR2 */
12929	2425,	12929	2425,
12930	/* BBIT0 */	12930	/* BBIT0 */
12931	2429,	12931	2429,
12932	/* BBIT032 */	12932	/* BBIT032 */
12933	2432,	12933	2432,
12934	/* BBIT1 */	12934	/* BBIT1 */
12935	2435,	12935	2435,
12936	/* BBIT132 */	12936	/* BBIT132 */
12937	2438,	12937	2438,
12938	/* BC */	12938	/* BC */
12939	2441,	12939	2441,
12940	/* BC16_MMR6 */	12940	/* BC16_MMR6 */
12941	2442,	12941	2442,
12942	/* BC1EQZ */	12942	/* BC1EQZ */
12943	2443,	12943	2443,
12944	/* BC1EQZC_MMR6 */	12944	/* BC1EQZC_MMR6 */
12945	2445,	12945	2445,
12946	/* BC1F */	12946	/* BC1F */
12947	2447,	12947	2447,
12948	/* BC1FL */	12948	/* BC1FL */
12949	2449,	12949	2449,
12950	/* BC1F_MM */	12950	/* BC1F_MM */
12951	2451,	12951	2451,
12952	/* BC1NEZ */	12952	/* BC1NEZ */
12953	2453,	12953	2453,
12954	/* BC1NEZC_MMR6 */	12954	/* BC1NEZC_MMR6 */
12955	2455,	12955	2455,
12956	/* BC1T */	12956	/* BC1T */
12957	2457,	12957	2457,
12958	/* BC1TL */	12958	/* BC1TL */
12959	2459,	12959	2459,
12960	/* BC1T_MM */	12960	/* BC1T_MM */
12961	2461,	12961	2461,
12962	/* BC2EQZ */	12962	/* BC2EQZ */
12963	2463,	12963	2463,
12964	/* BC2EQZC_MMR6 */	12964	/* BC2EQZC_MMR6 */
12965	2465,	12965	2465,
12966	/* BC2NEZ */	12966	/* BC2NEZ */
12967	2467,	12967	2467,
12968	/* BC2NEZC_MMR6 */	12968	/* BC2NEZC_MMR6 */
12969	2469,	12969	2469,
12970	/* BCLRI_B */	12970	/* BCLRI_B */
12971	2471,	12971	2471,
12972	/* BCLRI_D */	12972	/* BCLRI_D */
12973	2474,	12973	2474,
12974	/* BCLRI_H */	12974	/* BCLRI_H */
12975	2477,	12975	2477,
12976	/* BCLRI_W */	12976	/* BCLRI_W */
12977	2480,	12977	2480,
12978	/* BCLR_B */	12978	/* BCLR_B */
12979	2483,	12979	2483,
12980	/* BCLR_D */	12980	/* BCLR_D */
12981	2486,	12981	2486,
12982	/* BCLR_H */	12982	/* BCLR_H */
12983	2489,	12983	2489,
12984	/* BCLR_W */	12984	/* BCLR_W */
12985	2492,	12985	2492,
12986	/* BC_MMR6 */	12986	/* BC_MMR6 */
12987	2495,	12987	2495,
12988	/* BEQ */	12988	/* BEQ */
12989	2496,	12989	2496,
12990	/* BEQ64 */	12990	/* BEQ64 */
12991	2499,	12991	2499,
12992	/* BEQC */	12992	/* BEQC */
12993	2502,	12993	2502,
12994	/* BEQC64 */	12994	/* BEQC64 */
12995	2505,	12995	2505,
12996	/* BEQC_MMR6 */	12996	/* BEQC_MMR6 */
12997	2508,	12997	2508,
12998	/* BEQL */	12998	/* BEQL */
12999	2511,	12999	2511,
13000	/* BEQZ16_MM */	13000	/* BEQZ16_MM */
13001	2514,	13001	2514,
13002	/* BEQZALC */	13002	/* BEQZALC */
13003	2516,	13003	2516,
13004	/* BEQZALC_MMR6 */	13004	/* BEQZALC_MMR6 */
13005	2518,	13005	2518,
13006	/* BEQZC */	13006	/* BEQZC */
13007	2520,	13007	2520,
13008	/* BEQZC16_MMR6 */	13008	/* BEQZC16_MMR6 */
13009	2522,	13009	2522,
13010	/* BEQZC64 */	13010	/* BEQZC64 */
13011	2524,	13011	2524,
13012	/* BEQZC_MM */	13012	/* BEQZC_MM */
13013	2526,	13013	2526,
13014	/* BEQZC_MMR6 */	13014	/* BEQZC_MMR6 */
13015	2528,	13015	2528,
13016	/* BEQ_MM */	13016	/* BEQ_MM */
13017	2530,	13017	2530,
13018	/* BGEC */	13018	/* BGEC */
13019	2533,	13019	2533,
13020	/* BGEC64 */	13020	/* BGEC64 */
13021	2536,	13021	2536,
13022	/* BGEC_MMR6 */	13022	/* BGEC_MMR6 */
13023	2539,	13023	2539,
13024	/* BGEUC */	13024	/* BGEUC */
13025	2542,	13025	2542,
13026	/* BGEUC64 */	13026	/* BGEUC64 */
13027	2545,	13027	2545,
13028	/* BGEUC_MMR6 */	13028	/* BGEUC_MMR6 */
13029	2548,	13029	2548,
13030	/* BGEZ */	13030	/* BGEZ */
13031	2551,	13031	2551,
13032	/* BGEZ64 */	13032	/* BGEZ64 */
13033	2553,	13033	2553,
13034	/* BGEZAL */	13034	/* BGEZAL */
13035	2555,	13035	2555,
13036	/* BGEZALC */	13036	/* BGEZALC */
13037	2557,	13037	2557,
13038	/* BGEZALC_MMR6 */	13038	/* BGEZALC_MMR6 */
13039	2559,	13039	2559,
13040	/* BGEZALL */	13040	/* BGEZALL */
13041	2561,	13041	2561,
13042	/* BGEZALS_MM */	13042	/* BGEZALS_MM */
13043	2563,	13043	2563,
13044	/* BGEZAL_MM */	13044	/* BGEZAL_MM */
13045	2565,	13045	2565,
13046	/* BGEZC */	13046	/* BGEZC */
13047	2567,	13047	2567,
13048	/* BGEZC64 */	13048	/* BGEZC64 */
13049	2569,	13049	2569,
13050	/* BGEZC_MMR6 */	13050	/* BGEZC_MMR6 */
13051	2571,	13051	2571,
13052	/* BGEZL */	13052	/* BGEZL */
13053	2573,	13053	2573,
13054	/* BGEZ_MM */	13054	/* BGEZ_MM */
13055	2575,	13055	2575,
13056	/* BGTZ */	13056	/* BGTZ */
13057	2577,	13057	2577,
13058	/* BGTZ64 */	13058	/* BGTZ64 */
13059	2579,	13059	2579,
13060	/* BGTZALC */	13060	/* BGTZALC */
13061	2581,	13061	2581,
13062	/* BGTZALC_MMR6 */	13062	/* BGTZALC_MMR6 */
13063	2583,	13063	2583,
13064	/* BGTZC */	13064	/* BGTZC */
13065	2585,	13065	2585,
13066	/* BGTZC64 */	13066	/* BGTZC64 */
13067	2587,	13067	2587,
13068	/* BGTZC_MMR6 */	13068	/* BGTZC_MMR6 */
13069	2589,	13069	2589,
13070	/* BGTZL */	13070	/* BGTZL */
13071	2591,	13071	2591,
13072	/* BGTZ_MM */	13072	/* BGTZ_MM */
13073	2593,	13073	2593,
13074	/* BINSLI_B */	13074	/* BINSLI_B */
13075	2595,	13075	2595,
13076	/* BINSLI_D */	13076	/* BINSLI_D */
13077	2599,	13077	2599,
13078	/* BINSLI_H */	13078	/* BINSLI_H */
13079	2603,	13079	2603,
13080	/* BINSLI_W */	13080	/* BINSLI_W */
13081	2607,	13081	2607,
13082	/* BINSL_B */	13082	/* BINSL_B */
13083	2611,	13083	2611,
13084	/* BINSL_D */	13084	/* BINSL_D */
13085	2615,	13085	2615,
13086	/* BINSL_H */	13086	/* BINSL_H */
13087	2619,	13087	2619,
13088	/* BINSL_W */	13088	/* BINSL_W */
13089	2623,	13089	2623,
13090	/* BINSRI_B */	13090	/* BINSRI_B */
13091	2627,	13091	2627,
13092	/* BINSRI_D */	13092	/* BINSRI_D */
13093	2631,	13093	2631,
13094	/* BINSRI_H */	13094	/* BINSRI_H */
13095	2635,	13095	2635,
13096	/* BINSRI_W */	13096	/* BINSRI_W */
13097	2639,	13097	2639,
13098	/* BINSR_B */	13098	/* BINSR_B */
13099	2643,	13099	2643,
13100	/* BINSR_D */	13100	/* BINSR_D */
13101	2647,	13101	2647,
13102	/* BINSR_H */	13102	/* BINSR_H */
13103	2651,	13103	2651,
13104	/* BINSR_W */	13104	/* BINSR_W */
13105	2655,	13105	2655,
13106	/* BITREV */	13106	/* BITREV */
13107	2659,	13107	2659,
13108	/* BITREV_MM */	13108	/* BITREV_MM */
13109	2661,	13109	2661,
13110	/* BITSWAP */	13110	/* BITSWAP */
13111	2663,	13111	2663,
13112	/* BITSWAP_MMR6 */	13112	/* BITSWAP_MMR6 */
13113	2665,	13113	2665,
13114	/* BLEZ */	13114	/* BLEZ */
13115	2667,	13115	2667,
13116	/* BLEZ64 */	13116	/* BLEZ64 */
13117	2669,	13117	2669,
13118	/* BLEZALC */	13118	/* BLEZALC */
13119	2671,	13119	2671,
13120	/* BLEZALC_MMR6 */	13120	/* BLEZALC_MMR6 */
13121	2673,	13121	2673,
13122	/* BLEZC */	13122	/* BLEZC */
13123	2675,	13123	2675,
13124	/* BLEZC64 */	13124	/* BLEZC64 */
13125	2677,	13125	2677,
13126	/* BLEZC_MMR6 */	13126	/* BLEZC_MMR6 */
13127	2679,	13127	2679,
13128	/* BLEZL */	13128	/* BLEZL */
13129	2681,	13129	2681,
13130	/* BLEZ_MM */	13130	/* BLEZ_MM */
13131	2683,	13131	2683,
13132	/* BLTC */	13132	/* BLTC */
13133	2685,	13133	2685,
13134	/* BLTC64 */	13134	/* BLTC64 */
13135	2688,	13135	2688,
13136	/* BLTC_MMR6 */	13136	/* BLTC_MMR6 */
13137	2691,	13137	2691,
13138	/* BLTUC */	13138	/* BLTUC */
13139	2694,	13139	2694,
13140	/* BLTUC64 */	13140	/* BLTUC64 */
13141	2697,	13141	2697,
13142	/* BLTUC_MMR6 */	13142	/* BLTUC_MMR6 */
13143	2700,	13143	2700,
13144	/* BLTZ */	13144	/* BLTZ */
13145	2703,	13145	2703,
13146	/* BLTZ64 */	13146	/* BLTZ64 */
13147	2705,	13147	2705,
13148	/* BLTZAL */	13148	/* BLTZAL */
13149	2707,	13149	2707,
13150	/* BLTZALC */	13150	/* BLTZALC */
13151	2709,	13151	2709,
13152	/* BLTZALC_MMR6 */	13152	/* BLTZALC_MMR6 */
13153	2711,	13153	2711,
13154	/* BLTZALL */	13154	/* BLTZALL */
13155	2713,	13155	2713,
13156	/* BLTZALS_MM */	13156	/* BLTZALS_MM */
13157	2715,	13157	2715,
13158	/* BLTZAL_MM */	13158	/* BLTZAL_MM */
13159	2717,	13159	2717,
13160	/* BLTZC */	13160	/* BLTZC */
13161	2719,	13161	2719,
13162	/* BLTZC64 */	13162	/* BLTZC64 */
13163	2721,	13163	2721,
13164	/* BLTZC_MMR6 */	13164	/* BLTZC_MMR6 */
13165	2723,	13165	2723,
13166	/* BLTZL */	13166	/* BLTZL */
13167	2725,	13167	2725,
13168	/* BLTZ_MM */	13168	/* BLTZ_MM */
13169	2727,	13169	2727,
13170	/* BMNZI_B */	13170	/* BMNZI_B */
13171	2729,	13171	2729,
13172	/* BMNZ_V */	13172	/* BMNZ_V */
13173	2733,	13173	2733,
13174	/* BMZI_B */	13174	/* BMZI_B */
13175	2737,	13175	2737,
13176	/* BMZ_V */	13176	/* BMZ_V */
13177	2741,	13177	2741,
13178	/* BNE */	13178	/* BNE */
13179	2745,	13179	2745,
13180	/* BNE64 */	13180	/* BNE64 */
13181	2748,	13181	2748,
13182	/* BNEC */	13182	/* BNEC */
13183	2751,	13183	2751,
13184	/* BNEC64 */	13184	/* BNEC64 */
13185	2754,	13185	2754,
13186	/* BNEC_MMR6 */	13186	/* BNEC_MMR6 */
13187	2757,	13187	2757,
13188	/* BNEGI_B */	13188	/* BNEGI_B */
13189	2760,	13189	2760,
13190	/* BNEGI_D */	13190	/* BNEGI_D */
13191	2763,	13191	2763,
13192	/* BNEGI_H */	13192	/* BNEGI_H */
13193	2766,	13193	2766,
13194	/* BNEGI_W */	13194	/* BNEGI_W */
13195	2769,	13195	2769,
13196	/* BNEG_B */	13196	/* BNEG_B */
13197	2772,	13197	2772,
13198	/* BNEG_D */	13198	/* BNEG_D */
13199	2775,	13199	2775,
13200	/* BNEG_H */	13200	/* BNEG_H */
13201	2778,	13201	2778,
13202	/* BNEG_W */	13202	/* BNEG_W */
13203	2781,	13203	2781,
13204	/* BNEL */	13204	/* BNEL */
13205	2784,	13205	2784,
13206	/* BNEZ16_MM */	13206	/* BNEZ16_MM */
13207	2787,	13207	2787,
13208	/* BNEZALC */	13208	/* BNEZALC */
13209	2789,	13209	2789,
13210	/* BNEZALC_MMR6 */	13210	/* BNEZALC_MMR6 */
13211	2791,	13211	2791,
13212	/* BNEZC */	13212	/* BNEZC */
13213	2793,	13213	2793,
13214	/* BNEZC16_MMR6 */	13214	/* BNEZC16_MMR6 */
13215	2795,	13215	2795,
13216	/* BNEZC64 */	13216	/* BNEZC64 */
13217	2797,	13217	2797,
13218	/* BNEZC_MM */	13218	/* BNEZC_MM */
13219	2799,	13219	2799,
13220	/* BNEZC_MMR6 */	13220	/* BNEZC_MMR6 */
13221	2801,	13221	2801,
13222	/* BNE_MM */	13222	/* BNE_MM */
13223	2803,	13223	2803,
13224	/* BNVC */	13224	/* BNVC */
13225	2806,	13225	2806,
13226	/* BNVC_MMR6 */	13226	/* BNVC_MMR6 */
13227	2809,	13227	2809,
13228	/* BNZ_B */	13228	/* BNZ_B */
13229	2812,	13229	2812,
13230	/* BNZ_D */	13230	/* BNZ_D */
13231	2814,	13231	2814,
13232	/* BNZ_H */	13232	/* BNZ_H */
13233	2816,	13233	2816,
13234	/* BNZ_V */	13234	/* BNZ_V */
13235	2818,	13235	2818,
13236	/* BNZ_W */	13236	/* BNZ_W */
13237	2820,	13237	2820,
13238	/* BOVC */	13238	/* BOVC */
13239	2822,	13239	2822,
13240	/* BOVC_MMR6 */	13240	/* BOVC_MMR6 */
13241	2825,	13241	2825,
13242	/* BPOSGE32 */	13242	/* BPOSGE32 */
13243	2828,	13243	2828,
13244	/* BPOSGE32C_MMR3 */	13244	/* BPOSGE32C_MMR3 */
13245	2829,	13245	2829,
13246	/* BPOSGE32_MM */	13246	/* BPOSGE32_MM */
13247	2830,	13247	2830,
13248	/* BREAK */	13248	/* BREAK */
13249	2831,	13249	2831,
13250	/* BREAK16_MM */	13250	/* BREAK16_MM */
13251	2833,	13251	2833,
13252	/* BREAK16_MMR6 */	13252	/* BREAK16_MMR6 */
13253	2834,	13253	2834,
13254	/* BREAK_MM */	13254	/* BREAK_MM */
13255	2835,	13255	2835,
13256	/* BREAK_MMR6 */	13256	/* BREAK_MMR6 */
13257	2837,	13257	2837,
13258	/* BSELI_B */	13258	/* BSELI_B */
13259	2839,	13259	2839,
13260	/* BSEL_V */	13260	/* BSEL_V */
13261	2843,	13261	2843,
13262	/* BSETI_B */	13262	/* BSETI_B */
13263	2847,	13263	2847,
13264	/* BSETI_D */	13264	/* BSETI_D */
13265	2850,	13265	2850,
13266	/* BSETI_H */	13266	/* BSETI_H */
13267	2853,	13267	2853,
13268	/* BSETI_W */	13268	/* BSETI_W */
13269	2856,	13269	2856,
13270	/* BSET_B */	13270	/* BSET_B */
13271	2859,	13271	2859,
13272	/* BSET_D */	13272	/* BSET_D */
13273	2862,	13273	2862,
13274	/* BSET_H */	13274	/* BSET_H */
13275	2865,	13275	2865,
13276	/* BSET_W */	13276	/* BSET_W */
13277	2868,	13277	2868,
13278	/* BZ_B */	13278	/* BZ_B */
13279	2871,	13279	2871,
13280	/* BZ_D */	13280	/* BZ_D */
13281	2873,	13281	2873,
13282	/* BZ_H */	13282	/* BZ_H */
13283	2875,	13283	2875,
13284	/* BZ_V */	13284	/* BZ_V */
13285	2877,	13285	2877,
13286	/* BZ_W */	13286	/* BZ_W */
13287	2879,	13287	2879,
13288	/* BeqzRxImm16 */	13288	/* BeqzRxImm16 */
13289	2881,	13289	2881,
13290	/* BeqzRxImmX16 */	13290	/* BeqzRxImmX16 */
13291	2883,	13291	2883,
13292	/* Bimm16 */	13292	/* Bimm16 */
13293	2885,	13293	2885,
13294	/* BimmX16 */	13294	/* BimmX16 */
13295	2886,	13295	2886,
13296	/* BnezRxImm16 */	13296	/* BnezRxImm16 */
13297	2887,	13297	2887,
13298	/* BnezRxImmX16 */	13298	/* BnezRxImmX16 */
13299	2889,	13299	2889,
13300	/* Break16 */	13300	/* Break16 */
13301	2891,	13301	2891,
13302	/* Bteqz16 */	13302	/* Bteqz16 */
13303	2891,	13303	2891,
13304	/* BteqzX16 */	13304	/* BteqzX16 */
13305	2892,	13305	2892,
13306	/* Btnez16 */	13306	/* Btnez16 */
13307	2893,	13307	2893,
13308	/* BtnezX16 */	13308	/* BtnezX16 */
13309	2894,	13309	2894,
13310	/* CACHE */	13310	/* CACHE */
13311	2895,	13311	2895,
13312	/* CACHEE */	13312	/* CACHEE */
13313	2898,	13313	2898,
13314	/* CACHEE_MM */	13314	/* CACHEE_MM */
13315	2901,	13315	2901,
13316	/* CACHE_MM */	13316	/* CACHE_MM */
13317	2904,	13317	2904,
13318	/* CACHE_MMR6 */	13318	/* CACHE_MMR6 */
13319	2907,	13319	2907,
13320	/* CACHE_R6 */	13320	/* CACHE_R6 */
13321	2910,	13321	2910,
13322	/* CEIL_L_D64 */	13322	/* CEIL_L_D64 */
13323	2913,	13323	2913,
13324	/* CEIL_L_D_MMR6 */	13324	/* CEIL_L_D_MMR6 */
13325	2915,	13325	2915,
13326	/* CEIL_L_S */	13326	/* CEIL_L_S */
13327	2917,	13327	2917,
13328	/* CEIL_L_S_MMR6 */	13328	/* CEIL_L_S_MMR6 */
13329	2919,	13329	2919,
13330	/* CEIL_W_D32 */	13330	/* CEIL_W_D32 */
13331	2921,	13331	2921,
13332	/* CEIL_W_D64 */	13332	/* CEIL_W_D64 */
13333	2923,	13333	2923,
13334	/* CEIL_W_D_MMR6 */	13334	/* CEIL_W_D_MMR6 */
13335	2925,	13335	2925,
13336	/* CEIL_W_MM */	13336	/* CEIL_W_MM */
13337	2927,	13337	2927,
13338	/* CEIL_W_S */	13338	/* CEIL_W_S */
13339	2929,	13339	2929,
13340	/* CEIL_W_S_MM */	13340	/* CEIL_W_S_MM */
13341	2931,	13341	2931,
13342	/* CEIL_W_S_MMR6 */	13342	/* CEIL_W_S_MMR6 */
13343	2933,	13343	2933,
13344	/* CEQI_B */	13344	/* CEQI_B */
13345	2935,	13345	2935,
13346	/* CEQI_D */	13346	/* CEQI_D */
13347	2938,	13347	2938,
13348	/* CEQI_H */	13348	/* CEQI_H */
13349	2941,	13349	2941,
13350	/* CEQI_W */	13350	/* CEQI_W */
13351	2944,	13351	2944,
13352	/* CEQ_B */	13352	/* CEQ_B */
13353	2947,	13353	2947,
13354	/* CEQ_D */	13354	/* CEQ_D */
13355	2950,	13355	2950,
13356	/* CEQ_H */	13356	/* CEQ_H */
13357	2953,	13357	2953,
13358	/* CEQ_W */	13358	/* CEQ_W */
13359	2956,	13359	2956,
13360	/* CFC1 */	13360	/* CFC1 */
13361	2959,	13361	2959,
13362	/* CFC1_MM */	13362	/* CFC1_MM */
13363	2961,	13363	2961,
13364	/* CFC2_MM */	13364	/* CFC2_MM */
13365	2963,	13365	2963,
13366	/* CFCMSA */	13366	/* CFCMSA */
13367	2965,	13367	2965,
13368	/* CINS */	13368	/* CINS */
13369	2967,	13369	2967,
13370	/* CINS32 */	13370	/* CINS32 */
13371	2971,	13371	2971,
13372	/* CINS64_32 */	13372	/* CINS64_32 */
13373	2975,	13373	2975,
13374	/* CINS_i32 */	13374	/* CINS_i32 */
13375	2979,	13375	2979,
13376	/* CLASS_D */	13376	/* CLASS_D */
13377	2983,	13377	2983,
13378	/* CLASS_D_MMR6 */	13378	/* CLASS_D_MMR6 */
13379	2985,	13379	2985,
13380	/* CLASS_S */	13380	/* CLASS_S */
13381	2987,	13381	2987,
13382	/* CLASS_S_MMR6 */	13382	/* CLASS_S_MMR6 */
13383	2989,	13383	2989,
13384	/* CLEI_S_B */	13384	/* CLEI_S_B */
13385	2991,	13385	2991,
13386	/* CLEI_S_D */	13386	/* CLEI_S_D */
13387	2994,	13387	2994,
13388	/* CLEI_S_H */	13388	/* CLEI_S_H */
13389	2997,	13389	2997,
13390	/* CLEI_S_W */	13390	/* CLEI_S_W */
13391	3000,	13391	3000,
13392	/* CLEI_U_B */	13392	/* CLEI_U_B */
13393	3003,	13393	3003,
13394	/* CLEI_U_D */	13394	/* CLEI_U_D */
13395	3006,	13395	3006,
13396	/* CLEI_U_H */	13396	/* CLEI_U_H */
13397	3009,	13397	3009,
13398	/* CLEI_U_W */	13398	/* CLEI_U_W */
13399	3012,	13399	3012,
13400	/* CLE_S_B */	13400	/* CLE_S_B */
13401	3015,	13401	3015,
13402	/* CLE_S_D */	13402	/* CLE_S_D */
13403	3018,	13403	3018,
13404	/* CLE_S_H */	13404	/* CLE_S_H */
13405	3021,	13405	3021,
13406	/* CLE_S_W */	13406	/* CLE_S_W */
13407	3024,	13407	3024,
13408	/* CLE_U_B */	13408	/* CLE_U_B */
13409	3027,	13409	3027,
13410	/* CLE_U_D */	13410	/* CLE_U_D */
13411	3030,	13411	3030,
13412	/* CLE_U_H */	13412	/* CLE_U_H */
13413	3033,	13413	3033,
13414	/* CLE_U_W */	13414	/* CLE_U_W */
13415	3036,	13415	3036,
13416	/* CLO */	13416	/* CLO */
13417	3039,	13417	3039,
13418	/* CLO_MM */	13418	/* CLO_MM */
13419	3041,	13419	3041,
13420	/* CLO_MMR6 */	13420	/* CLO_MMR6 */
13421	3043,	13421	3043,
13422	/* CLO_R6 */	13422	/* CLO_R6 */
13423	3045,	13423	3045,
13424	/* CLTI_S_B */	13424	/* CLTI_S_B */
13425	3047,	13425	3047,
13426	/* CLTI_S_D */	13426	/* CLTI_S_D */
13427	3050,	13427	3050,
13428	/* CLTI_S_H */	13428	/* CLTI_S_H */
13429	3053,	13429	3053,
13430	/* CLTI_S_W */	13430	/* CLTI_S_W */
13431	3056,	13431	3056,
13432	/* CLTI_U_B */	13432	/* CLTI_U_B */
13433	3059,	13433	3059,
13434	/* CLTI_U_D */	13434	/* CLTI_U_D */
13435	3062,	13435	3062,
13436	/* CLTI_U_H */	13436	/* CLTI_U_H */
13437	3065,	13437	3065,
13438	/* CLTI_U_W */	13438	/* CLTI_U_W */
13439	3068,	13439	3068,
13440	/* CLT_S_B */	13440	/* CLT_S_B */
13441	3071,	13441	3071,
13442	/* CLT_S_D */	13442	/* CLT_S_D */
13443	3074,	13443	3074,
13444	/* CLT_S_H */	13444	/* CLT_S_H */
13445	3077,	13445	3077,
13446	/* CLT_S_W */	13446	/* CLT_S_W */
13447	3080,	13447	3080,
13448	/* CLT_U_B */	13448	/* CLT_U_B */
13449	3083,	13449	3083,
13450	/* CLT_U_D */	13450	/* CLT_U_D */
13451	3086,	13451	3086,
13452	/* CLT_U_H */	13452	/* CLT_U_H */
13453	3089,	13453	3089,
13454	/* CLT_U_W */	13454	/* CLT_U_W */
13455	3092,	13455	3092,
13456	/* CLZ */	13456	/* CLZ */
13457	3095,	13457	3095,
13458	/* CLZ_MM */	13458	/* CLZ_MM */
13459	3097,	13459	3097,
13460	/* CLZ_MMR6 */	13460	/* CLZ_MMR6 */
13461	3099,	13461	3099,
13462	/* CLZ_R6 */	13462	/* CLZ_R6 */
13463	3101,	13463	3101,
13464	/* CMPGDU_EQ_QB */	13464	/* CMPGDU_EQ_QB */
13465	3103,	13465	3103,
13466	/* CMPGDU_EQ_QB_MMR2 */	13466	/* CMPGDU_EQ_QB_MMR2 */
13467	3106,	13467	3106,
13468	/* CMPGDU_LE_QB */	13468	/* CMPGDU_LE_QB */
13469	3109,	13469	3109,
13470	/* CMPGDU_LE_QB_MMR2 */	13470	/* CMPGDU_LE_QB_MMR2 */
13471	3112,	13471	3112,
13472	/* CMPGDU_LT_QB */	13472	/* CMPGDU_LT_QB */
13473	3115,	13473	3115,
13474	/* CMPGDU_LT_QB_MMR2 */	13474	/* CMPGDU_LT_QB_MMR2 */
13475	3118,	13475	3118,
13476	/* CMPGU_EQ_QB */	13476	/* CMPGU_EQ_QB */
13477	3121,	13477	3121,
13478	/* CMPGU_EQ_QB_MM */	13478	/* CMPGU_EQ_QB_MM */
13479	3124,	13479	3124,
13480	/* CMPGU_LE_QB */	13480	/* CMPGU_LE_QB */
13481	3127,	13481	3127,
13482	/* CMPGU_LE_QB_MM */	13482	/* CMPGU_LE_QB_MM */
13483	3130,	13483	3130,
13484	/* CMPGU_LT_QB */	13484	/* CMPGU_LT_QB */
13485	3133,	13485	3133,
13486	/* CMPGU_LT_QB_MM */	13486	/* CMPGU_LT_QB_MM */
13487	3136,	13487	3136,
13488	/* CMPU_EQ_QB */	13488	/* CMPU_EQ_QB */
13489	3139,	13489	3139,
13490	/* CMPU_EQ_QB_MM */	13490	/* CMPU_EQ_QB_MM */
13491	3141,	13491	3141,
13492	/* CMPU_LE_QB */	13492	/* CMPU_LE_QB */
13493	3143,	13493	3143,
13494	/* CMPU_LE_QB_MM */	13494	/* CMPU_LE_QB_MM */
13495	3145,	13495	3145,
13496	/* CMPU_LT_QB */	13496	/* CMPU_LT_QB */
13497	3147,	13497	3147,
13498	/* CMPU_LT_QB_MM */	13498	/* CMPU_LT_QB_MM */
13499	3149,	13499	3149,
13500	/* CMP_AF_D_MMR6 */	13500	/* CMP_AF_D_MMR6 */
13501	3151,	13501	3151,
13502	/* CMP_AF_S_MMR6 */	13502	/* CMP_AF_S_MMR6 */
13503	3154,	13503	3154,
13504	/* CMP_EQ_D */	13504	/* CMP_EQ_D */
13505	3157,	13505	3157,
13506	/* CMP_EQ_D_MMR6 */	13506	/* CMP_EQ_D_MMR6 */
13507	3160,	13507	3160,
13508	/* CMP_EQ_PH */	13508	/* CMP_EQ_PH */
13509	3163,	13509	3163,
13510	/* CMP_EQ_PH_MM */	13510	/* CMP_EQ_PH_MM */
13511	3165,	13511	3165,
13512	/* CMP_EQ_S */	13512	/* CMP_EQ_S */
13513	3167,	13513	3167,
13514	/* CMP_EQ_S_MMR6 */	13514	/* CMP_EQ_S_MMR6 */
13515	3170,	13515	3170,
13516	/* CMP_F_D */	13516	/* CMP_F_D */
13517	3173,	13517	3173,
13518	/* CMP_F_S */	13518	/* CMP_F_S */
13519	3176,	13519	3176,
13520	/* CMP_LE_D */	13520	/* CMP_LE_D */
13521	3179,	13521	3179,
13522	/* CMP_LE_D_MMR6 */	13522	/* CMP_LE_D_MMR6 */
13523	3182,	13523	3182,
13524	/* CMP_LE_PH */	13524	/* CMP_LE_PH */
13525	3185,	13525	3185,
13526	/* CMP_LE_PH_MM */	13526	/* CMP_LE_PH_MM */
13527	3187,	13527	3187,
13528	/* CMP_LE_S */	13528	/* CMP_LE_S */
13529	3189,	13529	3189,
13530	/* CMP_LE_S_MMR6 */	13530	/* CMP_LE_S_MMR6 */
13531	3192,	13531	3192,
13532	/* CMP_LT_D */	13532	/* CMP_LT_D */
13533	3195,	13533	3195,
13534	/* CMP_LT_D_MMR6 */	13534	/* CMP_LT_D_MMR6 */
13535	3198,	13535	3198,
13536	/* CMP_LT_PH */	13536	/* CMP_LT_PH */
13537	3201,	13537	3201,
13538	/* CMP_LT_PH_MM */	13538	/* CMP_LT_PH_MM */
13539	3203,	13539	3203,
13540	/* CMP_LT_S */	13540	/* CMP_LT_S */
13541	3205,	13541	3205,
13542	/* CMP_LT_S_MMR6 */	13542	/* CMP_LT_S_MMR6 */
13543	3208,	13543	3208,
13544	/* CMP_SAF_D */	13544	/* CMP_SAF_D */
13545	3211,	13545	3211,
13546	/* CMP_SAF_D_MMR6 */	13546	/* CMP_SAF_D_MMR6 */
13547	3214,	13547	3214,
13548	/* CMP_SAF_S */	13548	/* CMP_SAF_S */
13549	3217,	13549	3217,
13550	/* CMP_SAF_S_MMR6 */	13550	/* CMP_SAF_S_MMR6 */
13551	3220,	13551	3220,
13552	/* CMP_SEQ_D */	13552	/* CMP_SEQ_D */
13553	3223,	13553	3223,
13554	/* CMP_SEQ_D_MMR6 */	13554	/* CMP_SEQ_D_MMR6 */
13555	3226,	13555	3226,
13556	/* CMP_SEQ_S */	13556	/* CMP_SEQ_S */
13557	3229,	13557	3229,
13558	/* CMP_SEQ_S_MMR6 */	13558	/* CMP_SEQ_S_MMR6 */
13559	3232,	13559	3232,
13560	/* CMP_SLE_D */	13560	/* CMP_SLE_D */
13561	3235,	13561	3235,
13562	/* CMP_SLE_D_MMR6 */	13562	/* CMP_SLE_D_MMR6 */
13563	3238,	13563	3238,
13564	/* CMP_SLE_S */	13564	/* CMP_SLE_S */
13565	3241,	13565	3241,
13566	/* CMP_SLE_S_MMR6 */	13566	/* CMP_SLE_S_MMR6 */
13567	3244,	13567	3244,
13568	/* CMP_SLT_D */	13568	/* CMP_SLT_D */
13569	3247,	13569	3247,
13570	/* CMP_SLT_D_MMR6 */	13570	/* CMP_SLT_D_MMR6 */
13571	3250,	13571	3250,
13572	/* CMP_SLT_S */	13572	/* CMP_SLT_S */
13573	3253,	13573	3253,
13574	/* CMP_SLT_S_MMR6 */	13574	/* CMP_SLT_S_MMR6 */
13575	3256,	13575	3256,
13576	/* CMP_SUEQ_D */	13576	/* CMP_SUEQ_D */
13577	3259,	13577	3259,
13578	/* CMP_SUEQ_D_MMR6 */	13578	/* CMP_SUEQ_D_MMR6 */
13579	3262,	13579	3262,
13580	/* CMP_SUEQ_S */	13580	/* CMP_SUEQ_S */
13581	3265,	13581	3265,
13582	/* CMP_SUEQ_S_MMR6 */	13582	/* CMP_SUEQ_S_MMR6 */
13583	3268,	13583	3268,
13584	/* CMP_SULE_D */	13584	/* CMP_SULE_D */
13585	3271,	13585	3271,
13586	/* CMP_SULE_D_MMR6 */	13586	/* CMP_SULE_D_MMR6 */
13587	3274,	13587	3274,
13588	/* CMP_SULE_S */	13588	/* CMP_SULE_S */
13589	3277,	13589	3277,
13590	/* CMP_SULE_S_MMR6 */	13590	/* CMP_SULE_S_MMR6 */
13591	3280,	13591	3280,
13592	/* CMP_SULT_D */	13592	/* CMP_SULT_D */
13593	3283,	13593	3283,
13594	/* CMP_SULT_D_MMR6 */	13594	/* CMP_SULT_D_MMR6 */
13595	3286,	13595	3286,
13596	/* CMP_SULT_S */	13596	/* CMP_SULT_S */
13597	3289,	13597	3289,
13598	/* CMP_SULT_S_MMR6 */	13598	/* CMP_SULT_S_MMR6 */
13599	3292,	13599	3292,
13600	/* CMP_SUN_D */	13600	/* CMP_SUN_D */
13601	3295,	13601	3295,
13602	/* CMP_SUN_D_MMR6 */	13602	/* CMP_SUN_D_MMR6 */
13603	3298,	13603	3298,
13604	/* CMP_SUN_S */	13604	/* CMP_SUN_S */
13605	3301,	13605	3301,
13606	/* CMP_SUN_S_MMR6 */	13606	/* CMP_SUN_S_MMR6 */
13607	3304,	13607	3304,
13608	/* CMP_UEQ_D */	13608	/* CMP_UEQ_D */
13609	3307,	13609	3307,
13610	/* CMP_UEQ_D_MMR6 */	13610	/* CMP_UEQ_D_MMR6 */
13611	3310,	13611	3310,
13612	/* CMP_UEQ_S */	13612	/* CMP_UEQ_S */
13613	3313,	13613	3313,
13614	/* CMP_UEQ_S_MMR6 */	13614	/* CMP_UEQ_S_MMR6 */
13615	3316,	13615	3316,
13616	/* CMP_ULE_D */	13616	/* CMP_ULE_D */
13617	3319,	13617	3319,
13618	/* CMP_ULE_D_MMR6 */	13618	/* CMP_ULE_D_MMR6 */
13619	3322,	13619	3322,
13620	/* CMP_ULE_S */	13620	/* CMP_ULE_S */
13621	3325,	13621	3325,
13622	/* CMP_ULE_S_MMR6 */	13622	/* CMP_ULE_S_MMR6 */
13623	3328,	13623	3328,
13624	/* CMP_ULT_D */	13624	/* CMP_ULT_D */
13625	3331,	13625	3331,
13626	/* CMP_ULT_D_MMR6 */	13626	/* CMP_ULT_D_MMR6 */
13627	3334,	13627	3334,
13628	/* CMP_ULT_S */	13628	/* CMP_ULT_S */
13629	3337,	13629	3337,
13630	/* CMP_ULT_S_MMR6 */	13630	/* CMP_ULT_S_MMR6 */
13631	3340,	13631	3340,
13632	/* CMP_UN_D */	13632	/* CMP_UN_D */
13633	3343,	13633	3343,
13634	/* CMP_UN_D_MMR6 */	13634	/* CMP_UN_D_MMR6 */
13635	3346,	13635	3346,
13636	/* CMP_UN_S */	13636	/* CMP_UN_S */
13637	3349,	13637	3349,
13638	/* CMP_UN_S_MMR6 */	13638	/* CMP_UN_S_MMR6 */
13639	3352,	13639	3352,
13640	/* COPY_S_B */	13640	/* COPY_S_B */
13641	3355,	13641	3355,
13642	/* COPY_S_D */	13642	/* COPY_S_D */
13643	3358,	13643	3358,
13644	/* COPY_S_H */	13644	/* COPY_S_H */
13645	3361,	13645	3361,
13646	/* COPY_S_W */	13646	/* COPY_S_W */
13647	3364,	13647	3364,
13648	/* COPY_U_B */	13648	/* COPY_U_B */
13649	3367,	13649	3367,
13650	/* COPY_U_H */	13650	/* COPY_U_H */
13651	3370,	13651	3370,
13652	/* COPY_U_W */	13652	/* COPY_U_W */
13653	3373,	13653	3373,
13654	/* CRC32B */	13654	/* CRC32B */
13655	3376,	13655	3376,
13656	/* CRC32CB */	13656	/* CRC32CB */
13657	3379,	13657	3379,
13658	/* CRC32CD */	13658	/* CRC32CD */
13659	3382,	13659	3382,
13660	/* CRC32CH */	13660	/* CRC32CH */
13661	3385,	13661	3385,
13662	/* CRC32CW */	13662	/* CRC32CW */
13663	3388,	13663	3388,
13664	/* CRC32D */	13664	/* CRC32D */
13665	3391,	13665	3391,
13666	/* CRC32H */	13666	/* CRC32H */
13667	3394,	13667	3394,
13668	/* CRC32W */	13668	/* CRC32W */
13669	3397,	13669	3397,
13670	/* CTC1 */	13670	/* CTC1 */
13671	3400,	13671	3400,
13672	/* CTC1_MM */	13672	/* CTC1_MM */
13673	3402,	13673	3402,
13674	/* CTC2_MM */	13674	/* CTC2_MM */
13675	3404,	13675	3404,
13676	/* CTCMSA */	13676	/* CTCMSA */
13677	3406,	13677	3406,
13678	/* CVT_D32_S */	13678	/* CVT_D32_S */
13679	3408,	13679	3408,
13680	/* CVT_D32_S_MM */	13680	/* CVT_D32_S_MM */
13681	3410,	13681	3410,
13682	/* CVT_D32_W */	13682	/* CVT_D32_W */
13683	3412,	13683	3412,
13684	/* CVT_D32_W_MM */	13684	/* CVT_D32_W_MM */
13685	3414,	13685	3414,
13686	/* CVT_D64_L */	13686	/* CVT_D64_L */
13687	3416,	13687	3416,
13688	/* CVT_D64_S */	13688	/* CVT_D64_S */
13689	3418,	13689	3418,
13690	/* CVT_D64_S_MM */	13690	/* CVT_D64_S_MM */
13691	3420,	13691	3420,
13692	/* CVT_D64_W */	13692	/* CVT_D64_W */
13693	3422,	13693	3422,
13694	/* CVT_D64_W_MM */	13694	/* CVT_D64_W_MM */
13695	3424,	13695	3424,
13696	/* CVT_D_L_MMR6 */	13696	/* CVT_D_L_MMR6 */
13697	3426,	13697	3426,
13698	/* CVT_L_D64 */	13698	/* CVT_L_D64 */
13699	3428,	13699	3428,
13700	/* CVT_L_D64_MM */	13700	/* CVT_L_D64_MM */
13701	3430,	13701	3430,
13702	/* CVT_L_D_MMR6 */	13702	/* CVT_L_D_MMR6 */
13703	3432,	13703	3432,
13704	/* CVT_L_S */	13704	/* CVT_L_S */
13705	3434,	13705	3434,
13706	/* CVT_L_S_MM */	13706	/* CVT_L_S_MM */
13707	3436,	13707	3436,
13708	/* CVT_L_S_MMR6 */	13708	/* CVT_L_S_MMR6 */
13709	3438,	13709	3438,
13710	/* CVT_PS_PW64 */	13710	/* CVT_PS_PW64 */
13711	3440,	13711	3440,
13712	/* CVT_PS_S64 */	13712	/* CVT_PS_S64 */
13713	3442,	13713	3442,
13714	/* CVT_PW_PS64 */	13714	/* CVT_PW_PS64 */
13715	3445,	13715	3445,
13716	/* CVT_S_D32 */	13716	/* CVT_S_D32 */
13717	3447,	13717	3447,
13718	/* CVT_S_D32_MM */	13718	/* CVT_S_D32_MM */
13719	3449,	13719	3449,
13720	/* CVT_S_D64 */	13720	/* CVT_S_D64 */
13721	3451,	13721	3451,
13722	/* CVT_S_D64_MM */	13722	/* CVT_S_D64_MM */
13723	3453,	13723	3453,
13724	/* CVT_S_L */	13724	/* CVT_S_L */
13725	3455,	13725	3455,
13726	/* CVT_S_L_MMR6 */	13726	/* CVT_S_L_MMR6 */
13727	3457,	13727	3457,
13728	/* CVT_S_PL64 */	13728	/* CVT_S_PL64 */
13729	3459,	13729	3459,
13730	/* CVT_S_PU64 */	13730	/* CVT_S_PU64 */
13731	3461,	13731	3461,
13732	/* CVT_S_W */	13732	/* CVT_S_W */
13733	3463,	13733	3463,
13734	/* CVT_S_W_MM */	13734	/* CVT_S_W_MM */
13735	3465,	13735	3465,
13736	/* CVT_S_W_MMR6 */	13736	/* CVT_S_W_MMR6 */
13737	3467,	13737	3467,
13738	/* CVT_W_D32 */	13738	/* CVT_W_D32 */
13739	3469,	13739	3469,
13740	/* CVT_W_D32_MM */	13740	/* CVT_W_D32_MM */
13741	3471,	13741	3471,
13742	/* CVT_W_D64 */	13742	/* CVT_W_D64 */
13743	3473,	13743	3473,
13744	/* CVT_W_D64_MM */	13744	/* CVT_W_D64_MM */
13745	3475,	13745	3475,
13746	/* CVT_W_S */	13746	/* CVT_W_S */
13747	3477,	13747	3477,
13748	/* CVT_W_S_MM */	13748	/* CVT_W_S_MM */
13749	3479,	13749	3479,
13750	/* CVT_W_S_MMR6 */	13750	/* CVT_W_S_MMR6 */
13751	3481,	13751	3481,
13752	/* C_EQ_D32 */	13752	/* C_EQ_D32 */
13753	3483,	13753	3483,
13754	/* C_EQ_D32_MM */	13754	/* C_EQ_D32_MM */
13755	3486,	13755	3486,
13756	/* C_EQ_D64 */	13756	/* C_EQ_D64 */
13757	3489,	13757	3489,
13758	/* C_EQ_D64_MM */	13758	/* C_EQ_D64_MM */
13759	3492,	13759	3492,
13760	/* C_EQ_S */	13760	/* C_EQ_S */
13761	3495,	13761	3495,
13762	/* C_EQ_S_MM */	13762	/* C_EQ_S_MM */
13763	3498,	13763	3498,
13764	/* C_F_D32 */	13764	/* C_F_D32 */
13765	3501,	13765	3501,
13766	/* C_F_D32_MM */	13766	/* C_F_D32_MM */
13767	3504,	13767	3504,
13768	/* C_F_D64 */	13768	/* C_F_D64 */
13769	3507,	13769	3507,
13770	/* C_F_D64_MM */	13770	/* C_F_D64_MM */
13771	3510,	13771	3510,
13772	/* C_F_S */	13772	/* C_F_S */
13773	3513,	13773	3513,
13774	/* C_F_S_MM */	13774	/* C_F_S_MM */
13775	3516,	13775	3516,
13776	/* C_LE_D32 */	13776	/* C_LE_D32 */
13777	3519,	13777	3519,
13778	/* C_LE_D32_MM */	13778	/* C_LE_D32_MM */
13779	3522,	13779	3522,
13780	/* C_LE_D64 */	13780	/* C_LE_D64 */
13781	3525,	13781	3525,
13782	/* C_LE_D64_MM */	13782	/* C_LE_D64_MM */
13783	3528,	13783	3528,
13784	/* C_LE_S */	13784	/* C_LE_S */
13785	3531,	13785	3531,
13786	/* C_LE_S_MM */	13786	/* C_LE_S_MM */
13787	3534,	13787	3534,
13788	/* C_LT_D32 */	13788	/* C_LT_D32 */
13789	3537,	13789	3537,
13790	/* C_LT_D32_MM */	13790	/* C_LT_D32_MM */
13791	3540,	13791	3540,
13792	/* C_LT_D64 */	13792	/* C_LT_D64 */
13793	3543,	13793	3543,
13794	/* C_LT_D64_MM */	13794	/* C_LT_D64_MM */
13795	3546,	13795	3546,
13796	/* C_LT_S */	13796	/* C_LT_S */
13797	3549,	13797	3549,
13798	/* C_LT_S_MM */	13798	/* C_LT_S_MM */
13799	3552,	13799	3552,
13800	/* C_NGE_D32 */	13800	/* C_NGE_D32 */
13801	3555,	13801	3555,
13802	/* C_NGE_D32_MM */	13802	/* C_NGE_D32_MM */
13803	3558,	13803	3558,
13804	/* C_NGE_D64 */	13804	/* C_NGE_D64 */
13805	3561,	13805	3561,
13806	/* C_NGE_D64_MM */	13806	/* C_NGE_D64_MM */
13807	3564,	13807	3564,
13808	/* C_NGE_S */	13808	/* C_NGE_S */
13809	3567,	13809	3567,
13810	/* C_NGE_S_MM */	13810	/* C_NGE_S_MM */
13811	3570,	13811	3570,
13812	/* C_NGLE_D32 */	13812	/* C_NGLE_D32 */
13813	3573,	13813	3573,
13814	/* C_NGLE_D32_MM */	13814	/* C_NGLE_D32_MM */
13815	3576,	13815	3576,
13816	/* C_NGLE_D64 */	13816	/* C_NGLE_D64 */
13817	3579,	13817	3579,
13818	/* C_NGLE_D64_MM */	13818	/* C_NGLE_D64_MM */
13819	3582,	13819	3582,
13820	/* C_NGLE_S */	13820	/* C_NGLE_S */
13821	3585,	13821	3585,
13822	/* C_NGLE_S_MM */	13822	/* C_NGLE_S_MM */
13823	3588,	13823	3588,
13824	/* C_NGL_D32 */	13824	/* C_NGL_D32 */
13825	3591,	13825	3591,
13826	/* C_NGL_D32_MM */	13826	/* C_NGL_D32_MM */
13827	3594,	13827	3594,
13828	/* C_NGL_D64 */	13828	/* C_NGL_D64 */
13829	3597,	13829	3597,
13830	/* C_NGL_D64_MM */	13830	/* C_NGL_D64_MM */
13831	3600,	13831	3600,
13832	/* C_NGL_S */	13832	/* C_NGL_S */
13833	3603,	13833	3603,
13834	/* C_NGL_S_MM */	13834	/* C_NGL_S_MM */
13835	3606,	13835	3606,
13836	/* C_NGT_D32 */	13836	/* C_NGT_D32 */
13837	3609,	13837	3609,
13838	/* C_NGT_D32_MM */	13838	/* C_NGT_D32_MM */
13839	3612,	13839	3612,
13840	/* C_NGT_D64 */	13840	/* C_NGT_D64 */
13841	3615,	13841	3615,
13842	/* C_NGT_D64_MM */	13842	/* C_NGT_D64_MM */
13843	3618,	13843	3618,
13844	/* C_NGT_S */	13844	/* C_NGT_S */
13845	3621,	13845	3621,
13846	/* C_NGT_S_MM */	13846	/* C_NGT_S_MM */
13847	3624,	13847	3624,
13848	/* C_OLE_D32 */	13848	/* C_OLE_D32 */
13849	3627,	13849	3627,
13850	/* C_OLE_D32_MM */	13850	/* C_OLE_D32_MM */
13851	3630,	13851	3630,
13852	/* C_OLE_D64 */	13852	/* C_OLE_D64 */
13853	3633,	13853	3633,
13854	/* C_OLE_D64_MM */	13854	/* C_OLE_D64_MM */
13855	3636,	13855	3636,
13856	/* C_OLE_S */	13856	/* C_OLE_S */
13857	3639,	13857	3639,
13858	/* C_OLE_S_MM */	13858	/* C_OLE_S_MM */
13859	3642,	13859	3642,
13860	/* C_OLT_D32 */	13860	/* C_OLT_D32 */
13861	3645,	13861	3645,
13862	/* C_OLT_D32_MM */	13862	/* C_OLT_D32_MM */
13863	3648,	13863	3648,
13864	/* C_OLT_D64 */	13864	/* C_OLT_D64 */
13865	3651,	13865	3651,
13866	/* C_OLT_D64_MM */	13866	/* C_OLT_D64_MM */
13867	3654,	13867	3654,
13868	/* C_OLT_S */	13868	/* C_OLT_S */
13869	3657,	13869	3657,
13870	/* C_OLT_S_MM */	13870	/* C_OLT_S_MM */
13871	3660,	13871	3660,
13872	/* C_SEQ_D32 */	13872	/* C_SEQ_D32 */
13873	3663,	13873	3663,
13874	/* C_SEQ_D32_MM */	13874	/* C_SEQ_D32_MM */
13875	3666,	13875	3666,
13876	/* C_SEQ_D64 */	13876	/* C_SEQ_D64 */
13877	3669,	13877	3669,
13878	/* C_SEQ_D64_MM */	13878	/* C_SEQ_D64_MM */
13879	3672,	13879	3672,
13880	/* C_SEQ_S */	13880	/* C_SEQ_S */
13881	3675,	13881	3675,
13882	/* C_SEQ_S_MM */	13882	/* C_SEQ_S_MM */
13883	3678,	13883	3678,
13884	/* C_SF_D32 */	13884	/* C_SF_D32 */
13885	3681,	13885	3681,
13886	/* C_SF_D32_MM */	13886	/* C_SF_D32_MM */
13887	3684,	13887	3684,
13888	/* C_SF_D64 */	13888	/* C_SF_D64 */
13889	3687,	13889	3687,
13890	/* C_SF_D64_MM */	13890	/* C_SF_D64_MM */
13891	3690,	13891	3690,
13892	/* C_SF_S */	13892	/* C_SF_S */
13893	3693,	13893	3693,
13894	/* C_SF_S_MM */	13894	/* C_SF_S_MM */
13895	3696,	13895	3696,
13896	/* C_UEQ_D32 */	13896	/* C_UEQ_D32 */
13897	3699,	13897	3699,
13898	/* C_UEQ_D32_MM */	13898	/* C_UEQ_D32_MM */
13899	3702,	13899	3702,
13900	/* C_UEQ_D64 */	13900	/* C_UEQ_D64 */
13901	3705,	13901	3705,
13902	/* C_UEQ_D64_MM */	13902	/* C_UEQ_D64_MM */
13903	3708,	13903	3708,
13904	/* C_UEQ_S */	13904	/* C_UEQ_S */
13905	3711,	13905	3711,
13906	/* C_UEQ_S_MM */	13906	/* C_UEQ_S_MM */
13907	3714,	13907	3714,
13908	/* C_ULE_D32 */	13908	/* C_ULE_D32 */
13909	3717,	13909	3717,
13910	/* C_ULE_D32_MM */	13910	/* C_ULE_D32_MM */
13911	3720,	13911	3720,
13912	/* C_ULE_D64 */	13912	/* C_ULE_D64 */
13913	3723,	13913	3723,
13914	/* C_ULE_D64_MM */	13914	/* C_ULE_D64_MM */
13915	3726,	13915	3726,
13916	/* C_ULE_S */	13916	/* C_ULE_S */
13917	3729,	13917	3729,
13918	/* C_ULE_S_MM */	13918	/* C_ULE_S_MM */
13919	3732,	13919	3732,
13920	/* C_ULT_D32 */	13920	/* C_ULT_D32 */
13921	3735,	13921	3735,
13922	/* C_ULT_D32_MM */	13922	/* C_ULT_D32_MM */
13923	3738,	13923	3738,
13924	/* C_ULT_D64 */	13924	/* C_ULT_D64 */
13925	3741,	13925	3741,
13926	/* C_ULT_D64_MM */	13926	/* C_ULT_D64_MM */
13927	3744,	13927	3744,
13928	/* C_ULT_S */	13928	/* C_ULT_S */
13929	3747,	13929	3747,
13930	/* C_ULT_S_MM */	13930	/* C_ULT_S_MM */
13931	3750,	13931	3750,
13932	/* C_UN_D32 */	13932	/* C_UN_D32 */
13933	3753,	13933	3753,
13934	/* C_UN_D32_MM */	13934	/* C_UN_D32_MM */
13935	3756,	13935	3756,
13936	/* C_UN_D64 */	13936	/* C_UN_D64 */
13937	3759,	13937	3759,
13938	/* C_UN_D64_MM */	13938	/* C_UN_D64_MM */
13939	3762,	13939	3762,
13940	/* C_UN_S */	13940	/* C_UN_S */
13941	3765,	13941	3765,
13942	/* C_UN_S_MM */	13942	/* C_UN_S_MM */
13943	3768,	13943	3768,
13944	/* CmpRxRy16 */	13944	/* CmpRxRy16 */
13945	3771,	13945	3771,
13946	/* CmpiRxImm16 */	13946	/* CmpiRxImm16 */
13947	3773,	13947	3773,
13948	/* CmpiRxImmX16 */	13948	/* CmpiRxImmX16 */
13949	3775,	13949	3775,
13950	/* DADD */	13950	/* DADD */
13951	3777,	13951	3777,
13952	/* DADDi */	13952	/* DADDi */
13953	3780,	13953	3780,
13954	/* DADDiu */	13954	/* DADDiu */
13955	3783,	13955	3783,
13956	/* DADDu */	13956	/* DADDu */
13957	3786,	13957	3786,
13958	/* DAHI */	13958	/* DAHI */
13959	3789,	13959	3789,
13960	/* DALIGN */	13960	/* DALIGN */
13961	3792,	13961	3792,
13962	/* DATI */	13962	/* DATI */
13963	3796,	13963	3796,
13964	/* DAUI */	13964	/* DAUI */
13965	3799,	13965	3799,
13966	/* DBITSWAP */	13966	/* DBITSWAP */
13967	3802,	13967	3802,
13968	/* DCLO */	13968	/* DCLO */
13969	3804,	13969	3804,
13970	/* DCLO_R6 */	13970	/* DCLO_R6 */
13971	3806,	13971	3806,
13972	/* DCLZ */	13972	/* DCLZ */
13973	3808,	13973	3808,
13974	/* DCLZ_R6 */	13974	/* DCLZ_R6 */
13975	3810,	13975	3810,
13976	/* DDIV */	13976	/* DDIV */
13977	3812,	13977	3812,
13978	/* DDIVU */	13978	/* DDIVU */
13979	3815,	13979	3815,
13980	/* DERET */	13980	/* DERET */
13981	3818,	13981	3818,
13982	/* DERET_MM */	13982	/* DERET_MM */
13983	3818,	13983	3818,
13984	/* DERET_MMR6 */	13984	/* DERET_MMR6 */
13985	3818,	13985	3818,
13986	/* DEXT */	13986	/* DEXT */
13987	3818,	13987	3818,
13988	/* DEXT64_32 */	13988	/* DEXT64_32 */
13989	3822,	13989	3822,
13990	/* DEXTM */	13990	/* DEXTM */
13991	3826,	13991	3826,
13992	/* DEXTU */	13992	/* DEXTU */
13993	3830,	13993	3830,
13994	/* DI */	13994	/* DI */
13995	3834,	13995	3834,
13996	/* DINS */	13996	/* DINS */
13997	3835,	13997	3835,
13998	/* DINSM */	13998	/* DINSM */
13999	3840,	13999	3840,
14000	/* DINSU */	14000	/* DINSU */
14001	3845,	14001	3845,
14002	/* DIV */	14002	/* DIV */
14003	3850,	14003	3850,
14004	/* DIVU */	14004	/* DIVU */
14005	3853,	14005	3853,
14006	/* DIVU_MMR6 */	14006	/* DIVU_MMR6 */
14007	3856,	14007	3856,
14008	/* DIV_MMR6 */	14008	/* DIV_MMR6 */
14009	3859,	14009	3859,
14010	/* DIV_S_B */	14010	/* DIV_S_B */
14011	3862,	14011	3862,
14012	/* DIV_S_D */	14012	/* DIV_S_D */
14013	3865,	14013	3865,
14014	/* DIV_S_H */	14014	/* DIV_S_H */
14015	3868,	14015	3868,
14016	/* DIV_S_W */	14016	/* DIV_S_W */
14017	3871,	14017	3871,
14018	/* DIV_U_B */	14018	/* DIV_U_B */
14019	3874,	14019	3874,
14020	/* DIV_U_D */	14020	/* DIV_U_D */
14021	3877,	14021	3877,
14022	/* DIV_U_H */	14022	/* DIV_U_H */
14023	3880,	14023	3880,
14024	/* DIV_U_W */	14024	/* DIV_U_W */
14025	3883,	14025	3883,
14026	/* DI_MM */	14026	/* DI_MM */
14027	3886,	14027	3886,
14028	/* DI_MMR6 */	14028	/* DI_MMR6 */
14029	3887,	14029	3887,
14030	/* DLSA */	14030	/* DLSA */
14031	3888,	14031	3888,
14032	/* DLSA_R6 */	14032	/* DLSA_R6 */
14033	3892,	14033	3892,
14034	/* DMFC0 */	14034	/* DMFC0 */
14035	3896,	14035	3896,
14036	/* DMFC1 */	14036	/* DMFC1 */
14037	3899,	14037	3899,
14038	/* DMFC2 */	14038	/* DMFC2 */
14039	3901,	14039	3901,
14040	/* DMFC2_OCTEON */	14040	/* DMFC2_OCTEON */
14041	3904,	14041	3904,
14042	/* DMFGC0 */	14042	/* DMFGC0 */
14043	3906,	14043	3906,
14044	/* DMOD */	14044	/* DMOD */
14045	3909,	14045	3909,
14046	/* DMODU */	14046	/* DMODU */
14047	3912,	14047	3912,
14048	/* DMT */	14048	/* DMT */
14049	3915,	14049	3915,
14050	/* DMTC0 */	14050	/* DMTC0 */
14051	3916,	14051	3916,
14052	/* DMTC1 */	14052	/* DMTC1 */
14053	3919,	14053	3919,
14054	/* DMTC2 */	14054	/* DMTC2 */
14055	3921,	14055	3921,
14056	/* DMTC2_OCTEON */	14056	/* DMTC2_OCTEON */
14057	3924,	14057	3924,
14058	/* DMTGC0 */	14058	/* DMTGC0 */
14059	3926,	14059	3926,
14060	/* DMUH */	14060	/* DMUH */
14061	3929,	14061	3929,
14062	/* DMUHU */	14062	/* DMUHU */
14063	3932,	14063	3932,
14064	/* DMUL */	14064	/* DMUL */
14065	3935,	14065	3935,
14066	/* DMULT */	14066	/* DMULT */
14067	3938,	14067	3938,
14068	/* DMULTu */	14068	/* DMULTu */
14069	3940,	14069	3940,
14070	/* DMULU */	14070	/* DMULU */
14071	3942,	14071	3942,
14072	/* DMUL_R6 */	14072	/* DMUL_R6 */
14073	3945,	14073	3945,
14074	/* DOTP_S_D */	14074	/* DOTP_S_D */
14075	3948,	14075	3948,
14076	/* DOTP_S_H */	14076	/* DOTP_S_H */
14077	3951,	14077	3951,
14078	/* DOTP_S_W */	14078	/* DOTP_S_W */
14079	3954,	14079	3954,
14080	/* DOTP_U_D */	14080	/* DOTP_U_D */
14081	3957,	14081	3957,
14082	/* DOTP_U_H */	14082	/* DOTP_U_H */
14083	3960,	14083	3960,
14084	/* DOTP_U_W */	14084	/* DOTP_U_W */
14085	3963,	14085	3963,
14086	/* DPADD_S_D */	14086	/* DPADD_S_D */
14087	3966,	14087	3966,
14088	/* DPADD_S_H */	14088	/* DPADD_S_H */
14089	3970,	14089	3970,
14090	/* DPADD_S_W */	14090	/* DPADD_S_W */
14091	3974,	14091	3974,
14092	/* DPADD_U_D */	14092	/* DPADD_U_D */
14093	3978,	14093	3978,
14094	/* DPADD_U_H */	14094	/* DPADD_U_H */
14095	3982,	14095	3982,
14096	/* DPADD_U_W */	14096	/* DPADD_U_W */
14097	3986,	14097	3986,
14098	/* DPAQX_SA_W_PH */	14098	/* DPAQX_SA_W_PH */
14099	3990,	14099	3990,
14100	/* DPAQX_SA_W_PH_MMR2 */	14100	/* DPAQX_SA_W_PH_MMR2 */
14101	3994,	14101	3994,
14102	/* DPAQX_S_W_PH */	14102	/* DPAQX_S_W_PH */
14103	3998,	14103	3998,
14104	/* DPAQX_S_W_PH_MMR2 */	14104	/* DPAQX_S_W_PH_MMR2 */
14105	4002,	14105	4002,
14106	/* DPAQ_SA_L_W */	14106	/* DPAQ_SA_L_W */
14107	4006,	14107	4006,
14108	/* DPAQ_SA_L_W_MM */	14108	/* DPAQ_SA_L_W_MM */
14109	4010,	14109	4010,
14110	/* DPAQ_S_W_PH */	14110	/* DPAQ_S_W_PH */
14111	4014,	14111	4014,
14112	/* DPAQ_S_W_PH_MM */	14112	/* DPAQ_S_W_PH_MM */
14113	4018,	14113	4018,
14114	/* DPAU_H_QBL */	14114	/* DPAU_H_QBL */
14115	4022,	14115	4022,
14116	/* DPAU_H_QBL_MM */	14116	/* DPAU_H_QBL_MM */
14117	4026,	14117	4026,
14118	/* DPAU_H_QBR */	14118	/* DPAU_H_QBR */
14119	4030,	14119	4030,
14120	/* DPAU_H_QBR_MM */	14120	/* DPAU_H_QBR_MM */
14121	4034,	14121	4034,
14122	/* DPAX_W_PH */	14122	/* DPAX_W_PH */
14123	4038,	14123	4038,
14124	/* DPAX_W_PH_MMR2 */	14124	/* DPAX_W_PH_MMR2 */
14125	4042,	14125	4042,
14126	/* DPA_W_PH */	14126	/* DPA_W_PH */
14127	4046,	14127	4046,
14128	/* DPA_W_PH_MMR2 */	14128	/* DPA_W_PH_MMR2 */
14129	4050,	14129	4050,
14130	/* DPOP */	14130	/* DPOP */
14131	4054,	14131	4054,
14132	/* DPSQX_SA_W_PH */	14132	/* DPSQX_SA_W_PH */
14133	4056,	14133	4056,
14134	/* DPSQX_SA_W_PH_MMR2 */	14134	/* DPSQX_SA_W_PH_MMR2 */
14135	4060,	14135	4060,
14136	/* DPSQX_S_W_PH */	14136	/* DPSQX_S_W_PH */
14137	4064,	14137	4064,
14138	/* DPSQX_S_W_PH_MMR2 */	14138	/* DPSQX_S_W_PH_MMR2 */
14139	4068,	14139	4068,
14140	/* DPSQ_SA_L_W */	14140	/* DPSQ_SA_L_W */
14141	4072,	14141	4072,
14142	/* DPSQ_SA_L_W_MM */	14142	/* DPSQ_SA_L_W_MM */
14143	4076,	14143	4076,
14144	/* DPSQ_S_W_PH */	14144	/* DPSQ_S_W_PH */
14145	4080,	14145	4080,
14146	/* DPSQ_S_W_PH_MM */	14146	/* DPSQ_S_W_PH_MM */
14147	4084,	14147	4084,
14148	/* DPSUB_S_D */	14148	/* DPSUB_S_D */
14149	4088,	14149	4088,
14150	/* DPSUB_S_H */	14150	/* DPSUB_S_H */
14151	4092,	14151	4092,
14152	/* DPSUB_S_W */	14152	/* DPSUB_S_W */
14153	4096,	14153	4096,
14154	/* DPSUB_U_D */	14154	/* DPSUB_U_D */
14155	4100,	14155	4100,
14156	/* DPSUB_U_H */	14156	/* DPSUB_U_H */
14157	4104,	14157	4104,
14158	/* DPSUB_U_W */	14158	/* DPSUB_U_W */
14159	4108,	14159	4108,
14160	/* DPSU_H_QBL */	14160	/* DPSU_H_QBL */
14161	4112,	14161	4112,
14162	/* DPSU_H_QBL_MM */	14162	/* DPSU_H_QBL_MM */
14163	4116,	14163	4116,
14164	/* DPSU_H_QBR */	14164	/* DPSU_H_QBR */
14165	4120,	14165	4120,
14166	/* DPSU_H_QBR_MM */	14166	/* DPSU_H_QBR_MM */
14167	4124,	14167	4124,
14168	/* DPSX_W_PH */	14168	/* DPSX_W_PH */
14169	4128,	14169	4128,
14170	/* DPSX_W_PH_MMR2 */	14170	/* DPSX_W_PH_MMR2 */
14171	4132,	14171	4132,
14172	/* DPS_W_PH */	14172	/* DPS_W_PH */
14173	4136,	14173	4136,
14174	/* DPS_W_PH_MMR2 */	14174	/* DPS_W_PH_MMR2 */
14175	4140,	14175	4140,
14176	/* DROTR */	14176	/* DROTR */
14177	4144,	14177	4144,
14178	/* DROTR32 */	14178	/* DROTR32 */
14179	4147,	14179	4147,
14180	/* DROTRV */	14180	/* DROTRV */
14181	4150,	14181	4150,
14182	/* DSBH */	14182	/* DSBH */
14183	4153,	14183	4153,
14184	/* DSDIV */	14184	/* DSDIV */
14185	4155,	14185	4155,
14186	/* DSHD */	14186	/* DSHD */
14187	4157,	14187	4157,
14188	/* DSLL */	14188	/* DSLL */
14189	4159,	14189	4159,
14190	/* DSLL32 */	14190	/* DSLL32 */
14191	4162,	14191	4162,
14192	/* DSLL64_32 */	14192	/* DSLL64_32 */
14193	4165,	14193	4165,
14194	/* DSLLV */	14194	/* DSLLV */
14195	4167,	14195	4167,
14196	/* DSRA */	14196	/* DSRA */
14197	4170,	14197	4170,
14198	/* DSRA32 */	14198	/* DSRA32 */
14199	4173,	14199	4173,
14200	/* DSRAV */	14200	/* DSRAV */
14201	4176,	14201	4176,
14202	/* DSRL */	14202	/* DSRL */
14203	4179,	14203	4179,
14204	/* DSRL32 */	14204	/* DSRL32 */
14205	4182,	14205	4182,
14206	/* DSRLV */	14206	/* DSRLV */
14207	4185,	14207	4185,
14208	/* DSUB */	14208	/* DSUB */
14209	4188,	14209	4188,
14210	/* DSUBu */	14210	/* DSUBu */
14211	4191,	14211	4191,
14212	/* DUDIV */	14212	/* DUDIV */
14213	4194,	14213	4194,
14214	/* DVP */	14214	/* DVP */
14215	4196,	14215	4196,
14216	/* DVPE */	14216	/* DVPE */
14217	4197,	14217	4197,
14218	/* DVP_MMR6 */	14218	/* DVP_MMR6 */
14219	4198,	14219	4198,
14220	/* DivRxRy16 */	14220	/* DivRxRy16 */
14221	4199,	14221	4199,
14222	/* DivuRxRy16 */	14222	/* DivuRxRy16 */
14223	4201,	14223	4201,
14224	/* EHB */	14224	/* EHB */
14225	4203,	14225	4203,
14226	/* EHB_MM */	14226	/* EHB_MM */
14227	4203,	14227	4203,
14228	/* EHB_MMR6 */	14228	/* EHB_MMR6 */
14229	4203,	14229	4203,
14230	/* EI */	14230	/* EI */
14231	4203,	14231	4203,
14232	/* EI_MM */	14232	/* EI_MM */
14233	4204,	14233	4204,
14234	/* EI_MMR6 */	14234	/* EI_MMR6 */
14235	4205,	14235	4205,
14236	/* EMT */	14236	/* EMT */
14237	4206,	14237	4206,
14238	/* ERET */	14238	/* ERET */
14239	4207,	14239	4207,
14240	/* ERETNC */	14240	/* ERETNC */
14241	4207,	14241	4207,
14242	/* ERETNC_MMR6 */	14242	/* ERETNC_MMR6 */
14243	4207,	14243	4207,
14244	/* ERET_MM */	14244	/* ERET_MM */
14245	4207,	14245	4207,
14246	/* ERET_MMR6 */	14246	/* ERET_MMR6 */
14247	4207,	14247	4207,
14248	/* EVP */	14248	/* EVP */
14249	4207,	14249	4207,
14250	/* EVPE */	14250	/* EVPE */
14251	4208,	14251	4208,
14252	/* EVP_MMR6 */	14252	/* EVP_MMR6 */
14253	4209,	14253	4209,
14254	/* EXT */	14254	/* EXT */
14255	4210,	14255	4210,
14256	/* EXTP */	14256	/* EXTP */
14257	4214,	14257	4214,
14258	/* EXTPDP */	14258	/* EXTPDP */
14259	4217,	14259	4217,
14260	/* EXTPDPV */	14260	/* EXTPDPV */
14261	4220,	14261	4220,
14262	/* EXTPDPV_MM */	14262	/* EXTPDPV_MM */
14263	4223,	14263	4223,
14264	/* EXTPDP_MM */	14264	/* EXTPDP_MM */
14265	4226,	14265	4226,
14266	/* EXTPV */	14266	/* EXTPV */
14267	4229,	14267	4229,
14268	/* EXTPV_MM */	14268	/* EXTPV_MM */
14269	4232,	14269	4232,
14270	/* EXTP_MM */	14270	/* EXTP_MM */
14271	4235,	14271	4235,
14272	/* EXTRV_RS_W */	14272	/* EXTRV_RS_W */
14273	4238,	14273	4238,
14274	/* EXTRV_RS_W_MM */	14274	/* EXTRV_RS_W_MM */
14275	4241,	14275	4241,
14276	/* EXTRV_R_W */	14276	/* EXTRV_R_W */
14277	4244,	14277	4244,
14278	/* EXTRV_R_W_MM */	14278	/* EXTRV_R_W_MM */
14279	4247,	14279	4247,
14280	/* EXTRV_S_H */	14280	/* EXTRV_S_H */
14281	4250,	14281	4250,
14282	/* EXTRV_S_H_MM */	14282	/* EXTRV_S_H_MM */
14283	4253,	14283	4253,
14284	/* EXTRV_W */	14284	/* EXTRV_W */
14285	4256,	14285	4256,
14286	/* EXTRV_W_MM */	14286	/* EXTRV_W_MM */
14287	4259,	14287	4259,
14288	/* EXTR_RS_W */	14288	/* EXTR_RS_W */
14289	4262,	14289	4262,
14290	/* EXTR_RS_W_MM */	14290	/* EXTR_RS_W_MM */
14291	4265,	14291	4265,
14292	/* EXTR_R_W */	14292	/* EXTR_R_W */
14293	4268,	14293	4268,
14294	/* EXTR_R_W_MM */	14294	/* EXTR_R_W_MM */
14295	4271,	14295	4271,
14296	/* EXTR_S_H */	14296	/* EXTR_S_H */
14297	4274,	14297	4274,
14298	/* EXTR_S_H_MM */	14298	/* EXTR_S_H_MM */
14299	4277,	14299	4277,
14300	/* EXTR_W */	14300	/* EXTR_W */
14301	4280,	14301	4280,
14302	/* EXTR_W_MM */	14302	/* EXTR_W_MM */
14303	4283,	14303	4283,
14304	/* EXTS */	14304	/* EXTS */
14305	4286,	14305	4286,
14306	/* EXTS32 */	14306	/* EXTS32 */
14307	4290,	14307	4290,
14308	/* EXT_MM */	14308	/* EXT_MM */
14309	4294,	14309	4294,
14310	/* EXT_MMR6 */	14310	/* EXT_MMR6 */
14311	4298,	14311	4298,
14312	/* FABS_D32 */	14312	/* FABS_D32 */
14313	4302,	14313	4302,
14314	/* FABS_D32_MM */	14314	/* FABS_D32_MM */
14315	4304,	14315	4304,
14316	/* FABS_D64 */	14316	/* FABS_D64 */
14317	4306,	14317	4306,
14318	/* FABS_D64_MM */	14318	/* FABS_D64_MM */
14319	4308,	14319	4308,
14320	/* FABS_S */	14320	/* FABS_S */
14321	4310,	14321	4310,
14322	/* FABS_S_MM */	14322	/* FABS_S_MM */
14323	4312,	14323	4312,
14324	/* FADD_D */	14324	/* FADD_D */
14325	4314,	14325	4314,
14326	/* FADD_D32 */	14326	/* FADD_D32 */
14327	4317,	14327	4317,
14328	/* FADD_D32_MM */	14328	/* FADD_D32_MM */
14329	4320,	14329	4320,
14330	/* FADD_D64 */	14330	/* FADD_D64 */
14331	4323,	14331	4323,
14332	/* FADD_D64_MM */	14332	/* FADD_D64_MM */
14333	4326,	14333	4326,
14334	/* FADD_PS64 */	14334	/* FADD_PS64 */
14335	4329,	14335	4329,
14336	/* FADD_S */	14336	/* FADD_S */
14337	4332,	14337	4332,
14338	/* FADD_S_MM */	14338	/* FADD_S_MM */
14339	4335,	14339	4335,
14340	/* FADD_S_MMR6 */	14340	/* FADD_S_MMR6 */
14341	4338,	14341	4338,
14342	/* FADD_W */	14342	/* FADD_W */
14343	4341,	14343	4341,
14344	/* FCAF_D */	14344	/* FCAF_D */
14345	4344,	14345	4344,
14346	/* FCAF_W */	14346	/* FCAF_W */
14347	4347,	14347	4347,
14348	/* FCEQ_D */	14348	/* FCEQ_D */
14349	4350,	14349	4350,
14350	/* FCEQ_W */	14350	/* FCEQ_W */
14351	4353,	14351	4353,
14352	/* FCLASS_D */	14352	/* FCLASS_D */
14353	4356,	14353	4356,
14354	/* FCLASS_W */	14354	/* FCLASS_W */
14355	4358,	14355	4358,
14356	/* FCLE_D */	14356	/* FCLE_D */
14357	4360,	14357	4360,
14358	/* FCLE_W */	14358	/* FCLE_W */
14359	4363,	14359	4363,
14360	/* FCLT_D */	14360	/* FCLT_D */
14361	4366,	14361	4366,
14362	/* FCLT_W */	14362	/* FCLT_W */
14363	4369,	14363	4369,
14364	/* FCMP_D32 */	14364	/* FCMP_D32 */
14365	4372,	14365	4372,
14366	/* FCMP_D32_MM */	14366	/* FCMP_D32_MM */
14367	4375,	14367	4375,
14368	/* FCMP_D64 */	14368	/* FCMP_D64 */
14369	4378,	14369	4378,
14370	/* FCMP_S32 */	14370	/* FCMP_S32 */
14371	4381,	14371	4381,
14372	/* FCMP_S32_MM */	14372	/* FCMP_S32_MM */
14373	4384,	14373	4384,
14374	/* FCNE_D */	14374	/* FCNE_D */
14375	4387,	14375	4387,
14376	/* FCNE_W */	14376	/* FCNE_W */
14377	4390,	14377	4390,
14378	/* FCOR_D */	14378	/* FCOR_D */
14379	4393,	14379	4393,
14380	/* FCOR_W */	14380	/* FCOR_W */
14381	4396,	14381	4396,
14382	/* FCUEQ_D */	14382	/* FCUEQ_D */
14383	4399,	14383	4399,
14384	/* FCUEQ_W */	14384	/* FCUEQ_W */
14385	4402,	14385	4402,
14386	/* FCULE_D */	14386	/* FCULE_D */
14387	4405,	14387	4405,
14388	/* FCULE_W */	14388	/* FCULE_W */
14389	4408,	14389	4408,
14390	/* FCULT_D */	14390	/* FCULT_D */
14391	4411,	14391	4411,
14392	/* FCULT_W */	14392	/* FCULT_W */
14393	4414,	14393	4414,
14394	/* FCUNE_D */	14394	/* FCUNE_D */
14395	4417,	14395	4417,
14396	/* FCUNE_W */	14396	/* FCUNE_W */
14397	4420,	14397	4420,
14398	/* FCUN_D */	14398	/* FCUN_D */
14399	4423,	14399	4423,
14400	/* FCUN_W */	14400	/* FCUN_W */
14401	4426,	14401	4426,
14402	/* FDIV_D */	14402	/* FDIV_D */
14403	4429,	14403	4429,
14404	/* FDIV_D32 */	14404	/* FDIV_D32 */
14405	4432,	14405	4432,
14406	/* FDIV_D32_MM */	14406	/* FDIV_D32_MM */
14407	4435,	14407	4435,
14408	/* FDIV_D64 */	14408	/* FDIV_D64 */
14409	4438,	14409	4438,
14410	/* FDIV_D64_MM */	14410	/* FDIV_D64_MM */
14411	4441,	14411	4441,
14412	/* FDIV_S */	14412	/* FDIV_S */
14413	4444,	14413	4444,
14414	/* FDIV_S_MM */	14414	/* FDIV_S_MM */
14415	4447,	14415	4447,
14416	/* FDIV_S_MMR6 */	14416	/* FDIV_S_MMR6 */
14417	4450,	14417	4450,
14418	/* FDIV_W */	14418	/* FDIV_W */
14419	4453,	14419	4453,
14420	/* FEXDO_H */	14420	/* FEXDO_H */
14421	4456,	14421	4456,
14422	/* FEXDO_W */	14422	/* FEXDO_W */
14423	4459,	14423	4459,
14424	/* FEXP2_D */	14424	/* FEXP2_D */
14425	4462,	14425	4462,
14426	/* FEXP2_W */	14426	/* FEXP2_W */
14427	4465,	14427	4465,
14428	/* FEXUPL_D */	14428	/* FEXUPL_D */
14429	4468,	14429	4468,
14430	/* FEXUPL_W */	14430	/* FEXUPL_W */
14431	4470,	14431	4470,
14432	/* FEXUPR_D */	14432	/* FEXUPR_D */
14433	4472,	14433	4472,
14434	/* FEXUPR_W */	14434	/* FEXUPR_W */
14435	4474,	14435	4474,
14436	/* FFINT_S_D */	14436	/* FFINT_S_D */
14437	4476,	14437	4476,
14438	/* FFINT_S_W */	14438	/* FFINT_S_W */
14439	4478,	14439	4478,
14440	/* FFINT_U_D */	14440	/* FFINT_U_D */
14441	4480,	14441	4480,
14442	/* FFINT_U_W */	14442	/* FFINT_U_W */
14443	4482,	14443	4482,
14444	/* FFQL_D */	14444	/* FFQL_D */
14445	4484,	14445	4484,
14446	/* FFQL_W */	14446	/* FFQL_W */
14447	4486,	14447	4486,
14448	/* FFQR_D */	14448	/* FFQR_D */
14449	4488,	14449	4488,
14450	/* FFQR_W */	14450	/* FFQR_W */
14451	4490,	14451	4490,
14452	/* FILL_B */	14452	/* FILL_B */
14453	4492,	14453	4492,
14454	/* FILL_D */	14454	/* FILL_D */
14455	4494,	14455	4494,
14456	/* FILL_H */	14456	/* FILL_H */
14457	4496,	14457	4496,
14458	/* FILL_W */	14458	/* FILL_W */
14459	4498,	14459	4498,
14460	/* FLOG2_D */	14460	/* FLOG2_D */
14461	4500,	14461	4500,
14462	/* FLOG2_W */	14462	/* FLOG2_W */
14463	4502,	14463	4502,
14464	/* FLOOR_L_D64 */	14464	/* FLOOR_L_D64 */
14465	4504,	14465	4504,
14466	/* FLOOR_L_D_MMR6 */	14466	/* FLOOR_L_D_MMR6 */
14467	4506,	14467	4506,
14468	/* FLOOR_L_S */	14468	/* FLOOR_L_S */
14469	4508,	14469	4508,
14470	/* FLOOR_L_S_MMR6 */	14470	/* FLOOR_L_S_MMR6 */
14471	4510,	14471	4510,
14472	/* FLOOR_W_D32 */	14472	/* FLOOR_W_D32 */
14473	4512,	14473	4512,
14474	/* FLOOR_W_D64 */	14474	/* FLOOR_W_D64 */
14475	4514,	14475	4514,
14476	/* FLOOR_W_D_MMR6 */	14476	/* FLOOR_W_D_MMR6 */
14477	4516,	14477	4516,
14478	/* FLOOR_W_MM */	14478	/* FLOOR_W_MM */
14479	4518,	14479	4518,
14480	/* FLOOR_W_S */	14480	/* FLOOR_W_S */
14481	4520,	14481	4520,
14482	/* FLOOR_W_S_MM */	14482	/* FLOOR_W_S_MM */
14483	4522,	14483	4522,
14484	/* FLOOR_W_S_MMR6 */	14484	/* FLOOR_W_S_MMR6 */
14485	4524,	14485	4524,
14486	/* FMADD_D */	14486	/* FMADD_D */
14487	4526,	14487	4526,
14488	/* FMADD_W */	14488	/* FMADD_W */
14489	4530,	14489	4530,
14490	/* FMAX_A_D */	14490	/* FMAX_A_D */
14491	4534,	14491	4534,
14492	/* FMAX_A_W */	14492	/* FMAX_A_W */
14493	4537,	14493	4537,
14494	/* FMAX_D */	14494	/* FMAX_D */
14495	4540,	14495	4540,
14496	/* FMAX_W */	14496	/* FMAX_W */
14497	4543,	14497	4543,
14498	/* FMIN_A_D */	14498	/* FMIN_A_D */
14499	4546,	14499	4546,
14500	/* FMIN_A_W */	14500	/* FMIN_A_W */
14501	4549,	14501	4549,
14502	/* FMIN_D */	14502	/* FMIN_D */
14503	4552,	14503	4552,
14504	/* FMIN_W */	14504	/* FMIN_W */
14505	4555,	14505	4555,
14506	/* FMOV_D32 */	14506	/* FMOV_D32 */
14507	4558,	14507	4558,
14508	/* FMOV_D32_MM */	14508	/* FMOV_D32_MM */
14509	4560,	14509	4560,
14510	/* FMOV_D64 */	14510	/* FMOV_D64 */
14511	4562,	14511	4562,
14512	/* FMOV_D64_MM */	14512	/* FMOV_D64_MM */
14513	4564,	14513	4564,
14514	/* FMOV_D_MMR6 */	14514	/* FMOV_D_MMR6 */
14515	4566,	14515	4566,
14516	/* FMOV_S */	14516	/* FMOV_S */
14517	4568,	14517	4568,
14518	/* FMOV_S_MM */	14518	/* FMOV_S_MM */
14519	4570,	14519	4570,
14520	/* FMOV_S_MMR6 */	14520	/* FMOV_S_MMR6 */
14521	4572,	14521	4572,
14522	/* FMSUB_D */	14522	/* FMSUB_D */
14523	4574,	14523	4574,
14524	/* FMSUB_W */	14524	/* FMSUB_W */
14525	4578,	14525	4578,
14526	/* FMUL_D */	14526	/* FMUL_D */
14527	4582,	14527	4582,
14528	/* FMUL_D32 */	14528	/* FMUL_D32 */
14529	4585,	14529	4585,
14530	/* FMUL_D32_MM */	14530	/* FMUL_D32_MM */
14531	4588,	14531	4588,
14532	/* FMUL_D64 */	14532	/* FMUL_D64 */
14533	4591,	14533	4591,
14534	/* FMUL_D64_MM */	14534	/* FMUL_D64_MM */
14535	4594,	14535	4594,
14536	/* FMUL_PS64 */	14536	/* FMUL_PS64 */
14537	4597,	14537	4597,
14538	/* FMUL_S */	14538	/* FMUL_S */
14539	4600,	14539	4600,
14540	/* FMUL_S_MM */	14540	/* FMUL_S_MM */
14541	4603,	14541	4603,
14542	/* FMUL_S_MMR6 */	14542	/* FMUL_S_MMR6 */
14543	4606,	14543	4606,
14544	/* FMUL_W */	14544	/* FMUL_W */
14545	4609,	14545	4609,
14546	/* FNEG_D32 */	14546	/* FNEG_D32 */
14547	4612,	14547	4612,
14548	/* FNEG_D32_MM */	14548	/* FNEG_D32_MM */
14549	4614,	14549	4614,
14550	/* FNEG_D64 */	14550	/* FNEG_D64 */
14551	4616,	14551	4616,
14552	/* FNEG_D64_MM */	14552	/* FNEG_D64_MM */
14553	4618,	14553	4618,
14554	/* FNEG_S */	14554	/* FNEG_S */
14555	4620,	14555	4620,
14556	/* FNEG_S_MM */	14556	/* FNEG_S_MM */
14557	4622,	14557	4622,
14558	/* FNEG_S_MMR6 */	14558	/* FNEG_S_MMR6 */
14559	4624,	14559	4624,
14560	/* FORK */	14560	/* FORK */
14561	4626,	14561	4626,
14562	/* FRCP_D */	14562	/* FRCP_D */
14563	4629,	14563	4629,
14564	/* FRCP_W */	14564	/* FRCP_W */
14565	4631,	14565	4631,
14566	/* FRINT_D */	14566	/* FRINT_D */
14567	4633,	14567	4633,
14568	/* FRINT_W */	14568	/* FRINT_W */
14569	4635,	14569	4635,
14570	/* FRSQRT_D */	14570	/* FRSQRT_D */
14571	4637,	14571	4637,
14572	/* FRSQRT_W */	14572	/* FRSQRT_W */
14573	4639,	14573	4639,
14574	/* FSAF_D */	14574	/* FSAF_D */
14575	4641,	14575	4641,
14576	/* FSAF_W */	14576	/* FSAF_W */
14577	4644,	14577	4644,
14578	/* FSEQ_D */	14578	/* FSEQ_D */
14579	4647,	14579	4647,
14580	/* FSEQ_W */	14580	/* FSEQ_W */
14581	4650,	14581	4650,
14582	/* FSLE_D */	14582	/* FSLE_D */
14583	4653,	14583	4653,
14584	/* FSLE_W */	14584	/* FSLE_W */
14585	4656,	14585	4656,
14586	/* FSLT_D */	14586	/* FSLT_D */
14587	4659,	14587	4659,
14588	/* FSLT_W */	14588	/* FSLT_W */
14589	4662,	14589	4662,
14590	/* FSNE_D */	14590	/* FSNE_D */
14591	4665,	14591	4665,
14592	/* FSNE_W */	14592	/* FSNE_W */
14593	4668,	14593	4668,
14594	/* FSOR_D */	14594	/* FSOR_D */
14595	4671,	14595	4671,
14596	/* FSOR_W */	14596	/* FSOR_W */
14597	4674,	14597	4674,
14598	/* FSQRT_D */	14598	/* FSQRT_D */
14599	4677,	14599	4677,
14600	/* FSQRT_D32 */	14600	/* FSQRT_D32 */
14601	4679,	14601	4679,
14602	/* FSQRT_D32_MM */	14602	/* FSQRT_D32_MM */
14603	4681,	14603	4681,
14604	/* FSQRT_D64 */	14604	/* FSQRT_D64 */
14605	4683,	14605	4683,
14606	/* FSQRT_D64_MM */	14606	/* FSQRT_D64_MM */
14607	4685,	14607	4685,
14608	/* FSQRT_S */	14608	/* FSQRT_S */
14609	4687,	14609	4687,
14610	/* FSQRT_S_MM */	14610	/* FSQRT_S_MM */
14611	4689,	14611	4689,
14612	/* FSQRT_W */	14612	/* FSQRT_W */
14613	4691,	14613	4691,
14614	/* FSUB_D */	14614	/* FSUB_D */
14615	4693,	14615	4693,
14616	/* FSUB_D32 */	14616	/* FSUB_D32 */
14617	4696,	14617	4696,
14618	/* FSUB_D32_MM */	14618	/* FSUB_D32_MM */
14619	4699,	14619	4699,
14620	/* FSUB_D64 */	14620	/* FSUB_D64 */
14621	4702,	14621	4702,
14622	/* FSUB_D64_MM */	14622	/* FSUB_D64_MM */
14623	4705,	14623	4705,
14624	/* FSUB_PS64 */	14624	/* FSUB_PS64 */
14625	4708,	14625	4708,
14626	/* FSUB_S */	14626	/* FSUB_S */
14627	4711,	14627	4711,
14628	/* FSUB_S_MM */	14628	/* FSUB_S_MM */
14629	4714,	14629	4714,
14630	/* FSUB_S_MMR6 */	14630	/* FSUB_S_MMR6 */
14631	4717,	14631	4717,
14632	/* FSUB_W */	14632	/* FSUB_W */
14633	4720,	14633	4720,
14634	/* FSUEQ_D */	14634	/* FSUEQ_D */
14635	4723,	14635	4723,
14636	/* FSUEQ_W */	14636	/* FSUEQ_W */
14637	4726,	14637	4726,
14638	/* FSULE_D */	14638	/* FSULE_D */
14639	4729,	14639	4729,
14640	/* FSULE_W */	14640	/* FSULE_W */
14641	4732,	14641	4732,
14642	/* FSULT_D */	14642	/* FSULT_D */
14643	4735,	14643	4735,
14644	/* FSULT_W */	14644	/* FSULT_W */
14645	4738,	14645	4738,
14646	/* FSUNE_D */	14646	/* FSUNE_D */
14647	4741,	14647	4741,
14648	/* FSUNE_W */	14648	/* FSUNE_W */
14649	4744,	14649	4744,
14650	/* FSUN_D */	14650	/* FSUN_D */
14651	4747,	14651	4747,
14652	/* FSUN_W */	14652	/* FSUN_W */
14653	4750,	14653	4750,
14654	/* FTINT_S_D */	14654	/* FTINT_S_D */
14655	4753,	14655	4753,
14656	/* FTINT_S_W */	14656	/* FTINT_S_W */
14657	4755,	14657	4755,
14658	/* FTINT_U_D */	14658	/* FTINT_U_D */
14659	4757,	14659	4757,
14660	/* FTINT_U_W */	14660	/* FTINT_U_W */
14661	4759,	14661	4759,
14662	/* FTQ_H */	14662	/* FTQ_H */
14663	4761,	14663	4761,
14664	/* FTQ_W */	14664	/* FTQ_W */
14665	4764,	14665	4764,
14666	/* FTRUNC_S_D */	14666	/* FTRUNC_S_D */
14667	4767,	14667	4767,
14668	/* FTRUNC_S_W */	14668	/* FTRUNC_S_W */
14669	4769,	14669	4769,
14670	/* FTRUNC_U_D */	14670	/* FTRUNC_U_D */
14671	4771,	14671	4771,
14672	/* FTRUNC_U_W */	14672	/* FTRUNC_U_W */
14673	4773,	14673	4773,
14674	/* GINVI */	14674	/* GINVI */
14675	4775,	14675	4775,
14676	/* GINVI_MMR6 */	14676	/* GINVI_MMR6 */
14677	4776,	14677	4776,
14678	/* GINVT */	14678	/* GINVT */
14679	4777,	14679	4777,
14680	/* GINVT_MMR6 */	14680	/* GINVT_MMR6 */
14681	4779,	14681	4779,
14682	/* HADD_S_D */	14682	/* HADD_S_D */
14683	4781,	14683	4781,
14684	/* HADD_S_H */	14684	/* HADD_S_H */
14685	4784,	14685	4784,
14686	/* HADD_S_W */	14686	/* HADD_S_W */
14687	4787,	14687	4787,
14688	/* HADD_U_D */	14688	/* HADD_U_D */
14689	4790,	14689	4790,
14690	/* HADD_U_H */	14690	/* HADD_U_H */
14691	4793,	14691	4793,
14692	/* HADD_U_W */	14692	/* HADD_U_W */
14693	4796,	14693	4796,
14694	/* HSUB_S_D */	14694	/* HSUB_S_D */
14695	4799,	14695	4799,
14696	/* HSUB_S_H */	14696	/* HSUB_S_H */
14697	4802,	14697	4802,
14698	/* HSUB_S_W */	14698	/* HSUB_S_W */
14699	4805,	14699	4805,
14700	/* HSUB_U_D */	14700	/* HSUB_U_D */
14701	4808,	14701	4808,
14702	/* HSUB_U_H */	14702	/* HSUB_U_H */
14703	4811,	14703	4811,
14704	/* HSUB_U_W */	14704	/* HSUB_U_W */
14705	4814,	14705	4814,
14706	/* HYPCALL */	14706	/* HYPCALL */
14707	4817,	14707	4817,
14708	/* HYPCALL_MM */	14708	/* HYPCALL_MM */
14709	4818,	14709	4818,
14710	/* ILVEV_B */	14710	/* ILVEV_B */
14711	4819,	14711	4819,
14712	/* ILVEV_D */	14712	/* ILVEV_D */
14713	4822,	14713	4822,
14714	/* ILVEV_H */	14714	/* ILVEV_H */
14715	4825,	14715	4825,
14716	/* ILVEV_W */	14716	/* ILVEV_W */
14717	4828,	14717	4828,
14718	/* ILVL_B */	14718	/* ILVL_B */
14719	4831,	14719	4831,
14720	/* ILVL_D */	14720	/* ILVL_D */
14721	4834,	14721	4834,
14722	/* ILVL_H */	14722	/* ILVL_H */
14723	4837,	14723	4837,
14724	/* ILVL_W */	14724	/* ILVL_W */
14725	4840,	14725	4840,
14726	/* ILVOD_B */	14726	/* ILVOD_B */
14727	4843,	14727	4843,
14728	/* ILVOD_D */	14728	/* ILVOD_D */
14729	4846,	14729	4846,
14730	/* ILVOD_H */	14730	/* ILVOD_H */
14731	4849,	14731	4849,
14732	/* ILVOD_W */	14732	/* ILVOD_W */
14733	4852,	14733	4852,
14734	/* ILVR_B */	14734	/* ILVR_B */
14735	4855,	14735	4855,
14736	/* ILVR_D */	14736	/* ILVR_D */
14737	4858,	14737	4858,
14738	/* ILVR_H */	14738	/* ILVR_H */
14739	4861,	14739	4861,
14740	/* ILVR_W */	14740	/* ILVR_W */
14741	4864,	14741	4864,
14742	/* INS */	14742	/* INS */
14743	4867,	14743	4867,
14744	/* INSERT_B */	14744	/* INSERT_B */
14745	4872,	14745	4872,
14746	/* INSERT_D */	14746	/* INSERT_D */
14747	4876,	14747	4876,
14748	/* INSERT_H */	14748	/* INSERT_H */
14749	4880,	14749	4880,
14750	/* INSERT_W */	14750	/* INSERT_W */
14751	4884,	14751	4884,
14752	/* INSV */	14752	/* INSV */
14753	4888,	14753	4888,
14754	/* INSVE_B */	14754	/* INSVE_B */
14755	4891,	14755	4891,
14756	/* INSVE_D */	14756	/* INSVE_D */
14757	4896,	14757	4896,
14758	/* INSVE_H */	14758	/* INSVE_H */
14759	4901,	14759	4901,
14760	/* INSVE_W */	14760	/* INSVE_W */
14761	4906,	14761	4906,
14762	/* INSV_MM */	14762	/* INSV_MM */
14763	4911,	14763	4911,
14764	/* INS_MM */	14764	/* INS_MM */
14765	4914,	14765	4914,
14766	/* INS_MMR6 */	14766	/* INS_MMR6 */
14767	4919,	14767	4919,
14768	/* J */	14768	/* J */
14769	4924,	14769	4924,
14770	/* JAL */	14770	/* JAL */
14771	4925,	14771	4925,
14772	/* JALR */	14772	/* JALR */
14773	4926,	14773	4926,
14774	/* JALR16_MM */	14774	/* JALR16_MM */
14775	4928,	14775	4928,
14776	/* JALR64 */	14776	/* JALR64 */
14777	4929,	14777	4929,
14778	/* JALRC16_MMR6 */	14778	/* JALRC16_MMR6 */
14779	4931,	14779	4931,
14780	/* JALRC_HB_MMR6 */	14780	/* JALRC_HB_MMR6 */
14781	4932,	14781	4932,
14782	/* JALRC_MMR6 */	14782	/* JALRC_MMR6 */
14783	4934,	14783	4934,
14784	/* JALRS16_MM */	14784	/* JALRS16_MM */
14785	4936,	14785	4936,
14786	/* JALRS_MM */	14786	/* JALRS_MM */
14787	4937,	14787	4937,
14788	/* JALR_HB */	14788	/* JALR_HB */
14789	4939,	14789	4939,
14790	/* JALR_HB64 */	14790	/* JALR_HB64 */
14791	4941,	14791	4941,
14792	/* JALR_MM */	14792	/* JALR_MM */
14793	4943,	14793	4943,
14794	/* JALS_MM */	14794	/* JALS_MM */
14795	4945,	14795	4945,
14796	/* JALX */	14796	/* JALX */
14797	4946,	14797	4946,
14798	/* JALX_MM */	14798	/* JALX_MM */
14799	4947,	14799	4947,
14800	/* JAL_MM */	14800	/* JAL_MM */
14801	4948,	14801	4948,
14802	/* JIALC */	14802	/* JIALC */
14803	4949,	14803	4949,
14804	/* JIALC64 */	14804	/* JIALC64 */
14805	4951,	14805	4951,
14806	/* JIALC_MMR6 */	14806	/* JIALC_MMR6 */
14807	4953,	14807	4953,
14808	/* JIC */	14808	/* JIC */
14809	4955,	14809	4955,
14810	/* JIC64 */	14810	/* JIC64 */
14811	4957,	14811	4957,
14812	/* JIC_MMR6 */	14812	/* JIC_MMR6 */
14813	4959,	14813	4959,
14814	/* JR */	14814	/* JR */
14815	4961,	14815	4961,
14816	/* JR16_MM */	14816	/* JR16_MM */
14817	4962,	14817	4962,
14818	/* JR64 */	14818	/* JR64 */
14819	4963,	14819	4963,
14820	/* JRADDIUSP */	14820	/* JRADDIUSP */
14821	4964,	14821	4964,
14822	/* JRC16_MM */	14822	/* JRC16_MM */
14823	4965,	14823	4965,
14824	/* JRC16_MMR6 */	14824	/* JRC16_MMR6 */
14825	4966,	14825	4966,
14826	/* JRCADDIUSP_MMR6 */	14826	/* JRCADDIUSP_MMR6 */
14827	4967,	14827	4967,
14828	/* JR_HB */	14828	/* JR_HB */
14829	4968,	14829	4968,
14830	/* JR_HB64 */	14830	/* JR_HB64 */
14831	4969,	14831	4969,
14832	/* JR_HB64_R6 */	14832	/* JR_HB64_R6 */
14833	4970,	14833	4970,
14834	/* JR_HB_R6 */	14834	/* JR_HB_R6 */
14835	4971,	14835	4971,
14836	/* JR_MM */	14836	/* JR_MM */
14837	4972,	14837	4972,
14838	/* J_MM */	14838	/* J_MM */
14839	4973,	14839	4973,
14840	/* Jal16 */	14840	/* Jal16 */
14841	4974,	14841	4974,
14842	/* JalB16 */	14842	/* JalB16 */
14843	4975,	14843	4975,
14844	/* JrRa16 */	14844	/* JrRa16 */
14845	4976,	14845	4976,
14846	/* JrcRa16 */	14846	/* JrcRa16 */
14847	4976,	14847	4976,
14848	/* JrcRx16 */	14848	/* JrcRx16 */
14849	4976,	14849	4976,
14850	/* JumpLinkReg16 */	14850	/* JumpLinkReg16 */
14851	4977,	14851	4977,
14852	/* LB */	14852	/* LB */
14853	4978,	14853	4978,
14854	/* LB64 */	14854	/* LB64 */
14855	4981,	14855	4981,
14856	/* LBE */	14856	/* LBE */
14857	4984,	14857	4984,
14858	/* LBE_MM */	14858	/* LBE_MM */
14859	4987,	14859	4987,
14860	/* LBU16_MM */	14860	/* LBU16_MM */
14861	4990,	14861	4990,
14862	/* LBUX */	14862	/* LBUX */
14863	4993,	14863	4993,
14864	/* LBUX_MM */	14864	/* LBUX_MM */
14865	4996,	14865	4996,
14866	/* LBU_MMR6 */	14866	/* LBU_MMR6 */
14867	4999,	14867	4999,
14868	/* LB_MM */	14868	/* LB_MM */
14869	5002,	14869	5002,
14870	/* LB_MMR6 */	14870	/* LB_MMR6 */
14871	5005,	14871	5005,
14872	/* LBu */	14872	/* LBu */
14873	5008,	14873	5008,
14874	/* LBu64 */	14874	/* LBu64 */
14875	5011,	14875	5011,
14876	/* LBuE */	14876	/* LBuE */
14877	5014,	14877	5014,
14878	/* LBuE_MM */	14878	/* LBuE_MM */
14879	5017,	14879	5017,
14880	/* LBu_MM */	14880	/* LBu_MM */
14881	5020,	14881	5020,
14882	/* LD */	14882	/* LD */
14883	5023,	14883	5023,
14884	/* LDC1 */	14884	/* LDC1 */
14885	5026,	14885	5026,
14886	/* LDC164 */	14886	/* LDC164 */
14887	5029,	14887	5029,
14888	/* LDC1_D64_MMR6 */	14888	/* LDC1_D64_MMR6 */
14889	5032,	14889	5032,
14890	/* LDC1_MM_D32 */	14890	/* LDC1_MM_D32 */
14891	5035,	14891	5035,
14892	/* LDC1_MM_D64 */	14892	/* LDC1_MM_D64 */
14893	5038,	14893	5038,
14894	/* LDC2 */	14894	/* LDC2 */
14895	5041,	14895	5041,
14896	/* LDC2_MMR6 */	14896	/* LDC2_MMR6 */
14897	5044,	14897	5044,
14898	/* LDC2_R6 */	14898	/* LDC2_R6 */
14899	5047,	14899	5047,
14900	/* LDC3 */	14900	/* LDC3 */
14901	5050,	14901	5050,
14902	/* LDI_B */	14902	/* LDI_B */
14903	5053,	14903	5053,
14904	/* LDI_D */	14904	/* LDI_D */
14905	5055,	14905	5055,
14906	/* LDI_H */	14906	/* LDI_H */
14907	5057,	14907	5057,
14908	/* LDI_W */	14908	/* LDI_W */
14909	5059,	14909	5059,
14910	/* LDL */	14910	/* LDL */
14911	5061,	14911	5061,
14912	/* LDPC */	14912	/* LDPC */
14913	5065,	14913	5065,
14914	/* LDR */	14914	/* LDR */
14915	5067,	14915	5067,
14916	/* LDXC1 */	14916	/* LDXC1 */
14917	5071,	14917	5071,
14918	/* LDXC164 */	14918	/* LDXC164 */
14919	5074,	14919	5074,
14920	/* LD_B */	14920	/* LD_B */
14921	5077,	14921	5077,
14922	/* LD_D */	14922	/* LD_D */
14923	5080,	14923	5080,
14924	/* LD_H */	14924	/* LD_H */
14925	5083,	14925	5083,
14926	/* LD_W */	14926	/* LD_W */
14927	5086,	14927	5086,
14928	/* LEA_ADDiu */	14928	/* LEA_ADDiu */
14929	5089,	14929	5089,
14930	/* LEA_ADDiu64 */	14930	/* LEA_ADDiu64 */
14931	5092,	14931	5092,
14932	/* LEA_ADDiu_MM */	14932	/* LEA_ADDiu_MM */
14933	5095,	14933	5095,
14934	/* LH */	14934	/* LH */
14935	5098,	14935	5098,
14936	/* LH64 */	14936	/* LH64 */
14937	5101,	14937	5101,
14938	/* LHE */	14938	/* LHE */
14939	5104,	14939	5104,
14940	/* LHE_MM */	14940	/* LHE_MM */
14941	5107,	14941	5107,
14942	/* LHU16_MM */	14942	/* LHU16_MM */
14943	5110,	14943	5110,
14944	/* LHX */	14944	/* LHX */
14945	5113,	14945	5113,
14946	/* LHX_MM */	14946	/* LHX_MM */
14947	5116,	14947	5116,
14948	/* LH_MM */	14948	/* LH_MM */
14949	5119,	14949	5119,
14950	/* LHu */	14950	/* LHu */
14951	5122,	14951	5122,
14952	/* LHu64 */	14952	/* LHu64 */
14953	5125,	14953	5125,
14954	/* LHuE */	14954	/* LHuE */
14955	5128,	14955	5128,
14956	/* LHuE_MM */	14956	/* LHuE_MM */
14957	5131,	14957	5131,
14958	/* LHu_MM */	14958	/* LHu_MM */
14959	5134,	14959	5134,
14960	/* LI16_MM */	14960	/* LI16_MM */
14961	5137,	14961	5137,
14962	/* LI16_MMR6 */	14962	/* LI16_MMR6 */
14963	5139,	14963	5139,
14964	/* LL */	14964	/* LL */
14965	5141,	14965	5141,
14966	/* LL64 */	14966	/* LL64 */
14967	5144,	14967	5144,
14968	/* LL64_R6 */	14968	/* LL64_R6 */
14969	5147,	14969	5147,
14970	/* LLD */	14970	/* LLD */
14971	5150,	14971	5150,
14972	/* LLD_R6 */	14972	/* LLD_R6 */
14973	5153,	14973	5153,
14974	/* LLE */	14974	/* LLE */
14975	5156,	14975	5156,
14976	/* LLE_MM */	14976	/* LLE_MM */
14977	5159,	14977	5159,
14978	/* LL_MM */	14978	/* LL_MM */
14979	5162,	14979	5162,
14980	/* LL_MMR6 */	14980	/* LL_MMR6 */
14981	5165,	14981	5165,
14982	/* LL_R6 */	14982	/* LL_R6 */
14983	5168,	14983	5168,
14984	/* LSA */	14984	/* LSA */
14985	5171,	14985	5171,
14986	/* LSA_MMR6 */	14986	/* LSA_MMR6 */
14987	5175,	14987	5175,
14988	/* LSA_R6 */	14988	/* LSA_R6 */
14989	5179,	14989	5179,
14990	/* LUI_MMR6 */	14990	/* LUI_MMR6 */
14991	5183,	14991	5183,
14992	/* LUXC1 */	14992	/* LUXC1 */
14993	5185,	14993	5185,
14994	/* LUXC164 */	14994	/* LUXC164 */
14995	5188,	14995	5188,
14996	/* LUXC1_MM */	14996	/* LUXC1_MM */
14997	5191,	14997	5191,
14998	/* LUi */	14998	/* LUi */
14999	5194,	14999	5194,
15000	/* LUi64 */	15000	/* LUi64 */
15001	5196,	15001	5196,
15002	/* LUi_MM */	15002	/* LUi_MM */
15003	5198,	15003	5198,
15004	/* LW */	15004	/* LW */
15005	5200,	15005	5200,
15006	/* LW16_MM */	15006	/* LW16_MM */
15007	5203,	15007	5203,
15008	/* LW64 */	15008	/* LW64 */
15009	5206,	15009	5206,
15010	/* LWC1 */	15010	/* LWC1 */
15011	5209,	15011	5209,
15012	/* LWC1_MM */	15012	/* LWC1_MM */
15013	5212,	15013	5212,
15014	/* LWC2 */	15014	/* LWC2 */
15015	5215,	15015	5215,
15016	/* LWC2_MMR6 */	15016	/* LWC2_MMR6 */
15017	5218,	15017	5218,
15018	/* LWC2_R6 */	15018	/* LWC2_R6 */
15019	5221,	15019	5221,
15020	/* LWC3 */	15020	/* LWC3 */
15021	5224,	15021	5224,
15022	/* LWDSP */	15022	/* LWDSP */
15023	5227,	15023	5227,
15024	/* LWDSP_MM */	15024	/* LWDSP_MM */
15025	5230,	15025	5230,
15026	/* LWE */	15026	/* LWE */
15027	5233,	15027	5233,
15028	/* LWE_MM */	15028	/* LWE_MM */
15029	5236,	15029	5236,
15030	/* LWGP_MM */	15030	/* LWGP_MM */
15031	5239,	15031	5239,
15032	/* LWL */	15032	/* LWL */
15033	5242,	15033	5242,
15034	/* LWL64 */	15034	/* LWL64 */
15035	5246,	15035	5246,
15036	/* LWLE */	15036	/* LWLE */
15037	5250,	15037	5250,
15038	/* LWLE_MM */	15038	/* LWLE_MM */
15039	5254,	15039	5254,
15040	/* LWL_MM */	15040	/* LWL_MM */
15041	5258,	15041	5258,
15042	/* LWM16_MM */	15042	/* LWM16_MM */
15043	5262,	15043	5262,
15044	/* LWM16_MMR6 */	15044	/* LWM16_MMR6 */
15045	5265,	15045	5265,
15046	/* LWM32_MM */	15046	/* LWM32_MM */
15047	5268,	15047	5268,
15048	/* LWPC */	15048	/* LWPC */
15049	5271,	15049	5271,
15050	/* LWPC_MMR6 */	15050	/* LWPC_MMR6 */
15051	5273,	15051	5273,
15052	/* LWP_MM */	15052	/* LWP_MM */
15053	5275,	15053	5275,
15054	/* LWR */	15054	/* LWR */
15055	5279,	15055	5279,
15056	/* LWR64 */	15056	/* LWR64 */
15057	5283,	15057	5283,
15058	/* LWRE */	15058	/* LWRE */
15059	5287,	15059	5287,
15060	/* LWRE_MM */	15060	/* LWRE_MM */
15061	5291,	15061	5291,
15062	/* LWR_MM */	15062	/* LWR_MM */
15063	5295,	15063	5295,
15064	/* LWSP_MM */	15064	/* LWSP_MM */
15065	5299,	15065	5299,
15066	/* LWUPC */	15066	/* LWUPC */
15067	5302,	15067	5302,
15068	/* LWU_MM */	15068	/* LWU_MM */
15069	5304,	15069	5304,
15070	/* LWX */	15070	/* LWX */
15071	5307,	15071	5307,
15072	/* LWXC1 */	15072	/* LWXC1 */
15073	5310,	15073	5310,
15074	/* LWXC1_MM */	15074	/* LWXC1_MM */
15075	5313,	15075	5313,
15076	/* LWXS_MM */	15076	/* LWXS_MM */
15077	5316,	15077	5316,
15078	/* LWX_MM */	15078	/* LWX_MM */
15079	5319,	15079	5319,
15080	/* LW_MM */	15080	/* LW_MM */
15081	5322,	15081	5322,
15082	/* LW_MMR6 */	15082	/* LW_MMR6 */
15083	5325,	15083	5325,
15084	/* LWu */	15084	/* LWu */
15085	5328,	15085	5328,
15086	/* LbRxRyOffMemX16 */	15086	/* LbRxRyOffMemX16 */
15087	5331,	15087	5331,
15088	/* LbuRxRyOffMemX16 */	15088	/* LbuRxRyOffMemX16 */
15089	5334,	15089	5334,
15090	/* LhRxRyOffMemX16 */	15090	/* LhRxRyOffMemX16 */
15091	5337,	15091	5337,
15092	/* LhuRxRyOffMemX16 */	15092	/* LhuRxRyOffMemX16 */
15093	5340,	15093	5340,
15094	/* LiRxImm16 */	15094	/* LiRxImm16 */
15095	5343,	15095	5343,
15096	/* LiRxImmAlignX16 */	15096	/* LiRxImmAlignX16 */
15097	5345,	15097	5345,
15098	/* LiRxImmX16 */	15098	/* LiRxImmX16 */
15099	5347,	15099	5347,
15100	/* LwRxPcTcp16 */	15100	/* LwRxPcTcp16 */
15101	5349,	15101	5349,
15102	/* LwRxPcTcpX16 */	15102	/* LwRxPcTcpX16 */
15103	5352,	15103	5352,
15104	/* LwRxRyOffMemX16 */	15104	/* LwRxRyOffMemX16 */
15105	5355,	15105	5355,
15106	/* LwRxSpImmX16 */	15106	/* LwRxSpImmX16 */
15107	5358,	15107	5358,
15108	/* MADD */	15108	/* MADD */
15109	5361,	15109	5361,
15110	/* MADDF_D */	15110	/* MADDF_D */
15111	5363,	15111	5363,
15112	/* MADDF_D_MMR6 */	15112	/* MADDF_D_MMR6 */
15113	5367,	15113	5367,
15114	/* MADDF_S */	15114	/* MADDF_S */
15115	5371,	15115	5371,
15116	/* MADDF_S_MMR6 */	15116	/* MADDF_S_MMR6 */
15117	5375,	15117	5375,
15118	/* MADDR_Q_H */	15118	/* MADDR_Q_H */
15119	5379,	15119	5379,
15120	/* MADDR_Q_W */	15120	/* MADDR_Q_W */
15121	5383,	15121	5383,
15122	/* MADDU */	15122	/* MADDU */
15123	5387,	15123	5387,
15124	/* MADDU_DSP */	15124	/* MADDU_DSP */
15125	5389,	15125	5389,
15126	/* MADDU_DSP_MM */	15126	/* MADDU_DSP_MM */
15127	5393,	15127	5393,
15128	/* MADDU_MM */	15128	/* MADDU_MM */
15129	5397,	15129	5397,
15130	/* MADDV_B */	15130	/* MADDV_B */
15131	5399,	15131	5399,
15132	/* MADDV_D */	15132	/* MADDV_D */
15133	5403,	15133	5403,
15134	/* MADDV_H */	15134	/* MADDV_H */
15135	5407,	15135	5407,
15136	/* MADDV_W */	15136	/* MADDV_W */
15137	5411,	15137	5411,
15138	/* MADD_D32 */	15138	/* MADD_D32 */
15139	5415,	15139	5415,
15140	/* MADD_D32_MM */	15140	/* MADD_D32_MM */
15141	5419,	15141	5419,
15142	/* MADD_D64 */	15142	/* MADD_D64 */
15143	5423,	15143	5423,
15144	/* MADD_DSP */	15144	/* MADD_DSP */
15145	5427,	15145	5427,
15146	/* MADD_DSP_MM */	15146	/* MADD_DSP_MM */
15147	5431,	15147	5431,
15148	/* MADD_MM */	15148	/* MADD_MM */
15149	5435,	15149	5435,
15150	/* MADD_Q_H */	15150	/* MADD_Q_H */
15151	5437,	15151	5437,
15152	/* MADD_Q_W */	15152	/* MADD_Q_W */
15153	5441,	15153	5441,
15154	/* MADD_S */	15154	/* MADD_S */
15155	5445,	15155	5445,
15156	/* MADD_S_MM */	15156	/* MADD_S_MM */
15157	5449,	15157	5449,
15158	/* MAQ_SA_W_PHL */	15158	/* MAQ_SA_W_PHL */
15159	5453,	15159	5453,
15160	/* MAQ_SA_W_PHL_MM */	15160	/* MAQ_SA_W_PHL_MM */
15161	5457,	15161	5457,
15162	/* MAQ_SA_W_PHR */	15162	/* MAQ_SA_W_PHR */
15163	5461,	15163	5461,
15164	/* MAQ_SA_W_PHR_MM */	15164	/* MAQ_SA_W_PHR_MM */
15165	5465,	15165	5465,
15166	/* MAQ_S_W_PHL */	15166	/* MAQ_S_W_PHL */
15167	5469,	15167	5469,
15168	/* MAQ_S_W_PHL_MM */	15168	/* MAQ_S_W_PHL_MM */
15169	5473,	15169	5473,
15170	/* MAQ_S_W_PHR */	15170	/* MAQ_S_W_PHR */
15171	5477,	15171	5477,
15172	/* MAQ_S_W_PHR_MM */	15172	/* MAQ_S_W_PHR_MM */
15173	5481,	15173	5481,
15174	/* MAXA_D */	15174	/* MAXA_D */
15175	5485,	15175	5485,
15176	/* MAXA_D_MMR6 */	15176	/* MAXA_D_MMR6 */
15177	5488,	15177	5488,
15178	/* MAXA_S */	15178	/* MAXA_S */
15179	5491,	15179	5491,
15180	/* MAXA_S_MMR6 */	15180	/* MAXA_S_MMR6 */
15181	5494,	15181	5494,
15182	/* MAXI_S_B */	15182	/* MAXI_S_B */
15183	5497,	15183	5497,
15184	/* MAXI_S_D */	15184	/* MAXI_S_D */
15185	5500,	15185	5500,
15186	/* MAXI_S_H */	15186	/* MAXI_S_H */
15187	5503,	15187	5503,
15188	/* MAXI_S_W */	15188	/* MAXI_S_W */
15189	5506,	15189	5506,
15190	/* MAXI_U_B */	15190	/* MAXI_U_B */
15191	5509,	15191	5509,
15192	/* MAXI_U_D */	15192	/* MAXI_U_D */
15193	5512,	15193	5512,
15194	/* MAXI_U_H */	15194	/* MAXI_U_H */
15195	5515,	15195	5515,
15196	/* MAXI_U_W */	15196	/* MAXI_U_W */
15197	5518,	15197	5518,
15198	/* MAX_A_B */	15198	/* MAX_A_B */
15199	5521,	15199	5521,
15200	/* MAX_A_D */	15200	/* MAX_A_D */
15201	5524,	15201	5524,
15202	/* MAX_A_H */	15202	/* MAX_A_H */
15203	5527,	15203	5527,
15204	/* MAX_A_W */	15204	/* MAX_A_W */
15205	5530,	15205	5530,
15206	/* MAX_D */	15206	/* MAX_D */
15207	5533,	15207	5533,
15208	/* MAX_D_MMR6 */	15208	/* MAX_D_MMR6 */
15209	5536,	15209	5536,
15210	/* MAX_S */	15210	/* MAX_S */
15211	5539,	15211	5539,
15212	/* MAX_S_B */	15212	/* MAX_S_B */
15213	5542,	15213	5542,
15214	/* MAX_S_D */	15214	/* MAX_S_D */
15215	5545,	15215	5545,
15216	/* MAX_S_H */	15216	/* MAX_S_H */
15217	5548,	15217	5548,
15218	/* MAX_S_MMR6 */	15218	/* MAX_S_MMR6 */
15219	5551,	15219	5551,
15220	/* MAX_S_W */	15220	/* MAX_S_W */
15221	5554,	15221	5554,
15222	/* MAX_U_B */	15222	/* MAX_U_B */
15223	5557,	15223	5557,
15224	/* MAX_U_D */	15224	/* MAX_U_D */
15225	5560,	15225	5560,
15226	/* MAX_U_H */	15226	/* MAX_U_H */
15227	5563,	15227	5563,
15228	/* MAX_U_W */	15228	/* MAX_U_W */
15229	5566,	15229	5566,
15230	/* MFC0 */	15230	/* MFC0 */
15231	5569,	15231	5569,
15232	/* MFC0_MMR6 */	15232	/* MFC0_MMR6 */
15233	5572,	15233	5572,
15234	/* MFC1 */	15234	/* MFC1 */
15235	5575,	15235	5575,
15236	/* MFC1_D64 */	15236	/* MFC1_D64 */
15237	5577,	15237	5577,
15238	/* MFC1_MM */	15238	/* MFC1_MM */
15239	5579,	15239	5579,
15240	/* MFC1_MMR6 */	15240	/* MFC1_MMR6 */
15241	5581,	15241	5581,
15242	/* MFC2 */	15242	/* MFC2 */
15243	5583,	15243	5583,
15244	/* MFC2_MMR6 */	15244	/* MFC2_MMR6 */
15245	5586,	15245	5586,
15246	/* MFGC0 */	15246	/* MFGC0 */
15247	5588,	15247	5588,
15248	/* MFGC0_MM */	15248	/* MFGC0_MM */
15249	5591,	15249	5591,
15250	/* MFHC0_MMR6 */	15250	/* MFHC0_MMR6 */
15251	5594,	15251	5594,
15252	/* MFHC1_D32 */	15252	/* MFHC1_D32 */
15253	5597,	15253	5597,
15254	/* MFHC1_D32_MM */	15254	/* MFHC1_D32_MM */
15255	5599,	15255	5599,
15256	/* MFHC1_D64 */	15256	/* MFHC1_D64 */
15257	5601,	15257	5601,
15258	/* MFHC1_D64_MM */	15258	/* MFHC1_D64_MM */
15259	5603,	15259	5603,
15260	/* MFHC2_MMR6 */	15260	/* MFHC2_MMR6 */
15261	5605,	15261	5605,
15262	/* MFHGC0 */	15262	/* MFHGC0 */
15263	5607,	15263	5607,
15264	/* MFHGC0_MM */	15264	/* MFHGC0_MM */
15265	5610,	15265	5610,
15266	/* MFHI */	15266	/* MFHI */
15267	5613,	15267	5613,
15268	/* MFHI16_MM */	15268	/* MFHI16_MM */
15269	5614,	15269	5614,
15270	/* MFHI64 */	15270	/* MFHI64 */
15271	5615,	15271	5615,
15272	/* MFHI_DSP */	15272	/* MFHI_DSP */
15273	5616,	15273	5616,
15274	/* MFHI_DSP_MM */	15274	/* MFHI_DSP_MM */
15275	5618,	15275	5618,
15276	/* MFHI_MM */	15276	/* MFHI_MM */
15277	5620,	15277	5620,
15278	/* MFLO */	15278	/* MFLO */
15279	5621,	15279	5621,
15280	/* MFLO16_MM */	15280	/* MFLO16_MM */
15281	5622,	15281	5622,
15282	/* MFLO64 */	15282	/* MFLO64 */
15283	5623,	15283	5623,
15284	/* MFLO_DSP */	15284	/* MFLO_DSP */
15285	5624,	15285	5624,
15286	/* MFLO_DSP_MM */	15286	/* MFLO_DSP_MM */
15287	5626,	15287	5626,
15288	/* MFLO_MM */	15288	/* MFLO_MM */
15289	5628,	15289	5628,
15290	/* MFTR */	15290	/* MFTR */
15291	5629,	15291	5629,
15292	/* MINA_D */	15292	/* MINA_D */
15293	5634,	15293	5634,
15294	/* MINA_D_MMR6 */	15294	/* MINA_D_MMR6 */
15295	5637,	15295	5637,
15296	/* MINA_S */	15296	/* MINA_S */
15297	5640,	15297	5640,
15298	/* MINA_S_MMR6 */	15298	/* MINA_S_MMR6 */
15299	5643,	15299	5643,
15300	/* MINI_S_B */	15300	/* MINI_S_B */
15301	5646,	15301	5646,
15302	/* MINI_S_D */	15302	/* MINI_S_D */
15303	5649,	15303	5649,
15304	/* MINI_S_H */	15304	/* MINI_S_H */
15305	5652,	15305	5652,
15306	/* MINI_S_W */	15306	/* MINI_S_W */
15307	5655,	15307	5655,
15308	/* MINI_U_B */	15308	/* MINI_U_B */
15309	5658,	15309	5658,
15310	/* MINI_U_D */	15310	/* MINI_U_D */
15311	5661,	15311	5661,
15312	/* MINI_U_H */	15312	/* MINI_U_H */
15313	5664,	15313	5664,
15314	/* MINI_U_W */	15314	/* MINI_U_W */
15315	5667,	15315	5667,
15316	/* MIN_A_B */	15316	/* MIN_A_B */
15317	5670,	15317	5670,
15318	/* MIN_A_D */	15318	/* MIN_A_D */
15319	5673,	15319	5673,
15320	/* MIN_A_H */	15320	/* MIN_A_H */
15321	5676,	15321	5676,
15322	/* MIN_A_W */	15322	/* MIN_A_W */
15323	5679,	15323	5679,
15324	/* MIN_D */	15324	/* MIN_D */
15325	5682,	15325	5682,
15326	/* MIN_D_MMR6 */	15326	/* MIN_D_MMR6 */
15327	5685,	15327	5685,
15328	/* MIN_S */	15328	/* MIN_S */
15329	5688,	15329	5688,
15330	/* MIN_S_B */	15330	/* MIN_S_B */
15331	5691,	15331	5691,
15332	/* MIN_S_D */	15332	/* MIN_S_D */
15333	5694,	15333	5694,
15334	/* MIN_S_H */	15334	/* MIN_S_H */
15335	5697,	15335	5697,
15336	/* MIN_S_MMR6 */	15336	/* MIN_S_MMR6 */
15337	5700,	15337	5700,
15338	/* MIN_S_W */	15338	/* MIN_S_W */
15339	5703,	15339	5703,
15340	/* MIN_U_B */	15340	/* MIN_U_B */
15341	5706,	15341	5706,
15342	/* MIN_U_D */	15342	/* MIN_U_D */
15343	5709,	15343	5709,
15344	/* MIN_U_H */	15344	/* MIN_U_H */
15345	5712,	15345	5712,
15346	/* MIN_U_W */	15346	/* MIN_U_W */
15347	5715,	15347	5715,
15348	/* MOD */	15348	/* MOD */
15349	5718,	15349	5718,
15350	/* MODSUB */	15350	/* MODSUB */
15351	5721,	15351	5721,
15352	/* MODSUB_MM */	15352	/* MODSUB_MM */
15353	5724,	15353	5724,
15354	/* MODU */	15354	/* MODU */
15355	5727,	15355	5727,
15356	/* MODU_MMR6 */	15356	/* MODU_MMR6 */
15357	5730,	15357	5730,
15358	/* MOD_MMR6 */	15358	/* MOD_MMR6 */
15359	5733,	15359	5733,
15360	/* MOD_S_B */	15360	/* MOD_S_B */
15361	5736,	15361	5736,
15362	/* MOD_S_D */	15362	/* MOD_S_D */
15363	5739,	15363	5739,
15364	/* MOD_S_H */	15364	/* MOD_S_H */
15365	5742,	15365	5742,
15366	/* MOD_S_W */	15366	/* MOD_S_W */
15367	5745,	15367	5745,
15368	/* MOD_U_B */	15368	/* MOD_U_B */
15369	5748,	15369	5748,
15370	/* MOD_U_D */	15370	/* MOD_U_D */
15371	5751,	15371	5751,
15372	/* MOD_U_H */	15372	/* MOD_U_H */
15373	5754,	15373	5754,
15374	/* MOD_U_W */	15374	/* MOD_U_W */
15375	5757,	15375	5757,
15376	/* MOVE16_MM */	15376	/* MOVE16_MM */
15377	5760,	15377	5760,
15378	/* MOVE16_MMR6 */	15378	/* MOVE16_MMR6 */
15379	5762,	15379	5762,
15380	/* MOVEP_MM */	15380	/* MOVEP_MM */
15381	5764,	15381	5764,
15382	/* MOVEP_MMR6 */	15382	/* MOVEP_MMR6 */
15383	5768,	15383	5768,
15384	/* MOVE_V */	15384	/* MOVE_V */
15385	5772,	15385	5772,
15386	/* MOVF_D32 */	15386	/* MOVF_D32 */
15387	5774,	15387	5774,
15388	/* MOVF_D32_MM */	15388	/* MOVF_D32_MM */
15389	5778,	15389	5778,
15390	/* MOVF_D64 */	15390	/* MOVF_D64 */
15391	5782,	15391	5782,
15392	/* MOVF_I */	15392	/* MOVF_I */
15393	5786,	15393	5786,
15394	/* MOVF_I64 */	15394	/* MOVF_I64 */
15395	5790,	15395	5790,
15396	/* MOVF_I_MM */	15396	/* MOVF_I_MM */
15397	5794,	15397	5794,
15398	/* MOVF_S */	15398	/* MOVF_S */
15399	5798,	15399	5798,
15400	/* MOVF_S_MM */	15400	/* MOVF_S_MM */
15401	5802,	15401	5802,
15402	/* MOVN_I64_D64 */	15402	/* MOVN_I64_D64 */
15403	5806,	15403	5806,
15404	/* MOVN_I64_I */	15404	/* MOVN_I64_I */
15405	5810,	15405	5810,
15406	/* MOVN_I64_I64 */	15406	/* MOVN_I64_I64 */
15407	5814,	15407	5814,
15408	/* MOVN_I64_S */	15408	/* MOVN_I64_S */
15409	5818,	15409	5818,
15410	/* MOVN_I_D32 */	15410	/* MOVN_I_D32 */
15411	5822,	15411	5822,
15412	/* MOVN_I_D32_MM */	15412	/* MOVN_I_D32_MM */
15413	5826,	15413	5826,
15414	/* MOVN_I_D64 */	15414	/* MOVN_I_D64 */
15415	5830,	15415	5830,
15416	/* MOVN_I_I */	15416	/* MOVN_I_I */
15417	5834,	15417	5834,
15418	/* MOVN_I_I64 */	15418	/* MOVN_I_I64 */
15419	5838,	15419	5838,
15420	/* MOVN_I_MM */	15420	/* MOVN_I_MM */
15421	5842,	15421	5842,
15422	/* MOVN_I_S */	15422	/* MOVN_I_S */
15423	5846,	15423	5846,
15424	/* MOVN_I_S_MM */	15424	/* MOVN_I_S_MM */
15425	5850,	15425	5850,
15426	/* MOVT_D32 */	15426	/* MOVT_D32 */
15427	5854,	15427	5854,
15428	/* MOVT_D32_MM */	15428	/* MOVT_D32_MM */
15429	5858,	15429	5858,
15430	/* MOVT_D64 */	15430	/* MOVT_D64 */
15431	5862,	15431	5862,
15432	/* MOVT_I */	15432	/* MOVT_I */
15433	5866,	15433	5866,
15434	/* MOVT_I64 */	15434	/* MOVT_I64 */
15435	5870,	15435	5870,
15436	/* MOVT_I_MM */	15436	/* MOVT_I_MM */
15437	5874,	15437	5874,
15438	/* MOVT_S */	15438	/* MOVT_S */
15439	5878,	15439	5878,
15440	/* MOVT_S_MM */	15440	/* MOVT_S_MM */
15441	5882,	15441	5882,
15442	/* MOVZ_I64_D64 */	15442	/* MOVZ_I64_D64 */
15443	5886,	15443	5886,
15444	/* MOVZ_I64_I */	15444	/* MOVZ_I64_I */
15445	5890,	15445	5890,
15446	/* MOVZ_I64_I64 */	15446	/* MOVZ_I64_I64 */
15447	5894,	15447	5894,
15448	/* MOVZ_I64_S */	15448	/* MOVZ_I64_S */
15449	5898,	15449	5898,
15450	/* MOVZ_I_D32 */	15450	/* MOVZ_I_D32 */
15451	5902,	15451	5902,
15452	/* MOVZ_I_D32_MM */	15452	/* MOVZ_I_D32_MM */
15453	5906,	15453	5906,
15454	/* MOVZ_I_D64 */	15454	/* MOVZ_I_D64 */
15455	5910,	15455	5910,
15456	/* MOVZ_I_I */	15456	/* MOVZ_I_I */
15457	5914,	15457	5914,
15458	/* MOVZ_I_I64 */	15458	/* MOVZ_I_I64 */
15459	5918,	15459	5918,
15460	/* MOVZ_I_MM */	15460	/* MOVZ_I_MM */
15461	5922,	15461	5922,
15462	/* MOVZ_I_S */	15462	/* MOVZ_I_S */
15463	5926,	15463	5926,
15464	/* MOVZ_I_S_MM */	15464	/* MOVZ_I_S_MM */
15465	5930,	15465	5930,
15466	/* MSUB */	15466	/* MSUB */
15467	5934,	15467	5934,
15468	/* MSUBF_D */	15468	/* MSUBF_D */
15469	5936,	15469	5936,
15470	/* MSUBF_D_MMR6 */	15470	/* MSUBF_D_MMR6 */
15471	5940,	15471	5940,
15472	/* MSUBF_S */	15472	/* MSUBF_S */
15473	5944,	15473	5944,
15474	/* MSUBF_S_MMR6 */	15474	/* MSUBF_S_MMR6 */
15475	5948,	15475	5948,
15476	/* MSUBR_Q_H */	15476	/* MSUBR_Q_H */
15477	5952,	15477	5952,
15478	/* MSUBR_Q_W */	15478	/* MSUBR_Q_W */
15479	5956,	15479	5956,
15480	/* MSUBU */	15480	/* MSUBU */
15481	5960,	15481	5960,
15482	/* MSUBU_DSP */	15482	/* MSUBU_DSP */
15483	5962,	15483	5962,
15484	/* MSUBU_DSP_MM */	15484	/* MSUBU_DSP_MM */
15485	5966,	15485	5966,
15486	/* MSUBU_MM */	15486	/* MSUBU_MM */
15487	5970,	15487	5970,
15488	/* MSUBV_B */	15488	/* MSUBV_B */
15489	5972,	15489	5972,
15490	/* MSUBV_D */	15490	/* MSUBV_D */
15491	5976,	15491	5976,
15492	/* MSUBV_H */	15492	/* MSUBV_H */
15493	5980,	15493	5980,
15494	/* MSUBV_W */	15494	/* MSUBV_W */
15495	5984,	15495	5984,
15496	/* MSUB_D32 */	15496	/* MSUB_D32 */
15497	5988,	15497	5988,
15498	/* MSUB_D32_MM */	15498	/* MSUB_D32_MM */
15499	5992,	15499	5992,
15500	/* MSUB_D64 */	15500	/* MSUB_D64 */
15501	5996,	15501	5996,
15502	/* MSUB_DSP */	15502	/* MSUB_DSP */
15503	6000,	15503	6000,
15504	/* MSUB_DSP_MM */	15504	/* MSUB_DSP_MM */
15505	6004,	15505	6004,
15506	/* MSUB_MM */	15506	/* MSUB_MM */
15507	6008,	15507	6008,
15508	/* MSUB_Q_H */	15508	/* MSUB_Q_H */
15509	6010,	15509	6010,
15510	/* MSUB_Q_W */	15510	/* MSUB_Q_W */
15511	6014,	15511	6014,
15512	/* MSUB_S */	15512	/* MSUB_S */
15513	6018,	15513	6018,
15514	/* MSUB_S_MM */	15514	/* MSUB_S_MM */
15515	6022,	15515	6022,
15516	/* MTC0 */	15516	/* MTC0 */
15517	6026,	15517	6026,
15518	/* MTC0_MMR6 */	15518	/* MTC0_MMR6 */
15519	6029,	15519	6029,
15520	/* MTC1 */	15520	/* MTC1 */
15521	6032,	15521	6032,
15522	/* MTC1_D64 */	15522	/* MTC1_D64 */
15523	6034,	15523	6034,
15524	/* MTC1_D64_MM */	15524	/* MTC1_D64_MM */
15525	6036,	15525	6036,
15526	/* MTC1_MM */	15526	/* MTC1_MM */
15527	6038,	15527	6038,
15528	/* MTC1_MMR6 */	15528	/* MTC1_MMR6 */
15529	6040,	15529	6040,
15530	/* MTC2 */	15530	/* MTC2 */
15531	6042,	15531	6042,
15532	/* MTC2_MMR6 */	15532	/* MTC2_MMR6 */
15533	6045,	15533	6045,
15534	/* MTGC0 */	15534	/* MTGC0 */
15535	6047,	15535	6047,
15536	/* MTGC0_MM */	15536	/* MTGC0_MM */
15537	6050,	15537	6050,
15538	/* MTHC0_MMR6 */	15538	/* MTHC0_MMR6 */
15539	6053,	15539	6053,
15540	/* MTHC1_D32 */	15540	/* MTHC1_D32 */
15541	6056,	15541	6056,
15542	/* MTHC1_D32_MM */	15542	/* MTHC1_D32_MM */
15543	6059,	15543	6059,
15544	/* MTHC1_D64 */	15544	/* MTHC1_D64 */
15545	6062,	15545	6062,
15546	/* MTHC1_D64_MM */	15546	/* MTHC1_D64_MM */
15547	6065,	15547	6065,
15548	/* MTHC2_MMR6 */	15548	/* MTHC2_MMR6 */
15549	6068,	15549	6068,
15550	/* MTHGC0 */	15550	/* MTHGC0 */
15551	6070,	15551	6070,
15552	/* MTHGC0_MM */	15552	/* MTHGC0_MM */
15553	6073,	15553	6073,
15554	/* MTHI */	15554	/* MTHI */
15555	6076,	15555	6076,
15556	/* MTHI64 */	15556	/* MTHI64 */
15557	6077,	15557	6077,
15558	/* MTHI_DSP */	15558	/* MTHI_DSP */
15559	6078,	15559	6078,
15560	/* MTHI_DSP_MM */	15560	/* MTHI_DSP_MM */
15561	6080,	15561	6080,
15562	/* MTHI_MM */	15562	/* MTHI_MM */
15563	6082,	15563	6082,
15564	/* MTHLIP */	15564	/* MTHLIP */
15565	6083,	15565	6083,
15566	/* MTHLIP_MM */	15566	/* MTHLIP_MM */
15567	6086,	15567	6086,
15568	/* MTLO */	15568	/* MTLO */
15569	6089,	15569	6089,
15570	/* MTLO64 */	15570	/* MTLO64 */
15571	6090,	15571	6090,
15572	/* MTLO_DSP */	15572	/* MTLO_DSP */
15573	6091,	15573	6091,
15574	/* MTLO_DSP_MM */	15574	/* MTLO_DSP_MM */
15575	6093,	15575	6093,
15576	/* MTLO_MM */	15576	/* MTLO_MM */
15577	6095,	15577	6095,
15578	/* MTM0 */	15578	/* MTM0 */
15579	6096,	15579	6096,
15580	/* MTM1 */	15580	/* MTM1 */
15581	6097,	15581	6097,
15582	/* MTM2 */	15582	/* MTM2 */
15583	6098,	15583	6098,
15584	/* MTP0 */	15584	/* MTP0 */
15585	6099,	15585	6099,
15586	/* MTP1 */	15586	/* MTP1 */
15587	6100,	15587	6100,
15588	/* MTP2 */	15588	/* MTP2 */
15589	6101,	15589	6101,
15590	/* MTTR */	15590	/* MTTR */
15591	6102,	15591	6102,
15592	/* MUH */	15592	/* MUH */
15593	6107,	15593	6107,
15594	/* MUHU */	15594	/* MUHU */
15595	6110,	15595	6110,
15596	/* MUHU_MMR6 */	15596	/* MUHU_MMR6 */
15597	6113,	15597	6113,
15598	/* MUH_MMR6 */	15598	/* MUH_MMR6 */
15599	6116,	15599	6116,
15600	/* MUL */	15600	/* MUL */
15601	6119,	15601	6119,
15602	/* MULEQ_S_W_PHL */	15602	/* MULEQ_S_W_PHL */
15603	6122,	15603	6122,
15604	/* MULEQ_S_W_PHL_MM */	15604	/* MULEQ_S_W_PHL_MM */
15605	6125,	15605	6125,
15606	/* MULEQ_S_W_PHR */	15606	/* MULEQ_S_W_PHR */
15607	6128,	15607	6128,
15608	/* MULEQ_S_W_PHR_MM */	15608	/* MULEQ_S_W_PHR_MM */
15609	6131,	15609	6131,
15610	/* MULEU_S_PH_QBL */	15610	/* MULEU_S_PH_QBL */
15611	6134,	15611	6134,
15612	/* MULEU_S_PH_QBL_MM */	15612	/* MULEU_S_PH_QBL_MM */
15613	6137,	15613	6137,
15614	/* MULEU_S_PH_QBR */	15614	/* MULEU_S_PH_QBR */
15615	6140,	15615	6140,
15616	/* MULEU_S_PH_QBR_MM */	15616	/* MULEU_S_PH_QBR_MM */
15617	6143,	15617	6143,
15618	/* MULQ_RS_PH */	15618	/* MULQ_RS_PH */
15619	6146,	15619	6146,
15620	/* MULQ_RS_PH_MM */	15620	/* MULQ_RS_PH_MM */
15621	6149,	15621	6149,
15622	/* MULQ_RS_W */	15622	/* MULQ_RS_W */
15623	6152,	15623	6152,
15624	/* MULQ_RS_W_MMR2 */	15624	/* MULQ_RS_W_MMR2 */
15625	6155,	15625	6155,
15626	/* MULQ_S_PH */	15626	/* MULQ_S_PH */
15627	6158,	15627	6158,
15628	/* MULQ_S_PH_MMR2 */	15628	/* MULQ_S_PH_MMR2 */
15629	6161,	15629	6161,
15630	/* MULQ_S_W */	15630	/* MULQ_S_W */
15631	6164,	15631	6164,
15632	/* MULQ_S_W_MMR2 */	15632	/* MULQ_S_W_MMR2 */
15633	6167,	15633	6167,
15634	/* MULR_PS64 */	15634	/* MULR_PS64 */
15635	6170,	15635	6170,
15636	/* MULR_Q_H */	15636	/* MULR_Q_H */
15637	6173,	15637	6173,
15638	/* MULR_Q_W */	15638	/* MULR_Q_W */
15639	6176,	15639	6176,
15640	/* MULSAQ_S_W_PH */	15640	/* MULSAQ_S_W_PH */
15641	6179,	15641	6179,
15642	/* MULSAQ_S_W_PH_MM */	15642	/* MULSAQ_S_W_PH_MM */
15643	6183,	15643	6183,
15644	/* MULSA_W_PH */	15644	/* MULSA_W_PH */
15645	6187,	15645	6187,
15646	/* MULSA_W_PH_MMR2 */	15646	/* MULSA_W_PH_MMR2 */
15647	6191,	15647	6191,
15648	/* MULT */	15648	/* MULT */
15649	6195,	15649	6195,
15650	/* MULTU_DSP */	15650	/* MULTU_DSP */
15651	6197,	15651	6197,
15652	/* MULTU_DSP_MM */	15652	/* MULTU_DSP_MM */
15653	6200,	15653	6200,
15654	/* MULT_DSP */	15654	/* MULT_DSP */
15655	6203,	15655	6203,
15656	/* MULT_DSP_MM */	15656	/* MULT_DSP_MM */
15657	6206,	15657	6206,
15658	/* MULT_MM */	15658	/* MULT_MM */
15659	6209,	15659	6209,
15660	/* MULTu */	15660	/* MULTu */
15661	6211,	15661	6211,
15662	/* MULTu_MM */	15662	/* MULTu_MM */
15663	6213,	15663	6213,
15664	/* MULU */	15664	/* MULU */
15665	6215,	15665	6215,
15666	/* MULU_MMR6 */	15666	/* MULU_MMR6 */
15667	6218,	15667	6218,
15668	/* MULV_B */	15668	/* MULV_B */
15669	6221,	15669	6221,
15670	/* MULV_D */	15670	/* MULV_D */
15671	6224,	15671	6224,
15672	/* MULV_H */	15672	/* MULV_H */
15673	6227,	15673	6227,
15674	/* MULV_W */	15674	/* MULV_W */
15675	6230,	15675	6230,
15676	/* MUL_MM */	15676	/* MUL_MM */
15677	6233,	15677	6233,
15678	/* MUL_MMR6 */	15678	/* MUL_MMR6 */
15679	6236,	15679	6236,
15680	/* MUL_PH */	15680	/* MUL_PH */
15681	6239,	15681	6239,
15682	/* MUL_PH_MMR2 */	15682	/* MUL_PH_MMR2 */
15683	6242,	15683	6242,
15684	/* MUL_Q_H */	15684	/* MUL_Q_H */
15685	6245,	15685	6245,
15686	/* MUL_Q_W */	15686	/* MUL_Q_W */
15687	6248,	15687	6248,
15688	/* MUL_R6 */	15688	/* MUL_R6 */
15689	6251,	15689	6251,
15690	/* MUL_S_PH */	15690	/* MUL_S_PH */
15691	6254,	15691	6254,
15692	/* MUL_S_PH_MMR2 */	15692	/* MUL_S_PH_MMR2 */
15693	6257,	15693	6257,
15694	/* Mfhi16 */	15694	/* Mfhi16 */
15695	6260,	15695	6260,
15696	/* Mflo16 */	15696	/* Mflo16 */
15697	6261,	15697	6261,
15698	/* Move32R16 */	15698	/* Move32R16 */
15699	6262,	15699	6262,
15700	/* MoveR3216 */	15700	/* MoveR3216 */
15701	6264,	15701	6264,
15702	/* NLOC_B */	15702	/* NLOC_B */
15703	6266,	15703	6266,
15704	/* NLOC_D */	15704	/* NLOC_D */
15705	6268,	15705	6268,
15706	/* NLOC_H */	15706	/* NLOC_H */
15707	6270,	15707	6270,
15708	/* NLOC_W */	15708	/* NLOC_W */
15709	6272,	15709	6272,
15710	/* NLZC_B */	15710	/* NLZC_B */
15711	6274,	15711	6274,
15712	/* NLZC_D */	15712	/* NLZC_D */
15713	6276,	15713	6276,
15714	/* NLZC_H */	15714	/* NLZC_H */
15715	6278,	15715	6278,
15716	/* NLZC_W */	15716	/* NLZC_W */
15717	6280,	15717	6280,
15718	/* NMADD_D32 */	15718	/* NMADD_D32 */
15719	6282,	15719	6282,
15720	/* NMADD_D32_MM */	15720	/* NMADD_D32_MM */
15721	6286,	15721	6286,
15722	/* NMADD_D64 */	15722	/* NMADD_D64 */
15723	6290,	15723	6290,
15724	/* NMADD_S */	15724	/* NMADD_S */
15725	6294,	15725	6294,
15726	/* NMADD_S_MM */	15726	/* NMADD_S_MM */
15727	6298,	15727	6298,
15728	/* NMSUB_D32 */	15728	/* NMSUB_D32 */
15729	6302,	15729	6302,
15730	/* NMSUB_D32_MM */	15730	/* NMSUB_D32_MM */
15731	6306,	15731	6306,
15732	/* NMSUB_D64 */	15732	/* NMSUB_D64 */
15733	6310,	15733	6310,
15734	/* NMSUB_S */	15734	/* NMSUB_S */
15735	6314,	15735	6314,
15736	/* NMSUB_S_MM */	15736	/* NMSUB_S_MM */
15737	6318,	15737	6318,
15738	/* NOR */	15738	/* NOR */
15739	6322,	15739	6322,
15740	/* NOR64 */	15740	/* NOR64 */
15741	6325,	15741	6325,
15742	/* NORI_B */	15742	/* NORI_B */
15743	6328,	15743	6328,
15744	/* NOR_MM */	15744	/* NOR_MM */
15745	6331,	15745	6331,
15746	/* NOR_MMR6 */	15746	/* NOR_MMR6 */
15747	6334,	15747	6334,
15748	/* NOR_V */	15748	/* NOR_V */
15749	6337,	15749	6337,
15750	/* NOT16_MM */	15750	/* NOT16_MM */
15751	6340,	15751	6340,
15752	/* NOT16_MMR6 */	15752	/* NOT16_MMR6 */
15753	6342,	15753	6342,
15754	/* NegRxRy16 */	15754	/* NegRxRy16 */
15755	6344,	15755	6344,
15756	/* NotRxRy16 */	15756	/* NotRxRy16 */
15757	6346,	15757	6346,
15758	/* OR */	15758	/* OR */
15759	6348,	15759	6348,
15760	/* OR16_MM */	15760	/* OR16_MM */
15761	6351,	15761	6351,
15762	/* OR16_MMR6 */	15762	/* OR16_MMR6 */
15763	6354,	15763	6354,
15764	/* OR64 */	15764	/* OR64 */
15765	6357,	15765	6357,
15766	/* ORI_B */	15766	/* ORI_B */
15767	6360,	15767	6360,
15768	/* ORI_MMR6 */	15768	/* ORI_MMR6 */
15769	6363,	15769	6363,
15770	/* OR_MM */	15770	/* OR_MM */
15771	6366,	15771	6366,
15772	/* OR_MMR6 */	15772	/* OR_MMR6 */
15773	6369,	15773	6369,
15774	/* OR_V */	15774	/* OR_V */
15775	6372,	15775	6372,
15776	/* ORi */	15776	/* ORi */
15777	6375,	15777	6375,
15778	/* ORi64 */	15778	/* ORi64 */
15779	6378,	15779	6378,
15780	/* ORi_MM */	15780	/* ORi_MM */
15781	6381,	15781	6381,
15782	/* OrRxRxRy16 */	15782	/* OrRxRxRy16 */
15783	6384,	15783	6384,
15784	/* PACKRL_PH */	15784	/* PACKRL_PH */
15785	6387,	15785	6387,
15786	/* PACKRL_PH_MM */	15786	/* PACKRL_PH_MM */
15787	6390,	15787	6390,
15788	/* PAUSE */	15788	/* PAUSE */
15789	6393,	15789	6393,
15790	/* PAUSE_MM */	15790	/* PAUSE_MM */
15791	6393,	15791	6393,
15792	/* PAUSE_MMR6 */	15792	/* PAUSE_MMR6 */
15793	6393,	15793	6393,
15794	/* PCKEV_B */	15794	/* PCKEV_B */
15795	6393,	15795	6393,
15796	/* PCKEV_D */	15796	/* PCKEV_D */
15797	6396,	15797	6396,
15798	/* PCKEV_H */	15798	/* PCKEV_H */
15799	6399,	15799	6399,
15800	/* PCKEV_W */	15800	/* PCKEV_W */
15801	6402,	15801	6402,
15802	/* PCKOD_B */	15802	/* PCKOD_B */
15803	6405,	15803	6405,
15804	/* PCKOD_D */	15804	/* PCKOD_D */
15805	6408,	15805	6408,
15806	/* PCKOD_H */	15806	/* PCKOD_H */
15807	6411,	15807	6411,
15808	/* PCKOD_W */	15808	/* PCKOD_W */
15809	6414,	15809	6414,
15810	/* PCNT_B */	15810	/* PCNT_B */
15811	6417,	15811	6417,
15812	/* PCNT_D */	15812	/* PCNT_D */
15813	6419,	15813	6419,
15814	/* PCNT_H */	15814	/* PCNT_H */
15815	6421,	15815	6421,
15816	/* PCNT_W */	15816	/* PCNT_W */
15817	6423,	15817	6423,
15818	/* PICK_PH */	15818	/* PICK_PH */
15819	6425,	15819	6425,
15820	/* PICK_PH_MM */	15820	/* PICK_PH_MM */
15821	6428,	15821	6428,
15822	/* PICK_QB */	15822	/* PICK_QB */
15823	6431,	15823	6431,
15824	/* PICK_QB_MM */	15824	/* PICK_QB_MM */
15825	6434,	15825	6434,
15826	/* PLL_PS64 */	15826	/* PLL_PS64 */
15827	6437,	15827	6437,
15828	/* PLU_PS64 */	15828	/* PLU_PS64 */
15829	6440,	15829	6440,
15830	/* POP */	15830	/* POP */
15831	6443,	15831	6443,
15832	/* PRECEQU_PH_QBL */	15832	/* PRECEQU_PH_QBL */
15833	6445,	15833	6445,
15834	/* PRECEQU_PH_QBLA */	15834	/* PRECEQU_PH_QBLA */
15835	6447,	15835	6447,
15836	/* PRECEQU_PH_QBLA_MM */	15836	/* PRECEQU_PH_QBLA_MM */
15837	6449,	15837	6449,
15838	/* PRECEQU_PH_QBL_MM */	15838	/* PRECEQU_PH_QBL_MM */
15839	6451,	15839	6451,
15840	/* PRECEQU_PH_QBR */	15840	/* PRECEQU_PH_QBR */
15841	6453,	15841	6453,
15842	/* PRECEQU_PH_QBRA */	15842	/* PRECEQU_PH_QBRA */
15843	6455,	15843	6455,
15844	/* PRECEQU_PH_QBRA_MM */	15844	/* PRECEQU_PH_QBRA_MM */
15845	6457,	15845	6457,
15846	/* PRECEQU_PH_QBR_MM */	15846	/* PRECEQU_PH_QBR_MM */
15847	6459,	15847	6459,
15848	/* PRECEQ_W_PHL */	15848	/* PRECEQ_W_PHL */
15849	6461,	15849	6461,
15850	/* PRECEQ_W_PHL_MM */	15850	/* PRECEQ_W_PHL_MM */
15851	6463,	15851	6463,
15852	/* PRECEQ_W_PHR */	15852	/* PRECEQ_W_PHR */
15853	6465,	15853	6465,
15854	/* PRECEQ_W_PHR_MM */	15854	/* PRECEQ_W_PHR_MM */
15855	6467,	15855	6467,
15856	/* PRECEU_PH_QBL */	15856	/* PRECEU_PH_QBL */
15857	6469,	15857	6469,
15858	/* PRECEU_PH_QBLA */	15858	/* PRECEU_PH_QBLA */
15859	6471,	15859	6471,
15860	/* PRECEU_PH_QBLA_MM */	15860	/* PRECEU_PH_QBLA_MM */
15861	6473,	15861	6473,
15862	/* PRECEU_PH_QBL_MM */	15862	/* PRECEU_PH_QBL_MM */
15863	6475,	15863	6475,
15864	/* PRECEU_PH_QBR */	15864	/* PRECEU_PH_QBR */
15865	6477,	15865	6477,
15866	/* PRECEU_PH_QBRA */	15866	/* PRECEU_PH_QBRA */
15867	6479,	15867	6479,
15868	/* PRECEU_PH_QBRA_MM */	15868	/* PRECEU_PH_QBRA_MM */
15869	6481,	15869	6481,
15870	/* PRECEU_PH_QBR_MM */	15870	/* PRECEU_PH_QBR_MM */
15871	6483,	15871	6483,
15872	/* PRECRQU_S_QB_PH */	15872	/* PRECRQU_S_QB_PH */
15873	6485,	15873	6485,
15874	/* PRECRQU_S_QB_PH_MM */	15874	/* PRECRQU_S_QB_PH_MM */
15875	6488,	15875	6488,
15876	/* PRECRQ_PH_W */	15876	/* PRECRQ_PH_W */
15877	6491,	15877	6491,
15878	/* PRECRQ_PH_W_MM */	15878	/* PRECRQ_PH_W_MM */
15879	6494,	15879	6494,
15880	/* PRECRQ_QB_PH */	15880	/* PRECRQ_QB_PH */
15881	6497,	15881	6497,
15882	/* PRECRQ_QB_PH_MM */	15882	/* PRECRQ_QB_PH_MM */
15883	6500,	15883	6500,
15884	/* PRECRQ_RS_PH_W */	15884	/* PRECRQ_RS_PH_W */
15885	6503,	15885	6503,
15886	/* PRECRQ_RS_PH_W_MM */	15886	/* PRECRQ_RS_PH_W_MM */
15887	6506,	15887	6506,
15888	/* PRECR_QB_PH */	15888	/* PRECR_QB_PH */
15889	6509,	15889	6509,
15890	/* PRECR_QB_PH_MMR2 */	15890	/* PRECR_QB_PH_MMR2 */
15891	6512,	15891	6512,
15892	/* PRECR_SRA_PH_W */	15892	/* PRECR_SRA_PH_W */
15893	6515,	15893	6515,
15894	/* PRECR_SRA_PH_W_MMR2 */	15894	/* PRECR_SRA_PH_W_MMR2 */
15895	6519,	15895	6519,
15896	/* PRECR_SRA_R_PH_W */	15896	/* PRECR_SRA_R_PH_W */
15897	6523,	15897	6523,
15898	/* PRECR_SRA_R_PH_W_MMR2 */	15898	/* PRECR_SRA_R_PH_W_MMR2 */
15899	6527,	15899	6527,
15900	/* PREF */	15900	/* PREF */
15901	6531,	15901	6531,
15902	/* PREFE */	15902	/* PREFE */
15903	6534,	15903	6534,
15904	/* PREFE_MM */	15904	/* PREFE_MM */
15905	6537,	15905	6537,
15906	/* PREFX_MM */	15906	/* PREFX_MM */
15907	6540,	15907	6540,
15908	/* PREF_MM */	15908	/* PREF_MM */
15909	6543,	15909	6543,
15910	/* PREF_MMR6 */	15910	/* PREF_MMR6 */
15911	6546,	15911	6546,
15912	/* PREF_R6 */	15912	/* PREF_R6 */
15913	6549,	15913	6549,
15914	/* PREPEND */	15914	/* PREPEND */
15915	6552,	15915	6552,
15916	/* PREPEND_MMR2 */	15916	/* PREPEND_MMR2 */
15917	6556,	15917	6556,
15918	/* PUL_PS64 */	15918	/* PUL_PS64 */
15919	6560,	15919	6560,
15920	/* PUU_PS64 */	15920	/* PUU_PS64 */
15921	6563,	15921	6563,
15922	/* RADDU_W_QB */	15922	/* RADDU_W_QB */
15923	6566,	15923	6566,
15924	/* RADDU_W_QB_MM */	15924	/* RADDU_W_QB_MM */
15925	6568,	15925	6568,
15926	/* RDDSP */	15926	/* RDDSP */
15927	6570,	15927	6570,
15928	/* RDDSP_MM */	15928	/* RDDSP_MM */
15929	6572,	15929	6572,
15930	/* RDHWR */	15930	/* RDHWR */
15931	6574,	15931	6574,
15932	/* RDHWR64 */	15932	/* RDHWR64 */
15933	6577,	15933	6577,
15934	/* RDHWR_MM */	15934	/* RDHWR_MM */
15935	6580,	15935	6580,
15936	/* RDHWR_MMR6 */	15936	/* RDHWR_MMR6 */
15937	6583,	15937	6583,
15938	/* RDPGPR_MMR6 */	15938	/* RDPGPR_MMR6 */
15939	6586,	15939	6586,
15940	/* RECIP_D32 */	15940	/* RECIP_D32 */
15941	6588,	15941	6588,
15942	/* RECIP_D32_MM */	15942	/* RECIP_D32_MM */
15943	6590,	15943	6590,
15944	/* RECIP_D64 */	15944	/* RECIP_D64 */
15945	6592,	15945	6592,
15946	/* RECIP_D64_MM */	15946	/* RECIP_D64_MM */
15947	6594,	15947	6594,
15948	/* RECIP_S */	15948	/* RECIP_S */
15949	6596,	15949	6596,
15950	/* RECIP_S_MM */	15950	/* RECIP_S_MM */
15951	6598,	15951	6598,
15952	/* REPLV_PH */	15952	/* REPLV_PH */
15953	6600,	15953	6600,
15954	/* REPLV_PH_MM */	15954	/* REPLV_PH_MM */
15955	6602,	15955	6602,
15956	/* REPLV_QB */	15956	/* REPLV_QB */
15957	6604,	15957	6604,
15958	/* REPLV_QB_MM */	15958	/* REPLV_QB_MM */
15959	6606,	15959	6606,
15960	/* REPL_PH */	15960	/* REPL_PH */
15961	6608,	15961	6608,
15962	/* REPL_PH_MM */	15962	/* REPL_PH_MM */
15963	6610,	15963	6610,
15964	/* REPL_QB */	15964	/* REPL_QB */
15965	6612,	15965	6612,
15966	/* REPL_QB_MM */	15966	/* REPL_QB_MM */
15967	6614,	15967	6614,
15968	/* RINT_D */	15968	/* RINT_D */
15969	6616,	15969	6616,
15970	/* RINT_D_MMR6 */	15970	/* RINT_D_MMR6 */
15971	6618,	15971	6618,
15972	/* RINT_S */	15972	/* RINT_S */
15973	6620,	15973	6620,
15974	/* RINT_S_MMR6 */	15974	/* RINT_S_MMR6 */
15975	6622,	15975	6622,
15976	/* ROTR */	15976	/* ROTR */
15977	6624,	15977	6624,
15978	/* ROTRV */	15978	/* ROTRV */
15979	6627,	15979	6627,
15980	/* ROTRV_MM */	15980	/* ROTRV_MM */
15981	6630,	15981	6630,
15982	/* ROTR_MM */	15982	/* ROTR_MM */
15983	6633,	15983	6633,
15984	/* ROUND_L_D64 */	15984	/* ROUND_L_D64 */
15985	6636,	15985	6636,
15986	/* ROUND_L_D_MMR6 */	15986	/* ROUND_L_D_MMR6 */
15987	6638,	15987	6638,
15988	/* ROUND_L_S */	15988	/* ROUND_L_S */
15989	6640,	15989	6640,
15990	/* ROUND_L_S_MMR6 */	15990	/* ROUND_L_S_MMR6 */
15991	6642,	15991	6642,
15992	/* ROUND_W_D32 */	15992	/* ROUND_W_D32 */
15993	6644,	15993	6644,
15994	/* ROUND_W_D64 */	15994	/* ROUND_W_D64 */
15995	6646,	15995	6646,
15996	/* ROUND_W_D_MMR6 */	15996	/* ROUND_W_D_MMR6 */
15997	6648,	15997	6648,
15998	/* ROUND_W_MM */	15998	/* ROUND_W_MM */
15999	6650,	15999	6650,
16000	/* ROUND_W_S */	16000	/* ROUND_W_S */
16001	6652,	16001	6652,
16002	/* ROUND_W_S_MM */	16002	/* ROUND_W_S_MM */
16003	6654,	16003	6654,
16004	/* ROUND_W_S_MMR6 */	16004	/* ROUND_W_S_MMR6 */
16005	6656,	16005	6656,
16006	/* RSQRT_D32 */	16006	/* RSQRT_D32 */
16007	6658,	16007	6658,
16008	/* RSQRT_D32_MM */	16008	/* RSQRT_D32_MM */
16009	6660,	16009	6660,
16010	/* RSQRT_D64 */	16010	/* RSQRT_D64 */
16011	6662,	16011	6662,
16012	/* RSQRT_D64_MM */	16012	/* RSQRT_D64_MM */
16013	6664,	16013	6664,
16014	/* RSQRT_S */	16014	/* RSQRT_S */
16015	6666,	16015	6666,
16016	/* RSQRT_S_MM */	16016	/* RSQRT_S_MM */
16017	6668,	16017	6668,
16018	/* Restore16 */	16018	/* Restore16 */
16019	6670,	16019	6670,
16020	/* RestoreX16 */	16020	/* RestoreX16 */
16021	6670,	16021	6670,
16022	/* SAA */	16022	/* SAA */
16023	6670,	16023	6670,
16024	/* SAAD */	16024	/* SAAD */
16025	6672,	16025	6672,
16026	/* SAT_S_B */	16026	/* SAT_S_B */
16027	6674,	16027	6674,
16028	/* SAT_S_D */	16028	/* SAT_S_D */
16029	6677,	16029	6677,
16030	/* SAT_S_H */	16030	/* SAT_S_H */
16031	6680,	16031	6680,
16032	/* SAT_S_W */	16032	/* SAT_S_W */
16033	6683,	16033	6683,
16034	/* SAT_U_B */	16034	/* SAT_U_B */
16035	6686,	16035	6686,
16036	/* SAT_U_D */	16036	/* SAT_U_D */
16037	6689,	16037	6689,
16038	/* SAT_U_H */	16038	/* SAT_U_H */
16039	6692,	16039	6692,
16040	/* SAT_U_W */	16040	/* SAT_U_W */
16041	6695,	16041	6695,
16042	/* SB */	16042	/* SB */
16043	6698,	16043	6698,
16044	/* SB16_MM */	16044	/* SB16_MM */
16045	6701,	16045	6701,
16046	/* SB16_MMR6 */	16046	/* SB16_MMR6 */
16047	6704,	16047	6704,
16048	/* SB64 */	16048	/* SB64 */
16049	6707,	16049	6707,
16050	/* SBE */	16050	/* SBE */
16051	6710,	16051	6710,
16052	/* SBE_MM */	16052	/* SBE_MM */
16053	6713,	16053	6713,
16054	/* SB_MM */	16054	/* SB_MM */
16055	6716,	16055	6716,
16056	/* SB_MMR6 */	16056	/* SB_MMR6 */
16057	6719,	16057	6719,
16058	/* SC */	16058	/* SC */
16059	6722,	16059	6722,
16060	/* SC64 */	16060	/* SC64 */
16061	6726,	16061	6726,
16062	/* SC64_R6 */	16062	/* SC64_R6 */
16063	6730,	16063	6730,
16064	/* SCD */	16064	/* SCD */
16065	6734,	16065	6734,
16066	/* SCD_R6 */	16066	/* SCD_R6 */
16067	6738,	16067	6738,
16068	/* SCE */	16068	/* SCE */
16069	6742,	16069	6742,
16070	/* SCE_MM */	16070	/* SCE_MM */
16071	6746,	16071	6746,
16072	/* SC_MM */	16072	/* SC_MM */
16073	6750,	16073	6750,
16074	/* SC_MMR6 */	16074	/* SC_MMR6 */
16075	6754,	16075	6754,
16076	/* SC_R6 */	16076	/* SC_R6 */
16077	6758,	16077	6758,
16078	/* SD */	16078	/* SD */
16079	6762,	16079	6762,
16080	/* SDBBP */	16080	/* SDBBP */
16081	6765,	16081	6765,
16082	/* SDBBP16_MM */	16082	/* SDBBP16_MM */
16083	6766,	16083	6766,
16084	/* SDBBP16_MMR6 */	16084	/* SDBBP16_MMR6 */
16085	6767,	16085	6767,
16086	/* SDBBP_MM */	16086	/* SDBBP_MM */
16087	6768,	16087	6768,
16088	/* SDBBP_MMR6 */	16088	/* SDBBP_MMR6 */
16089	6769,	16089	6769,
16090	/* SDBBP_R6 */	16090	/* SDBBP_R6 */
16091	6770,	16091	6770,
16092	/* SDC1 */	16092	/* SDC1 */
16093	6771,	16093	6771,
16094	/* SDC164 */	16094	/* SDC164 */
16095	6774,	16095	6774,
16096	/* SDC1_D64_MMR6 */	16096	/* SDC1_D64_MMR6 */
16097	6777,	16097	6777,
16098	/* SDC1_MM_D32 */	16098	/* SDC1_MM_D32 */
16099	6780,	16099	6780,
16100	/* SDC1_MM_D64 */	16100	/* SDC1_MM_D64 */
16101	6783,	16101	6783,
16102	/* SDC2 */	16102	/* SDC2 */
16103	6786,	16103	6786,
16104	/* SDC2_MMR6 */	16104	/* SDC2_MMR6 */
16105	6789,	16105	6789,
16106	/* SDC2_R6 */	16106	/* SDC2_R6 */
16107	6792,	16107	6792,
16108	/* SDC3 */	16108	/* SDC3 */
16109	6795,	16109	6795,
16110	/* SDIV */	16110	/* SDIV */
16111	6798,	16111	6798,
16112	/* SDIV_MM */	16112	/* SDIV_MM */
16113	6800,	16113	6800,
16114	/* SDL */	16114	/* SDL */
16115	6802,	16115	6802,
16116	/* SDR */	16116	/* SDR */
16117	6805,	16117	6805,
16118	/* SDXC1 */	16118	/* SDXC1 */
16119	6808,	16119	6808,
16120	/* SDXC164 */	16120	/* SDXC164 */
16121	6811,	16121	6811,
16122	/* SEB */	16122	/* SEB */
16123	6814,	16123	6814,
16124	/* SEB64 */	16124	/* SEB64 */
16125	6816,	16125	6816,
16126	/* SEB_MM */	16126	/* SEB_MM */
16127	6818,	16127	6818,
16128	/* SEH */	16128	/* SEH */
16129	6820,	16129	6820,
16130	/* SEH64 */	16130	/* SEH64 */
16131	6822,	16131	6822,
16132	/* SEH_MM */	16132	/* SEH_MM */
16133	6824,	16133	6824,
16134	/* SELEQZ */	16134	/* SELEQZ */
16135	6826,	16135	6826,
16136	/* SELEQZ64 */	16136	/* SELEQZ64 */
16137	6829,	16137	6829,
16138	/* SELEQZ_D */	16138	/* SELEQZ_D */
16139	6832,	16139	6832,
16140	/* SELEQZ_D_MMR6 */	16140	/* SELEQZ_D_MMR6 */
16141	6835,	16141	6835,
16142	/* SELEQZ_MMR6 */	16142	/* SELEQZ_MMR6 */
16143	6838,	16143	6838,
16144	/* SELEQZ_S */	16144	/* SELEQZ_S */
16145	6841,	16145	6841,
16146	/* SELEQZ_S_MMR6 */	16146	/* SELEQZ_S_MMR6 */
16147	6844,	16147	6844,
16148	/* SELNEZ */	16148	/* SELNEZ */
16149	6847,	16149	6847,
16150	/* SELNEZ64 */	16150	/* SELNEZ64 */
16151	6850,	16151	6850,
16152	/* SELNEZ_D */	16152	/* SELNEZ_D */
16153	6853,	16153	6853,
16154	/* SELNEZ_D_MMR6 */	16154	/* SELNEZ_D_MMR6 */
16155	6856,	16155	6856,
16156	/* SELNEZ_MMR6 */	16156	/* SELNEZ_MMR6 */
16157	6859,	16157	6859,
16158	/* SELNEZ_S */	16158	/* SELNEZ_S */
16159	6862,	16159	6862,
16160	/* SELNEZ_S_MMR6 */	16160	/* SELNEZ_S_MMR6 */
16161	6865,	16161	6865,
16162	/* SEL_D */	16162	/* SEL_D */
16163	6868,	16163	6868,
16164	/* SEL_D_MMR6 */	16164	/* SEL_D_MMR6 */
16165	6872,	16165	6872,
16166	/* SEL_S */	16166	/* SEL_S */
16167	6876,	16167	6876,
16168	/* SEL_S_MMR6 */	16168	/* SEL_S_MMR6 */
16169	6880,	16169	6880,
16170	/* SEQ */	16170	/* SEQ */
16171	6884,	16171	6884,
16172	/* SEQi */	16172	/* SEQi */
16173	6887,	16173	6887,
16174	/* SH */	16174	/* SH */
16175	6890,	16175	6890,
16176	/* SH16_MM */	16176	/* SH16_MM */
16177	6893,	16177	6893,
16178	/* SH16_MMR6 */	16178	/* SH16_MMR6 */
16179	6896,	16179	6896,
16180	/* SH64 */	16180	/* SH64 */
16181	6899,	16181	6899,
16182	/* SHE */	16182	/* SHE */
16183	6902,	16183	6902,
16184	/* SHE_MM */	16184	/* SHE_MM */
16185	6905,	16185	6905,
16186	/* SHF_B */	16186	/* SHF_B */
16187	6908,	16187	6908,
16188	/* SHF_H */	16188	/* SHF_H */
16189	6911,	16189	6911,
16190	/* SHF_W */	16190	/* SHF_W */
16191	6914,	16191	6914,
16192	/* SHILO */	16192	/* SHILO */
16193	6917,	16193	6917,
16194	/* SHILOV */	16194	/* SHILOV */
16195	6920,	16195	6920,
16196	/* SHILOV_MM */	16196	/* SHILOV_MM */
16197	6923,	16197	6923,
16198	/* SHILO_MM */	16198	/* SHILO_MM */
16199	6926,	16199	6926,
16200	/* SHLLV_PH */	16200	/* SHLLV_PH */
16201	6929,	16201	6929,
16202	/* SHLLV_PH_MM */	16202	/* SHLLV_PH_MM */
16203	6932,	16203	6932,
16204	/* SHLLV_QB */	16204	/* SHLLV_QB */
16205	6935,	16205	6935,
16206	/* SHLLV_QB_MM */	16206	/* SHLLV_QB_MM */
16207	6938,	16207	6938,
16208	/* SHLLV_S_PH */	16208	/* SHLLV_S_PH */
16209	6941,	16209	6941,
16210	/* SHLLV_S_PH_MM */	16210	/* SHLLV_S_PH_MM */
16211	6944,	16211	6944,
16212	/* SHLLV_S_W */	16212	/* SHLLV_S_W */
16213	6947,	16213	6947,
16214	/* SHLLV_S_W_MM */	16214	/* SHLLV_S_W_MM */
16215	6950,	16215	6950,
16216	/* SHLL_PH */	16216	/* SHLL_PH */
16217	6953,	16217	6953,
16218	/* SHLL_PH_MM */	16218	/* SHLL_PH_MM */
16219	6956,	16219	6956,
16220	/* SHLL_QB */	16220	/* SHLL_QB */
16221	6959,	16221	6959,
16222	/* SHLL_QB_MM */	16222	/* SHLL_QB_MM */
16223	6962,	16223	6962,
16224	/* SHLL_S_PH */	16224	/* SHLL_S_PH */
16225	6965,	16225	6965,
16226	/* SHLL_S_PH_MM */	16226	/* SHLL_S_PH_MM */
16227	6968,	16227	6968,
16228	/* SHLL_S_W */	16228	/* SHLL_S_W */
16229	6971,	16229	6971,
16230	/* SHLL_S_W_MM */	16230	/* SHLL_S_W_MM */
16231	6974,	16231	6974,
16232	/* SHRAV_PH */	16232	/* SHRAV_PH */
16233	6977,	16233	6977,
16234	/* SHRAV_PH_MM */	16234	/* SHRAV_PH_MM */
16235	6980,	16235	6980,
16236	/* SHRAV_QB */	16236	/* SHRAV_QB */
16237	6983,	16237	6983,
16238	/* SHRAV_QB_MMR2 */	16238	/* SHRAV_QB_MMR2 */
16239	6986,	16239	6986,
16240	/* SHRAV_R_PH */	16240	/* SHRAV_R_PH */
16241	6989,	16241	6989,
16242	/* SHRAV_R_PH_MM */	16242	/* SHRAV_R_PH_MM */
16243	6992,	16243	6992,
16244	/* SHRAV_R_QB */	16244	/* SHRAV_R_QB */
16245	6995,	16245	6995,
16246	/* SHRAV_R_QB_MMR2 */	16246	/* SHRAV_R_QB_MMR2 */
16247	6998,	16247	6998,
16248	/* SHRAV_R_W */	16248	/* SHRAV_R_W */
16249	7001,	16249	7001,
16250	/* SHRAV_R_W_MM */	16250	/* SHRAV_R_W_MM */
16251	7004,	16251	7004,
16252	/* SHRA_PH */	16252	/* SHRA_PH */
16253	7007,	16253	7007,
16254	/* SHRA_PH_MM */	16254	/* SHRA_PH_MM */
16255	7010,	16255	7010,
16256	/* SHRA_QB */	16256	/* SHRA_QB */
16257	7013,	16257	7013,
16258	/* SHRA_QB_MMR2 */	16258	/* SHRA_QB_MMR2 */
16259	7016,	16259	7016,
16260	/* SHRA_R_PH */	16260	/* SHRA_R_PH */
16261	7019,	16261	7019,
16262	/* SHRA_R_PH_MM */	16262	/* SHRA_R_PH_MM */
16263	7022,	16263	7022,
16264	/* SHRA_R_QB */	16264	/* SHRA_R_QB */
16265	7025,	16265	7025,
16266	/* SHRA_R_QB_MMR2 */	16266	/* SHRA_R_QB_MMR2 */
16267	7028,	16267	7028,
16268	/* SHRA_R_W */	16268	/* SHRA_R_W */
16269	7031,	16269	7031,
16270	/* SHRA_R_W_MM */	16270	/* SHRA_R_W_MM */
16271	7034,	16271	7034,
16272	/* SHRLV_PH */	16272	/* SHRLV_PH */
16273	7037,	16273	7037,
16274	/* SHRLV_PH_MMR2 */	16274	/* SHRLV_PH_MMR2 */
16275	7040,	16275	7040,
16276	/* SHRLV_QB */	16276	/* SHRLV_QB */
16277	7043,	16277	7043,
16278	/* SHRLV_QB_MM */	16278	/* SHRLV_QB_MM */
16279	7046,	16279	7046,
16280	/* SHRL_PH */	16280	/* SHRL_PH */
16281	7049,	16281	7049,
16282	/* SHRL_PH_MMR2 */	16282	/* SHRL_PH_MMR2 */
16283	7052,	16283	7052,
16284	/* SHRL_QB */	16284	/* SHRL_QB */
16285	7055,	16285	7055,
16286	/* SHRL_QB_MM */	16286	/* SHRL_QB_MM */
16287	7058,	16287	7058,
16288	/* SH_MM */	16288	/* SH_MM */
16289	7061,	16289	7061,
16290	/* SH_MMR6 */	16290	/* SH_MMR6 */
16291	7064,	16291	7064,
16292	/* SIGRIE */	16292	/* SIGRIE */
16293	7067,	16293	7067,
16294	/* SIGRIE_MMR6 */	16294	/* SIGRIE_MMR6 */
16295	7068,	16295	7068,
16296	/* SLDI_B */	16296	/* SLDI_B */
16297	7069,	16297	7069,
16298	/* SLDI_D */	16298	/* SLDI_D */
16299	7073,	16299	7073,
16300	/* SLDI_H */	16300	/* SLDI_H */
16301	7077,	16301	7077,
16302	/* SLDI_W */	16302	/* SLDI_W */
16303	7081,	16303	7081,
16304	/* SLD_B */	16304	/* SLD_B */
16305	7085,	16305	7085,
16306	/* SLD_D */	16306	/* SLD_D */
16307	7089,	16307	7089,
16308	/* SLD_H */	16308	/* SLD_H */
16309	7093,	16309	7093,
16310	/* SLD_W */	16310	/* SLD_W */
16311	7097,	16311	7097,
16312	/* SLL */	16312	/* SLL */
16313	7101,	16313	7101,
16314	/* SLL16_MM */	16314	/* SLL16_MM */
16315	7104,	16315	7104,
16316	/* SLL16_MMR6 */	16316	/* SLL16_MMR6 */
16317	7107,	16317	7107,
16318	/* SLL64_32 */	16318	/* SLL64_32 */
16319	7110,	16319	7110,
16320	/* SLL64_64 */	16320	/* SLL64_64 */
16321	7112,	16321	7112,
16322	/* SLLI_B */	16322	/* SLLI_B */
16323	7114,	16323	7114,
16324	/* SLLI_D */	16324	/* SLLI_D */
16325	7117,	16325	7117,
16326	/* SLLI_H */	16326	/* SLLI_H */
16327	7120,	16327	7120,
16328	/* SLLI_W */	16328	/* SLLI_W */
16329	7123,	16329	7123,
16330	/* SLLV */	16330	/* SLLV */
16331	7126,	16331	7126,
16332	/* SLLV_MM */	16332	/* SLLV_MM */
16333	7129,	16333	7129,
16334	/* SLL_B */	16334	/* SLL_B */
16335	7132,	16335	7132,
16336	/* SLL_D */	16336	/* SLL_D */
16337	7135,	16337	7135,
16338	/* SLL_H */	16338	/* SLL_H */
16339	7138,	16339	7138,
16340	/* SLL_MM */	16340	/* SLL_MM */
16341	7141,	16341	7141,
16342	/* SLL_MMR6 */	16342	/* SLL_MMR6 */
16343	7144,	16343	7144,
16344	/* SLL_W */	16344	/* SLL_W */
16345	7147,	16345	7147,
16346	/* SLT */	16346	/* SLT */
16347	7150,	16347	7150,
16348	/* SLT64 */	16348	/* SLT64 */
16349	7153,	16349	7153,
16350	/* SLT_MM */	16350	/* SLT_MM */
16351	7156,	16351	7156,
16352	/* SLTi */	16352	/* SLTi */
16353	7159,	16353	7159,
16354	/* SLTi64 */	16354	/* SLTi64 */
16355	7162,	16355	7162,
16356	/* SLTi_MM */	16356	/* SLTi_MM */
16357	7165,	16357	7165,
16358	/* SLTiu */	16358	/* SLTiu */
16359	7168,	16359	7168,
16360	/* SLTiu64 */	16360	/* SLTiu64 */
16361	7171,	16361	7171,
16362	/* SLTiu_MM */	16362	/* SLTiu_MM */
16363	7174,	16363	7174,
16364	/* SLTu */	16364	/* SLTu */
16365	7177,	16365	7177,
16366	/* SLTu64 */	16366	/* SLTu64 */
16367	7180,	16367	7180,
16368	/* SLTu_MM */	16368	/* SLTu_MM */
16369	7183,	16369	7183,
16370	/* SNE */	16370	/* SNE */
16371	7186,	16371	7186,
16372	/* SNEi */	16372	/* SNEi */
16373	7189,	16373	7189,
16374	/* SPLATI_B */	16374	/* SPLATI_B */
16375	7192,	16375	7192,
16376	/* SPLATI_D */	16376	/* SPLATI_D */
16377	7195,	16377	7195,
16378	/* SPLATI_H */	16378	/* SPLATI_H */
16379	7198,	16379	7198,
16380	/* SPLATI_W */	16380	/* SPLATI_W */
16381	7201,	16381	7201,
16382	/* SPLAT_B */	16382	/* SPLAT_B */
16383	7204,	16383	7204,
16384	/* SPLAT_D */	16384	/* SPLAT_D */
16385	7207,	16385	7207,
16386	/* SPLAT_H */	16386	/* SPLAT_H */
16387	7210,	16387	7210,
16388	/* SPLAT_W */	16388	/* SPLAT_W */
16389	7213,	16389	7213,
16390	/* SRA */	16390	/* SRA */
16391	7216,	16391	7216,
16392	/* SRAI_B */	16392	/* SRAI_B */
16393	7219,	16393	7219,
16394	/* SRAI_D */	16394	/* SRAI_D */
16395	7222,	16395	7222,
16396	/* SRAI_H */	16396	/* SRAI_H */
16397	7225,	16397	7225,
16398	/* SRAI_W */	16398	/* SRAI_W */
16399	7228,	16399	7228,
16400	/* SRARI_B */	16400	/* SRARI_B */
16401	7231,	16401	7231,
16402	/* SRARI_D */	16402	/* SRARI_D */
16403	7234,	16403	7234,
16404	/* SRARI_H */	16404	/* SRARI_H */
16405	7237,	16405	7237,
16406	/* SRARI_W */	16406	/* SRARI_W */
16407	7240,	16407	7240,
16408	/* SRAR_B */	16408	/* SRAR_B */
16409	7243,	16409	7243,
16410	/* SRAR_D */	16410	/* SRAR_D */
16411	7246,	16411	7246,
16412	/* SRAR_H */	16412	/* SRAR_H */
16413	7249,	16413	7249,
16414	/* SRAR_W */	16414	/* SRAR_W */
16415	7252,	16415	7252,
16416	/* SRAV */	16416	/* SRAV */
16417	7255,	16417	7255,
16418	/* SRAV_MM */	16418	/* SRAV_MM */
16419	7258,	16419	7258,
16420	/* SRA_B */	16420	/* SRA_B */
16421	7261,	16421	7261,
16422	/* SRA_D */	16422	/* SRA_D */
16423	7264,	16423	7264,
16424	/* SRA_H */	16424	/* SRA_H */
16425	7267,	16425	7267,
16426	/* SRA_MM */	16426	/* SRA_MM */
16427	7270,	16427	7270,
16428	/* SRA_W */	16428	/* SRA_W */
16429	7273,	16429	7273,
16430	/* SRL */	16430	/* SRL */
16431	7276,	16431	7276,
16432	/* SRL16_MM */	16432	/* SRL16_MM */
16433	7279,	16433	7279,
16434	/* SRL16_MMR6 */	16434	/* SRL16_MMR6 */
16435	7282,	16435	7282,
16436	/* SRLI_B */	16436	/* SRLI_B */
16437	7285,	16437	7285,
16438	/* SRLI_D */	16438	/* SRLI_D */
16439	7288,	16439	7288,
16440	/* SRLI_H */	16440	/* SRLI_H */
16441	7291,	16441	7291,
16442	/* SRLI_W */	16442	/* SRLI_W */
16443	7294,	16443	7294,
16444	/* SRLRI_B */	16444	/* SRLRI_B */
16445	7297,	16445	7297,
16446	/* SRLRI_D */	16446	/* SRLRI_D */
16447	7300,	16447	7300,
16448	/* SRLRI_H */	16448	/* SRLRI_H */
16449	7303,	16449	7303,
16450	/* SRLRI_W */	16450	/* SRLRI_W */
16451	7306,	16451	7306,
16452	/* SRLR_B */	16452	/* SRLR_B */
16453	7309,	16453	7309,
16454	/* SRLR_D */	16454	/* SRLR_D */
16455	7312,	16455	7312,
16456	/* SRLR_H */	16456	/* SRLR_H */
16457	7315,	16457	7315,
16458	/* SRLR_W */	16458	/* SRLR_W */
16459	7318,	16459	7318,
16460	/* SRLV */	16460	/* SRLV */
16461	7321,	16461	7321,
16462	/* SRLV_MM */	16462	/* SRLV_MM */
16463	7324,	16463	7324,
16464	/* SRL_B */	16464	/* SRL_B */
16465	7327,	16465	7327,
16466	/* SRL_D */	16466	/* SRL_D */
16467	7330,	16467	7330,
16468	/* SRL_H */	16468	/* SRL_H */
16469	7333,	16469	7333,
16470	/* SRL_MM */	16470	/* SRL_MM */
16471	7336,	16471	7336,
16472	/* SRL_W */	16472	/* SRL_W */
16473	7339,	16473	7339,
16474	/* SSNOP */	16474	/* SSNOP */
16475	7342,	16475	7342,
16476	/* SSNOP_MM */	16476	/* SSNOP_MM */
16477	7342,	16477	7342,
16478	/* SSNOP_MMR6 */	16478	/* SSNOP_MMR6 */
16479	7342,	16479	7342,
16480	/* ST_B */	16480	/* ST_B */
16481	7342,	16481	7342,
16482	/* ST_D */	16482	/* ST_D */
16483	7345,	16483	7345,
16484	/* ST_H */	16484	/* ST_H */
16485	7348,	16485	7348,
16486	/* ST_W */	16486	/* ST_W */
16487	7351,	16487	7351,
16488	/* SUB */	16488	/* SUB */
16489	7354,	16489	7354,
16490	/* SUBQH_PH */	16490	/* SUBQH_PH */
16491	7357,	16491	7357,
16492	/* SUBQH_PH_MMR2 */	16492	/* SUBQH_PH_MMR2 */
16493	7360,	16493	7360,
16494	/* SUBQH_R_PH */	16494	/* SUBQH_R_PH */
16495	7363,	16495	7363,
16496	/* SUBQH_R_PH_MMR2 */	16496	/* SUBQH_R_PH_MMR2 */
16497	7366,	16497	7366,
16498	/* SUBQH_R_W */	16498	/* SUBQH_R_W */
16499	7369,	16499	7369,
16500	/* SUBQH_R_W_MMR2 */	16500	/* SUBQH_R_W_MMR2 */
16501	7372,	16501	7372,
16502	/* SUBQH_W */	16502	/* SUBQH_W */
16503	7375,	16503	7375,
16504	/* SUBQH_W_MMR2 */	16504	/* SUBQH_W_MMR2 */
16505	7378,	16505	7378,
16506	/* SUBQ_PH */	16506	/* SUBQ_PH */
16507	7381,	16507	7381,
16508	/* SUBQ_PH_MM */	16508	/* SUBQ_PH_MM */
16509	7384,	16509	7384,
16510	/* SUBQ_S_PH */	16510	/* SUBQ_S_PH */
16511	7387,	16511	7387,
16512	/* SUBQ_S_PH_MM */	16512	/* SUBQ_S_PH_MM */
16513	7390,	16513	7390,
16514	/* SUBQ_S_W */	16514	/* SUBQ_S_W */
16515	7393,	16515	7393,
16516	/* SUBQ_S_W_MM */	16516	/* SUBQ_S_W_MM */
16517	7396,	16517	7396,
16518	/* SUBSUS_U_B */	16518	/* SUBSUS_U_B */
16519	7399,	16519	7399,
16520	/* SUBSUS_U_D */	16520	/* SUBSUS_U_D */
16521	7402,	16521	7402,
16522	/* SUBSUS_U_H */	16522	/* SUBSUS_U_H */
16523	7405,	16523	7405,
16524	/* SUBSUS_U_W */	16524	/* SUBSUS_U_W */
16525	7408,	16525	7408,
16526	/* SUBSUU_S_B */	16526	/* SUBSUU_S_B */
16527	7411,	16527	7411,
16528	/* SUBSUU_S_D */	16528	/* SUBSUU_S_D */
16529	7414,	16529	7414,
16530	/* SUBSUU_S_H */	16530	/* SUBSUU_S_H */
16531	7417,	16531	7417,
16532	/* SUBSUU_S_W */	16532	/* SUBSUU_S_W */
16533	7420,	16533	7420,
16534	/* SUBS_S_B */	16534	/* SUBS_S_B */
16535	7423,	16535	7423,
16536	/* SUBS_S_D */	16536	/* SUBS_S_D */
16537	7426,	16537	7426,
16538	/* SUBS_S_H */	16538	/* SUBS_S_H */
16539	7429,	16539	7429,
16540	/* SUBS_S_W */	16540	/* SUBS_S_W */
16541	7432,	16541	7432,
16542	/* SUBS_U_B */	16542	/* SUBS_U_B */
16543	7435,	16543	7435,
16544	/* SUBS_U_D */	16544	/* SUBS_U_D */
16545	7438,	16545	7438,
16546	/* SUBS_U_H */	16546	/* SUBS_U_H */
16547	7441,	16547	7441,
16548	/* SUBS_U_W */	16548	/* SUBS_U_W */
16549	7444,	16549	7444,
16550	/* SUBU16_MM */	16550	/* SUBU16_MM */
16551	7447,	16551	7447,
16552	/* SUBU16_MMR6 */	16552	/* SUBU16_MMR6 */
16553	7450,	16553	7450,
16554	/* SUBUH_QB */	16554	/* SUBUH_QB */
16555	7453,	16555	7453,
16556	/* SUBUH_QB_MMR2 */	16556	/* SUBUH_QB_MMR2 */
16557	7456,	16557	7456,
16558	/* SUBUH_R_QB */	16558	/* SUBUH_R_QB */
16559	7459,	16559	7459,
16560	/* SUBUH_R_QB_MMR2 */	16560	/* SUBUH_R_QB_MMR2 */
16561	7462,	16561	7462,
16562	/* SUBU_MMR6 */	16562	/* SUBU_MMR6 */
16563	7465,	16563	7465,
16564	/* SUBU_PH */	16564	/* SUBU_PH */
16565	7468,	16565	7468,
16566	/* SUBU_PH_MMR2 */	16566	/* SUBU_PH_MMR2 */
16567	7471,	16567	7471,
16568	/* SUBU_QB */	16568	/* SUBU_QB */
16569	7474,	16569	7474,
16570	/* SUBU_QB_MM */	16570	/* SUBU_QB_MM */
16571	7477,	16571	7477,
16572	/* SUBU_S_PH */	16572	/* SUBU_S_PH */
16573	7480,	16573	7480,
16574	/* SUBU_S_PH_MMR2 */	16574	/* SUBU_S_PH_MMR2 */
16575	7483,	16575	7483,
16576	/* SUBU_S_QB */	16576	/* SUBU_S_QB */
16577	7486,	16577	7486,
16578	/* SUBU_S_QB_MM */	16578	/* SUBU_S_QB_MM */
16579	7489,	16579	7489,
16580	/* SUBVI_B */	16580	/* SUBVI_B */
16581	7492,	16581	7492,
16582	/* SUBVI_D */	16582	/* SUBVI_D */
16583	7495,	16583	7495,
16584	/* SUBVI_H */	16584	/* SUBVI_H */
16585	7498,	16585	7498,
16586	/* SUBVI_W */	16586	/* SUBVI_W */
16587	7501,	16587	7501,
16588	/* SUBV_B */	16588	/* SUBV_B */
16589	7504,	16589	7504,
16590	/* SUBV_D */	16590	/* SUBV_D */
16591	7507,	16591	7507,
16592	/* SUBV_H */	16592	/* SUBV_H */
16593	7510,	16593	7510,
16594	/* SUBV_W */	16594	/* SUBV_W */
16595	7513,	16595	7513,
16596	/* SUB_MM */	16596	/* SUB_MM */
16597	7516,	16597	7516,
16598	/* SUB_MMR6 */	16598	/* SUB_MMR6 */
16599	7519,	16599	7519,
16600	/* SUBu */	16600	/* SUBu */
16601	7522,	16601	7522,
16602	/* SUBu_MM */	16602	/* SUBu_MM */
16603	7525,	16603	7525,
16604	/* SUXC1 */	16604	/* SUXC1 */
16605	7528,	16605	7528,
16606	/* SUXC164 */	16606	/* SUXC164 */
16607	7531,	16607	7531,
16608	/* SUXC1_MM */	16608	/* SUXC1_MM */
16609	7534,	16609	7534,
16610	/* SW */	16610	/* SW */
16611	7537,	16611	7537,
16612	/* SW16_MM */	16612	/* SW16_MM */
16613	7540,	16613	7540,
16614	/* SW16_MMR6 */	16614	/* SW16_MMR6 */
16615	7543,	16615	7543,
16616	/* SW64 */	16616	/* SW64 */
16617	7546,	16617	7546,
16618	/* SWC1 */	16618	/* SWC1 */
16619	7549,	16619	7549,
16620	/* SWC1_MM */	16620	/* SWC1_MM */
16621	7552,	16621	7552,
16622	/* SWC2 */	16622	/* SWC2 */
16623	7555,	16623	7555,
16624	/* SWC2_MMR6 */	16624	/* SWC2_MMR6 */
16625	7558,	16625	7558,
16626	/* SWC2_R6 */	16626	/* SWC2_R6 */
16627	7561,	16627	7561,
16628	/* SWC3 */	16628	/* SWC3 */
16629	7564,	16629	7564,
16630	/* SWDSP */	16630	/* SWDSP */
16631	7567,	16631	7567,
16632	/* SWDSP_MM */	16632	/* SWDSP_MM */
16633	7570,	16633	7570,
16634	/* SWE */	16634	/* SWE */
16635	7573,	16635	7573,
16636	/* SWE_MM */	16636	/* SWE_MM */
16637	7576,	16637	7576,
16638	/* SWL */	16638	/* SWL */
16639	7579,	16639	7579,
16640	/* SWL64 */	16640	/* SWL64 */
16641	7582,	16641	7582,
16642	/* SWLE */	16642	/* SWLE */
16643	7585,	16643	7585,
16644	/* SWLE_MM */	16644	/* SWLE_MM */
16645	7588,	16645	7588,
16646	/* SWL_MM */	16646	/* SWL_MM */
16647	7591,	16647	7591,
16648	/* SWM16_MM */	16648	/* SWM16_MM */
16649	7594,	16649	7594,
16650	/* SWM16_MMR6 */	16650	/* SWM16_MMR6 */
16651	7597,	16651	7597,
16652	/* SWM32_MM */	16652	/* SWM32_MM */
16653	7600,	16653	7600,
16654	/* SWP_MM */	16654	/* SWP_MM */
16655	7603,	16655	7603,
16656	/* SWR */	16656	/* SWR */
16657	7607,	16657	7607,
16658	/* SWR64 */	16658	/* SWR64 */
16659	7610,	16659	7610,
16660	/* SWRE */	16660	/* SWRE */
16661	7613,	16661	7613,
16662	/* SWRE_MM */	16662	/* SWRE_MM */
16663	7616,	16663	7616,
16664	/* SWR_MM */	16664	/* SWR_MM */
16665	7619,	16665	7619,
16666	/* SWSP_MM */	16666	/* SWSP_MM */
16667	7622,	16667	7622,
16668	/* SWSP_MMR6 */	16668	/* SWSP_MMR6 */
16669	7625,	16669	7625,
16670	/* SWXC1 */	16670	/* SWXC1 */
16671	7628,	16671	7628,
16672	/* SWXC1_MM */	16672	/* SWXC1_MM */
16673	7631,	16673	7631,
16674	/* SW_MM */	16674	/* SW_MM */
16675	7634,	16675	7634,
16676	/* SW_MMR6 */	16676	/* SW_MMR6 */
16677	7637,	16677	7637,
16678	/* SYNC */	16678	/* SYNC */
16679	7640,	16679	7640,
16680	/* SYNCI */	16680	/* SYNCI */
16681	7641,	16681	7641,
16682	/* SYNCI_MM */	16682	/* SYNCI_MM */
16683	7643,	16683	7643,
16684	/* SYNCI_MMR6 */	16684	/* SYNCI_MMR6 */
16685	7645,	16685	7645,
16686	/* SYNC_MM */	16686	/* SYNC_MM */
16687	7647,	16687	7647,
16688	/* SYNC_MMR6 */	16688	/* SYNC_MMR6 */
16689	7648,	16689	7648,
16690	/* SYSCALL */	16690	/* SYSCALL */
16691	7649,	16691	7649,
16692	/* SYSCALL_MM */	16692	/* SYSCALL_MM */
16693	7650,	16693	7650,
16694	/* Save16 */	16694	/* Save16 */
16695	7651,	16695	7651,
16696	/* SaveX16 */	16696	/* SaveX16 */
16697	7651,	16697	7651,
16698	/* SbRxRyOffMemX16 */	16698	/* SbRxRyOffMemX16 */
16699	7651,	16699	7651,
16700	/* SebRx16 */	16700	/* SebRx16 */
16701	7654,	16701	7654,
16702	/* SehRx16 */	16702	/* SehRx16 */
16703	7656,	16703	7656,
16704	/* ShRxRyOffMemX16 */	16704	/* ShRxRyOffMemX16 */
16705	7658,	16705	7658,
16706	/* SllX16 */	16706	/* SllX16 */
16707	7661,	16707	7661,
16708	/* SllvRxRy16 */	16708	/* SllvRxRy16 */
16709	7664,	16709	7664,
16710	/* SltRxRy16 */	16710	/* SltRxRy16 */
16711	7667,	16711	7667,
16712	/* SltiRxImm16 */	16712	/* SltiRxImm16 */
16713	7669,	16713	7669,
16714	/* SltiRxImmX16 */	16714	/* SltiRxImmX16 */
16715	7671,	16715	7671,
16716	/* SltiuRxImm16 */	16716	/* SltiuRxImm16 */
16717	7673,	16717	7673,
16718	/* SltiuRxImmX16 */	16718	/* SltiuRxImmX16 */
16719	7675,	16719	7675,
16720	/* SltuRxRy16 */	16720	/* SltuRxRy16 */
16721	7677,	16721	7677,
16722	/* SraX16 */	16722	/* SraX16 */
16723	7679,	16723	7679,
16724	/* SravRxRy16 */	16724	/* SravRxRy16 */
16725	7682,	16725	7682,
16726	/* SrlX16 */	16726	/* SrlX16 */
16727	7685,	16727	7685,
16728	/* SrlvRxRy16 */	16728	/* SrlvRxRy16 */
16729	7688,	16729	7688,
16730	/* SubuRxRyRz16 */	16730	/* SubuRxRyRz16 */
16731	7691,	16731	7691,
16732	/* SwRxRyOffMemX16 */	16732	/* SwRxRyOffMemX16 */
16733	7694,	16733	7694,
16734	/* SwRxSpImmX16 */	16734	/* SwRxSpImmX16 */
16735	7697,	16735	7697,
16736	/* TEQ */	16736	/* TEQ */
16737	7700,	16737	7700,
16738	/* TEQI */	16738	/* TEQI */
16739	7703,	16739	7703,
16740	/* TEQI_MM */	16740	/* TEQI_MM */
16741	7705,	16741	7705,
16742	/* TEQ_MM */	16742	/* TEQ_MM */
16743	7707,	16743	7707,
16744	/* TGE */	16744	/* TGE */
16745	7710,	16745	7710,
16746	/* TGEI */	16746	/* TGEI */
16747	7713,	16747	7713,
16748	/* TGEIU */	16748	/* TGEIU */
16749	7715,	16749	7715,
16750	/* TGEIU_MM */	16750	/* TGEIU_MM */
16751	7717,	16751	7717,
16752	/* TGEI_MM */	16752	/* TGEI_MM */
16753	7719,	16753	7719,
16754	/* TGEU */	16754	/* TGEU */
16755	7721,	16755	7721,
16756	/* TGEU_MM */	16756	/* TGEU_MM */
16757	7724,	16757	7724,
16758	/* TGE_MM */	16758	/* TGE_MM */
16759	7727,	16759	7727,
16760	/* TLBGINV */	16760	/* TLBGINV */
16761	7730,	16761	7730,
16762	/* TLBGINVF */	16762	/* TLBGINVF */
16763	7730,	16763	7730,
16764	/* TLBGINVF_MM */	16764	/* TLBGINVF_MM */
16765	7730,	16765	7730,
16766	/* TLBGINV_MM */	16766	/* TLBGINV_MM */
16767	7730,	16767	7730,
16768	/* TLBGP */	16768	/* TLBGP */
16769	7730,	16769	7730,
16770	/* TLBGP_MM */	16770	/* TLBGP_MM */
16771	7730,	16771	7730,
16772	/* TLBGR */	16772	/* TLBGR */
16773	7730,	16773	7730,
16774	/* TLBGR_MM */	16774	/* TLBGR_MM */
16775	7730,	16775	7730,
16776	/* TLBGWI */	16776	/* TLBGWI */
16777	7730,	16777	7730,
16778	/* TLBGWI_MM */	16778	/* TLBGWI_MM */
16779	7730,	16779	7730,
16780	/* TLBGWR */	16780	/* TLBGWR */
16781	7730,	16781	7730,
16782	/* TLBGWR_MM */	16782	/* TLBGWR_MM */
16783	7730,	16783	7730,
16784	/* TLBINV */	16784	/* TLBINV */
16785	7730,	16785	7730,
16786	/* TLBINVF */	16786	/* TLBINVF */
16787	7730,	16787	7730,
16788	/* TLBINVF_MMR6 */	16788	/* TLBINVF_MMR6 */
16789	7730,	16789	7730,
16790	/* TLBINV_MMR6 */	16790	/* TLBINV_MMR6 */
16791	7730,	16791	7730,
16792	/* TLBP */	16792	/* TLBP */
16793	7730,	16793	7730,
16794	/* TLBP_MM */	16794	/* TLBP_MM */
16795	7730,	16795	7730,
16796	/* TLBR */	16796	/* TLBR */
16797	7730,	16797	7730,
16798	/* TLBR_MM */	16798	/* TLBR_MM */
16799	7730,	16799	7730,
16800	/* TLBWI */	16800	/* TLBWI */
16801	7730,	16801	7730,
16802	/* TLBWI_MM */	16802	/* TLBWI_MM */
16803	7730,	16803	7730,
16804	/* TLBWR */	16804	/* TLBWR */
16805	7730,	16805	7730,
16806	/* TLBWR_MM */	16806	/* TLBWR_MM */
16807	7730,	16807	7730,
16808	/* TLT */	16808	/* TLT */
16809	7730,	16809	7730,
16810	/* TLTI */	16810	/* TLTI */
16811	7733,	16811	7733,
16812	/* TLTIU_MM */	16812	/* TLTIU_MM */
16813	7735,	16813	7735,
16814	/* TLTI_MM */	16814	/* TLTI_MM */
16815	7737,	16815	7737,
16816	/* TLTU */	16816	/* TLTU */
16817	7739,	16817	7739,
16818	/* TLTU_MM */	16818	/* TLTU_MM */
16819	7742,	16819	7742,
16820	/* TLT_MM */	16820	/* TLT_MM */
16821	7745,	16821	7745,
16822	/* TNE */	16822	/* TNE */
16823	7748,	16823	7748,
16824	/* TNEI */	16824	/* TNEI */
16825	7751,	16825	7751,
16826	/* TNEI_MM */	16826	/* TNEI_MM */
16827	7753,	16827	7753,
16828	/* TNE_MM */	16828	/* TNE_MM */
16829	7755,	16829	7755,
16830	/* TRUNC_L_D64 */	16830	/* TRUNC_L_D64 */
16831	7758,	16831	7758,
16832	/* TRUNC_L_D_MMR6 */	16832	/* TRUNC_L_D_MMR6 */
16833	7760,	16833	7760,
16834	/* TRUNC_L_S */	16834	/* TRUNC_L_S */
16835	7762,	16835	7762,
16836	/* TRUNC_L_S_MMR6 */	16836	/* TRUNC_L_S_MMR6 */
16837	7764,	16837	7764,
16838	/* TRUNC_W_D32 */	16838	/* TRUNC_W_D32 */
16839	7766,	16839	7766,
16840	/* TRUNC_W_D64 */	16840	/* TRUNC_W_D64 */
16841	7768,	16841	7768,
16842	/* TRUNC_W_D_MMR6 */	16842	/* TRUNC_W_D_MMR6 */
16843	7770,	16843	7770,
16844	/* TRUNC_W_MM */	16844	/* TRUNC_W_MM */
16845	7772,	16845	7772,
16846	/* TRUNC_W_S */	16846	/* TRUNC_W_S */
16847	7774,	16847	7774,
16848	/* TRUNC_W_S_MM */	16848	/* TRUNC_W_S_MM */
16849	7776,	16849	7776,
16850	/* TRUNC_W_S_MMR6 */	16850	/* TRUNC_W_S_MMR6 */
16851	7778,	16851	7778,
16852	/* TTLTIU */	16852	/* TTLTIU */
16853	7780,	16853	7780,
16854	/* UDIV */	16854	/* UDIV */
16855	7782,	16855	7782,
16856	/* UDIV_MM */	16856	/* UDIV_MM */
16857	7784,	16857	7784,
16858	/* V3MULU */	16858	/* V3MULU */
16859	7786,	16859	7786,
16860	/* VMM0 */	16860	/* VMM0 */
16861	7789,	16861	7789,
16862	/* VMULU */	16862	/* VMULU */
16863	7792,	16863	7792,
16864	/* VSHF_B */	16864	/* VSHF_B */
16865	7795,	16865	7795,
16866	/* VSHF_D */	16866	/* VSHF_D */
16867	7799,	16867	7799,
16868	/* VSHF_H */	16868	/* VSHF_H */
16869	7803,	16869	7803,
16870	/* VSHF_W */	16870	/* VSHF_W */
16871	7807,	16871	7807,
16872	/* WAIT */	16872	/* WAIT */
16873	7811,	16873	7811,
16874	/* WAIT_MM */	16874	/* WAIT_MM */
16875	7811,	16875	7811,
16876	/* WAIT_MMR6 */	16876	/* WAIT_MMR6 */
16877	7812,	16877	7812,
16878	/* WRDSP */	16878	/* WRDSP */
16879	7813,	16879	7813,
16880	/* WRDSP_MM */	16880	/* WRDSP_MM */
16881	7815,	16881	7815,
16882	/* WRPGPR_MMR6 */	16882	/* WRPGPR_MMR6 */
16883	7817,	16883	7817,
16884	/* WSBH */	16884	/* WSBH */
16885	7819,	16885	7819,
16886	/* WSBH_MM */	16886	/* WSBH_MM */
16887	7821,	16887	7821,
16888	/* WSBH_MMR6 */	16888	/* WSBH_MMR6 */
16889	7823,	16889	7823,
16890	/* XOR */	16890	/* XOR */
16891	7825,	16891	7825,
16892	/* XOR16_MM */	16892	/* XOR16_MM */
16893	7828,	16893	7828,
16894	/* XOR16_MMR6 */	16894	/* XOR16_MMR6 */
16895	7831,	16895	7831,
16896	/* XOR64 */	16896	/* XOR64 */
16897	7834,	16897	7834,
16898	/* XORI_B */	16898	/* XORI_B */
16899	7837,	16899	7837,
16900	/* XORI_MMR6 */	16900	/* XORI_MMR6 */
16901	7840,	16901	7840,
16902	/* XOR_MM */	16902	/* XOR_MM */
16903	7843,	16903	7843,
16904	/* XOR_MMR6 */	16904	/* XOR_MMR6 */
16905	7846,	16905	7846,
16906	/* XOR_V */	16906	/* XOR_V */
16907	7849,	16907	7849,
16908	/* XORi */	16908	/* XORi */
16909	7852,	16909	7852,
16910	/* XORi64 */	16910	/* XORi64 */
16911	7855,	16911	7855,
16912	/* XORi_MM */	16912	/* XORi_MM */
16913	7858,	16913	7858,
16914	/* XorRxRxRy16 */	16914	/* XorRxRxRy16 */
16915	7861,	16915	7861,
16916	/* YIELD */	16916	/* YIELD */
16917	7864,	16917	7864,
16918	};	16918	};
16919		16919
16920	using namespace OpTypes;	16920	using namespace OpTypes;
16921	static const int16_t OpcodeOperandTypes[] = {	16921	static const int16_t OpcodeOperandTypes[] = {
16922		16922
16923	/* PHI */	16923	/* PHI */
16924	-1,	16924	-1,
16925	/* INLINEASM */	16925	/* INLINEASM */
16926	/* INLINEASM_BR */	16926	/* INLINEASM_BR */
16927	/* CFI_INSTRUCTION */	16927	/* CFI_INSTRUCTION */
16928	i32imm,	16928	i32imm,
16929	/* EH_LABEL */	16929	/* EH_LABEL */
16930	i32imm,	16930	i32imm,
16931	/* GC_LABEL */	16931	/* GC_LABEL */
16932	i32imm,	16932	i32imm,
16933	/* ANNOTATION_LABEL */	16933	/* ANNOTATION_LABEL */
16934	i32imm,	16934	i32imm,
16935	/* KILL */	16935	/* KILL */
16936	/* EXTRACT_SUBREG */	16936	/* EXTRACT_SUBREG */
16937	-1, -1, i32imm,	16937	-1, -1, i32imm,
16938	/* INSERT_SUBREG */	16938	/* INSERT_SUBREG */
16939	-1, -1, -1, i32imm,	16939	-1, -1, -1, i32imm,
16940	/* IMPLICIT_DEF */	16940	/* IMPLICIT_DEF */
16941	-1,	16941	-1,
16942	/* SUBREG_TO_REG */	16942	/* SUBREG_TO_REG */
16943	-1, -1, -1, i32imm,	16943	-1, -1, -1, i32imm,
16944	/* COPY_TO_REGCLASS */	16944	/* COPY_TO_REGCLASS */
16945	-1, -1, i32imm,	16945	-1, -1, i32imm,
16946	/* DBG_VALUE */	16946	/* DBG_VALUE */
16947	/* DBG_VALUE_LIST */	16947	/* DBG_VALUE_LIST */
16948	/* DBG_INSTR_REF */	16948	/* DBG_INSTR_REF */
16949	/* DBG_PHI */	16949	/* DBG_PHI */
16950	/* DBG_LABEL */	16950	/* DBG_LABEL */
16951	-1,	16951	-1,
16952	/* REG_SEQUENCE */	16952	/* REG_SEQUENCE */
16953	-1, -1,	16953	-1, -1,
16954	/* COPY */	16954	/* COPY */
16955	-1, -1,	16955	-1, -1,
16956	/* BUNDLE */	16956	/* BUNDLE */
16957	/* LIFETIME_START */	16957	/* LIFETIME_START */
16958	i32imm,	16958	i32imm,
16959	/* LIFETIME_END */	16959	/* LIFETIME_END */
16960	i32imm,	16960	i32imm,
16961	/* PSEUDO_PROBE */	16961	/* PSEUDO_PROBE */
16962	i64imm, i64imm, i8imm, i32imm,	16962	i64imm, i64imm, i8imm, i32imm,
16963	/* ARITH_FENCE */	16963	/* ARITH_FENCE */
16964	-1, -1,	16964	-1, -1,
16965	/* STACKMAP */	16965	/* STACKMAP */
16966	i64imm, i32imm,	16966	i64imm, i32imm,
16967	/* FENTRY_CALL */	16967	/* FENTRY_CALL */
16968	/* PATCHPOINT */	16968	/* PATCHPOINT */
16969	-1, i64imm, i32imm, -1, i32imm, i32imm,	16969	-1, i64imm, i32imm, -1, i32imm, i32imm,
16970	/* LOAD_STACK_GUARD */	16970	/* LOAD_STACK_GUARD */
16971	-1,	16971	-1,
16972	/* PREALLOCATED_SETUP */	16972	/* PREALLOCATED_SETUP */
16973	i32imm,	16973	i32imm,
16974	/* PREALLOCATED_ARG */	16974	/* PREALLOCATED_ARG */
16975	-1, i32imm, i32imm,	16975	-1, i32imm, i32imm,
16976	/* STATEPOINT */	16976	/* STATEPOINT */
16977	/* LOCAL_ESCAPE */	16977	/* LOCAL_ESCAPE */
16978	-1, i32imm,	16978	-1, i32imm,
16979	/* FAULTING_OP */	16979	/* FAULTING_OP */
16980	-1,	16980	-1,
16981	/* PATCHABLE_OP */	16981	/* PATCHABLE_OP */
16982	/* PATCHABLE_FUNCTION_ENTER */	16982	/* PATCHABLE_FUNCTION_ENTER */
16983	/* PATCHABLE_RET */	16983	/* PATCHABLE_RET */
16984	/* PATCHABLE_FUNCTION_EXIT */	16984	/* PATCHABLE_FUNCTION_EXIT */
16985	/* PATCHABLE_TAIL_CALL */	16985	/* PATCHABLE_TAIL_CALL */
16986	/* PATCHABLE_EVENT_CALL */	16986	/* PATCHABLE_EVENT_CALL */
16987	-1, -1,	16987	-1, -1,
16988	/* PATCHABLE_TYPED_EVENT_CALL */	16988	/* PATCHABLE_TYPED_EVENT_CALL */
16989	-1, -1, -1,	16989	-1, -1, -1,
16990	/* ICALL_BRANCH_FUNNEL */	16990	/* ICALL_BRANCH_FUNNEL */
16991	/* MEMBARRIER */	16991	/* MEMBARRIER */
16992	/* G_ASSERT_SEXT */	16992	/* G_ASSERT_SEXT */
16993	type0, type0, untyped_imm_0,	16993	type0, type0, untyped_imm_0,
16994	/* G_ASSERT_ZEXT */	16994	/* G_ASSERT_ZEXT */
16995	type0, type0, untyped_imm_0,	16995	type0, type0, untyped_imm_0,
16996	/* G_ASSERT_ALIGN */	16996	/* G_ASSERT_ALIGN */
16997	type0, type0, untyped_imm_0,	16997	type0, type0, untyped_imm_0,
16998	/* G_ADD */	16998	/* G_ADD */
16999	type0, type0, type0,	16999	type0, type0, type0,
17000	/* G_SUB */	17000	/* G_SUB */
17001	type0, type0, type0,	17001	type0, type0, type0,
17002	/* G_MUL */	17002	/* G_MUL */
17003	type0, type0, type0,	17003	type0, type0, type0,
17004	/* G_SDIV */	17004	/* G_SDIV */
17005	type0, type0, type0,	17005	type0, type0, type0,
17006	/* G_UDIV */	17006	/* G_UDIV */
17007	type0, type0, type0,	17007	type0, type0, type0,
17008	/* G_SREM */	17008	/* G_SREM */
17009	type0, type0, type0,	17009	type0, type0, type0,
17010	/* G_UREM */	17010	/* G_UREM */
17011	type0, type0, type0,	17011	type0, type0, type0,
17012	/* G_SDIVREM */	17012	/* G_SDIVREM */
17013	type0, type0, type0, type0,	17013	type0, type0, type0, type0,
17014	/* G_UDIVREM */	17014	/* G_UDIVREM */
17015	type0, type0, type0, type0,	17015	type0, type0, type0, type0,
17016	/* G_AND */	17016	/* G_AND */
17017	type0, type0, type0,	17017	type0, type0, type0,
17018	/* G_OR */	17018	/* G_OR */
17019	type0, type0, type0,	17019	type0, type0, type0,
17020	/* G_XOR */	17020	/* G_XOR */
17021	type0, type0, type0,	17021	type0, type0, type0,
17022	/* G_IMPLICIT_DEF */	17022	/* G_IMPLICIT_DEF */
17023	type0,	17023	type0,
17024	/* G_PHI */	17024	/* G_PHI */
17025	type0,	17025	type0,
17026	/* G_FRAME_INDEX */	17026	/* G_FRAME_INDEX */
17027	type0, -1,	17027	type0, -1,
17028	/* G_GLOBAL_VALUE */	17028	/* G_GLOBAL_VALUE */
17029	type0, -1,	17029	type0, -1,
17030	/* G_CONSTANT_POOL */	17030	/* G_CONSTANT_POOL */
17031	type0, -1,	17031	type0, -1,
17032	/* G_EXTRACT */	17032	/* G_EXTRACT */
17033	type0, type1, untyped_imm_0,	17033	type0, type1, untyped_imm_0,
17034	/* G_UNMERGE_VALUES */	17034	/* G_UNMERGE_VALUES */
17035	type0, type1,	17035	type0, type1,
17036	/* G_INSERT */	17036	/* G_INSERT */
17037	type0, type0, type1, untyped_imm_0,	17037	type0, type0, type1, untyped_imm_0,
17038	/* G_MERGE_VALUES */	17038	/* G_MERGE_VALUES */
17039	type0, type1,	17039	type0, type1,
17040	/* G_BUILD_VECTOR */	17040	/* G_BUILD_VECTOR */
17041	type0, type1,	17041	type0, type1,
17042	/* G_BUILD_VECTOR_TRUNC */	17042	/* G_BUILD_VECTOR_TRUNC */
17043	type0, type1,	17043	type0, type1,
17044	/* G_CONCAT_VECTORS */	17044	/* G_CONCAT_VECTORS */
17045	type0, type1,	17045	type0, type1,
17046	/* G_PTRTOINT */	17046	/* G_PTRTOINT */
17047	type0, type1,	17047	type0, type1,
17048	/* G_INTTOPTR */	17048	/* G_INTTOPTR */
17049	type0, type1,	17049	type0, type1,
17050	/* G_BITCAST */	17050	/* G_BITCAST */
17051	type0, type1,	17051	type0, type1,
17052	/* G_FREEZE */	17052	/* G_FREEZE */
17053	type0, type0,	17053	type0, type0,
17054	/* G_CONSTANT_FOLD_BARRIER */	17054	/* G_CONSTANT_FOLD_BARRIER */
17055	type0, type0,	17055	type0, type0,
17056	/* G_INTRINSIC_FPTRUNC_ROUND */	17056	/* G_INTRINSIC_FPTRUNC_ROUND */
17057	type0, type1, i32imm,	17057	type0, type1, i32imm,
17058	/* G_INTRINSIC_TRUNC */	17058	/* G_INTRINSIC_TRUNC */
17059	type0, type0,	17059	type0, type0,
17060	/* G_INTRINSIC_ROUND */	17060	/* G_INTRINSIC_ROUND */
17061	type0, type0,	17061	type0, type0,
17062	/* G_INTRINSIC_LRINT */	17062	/* G_INTRINSIC_LRINT */
17063	type0, type1,	17063	type0, type1,
17064	/* G_INTRINSIC_ROUNDEVEN */	17064	/* G_INTRINSIC_ROUNDEVEN */
17065	type0, type0,	17065	type0, type0,
17066	/* G_READCYCLECOUNTER */	17066	/* G_READCYCLECOUNTER */
17067	type0,	17067	type0,
17068	/* G_LOAD */	17068	/* G_LOAD */
17069	type0, ptype1,	17069	type0, ptype1,
17070	/* G_SEXTLOAD */	17070	/* G_SEXTLOAD */
17071	type0, ptype1,	17071	type0, ptype1,
17072	/* G_ZEXTLOAD */	17072	/* G_ZEXTLOAD */
17073	type0, ptype1,	17073	type0, ptype1,
17074	/* G_INDEXED_LOAD */	17074	/* G_INDEXED_LOAD */
17075	type0, ptype1, ptype1, type2, -1,	17075	type0, ptype1, ptype1, type2, -1,
17076	/* G_INDEXED_SEXTLOAD */	17076	/* G_INDEXED_SEXTLOAD */
17077	type0, ptype1, ptype1, type2, -1,	17077	type0, ptype1, ptype1, type2, -1,
17078	/* G_INDEXED_ZEXTLOAD */	17078	/* G_INDEXED_ZEXTLOAD */
17079	type0, ptype1, ptype1, type2, -1,	17079	type0, ptype1, ptype1, type2, -1,
17080	/* G_STORE */	17080	/* G_STORE */
17081	type0, ptype1,	17081	type0, ptype1,
17082	/* G_INDEXED_STORE */	17082	/* G_INDEXED_STORE */
17083	ptype0, type1, ptype0, ptype2, -1,	17083	ptype0, type1, ptype0, ptype2, -1,
17084	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	17084	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
17085	type0, type1, type2, type0, type0,	17085	type0, type1, type2, type0, type0,
17086	/* G_ATOMIC_CMPXCHG */	17086	/* G_ATOMIC_CMPXCHG */
17087	type0, ptype1, type0, type0,	17087	type0, ptype1, type0, type0,
17088	/* G_ATOMICRMW_XCHG */	17088	/* G_ATOMICRMW_XCHG */
17089	type0, ptype1, type0,	17089	type0, ptype1, type0,
17090	/* G_ATOMICRMW_ADD */	17090	/* G_ATOMICRMW_ADD */
17091	type0, ptype1, type0,	17091	type0, ptype1, type0,
17092	/* G_ATOMICRMW_SUB */	17092	/* G_ATOMICRMW_SUB */
17093	type0, ptype1, type0,	17093	type0, ptype1, type0,
17094	/* G_ATOMICRMW_AND */	17094	/* G_ATOMICRMW_AND */
17095	type0, ptype1, type0,	17095	type0, ptype1, type0,
17096	/* G_ATOMICRMW_NAND */	17096	/* G_ATOMICRMW_NAND */
17097	type0, ptype1, type0,	17097	type0, ptype1, type0,
17098	/* G_ATOMICRMW_OR */	17098	/* G_ATOMICRMW_OR */
17099	type0, ptype1, type0,	17099	type0, ptype1, type0,
17100	/* G_ATOMICRMW_XOR */	17100	/* G_ATOMICRMW_XOR */
17101	type0, ptype1, type0,	17101	type0, ptype1, type0,
17102	/* G_ATOMICRMW_MAX */	17102	/* G_ATOMICRMW_MAX */
17103	type0, ptype1, type0,	17103	type0, ptype1, type0,
17104	/* G_ATOMICRMW_MIN */	17104	/* G_ATOMICRMW_MIN */
17105	type0, ptype1, type0,	17105	type0, ptype1, type0,
17106	/* G_ATOMICRMW_UMAX */	17106	/* G_ATOMICRMW_UMAX */
17107	type0, ptype1, type0,	17107	type0, ptype1, type0,
17108	/* G_ATOMICRMW_UMIN */	17108	/* G_ATOMICRMW_UMIN */
17109	type0, ptype1, type0,	17109	type0, ptype1, type0,
17110	/* G_ATOMICRMW_FADD */	17110	/* G_ATOMICRMW_FADD */
17111	type0, ptype1, type0,	17111	type0, ptype1, type0,
17112	/* G_ATOMICRMW_FSUB */	17112	/* G_ATOMICRMW_FSUB */
17113	type0, ptype1, type0,	17113	type0, ptype1, type0,
17114	/* G_ATOMICRMW_FMAX */	17114	/* G_ATOMICRMW_FMAX */
17115	type0, ptype1, type0,	17115	type0, ptype1, type0,
17116	/* G_ATOMICRMW_FMIN */	17116	/* G_ATOMICRMW_FMIN */
17117	type0, ptype1, type0,	17117	type0, ptype1, type0,
17118	/* G_ATOMICRMW_UINC_WRAP */	17118	/* G_ATOMICRMW_UINC_WRAP */
17119	type0, ptype1, type0,	17119	type0, ptype1, type0,
17120	/* G_ATOMICRMW_UDEC_WRAP */	17120	/* G_ATOMICRMW_UDEC_WRAP */
17121	type0, ptype1, type0,	17121	type0, ptype1, type0,
17122	/* G_FENCE */	17122	/* G_FENCE */
17123	i32imm, i32imm,	17123	i32imm, i32imm,
17124	/* G_BRCOND */	17124	/* G_BRCOND */
17125	type0, -1,	17125	type0, -1,
17126	/* G_BRINDIRECT */	17126	/* G_BRINDIRECT */
17127	type0,	17127	type0,
17128	/* G_INVOKE_REGION_START */	17128	/* G_INVOKE_REGION_START */
17129	/* G_INTRINSIC */	17129	/* G_INTRINSIC */
17130	-1,	17130	-1,
17131	/* G_INTRINSIC_W_SIDE_EFFECTS */	17131	/* G_INTRINSIC_W_SIDE_EFFECTS */
17132	-1,	17132	-1,
17133	/* G_ANYEXT */	17133	/* G_ANYEXT */
17134	type0, type1,	17134	type0, type1,
17135	/* G_TRUNC */	17135	/* G_TRUNC */
17136	type0, type1,	17136	type0, type1,
17137	/* G_CONSTANT */	17137	/* G_CONSTANT */
17138	type0, -1,	17138	type0, -1,
17139	/* G_FCONSTANT */	17139	/* G_FCONSTANT */
17140	type0, -1,	17140	type0, -1,
17141	/* G_VASTART */	17141	/* G_VASTART */
17142	type0,	17142	type0,
17143	/* G_VAARG */	17143	/* G_VAARG */
17144	type0, type1, -1,	17144	type0, type1, -1,
17145	/* G_SEXT */	17145	/* G_SEXT */
17146	type0, type1,	17146	type0, type1,
17147	/* G_SEXT_INREG */	17147	/* G_SEXT_INREG */
17148	type0, type0, untyped_imm_0,	17148	type0, type0, untyped_imm_0,
17149	/* G_ZEXT */	17149	/* G_ZEXT */
17150	type0, type1,	17150	type0, type1,
17151	/* G_SHL */	17151	/* G_SHL */
17152	type0, type0, type1,	17152	type0, type0, type1,
17153	/* G_LSHR */	17153	/* G_LSHR */
17154	type0, type0, type1,	17154	type0, type0, type1,
17155	/* G_ASHR */	17155	/* G_ASHR */
17156	type0, type0, type1,	17156	type0, type0, type1,
17157	/* G_FSHL */	17157	/* G_FSHL */
17158	type0, type0, type0, type1,	17158	type0, type0, type0, type1,
17159	/* G_FSHR */	17159	/* G_FSHR */
17160	type0, type0, type0, type1,	17160	type0, type0, type0, type1,
17161	/* G_ROTR */	17161	/* G_ROTR */
17162	type0, type0, type1,	17162	type0, type0, type1,
17163	/* G_ROTL */	17163	/* G_ROTL */
17164	type0, type0, type1,	17164	type0, type0, type1,
17165	/* G_ICMP */	17165	/* G_ICMP */
17166	type0, -1, type1, type1,	17166	type0, -1, type1, type1,
17167	/* G_FCMP */	17167	/* G_FCMP */
17168	type0, -1, type1, type1,	17168	type0, -1, type1, type1,
17169	/* G_SELECT */	17169	/* G_SELECT */
17170	type0, type1, type0, type0,	17170	type0, type1, type0, type0,
17171	/* G_UADDO */	17171	/* G_UADDO */
17172	type0, type1, type0, type0,	17172	type0, type1, type0, type0,
17173	/* G_UADDE */	17173	/* G_UADDE */
17174	type0, type1, type0, type0, type1,	17174	type0, type1, type0, type0, type1,
17175	/* G_USUBO */	17175	/* G_USUBO */
17176	type0, type1, type0, type0,	17176	type0, type1, type0, type0,
17177	/* G_USUBE */	17177	/* G_USUBE */
17178	type0, type1, type0, type0, type1,	17178	type0, type1, type0, type0, type1,
17179	/* G_SADDO */	17179	/* G_SADDO */
17180	type0, type1, type0, type0,	17180	type0, type1, type0, type0,
17181	/* G_SADDE */	17181	/* G_SADDE */
17182	type0, type1, type0, type0, type1,	17182	type0, type1, type0, type0, type1,
17183	/* G_SSUBO */	17183	/* G_SSUBO */
17184	type0, type1, type0, type0,	17184	type0, type1, type0, type0,
17185	/* G_SSUBE */	17185	/* G_SSUBE */
17186	type0, type1, type0, type0, type1,	17186	type0, type1, type0, type0, type1,
17187	/* G_UMULO */	17187	/* G_UMULO */
17188	type0, type1, type0, type0,	17188	type0, type1, type0, type0,
17189	/* G_SMULO */	17189	/* G_SMULO */
17190	type0, type1, type0, type0,	17190	type0, type1, type0, type0,
17191	/* G_UMULH */	17191	/* G_UMULH */
17192	type0, type0, type0,	17192	type0, type0, type0,
17193	/* G_SMULH */	17193	/* G_SMULH */
17194	type0, type0, type0,	17194	type0, type0, type0,
17195	/* G_UADDSAT */	17195	/* G_UADDSAT */
17196	type0, type0, type0,	17196	type0, type0, type0,
17197	/* G_SADDSAT */	17197	/* G_SADDSAT */
17198	type0, type0, type0,	17198	type0, type0, type0,
17199	/* G_USUBSAT */	17199	/* G_USUBSAT */
17200	type0, type0, type0,	17200	type0, type0, type0,
17201	/* G_SSUBSAT */	17201	/* G_SSUBSAT */
17202	type0, type0, type0,	17202	type0, type0, type0,
17203	/* G_USHLSAT */	17203	/* G_USHLSAT */
17204	type0, type0, type1,	17204	type0, type0, type1,
17205	/* G_SSHLSAT */	17205	/* G_SSHLSAT */
17206	type0, type0, type1,	17206	type0, type0, type1,
17207	/* G_SMULFIX */	17207	/* G_SMULFIX */
17208	type0, type0, type0, untyped_imm_0,	17208	type0, type0, type0, untyped_imm_0,
17209	/* G_UMULFIX */	17209	/* G_UMULFIX */
17210	type0, type0, type0, untyped_imm_0,	17210	type0, type0, type0, untyped_imm_0,
17211	/* G_SMULFIXSAT */	17211	/* G_SMULFIXSAT */
17212	type0, type0, type0, untyped_imm_0,	17212	type0, type0, type0, untyped_imm_0,
17213	/* G_UMULFIXSAT */	17213	/* G_UMULFIXSAT */
17214	type0, type0, type0, untyped_imm_0,	17214	type0, type0, type0, untyped_imm_0,
17215	/* G_SDIVFIX */	17215	/* G_SDIVFIX */
17216	type0, type0, type0, untyped_imm_0,	17216	type0, type0, type0, untyped_imm_0,
17217	/* G_UDIVFIX */	17217	/* G_UDIVFIX */
17218	type0, type0, type0, untyped_imm_0,	17218	type0, type0, type0, untyped_imm_0,
17219	/* G_SDIVFIXSAT */	17219	/* G_SDIVFIXSAT */
17220	type0, type0, type0, untyped_imm_0,	17220	type0, type0, type0, untyped_imm_0,
17221	/* G_UDIVFIXSAT */	17221	/* G_UDIVFIXSAT */
17222	type0, type0, type0, untyped_imm_0,	17222	type0, type0, type0, untyped_imm_0,
17223	/* G_FADD */	17223	/* G_FADD */
17224	type0, type0, type0,	17224	type0, type0, type0,
17225	/* G_FSUB */	17225	/* G_FSUB */
17226	type0, type0, type0,	17226	type0, type0, type0,
17227	/* G_FMUL */	17227	/* G_FMUL */
17228	type0, type0, type0,	17228	type0, type0, type0,
17229	/* G_FMA */	17229	/* G_FMA */
17230	type0, type0, type0, type0,	17230	type0, type0, type0, type0,
17231	/* G_FMAD */	17231	/* G_FMAD */
17232	type0, type0, type0, type0,	17232	type0, type0, type0, type0,
17233	/* G_FDIV */	17233	/* G_FDIV */
17234	type0, type0, type0,	17234	type0, type0, type0,
17235	/* G_FREM */	17235	/* G_FREM */
17236	type0, type0, type0,	17236	type0, type0, type0,
17237	/* G_FPOW */	17237	/* G_FPOW */
17238	type0, type0, type0,	17238	type0, type0, type0,
17239	/* G_FPOWI */	17239	/* G_FPOWI */
17240	type0, type0, type1,	17240	type0, type0, type1,
17241	/* G_FEXP */	17241	/* G_FEXP */
17242	type0, type0,	17242	type0, type0,
17243	/* G_FEXP2 */	17243	/* G_FEXP2 */
17244	type0, type0,	17244	type0, type0,
17245	/* G_FLOG */	17245	/* G_FLOG */
17246	type0, type0,	17246	type0, type0,
17247	/* G_FLOG2 */	17247	/* G_FLOG2 */
17248	type0, type0,	17248	type0, type0,
17249	/* G_FLOG10 */	17249	/* G_FLOG10 */
17250	type0, type0,	17250	type0, type0,
17251	/* G_FLDEXP */	17251	/* G_FLDEXP */
17252	type0, type0, type1,	17252	type0, type0, type1,
17253	/* G_FFREXP */	17253	/* G_FFREXP */
17254	type0, type1, type0,	17254	type0, type1, type0,
17255	/* G_FNEG */	17255	/* G_FNEG */
17256	type0, type0,	17256	type0, type0,
17257	/* G_FPEXT */	17257	/* G_FPEXT */
17258	type0, type1,	17258	type0, type1,
17259	/* G_FPTRUNC */	17259	/* G_FPTRUNC */
17260	type0, type1,	17260	type0, type1,
17261	/* G_FPTOSI */	17261	/* G_FPTOSI */
17262	type0, type1,	17262	type0, type1,
17263	/* G_FPTOUI */	17263	/* G_FPTOUI */
17264	type0, type1,	17264	type0, type1,
17265	/* G_SITOFP */	17265	/* G_SITOFP */
17266	type0, type1,	17266	type0, type1,
17267	/* G_UITOFP */	17267	/* G_UITOFP */
17268	type0, type1,	17268	type0, type1,
17269	/* G_FABS */	17269	/* G_FABS */
17270	type0, type0,	17270	type0, type0,
17271	/* G_FCOPYSIGN */	17271	/* G_FCOPYSIGN */
17272	type0, type0, type1,	17272	type0, type0, type1,
17273	/* G_IS_FPCLASS */	17273	/* G_IS_FPCLASS */
17274	type0, type1, -1,	17274	type0, type1, -1,
17275	/* G_FCANONICALIZE */	17275	/* G_FCANONICALIZE */
17276	type0, type0,	17276	type0, type0,
17277	/* G_FMINNUM */	17277	/* G_FMINNUM */
17278	type0, type0, type0,	17278	type0, type0, type0,
17279	/* G_FMAXNUM */	17279	/* G_FMAXNUM */
17280	type0, type0, type0,	17280	type0, type0, type0,
17281	/* G_FMINNUM_IEEE */	17281	/* G_FMINNUM_IEEE */
17282	type0, type0, type0,	17282	type0, type0, type0,
17283	/* G_FMAXNUM_IEEE */	17283	/* G_FMAXNUM_IEEE */
17284	type0, type0, type0,	17284	type0, type0, type0,
17285	/* G_FMINIMUM */	17285	/* G_FMINIMUM */
17286	type0, type0, type0,	17286	type0, type0, type0,
17287	/* G_FMAXIMUM */	17287	/* G_FMAXIMUM */
17288	type0, type0, type0,	17288	type0, type0, type0,
17289	/* G_PTR_ADD */	17289	/* G_PTR_ADD */
17290	ptype0, ptype0, type1,	17290	ptype0, ptype0, type1,
17291	/* G_PTRMASK */	17291	/* G_PTRMASK */
17292	ptype0, ptype0, type1,	17292	ptype0, ptype0, type1,
17293	/* G_SMIN */	17293	/* G_SMIN */
17294	type0, type0, type0,	17294	type0, type0, type0,
17295	/* G_SMAX */	17295	/* G_SMAX */
17296	type0, type0, type0,	17296	type0, type0, type0,
17297	/* G_UMIN */	17297	/* G_UMIN */
17298	type0, type0, type0,	17298	type0, type0, type0,
17299	/* G_UMAX */	17299	/* G_UMAX */
17300	type0, type0, type0,	17300	type0, type0, type0,
17301	/* G_ABS */	17301	/* G_ABS */
17302	type0, type0,	17302	type0, type0,
17303	/* G_LROUND */	17303	/* G_LROUND */
17304	type0, type1,	17304	type0, type1,
17305	/* G_LLROUND */	17305	/* G_LLROUND */
17306	type0, type1,	17306	type0, type1,
17307	/* G_BR */	17307	/* G_BR */
17308	-1,	17308	-1,
17309	/* G_BRJT */	17309	/* G_BRJT */
17310	ptype0, -1, type1,	17310	ptype0, -1, type1,
17311	/* G_INSERT_VECTOR_ELT */	17311	/* G_INSERT_VECTOR_ELT */
17312	type0, type0, type1, type2,	17312	type0, type0, type1, type2,
17313	/* G_EXTRACT_VECTOR_ELT */	17313	/* G_EXTRACT_VECTOR_ELT */
17314	type0, type1, type2,	17314	type0, type1, type2,
17315	/* G_SHUFFLE_VECTOR */	17315	/* G_SHUFFLE_VECTOR */
17316	type0, type1, type1, -1,	17316	type0, type1, type1, -1,
17317	/* G_CTTZ */	17317	/* G_CTTZ */
17318	type0, type1,	17318	type0, type1,
17319	/* G_CTTZ_ZERO_UNDEF */	17319	/* G_CTTZ_ZERO_UNDEF */
17320	type0, type1,	17320	type0, type1,
17321	/* G_CTLZ */	17321	/* G_CTLZ */
17322	type0, type1,	17322	type0, type1,
17323	/* G_CTLZ_ZERO_UNDEF */	17323	/* G_CTLZ_ZERO_UNDEF */
17324	type0, type1,	17324	type0, type1,
17325	/* G_CTPOP */	17325	/* G_CTPOP */
17326	type0, type1,	17326	type0, type1,
17327	/* G_BSWAP */	17327	/* G_BSWAP */
17328	type0, type0,	17328	type0, type0,
17329	/* G_BITREVERSE */	17329	/* G_BITREVERSE */
17330	type0, type0,	17330	type0, type0,
17331	/* G_FCEIL */	17331	/* G_FCEIL */
17332	type0, type0,	17332	type0, type0,
17333	/* G_FCOS */	17333	/* G_FCOS */
17334	type0, type0,	17334	type0, type0,
17335	/* G_FSIN */	17335	/* G_FSIN */
17336	type0, type0,	17336	type0, type0,
17337	/* G_FSQRT */	17337	/* G_FSQRT */
17338	type0, type0,	17338	type0, type0,
17339	/* G_FFLOOR */	17339	/* G_FFLOOR */
17340	type0, type0,	17340	type0, type0,
17341	/* G_FRINT */	17341	/* G_FRINT */
17342	type0, type0,	17342	type0, type0,
17343	/* G_FNEARBYINT */	17343	/* G_FNEARBYINT */
17344	type0, type0,	17344	type0, type0,
17345	/* G_ADDRSPACE_CAST */	17345	/* G_ADDRSPACE_CAST */
17346	type0, type1,	17346	type0, type1,
17347	/* G_BLOCK_ADDR */	17347	/* G_BLOCK_ADDR */
17348	type0, -1,	17348	type0, -1,
17349	/* G_JUMP_TABLE */	17349	/* G_JUMP_TABLE */
17350	type0, -1,	17350	type0, -1,
17351	/* G_DYN_STACKALLOC */	17351	/* G_DYN_STACKALLOC */
17352	ptype0, type1, i32imm,	17352	ptype0, type1, i32imm,
17353	/* G_STRICT_FADD */	17353	/* G_STRICT_FADD */
17354	type0, type0, type0,	17354	type0, type0, type0,
17355	/* G_STRICT_FSUB */	17355	/* G_STRICT_FSUB */
17356	type0, type0, type0,	17356	type0, type0, type0,
17357	/* G_STRICT_FMUL */	17357	/* G_STRICT_FMUL */
17358	type0, type0, type0,	17358	type0, type0, type0,
17359	/* G_STRICT_FDIV */	17359	/* G_STRICT_FDIV */
17360	type0, type0, type0,	17360	type0, type0, type0,
17361	/* G_STRICT_FREM */	17361	/* G_STRICT_FREM */
17362	type0, type0, type0,	17362	type0, type0, type0,
17363	/* G_STRICT_FMA */	17363	/* G_STRICT_FMA */
17364	type0, type0, type0, type0,	17364	type0, type0, type0, type0,
17365	/* G_STRICT_FSQRT */	17365	/* G_STRICT_FSQRT */
17366	type0, type0,	17366	type0, type0,
17367	/* G_STRICT_FLDEXP */	17367	/* G_STRICT_FLDEXP */
17368	type0, type0, type1,	17368	type0, type0, type1,
17369	/* G_READ_REGISTER */	17369	/* G_READ_REGISTER */
17370	type0, -1,	17370	type0, -1,
17371	/* G_WRITE_REGISTER */	17371	/* G_WRITE_REGISTER */
17372	-1, type0,	17372	-1, type0,
17373	/* G_MEMCPY */	17373	/* G_MEMCPY */
17374	ptype0, ptype1, type2, untyped_imm_0,	17374	ptype0, ptype1, type2, untyped_imm_0,
17375	/* G_MEMCPY_INLINE */	17375	/* G_MEMCPY_INLINE */
17376	ptype0, ptype1, type2,	17376	ptype0, ptype1, type2,
17377	/* G_MEMMOVE */	17377	/* G_MEMMOVE */
17378	ptype0, ptype1, type2, untyped_imm_0,	17378	ptype0, ptype1, type2, untyped_imm_0,
17379	/* G_MEMSET */	17379	/* G_MEMSET */
17380	ptype0, type1, type2, untyped_imm_0,	17380	ptype0, type1, type2, untyped_imm_0,
17381	/* G_BZERO */	17381	/* G_BZERO */
17382	ptype0, type1, untyped_imm_0,	17382	ptype0, type1, untyped_imm_0,
17383	/* G_VECREDUCE_SEQ_FADD */	17383	/* G_VECREDUCE_SEQ_FADD */
17384	type0, type1, type2,	17384	type0, type1, type2,
17385	/* G_VECREDUCE_SEQ_FMUL */	17385	/* G_VECREDUCE_SEQ_FMUL */
17386	type0, type1, type2,	17386	type0, type1, type2,
17387	/* G_VECREDUCE_FADD */	17387	/* G_VECREDUCE_FADD */
17388	type0, type1,	17388	type0, type1,
17389	/* G_VECREDUCE_FMUL */	17389	/* G_VECREDUCE_FMUL */
17390	type0, type1,	17390	type0, type1,
17391	/* G_VECREDUCE_FMAX */	17391	/* G_VECREDUCE_FMAX */
17392	type0, type1,	17392	type0, type1,
17393	/* G_VECREDUCE_FMIN */	17393	/* G_VECREDUCE_FMIN */
17394	type0, type1,	17394	type0, type1,
17395	/* G_VECREDUCE_ADD */	17395	/* G_VECREDUCE_ADD */
17396	type0, type1,	17396	type0, type1,
17397	/* G_VECREDUCE_MUL */	17397	/* G_VECREDUCE_MUL */
17398	type0, type1,	17398	type0, type1,
17399	/* G_VECREDUCE_AND */	17399	/* G_VECREDUCE_AND */
17400	type0, type1,	17400	type0, type1,
17401	/* G_VECREDUCE_OR */	17401	/* G_VECREDUCE_OR */
17402	type0, type1,	17402	type0, type1,
17403	/* G_VECREDUCE_XOR */	17403	/* G_VECREDUCE_XOR */
17404	type0, type1,	17404	type0, type1,
17405	/* G_VECREDUCE_SMAX */	17405	/* G_VECREDUCE_SMAX */
17406	type0, type1,	17406	type0, type1,
17407	/* G_VECREDUCE_SMIN */	17407	/* G_VECREDUCE_SMIN */
17408	type0, type1,	17408	type0, type1,
17409	/* G_VECREDUCE_UMAX */	17409	/* G_VECREDUCE_UMAX */
17410	type0, type1,	17410	type0, type1,
17411	/* G_VECREDUCE_UMIN */	17411	/* G_VECREDUCE_UMIN */
17412	type0, type1,	17412	type0, type1,
17413	/* G_SBFX */	17413	/* G_SBFX */
17414	type0, type0, type1, type1,	17414	type0, type0, type1, type1,
17415	/* G_UBFX */	17415	/* G_UBFX */
17416	type0, type0, type1, type1,	17416	type0, type0, type1, type1,
17417	/* ABSMacro */	17417	/* ABSMacro */
17418	GPR32Opnd, GPR32Opnd,	17418	GPR32Opnd, GPR32Opnd,
17419	/* ADJCALLSTACKDOWN */	17419	/* ADJCALLSTACKDOWN */
17420	i32imm, i32imm,	17420	i32imm, i32imm,
17421	/* ADJCALLSTACKUP */	17421	/* ADJCALLSTACKUP */
17422	i32imm, i32imm,	17422	i32imm, i32imm,
17423	/* AND_V_D_PSEUDO */	17423	/* AND_V_D_PSEUDO */
17424	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	17424	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17425	/* AND_V_H_PSEUDO */	17425	/* AND_V_H_PSEUDO */
17426	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	17426	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17427	/* AND_V_W_PSEUDO */	17427	/* AND_V_W_PSEUDO */
17428	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	17428	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17429	/* ATOMIC_CMP_SWAP_I16 */	17429	/* ATOMIC_CMP_SWAP_I16 */
17430	GPR32, -1, GPR32, GPR32,	17430	GPR32, -1, GPR32, GPR32,
17431	/* ATOMIC_CMP_SWAP_I16_POSTRA */	17431	/* ATOMIC_CMP_SWAP_I16_POSTRA */
17432	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	17432	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,
17433	/* ATOMIC_CMP_SWAP_I32 */	17433	/* ATOMIC_CMP_SWAP_I32 */
17434	GPR32, -1, GPR32, GPR32,	17434	GPR32, -1, GPR32, GPR32,
17435	/* ATOMIC_CMP_SWAP_I32_POSTRA */	17435	/* ATOMIC_CMP_SWAP_I32_POSTRA */
17436	GPR32, -1, GPR32, GPR32,	17436	GPR32, -1, GPR32, GPR32,
17437	/* ATOMIC_CMP_SWAP_I64 */	17437	/* ATOMIC_CMP_SWAP_I64 */
17438	GPR64, -1, GPR64, GPR64,	17438	GPR64, -1, GPR64, GPR64,
17439	/* ATOMIC_CMP_SWAP_I64_POSTRA */	17439	/* ATOMIC_CMP_SWAP_I64_POSTRA */
17440	GPR64, -1, GPR64, GPR64,	17440	GPR64, -1, GPR64, GPR64,
17441	/* ATOMIC_CMP_SWAP_I8 */	17441	/* ATOMIC_CMP_SWAP_I8 */
17442	GPR32, -1, GPR32, GPR32,	17442	GPR32, -1, GPR32, GPR32,
17443	/* ATOMIC_CMP_SWAP_I8_POSTRA */	17443	/* ATOMIC_CMP_SWAP_I8_POSTRA */
17444	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	17444	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,
17445	/* ATOMIC_LOAD_ADD_I16 */	17445	/* ATOMIC_LOAD_ADD_I16 */
17446	GPR32, -1, GPR32,	17446	GPR32, -1, GPR32,
17447	/* ATOMIC_LOAD_ADD_I16_POSTRA */	17447	/* ATOMIC_LOAD_ADD_I16_POSTRA */
17448	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17448	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17449	/* ATOMIC_LOAD_ADD_I32 */	17449	/* ATOMIC_LOAD_ADD_I32 */
17450	GPR32, -1, GPR32,	17450	GPR32, -1, GPR32,
17451	/* ATOMIC_LOAD_ADD_I32_POSTRA */	17451	/* ATOMIC_LOAD_ADD_I32_POSTRA */
17452	GPR32, -1, GPR32,	17452	GPR32, -1, GPR32,
17453	/* ATOMIC_LOAD_ADD_I64 */	17453	/* ATOMIC_LOAD_ADD_I64 */
17454	GPR64, -1, GPR64,	17454	GPR64, -1, GPR64,
17455	/* ATOMIC_LOAD_ADD_I64_POSTRA */	17455	/* ATOMIC_LOAD_ADD_I64_POSTRA */
17456	GPR64, -1, GPR64,	17456	GPR64, -1, GPR64,
17457	/* ATOMIC_LOAD_ADD_I8 */	17457	/* ATOMIC_LOAD_ADD_I8 */
17458	GPR32, -1, GPR32,	17458	GPR32, -1, GPR32,
17459	/* ATOMIC_LOAD_ADD_I8_POSTRA */	17459	/* ATOMIC_LOAD_ADD_I8_POSTRA */
17460	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17460	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17461	/* ATOMIC_LOAD_AND_I16 */	17461	/* ATOMIC_LOAD_AND_I16 */
17462	GPR32, -1, GPR32,	17462	GPR32, -1, GPR32,
17463	/* ATOMIC_LOAD_AND_I16_POSTRA */	17463	/* ATOMIC_LOAD_AND_I16_POSTRA */
17464	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17464	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17465	/* ATOMIC_LOAD_AND_I32 */	17465	/* ATOMIC_LOAD_AND_I32 */
17466	GPR32, -1, GPR32,	17466	GPR32, -1, GPR32,
17467	/* ATOMIC_LOAD_AND_I32_POSTRA */	17467	/* ATOMIC_LOAD_AND_I32_POSTRA */
17468	GPR32, -1, GPR32,	17468	GPR32, -1, GPR32,
17469	/* ATOMIC_LOAD_AND_I64 */	17469	/* ATOMIC_LOAD_AND_I64 */
17470	GPR64, -1, GPR64,	17470	GPR64, -1, GPR64,
17471	/* ATOMIC_LOAD_AND_I64_POSTRA */	17471	/* ATOMIC_LOAD_AND_I64_POSTRA */
17472	GPR64, -1, GPR64,	17472	GPR64, -1, GPR64,
17473	/* ATOMIC_LOAD_AND_I8 */	17473	/* ATOMIC_LOAD_AND_I8 */
17474	GPR32, -1, GPR32,	17474	GPR32, -1, GPR32,
17475	/* ATOMIC_LOAD_AND_I8_POSTRA */	17475	/* ATOMIC_LOAD_AND_I8_POSTRA */
17476	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17476	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17477	/* ATOMIC_LOAD_MAX_I16 */	17477	/* ATOMIC_LOAD_MAX_I16 */
17478	GPR32, -1, GPR32,	17478	GPR32, -1, GPR32,
17479	/* ATOMIC_LOAD_MAX_I16_POSTRA */	17479	/* ATOMIC_LOAD_MAX_I16_POSTRA */
17480	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17480	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17481	/* ATOMIC_LOAD_MAX_I32 */	17481	/* ATOMIC_LOAD_MAX_I32 */
17482	GPR32, -1, GPR32,	17482	GPR32, -1, GPR32,
17483	/* ATOMIC_LOAD_MAX_I32_POSTRA */	17483	/* ATOMIC_LOAD_MAX_I32_POSTRA */
17484	GPR32, -1, GPR32,	17484	GPR32, -1, GPR32,
17485	/* ATOMIC_LOAD_MAX_I64 */	17485	/* ATOMIC_LOAD_MAX_I64 */
17486	GPR64, -1, GPR64,	17486	GPR64, -1, GPR64,
17487	/* ATOMIC_LOAD_MAX_I64_POSTRA */	17487	/* ATOMIC_LOAD_MAX_I64_POSTRA */
17488	GPR64, -1, GPR64,	17488	GPR64, -1, GPR64,
17489	/* ATOMIC_LOAD_MAX_I8 */	17489	/* ATOMIC_LOAD_MAX_I8 */
17490	GPR32, -1, GPR32,	17490	GPR32, -1, GPR32,
17491	/* ATOMIC_LOAD_MAX_I8_POSTRA */	17491	/* ATOMIC_LOAD_MAX_I8_POSTRA */
17492	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17492	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17493	/* ATOMIC_LOAD_MIN_I16 */	17493	/* ATOMIC_LOAD_MIN_I16 */
17494	GPR32, -1, GPR32,	17494	GPR32, -1, GPR32,
17495	/* ATOMIC_LOAD_MIN_I16_POSTRA */	17495	/* ATOMIC_LOAD_MIN_I16_POSTRA */
17496	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17496	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17497	/* ATOMIC_LOAD_MIN_I32 */	17497	/* ATOMIC_LOAD_MIN_I32 */
17498	GPR32, -1, GPR32,	17498	GPR32, -1, GPR32,
17499	/* ATOMIC_LOAD_MIN_I32_POSTRA */	17499	/* ATOMIC_LOAD_MIN_I32_POSTRA */
17500	GPR32, -1, GPR32,	17500	GPR32, -1, GPR32,
17501	/* ATOMIC_LOAD_MIN_I64 */	17501	/* ATOMIC_LOAD_MIN_I64 */
17502	GPR64, -1, GPR64,	17502	GPR64, -1, GPR64,
17503	/* ATOMIC_LOAD_MIN_I64_POSTRA */	17503	/* ATOMIC_LOAD_MIN_I64_POSTRA */
17504	GPR64, -1, GPR64,	17504	GPR64, -1, GPR64,
17505	/* ATOMIC_LOAD_MIN_I8 */	17505	/* ATOMIC_LOAD_MIN_I8 */
17506	GPR32, -1, GPR32,	17506	GPR32, -1, GPR32,
17507	/* ATOMIC_LOAD_MIN_I8_POSTRA */	17507	/* ATOMIC_LOAD_MIN_I8_POSTRA */
17508	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17508	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17509	/* ATOMIC_LOAD_NAND_I16 */	17509	/* ATOMIC_LOAD_NAND_I16 */
17510	GPR32, -1, GPR32,	17510	GPR32, -1, GPR32,
17511	/* ATOMIC_LOAD_NAND_I16_POSTRA */	17511	/* ATOMIC_LOAD_NAND_I16_POSTRA */
17512	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17512	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17513	/* ATOMIC_LOAD_NAND_I32 */	17513	/* ATOMIC_LOAD_NAND_I32 */
17514	GPR32, -1, GPR32,	17514	GPR32, -1, GPR32,
17515	/* ATOMIC_LOAD_NAND_I32_POSTRA */	17515	/* ATOMIC_LOAD_NAND_I32_POSTRA */
17516	GPR32, -1, GPR32,	17516	GPR32, -1, GPR32,
17517	/* ATOMIC_LOAD_NAND_I64 */	17517	/* ATOMIC_LOAD_NAND_I64 */
17518	GPR64, -1, GPR64,	17518	GPR64, -1, GPR64,
17519	/* ATOMIC_LOAD_NAND_I64_POSTRA */	17519	/* ATOMIC_LOAD_NAND_I64_POSTRA */
17520	GPR64, -1, GPR64,	17520	GPR64, -1, GPR64,
17521	/* ATOMIC_LOAD_NAND_I8 */	17521	/* ATOMIC_LOAD_NAND_I8 */
17522	GPR32, -1, GPR32,	17522	GPR32, -1, GPR32,
17523	/* ATOMIC_LOAD_NAND_I8_POSTRA */	17523	/* ATOMIC_LOAD_NAND_I8_POSTRA */
17524	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17524	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17525	/* ATOMIC_LOAD_OR_I16 */	17525	/* ATOMIC_LOAD_OR_I16 */
17526	GPR32, -1, GPR32,	17526	GPR32, -1, GPR32,
17527	/* ATOMIC_LOAD_OR_I16_POSTRA */	17527	/* ATOMIC_LOAD_OR_I16_POSTRA */
17528	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17528	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17529	/* ATOMIC_LOAD_OR_I32 */	17529	/* ATOMIC_LOAD_OR_I32 */
17530	GPR32, -1, GPR32,	17530	GPR32, -1, GPR32,
17531	/* ATOMIC_LOAD_OR_I32_POSTRA */	17531	/* ATOMIC_LOAD_OR_I32_POSTRA */
17532	GPR32, -1, GPR32,	17532	GPR32, -1, GPR32,
17533	/* ATOMIC_LOAD_OR_I64 */	17533	/* ATOMIC_LOAD_OR_I64 */
17534	GPR64, -1, GPR64,	17534	GPR64, -1, GPR64,
17535	/* ATOMIC_LOAD_OR_I64_POSTRA */	17535	/* ATOMIC_LOAD_OR_I64_POSTRA */
17536	GPR64, -1, GPR64,	17536	GPR64, -1, GPR64,
17537	/* ATOMIC_LOAD_OR_I8 */	17537	/* ATOMIC_LOAD_OR_I8 */
17538	GPR32, -1, GPR32,	17538	GPR32, -1, GPR32,
17539	/* ATOMIC_LOAD_OR_I8_POSTRA */	17539	/* ATOMIC_LOAD_OR_I8_POSTRA */
17540	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17540	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17541	/* ATOMIC_LOAD_SUB_I16 */	17541	/* ATOMIC_LOAD_SUB_I16 */
17542	GPR32, -1, GPR32,	17542	GPR32, -1, GPR32,
17543	/* ATOMIC_LOAD_SUB_I16_POSTRA */	17543	/* ATOMIC_LOAD_SUB_I16_POSTRA */
17544	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17544	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17545	/* ATOMIC_LOAD_SUB_I32 */	17545	/* ATOMIC_LOAD_SUB_I32 */
17546	GPR32, -1, GPR32,	17546	GPR32, -1, GPR32,
17547	/* ATOMIC_LOAD_SUB_I32_POSTRA */	17547	/* ATOMIC_LOAD_SUB_I32_POSTRA */
17548	GPR32, -1, GPR32,	17548	GPR32, -1, GPR32,
17549	/* ATOMIC_LOAD_SUB_I64 */	17549	/* ATOMIC_LOAD_SUB_I64 */
17550	GPR64, -1, GPR64,	17550	GPR64, -1, GPR64,
17551	/* ATOMIC_LOAD_SUB_I64_POSTRA */	17551	/* ATOMIC_LOAD_SUB_I64_POSTRA */
17552	GPR64, -1, GPR64,	17552	GPR64, -1, GPR64,
17553	/* ATOMIC_LOAD_SUB_I8 */	17553	/* ATOMIC_LOAD_SUB_I8 */
17554	GPR32, -1, GPR32,	17554	GPR32, -1, GPR32,
17555	/* ATOMIC_LOAD_SUB_I8_POSTRA */	17555	/* ATOMIC_LOAD_SUB_I8_POSTRA */
17556	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17556	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17557	/* ATOMIC_LOAD_UMAX_I16 */	17557	/* ATOMIC_LOAD_UMAX_I16 */
17558	GPR32, -1, GPR32,	17558	GPR32, -1, GPR32,
17559	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	17559	/* ATOMIC_LOAD_UMAX_I16_POSTRA */
17560	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17560	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17561	/* ATOMIC_LOAD_UMAX_I32 */	17561	/* ATOMIC_LOAD_UMAX_I32 */
17562	GPR32, -1, GPR32,	17562	GPR32, -1, GPR32,
17563	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	17563	/* ATOMIC_LOAD_UMAX_I32_POSTRA */
17564	GPR32, -1, GPR32,	17564	GPR32, -1, GPR32,
17565	/* ATOMIC_LOAD_UMAX_I64 */	17565	/* ATOMIC_LOAD_UMAX_I64 */
17566	GPR64, -1, GPR64,	17566	GPR64, -1, GPR64,
17567	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	17567	/* ATOMIC_LOAD_UMAX_I64_POSTRA */
17568	GPR64, -1, GPR64,	17568	GPR64, -1, GPR64,
17569	/* ATOMIC_LOAD_UMAX_I8 */	17569	/* ATOMIC_LOAD_UMAX_I8 */
17570	GPR32, -1, GPR32,	17570	GPR32, -1, GPR32,
17571	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	17571	/* ATOMIC_LOAD_UMAX_I8_POSTRA */
17572	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17572	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17573	/* ATOMIC_LOAD_UMIN_I16 */	17573	/* ATOMIC_LOAD_UMIN_I16 */
17574	GPR32, -1, GPR32,	17574	GPR32, -1, GPR32,
17575	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	17575	/* ATOMIC_LOAD_UMIN_I16_POSTRA */
17576	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17576	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17577	/* ATOMIC_LOAD_UMIN_I32 */	17577	/* ATOMIC_LOAD_UMIN_I32 */
17578	GPR32, -1, GPR32,	17578	GPR32, -1, GPR32,
17579	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	17579	/* ATOMIC_LOAD_UMIN_I32_POSTRA */
17580	GPR32, -1, GPR32,	17580	GPR32, -1, GPR32,
17581	/* ATOMIC_LOAD_UMIN_I64 */	17581	/* ATOMIC_LOAD_UMIN_I64 */
17582	GPR64, -1, GPR64,	17582	GPR64, -1, GPR64,
17583	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	17583	/* ATOMIC_LOAD_UMIN_I64_POSTRA */
17584	GPR64, -1, GPR64,	17584	GPR64, -1, GPR64,
17585	/* ATOMIC_LOAD_UMIN_I8 */	17585	/* ATOMIC_LOAD_UMIN_I8 */
17586	GPR32, -1, GPR32,	17586	GPR32, -1, GPR32,
17587	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	17587	/* ATOMIC_LOAD_UMIN_I8_POSTRA */
17588	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17588	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17589	/* ATOMIC_LOAD_XOR_I16 */	17589	/* ATOMIC_LOAD_XOR_I16 */
17590	GPR32, -1, GPR32,	17590	GPR32, -1, GPR32,
17591	/* ATOMIC_LOAD_XOR_I16_POSTRA */	17591	/* ATOMIC_LOAD_XOR_I16_POSTRA */
17592	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17592	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17593	/* ATOMIC_LOAD_XOR_I32 */	17593	/* ATOMIC_LOAD_XOR_I32 */
17594	GPR32, -1, GPR32,	17594	GPR32, -1, GPR32,
17595	/* ATOMIC_LOAD_XOR_I32_POSTRA */	17595	/* ATOMIC_LOAD_XOR_I32_POSTRA */
17596	GPR32, -1, GPR32,	17596	GPR32, -1, GPR32,
17597	/* ATOMIC_LOAD_XOR_I64 */	17597	/* ATOMIC_LOAD_XOR_I64 */
17598	GPR64, -1, GPR64,	17598	GPR64, -1, GPR64,
17599	/* ATOMIC_LOAD_XOR_I64_POSTRA */	17599	/* ATOMIC_LOAD_XOR_I64_POSTRA */
17600	GPR64, -1, GPR64,	17600	GPR64, -1, GPR64,
17601	/* ATOMIC_LOAD_XOR_I8 */	17601	/* ATOMIC_LOAD_XOR_I8 */
17602	GPR32, -1, GPR32,	17602	GPR32, -1, GPR32,
17603	/* ATOMIC_LOAD_XOR_I8_POSTRA */	17603	/* ATOMIC_LOAD_XOR_I8_POSTRA */
17604	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17604	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17605	/* ATOMIC_SWAP_I16 */	17605	/* ATOMIC_SWAP_I16 */
17606	GPR32, -1, GPR32,	17606	GPR32, -1, GPR32,
17607	/* ATOMIC_SWAP_I16_POSTRA */	17607	/* ATOMIC_SWAP_I16_POSTRA */
17608	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17608	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17609	/* ATOMIC_SWAP_I32 */	17609	/* ATOMIC_SWAP_I32 */
17610	GPR32, -1, GPR32,	17610	GPR32, -1, GPR32,
17611	/* ATOMIC_SWAP_I32_POSTRA */	17611	/* ATOMIC_SWAP_I32_POSTRA */
17612	GPR32, -1, GPR32,	17612	GPR32, -1, GPR32,
17613	/* ATOMIC_SWAP_I64 */	17613	/* ATOMIC_SWAP_I64 */
17614	GPR64, -1, GPR64,	17614	GPR64, -1, GPR64,
17615	/* ATOMIC_SWAP_I64_POSTRA */	17615	/* ATOMIC_SWAP_I64_POSTRA */
17616	GPR64, -1, GPR64,	17616	GPR64, -1, GPR64,
17617	/* ATOMIC_SWAP_I8 */	17617	/* ATOMIC_SWAP_I8 */
17618	GPR32, -1, GPR32,	17618	GPR32, -1, GPR32,
17619	/* ATOMIC_SWAP_I8_POSTRA */	17619	/* ATOMIC_SWAP_I8_POSTRA */
17620	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	17620	GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17621	/* B */	17621	/* B */
17622	brtarget,	17622	brtarget,
17623	/* BAL_BR */	17623	/* BAL_BR */
17624	brtarget,	17624	brtarget,
17625	/* BAL_BR_MM */	17625	/* BAL_BR_MM */
17626	brtarget_mm,	17626	brtarget_mm,
17627	/* BEQLImmMacro */	17627	/* BEQLImmMacro */
17628	GPR32Opnd, imm64, brtarget,	17628	GPR32Opnd, imm64, brtarget,
17629	/* BGE */	17629	/* BGE */
17630	GPR32Opnd, GPR32Opnd, brtarget,	17630	GPR32Opnd, GPR32Opnd, brtarget,
17631	/* BGEImmMacro */	17631	/* BGEImmMacro */
17632	GPR32Opnd, imm64, brtarget,	17632	GPR32Opnd, imm64, brtarget,
17633	/* BGEL */	17633	/* BGEL */
17634	GPR32Opnd, GPR32Opnd, brtarget,	17634	GPR32Opnd, GPR32Opnd, brtarget,
17635	/* BGELImmMacro */	17635	/* BGELImmMacro */
17636	GPR32Opnd, imm64, brtarget,	17636	GPR32Opnd, imm64, brtarget,
17637	/* BGEU */	17637	/* BGEU */
17638	GPR32Opnd, GPR32Opnd, brtarget,	17638	GPR32Opnd, GPR32Opnd, brtarget,
17639	/* BGEUImmMacro */	17639	/* BGEUImmMacro */
17640	GPR32Opnd, imm64, brtarget,	17640	GPR32Opnd, imm64, brtarget,
17641	/* BGEUL */	17641	/* BGEUL */
17642	GPR32Opnd, GPR32Opnd, brtarget,	17642	GPR32Opnd, GPR32Opnd, brtarget,
17643	/* BGEULImmMacro */	17643	/* BGEULImmMacro */
17644	GPR32Opnd, imm64, brtarget,	17644	GPR32Opnd, imm64, brtarget,
17645	/* BGT */	17645	/* BGT */
17646	GPR32Opnd, GPR32Opnd, brtarget,	17646	GPR32Opnd, GPR32Opnd, brtarget,
17647	/* BGTImmMacro */	17647	/* BGTImmMacro */
17648	GPR32Opnd, imm64, brtarget,	17648	GPR32Opnd, imm64, brtarget,
17649	/* BGTL */	17649	/* BGTL */
17650	GPR32Opnd, GPR32Opnd, brtarget,	17650	GPR32Opnd, GPR32Opnd, brtarget,
17651	/* BGTLImmMacro */	17651	/* BGTLImmMacro */
17652	GPR32Opnd, imm64, brtarget,	17652	GPR32Opnd, imm64, brtarget,
17653	/* BGTU */	17653	/* BGTU */
17654	GPR32Opnd, GPR32Opnd, brtarget,	17654	GPR32Opnd, GPR32Opnd, brtarget,
17655	/* BGTUImmMacro */	17655	/* BGTUImmMacro */
17656	GPR32Opnd, imm64, brtarget,	17656	GPR32Opnd, imm64, brtarget,
17657	/* BGTUL */	17657	/* BGTUL */
17658	GPR32Opnd, GPR32Opnd, brtarget,	17658	GPR32Opnd, GPR32Opnd, brtarget,
17659	/* BGTULImmMacro */	17659	/* BGTULImmMacro */
17660	GPR32Opnd, imm64, brtarget,	17660	GPR32Opnd, imm64, brtarget,
17661	/* BLE */	17661	/* BLE */
17662	GPR32Opnd, GPR32Opnd, brtarget,	17662	GPR32Opnd, GPR32Opnd, brtarget,
17663	/* BLEImmMacro */	17663	/* BLEImmMacro */
17664	GPR32Opnd, imm64, brtarget,	17664	GPR32Opnd, imm64, brtarget,
17665	/* BLEL */	17665	/* BLEL */
17666	GPR32Opnd, GPR32Opnd, brtarget,	17666	GPR32Opnd, GPR32Opnd, brtarget,
17667	/* BLELImmMacro */	17667	/* BLELImmMacro */
17668	GPR32Opnd, imm64, brtarget,	17668	GPR32Opnd, imm64, brtarget,
17669	/* BLEU */	17669	/* BLEU */
17670	GPR32Opnd, GPR32Opnd, brtarget,	17670	GPR32Opnd, GPR32Opnd, brtarget,
17671	/* BLEUImmMacro */	17671	/* BLEUImmMacro */
17672	GPR32Opnd, imm64, brtarget,	17672	GPR32Opnd, imm64, brtarget,
17673	/* BLEUL */	17673	/* BLEUL */
17674	GPR32Opnd, GPR32Opnd, brtarget,	17674	GPR32Opnd, GPR32Opnd, brtarget,
17675	/* BLEULImmMacro */	17675	/* BLEULImmMacro */
17676	GPR32Opnd, imm64, brtarget,	17676	GPR32Opnd, imm64, brtarget,
17677	/* BLT */	17677	/* BLT */
17678	GPR32Opnd, GPR32Opnd, brtarget,	17678	GPR32Opnd, GPR32Opnd, brtarget,
17679	/* BLTImmMacro */	17679	/* BLTImmMacro */
17680	GPR32Opnd, imm64, brtarget,	17680	GPR32Opnd, imm64, brtarget,
17681	/* BLTL */	17681	/* BLTL */
17682	GPR32Opnd, GPR32Opnd, brtarget,	17682	GPR32Opnd, GPR32Opnd, brtarget,
17683	/* BLTLImmMacro */	17683	/* BLTLImmMacro */
17684	GPR32Opnd, imm64, brtarget,	17684	GPR32Opnd, imm64, brtarget,
17685	/* BLTU */	17685	/* BLTU */
17686	GPR32Opnd, GPR32Opnd, brtarget,	17686	GPR32Opnd, GPR32Opnd, brtarget,
17687	/* BLTUImmMacro */	17687	/* BLTUImmMacro */
17688	GPR32Opnd, imm64, brtarget,	17688	GPR32Opnd, imm64, brtarget,
17689	/* BLTUL */	17689	/* BLTUL */
17690	GPR32Opnd, GPR32Opnd, brtarget,	17690	GPR32Opnd, GPR32Opnd, brtarget,
17691	/* BLTULImmMacro */	17691	/* BLTULImmMacro */
17692	GPR32Opnd, imm64, brtarget,	17692	GPR32Opnd, imm64, brtarget,
17693	/* BNELImmMacro */	17693	/* BNELImmMacro */
17694	GPR32Opnd, imm64, brtarget,	17694	GPR32Opnd, imm64, brtarget,
17695	/* BPOSGE32_PSEUDO */	17695	/* BPOSGE32_PSEUDO */
17696	GPR32Opnd,	17696	GPR32Opnd,
17697	/* BSEL_D_PSEUDO */	17697	/* BSEL_D_PSEUDO */
17698	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	17698	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17699	/* BSEL_FD_PSEUDO */	17699	/* BSEL_FD_PSEUDO */
17700	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	17700	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17701	/* BSEL_FW_PSEUDO */	17701	/* BSEL_FW_PSEUDO */
17702	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	17702	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17703	/* BSEL_H_PSEUDO */	17703	/* BSEL_H_PSEUDO */
17704	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	17704	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17705	/* BSEL_W_PSEUDO */	17705	/* BSEL_W_PSEUDO */
17706	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	17706	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17707	/* B_MM */	17707	/* B_MM */
17708	brtarget,	17708	brtarget,
17709	/* B_MMR6_Pseudo */	17709	/* B_MMR6_Pseudo */
17710	brtarget_mm,	17710	brtarget_mm,
17711	/* B_MM_Pseudo */	17711	/* B_MM_Pseudo */
17712	brtarget_mm,	17712	brtarget_mm,
17713	/* BeqImm */	17713	/* BeqImm */
17714	GPR32Opnd, imm64, brtarget,	17714	GPR32Opnd, imm64, brtarget,
17715	/* BneImm */	17715	/* BneImm */
17716	GPR32Opnd, imm64, brtarget,	17716	GPR32Opnd, imm64, brtarget,
17717	/* BteqzT8CmpX16 */	17717	/* BteqzT8CmpX16 */
17718	CPU16Regs, CPU16Regs, brtarget,	17718	CPU16Regs, CPU16Regs, brtarget,
17719	/* BteqzT8CmpiX16 */	17719	/* BteqzT8CmpiX16 */
17720	CPU16Regs, simm16, brtarget,	17720	CPU16Regs, simm16, brtarget,
17721	/* BteqzT8SltX16 */	17721	/* BteqzT8SltX16 */
17722	CPU16Regs, CPU16Regs, brtarget,	17722	CPU16Regs, CPU16Regs, brtarget,
17723	/* BteqzT8SltiX16 */	17723	/* BteqzT8SltiX16 */
17724	CPU16Regs, simm16, brtarget,	17724	CPU16Regs, simm16, brtarget,
17725	/* BteqzT8SltiuX16 */	17725	/* BteqzT8SltiuX16 */
17726	CPU16Regs, simm16, brtarget,	17726	CPU16Regs, simm16, brtarget,
17727	/* BteqzT8SltuX16 */	17727	/* BteqzT8SltuX16 */
17728	CPU16Regs, CPU16Regs, brtarget,	17728	CPU16Regs, CPU16Regs, brtarget,
17729	/* BtnezT8CmpX16 */	17729	/* BtnezT8CmpX16 */
17730	CPU16Regs, CPU16Regs, brtarget,	17730	CPU16Regs, CPU16Regs, brtarget,
17731	/* BtnezT8CmpiX16 */	17731	/* BtnezT8CmpiX16 */
17732	CPU16Regs, simm16, brtarget,	17732	CPU16Regs, simm16, brtarget,
17733	/* BtnezT8SltX16 */	17733	/* BtnezT8SltX16 */
17734	CPU16Regs, CPU16Regs, brtarget,	17734	CPU16Regs, CPU16Regs, brtarget,
17735	/* BtnezT8SltiX16 */	17735	/* BtnezT8SltiX16 */
17736	CPU16Regs, simm16, brtarget,	17736	CPU16Regs, simm16, brtarget,
17737	/* BtnezT8SltiuX16 */	17737	/* BtnezT8SltiuX16 */
17738	CPU16Regs, simm16, brtarget,	17738	CPU16Regs, simm16, brtarget,
17739	/* BtnezT8SltuX16 */	17739	/* BtnezT8SltuX16 */
17740	CPU16Regs, CPU16Regs, brtarget,	17740	CPU16Regs, CPU16Regs, brtarget,
17741	/* BuildPairF64 */	17741	/* BuildPairF64 */
17742	AFGR64Opnd, GPR32Opnd, GPR32Opnd,	17742	AFGR64Opnd, GPR32Opnd, GPR32Opnd,
17743	/* BuildPairF64_64 */	17743	/* BuildPairF64_64 */
17744	FGR64Opnd, GPR32Opnd, GPR32Opnd,	17744	FGR64Opnd, GPR32Opnd, GPR32Opnd,
17745	/* CFTC1 */	17745	/* CFTC1 */
17746	GPR32Opnd, FGRCCOpnd,	17746	GPR32Opnd, FGRCCOpnd,
17747	/* CONSTPOOL_ENTRY */	17747	/* CONSTPOOL_ENTRY */
17748	cpinst_operand, cpinst_operand, i32imm,	17748	cpinst_operand, cpinst_operand, i32imm,
17749	/* COPY_FD_PSEUDO */	17749	/* COPY_FD_PSEUDO */
17750	FGR64, MSA128D, uimm1_ptr,	17750	FGR64, MSA128D, uimm1_ptr,
17751	/* COPY_FW_PSEUDO */	17751	/* COPY_FW_PSEUDO */
17752	FGR32, MSA128W, uimm2_ptr,	17752	FGR32, MSA128W, uimm2_ptr,
17753	/* CTTC1 */	17753	/* CTTC1 */
17754	FGRCCOpnd, GPR32Opnd,	17754	FGRCCOpnd, GPR32Opnd,
17755	/* Constant32 */	17755	/* Constant32 */
17756	simm32,	17756	simm32,
17757	/* DMULImmMacro */	17757	/* DMULImmMacro */
17758	GPR64Opnd, GPR64Opnd, simm32_relaxed,	17758	GPR64Opnd, GPR64Opnd, simm32_relaxed,
17759	/* DMULMacro */	17759	/* DMULMacro */
17760	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17760	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17761	/* DMULOMacro */	17761	/* DMULOMacro */
17762	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17762	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17763	/* DMULOUMacro */	17763	/* DMULOUMacro */
17764	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17764	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17765	/* DROL */	17765	/* DROL */
17766	GPR32Opnd, GPR32Opnd, GPR32Opnd,	17766	GPR32Opnd, GPR32Opnd, GPR32Opnd,
17767	/* DROLImm */	17767	/* DROLImm */
17768	GPR32Opnd, GPR32Opnd, simm16,	17768	GPR32Opnd, GPR32Opnd, simm16,
17769	/* DROR */	17769	/* DROR */
17770	GPR32Opnd, GPR32Opnd, GPR32Opnd,	17770	GPR32Opnd, GPR32Opnd, GPR32Opnd,
17771	/* DRORImm */	17771	/* DRORImm */
17772	GPR32Opnd, GPR32Opnd, simm16,	17772	GPR32Opnd, GPR32Opnd, simm16,
17773	/* DSDivIMacro */	17773	/* DSDivIMacro */
17774	GPR64Opnd, GPR64Opnd, imm64,	17774	GPR64Opnd, GPR64Opnd, imm64,
17775	/* DSDivMacro */	17775	/* DSDivMacro */
17776	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17776	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17777	/* DSRemIMacro */	17777	/* DSRemIMacro */
17778	GPR64Opnd, GPR64Opnd, simm32_relaxed,	17778	GPR64Opnd, GPR64Opnd, simm32_relaxed,
17779	/* DSRemMacro */	17779	/* DSRemMacro */
17780	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17780	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17781	/* DUDivIMacro */	17781	/* DUDivIMacro */
17782	GPR64Opnd, GPR64Opnd, imm64,	17782	GPR64Opnd, GPR64Opnd, imm64,
17783	/* DUDivMacro */	17783	/* DUDivMacro */
17784	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17784	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17785	/* DURemIMacro */	17785	/* DURemIMacro */
17786	GPR64Opnd, GPR64Opnd, simm32_relaxed,	17786	GPR64Opnd, GPR64Opnd, simm32_relaxed,
17787	/* DURemMacro */	17787	/* DURemMacro */
17788	GPR64Opnd, GPR64Opnd, GPR64Opnd,	17788	GPR64Opnd, GPR64Opnd, GPR64Opnd,
17789	/* ERet */	17789	/* ERet */
17790	/* ExtractElementF64 */	17790	/* ExtractElementF64 */
17791	GPR32Opnd, AFGR64Opnd, i32imm,	17791	GPR32Opnd, AFGR64Opnd, i32imm,
17792	/* ExtractElementF64_64 */	17792	/* ExtractElementF64_64 */
17793	GPR32Opnd, FGR64Opnd, i32imm,	17793	GPR32Opnd, FGR64Opnd, i32imm,
17794	/* FABS_D */	17794	/* FABS_D */
17795	MSA128DOpnd, MSA128DOpnd,	17795	MSA128DOpnd, MSA128DOpnd,
17796	/* FABS_W */	17796	/* FABS_W */
17797	MSA128WOpnd, MSA128WOpnd,	17797	MSA128WOpnd, MSA128WOpnd,
17798	/* FEXP2_D_1_PSEUDO */	17798	/* FEXP2_D_1_PSEUDO */
17799	MSA128D, MSA128D,	17799	MSA128D, MSA128D,
17800	/* FEXP2_W_1_PSEUDO */	17800	/* FEXP2_W_1_PSEUDO */
17801	MSA128W, MSA128W,	17801	MSA128W, MSA128W,
17802	/* FILL_FD_PSEUDO */	17802	/* FILL_FD_PSEUDO */
17803	MSA128D, FGR64,	17803	MSA128D, FGR64,
17804	/* FILL_FW_PSEUDO */	17804	/* FILL_FW_PSEUDO */
17805	MSA128W, FGR32,	17805	MSA128W, FGR32,
17806	/* GotPrologue16 */	17806	/* GotPrologue16 */
17807	CPU16Regs, CPU16Regs, simm16, simm16,	17807	CPU16Regs, CPU16Regs, simm16, simm16,
17808	/* INSERT_B_VIDX64_PSEUDO */	17808	/* INSERT_B_VIDX64_PSEUDO */
17809	MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,	17809	MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,
17810	/* INSERT_B_VIDX_PSEUDO */	17810	/* INSERT_B_VIDX_PSEUDO */
17811	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,	17811	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,
17812	/* INSERT_D_VIDX64_PSEUDO */	17812	/* INSERT_D_VIDX64_PSEUDO */
17813	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,	17813	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,
17814	/* INSERT_D_VIDX_PSEUDO */	17814	/* INSERT_D_VIDX_PSEUDO */
17815	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,	17815	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,
17816	/* INSERT_FD_PSEUDO */	17816	/* INSERT_FD_PSEUDO */
17817	MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,	17817	MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,
17818	/* INSERT_FD_VIDX64_PSEUDO */	17818	/* INSERT_FD_VIDX64_PSEUDO */
17819	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,	17819	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,
17820	/* INSERT_FD_VIDX_PSEUDO */	17820	/* INSERT_FD_VIDX_PSEUDO */
17821	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,	17821	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,
17822	/* INSERT_FW_PSEUDO */	17822	/* INSERT_FW_PSEUDO */
17823	MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,	17823	MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,
17824	/* INSERT_FW_VIDX64_PSEUDO */	17824	/* INSERT_FW_VIDX64_PSEUDO */
17825	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,	17825	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,
17826	/* INSERT_FW_VIDX_PSEUDO */	17826	/* INSERT_FW_VIDX_PSEUDO */
17827	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,	17827	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,
17828	/* INSERT_H_VIDX64_PSEUDO */	17828	/* INSERT_H_VIDX64_PSEUDO */
17829	MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,	17829	MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,
17830	/* INSERT_H_VIDX_PSEUDO */	17830	/* INSERT_H_VIDX_PSEUDO */
17831	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,	17831	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,
17832	/* INSERT_W_VIDX64_PSEUDO */	17832	/* INSERT_W_VIDX64_PSEUDO */
17833	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,	17833	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,
17834	/* INSERT_W_VIDX_PSEUDO */	17834	/* INSERT_W_VIDX_PSEUDO */
17835	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,	17835	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,
17836	/* JALR64Pseudo */	17836	/* JALR64Pseudo */
17837	GPR64Opnd,	17837	GPR64Opnd,
17838	/* JALRHB64Pseudo */	17838	/* JALRHB64Pseudo */
17839	GPR64Opnd,	17839	GPR64Opnd,
17840	/* JALRHBPseudo */	17840	/* JALRHBPseudo */
17841	GPR32Opnd,	17841	GPR32Opnd,
17842	/* JALRPseudo */	17842	/* JALRPseudo */
17843	GPR32Opnd,	17843	GPR32Opnd,
17844	/* JAL_MMR6 */	17844	/* JAL_MMR6 */
17845	calltarget,	17845	calltarget,
17846	/* JalOneReg */	17846	/* JalOneReg */
17847	GPR32Opnd,	17847	GPR32Opnd,
17848	/* JalTwoReg */	17848	/* JalTwoReg */
17849	GPR32Opnd, GPR32Opnd,	17849	GPR32Opnd, GPR32Opnd,
17850	/* LDMacro */	17850	/* LDMacro */
17851	GPR32Opnd, -1, simm16,	17851	GPR32Opnd, -1, simm16,
17852	/* LDR_D */	17852	/* LDR_D */
17853	MSA128DOpnd, -1, GPR32,	17853	MSA128DOpnd, -1, GPR32,
17854	/* LDR_W */	17854	/* LDR_W */
17855	MSA128WOpnd, -1, GPR32,	17855	MSA128WOpnd, -1, GPR32,
17856	/* LD_F16 */	17856	/* LD_F16 */
17857	MSA128F16, -1, simm10,	17857	MSA128F16, -1, simm10,
17858	/* LOAD_ACC128 */	17858	/* LOAD_ACC128 */
17859	ACC128, -1, simm16,	17859	ACC128, -1, simm16,
17860	/* LOAD_ACC64 */	17860	/* LOAD_ACC64 */
17861	ACC64, -1, simm16,	17861	ACC64, -1, simm16,
17862	/* LOAD_ACC64DSP */	17862	/* LOAD_ACC64DSP */
17863	ACC64DSPOpnd, -1, simm16,	17863	ACC64DSPOpnd, -1, simm16,
17864	/* LOAD_CCOND_DSP */	17864	/* LOAD_CCOND_DSP */
17865	DSPCC, -1, simm16,	17865	DSPCC, -1, simm16,
17866	/* LONG_BRANCH_ADDiu */	17866	/* LONG_BRANCH_ADDiu */
17867	GPR32Opnd, GPR32Opnd, brtarget, brtarget,	17867	GPR32Opnd, GPR32Opnd, brtarget, brtarget,
17868	/* LONG_BRANCH_ADDiu2Op */	17868	/* LONG_BRANCH_ADDiu2Op */
17869	GPR32Opnd, GPR32Opnd, brtarget,	17869	GPR32Opnd, GPR32Opnd, brtarget,
17870	/* LONG_BRANCH_DADDiu */	17870	/* LONG_BRANCH_DADDiu */
17871	GPR64Opnd, GPR64Opnd, brtarget, brtarget,	17871	GPR64Opnd, GPR64Opnd, brtarget, brtarget,
17872	/* LONG_BRANCH_DADDiu2Op */	17872	/* LONG_BRANCH_DADDiu2Op */
17873	GPR64Opnd, GPR64Opnd, brtarget,	17873	GPR64Opnd, GPR64Opnd, brtarget,
17874	/* LONG_BRANCH_LUi */	17874	/* LONG_BRANCH_LUi */
17875	GPR32Opnd, brtarget, brtarget,	17875	GPR32Opnd, brtarget, brtarget,
17876	/* LONG_BRANCH_LUi2Op */	17876	/* LONG_BRANCH_LUi2Op */
17877	GPR32Opnd, brtarget,	17877	GPR32Opnd, brtarget,
17878	/* LONG_BRANCH_LUi2Op_64 */	17878	/* LONG_BRANCH_LUi2Op_64 */
17879	GPR64Opnd, brtarget,	17879	GPR64Opnd, brtarget,
17880	/* LWM_MM */	17880	/* LWM_MM */
17881	reglist, -1, simm12,	17881	reglist, -1, simm12,
17882	/* LoadAddrImm32 */	17882	/* LoadAddrImm32 */
17883	GPR32Opnd, i32imm,	17883	GPR32Opnd, i32imm,
17884	/* LoadAddrImm64 */	17884	/* LoadAddrImm64 */
17885	GPR64Opnd, imm64,	17885	GPR64Opnd, imm64,
17886	/* LoadAddrReg32 */	17886	/* LoadAddrReg32 */
17887	GPR32Opnd, -1, simm16,	17887	GPR32Opnd, -1, simm16,
17888	/* LoadAddrReg64 */	17888	/* LoadAddrReg64 */
17889	GPR64Opnd, -1, simm16,	17889	GPR64Opnd, -1, simm16,
17890	/* LoadImm32 */	17890	/* LoadImm32 */
17891	GPR32Opnd, uimm32_coerced,	17891	GPR32Opnd, uimm32_coerced,
17892	/* LoadImm64 */	17892	/* LoadImm64 */
17893	GPR64Opnd, imm64,	17893	GPR64Opnd, imm64,
17894	/* LoadImmDoubleFGR */	17894	/* LoadImmDoubleFGR */
17895	StrictlyFGR64Opnd, imm64,	17895	StrictlyFGR64Opnd, imm64,
17896	/* LoadImmDoubleFGR_32 */	17896	/* LoadImmDoubleFGR_32 */
17897	StrictlyAFGR64Opnd, imm64,	17897	StrictlyAFGR64Opnd, imm64,
17898	/* LoadImmDoubleGPR */	17898	/* LoadImmDoubleGPR */
17899	GPR32Opnd, imm64,	17899	GPR32Opnd, imm64,
17900	/* LoadImmSingleFGR */	17900	/* LoadImmSingleFGR */
17901	StrictlyFGR32Opnd, imm64,	17901	StrictlyFGR32Opnd, imm64,
17902	/* LoadImmSingleGPR */	17902	/* LoadImmSingleGPR */
17903	GPR32Opnd, imm64,	17903	GPR32Opnd, imm64,
17904	/* LwConstant32 */	17904	/* LwConstant32 */
17905	CPU16Regs, simm32, simm32,	17905	CPU16Regs, simm32, simm32,
17906	/* MFTACX */	17906	/* MFTACX */
17907	GPR32Opnd, ACC64DSPOpnd,	17907	GPR32Opnd, ACC64DSPOpnd,
17908	/* MFTC0 */	17908	/* MFTC0 */
17909	GPR32Opnd, COP0Opnd, uimm3,	17909	GPR32Opnd, COP0Opnd, uimm3,
17910	/* MFTC1 */	17910	/* MFTC1 */
17911	GPR32Opnd, FGR32Opnd,	17911	GPR32Opnd, FGR32Opnd,
17912	/* MFTDSP */	17912	/* MFTDSP */
17913	GPR32Opnd,	17913	GPR32Opnd,
17914	/* MFTGPR */	17914	/* MFTGPR */
17915	GPR32Opnd, GPR32Opnd, uimm3,	17915	GPR32Opnd, GPR32Opnd, uimm3,
17916	/* MFTHC1 */	17916	/* MFTHC1 */
17917	GPR32Opnd, FGR32Opnd,	17917	GPR32Opnd, FGR32Opnd,
17918	/* MFTHI */	17918	/* MFTHI */
17919	GPR32Opnd, ACC64DSPOpnd,	17919	GPR32Opnd, ACC64DSPOpnd,
17920	/* MFTLO */	17920	/* MFTLO */
17921	GPR32Opnd, ACC64DSPOpnd,	17921	GPR32Opnd, ACC64DSPOpnd,
17922	/* MIPSeh_return32 */	17922	/* MIPSeh_return32 */
17923	GPR32, GPR32,	17923	GPR32, GPR32,
17924	/* MIPSeh_return64 */	17924	/* MIPSeh_return64 */
17925	GPR64, GPR64,	17925	GPR64, GPR64,
17926	/* MSA_FP_EXTEND_D_PSEUDO */	17926	/* MSA_FP_EXTEND_D_PSEUDO */
17927	FGR64Opnd, MSA128F16,	17927	FGR64Opnd, MSA128F16,
17928	/* MSA_FP_EXTEND_W_PSEUDO */	17928	/* MSA_FP_EXTEND_W_PSEUDO */
17929	FGR32Opnd, MSA128F16,	17929	FGR32Opnd, MSA128F16,
17930	/* MSA_FP_ROUND_D_PSEUDO */	17930	/* MSA_FP_ROUND_D_PSEUDO */
17931	MSA128F16, FGR64Opnd,	17931	MSA128F16, FGR64Opnd,
17932	/* MSA_FP_ROUND_W_PSEUDO */	17932	/* MSA_FP_ROUND_W_PSEUDO */
17933	MSA128F16, FGR32Opnd,	17933	MSA128F16, FGR32Opnd,
17934	/* MTTACX */	17934	/* MTTACX */
17935	ACC64DSPOpnd, GPR32Opnd,	17935	ACC64DSPOpnd, GPR32Opnd,
17936	/* MTTC0 */	17936	/* MTTC0 */
17937	COP0Opnd, GPR32Opnd, uimm3,	17937	COP0Opnd, GPR32Opnd, uimm3,
17938	/* MTTC1 */	17938	/* MTTC1 */
17939	FGR32Opnd, GPR32Opnd,	17939	FGR32Opnd, GPR32Opnd,
17940	/* MTTDSP */	17940	/* MTTDSP */
17941	GPR32Opnd,	17941	GPR32Opnd,
17942	/* MTTGPR */	17942	/* MTTGPR */
17943	GPR32Opnd, GPR32Opnd,	17943	GPR32Opnd, GPR32Opnd,
17944	/* MTTHC1 */	17944	/* MTTHC1 */
17945	FGR32Opnd, GPR32Opnd,	17945	FGR32Opnd, GPR32Opnd,
17946	/* MTTHI */	17946	/* MTTHI */
17947	ACC64DSPOpnd, GPR32Opnd,	17947	ACC64DSPOpnd, GPR32Opnd,
17948	/* MTTLO */	17948	/* MTTLO */
17949	ACC64DSPOpnd, GPR32Opnd,	17949	ACC64DSPOpnd, GPR32Opnd,
17950	/* MULImmMacro */	17950	/* MULImmMacro */
17951	GPR32Opnd, GPR32Opnd, simm32_relaxed,	17951	GPR32Opnd, GPR32Opnd, simm32_relaxed,
17952	/* MULOMacro */	17952	/* MULOMacro */
17953	GPR32Opnd, GPR32Opnd, GPR32Opnd,	17953	GPR32Opnd, GPR32Opnd, GPR32Opnd,
17954	/* MULOUMacro */	17954	/* MULOUMacro */
17955	GPR32Opnd, GPR32Opnd, GPR32Opnd,	17955	GPR32Opnd, GPR32Opnd, GPR32Opnd,
17956	/* MultRxRy16 */	17956	/* MultRxRy16 */
17957	CPU16Regs, CPU16Regs,	17957	CPU16Regs, CPU16Regs,
17958	/* MultRxRyRz16 */	17958	/* MultRxRyRz16 */
17959	CPU16Regs, CPU16Regs, CPU16Regs,	17959	CPU16Regs, CPU16Regs, CPU16Regs,
17960	/* MultuRxRy16 */	17960	/* MultuRxRy16 */
17961	CPU16Regs, CPU16Regs,	17961	CPU16Regs, CPU16Regs,
17962	/* MultuRxRyRz16 */	17962	/* MultuRxRyRz16 */
17963	CPU16Regs, CPU16Regs, CPU16Regs,	17963	CPU16Regs, CPU16Regs, CPU16Regs,
17964	/* NOP */	17964	/* NOP */
17965	/* NORImm */	17965	/* NORImm */
17966	GPR32Opnd, GPR32Opnd, simm32_relaxed,	17966	GPR32Opnd, GPR32Opnd, simm32_relaxed,
17967	/* NORImm64 */	17967	/* NORImm64 */
17968	GPR64Opnd, GPR64Opnd, imm64,	17968	GPR64Opnd, GPR64Opnd, imm64,
17969	/* NOR_V_D_PSEUDO */	17969	/* NOR_V_D_PSEUDO */
17970	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	17970	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17971	/* NOR_V_H_PSEUDO */	17971	/* NOR_V_H_PSEUDO */
17972	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	17972	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17973	/* NOR_V_W_PSEUDO */	17973	/* NOR_V_W_PSEUDO */
17974	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	17974	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17975	/* OR_V_D_PSEUDO */	17975	/* OR_V_D_PSEUDO */
17976	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	17976	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17977	/* OR_V_H_PSEUDO */	17977	/* OR_V_H_PSEUDO */
17978	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	17978	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17979	/* OR_V_W_PSEUDO */	17979	/* OR_V_W_PSEUDO */
17980	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	17980	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17981	/* PseudoCMPU_EQ_QB */	17981	/* PseudoCMPU_EQ_QB */
17982	DSPCC, DSPROpnd, DSPROpnd,	17982	DSPCC, DSPROpnd, DSPROpnd,
17983	/* PseudoCMPU_LE_QB */	17983	/* PseudoCMPU_LE_QB */
17984	DSPCC, DSPROpnd, DSPROpnd,	17984	DSPCC, DSPROpnd, DSPROpnd,
17985	/* PseudoCMPU_LT_QB */	17985	/* PseudoCMPU_LT_QB */
17986	DSPCC, DSPROpnd, DSPROpnd,	17986	DSPCC, DSPROpnd, DSPROpnd,
17987	/* PseudoCMP_EQ_PH */	17987	/* PseudoCMP_EQ_PH */
17988	DSPCC, DSPROpnd, DSPROpnd,	17988	DSPCC, DSPROpnd, DSPROpnd,
17989	/* PseudoCMP_LE_PH */	17989	/* PseudoCMP_LE_PH */
17990	DSPCC, DSPROpnd, DSPROpnd,	17990	DSPCC, DSPROpnd, DSPROpnd,
17991	/* PseudoCMP_LT_PH */	17991	/* PseudoCMP_LT_PH */
17992	DSPCC, DSPROpnd, DSPROpnd,	17992	DSPCC, DSPROpnd, DSPROpnd,
17993	/* PseudoCVT_D32_W */	17993	/* PseudoCVT_D32_W */
17994	AFGR64Opnd, GPR32Opnd,	17994	AFGR64Opnd, GPR32Opnd,
17995	/* PseudoCVT_D64_L */	17995	/* PseudoCVT_D64_L */
17996	FGR64Opnd, GPR64Opnd,	17996	FGR64Opnd, GPR64Opnd,
17997	/* PseudoCVT_D64_W */	17997	/* PseudoCVT_D64_W */
17998	FGR64Opnd, GPR32Opnd,	17998	FGR64Opnd, GPR32Opnd,
17999	/* PseudoCVT_S_L */	17999	/* PseudoCVT_S_L */
18000	FGR64Opnd, GPR64Opnd,	18000	FGR64Opnd, GPR64Opnd,
18001	/* PseudoCVT_S_W */	18001	/* PseudoCVT_S_W */
18002	FGR32Opnd, GPR32Opnd,	18002	FGR32Opnd, GPR32Opnd,
18003	/* PseudoDMULT */	18003	/* PseudoDMULT */
18004	ACC128, GPR64Opnd, GPR64Opnd,	18004	ACC128, GPR64Opnd, GPR64Opnd,
18005	/* PseudoDMULTu */	18005	/* PseudoDMULTu */
18006	ACC128, GPR64Opnd, GPR64Opnd,	18006	ACC128, GPR64Opnd, GPR64Opnd,
18007	/* PseudoDSDIV */	18007	/* PseudoDSDIV */
18008	ACC128, GPR64Opnd, GPR64Opnd,	18008	ACC128, GPR64Opnd, GPR64Opnd,
18009	/* PseudoDUDIV */	18009	/* PseudoDUDIV */
18010	ACC128, GPR64Opnd, GPR64Opnd,	18010	ACC128, GPR64Opnd, GPR64Opnd,
18011	/* PseudoD_SELECT_I */	18011	/* PseudoD_SELECT_I */
18012	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	18012	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
18013	/* PseudoD_SELECT_I64 */	18013	/* PseudoD_SELECT_I64 */
18014	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	18014	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
18015	/* PseudoIndirectBranch */	18015	/* PseudoIndirectBranch */
18016	GPR32Opnd,	18016	GPR32Opnd,
18017	/* PseudoIndirectBranch64 */	18017	/* PseudoIndirectBranch64 */
18018	GPR64Opnd,	18018	GPR64Opnd,
18019	/* PseudoIndirectBranch64R6 */	18019	/* PseudoIndirectBranch64R6 */
18020	GPR64Opnd,	18020	GPR64Opnd,
18021	/* PseudoIndirectBranchR6 */	18021	/* PseudoIndirectBranchR6 */
18022	GPR32Opnd,	18022	GPR32Opnd,
18023	/* PseudoIndirectBranch_MM */	18023	/* PseudoIndirectBranch_MM */
18024	GPR32Opnd,	18024	GPR32Opnd,
18025	/* PseudoIndirectBranch_MMR6 */	18025	/* PseudoIndirectBranch_MMR6 */
18026	GPR32Opnd,	18026	GPR32Opnd,
18027	/* PseudoIndirectHazardBranch */	18027	/* PseudoIndirectHazardBranch */
18028	GPR32Opnd,	18028	GPR32Opnd,
18029	/* PseudoIndirectHazardBranch64 */	18029	/* PseudoIndirectHazardBranch64 */
18030	GPR64Opnd,	18030	GPR64Opnd,
18031	/* PseudoIndrectHazardBranch64R6 */	18031	/* PseudoIndrectHazardBranch64R6 */
18032	GPR64Opnd,	18032	GPR64Opnd,
18033	/* PseudoIndrectHazardBranchR6 */	18033	/* PseudoIndrectHazardBranchR6 */
18034	GPR32Opnd,	18034	GPR32Opnd,
18035	/* PseudoMADD */	18035	/* PseudoMADD */
18036	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18036	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18037	/* PseudoMADDU */	18037	/* PseudoMADDU */
18038	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18038	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18039	/* PseudoMADDU_MM */	18039	/* PseudoMADDU_MM */
18040	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18040	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18041	/* PseudoMADD_MM */	18041	/* PseudoMADD_MM */
18042	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18042	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18043	/* PseudoMFHI */	18043	/* PseudoMFHI */
18044	GPR32, ACC64,	18044	GPR32, ACC64,
18045	/* PseudoMFHI64 */	18045	/* PseudoMFHI64 */
18046	GPR64, ACC128,	18046	GPR64, ACC128,
18047	/* PseudoMFHI_MM */	18047	/* PseudoMFHI_MM */
18048	GPR32, ACC64,	18048	GPR32, ACC64,
18049	/* PseudoMFLO */	18049	/* PseudoMFLO */
18050	GPR32, ACC64,	18050	GPR32, ACC64,
18051	/* PseudoMFLO64 */	18051	/* PseudoMFLO64 */
18052	GPR64, ACC128,	18052	GPR64, ACC128,
18053	/* PseudoMFLO_MM */	18053	/* PseudoMFLO_MM */
18054	GPR32, ACC64,	18054	GPR32, ACC64,
18055	/* PseudoMSUB */	18055	/* PseudoMSUB */
18056	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18056	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18057	/* PseudoMSUBU */	18057	/* PseudoMSUBU */
18058	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18058	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18059	/* PseudoMSUBU_MM */	18059	/* PseudoMSUBU_MM */
18060	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18060	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18061	/* PseudoMSUB_MM */	18061	/* PseudoMSUB_MM */
18062	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	18062	ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18063	/* PseudoMTLOHI */	18063	/* PseudoMTLOHI */
18064	ACC64, GPR32, GPR32,	18064	ACC64, GPR32, GPR32,
18065	/* PseudoMTLOHI64 */	18065	/* PseudoMTLOHI64 */
18066	ACC128, GPR64, GPR64,	18066	ACC128, GPR64, GPR64,
18067	/* PseudoMTLOHI_DSP */	18067	/* PseudoMTLOHI_DSP */
18068	ACC64DSP, GPR32, GPR32,	18068	ACC64DSP, GPR32, GPR32,
18069	/* PseudoMTLOHI_MM */	18069	/* PseudoMTLOHI_MM */
18070	ACC64, GPR32, GPR32,	18070	ACC64, GPR32, GPR32,
18071	/* PseudoMULT */	18071	/* PseudoMULT */
18072	ACC64, GPR32Opnd, GPR32Opnd,	18072	ACC64, GPR32Opnd, GPR32Opnd,
18073	/* PseudoMULT_MM */	18073	/* PseudoMULT_MM */
18074	ACC64, GPR32Opnd, GPR32Opnd,	18074	ACC64, GPR32Opnd, GPR32Opnd,
18075	/* PseudoMULTu */	18075	/* PseudoMULTu */
18076	ACC64, GPR32Opnd, GPR32Opnd,	18076	ACC64, GPR32Opnd, GPR32Opnd,
18077	/* PseudoMULTu_MM */	18077	/* PseudoMULTu_MM */
18078	ACC64, GPR32Opnd, GPR32Opnd,	18078	ACC64, GPR32Opnd, GPR32Opnd,
18079	/* PseudoPICK_PH */	18079	/* PseudoPICK_PH */
18080	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	18080	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,
18081	/* PseudoPICK_QB */	18081	/* PseudoPICK_QB */
18082	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	18082	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,
18083	/* PseudoReturn */	18083	/* PseudoReturn */
18084	GPR32Opnd,	18084	GPR32Opnd,
18085	/* PseudoReturn64 */	18085	/* PseudoReturn64 */
18086	GPR64Opnd,	18086	GPR64Opnd,
18087	/* PseudoSDIV */	18087	/* PseudoSDIV */
18088	ACC64, GPR32Opnd, GPR32Opnd,	18088	ACC64, GPR32Opnd, GPR32Opnd,
18089	/* PseudoSELECTFP_F_D32 */	18089	/* PseudoSELECTFP_F_D32 */
18090	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	18090	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
18091	/* PseudoSELECTFP_F_D64 */	18091	/* PseudoSELECTFP_F_D64 */
18092	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	18092	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
18093	/* PseudoSELECTFP_F_I */	18093	/* PseudoSELECTFP_F_I */
18094	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	18094	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,
18095	/* PseudoSELECTFP_F_I64 */	18095	/* PseudoSELECTFP_F_I64 */
18096	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	18096	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,
18097	/* PseudoSELECTFP_F_S */	18097	/* PseudoSELECTFP_F_S */
18098	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	18098	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
18099	/* PseudoSELECTFP_T_D32 */	18099	/* PseudoSELECTFP_T_D32 */
18100	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	18100	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
18101	/* PseudoSELECTFP_T_D64 */	18101	/* PseudoSELECTFP_T_D64 */
18102	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	18102	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
18103	/* PseudoSELECTFP_T_I */	18103	/* PseudoSELECTFP_T_I */
18104	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	18104	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,
18105	/* PseudoSELECTFP_T_I64 */	18105	/* PseudoSELECTFP_T_I64 */
18106	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	18106	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,
18107	/* PseudoSELECTFP_T_S */	18107	/* PseudoSELECTFP_T_S */
18108	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	18108	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
18109	/* PseudoSELECT_D32 */	18109	/* PseudoSELECT_D32 */
18110	AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,	18110	AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,
18111	/* PseudoSELECT_D64 */	18111	/* PseudoSELECT_D64 */
18112	FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,	18112	FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,
18113	/* PseudoSELECT_I */	18113	/* PseudoSELECT_I */
18114	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	18114	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
18115	/* PseudoSELECT_I64 */	18115	/* PseudoSELECT_I64 */
18116	GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,	18116	GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,
18117	/* PseudoSELECT_S */	18117	/* PseudoSELECT_S */
18118	FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,	18118	FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,
18119	/* PseudoTRUNC_W_D */	18119	/* PseudoTRUNC_W_D */
18120	FGR32Opnd, FGR64Opnd, GPR32Opnd,	18120	FGR32Opnd, FGR64Opnd, GPR32Opnd,
18121	/* PseudoTRUNC_W_D32 */	18121	/* PseudoTRUNC_W_D32 */
18122	FGR32Opnd, AFGR64Opnd, GPR32Opnd,	18122	FGR32Opnd, AFGR64Opnd, GPR32Opnd,
18123	/* PseudoTRUNC_W_S */	18123	/* PseudoTRUNC_W_S */
18124	FGR32Opnd, FGR32Opnd, GPR32Opnd,	18124	FGR32Opnd, FGR32Opnd, GPR32Opnd,
18125	/* PseudoUDIV */	18125	/* PseudoUDIV */
18126	ACC64, GPR32Opnd, GPR32Opnd,	18126	ACC64, GPR32Opnd, GPR32Opnd,
18127	/* ROL */	18127	/* ROL */
18128	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18128	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18129	/* ROLImm */	18129	/* ROLImm */
18130	GPR32Opnd, GPR32Opnd, simm16,	18130	GPR32Opnd, GPR32Opnd, simm16,
18131	/* ROR */	18131	/* ROR */
18132	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18132	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18133	/* RORImm */	18133	/* RORImm */
18134	GPR32Opnd, GPR32Opnd, simm16,	18134	GPR32Opnd, GPR32Opnd, simm16,
18135	/* RetRA */	18135	/* RetRA */
18136	/* RetRA16 */	18136	/* RetRA16 */
18137	/* SDC1_M1 */	18137	/* SDC1_M1 */
18138	AFGR64Opnd, -1, simm16,	18138	AFGR64Opnd, -1, simm16,
18139	/* SDIV_MM_Pseudo */	18139	/* SDIV_MM_Pseudo */
18140	ACC64, GPR32Opnd, GPR32Opnd,	18140	ACC64, GPR32Opnd, GPR32Opnd,
18141	/* SDMacro */	18141	/* SDMacro */
18142	GPR32Opnd, -1, simm16,	18142	GPR32Opnd, -1, simm16,
18143	/* SDivIMacro */	18143	/* SDivIMacro */
18144	GPR32Opnd, GPR32Opnd, simm32,	18144	GPR32Opnd, GPR32Opnd, simm32,
18145	/* SDivMacro */	18145	/* SDivMacro */
18146	GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,	18146	GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,
18147	/* SEQIMacro */	18147	/* SEQIMacro */
18148	GPR32Opnd, GPR32Opnd, simm32_relaxed,	18148	GPR32Opnd, GPR32Opnd, simm32_relaxed,
18149	/* SEQMacro */	18149	/* SEQMacro */
18150	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18150	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18151	/* SGE */	18151	/* SGE */
18152	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18152	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18153	/* SGEImm */	18153	/* SGEImm */
18154	GPR32Opnd, GPR32Opnd, simm32,	18154	GPR32Opnd, GPR32Opnd, simm32,
18155	/* SGEImm64 */	18155	/* SGEImm64 */
18156	GPR64Opnd, GPR64Opnd, imm64,	18156	GPR64Opnd, GPR64Opnd, imm64,
18157	/* SGEU */	18157	/* SGEU */
18158	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18158	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18159	/* SGEUImm */	18159	/* SGEUImm */
18160	GPR32Opnd, GPR32Opnd, uimm32_coerced,	18160	GPR32Opnd, GPR32Opnd, uimm32_coerced,
18161	/* SGEUImm64 */	18161	/* SGEUImm64 */
18162	GPR64Opnd, GPR64Opnd, imm64,	18162	GPR64Opnd, GPR64Opnd, imm64,
18163	/* SGTImm */	18163	/* SGTImm */
18164	GPR32Opnd, GPR32Opnd, simm32,	18164	GPR32Opnd, GPR32Opnd, simm32,
18165	/* SGTImm64 */	18165	/* SGTImm64 */
18166	GPR64Opnd, GPR64Opnd, imm64,	18166	GPR64Opnd, GPR64Opnd, imm64,
18167	/* SGTUImm */	18167	/* SGTUImm */
18168	GPR32Opnd, GPR32Opnd, uimm32_coerced,	18168	GPR32Opnd, GPR32Opnd, uimm32_coerced,
18169	/* SGTUImm64 */	18169	/* SGTUImm64 */
18170	GPR64Opnd, GPR64Opnd, imm64,	18170	GPR64Opnd, GPR64Opnd, imm64,
18171	/* SLE */	18171	/* SLE */
18172	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18172	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18173	/* SLEImm */	18173	/* SLEImm */
18174	GPR32Opnd, GPR32Opnd, simm32,	18174	GPR32Opnd, GPR32Opnd, simm32,
18175	/* SLEImm64 */	18175	/* SLEImm64 */
18176	GPR64Opnd, GPR64Opnd, imm64,	18176	GPR64Opnd, GPR64Opnd, imm64,
18177	/* SLEU */	18177	/* SLEU */
18178	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18178	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18179	/* SLEUImm */	18179	/* SLEUImm */
18180	GPR32Opnd, GPR32Opnd, uimm32_coerced,	18180	GPR32Opnd, GPR32Opnd, uimm32_coerced,
18181	/* SLEUImm64 */	18181	/* SLEUImm64 */
18182	GPR64Opnd, GPR64Opnd, imm64,	18182	GPR64Opnd, GPR64Opnd, imm64,
18183	/* SLTImm64 */	18183	/* SLTImm64 */
18184	GPR64Opnd, GPR64Opnd, imm64,	18184	GPR64Opnd, GPR64Opnd, imm64,
18185	/* SLTUImm64 */	18185	/* SLTUImm64 */
18186	GPR64Opnd, GPR64Opnd, imm64,	18186	GPR64Opnd, GPR64Opnd, imm64,
18187	/* SNEIMacro */	18187	/* SNEIMacro */
18188	GPR32Opnd, GPR32Opnd, simm32_relaxed,	18188	GPR32Opnd, GPR32Opnd, simm32_relaxed,
18189	/* SNEMacro */	18189	/* SNEMacro */
18190	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18190	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18191	/* SNZ_B_PSEUDO */	18191	/* SNZ_B_PSEUDO */
18192	GPR32, MSA128B,	18192	GPR32, MSA128B,
18193	/* SNZ_D_PSEUDO */	18193	/* SNZ_D_PSEUDO */
18194	GPR32, MSA128D,	18194	GPR32, MSA128D,
18195	/* SNZ_H_PSEUDO */	18195	/* SNZ_H_PSEUDO */
18196	GPR32, MSA128H,	18196	GPR32, MSA128H,
18197	/* SNZ_V_PSEUDO */	18197	/* SNZ_V_PSEUDO */
18198	GPR32, MSA128B,	18198	GPR32, MSA128B,
18199	/* SNZ_W_PSEUDO */	18199	/* SNZ_W_PSEUDO */
18200	GPR32, MSA128W,	18200	GPR32, MSA128W,
18201	/* SRemIMacro */	18201	/* SRemIMacro */
18202	GPR32Opnd, GPR32Opnd, simm32_relaxed,	18202	GPR32Opnd, GPR32Opnd, simm32_relaxed,
18203	/* SRemMacro */	18203	/* SRemMacro */
18204	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18204	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18205	/* STORE_ACC128 */	18205	/* STORE_ACC128 */
18206	ACC128, -1, simm16,	18206	ACC128, -1, simm16,
18207	/* STORE_ACC64 */	18207	/* STORE_ACC64 */
18208	ACC64, -1, simm16,	18208	ACC64, -1, simm16,
18209	/* STORE_ACC64DSP */	18209	/* STORE_ACC64DSP */
18210	ACC64DSPOpnd, -1, simm16,	18210	ACC64DSPOpnd, -1, simm16,
18211	/* STORE_CCOND_DSP */	18211	/* STORE_CCOND_DSP */
18212	DSPCC, -1, simm16,	18212	DSPCC, -1, simm16,
18213	/* STR_D */	18213	/* STR_D */
18214	MSA128DOpnd, -1, GPR32,	18214	MSA128DOpnd, -1, GPR32,
18215	/* STR_W */	18215	/* STR_W */
18216	MSA128WOpnd, -1, GPR32,	18216	MSA128WOpnd, -1, GPR32,
18217	/* ST_F16 */	18217	/* ST_F16 */
18218	MSA128F16, -1, simm10,	18218	MSA128F16, -1, simm10,
18219	/* SWM_MM */	18219	/* SWM_MM */
18220	reglist, -1, simm12,	18220	reglist, -1, simm12,
18221	/* SZ_B_PSEUDO */	18221	/* SZ_B_PSEUDO */
18222	GPR32, MSA128B,	18222	GPR32, MSA128B,
18223	/* SZ_D_PSEUDO */	18223	/* SZ_D_PSEUDO */
18224	GPR32, MSA128D,	18224	GPR32, MSA128D,
18225	/* SZ_H_PSEUDO */	18225	/* SZ_H_PSEUDO */
18226	GPR32, MSA128H,	18226	GPR32, MSA128H,
18227	/* SZ_V_PSEUDO */	18227	/* SZ_V_PSEUDO */
18228	GPR32, MSA128B,	18228	GPR32, MSA128B,
18229	/* SZ_W_PSEUDO */	18229	/* SZ_W_PSEUDO */
18230	GPR32, MSA128W,	18230	GPR32, MSA128W,
18231	/* SaaAddr */	18231	/* SaaAddr */
18232	GPR64Opnd, -1, simm16,	18232	GPR64Opnd, -1, simm16,
18233	/* SaadAddr */	18233	/* SaadAddr */
18234	GPR64Opnd, -1, simm16,	18234	GPR64Opnd, -1, simm16,
18235	/* SelBeqZ */	18235	/* SelBeqZ */
18236	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18236	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18237	/* SelBneZ */	18237	/* SelBneZ */
18238	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18238	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18239	/* SelTBteqZCmp */	18239	/* SelTBteqZCmp */
18240	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18240	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18241	/* SelTBteqZCmpi */	18241	/* SelTBteqZCmpi */
18242	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18242	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18243	/* SelTBteqZSlt */	18243	/* SelTBteqZSlt */
18244	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18244	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18245	/* SelTBteqZSlti */	18245	/* SelTBteqZSlti */
18246	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18246	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18247	/* SelTBteqZSltiu */	18247	/* SelTBteqZSltiu */
18248	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18248	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18249	/* SelTBteqZSltu */	18249	/* SelTBteqZSltu */
18250	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18250	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18251	/* SelTBtneZCmp */	18251	/* SelTBtneZCmp */
18252	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18252	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18253	/* SelTBtneZCmpi */	18253	/* SelTBtneZCmpi */
18254	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18254	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18255	/* SelTBtneZSlt */	18255	/* SelTBtneZSlt */
18256	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18256	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18257	/* SelTBtneZSlti */	18257	/* SelTBtneZSlti */
18258	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18258	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18259	/* SelTBtneZSltiu */	18259	/* SelTBtneZSltiu */
18260	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	18260	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18261	/* SelTBtneZSltu */	18261	/* SelTBtneZSltu */
18262	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	18262	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18263	/* SltCCRxRy16 */	18263	/* SltCCRxRy16 */
18264	CPU16Regs, CPU16Regs, CPU16Regs,	18264	CPU16Regs, CPU16Regs, CPU16Regs,
18265	/* SltiCCRxImmX16 */	18265	/* SltiCCRxImmX16 */
18266	CPU16Regs, CPU16Regs, simm16,	18266	CPU16Regs, CPU16Regs, simm16,
18267	/* SltiuCCRxImmX16 */	18267	/* SltiuCCRxImmX16 */
18268	CPU16Regs, CPU16Regs, simm16,	18268	CPU16Regs, CPU16Regs, simm16,
18269	/* SltuCCRxRy16 */	18269	/* SltuCCRxRy16 */
18270	CPU16Regs, CPU16Regs, CPU16Regs,	18270	CPU16Regs, CPU16Regs, CPU16Regs,
18271	/* SltuRxRyRz16 */	18271	/* SltuRxRyRz16 */
18272	CPU16Regs, CPU16Regs, CPU16Regs,	18272	CPU16Regs, CPU16Regs, CPU16Regs,
18273	/* TAILCALL */	18273	/* TAILCALL */
18274	calltarget,	18274	calltarget,
18275	/* TAILCALL64R6REG */	18275	/* TAILCALL64R6REG */
18276	GPR64Opnd,	18276	GPR64Opnd,
18277	/* TAILCALLHB64R6REG */	18277	/* TAILCALLHB64R6REG */
18278	GPR64Opnd,	18278	GPR64Opnd,
18279	/* TAILCALLHBR6REG */	18279	/* TAILCALLHBR6REG */
18280	GPR32Opnd,	18280	GPR32Opnd,
18281	/* TAILCALLR6REG */	18281	/* TAILCALLR6REG */
18282	GPR32Opnd,	18282	GPR32Opnd,
18283	/* TAILCALLREG */	18283	/* TAILCALLREG */
18284	GPR32Opnd,	18284	GPR32Opnd,
18285	/* TAILCALLREG64 */	18285	/* TAILCALLREG64 */
18286	GPR64Opnd,	18286	GPR64Opnd,
18287	/* TAILCALLREGHB */	18287	/* TAILCALLREGHB */
18288	GPR32Opnd,	18288	GPR32Opnd,
18289	/* TAILCALLREGHB64 */	18289	/* TAILCALLREGHB64 */
18290	GPR64Opnd,	18290	GPR64Opnd,
18291	/* TAILCALLREG_MM */	18291	/* TAILCALLREG_MM */
18292	GPR32Opnd,	18292	GPR32Opnd,
18293	/* TAILCALLREG_MMR6 */	18293	/* TAILCALLREG_MMR6 */
18294	GPR32Opnd,	18294	GPR32Opnd,
18295	/* TAILCALL_MM */	18295	/* TAILCALL_MM */
18296	calltarget,	18296	calltarget,
18297	/* TAILCALL_MMR6 */	18297	/* TAILCALL_MMR6 */
18298	calltarget,	18298	calltarget,
18299	/* TRAP */	18299	/* TRAP */
18300	/* TRAP_MM */	18300	/* TRAP_MM */
18301	/* UDIV_MM_Pseudo */	18301	/* UDIV_MM_Pseudo */
18302	ACC64, GPR32Opnd, GPR32Opnd,	18302	ACC64, GPR32Opnd, GPR32Opnd,
18303	/* UDivIMacro */	18303	/* UDivIMacro */
18304	GPR32Opnd, GPR32Opnd, simm32,	18304	GPR32Opnd, GPR32Opnd, simm32,
18305	/* UDivMacro */	18305	/* UDivMacro */
18306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18306	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18307	/* URemIMacro */	18307	/* URemIMacro */
18308	GPR32Opnd, GPR32Opnd, simm32_relaxed,	18308	GPR32Opnd, GPR32Opnd, simm32_relaxed,
18309	/* URemMacro */	18309	/* URemMacro */
18310	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18310	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18311	/* Ulh */	18311	/* Ulh */
18312	GPR32Opnd, -1, simm16,	18312	GPR32Opnd, -1, simm16,
18313	/* Ulhu */	18313	/* Ulhu */
18314	GPR32Opnd, -1, simm16,	18314	GPR32Opnd, -1, simm16,
18315	/* Ulw */	18315	/* Ulw */
18316	GPR32Opnd, -1, simm16,	18316	GPR32Opnd, -1, simm16,
18317	/* Ush */	18317	/* Ush */
18318	GPR32Opnd, -1, simm16,	18318	GPR32Opnd, -1, simm16,
18319	/* Usw */	18319	/* Usw */
18320	GPR32Opnd, -1, simm16,	18320	GPR32Opnd, -1, simm16,
18321	/* XOR_V_D_PSEUDO */	18321	/* XOR_V_D_PSEUDO */
18322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18323	/* XOR_V_H_PSEUDO */	18323	/* XOR_V_H_PSEUDO */
18324	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18324	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18325	/* XOR_V_W_PSEUDO */	18325	/* XOR_V_W_PSEUDO */
18326	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18326	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18327	/* ABSQ_S_PH */	18327	/* ABSQ_S_PH */
18328	DSPROpnd, DSPROpnd,	18328	DSPROpnd, DSPROpnd,
18329	/* ABSQ_S_PH_MM */	18329	/* ABSQ_S_PH_MM */
18330	DSPROpnd, DSPROpnd,	18330	DSPROpnd, DSPROpnd,
18331	/* ABSQ_S_QB */	18331	/* ABSQ_S_QB */
18332	DSPROpnd, DSPROpnd,	18332	DSPROpnd, DSPROpnd,
18333	/* ABSQ_S_QB_MMR2 */	18333	/* ABSQ_S_QB_MMR2 */
18334	DSPROpnd, DSPROpnd,	18334	DSPROpnd, DSPROpnd,
18335	/* ABSQ_S_W */	18335	/* ABSQ_S_W */
18336	GPR32Opnd, GPR32Opnd,	18336	GPR32Opnd, GPR32Opnd,
18337	/* ABSQ_S_W_MM */	18337	/* ABSQ_S_W_MM */
18338	GPR32Opnd, GPR32Opnd,	18338	GPR32Opnd, GPR32Opnd,
18339	/* ADD */	18339	/* ADD */
18340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18340	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18341	/* ADDIUPC */	18341	/* ADDIUPC */
18342	GPR32Opnd, simm19_lsl2,	18342	GPR32Opnd, simm19_lsl2,
18343	/* ADDIUPC_MM */	18343	/* ADDIUPC_MM */
18344	GPRMM16Opnd, simm23_lsl2,	18344	GPRMM16Opnd, simm23_lsl2,
18345	/* ADDIUPC_MMR6 */	18345	/* ADDIUPC_MMR6 */
18346	GPR32Opnd, simm19_lsl2,	18346	GPR32Opnd, simm19_lsl2,
18347	/* ADDIUR1SP_MM */	18347	/* ADDIUR1SP_MM */
18348	GPRMM16Opnd, uimm6_lsl2,	18348	GPRMM16Opnd, uimm6_lsl2,
18349	/* ADDIUR2_MM */	18349	/* ADDIUR2_MM */
18350	GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,	18350	GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,
18351	/* ADDIUS5_MM */	18351	/* ADDIUS5_MM */
18352	GPR32Opnd, GPR32Opnd, simm4,	18352	GPR32Opnd, GPR32Opnd, simm4,
18353	/* ADDIUSP_MM */	18353	/* ADDIUSP_MM */
18354	simm9_addiusp,	18354	simm9_addiusp,
18355	/* ADDIU_MMR6 */	18355	/* ADDIU_MMR6 */
18356	GPR32Opnd, GPR32Opnd, simm16,	18356	GPR32Opnd, GPR32Opnd, simm16,
18357	/* ADDQH_PH */	18357	/* ADDQH_PH */
18358	DSPROpnd, DSPROpnd, DSPROpnd,	18358	DSPROpnd, DSPROpnd, DSPROpnd,
18359	/* ADDQH_PH_MMR2 */	18359	/* ADDQH_PH_MMR2 */
18360	DSPROpnd, DSPROpnd, DSPROpnd,	18360	DSPROpnd, DSPROpnd, DSPROpnd,
18361	/* ADDQH_R_PH */	18361	/* ADDQH_R_PH */
18362	DSPROpnd, DSPROpnd, DSPROpnd,	18362	DSPROpnd, DSPROpnd, DSPROpnd,
18363	/* ADDQH_R_PH_MMR2 */	18363	/* ADDQH_R_PH_MMR2 */
18364	DSPROpnd, DSPROpnd, DSPROpnd,	18364	DSPROpnd, DSPROpnd, DSPROpnd,
18365	/* ADDQH_R_W */	18365	/* ADDQH_R_W */
18366	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18366	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18367	/* ADDQH_R_W_MMR2 */	18367	/* ADDQH_R_W_MMR2 */
18368	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18368	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18369	/* ADDQH_W */	18369	/* ADDQH_W */
18370	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18370	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18371	/* ADDQH_W_MMR2 */	18371	/* ADDQH_W_MMR2 */
18372	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18372	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18373	/* ADDQ_PH */	18373	/* ADDQ_PH */
18374	DSPROpnd, DSPROpnd, DSPROpnd,	18374	DSPROpnd, DSPROpnd, DSPROpnd,
18375	/* ADDQ_PH_MM */	18375	/* ADDQ_PH_MM */
18376	DSPROpnd, DSPROpnd, DSPROpnd,	18376	DSPROpnd, DSPROpnd, DSPROpnd,
18377	/* ADDQ_S_PH */	18377	/* ADDQ_S_PH */
18378	DSPROpnd, DSPROpnd, DSPROpnd,	18378	DSPROpnd, DSPROpnd, DSPROpnd,
18379	/* ADDQ_S_PH_MM */	18379	/* ADDQ_S_PH_MM */
18380	DSPROpnd, DSPROpnd, DSPROpnd,	18380	DSPROpnd, DSPROpnd, DSPROpnd,
18381	/* ADDQ_S_W */	18381	/* ADDQ_S_W */
18382	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18382	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18383	/* ADDQ_S_W_MM */	18383	/* ADDQ_S_W_MM */
18384	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18384	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18385	/* ADDR_PS64 */	18385	/* ADDR_PS64 */
18386	FGR64Opnd, FGR64Opnd, FGR64Opnd,	18386	FGR64Opnd, FGR64Opnd, FGR64Opnd,
18387	/* ADDSC */	18387	/* ADDSC */
18388	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18388	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18389	/* ADDSC_MM */	18389	/* ADDSC_MM */
18390	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18390	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18391	/* ADDS_A_B */	18391	/* ADDS_A_B */
18392	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18392	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18393	/* ADDS_A_D */	18393	/* ADDS_A_D */
18394	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18394	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18395	/* ADDS_A_H */	18395	/* ADDS_A_H */
18396	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18396	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18397	/* ADDS_A_W */	18397	/* ADDS_A_W */
18398	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18398	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18399	/* ADDS_S_B */	18399	/* ADDS_S_B */
18400	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18400	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18401	/* ADDS_S_D */	18401	/* ADDS_S_D */
18402	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18402	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18403	/* ADDS_S_H */	18403	/* ADDS_S_H */
18404	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18404	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18405	/* ADDS_S_W */	18405	/* ADDS_S_W */
18406	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18406	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18407	/* ADDS_U_B */	18407	/* ADDS_U_B */
18408	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18408	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18409	/* ADDS_U_D */	18409	/* ADDS_U_D */
18410	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18410	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18411	/* ADDS_U_H */	18411	/* ADDS_U_H */
18412	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18412	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18413	/* ADDS_U_W */	18413	/* ADDS_U_W */
18414	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18414	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18415	/* ADDU16_MM */	18415	/* ADDU16_MM */
18416	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	18416	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18417	/* ADDU16_MMR6 */	18417	/* ADDU16_MMR6 */
18418	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	18418	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18419	/* ADDUH_QB */	18419	/* ADDUH_QB */
18420	DSPROpnd, DSPROpnd, DSPROpnd,	18420	DSPROpnd, DSPROpnd, DSPROpnd,
18421	/* ADDUH_QB_MMR2 */	18421	/* ADDUH_QB_MMR2 */
18422	DSPROpnd, DSPROpnd, DSPROpnd,	18422	DSPROpnd, DSPROpnd, DSPROpnd,
18423	/* ADDUH_R_QB */	18423	/* ADDUH_R_QB */
18424	DSPROpnd, DSPROpnd, DSPROpnd,	18424	DSPROpnd, DSPROpnd, DSPROpnd,
18425	/* ADDUH_R_QB_MMR2 */	18425	/* ADDUH_R_QB_MMR2 */
18426	DSPROpnd, DSPROpnd, DSPROpnd,	18426	DSPROpnd, DSPROpnd, DSPROpnd,
18427	/* ADDU_MMR6 */	18427	/* ADDU_MMR6 */
18428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18428	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18429	/* ADDU_PH */	18429	/* ADDU_PH */
18430	DSPROpnd, DSPROpnd, DSPROpnd,	18430	DSPROpnd, DSPROpnd, DSPROpnd,
18431	/* ADDU_PH_MMR2 */	18431	/* ADDU_PH_MMR2 */
18432	DSPROpnd, DSPROpnd, DSPROpnd,	18432	DSPROpnd, DSPROpnd, DSPROpnd,
18433	/* ADDU_QB */	18433	/* ADDU_QB */
18434	DSPROpnd, DSPROpnd, DSPROpnd,	18434	DSPROpnd, DSPROpnd, DSPROpnd,
18435	/* ADDU_QB_MM */	18435	/* ADDU_QB_MM */
18436	DSPROpnd, DSPROpnd, DSPROpnd,	18436	DSPROpnd, DSPROpnd, DSPROpnd,
18437	/* ADDU_S_PH */	18437	/* ADDU_S_PH */
18438	DSPROpnd, DSPROpnd, DSPROpnd,	18438	DSPROpnd, DSPROpnd, DSPROpnd,
18439	/* ADDU_S_PH_MMR2 */	18439	/* ADDU_S_PH_MMR2 */
18440	DSPROpnd, DSPROpnd, DSPROpnd,	18440	DSPROpnd, DSPROpnd, DSPROpnd,
18441	/* ADDU_S_QB */	18441	/* ADDU_S_QB */
18442	DSPROpnd, DSPROpnd, DSPROpnd,	18442	DSPROpnd, DSPROpnd, DSPROpnd,
18443	/* ADDU_S_QB_MM */	18443	/* ADDU_S_QB_MM */
18444	DSPROpnd, DSPROpnd, DSPROpnd,	18444	DSPROpnd, DSPROpnd, DSPROpnd,
18445	/* ADDVI_B */	18445	/* ADDVI_B */
18446	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	18446	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
18447	/* ADDVI_D */	18447	/* ADDVI_D */
18448	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	18448	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
18449	/* ADDVI_H */	18449	/* ADDVI_H */
18450	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	18450	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
18451	/* ADDVI_W */	18451	/* ADDVI_W */
18452	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18452	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18453	/* ADDV_B */	18453	/* ADDV_B */
18454	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18454	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18455	/* ADDV_D */	18455	/* ADDV_D */
18456	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18456	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18457	/* ADDV_H */	18457	/* ADDV_H */
18458	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18458	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18459	/* ADDV_W */	18459	/* ADDV_W */
18460	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18460	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18461	/* ADDWC */	18461	/* ADDWC */
18462	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18462	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18463	/* ADDWC_MM */	18463	/* ADDWC_MM */
18464	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18464	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18465	/* ADD_A_B */	18465	/* ADD_A_B */
18466	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18466	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18467	/* ADD_A_D */	18467	/* ADD_A_D */
18468	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18468	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18469	/* ADD_A_H */	18469	/* ADD_A_H */
18470	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18470	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18471	/* ADD_A_W */	18471	/* ADD_A_W */
18472	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18472	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18473	/* ADD_MM */	18473	/* ADD_MM */
18474	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18474	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18475	/* ADD_MMR6 */	18475	/* ADD_MMR6 */
18476	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18476	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18477	/* ADDi */	18477	/* ADDi */
18478	GPR32Opnd, GPR32Opnd, simm16_relaxed,	18478	GPR32Opnd, GPR32Opnd, simm16_relaxed,
18479	/* ADDi_MM */	18479	/* ADDi_MM */
18480	GPR32Opnd, GPR32Opnd, simm16,	18480	GPR32Opnd, GPR32Opnd, simm16,
18481	/* ADDiu */	18481	/* ADDiu */
18482	GPR32Opnd, GPR32Opnd, simm16_relaxed,	18482	GPR32Opnd, GPR32Opnd, simm16_relaxed,
18483	/* ADDiu_MM */	18483	/* ADDiu_MM */
18484	GPR32Opnd, GPR32Opnd, simm16,	18484	GPR32Opnd, GPR32Opnd, simm16,
18485	/* ADDu */	18485	/* ADDu */
18486	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18486	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18487	/* ADDu_MM */	18487	/* ADDu_MM */
18488	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18488	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18489	/* ALIGN */	18489	/* ALIGN */
18490	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	18490	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,
18491	/* ALIGN_MMR6 */	18491	/* ALIGN_MMR6 */
18492	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	18492	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,
18493	/* ALUIPC */	18493	/* ALUIPC */
18494	GPR32Opnd, simm16,	18494	GPR32Opnd, simm16,
18495	/* ALUIPC_MMR6 */	18495	/* ALUIPC_MMR6 */
18496	GPR32Opnd, simm16,	18496	GPR32Opnd, simm16,
18497	/* AND */	18497	/* AND */
18498	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18498	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18499	/* AND16_MM */	18499	/* AND16_MM */
18500	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	18500	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18501	/* AND16_MMR6 */	18501	/* AND16_MMR6 */
18502	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	18502	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18503	/* AND64 */	18503	/* AND64 */
18504	GPR64Opnd, GPR64Opnd, GPR64Opnd,	18504	GPR64Opnd, GPR64Opnd, GPR64Opnd,
18505	/* ANDI16_MM */	18505	/* ANDI16_MM */
18506	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	18506	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,
18507	/* ANDI16_MMR6 */	18507	/* ANDI16_MMR6 */
18508	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	18508	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,
18509	/* ANDI_B */	18509	/* ANDI_B */
18510	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	18510	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
18511	/* ANDI_MMR6 */	18511	/* ANDI_MMR6 */
18512	GPR32Opnd, GPR32Opnd, uimm16,	18512	GPR32Opnd, GPR32Opnd, uimm16,
18513	/* AND_MM */	18513	/* AND_MM */
18514	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18514	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18515	/* AND_MMR6 */	18515	/* AND_MMR6 */
18516	GPR32Opnd, GPR32Opnd, GPR32Opnd,	18516	GPR32Opnd, GPR32Opnd, GPR32Opnd,
18517	/* AND_V */	18517	/* AND_V */
18518	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18518	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18519	/* ANDi */	18519	/* ANDi */
18520	GPR32Opnd, GPR32Opnd, uimm16,	18520	GPR32Opnd, GPR32Opnd, uimm16,
18521	/* ANDi64 */	18521	/* ANDi64 */
18522	GPR64Opnd, GPR64Opnd, uimm16_64,	18522	GPR64Opnd, GPR64Opnd, uimm16_64,
18523	/* ANDi_MM */	18523	/* ANDi_MM */
18524	GPR32Opnd, GPR32Opnd, uimm16,	18524	GPR32Opnd, GPR32Opnd, uimm16,
18525	/* APPEND */	18525	/* APPEND */
18526	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	18526	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
18527	/* APPEND_MMR2 */	18527	/* APPEND_MMR2 */
18528	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	18528	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
18529	/* ASUB_S_B */	18529	/* ASUB_S_B */
18530	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18530	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18531	/* ASUB_S_D */	18531	/* ASUB_S_D */
18532	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18532	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18533	/* ASUB_S_H */	18533	/* ASUB_S_H */
18534	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18534	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18535	/* ASUB_S_W */	18535	/* ASUB_S_W */
18536	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18536	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18537	/* ASUB_U_B */	18537	/* ASUB_U_B */
18538	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18538	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18539	/* ASUB_U_D */	18539	/* ASUB_U_D */
18540	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18540	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18541	/* ASUB_U_H */	18541	/* ASUB_U_H */
18542	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18542	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18543	/* ASUB_U_W */	18543	/* ASUB_U_W */
18544	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18544	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18545	/* AUI */	18545	/* AUI */
18546	GPR32Opnd, GPR32Opnd, uimm16,	18546	GPR32Opnd, GPR32Opnd, uimm16,
18547	/* AUIPC */	18547	/* AUIPC */
18548	GPR32Opnd, simm16,	18548	GPR32Opnd, simm16,
18549	/* AUIPC_MMR6 */	18549	/* AUIPC_MMR6 */
18550	GPR32Opnd, simm16,	18550	GPR32Opnd, simm16,
18551	/* AUI_MMR6 */	18551	/* AUI_MMR6 */
18552	GPR32Opnd, GPR32Opnd, uimm16,	18552	GPR32Opnd, GPR32Opnd, uimm16,
18553	/* AVER_S_B */	18553	/* AVER_S_B */
18554	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18554	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18555	/* AVER_S_D */	18555	/* AVER_S_D */
18556	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18556	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18557	/* AVER_S_H */	18557	/* AVER_S_H */
18558	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18558	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18559	/* AVER_S_W */	18559	/* AVER_S_W */
18560	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18560	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18561	/* AVER_U_B */	18561	/* AVER_U_B */
18562	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18562	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18563	/* AVER_U_D */	18563	/* AVER_U_D */
18564	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18564	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18565	/* AVER_U_H */	18565	/* AVER_U_H */
18566	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18566	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18567	/* AVER_U_W */	18567	/* AVER_U_W */
18568	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18568	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18569	/* AVE_S_B */	18569	/* AVE_S_B */
18570	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18570	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18571	/* AVE_S_D */	18571	/* AVE_S_D */
18572	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18572	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18573	/* AVE_S_H */	18573	/* AVE_S_H */
18574	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18574	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18575	/* AVE_S_W */	18575	/* AVE_S_W */
18576	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18576	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18577	/* AVE_U_B */	18577	/* AVE_U_B */
18578	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18578	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18579	/* AVE_U_D */	18579	/* AVE_U_D */
18580	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18580	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18581	/* AVE_U_H */	18581	/* AVE_U_H */
18582	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18582	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18583	/* AVE_U_W */	18583	/* AVE_U_W */
18584	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18584	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18585	/* AddiuRxImmX16 */	18585	/* AddiuRxImmX16 */
18586	CPU16Regs, simm16,	18586	CPU16Regs, simm16,
18587	/* AddiuRxPcImmX16 */	18587	/* AddiuRxPcImmX16 */
18588	CPU16Regs, simm16,	18588	CPU16Regs, simm16,
18589	/* AddiuRxRxImm16 */	18589	/* AddiuRxRxImm16 */
18590	CPU16Regs, CPU16Regs, simm16,	18590	CPU16Regs, CPU16Regs, simm16,
18591	/* AddiuRxRxImmX16 */	18591	/* AddiuRxRxImmX16 */
18592	CPU16Regs, CPU16Regs, simm16,	18592	CPU16Regs, CPU16Regs, simm16,
18593	/* AddiuRxRyOffMemX16 */	18593	/* AddiuRxRyOffMemX16 */
18594	CPU16Regs, CPU16RegsPlusSP, simm16,	18594	CPU16Regs, CPU16RegsPlusSP, simm16,
18595	/* AddiuSpImm16 */	18595	/* AddiuSpImm16 */
18596	simm16,	18596	simm16,
18597	/* AddiuSpImmX16 */	18597	/* AddiuSpImmX16 */
18598	simm16,	18598	simm16,
18599	/* AdduRxRyRz16 */	18599	/* AdduRxRyRz16 */
18600	CPU16Regs, CPU16Regs, CPU16Regs,	18600	CPU16Regs, CPU16Regs, CPU16Regs,
18601	/* AndRxRxRy16 */	18601	/* AndRxRxRy16 */
18602	CPU16Regs, CPU16Regs, CPU16Regs,	18602	CPU16Regs, CPU16Regs, CPU16Regs,
18603	/* B16_MM */	18603	/* B16_MM */
18604	brtarget10_mm,	18604	brtarget10_mm,
18605	/* BADDu */	18605	/* BADDu */
18606	GPR64Opnd, GPR64Opnd, GPR64Opnd,	18606	GPR64Opnd, GPR64Opnd, GPR64Opnd,
18607	/* BAL */	18607	/* BAL */
18608	brtarget,	18608	brtarget,
18609	/* BALC */	18609	/* BALC */
18610	brtarget26,	18610	brtarget26,
18611	/* BALC_MMR6 */	18611	/* BALC_MMR6 */
18612	brtarget26_mm,	18612	brtarget26_mm,
18613	/* BALIGN */	18613	/* BALIGN */
18614	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	18614	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,
18615	/* BALIGN_MMR2 */	18615	/* BALIGN_MMR2 */
18616	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	18616	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,
18617	/* BBIT0 */	18617	/* BBIT0 */
18618	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	18618	GPR64Opnd, uimm5_64_report_uimm6, brtarget,
18619	/* BBIT032 */	18619	/* BBIT032 */
18620	GPR64Opnd, uimm5_64, brtarget,	18620	GPR64Opnd, uimm5_64, brtarget,
18621	/* BBIT1 */	18621	/* BBIT1 */
18622	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	18622	GPR64Opnd, uimm5_64_report_uimm6, brtarget,
18623	/* BBIT132 */	18623	/* BBIT132 */
18624	GPR64Opnd, uimm5_64, brtarget,	18624	GPR64Opnd, uimm5_64, brtarget,
18625	/* BC */	18625	/* BC */
18626	brtarget26,	18626	brtarget26,
18627	/* BC16_MMR6 */	18627	/* BC16_MMR6 */
18628	brtarget10_mm,	18628	brtarget10_mm,
18629	/* BC1EQZ */	18629	/* BC1EQZ */
18630	FGR64Opnd, brtarget,	18630	FGR64Opnd, brtarget,
18631	/* BC1EQZC_MMR6 */	18631	/* BC1EQZC_MMR6 */
18632	FGR64Opnd, brtarget_mm,	18632	FGR64Opnd, brtarget_mm,
18633	/* BC1F */	18633	/* BC1F */
18634	FCCRegsOpnd, brtarget,	18634	FCCRegsOpnd, brtarget,
18635	/* BC1FL */	18635	/* BC1FL */
18636	FCCRegsOpnd, brtarget,	18636	FCCRegsOpnd, brtarget,
18637	/* BC1F_MM */	18637	/* BC1F_MM */
18638	FCCRegsOpnd, brtarget_mm,	18638	FCCRegsOpnd, brtarget_mm,
18639	/* BC1NEZ */	18639	/* BC1NEZ */
18640	FGR64Opnd, brtarget,	18640	FGR64Opnd, brtarget,
18641	/* BC1NEZC_MMR6 */	18641	/* BC1NEZC_MMR6 */
18642	FGR64Opnd, brtarget_mm,	18642	FGR64Opnd, brtarget_mm,
18643	/* BC1T */	18643	/* BC1T */
18644	FCCRegsOpnd, brtarget,	18644	FCCRegsOpnd, brtarget,
18645	/* BC1TL */	18645	/* BC1TL */
18646	FCCRegsOpnd, brtarget,	18646	FCCRegsOpnd, brtarget,
18647	/* BC1T_MM */	18647	/* BC1T_MM */
18648	FCCRegsOpnd, brtarget_mm,	18648	FCCRegsOpnd, brtarget_mm,
18649	/* BC2EQZ */	18649	/* BC2EQZ */
18650	COP2Opnd, brtarget,	18650	COP2Opnd, brtarget,
18651	/* BC2EQZC_MMR6 */	18651	/* BC2EQZC_MMR6 */
18652	COP2Opnd, brtarget_mm,	18652	COP2Opnd, brtarget_mm,
18653	/* BC2NEZ */	18653	/* BC2NEZ */
18654	COP2Opnd, brtarget,	18654	COP2Opnd, brtarget,
18655	/* BC2NEZC_MMR6 */	18655	/* BC2NEZC_MMR6 */
18656	COP2Opnd, brtarget_mm,	18656	COP2Opnd, brtarget_mm,
18657	/* BCLRI_B */	18657	/* BCLRI_B */
18658	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	18658	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18659	/* BCLRI_D */	18659	/* BCLRI_D */
18660	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	18660	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18661	/* BCLRI_H */	18661	/* BCLRI_H */
18662	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	18662	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18663	/* BCLRI_W */	18663	/* BCLRI_W */
18664	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18664	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18665	/* BCLR_B */	18665	/* BCLR_B */
18666	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18666	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18667	/* BCLR_D */	18667	/* BCLR_D */
18668	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18668	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18669	/* BCLR_H */	18669	/* BCLR_H */
18670	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18670	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18671	/* BCLR_W */	18671	/* BCLR_W */
18672	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18672	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18673	/* BC_MMR6 */	18673	/* BC_MMR6 */
18674	brtarget26_mm,	18674	brtarget26_mm,
18675	/* BEQ */	18675	/* BEQ */
18676	GPR32Opnd, GPR32Opnd, brtarget,	18676	GPR32Opnd, GPR32Opnd, brtarget,
18677	/* BEQ64 */	18677	/* BEQ64 */
18678	GPR64Opnd, GPR64Opnd, brtarget,	18678	GPR64Opnd, GPR64Opnd, brtarget,
18679	/* BEQC */	18679	/* BEQC */
18680	GPR32Opnd, GPR32Opnd, brtarget,	18680	GPR32Opnd, GPR32Opnd, brtarget,
18681	/* BEQC64 */	18681	/* BEQC64 */
18682	GPR64Opnd, GPR64Opnd, brtarget,	18682	GPR64Opnd, GPR64Opnd, brtarget,
18683	/* BEQC_MMR6 */	18683	/* BEQC_MMR6 */
18684	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18684	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18685	/* BEQL */	18685	/* BEQL */
18686	GPR32Opnd, GPR32Opnd, brtarget,	18686	GPR32Opnd, GPR32Opnd, brtarget,
18687	/* BEQZ16_MM */	18687	/* BEQZ16_MM */
18688	GPRMM16Opnd, brtarget7_mm,	18688	GPRMM16Opnd, brtarget7_mm,
18689	/* BEQZALC */	18689	/* BEQZALC */
18690	GPR32Opnd, brtarget,	18690	GPR32Opnd, brtarget,
18691	/* BEQZALC_MMR6 */	18691	/* BEQZALC_MMR6 */
18692	GPR32Opnd, brtarget_mm,	18692	GPR32Opnd, brtarget_mm,
18693	/* BEQZC */	18693	/* BEQZC */
18694	GPR32Opnd, brtarget21,	18694	GPR32Opnd, brtarget21,
18695	/* BEQZC16_MMR6 */	18695	/* BEQZC16_MMR6 */
18696	GPRMM16Opnd, brtarget7_mm,	18696	GPRMM16Opnd, brtarget7_mm,
18697	/* BEQZC64 */	18697	/* BEQZC64 */
18698	GPR64Opnd, brtarget21,	18698	GPR64Opnd, brtarget21,
18699	/* BEQZC_MM */	18699	/* BEQZC_MM */
18700	GPR32Opnd, brtarget_mm,	18700	GPR32Opnd, brtarget_mm,
18701	/* BEQZC_MMR6 */	18701	/* BEQZC_MMR6 */
18702	GPR32Opnd, brtarget21_mm,	18702	GPR32Opnd, brtarget21_mm,
18703	/* BEQ_MM */	18703	/* BEQ_MM */
18704	GPR32Opnd, GPR32Opnd, brtarget_mm,	18704	GPR32Opnd, GPR32Opnd, brtarget_mm,
18705	/* BGEC */	18705	/* BGEC */
18706	GPR32Opnd, GPR32Opnd, brtarget,	18706	GPR32Opnd, GPR32Opnd, brtarget,
18707	/* BGEC64 */	18707	/* BGEC64 */
18708	GPR64Opnd, GPR64Opnd, brtarget,	18708	GPR64Opnd, GPR64Opnd, brtarget,
18709	/* BGEC_MMR6 */	18709	/* BGEC_MMR6 */
18710	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18710	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18711	/* BGEUC */	18711	/* BGEUC */
18712	GPR32Opnd, GPR32Opnd, brtarget,	18712	GPR32Opnd, GPR32Opnd, brtarget,
18713	/* BGEUC64 */	18713	/* BGEUC64 */
18714	GPR64Opnd, GPR64Opnd, brtarget,	18714	GPR64Opnd, GPR64Opnd, brtarget,
18715	/* BGEUC_MMR6 */	18715	/* BGEUC_MMR6 */
18716	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18716	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18717	/* BGEZ */	18717	/* BGEZ */
18718	GPR32Opnd, brtarget,	18718	GPR32Opnd, brtarget,
18719	/* BGEZ64 */	18719	/* BGEZ64 */
18720	GPR64Opnd, brtarget,	18720	GPR64Opnd, brtarget,
18721	/* BGEZAL */	18721	/* BGEZAL */
18722	GPR32Opnd, brtarget,	18722	GPR32Opnd, brtarget,
18723	/* BGEZALC */	18723	/* BGEZALC */
18724	GPR32Opnd, brtarget,	18724	GPR32Opnd, brtarget,
18725	/* BGEZALC_MMR6 */	18725	/* BGEZALC_MMR6 */
18726	GPR32Opnd, brtarget_mm,	18726	GPR32Opnd, brtarget_mm,
18727	/* BGEZALL */	18727	/* BGEZALL */
18728	GPR32Opnd, brtarget,	18728	GPR32Opnd, brtarget,
18729	/* BGEZALS_MM */	18729	/* BGEZALS_MM */
18730	GPR32Opnd, brtarget_mm,	18730	GPR32Opnd, brtarget_mm,
18731	/* BGEZAL_MM */	18731	/* BGEZAL_MM */
18732	GPR32Opnd, brtarget_mm,	18732	GPR32Opnd, brtarget_mm,
18733	/* BGEZC */	18733	/* BGEZC */
18734	GPR32Opnd, brtarget,	18734	GPR32Opnd, brtarget,
18735	/* BGEZC64 */	18735	/* BGEZC64 */
18736	GPR64Opnd, brtarget,	18736	GPR64Opnd, brtarget,
18737	/* BGEZC_MMR6 */	18737	/* BGEZC_MMR6 */
18738	GPR32Opnd, brtarget_lsl2_mm,	18738	GPR32Opnd, brtarget_lsl2_mm,
18739	/* BGEZL */	18739	/* BGEZL */
18740	GPR32Opnd, brtarget,	18740	GPR32Opnd, brtarget,
18741	/* BGEZ_MM */	18741	/* BGEZ_MM */
18742	GPR32Opnd, brtarget_mm,	18742	GPR32Opnd, brtarget_mm,
18743	/* BGTZ */	18743	/* BGTZ */
18744	GPR32Opnd, brtarget,	18744	GPR32Opnd, brtarget,
18745	/* BGTZ64 */	18745	/* BGTZ64 */
18746	GPR64Opnd, brtarget,	18746	GPR64Opnd, brtarget,
18747	/* BGTZALC */	18747	/* BGTZALC */
18748	GPR32Opnd, brtarget,	18748	GPR32Opnd, brtarget,
18749	/* BGTZALC_MMR6 */	18749	/* BGTZALC_MMR6 */
18750	GPR32Opnd, brtarget_mm,	18750	GPR32Opnd, brtarget_mm,
18751	/* BGTZC */	18751	/* BGTZC */
18752	GPR32Opnd, brtarget,	18752	GPR32Opnd, brtarget,
18753	/* BGTZC64 */	18753	/* BGTZC64 */
18754	GPR64Opnd, brtarget,	18754	GPR64Opnd, brtarget,
18755	/* BGTZC_MMR6 */	18755	/* BGTZC_MMR6 */
18756	GPR32Opnd, brtarget_lsl2_mm,	18756	GPR32Opnd, brtarget_lsl2_mm,
18757	/* BGTZL */	18757	/* BGTZL */
18758	GPR32Opnd, brtarget,	18758	GPR32Opnd, brtarget,
18759	/* BGTZ_MM */	18759	/* BGTZ_MM */
18760	GPR32Opnd, brtarget_mm,	18760	GPR32Opnd, brtarget_mm,
18761	/* BINSLI_B */	18761	/* BINSLI_B */
18762	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	18762	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18763	/* BINSLI_D */	18763	/* BINSLI_D */
18764	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	18764	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18765	/* BINSLI_H */	18765	/* BINSLI_H */
18766	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	18766	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18767	/* BINSLI_W */	18767	/* BINSLI_W */
18768	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18768	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18769	/* BINSL_B */	18769	/* BINSL_B */
18770	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18770	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18771	/* BINSL_D */	18771	/* BINSL_D */
18772	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18772	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18773	/* BINSL_H */	18773	/* BINSL_H */
18774	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18774	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18775	/* BINSL_W */	18775	/* BINSL_W */
18776	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18776	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18777	/* BINSRI_B */	18777	/* BINSRI_B */
18778	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	18778	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18779	/* BINSRI_D */	18779	/* BINSRI_D */
18780	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	18780	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18781	/* BINSRI_H */	18781	/* BINSRI_H */
18782	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	18782	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18783	/* BINSRI_W */	18783	/* BINSRI_W */
18784	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18784	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18785	/* BINSR_B */	18785	/* BINSR_B */
18786	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18786	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18787	/* BINSR_D */	18787	/* BINSR_D */
18788	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18788	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18789	/* BINSR_H */	18789	/* BINSR_H */
18790	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18790	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18791	/* BINSR_W */	18791	/* BINSR_W */
18792	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18792	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18793	/* BITREV */	18793	/* BITREV */
18794	GPR32Opnd, GPR32Opnd,	18794	GPR32Opnd, GPR32Opnd,
18795	/* BITREV_MM */	18795	/* BITREV_MM */
18796	GPR32Opnd, GPR32Opnd,	18796	GPR32Opnd, GPR32Opnd,
18797	/* BITSWAP */	18797	/* BITSWAP */
18798	GPR32Opnd, GPR32Opnd,	18798	GPR32Opnd, GPR32Opnd,
18799	/* BITSWAP_MMR6 */	18799	/* BITSWAP_MMR6 */
18800	GPR32Opnd, GPR32Opnd,	18800	GPR32Opnd, GPR32Opnd,
18801	/* BLEZ */	18801	/* BLEZ */
18802	GPR32Opnd, brtarget,	18802	GPR32Opnd, brtarget,
18803	/* BLEZ64 */	18803	/* BLEZ64 */
18804	GPR64Opnd, brtarget,	18804	GPR64Opnd, brtarget,
18805	/* BLEZALC */	18805	/* BLEZALC */
18806	GPR32Opnd, brtarget,	18806	GPR32Opnd, brtarget,
18807	/* BLEZALC_MMR6 */	18807	/* BLEZALC_MMR6 */
18808	GPR32Opnd, brtarget_mm,	18808	GPR32Opnd, brtarget_mm,
18809	/* BLEZC */	18809	/* BLEZC */
18810	GPR32Opnd, brtarget,	18810	GPR32Opnd, brtarget,
18811	/* BLEZC64 */	18811	/* BLEZC64 */
18812	GPR64Opnd, brtarget,	18812	GPR64Opnd, brtarget,
18813	/* BLEZC_MMR6 */	18813	/* BLEZC_MMR6 */
18814	GPR32Opnd, brtarget_lsl2_mm,	18814	GPR32Opnd, brtarget_lsl2_mm,
18815	/* BLEZL */	18815	/* BLEZL */
18816	GPR32Opnd, brtarget,	18816	GPR32Opnd, brtarget,
18817	/* BLEZ_MM */	18817	/* BLEZ_MM */
18818	GPR32Opnd, brtarget_mm,	18818	GPR32Opnd, brtarget_mm,
18819	/* BLTC */	18819	/* BLTC */
18820	GPR32Opnd, GPR32Opnd, brtarget,	18820	GPR32Opnd, GPR32Opnd, brtarget,
18821	/* BLTC64 */	18821	/* BLTC64 */
18822	GPR64Opnd, GPR64Opnd, brtarget,	18822	GPR64Opnd, GPR64Opnd, brtarget,
18823	/* BLTC_MMR6 */	18823	/* BLTC_MMR6 */
18824	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18824	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18825	/* BLTUC */	18825	/* BLTUC */
18826	GPR32Opnd, GPR32Opnd, brtarget,	18826	GPR32Opnd, GPR32Opnd, brtarget,
18827	/* BLTUC64 */	18827	/* BLTUC64 */
18828	GPR64Opnd, GPR64Opnd, brtarget,	18828	GPR64Opnd, GPR64Opnd, brtarget,
18829	/* BLTUC_MMR6 */	18829	/* BLTUC_MMR6 */
18830	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18830	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18831	/* BLTZ */	18831	/* BLTZ */
18832	GPR32Opnd, brtarget,	18832	GPR32Opnd, brtarget,
18833	/* BLTZ64 */	18833	/* BLTZ64 */
18834	GPR64Opnd, brtarget,	18834	GPR64Opnd, brtarget,
18835	/* BLTZAL */	18835	/* BLTZAL */
18836	GPR32Opnd, brtarget,	18836	GPR32Opnd, brtarget,
18837	/* BLTZALC */	18837	/* BLTZALC */
18838	GPR32Opnd, brtarget,	18838	GPR32Opnd, brtarget,
18839	/* BLTZALC_MMR6 */	18839	/* BLTZALC_MMR6 */
18840	GPR32Opnd, brtarget_mm,	18840	GPR32Opnd, brtarget_mm,
18841	/* BLTZALL */	18841	/* BLTZALL */
18842	GPR32Opnd, brtarget,	18842	GPR32Opnd, brtarget,
18843	/* BLTZALS_MM */	18843	/* BLTZALS_MM */
18844	GPR32Opnd, brtarget_mm,	18844	GPR32Opnd, brtarget_mm,
18845	/* BLTZAL_MM */	18845	/* BLTZAL_MM */
18846	GPR32Opnd, brtarget_mm,	18846	GPR32Opnd, brtarget_mm,
18847	/* BLTZC */	18847	/* BLTZC */
18848	GPR32Opnd, brtarget,	18848	GPR32Opnd, brtarget,
18849	/* BLTZC64 */	18849	/* BLTZC64 */
18850	GPR64Opnd, brtarget,	18850	GPR64Opnd, brtarget,
18851	/* BLTZC_MMR6 */	18851	/* BLTZC_MMR6 */
18852	GPR32Opnd, brtarget_lsl2_mm,	18852	GPR32Opnd, brtarget_lsl2_mm,
18853	/* BLTZL */	18853	/* BLTZL */
18854	GPR32Opnd, brtarget,	18854	GPR32Opnd, brtarget,
18855	/* BLTZ_MM */	18855	/* BLTZ_MM */
18856	GPR32Opnd, brtarget_mm,	18856	GPR32Opnd, brtarget_mm,
18857	/* BMNZI_B */	18857	/* BMNZI_B */
18858	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	18858	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
18859	/* BMNZ_V */	18859	/* BMNZ_V */
18860	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18860	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18861	/* BMZI_B */	18861	/* BMZI_B */
18862	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	18862	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
18863	/* BMZ_V */	18863	/* BMZ_V */
18864	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18864	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18865	/* BNE */	18865	/* BNE */
18866	GPR32Opnd, GPR32Opnd, brtarget,	18866	GPR32Opnd, GPR32Opnd, brtarget,
18867	/* BNE64 */	18867	/* BNE64 */
18868	GPR64Opnd, GPR64Opnd, brtarget,	18868	GPR64Opnd, GPR64Opnd, brtarget,
18869	/* BNEC */	18869	/* BNEC */
18870	GPR32Opnd, GPR32Opnd, brtarget,	18870	GPR32Opnd, GPR32Opnd, brtarget,
18871	/* BNEC64 */	18871	/* BNEC64 */
18872	GPR64Opnd, GPR64Opnd, brtarget,	18872	GPR64Opnd, GPR64Opnd, brtarget,
18873	/* BNEC_MMR6 */	18873	/* BNEC_MMR6 */
18874	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	18874	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18875	/* BNEGI_B */	18875	/* BNEGI_B */
18876	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	18876	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18877	/* BNEGI_D */	18877	/* BNEGI_D */
18878	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	18878	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18879	/* BNEGI_H */	18879	/* BNEGI_H */
18880	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	18880	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18881	/* BNEGI_W */	18881	/* BNEGI_W */
18882	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18882	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18883	/* BNEG_B */	18883	/* BNEG_B */
18884	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18884	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18885	/* BNEG_D */	18885	/* BNEG_D */
18886	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18886	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18887	/* BNEG_H */	18887	/* BNEG_H */
18888	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18888	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18889	/* BNEG_W */	18889	/* BNEG_W */
18890	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18890	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18891	/* BNEL */	18891	/* BNEL */
18892	GPR32Opnd, GPR32Opnd, brtarget,	18892	GPR32Opnd, GPR32Opnd, brtarget,
18893	/* BNEZ16_MM */	18893	/* BNEZ16_MM */
18894	GPRMM16Opnd, brtarget7_mm,	18894	GPRMM16Opnd, brtarget7_mm,
18895	/* BNEZALC */	18895	/* BNEZALC */
18896	GPR32Opnd, brtarget,	18896	GPR32Opnd, brtarget,
18897	/* BNEZALC_MMR6 */	18897	/* BNEZALC_MMR6 */
18898	GPR32Opnd, brtarget_mm,	18898	GPR32Opnd, brtarget_mm,
18899	/* BNEZC */	18899	/* BNEZC */
18900	GPR32Opnd, brtarget21,	18900	GPR32Opnd, brtarget21,
18901	/* BNEZC16_MMR6 */	18901	/* BNEZC16_MMR6 */
18902	GPRMM16Opnd, brtarget7_mm,	18902	GPRMM16Opnd, brtarget7_mm,
18903	/* BNEZC64 */	18903	/* BNEZC64 */
18904	GPR64Opnd, brtarget21,	18904	GPR64Opnd, brtarget21,
18905	/* BNEZC_MM */	18905	/* BNEZC_MM */
18906	GPR32Opnd, brtarget_mm,	18906	GPR32Opnd, brtarget_mm,
18907	/* BNEZC_MMR6 */	18907	/* BNEZC_MMR6 */
18908	GPR32Opnd, brtarget21_mm,	18908	GPR32Opnd, brtarget21_mm,
18909	/* BNE_MM */	18909	/* BNE_MM */
18910	GPR32Opnd, GPR32Opnd, brtarget_mm,	18910	GPR32Opnd, GPR32Opnd, brtarget_mm,
18911	/* BNVC */	18911	/* BNVC */
18912	GPR32Opnd, GPR32Opnd, brtarget,	18912	GPR32Opnd, GPR32Opnd, brtarget,
18913	/* BNVC_MMR6 */	18913	/* BNVC_MMR6 */
18914	GPR32Opnd, GPR32Opnd, brtargetr6,	18914	GPR32Opnd, GPR32Opnd, brtargetr6,
18915	/* BNZ_B */	18915	/* BNZ_B */
18916	MSA128BOpnd, brtarget,	18916	MSA128BOpnd, brtarget,
18917	/* BNZ_D */	18917	/* BNZ_D */
18918	MSA128DOpnd, brtarget,	18918	MSA128DOpnd, brtarget,
18919	/* BNZ_H */	18919	/* BNZ_H */
18920	MSA128HOpnd, brtarget,	18920	MSA128HOpnd, brtarget,
18921	/* BNZ_V */	18921	/* BNZ_V */
18922	MSA128BOpnd, brtarget,	18922	MSA128BOpnd, brtarget,
18923	/* BNZ_W */	18923	/* BNZ_W */
18924	MSA128WOpnd, brtarget,	18924	MSA128WOpnd, brtarget,
18925	/* BOVC */	18925	/* BOVC */
18926	GPR32Opnd, GPR32Opnd, brtarget,	18926	GPR32Opnd, GPR32Opnd, brtarget,
18927	/* BOVC_MMR6 */	18927	/* BOVC_MMR6 */
18928	GPR32Opnd, GPR32Opnd, brtargetr6,	18928	GPR32Opnd, GPR32Opnd, brtargetr6,
18929	/* BPOSGE32 */	18929	/* BPOSGE32 */
18930	brtarget,	18930	brtarget,
18931	/* BPOSGE32C_MMR3 */	18931	/* BPOSGE32C_MMR3 */
18932	brtarget1SImm16,	18932	brtarget1SImm16,
18933	/* BPOSGE32_MM */	18933	/* BPOSGE32_MM */
18934	brtarget_mm,	18934	brtarget_mm,
18935	/* BREAK */	18935	/* BREAK */
18936	uimm10, uimm10,	18936	uimm10, uimm10,
18937	/* BREAK16_MM */	18937	/* BREAK16_MM */
18938	uimm4,	18938	uimm4,
18939	/* BREAK16_MMR6 */	18939	/* BREAK16_MMR6 */
18940	uimm4,	18940	uimm4,
18941	/* BREAK_MM */	18941	/* BREAK_MM */
18942	uimm10, uimm10,	18942	uimm10, uimm10,
18943	/* BREAK_MMR6 */	18943	/* BREAK_MMR6 */
18944	uimm10, uimm10,	18944	uimm10, uimm10,
18945	/* BSELI_B */	18945	/* BSELI_B */
18946	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	18946	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
18947	/* BSEL_V */	18947	/* BSEL_V */
18948	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18948	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18949	/* BSETI_B */	18949	/* BSETI_B */
18950	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	18950	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18951	/* BSETI_D */	18951	/* BSETI_D */
18952	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	18952	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18953	/* BSETI_H */	18953	/* BSETI_H */
18954	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	18954	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18955	/* BSETI_W */	18955	/* BSETI_W */
18956	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	18956	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18957	/* BSET_B */	18957	/* BSET_B */
18958	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	18958	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18959	/* BSET_D */	18959	/* BSET_D */
18960	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	18960	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18961	/* BSET_H */	18961	/* BSET_H */
18962	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	18962	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18963	/* BSET_W */	18963	/* BSET_W */
18964	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	18964	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18965	/* BZ_B */	18965	/* BZ_B */
18966	MSA128BOpnd, brtarget,	18966	MSA128BOpnd, brtarget,
18967	/* BZ_D */	18967	/* BZ_D */
18968	MSA128DOpnd, brtarget,	18968	MSA128DOpnd, brtarget,
18969	/* BZ_H */	18969	/* BZ_H */
18970	MSA128HOpnd, brtarget,	18970	MSA128HOpnd, brtarget,
18971	/* BZ_V */	18971	/* BZ_V */
18972	MSA128BOpnd, brtarget,	18972	MSA128BOpnd, brtarget,
18973	/* BZ_W */	18973	/* BZ_W */
18974	MSA128WOpnd, brtarget,	18974	MSA128WOpnd, brtarget,
18975	/* BeqzRxImm16 */	18975	/* BeqzRxImm16 */
18976	CPU16Regs, brtarget,	18976	CPU16Regs, brtarget,
18977	/* BeqzRxImmX16 */	18977	/* BeqzRxImmX16 */
18978	CPU16Regs, brtarget,	18978	CPU16Regs, brtarget,
18979	/* Bimm16 */	18979	/* Bimm16 */
18980	brtarget,	18980	brtarget,
18981	/* BimmX16 */	18981	/* BimmX16 */
18982	brtarget,	18982	brtarget,
18983	/* BnezRxImm16 */	18983	/* BnezRxImm16 */
18984	CPU16Regs, brtarget,	18984	CPU16Regs, brtarget,
18985	/* BnezRxImmX16 */	18985	/* BnezRxImmX16 */
18986	CPU16Regs, brtarget,	18986	CPU16Regs, brtarget,
18987	/* Break16 */	18987	/* Break16 */
18988	/* Bteqz16 */	18988	/* Bteqz16 */
18989	simm16,	18989	simm16,
18990	/* BteqzX16 */	18990	/* BteqzX16 */
18991	simm16,	18991	simm16,
18992	/* Btnez16 */	18992	/* Btnez16 */
18993	simm16,	18993	simm16,
18994	/* BtnezX16 */	18994	/* BtnezX16 */
18995	simm16,	18995	simm16,
18996	/* CACHE */	18996	/* CACHE */
18997	-1, simm16, uimm5,	18997	-1, simm16, uimm5,
18998	/* CACHEE */	18998	/* CACHEE */
18999	-1, simm9, uimm5,	18999	-1, simm9, uimm5,
19000	/* CACHEE_MM */	19000	/* CACHEE_MM */
19001	-1, simm9, uimm5,	19001	-1, simm9, uimm5,
19002	/* CACHE_MM */	19002	/* CACHE_MM */
19003	-1, simm12, uimm5,	19003	-1, simm12, uimm5,
19004	/* CACHE_MMR6 */	19004	/* CACHE_MMR6 */
19005	-1, simm12, uimm5,	19005	-1, simm12, uimm5,
19006	/* CACHE_R6 */	19006	/* CACHE_R6 */
19007	-1, simm9, uimm5,	19007	-1, simm9, uimm5,
19008	/* CEIL_L_D64 */	19008	/* CEIL_L_D64 */
19009	FGR64Opnd, FGR64Opnd,	19009	FGR64Opnd, FGR64Opnd,
19010	/* CEIL_L_D_MMR6 */	19010	/* CEIL_L_D_MMR6 */
19011	FGR64Opnd, FGR64Opnd,	19011	FGR64Opnd, FGR64Opnd,
19012	/* CEIL_L_S */	19012	/* CEIL_L_S */
19013	FGR64Opnd, FGR32Opnd,	19013	FGR64Opnd, FGR32Opnd,
19014	/* CEIL_L_S_MMR6 */	19014	/* CEIL_L_S_MMR6 */
19015	FGR64Opnd, FGR32Opnd,	19015	FGR64Opnd, FGR32Opnd,
19016	/* CEIL_W_D32 */	19016	/* CEIL_W_D32 */
19017	FGR32Opnd, AFGR64Opnd,	19017	FGR32Opnd, AFGR64Opnd,
19018	/* CEIL_W_D64 */	19018	/* CEIL_W_D64 */
19019	FGR32Opnd, FGR64Opnd,	19019	FGR32Opnd, FGR64Opnd,
19020	/* CEIL_W_D_MMR6 */	19020	/* CEIL_W_D_MMR6 */
19021	FGR32Opnd, AFGR64Opnd,	19021	FGR32Opnd, AFGR64Opnd,
19022	/* CEIL_W_MM */	19022	/* CEIL_W_MM */
19023	FGR32Opnd, AFGR64Opnd,	19023	FGR32Opnd, AFGR64Opnd,
19024	/* CEIL_W_S */	19024	/* CEIL_W_S */
19025	FGR32Opnd, FGR32Opnd,	19025	FGR32Opnd, FGR32Opnd,
19026	/* CEIL_W_S_MM */	19026	/* CEIL_W_S_MM */
19027	FGR32Opnd, FGR32Opnd,	19027	FGR32Opnd, FGR32Opnd,
19028	/* CEIL_W_S_MMR6 */	19028	/* CEIL_W_S_MMR6 */
19029	FGR32Opnd, FGR32Opnd,	19029	FGR32Opnd, FGR32Opnd,
19030	/* CEQI_B */	19030	/* CEQI_B */
19031	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	19031	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19032	/* CEQI_D */	19032	/* CEQI_D */
19033	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	19033	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19034	/* CEQI_H */	19034	/* CEQI_H */
19035	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	19035	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19036	/* CEQI_W */	19036	/* CEQI_W */
19037	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	19037	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19038	/* CEQ_B */	19038	/* CEQ_B */
19039	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19039	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19040	/* CEQ_D */	19040	/* CEQ_D */
19041	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19041	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19042	/* CEQ_H */	19042	/* CEQ_H */
19043	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19043	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19044	/* CEQ_W */	19044	/* CEQ_W */
19045	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19045	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19046	/* CFC1 */	19046	/* CFC1 */
19047	GPR32Opnd, CCROpnd,	19047	GPR32Opnd, CCROpnd,
19048	/* CFC1_MM */	19048	/* CFC1_MM */
19049	GPR32Opnd, CCROpnd,	19049	GPR32Opnd, CCROpnd,
19050	/* CFC2_MM */	19050	/* CFC2_MM */
19051	GPR32Opnd, COP2Opnd,	19051	GPR32Opnd, COP2Opnd,
19052	/* CFCMSA */	19052	/* CFCMSA */
19053	GPR32Opnd, MSA128CROpnd,	19053	GPR32Opnd, MSA128CROpnd,
19054	/* CINS */	19054	/* CINS */
19055	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	19055	GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19056	/* CINS32 */	19056	/* CINS32 */
19057	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	19057	GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19058	/* CINS64_32 */	19058	/* CINS64_32 */
19059	GPR64Opnd, GPR32Opnd, uimm5, uimm5,	19059	GPR64Opnd, GPR32Opnd, uimm5, uimm5,
19060	/* CINS_i32 */	19060	/* CINS_i32 */
19061	GPR32Opnd, GPR32Opnd, uimm5, uimm5,	19061	GPR32Opnd, GPR32Opnd, uimm5, uimm5,
19062	/* CLASS_D */	19062	/* CLASS_D */
19063	FGR64Opnd, FGR64Opnd,	19063	FGR64Opnd, FGR64Opnd,
19064	/* CLASS_D_MMR6 */	19064	/* CLASS_D_MMR6 */
19065	FGR64Opnd, FGR64Opnd,	19065	FGR64Opnd, FGR64Opnd,
19066	/* CLASS_S */	19066	/* CLASS_S */
19067	FGR32Opnd, FGR32Opnd,	19067	FGR32Opnd, FGR32Opnd,
19068	/* CLASS_S_MMR6 */	19068	/* CLASS_S_MMR6 */
19069	FGR32Opnd, FGR32Opnd,	19069	FGR32Opnd, FGR32Opnd,
19070	/* CLEI_S_B */	19070	/* CLEI_S_B */
19071	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	19071	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19072	/* CLEI_S_D */	19072	/* CLEI_S_D */
19073	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	19073	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19074	/* CLEI_S_H */	19074	/* CLEI_S_H */
19075	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	19075	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19076	/* CLEI_S_W */	19076	/* CLEI_S_W */
19077	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	19077	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19078	/* CLEI_U_B */	19078	/* CLEI_U_B */
19079	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	19079	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
19080	/* CLEI_U_D */	19080	/* CLEI_U_D */
19081	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	19081	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
19082	/* CLEI_U_H */	19082	/* CLEI_U_H */
19083	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	19083	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
19084	/* CLEI_U_W */	19084	/* CLEI_U_W */
19085	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	19085	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19086	/* CLE_S_B */	19086	/* CLE_S_B */
19087	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19087	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19088	/* CLE_S_D */	19088	/* CLE_S_D */
19089	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19089	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19090	/* CLE_S_H */	19090	/* CLE_S_H */
19091	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19091	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19092	/* CLE_S_W */	19092	/* CLE_S_W */
19093	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19093	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19094	/* CLE_U_B */	19094	/* CLE_U_B */
19095	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19095	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19096	/* CLE_U_D */	19096	/* CLE_U_D */
19097	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19097	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19098	/* CLE_U_H */	19098	/* CLE_U_H */
19099	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19099	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19100	/* CLE_U_W */	19100	/* CLE_U_W */
19101	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19101	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19102	/* CLO */	19102	/* CLO */
19103	GPR32Opnd, GPR32Opnd,	19103	GPR32Opnd, GPR32Opnd,
19104	/* CLO_MM */	19104	/* CLO_MM */
19105	GPR32Opnd, GPR32Opnd,	19105	GPR32Opnd, GPR32Opnd,
19106	/* CLO_MMR6 */	19106	/* CLO_MMR6 */
19107	GPR32Opnd, GPR32Opnd,	19107	GPR32Opnd, GPR32Opnd,
19108	/* CLO_R6 */	19108	/* CLO_R6 */
19109	GPR32Opnd, GPR32Opnd,	19109	GPR32Opnd, GPR32Opnd,
19110	/* CLTI_S_B */	19110	/* CLTI_S_B */
19111	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	19111	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19112	/* CLTI_S_D */	19112	/* CLTI_S_D */
19113	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	19113	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19114	/* CLTI_S_H */	19114	/* CLTI_S_H */
19115	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	19115	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19116	/* CLTI_S_W */	19116	/* CLTI_S_W */
19117	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	19117	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19118	/* CLTI_U_B */	19118	/* CLTI_U_B */
19119	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	19119	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
19120	/* CLTI_U_D */	19120	/* CLTI_U_D */
19121	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	19121	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
19122	/* CLTI_U_H */	19122	/* CLTI_U_H */
19123	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	19123	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
19124	/* CLTI_U_W */	19124	/* CLTI_U_W */
19125	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	19125	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19126	/* CLT_S_B */	19126	/* CLT_S_B */
19127	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19127	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19128	/* CLT_S_D */	19128	/* CLT_S_D */
19129	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19129	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19130	/* CLT_S_H */	19130	/* CLT_S_H */
19131	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19131	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19132	/* CLT_S_W */	19132	/* CLT_S_W */
19133	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19133	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19134	/* CLT_U_B */	19134	/* CLT_U_B */
19135	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19135	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19136	/* CLT_U_D */	19136	/* CLT_U_D */
19137	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19137	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19138	/* CLT_U_H */	19138	/* CLT_U_H */
19139	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19139	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19140	/* CLT_U_W */	19140	/* CLT_U_W */
19141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19142	/* CLZ */	19142	/* CLZ */
19143	GPR32Opnd, GPR32Opnd,	19143	GPR32Opnd, GPR32Opnd,
19144	/* CLZ_MM */	19144	/* CLZ_MM */
19145	GPR32Opnd, GPR32Opnd,	19145	GPR32Opnd, GPR32Opnd,
19146	/* CLZ_MMR6 */	19146	/* CLZ_MMR6 */
19147	GPR32Opnd, GPR32Opnd,	19147	GPR32Opnd, GPR32Opnd,
19148	/* CLZ_R6 */	19148	/* CLZ_R6 */
19149	GPR32Opnd, GPR32Opnd,	19149	GPR32Opnd, GPR32Opnd,
19150	/* CMPGDU_EQ_QB */	19150	/* CMPGDU_EQ_QB */
19151	GPR32Opnd, DSPROpnd, DSPROpnd,	19151	GPR32Opnd, DSPROpnd, DSPROpnd,
19152	/* CMPGDU_EQ_QB_MMR2 */	19152	/* CMPGDU_EQ_QB_MMR2 */
19153	GPR32Opnd, DSPROpnd, DSPROpnd,	19153	GPR32Opnd, DSPROpnd, DSPROpnd,
19154	/* CMPGDU_LE_QB */	19154	/* CMPGDU_LE_QB */
19155	GPR32Opnd, DSPROpnd, DSPROpnd,	19155	GPR32Opnd, DSPROpnd, DSPROpnd,
19156	/* CMPGDU_LE_QB_MMR2 */	19156	/* CMPGDU_LE_QB_MMR2 */
19157	GPR32Opnd, DSPROpnd, DSPROpnd,	19157	GPR32Opnd, DSPROpnd, DSPROpnd,
19158	/* CMPGDU_LT_QB */	19158	/* CMPGDU_LT_QB */
19159	GPR32Opnd, DSPROpnd, DSPROpnd,	19159	GPR32Opnd, DSPROpnd, DSPROpnd,
19160	/* CMPGDU_LT_QB_MMR2 */	19160	/* CMPGDU_LT_QB_MMR2 */
19161	GPR32Opnd, DSPROpnd, DSPROpnd,	19161	GPR32Opnd, DSPROpnd, DSPROpnd,
19162	/* CMPGU_EQ_QB */	19162	/* CMPGU_EQ_QB */
19163	GPR32Opnd, DSPROpnd, DSPROpnd,	19163	GPR32Opnd, DSPROpnd, DSPROpnd,
19164	/* CMPGU_EQ_QB_MM */	19164	/* CMPGU_EQ_QB_MM */
19165	GPR32Opnd, DSPROpnd, DSPROpnd,	19165	GPR32Opnd, DSPROpnd, DSPROpnd,
19166	/* CMPGU_LE_QB */	19166	/* CMPGU_LE_QB */
19167	GPR32Opnd, DSPROpnd, DSPROpnd,	19167	GPR32Opnd, DSPROpnd, DSPROpnd,
19168	/* CMPGU_LE_QB_MM */	19168	/* CMPGU_LE_QB_MM */
19169	GPR32Opnd, DSPROpnd, DSPROpnd,	19169	GPR32Opnd, DSPROpnd, DSPROpnd,
19170	/* CMPGU_LT_QB */	19170	/* CMPGU_LT_QB */
19171	GPR32Opnd, DSPROpnd, DSPROpnd,	19171	GPR32Opnd, DSPROpnd, DSPROpnd,
19172	/* CMPGU_LT_QB_MM */	19172	/* CMPGU_LT_QB_MM */
19173	GPR32Opnd, DSPROpnd, DSPROpnd,	19173	GPR32Opnd, DSPROpnd, DSPROpnd,
19174	/* CMPU_EQ_QB */	19174	/* CMPU_EQ_QB */
19175	DSPROpnd, DSPROpnd,	19175	DSPROpnd, DSPROpnd,
19176	/* CMPU_EQ_QB_MM */	19176	/* CMPU_EQ_QB_MM */
19177	DSPROpnd, DSPROpnd,	19177	DSPROpnd, DSPROpnd,
19178	/* CMPU_LE_QB */	19178	/* CMPU_LE_QB */
19179	DSPROpnd, DSPROpnd,	19179	DSPROpnd, DSPROpnd,
19180	/* CMPU_LE_QB_MM */	19180	/* CMPU_LE_QB_MM */
19181	DSPROpnd, DSPROpnd,	19181	DSPROpnd, DSPROpnd,
19182	/* CMPU_LT_QB */	19182	/* CMPU_LT_QB */
19183	DSPROpnd, DSPROpnd,	19183	DSPROpnd, DSPROpnd,
19184	/* CMPU_LT_QB_MM */	19184	/* CMPU_LT_QB_MM */
19185	DSPROpnd, DSPROpnd,	19185	DSPROpnd, DSPROpnd,
19186	/* CMP_AF_D_MMR6 */	19186	/* CMP_AF_D_MMR6 */
19187	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19187	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19188	/* CMP_AF_S_MMR6 */	19188	/* CMP_AF_S_MMR6 */
19189	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19189	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19190	/* CMP_EQ_D */	19190	/* CMP_EQ_D */
19191	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19191	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19192	/* CMP_EQ_D_MMR6 */	19192	/* CMP_EQ_D_MMR6 */
19193	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19193	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19194	/* CMP_EQ_PH */	19194	/* CMP_EQ_PH */
19195	DSPROpnd, DSPROpnd,	19195	DSPROpnd, DSPROpnd,
19196	/* CMP_EQ_PH_MM */	19196	/* CMP_EQ_PH_MM */
19197	DSPROpnd, DSPROpnd,	19197	DSPROpnd, DSPROpnd,
19198	/* CMP_EQ_S */	19198	/* CMP_EQ_S */
19199	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19199	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19200	/* CMP_EQ_S_MMR6 */	19200	/* CMP_EQ_S_MMR6 */
19201	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19201	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19202	/* CMP_F_D */	19202	/* CMP_F_D */
19203	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19203	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19204	/* CMP_F_S */	19204	/* CMP_F_S */
19205	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19205	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19206	/* CMP_LE_D */	19206	/* CMP_LE_D */
19207	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19207	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19208	/* CMP_LE_D_MMR6 */	19208	/* CMP_LE_D_MMR6 */
19209	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19209	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19210	/* CMP_LE_PH */	19210	/* CMP_LE_PH */
19211	DSPROpnd, DSPROpnd,	19211	DSPROpnd, DSPROpnd,
19212	/* CMP_LE_PH_MM */	19212	/* CMP_LE_PH_MM */
19213	DSPROpnd, DSPROpnd,	19213	DSPROpnd, DSPROpnd,
19214	/* CMP_LE_S */	19214	/* CMP_LE_S */
19215	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19215	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19216	/* CMP_LE_S_MMR6 */	19216	/* CMP_LE_S_MMR6 */
19217	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19217	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19218	/* CMP_LT_D */	19218	/* CMP_LT_D */
19219	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19219	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19220	/* CMP_LT_D_MMR6 */	19220	/* CMP_LT_D_MMR6 */
19221	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19221	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19222	/* CMP_LT_PH */	19222	/* CMP_LT_PH */
19223	DSPROpnd, DSPROpnd,	19223	DSPROpnd, DSPROpnd,
19224	/* CMP_LT_PH_MM */	19224	/* CMP_LT_PH_MM */
19225	DSPROpnd, DSPROpnd,	19225	DSPROpnd, DSPROpnd,
19226	/* CMP_LT_S */	19226	/* CMP_LT_S */
19227	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19227	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19228	/* CMP_LT_S_MMR6 */	19228	/* CMP_LT_S_MMR6 */
19229	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19229	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19230	/* CMP_SAF_D */	19230	/* CMP_SAF_D */
19231	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19231	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19232	/* CMP_SAF_D_MMR6 */	19232	/* CMP_SAF_D_MMR6 */
19233	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19233	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19234	/* CMP_SAF_S */	19234	/* CMP_SAF_S */
19235	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19235	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19236	/* CMP_SAF_S_MMR6 */	19236	/* CMP_SAF_S_MMR6 */
19237	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19237	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19238	/* CMP_SEQ_D */	19238	/* CMP_SEQ_D */
19239	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19239	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19240	/* CMP_SEQ_D_MMR6 */	19240	/* CMP_SEQ_D_MMR6 */
19241	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19241	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19242	/* CMP_SEQ_S */	19242	/* CMP_SEQ_S */
19243	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19243	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19244	/* CMP_SEQ_S_MMR6 */	19244	/* CMP_SEQ_S_MMR6 */
19245	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19245	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19246	/* CMP_SLE_D */	19246	/* CMP_SLE_D */
19247	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19247	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19248	/* CMP_SLE_D_MMR6 */	19248	/* CMP_SLE_D_MMR6 */
19249	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19249	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19250	/* CMP_SLE_S */	19250	/* CMP_SLE_S */
19251	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19251	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19252	/* CMP_SLE_S_MMR6 */	19252	/* CMP_SLE_S_MMR6 */
19253	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19253	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19254	/* CMP_SLT_D */	19254	/* CMP_SLT_D */
19255	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19255	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19256	/* CMP_SLT_D_MMR6 */	19256	/* CMP_SLT_D_MMR6 */
19257	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19257	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19258	/* CMP_SLT_S */	19258	/* CMP_SLT_S */
19259	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19259	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19260	/* CMP_SLT_S_MMR6 */	19260	/* CMP_SLT_S_MMR6 */
19261	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19261	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19262	/* CMP_SUEQ_D */	19262	/* CMP_SUEQ_D */
19263	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19263	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19264	/* CMP_SUEQ_D_MMR6 */	19264	/* CMP_SUEQ_D_MMR6 */
19265	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19265	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19266	/* CMP_SUEQ_S */	19266	/* CMP_SUEQ_S */
19267	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19267	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19268	/* CMP_SUEQ_S_MMR6 */	19268	/* CMP_SUEQ_S_MMR6 */
19269	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19269	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19270	/* CMP_SULE_D */	19270	/* CMP_SULE_D */
19271	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19271	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19272	/* CMP_SULE_D_MMR6 */	19272	/* CMP_SULE_D_MMR6 */
19273	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19273	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19274	/* CMP_SULE_S */	19274	/* CMP_SULE_S */
19275	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19275	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19276	/* CMP_SULE_S_MMR6 */	19276	/* CMP_SULE_S_MMR6 */
19277	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19277	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19278	/* CMP_SULT_D */	19278	/* CMP_SULT_D */
19279	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19279	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19280	/* CMP_SULT_D_MMR6 */	19280	/* CMP_SULT_D_MMR6 */
19281	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19281	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19282	/* CMP_SULT_S */	19282	/* CMP_SULT_S */
19283	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19283	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19284	/* CMP_SULT_S_MMR6 */	19284	/* CMP_SULT_S_MMR6 */
19285	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19285	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19286	/* CMP_SUN_D */	19286	/* CMP_SUN_D */
19287	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19287	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19288	/* CMP_SUN_D_MMR6 */	19288	/* CMP_SUN_D_MMR6 */
19289	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19289	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19290	/* CMP_SUN_S */	19290	/* CMP_SUN_S */
19291	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19291	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19292	/* CMP_SUN_S_MMR6 */	19292	/* CMP_SUN_S_MMR6 */
19293	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19293	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19294	/* CMP_UEQ_D */	19294	/* CMP_UEQ_D */
19295	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19295	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19296	/* CMP_UEQ_D_MMR6 */	19296	/* CMP_UEQ_D_MMR6 */
19297	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19297	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19298	/* CMP_UEQ_S */	19298	/* CMP_UEQ_S */
19299	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19299	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19300	/* CMP_UEQ_S_MMR6 */	19300	/* CMP_UEQ_S_MMR6 */
19301	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19301	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19302	/* CMP_ULE_D */	19302	/* CMP_ULE_D */
19303	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19303	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19304	/* CMP_ULE_D_MMR6 */	19304	/* CMP_ULE_D_MMR6 */
19305	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19305	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19306	/* CMP_ULE_S */	19306	/* CMP_ULE_S */
19307	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19307	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19308	/* CMP_ULE_S_MMR6 */	19308	/* CMP_ULE_S_MMR6 */
19309	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19309	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19310	/* CMP_ULT_D */	19310	/* CMP_ULT_D */
19311	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19311	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19312	/* CMP_ULT_D_MMR6 */	19312	/* CMP_ULT_D_MMR6 */
19313	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19313	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19314	/* CMP_ULT_S */	19314	/* CMP_ULT_S */
19315	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19315	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19316	/* CMP_ULT_S_MMR6 */	19316	/* CMP_ULT_S_MMR6 */
19317	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19317	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19318	/* CMP_UN_D */	19318	/* CMP_UN_D */
19319	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19319	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19320	/* CMP_UN_D_MMR6 */	19320	/* CMP_UN_D_MMR6 */
19321	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	19321	FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19322	/* CMP_UN_S */	19322	/* CMP_UN_S */
19323	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19323	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19324	/* CMP_UN_S_MMR6 */	19324	/* CMP_UN_S_MMR6 */
19325	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	19325	FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19326	/* COPY_S_B */	19326	/* COPY_S_B */
19327	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	19327	GPR32Opnd, MSA128BOpnd, uimm4_ptr,
19328	/* COPY_S_D */	19328	/* COPY_S_D */
19329	GPR64Opnd, MSA128DOpnd, uimm1_ptr,	19329	GPR64Opnd, MSA128DOpnd, uimm1_ptr,
19330	/* COPY_S_H */	19330	/* COPY_S_H */
19331	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	19331	GPR32Opnd, MSA128HOpnd, uimm3_ptr,
19332	/* COPY_S_W */	19332	/* COPY_S_W */
19333	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	19333	GPR32Opnd, MSA128WOpnd, uimm2_ptr,
19334	/* COPY_U_B */	19334	/* COPY_U_B */
19335	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	19335	GPR32Opnd, MSA128BOpnd, uimm4_ptr,
19336	/* COPY_U_H */	19336	/* COPY_U_H */
19337	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	19337	GPR32Opnd, MSA128HOpnd, uimm3_ptr,
19338	/* COPY_U_W */	19338	/* COPY_U_W */
19339	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	19339	GPR32Opnd, MSA128WOpnd, uimm2_ptr,
19340	/* CRC32B */	19340	/* CRC32B */
19341	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19341	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19342	/* CRC32CB */	19342	/* CRC32CB */
19343	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19343	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19344	/* CRC32CD */	19344	/* CRC32CD */
19345	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19345	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19346	/* CRC32CH */	19346	/* CRC32CH */
19347	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19347	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19348	/* CRC32CW */	19348	/* CRC32CW */
19349	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19349	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19350	/* CRC32D */	19350	/* CRC32D */
19351	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19351	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19352	/* CRC32H */	19352	/* CRC32H */
19353	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19353	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19354	/* CRC32W */	19354	/* CRC32W */
19355	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19355	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19356	/* CTC1 */	19356	/* CTC1 */
19357	CCROpnd, GPR32Opnd,	19357	CCROpnd, GPR32Opnd,
19358	/* CTC1_MM */	19358	/* CTC1_MM */
19359	CCROpnd, GPR32Opnd,	19359	CCROpnd, GPR32Opnd,
19360	/* CTC2_MM */	19360	/* CTC2_MM */
19361	COP2Opnd, GPR32Opnd,	19361	COP2Opnd, GPR32Opnd,
19362	/* CTCMSA */	19362	/* CTCMSA */
19363	MSA128CROpnd, GPR32Opnd,	19363	MSA128CROpnd, GPR32Opnd,
19364	/* CVT_D32_S */	19364	/* CVT_D32_S */
19365	AFGR64Opnd, FGR32Opnd,	19365	AFGR64Opnd, FGR32Opnd,
19366	/* CVT_D32_S_MM */	19366	/* CVT_D32_S_MM */
19367	AFGR64Opnd, FGR32Opnd,	19367	AFGR64Opnd, FGR32Opnd,
19368	/* CVT_D32_W */	19368	/* CVT_D32_W */
19369	AFGR64Opnd, FGR32Opnd,	19369	AFGR64Opnd, FGR32Opnd,
19370	/* CVT_D32_W_MM */	19370	/* CVT_D32_W_MM */
19371	AFGR64Opnd, FGR32Opnd,	19371	AFGR64Opnd, FGR32Opnd,
19372	/* CVT_D64_L */	19372	/* CVT_D64_L */
19373	FGR64Opnd, FGR64Opnd,	19373	FGR64Opnd, FGR64Opnd,
19374	/* CVT_D64_S */	19374	/* CVT_D64_S */
19375	FGR64Opnd, FGR32Opnd,	19375	FGR64Opnd, FGR32Opnd,
19376	/* CVT_D64_S_MM */	19376	/* CVT_D64_S_MM */
19377	FGR64Opnd, FGR32Opnd,	19377	FGR64Opnd, FGR32Opnd,
19378	/* CVT_D64_W */	19378	/* CVT_D64_W */
19379	FGR64Opnd, FGR32Opnd,	19379	FGR64Opnd, FGR32Opnd,
19380	/* CVT_D64_W_MM */	19380	/* CVT_D64_W_MM */
19381	FGR64Opnd, FGR32Opnd,	19381	FGR64Opnd, FGR32Opnd,
19382	/* CVT_D_L_MMR6 */	19382	/* CVT_D_L_MMR6 */
19383	FGR64Opnd, FGR64Opnd,	19383	FGR64Opnd, FGR64Opnd,
19384	/* CVT_L_D64 */	19384	/* CVT_L_D64 */
19385	FGR64Opnd, FGR64Opnd,	19385	FGR64Opnd, FGR64Opnd,
19386	/* CVT_L_D64_MM */	19386	/* CVT_L_D64_MM */
19387	FGR64Opnd, FGR64Opnd,	19387	FGR64Opnd, FGR64Opnd,
19388	/* CVT_L_D_MMR6 */	19388	/* CVT_L_D_MMR6 */
19389	FGR64Opnd, FGR64Opnd,	19389	FGR64Opnd, FGR64Opnd,
19390	/* CVT_L_S */	19390	/* CVT_L_S */
19391	FGR64Opnd, FGR32Opnd,	19391	FGR64Opnd, FGR32Opnd,
19392	/* CVT_L_S_MM */	19392	/* CVT_L_S_MM */
19393	FGR64Opnd, FGR32Opnd,	19393	FGR64Opnd, FGR32Opnd,
19394	/* CVT_L_S_MMR6 */	19394	/* CVT_L_S_MMR6 */
19395	FGR64Opnd, FGR32Opnd,	19395	FGR64Opnd, FGR32Opnd,
19396	/* CVT_PS_PW64 */	19396	/* CVT_PS_PW64 */
19397	FGR64Opnd, FGR64Opnd,	19397	FGR64Opnd, FGR64Opnd,
19398	/* CVT_PS_S64 */	19398	/* CVT_PS_S64 */
19399	FGR64Opnd, FGR32Opnd, FGR32Opnd,	19399	FGR64Opnd, FGR32Opnd, FGR32Opnd,
19400	/* CVT_PW_PS64 */	19400	/* CVT_PW_PS64 */
19401	FGR64Opnd, FGR64Opnd,	19401	FGR64Opnd, FGR64Opnd,
19402	/* CVT_S_D32 */	19402	/* CVT_S_D32 */
19403	FGR32Opnd, AFGR64Opnd,	19403	FGR32Opnd, AFGR64Opnd,
19404	/* CVT_S_D32_MM */	19404	/* CVT_S_D32_MM */
19405	FGR32Opnd, AFGR64Opnd,	19405	FGR32Opnd, AFGR64Opnd,
19406	/* CVT_S_D64 */	19406	/* CVT_S_D64 */
19407	FGR32Opnd, FGR64Opnd,	19407	FGR32Opnd, FGR64Opnd,
19408	/* CVT_S_D64_MM */	19408	/* CVT_S_D64_MM */
19409	FGR32Opnd, FGR64Opnd,	19409	FGR32Opnd, FGR64Opnd,
19410	/* CVT_S_L */	19410	/* CVT_S_L */
19411	FGR32Opnd, FGR64Opnd,	19411	FGR32Opnd, FGR64Opnd,
19412	/* CVT_S_L_MMR6 */	19412	/* CVT_S_L_MMR6 */
19413	FGR64Opnd, FGR32Opnd,	19413	FGR64Opnd, FGR32Opnd,
19414	/* CVT_S_PL64 */	19414	/* CVT_S_PL64 */
19415	FGR32Opnd, FGR64Opnd,	19415	FGR32Opnd, FGR64Opnd,
19416	/* CVT_S_PU64 */	19416	/* CVT_S_PU64 */
19417	FGR32Opnd, FGR64Opnd,	19417	FGR32Opnd, FGR64Opnd,
19418	/* CVT_S_W */	19418	/* CVT_S_W */
19419	FGR32Opnd, FGR32Opnd,	19419	FGR32Opnd, FGR32Opnd,
19420	/* CVT_S_W_MM */	19420	/* CVT_S_W_MM */
19421	FGR32Opnd, FGR32Opnd,	19421	FGR32Opnd, FGR32Opnd,
19422	/* CVT_S_W_MMR6 */	19422	/* CVT_S_W_MMR6 */
19423	FGR32Opnd, FGR32Opnd,	19423	FGR32Opnd, FGR32Opnd,
19424	/* CVT_W_D32 */	19424	/* CVT_W_D32 */
19425	FGR32Opnd, AFGR64Opnd,	19425	FGR32Opnd, AFGR64Opnd,
19426	/* CVT_W_D32_MM */	19426	/* CVT_W_D32_MM */
19427	FGR32Opnd, AFGR64Opnd,	19427	FGR32Opnd, AFGR64Opnd,
19428	/* CVT_W_D64 */	19428	/* CVT_W_D64 */
19429	FGR32Opnd, FGR64Opnd,	19429	FGR32Opnd, FGR64Opnd,
19430	/* CVT_W_D64_MM */	19430	/* CVT_W_D64_MM */
19431	FGR32Opnd, FGR64Opnd,	19431	FGR32Opnd, FGR64Opnd,
19432	/* CVT_W_S */	19432	/* CVT_W_S */
19433	FGR32Opnd, FGR32Opnd,	19433	FGR32Opnd, FGR32Opnd,
19434	/* CVT_W_S_MM */	19434	/* CVT_W_S_MM */
19435	FGR32Opnd, FGR32Opnd,	19435	FGR32Opnd, FGR32Opnd,
19436	/* CVT_W_S_MMR6 */	19436	/* CVT_W_S_MMR6 */
19437	FGR32Opnd, FGR32Opnd,	19437	FGR32Opnd, FGR32Opnd,
19438	/* C_EQ_D32 */	19438	/* C_EQ_D32 */
19439	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19439	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19440	/* C_EQ_D32_MM */	19440	/* C_EQ_D32_MM */
19441	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19441	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19442	/* C_EQ_D64 */	19442	/* C_EQ_D64 */
19443	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19443	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19444	/* C_EQ_D64_MM */	19444	/* C_EQ_D64_MM */
19445	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19445	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19446	/* C_EQ_S */	19446	/* C_EQ_S */
19447	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19447	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19448	/* C_EQ_S_MM */	19448	/* C_EQ_S_MM */
19449	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19449	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19450	/* C_F_D32 */	19450	/* C_F_D32 */
19451	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19451	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19452	/* C_F_D32_MM */	19452	/* C_F_D32_MM */
19453	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19453	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19454	/* C_F_D64 */	19454	/* C_F_D64 */
19455	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19455	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19456	/* C_F_D64_MM */	19456	/* C_F_D64_MM */
19457	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19457	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19458	/* C_F_S */	19458	/* C_F_S */
19459	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19459	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19460	/* C_F_S_MM */	19460	/* C_F_S_MM */
19461	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19461	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19462	/* C_LE_D32 */	19462	/* C_LE_D32 */
19463	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19463	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19464	/* C_LE_D32_MM */	19464	/* C_LE_D32_MM */
19465	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19465	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19466	/* C_LE_D64 */	19466	/* C_LE_D64 */
19467	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19467	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19468	/* C_LE_D64_MM */	19468	/* C_LE_D64_MM */
19469	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19469	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19470	/* C_LE_S */	19470	/* C_LE_S */
19471	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19471	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19472	/* C_LE_S_MM */	19472	/* C_LE_S_MM */
19473	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19473	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19474	/* C_LT_D32 */	19474	/* C_LT_D32 */
19475	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19475	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19476	/* C_LT_D32_MM */	19476	/* C_LT_D32_MM */
19477	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19477	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19478	/* C_LT_D64 */	19478	/* C_LT_D64 */
19479	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19479	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19480	/* C_LT_D64_MM */	19480	/* C_LT_D64_MM */
19481	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19481	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19482	/* C_LT_S */	19482	/* C_LT_S */
19483	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19483	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19484	/* C_LT_S_MM */	19484	/* C_LT_S_MM */
19485	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19485	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19486	/* C_NGE_D32 */	19486	/* C_NGE_D32 */
19487	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19487	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19488	/* C_NGE_D32_MM */	19488	/* C_NGE_D32_MM */
19489	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19489	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19490	/* C_NGE_D64 */	19490	/* C_NGE_D64 */
19491	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19491	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19492	/* C_NGE_D64_MM */	19492	/* C_NGE_D64_MM */
19493	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19493	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19494	/* C_NGE_S */	19494	/* C_NGE_S */
19495	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19495	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19496	/* C_NGE_S_MM */	19496	/* C_NGE_S_MM */
19497	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19497	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19498	/* C_NGLE_D32 */	19498	/* C_NGLE_D32 */
19499	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19499	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19500	/* C_NGLE_D32_MM */	19500	/* C_NGLE_D32_MM */
19501	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19501	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19502	/* C_NGLE_D64 */	19502	/* C_NGLE_D64 */
19503	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19503	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19504	/* C_NGLE_D64_MM */	19504	/* C_NGLE_D64_MM */
19505	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19505	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19506	/* C_NGLE_S */	19506	/* C_NGLE_S */
19507	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19507	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19508	/* C_NGLE_S_MM */	19508	/* C_NGLE_S_MM */
19509	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19509	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19510	/* C_NGL_D32 */	19510	/* C_NGL_D32 */
19511	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19511	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19512	/* C_NGL_D32_MM */	19512	/* C_NGL_D32_MM */
19513	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19513	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19514	/* C_NGL_D64 */	19514	/* C_NGL_D64 */
19515	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19515	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19516	/* C_NGL_D64_MM */	19516	/* C_NGL_D64_MM */
19517	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19517	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19518	/* C_NGL_S */	19518	/* C_NGL_S */
19519	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19519	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19520	/* C_NGL_S_MM */	19520	/* C_NGL_S_MM */
19521	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19521	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19522	/* C_NGT_D32 */	19522	/* C_NGT_D32 */
19523	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19523	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19524	/* C_NGT_D32_MM */	19524	/* C_NGT_D32_MM */
19525	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19525	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19526	/* C_NGT_D64 */	19526	/* C_NGT_D64 */
19527	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19527	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19528	/* C_NGT_D64_MM */	19528	/* C_NGT_D64_MM */
19529	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19529	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19530	/* C_NGT_S */	19530	/* C_NGT_S */
19531	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19531	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19532	/* C_NGT_S_MM */	19532	/* C_NGT_S_MM */
19533	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19533	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19534	/* C_OLE_D32 */	19534	/* C_OLE_D32 */
19535	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19535	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19536	/* C_OLE_D32_MM */	19536	/* C_OLE_D32_MM */
19537	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19537	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19538	/* C_OLE_D64 */	19538	/* C_OLE_D64 */
19539	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19539	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19540	/* C_OLE_D64_MM */	19540	/* C_OLE_D64_MM */
19541	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19541	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19542	/* C_OLE_S */	19542	/* C_OLE_S */
19543	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19543	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19544	/* C_OLE_S_MM */	19544	/* C_OLE_S_MM */
19545	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19545	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19546	/* C_OLT_D32 */	19546	/* C_OLT_D32 */
19547	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19547	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19548	/* C_OLT_D32_MM */	19548	/* C_OLT_D32_MM */
19549	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19549	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19550	/* C_OLT_D64 */	19550	/* C_OLT_D64 */
19551	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19551	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19552	/* C_OLT_D64_MM */	19552	/* C_OLT_D64_MM */
19553	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19553	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19554	/* C_OLT_S */	19554	/* C_OLT_S */
19555	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19555	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19556	/* C_OLT_S_MM */	19556	/* C_OLT_S_MM */
19557	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19557	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19558	/* C_SEQ_D32 */	19558	/* C_SEQ_D32 */
19559	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19559	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19560	/* C_SEQ_D32_MM */	19560	/* C_SEQ_D32_MM */
19561	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19561	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19562	/* C_SEQ_D64 */	19562	/* C_SEQ_D64 */
19563	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19563	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19564	/* C_SEQ_D64_MM */	19564	/* C_SEQ_D64_MM */
19565	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19565	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19566	/* C_SEQ_S */	19566	/* C_SEQ_S */
19567	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19567	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19568	/* C_SEQ_S_MM */	19568	/* C_SEQ_S_MM */
19569	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19569	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19570	/* C_SF_D32 */	19570	/* C_SF_D32 */
19571	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19571	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19572	/* C_SF_D32_MM */	19572	/* C_SF_D32_MM */
19573	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19573	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19574	/* C_SF_D64 */	19574	/* C_SF_D64 */
19575	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19575	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19576	/* C_SF_D64_MM */	19576	/* C_SF_D64_MM */
19577	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19577	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19578	/* C_SF_S */	19578	/* C_SF_S */
19579	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19579	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19580	/* C_SF_S_MM */	19580	/* C_SF_S_MM */
19581	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19581	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19582	/* C_UEQ_D32 */	19582	/* C_UEQ_D32 */
19583	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19583	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19584	/* C_UEQ_D32_MM */	19584	/* C_UEQ_D32_MM */
19585	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19585	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19586	/* C_UEQ_D64 */	19586	/* C_UEQ_D64 */
19587	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19587	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19588	/* C_UEQ_D64_MM */	19588	/* C_UEQ_D64_MM */
19589	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19589	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19590	/* C_UEQ_S */	19590	/* C_UEQ_S */
19591	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19591	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19592	/* C_UEQ_S_MM */	19592	/* C_UEQ_S_MM */
19593	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19593	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19594	/* C_ULE_D32 */	19594	/* C_ULE_D32 */
19595	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19595	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19596	/* C_ULE_D32_MM */	19596	/* C_ULE_D32_MM */
19597	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19597	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19598	/* C_ULE_D64 */	19598	/* C_ULE_D64 */
19599	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19599	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19600	/* C_ULE_D64_MM */	19600	/* C_ULE_D64_MM */
19601	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19601	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19602	/* C_ULE_S */	19602	/* C_ULE_S */
19603	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19603	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19604	/* C_ULE_S_MM */	19604	/* C_ULE_S_MM */
19605	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19605	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19606	/* C_ULT_D32 */	19606	/* C_ULT_D32 */
19607	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19607	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19608	/* C_ULT_D32_MM */	19608	/* C_ULT_D32_MM */
19609	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19609	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19610	/* C_ULT_D64 */	19610	/* C_ULT_D64 */
19611	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19611	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19612	/* C_ULT_D64_MM */	19612	/* C_ULT_D64_MM */
19613	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19613	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19614	/* C_ULT_S */	19614	/* C_ULT_S */
19615	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19615	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19616	/* C_ULT_S_MM */	19616	/* C_ULT_S_MM */
19617	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19617	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19618	/* C_UN_D32 */	19618	/* C_UN_D32 */
19619	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19619	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19620	/* C_UN_D32_MM */	19620	/* C_UN_D32_MM */
19621	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	19621	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19622	/* C_UN_D64 */	19622	/* C_UN_D64 */
19623	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19623	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19624	/* C_UN_D64_MM */	19624	/* C_UN_D64_MM */
19625	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	19625	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19626	/* C_UN_S */	19626	/* C_UN_S */
19627	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19627	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19628	/* C_UN_S_MM */	19628	/* C_UN_S_MM */
19629	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	19629	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19630	/* CmpRxRy16 */	19630	/* CmpRxRy16 */
19631	CPU16Regs, CPU16Regs,	19631	CPU16Regs, CPU16Regs,
19632	/* CmpiRxImm16 */	19632	/* CmpiRxImm16 */
19633	CPU16Regs, simm16,	19633	CPU16Regs, simm16,
19634	/* CmpiRxImmX16 */	19634	/* CmpiRxImmX16 */
19635	CPU16Regs, simm16,	19635	CPU16Regs, simm16,
19636	/* DADD */	19636	/* DADD */
19637	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19637	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19638	/* DADDi */	19638	/* DADDi */
19639	GPR64Opnd, GPR64Opnd, simm16_64,	19639	GPR64Opnd, GPR64Opnd, simm16_64,
19640	/* DADDiu */	19640	/* DADDiu */
19641	GPR64Opnd, GPR64Opnd, simm16_64,	19641	GPR64Opnd, GPR64Opnd, simm16_64,
19642	/* DADDu */	19642	/* DADDu */
19643	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19643	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19644	/* DAHI */	19644	/* DAHI */
19645	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	19645	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,
19646	/* DALIGN */	19646	/* DALIGN */
19647	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,	19647	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,
19648	/* DATI */	19648	/* DATI */
19649	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	19649	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,
19650	/* DAUI */	19650	/* DAUI */
19651	GPR64Opnd, GPR64Opnd, uimm16,	19651	GPR64Opnd, GPR64Opnd, uimm16,
19652	/* DBITSWAP */	19652	/* DBITSWAP */
19653	GPR64Opnd, GPR64Opnd,	19653	GPR64Opnd, GPR64Opnd,
19654	/* DCLO */	19654	/* DCLO */
19655	GPR64Opnd, GPR64Opnd,	19655	GPR64Opnd, GPR64Opnd,
19656	/* DCLO_R6 */	19656	/* DCLO_R6 */
19657	GPR64Opnd, GPR64Opnd,	19657	GPR64Opnd, GPR64Opnd,
19658	/* DCLZ */	19658	/* DCLZ */
19659	GPR64Opnd, GPR64Opnd,	19659	GPR64Opnd, GPR64Opnd,
19660	/* DCLZ_R6 */	19660	/* DCLZ_R6 */
19661	GPR64Opnd, GPR64Opnd,	19661	GPR64Opnd, GPR64Opnd,
19662	/* DDIV */	19662	/* DDIV */
19663	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19663	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19664	/* DDIVU */	19664	/* DDIVU */
19665	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19665	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19666	/* DERET */	19666	/* DERET */
19667	/* DERET_MM */	19667	/* DERET_MM */
19668	/* DERET_MMR6 */	19668	/* DERET_MMR6 */
19669	/* DEXT */	19669	/* DEXT */
19670	GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,	19670	GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,
19671	/* DEXT64_32 */	19671	/* DEXT64_32 */
19672	GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,	19672	GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,
19673	/* DEXTM */	19673	/* DEXTM */
19674	GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,	19674	GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,
19675	/* DEXTU */	19675	/* DEXTU */
19676	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,	19676	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,
19677	/* DI */	19677	/* DI */
19678	GPR32Opnd,	19678	GPR32Opnd,
19679	/* DINS */	19679	/* DINS */
19680	GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,	19680	GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,
19681	/* DINSM */	19681	/* DINSM */
19682	GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,	19682	GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,
19683	/* DINSU */	19683	/* DINSU */
19684	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,	19684	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,
19685	/* DIV */	19685	/* DIV */
19686	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19686	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19687	/* DIVU */	19687	/* DIVU */
19688	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19688	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19689	/* DIVU_MMR6 */	19689	/* DIVU_MMR6 */
19690	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19690	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19691	/* DIV_MMR6 */	19691	/* DIV_MMR6 */
19692	GPR32Opnd, GPR32Opnd, GPR32Opnd,	19692	GPR32Opnd, GPR32Opnd, GPR32Opnd,
19693	/* DIV_S_B */	19693	/* DIV_S_B */
19694	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19694	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19695	/* DIV_S_D */	19695	/* DIV_S_D */
19696	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19696	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19697	/* DIV_S_H */	19697	/* DIV_S_H */
19698	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19698	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19699	/* DIV_S_W */	19699	/* DIV_S_W */
19700	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19700	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19701	/* DIV_U_B */	19701	/* DIV_U_B */
19702	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	19702	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19703	/* DIV_U_D */	19703	/* DIV_U_D */
19704	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	19704	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19705	/* DIV_U_H */	19705	/* DIV_U_H */
19706	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	19706	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19707	/* DIV_U_W */	19707	/* DIV_U_W */
19708	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	19708	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19709	/* DI_MM */	19709	/* DI_MM */
19710	GPR32Opnd,	19710	GPR32Opnd,
19711	/* DI_MMR6 */	19711	/* DI_MMR6 */
19712	GPR32Opnd,	19712	GPR32Opnd,
19713	/* DLSA */	19713	/* DLSA */
19714	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	19714	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,
19715	/* DLSA_R6 */	19715	/* DLSA_R6 */
19716	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	19716	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,
19717	/* DMFC0 */	19717	/* DMFC0 */
19718	GPR64Opnd, COP0Opnd, uimm3,	19718	GPR64Opnd, COP0Opnd, uimm3,
19719	/* DMFC1 */	19719	/* DMFC1 */
19720	GPR64Opnd, FGR64Opnd,	19720	GPR64Opnd, FGR64Opnd,
19721	/* DMFC2 */	19721	/* DMFC2 */
19722	GPR64Opnd, COP2Opnd, uimm3,	19722	GPR64Opnd, COP2Opnd, uimm3,
19723	/* DMFC2_OCTEON */	19723	/* DMFC2_OCTEON */
19724	GPR64Opnd, uimm16,	19724	GPR64Opnd, uimm16,
19725	/* DMFGC0 */	19725	/* DMFGC0 */
19726	GPR64Opnd, COP0Opnd, uimm3,	19726	GPR64Opnd, COP0Opnd, uimm3,
19727	/* DMOD */	19727	/* DMOD */
19728	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19728	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19729	/* DMODU */	19729	/* DMODU */
19730	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19730	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19731	/* DMT */	19731	/* DMT */
19732	GPR32Opnd,	19732	GPR32Opnd,
19733	/* DMTC0 */	19733	/* DMTC0 */
19734	COP0Opnd, GPR64Opnd, uimm3,	19734	COP0Opnd, GPR64Opnd, uimm3,
19735	/* DMTC1 */	19735	/* DMTC1 */
19736	FGR64Opnd, GPR64Opnd,	19736	FGR64Opnd, GPR64Opnd,
19737	/* DMTC2 */	19737	/* DMTC2 */
19738	COP2Opnd, GPR64Opnd, uimm3,	19738	COP2Opnd, GPR64Opnd, uimm3,
19739	/* DMTC2_OCTEON */	19739	/* DMTC2_OCTEON */
19740	GPR64Opnd, uimm16,	19740	GPR64Opnd, uimm16,
19741	/* DMTGC0 */	19741	/* DMTGC0 */
19742	COP0Opnd, GPR64Opnd, uimm3,	19742	COP0Opnd, GPR64Opnd, uimm3,
19743	/* DMUH */	19743	/* DMUH */
19744	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19744	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19745	/* DMUHU */	19745	/* DMUHU */
19746	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19746	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19747	/* DMUL */	19747	/* DMUL */
19748	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19748	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19749	/* DMULT */	19749	/* DMULT */
19750	GPR64Opnd, GPR64Opnd,	19750	GPR64Opnd, GPR64Opnd,
19751	/* DMULTu */	19751	/* DMULTu */
19752	GPR64Opnd, GPR64Opnd,	19752	GPR64Opnd, GPR64Opnd,
19753	/* DMULU */	19753	/* DMULU */
19754	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19754	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19755	/* DMUL_R6 */	19755	/* DMUL_R6 */
19756	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19756	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19757	/* DOTP_S_D */	19757	/* DOTP_S_D */
19758	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19758	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19759	/* DOTP_S_H */	19759	/* DOTP_S_H */
19760	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19760	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19761	/* DOTP_S_W */	19761	/* DOTP_S_W */
19762	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19762	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19763	/* DOTP_U_D */	19763	/* DOTP_U_D */
19764	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19764	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19765	/* DOTP_U_H */	19765	/* DOTP_U_H */
19766	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19766	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19767	/* DOTP_U_W */	19767	/* DOTP_U_W */
19768	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19768	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19769	/* DPADD_S_D */	19769	/* DPADD_S_D */
19770	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19770	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19771	/* DPADD_S_H */	19771	/* DPADD_S_H */
19772	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19772	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19773	/* DPADD_S_W */	19773	/* DPADD_S_W */
19774	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19774	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19775	/* DPADD_U_D */	19775	/* DPADD_U_D */
19776	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19776	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19777	/* DPADD_U_H */	19777	/* DPADD_U_H */
19778	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19778	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19779	/* DPADD_U_W */	19779	/* DPADD_U_W */
19780	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19780	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19781	/* DPAQX_SA_W_PH */	19781	/* DPAQX_SA_W_PH */
19782	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19782	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19783	/* DPAQX_SA_W_PH_MMR2 */	19783	/* DPAQX_SA_W_PH_MMR2 */
19784	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19784	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19785	/* DPAQX_S_W_PH */	19785	/* DPAQX_S_W_PH */
19786	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19786	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19787	/* DPAQX_S_W_PH_MMR2 */	19787	/* DPAQX_S_W_PH_MMR2 */
19788	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19788	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19789	/* DPAQ_SA_L_W */	19789	/* DPAQ_SA_L_W */
19790	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19790	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19791	/* DPAQ_SA_L_W_MM */	19791	/* DPAQ_SA_L_W_MM */
19792	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19792	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19793	/* DPAQ_S_W_PH */	19793	/* DPAQ_S_W_PH */
19794	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19794	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19795	/* DPAQ_S_W_PH_MM */	19795	/* DPAQ_S_W_PH_MM */
19796	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19796	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19797	/* DPAU_H_QBL */	19797	/* DPAU_H_QBL */
19798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19799	/* DPAU_H_QBL_MM */	19799	/* DPAU_H_QBL_MM */
19800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19801	/* DPAU_H_QBR */	19801	/* DPAU_H_QBR */
19802	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19802	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19803	/* DPAU_H_QBR_MM */	19803	/* DPAU_H_QBR_MM */
19804	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19804	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19805	/* DPAX_W_PH */	19805	/* DPAX_W_PH */
19806	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19806	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19807	/* DPAX_W_PH_MMR2 */	19807	/* DPAX_W_PH_MMR2 */
19808	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19808	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19809	/* DPA_W_PH */	19809	/* DPA_W_PH */
19810	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19810	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19811	/* DPA_W_PH_MMR2 */	19811	/* DPA_W_PH_MMR2 */
19812	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19812	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19813	/* DPOP */	19813	/* DPOP */
19814	GPR64Opnd, GPR64Opnd,	19814	GPR64Opnd, GPR64Opnd,
19815	/* DPSQX_SA_W_PH */	19815	/* DPSQX_SA_W_PH */
19816	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19816	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19817	/* DPSQX_SA_W_PH_MMR2 */	19817	/* DPSQX_SA_W_PH_MMR2 */
19818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19819	/* DPSQX_S_W_PH */	19819	/* DPSQX_S_W_PH */
19820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19821	/* DPSQX_S_W_PH_MMR2 */	19821	/* DPSQX_S_W_PH_MMR2 */
19822	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19822	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19823	/* DPSQ_SA_L_W */	19823	/* DPSQ_SA_L_W */
19824	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19824	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19825	/* DPSQ_SA_L_W_MM */	19825	/* DPSQ_SA_L_W_MM */
19826	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19826	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19827	/* DPSQ_S_W_PH */	19827	/* DPSQ_S_W_PH */
19828	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19828	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19829	/* DPSQ_S_W_PH_MM */	19829	/* DPSQ_S_W_PH_MM */
19830	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19830	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19831	/* DPSUB_S_D */	19831	/* DPSUB_S_D */
19832	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19832	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19833	/* DPSUB_S_H */	19833	/* DPSUB_S_H */
19834	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19834	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19835	/* DPSUB_S_W */	19835	/* DPSUB_S_W */
19836	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19836	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19837	/* DPSUB_U_D */	19837	/* DPSUB_U_D */
19838	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	19838	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
19839	/* DPSUB_U_H */	19839	/* DPSUB_U_H */
19840	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	19840	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
19841	/* DPSUB_U_W */	19841	/* DPSUB_U_W */
19842	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	19842	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
19843	/* DPSU_H_QBL */	19843	/* DPSU_H_QBL */
19844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19845	/* DPSU_H_QBL_MM */	19845	/* DPSU_H_QBL_MM */
19846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19847	/* DPSU_H_QBR */	19847	/* DPSU_H_QBR */
19848	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19848	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19849	/* DPSU_H_QBR_MM */	19849	/* DPSU_H_QBR_MM */
19850	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19850	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19851	/* DPSX_W_PH */	19851	/* DPSX_W_PH */
19852	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19852	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19853	/* DPSX_W_PH_MMR2 */	19853	/* DPSX_W_PH_MMR2 */
19854	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19854	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19855	/* DPS_W_PH */	19855	/* DPS_W_PH */
19856	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19856	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19857	/* DPS_W_PH_MMR2 */	19857	/* DPS_W_PH_MMR2 */
19858	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	19858	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
19859	/* DROTR */	19859	/* DROTR */
19860	GPR64Opnd, GPR64Opnd, uimm6,	19860	GPR64Opnd, GPR64Opnd, uimm6,
19861	/* DROTR32 */	19861	/* DROTR32 */
19862	GPR64Opnd, GPR64Opnd, uimm5,	19862	GPR64Opnd, GPR64Opnd, uimm5,
19863	/* DROTRV */	19863	/* DROTRV */
19864	GPR64Opnd, GPR64Opnd, GPR32Opnd,	19864	GPR64Opnd, GPR64Opnd, GPR32Opnd,
19865	/* DSBH */	19865	/* DSBH */
19866	GPR64Opnd, GPR64Opnd,	19866	GPR64Opnd, GPR64Opnd,
19867	/* DSDIV */	19867	/* DSDIV */
19868	GPR64Opnd, GPR64Opnd,	19868	GPR64Opnd, GPR64Opnd,
19869	/* DSHD */	19869	/* DSHD */
19870	GPR64Opnd, GPR64Opnd,	19870	GPR64Opnd, GPR64Opnd,
19871	/* DSLL */	19871	/* DSLL */
19872	GPR64Opnd, GPR64Opnd, uimm6,	19872	GPR64Opnd, GPR64Opnd, uimm6,
19873	/* DSLL32 */	19873	/* DSLL32 */
19874	GPR64Opnd, GPR64Opnd, uimm5,	19874	GPR64Opnd, GPR64Opnd, uimm5,
19875	/* DSLL64_32 */	19875	/* DSLL64_32 */
19876	GPR64, GPR32,	19876	GPR64, GPR32,
19877	/* DSLLV */	19877	/* DSLLV */
19878	GPR64Opnd, GPR64Opnd, GPR32Opnd,	19878	GPR64Opnd, GPR64Opnd, GPR32Opnd,
19879	/* DSRA */	19879	/* DSRA */
19880	GPR64Opnd, GPR64Opnd, uimm6,	19880	GPR64Opnd, GPR64Opnd, uimm6,
19881	/* DSRA32 */	19881	/* DSRA32 */
19882	GPR64Opnd, GPR64Opnd, uimm5,	19882	GPR64Opnd, GPR64Opnd, uimm5,
19883	/* DSRAV */	19883	/* DSRAV */
19884	GPR64Opnd, GPR64Opnd, GPR32Opnd,	19884	GPR64Opnd, GPR64Opnd, GPR32Opnd,
19885	/* DSRL */	19885	/* DSRL */
19886	GPR64Opnd, GPR64Opnd, uimm6,	19886	GPR64Opnd, GPR64Opnd, uimm6,
19887	/* DSRL32 */	19887	/* DSRL32 */
19888	GPR64Opnd, GPR64Opnd, uimm5,	19888	GPR64Opnd, GPR64Opnd, uimm5,
19889	/* DSRLV */	19889	/* DSRLV */
19890	GPR64Opnd, GPR64Opnd, GPR32Opnd,	19890	GPR64Opnd, GPR64Opnd, GPR32Opnd,
19891	/* DSUB */	19891	/* DSUB */
19892	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19892	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19893	/* DSUBu */	19893	/* DSUBu */
19894	GPR64Opnd, GPR64Opnd, GPR64Opnd,	19894	GPR64Opnd, GPR64Opnd, GPR64Opnd,
19895	/* DUDIV */	19895	/* DUDIV */
19896	GPR64Opnd, GPR64Opnd,	19896	GPR64Opnd, GPR64Opnd,
19897	/* DVP */	19897	/* DVP */
19898	GPR32Opnd,	19898	GPR32Opnd,
19899	/* DVPE */	19899	/* DVPE */
19900	GPR32Opnd,	19900	GPR32Opnd,
19901	/* DVP_MMR6 */	19901	/* DVP_MMR6 */
19902	GPR32Opnd,	19902	GPR32Opnd,
19903	/* DivRxRy16 */	19903	/* DivRxRy16 */
19904	CPU16Regs, CPU16Regs,	19904	CPU16Regs, CPU16Regs,
19905	/* DivuRxRy16 */	19905	/* DivuRxRy16 */
19906	CPU16Regs, CPU16Regs,	19906	CPU16Regs, CPU16Regs,
19907	/* EHB */	19907	/* EHB */
19908	/* EHB_MM */	19908	/* EHB_MM */
19909	/* EHB_MMR6 */	19909	/* EHB_MMR6 */
19910	/* EI */	19910	/* EI */
19911	GPR32Opnd,	19911	GPR32Opnd,
19912	/* EI_MM */	19912	/* EI_MM */
19913	GPR32Opnd,	19913	GPR32Opnd,
19914	/* EI_MMR6 */	19914	/* EI_MMR6 */
19915	GPR32Opnd,	19915	GPR32Opnd,
19916	/* EMT */	19916	/* EMT */
19917	GPR32Opnd,	19917	GPR32Opnd,
19918	/* ERET */	19918	/* ERET */
19919	/* ERETNC */	19919	/* ERETNC */
19920	/* ERETNC_MMR6 */	19920	/* ERETNC_MMR6 */
19921	/* ERET_MM */	19921	/* ERET_MM */
19922	/* ERET_MMR6 */	19922	/* ERET_MMR6 */
19923	/* EVP */	19923	/* EVP */
19924	GPR32Opnd,	19924	GPR32Opnd,
19925	/* EVPE */	19925	/* EVPE */
19926	GPR32Opnd,	19926	GPR32Opnd,
19927	/* EVP_MMR6 */	19927	/* EVP_MMR6 */
19928	GPR32Opnd,	19928	GPR32Opnd,
19929	/* EXT */	19929	/* EXT */
19930	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	19930	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
19931	/* EXTP */	19931	/* EXTP */
19932	GPR32Opnd, ACC64DSPOpnd, uimm5,	19932	GPR32Opnd, ACC64DSPOpnd, uimm5,
19933	/* EXTPDP */	19933	/* EXTPDP */
19934	GPR32Opnd, ACC64DSPOpnd, uimm5,	19934	GPR32Opnd, ACC64DSPOpnd, uimm5,
19935	/* EXTPDPV */	19935	/* EXTPDPV */
19936	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19936	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19937	/* EXTPDPV_MM */	19937	/* EXTPDPV_MM */
19938	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19938	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19939	/* EXTPDP_MM */	19939	/* EXTPDP_MM */
19940	GPR32Opnd, ACC64DSPOpnd, uimm5,	19940	GPR32Opnd, ACC64DSPOpnd, uimm5,
19941	/* EXTPV */	19941	/* EXTPV */
19942	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19942	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19943	/* EXTPV_MM */	19943	/* EXTPV_MM */
19944	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19944	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19945	/* EXTP_MM */	19945	/* EXTP_MM */
19946	GPR32Opnd, ACC64DSPOpnd, uimm5,	19946	GPR32Opnd, ACC64DSPOpnd, uimm5,
19947	/* EXTRV_RS_W */	19947	/* EXTRV_RS_W */
19948	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19948	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19949	/* EXTRV_RS_W_MM */	19949	/* EXTRV_RS_W_MM */
19950	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19950	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19951	/* EXTRV_R_W */	19951	/* EXTRV_R_W */
19952	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19952	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19953	/* EXTRV_R_W_MM */	19953	/* EXTRV_R_W_MM */
19954	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19954	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19955	/* EXTRV_S_H */	19955	/* EXTRV_S_H */
19956	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19956	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19957	/* EXTRV_S_H_MM */	19957	/* EXTRV_S_H_MM */
19958	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19958	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19959	/* EXTRV_W */	19959	/* EXTRV_W */
19960	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19960	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19961	/* EXTRV_W_MM */	19961	/* EXTRV_W_MM */
19962	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	19962	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
19963	/* EXTR_RS_W */	19963	/* EXTR_RS_W */
19964	GPR32Opnd, ACC64DSPOpnd, uimm5,	19964	GPR32Opnd, ACC64DSPOpnd, uimm5,
19965	/* EXTR_RS_W_MM */	19965	/* EXTR_RS_W_MM */
19966	GPR32Opnd, ACC64DSPOpnd, uimm5,	19966	GPR32Opnd, ACC64DSPOpnd, uimm5,
19967	/* EXTR_R_W */	19967	/* EXTR_R_W */
19968	GPR32Opnd, ACC64DSPOpnd, uimm5,	19968	GPR32Opnd, ACC64DSPOpnd, uimm5,
19969	/* EXTR_R_W_MM */	19969	/* EXTR_R_W_MM */
19970	GPR32Opnd, ACC64DSPOpnd, uimm5,	19970	GPR32Opnd, ACC64DSPOpnd, uimm5,
19971	/* EXTR_S_H */	19971	/* EXTR_S_H */
19972	GPR32Opnd, ACC64DSPOpnd, uimm5,	19972	GPR32Opnd, ACC64DSPOpnd, uimm5,
19973	/* EXTR_S_H_MM */	19973	/* EXTR_S_H_MM */
19974	GPR32Opnd, ACC64DSPOpnd, uimm5,	19974	GPR32Opnd, ACC64DSPOpnd, uimm5,
19975	/* EXTR_W */	19975	/* EXTR_W */
19976	GPR32Opnd, ACC64DSPOpnd, uimm5,	19976	GPR32Opnd, ACC64DSPOpnd, uimm5,
19977	/* EXTR_W_MM */	19977	/* EXTR_W_MM */
19978	GPR32Opnd, ACC64DSPOpnd, uimm5,	19978	GPR32Opnd, ACC64DSPOpnd, uimm5,
19979	/* EXTS */	19979	/* EXTS */
19980	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	19980	GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19981	/* EXTS32 */	19981	/* EXTS32 */
19982	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	19982	GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19983	/* EXT_MM */	19983	/* EXT_MM */
19984	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	19984	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
19985	/* EXT_MMR6 */	19985	/* EXT_MMR6 */
19986	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	19986	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
19987	/* FABS_D32 */	19987	/* FABS_D32 */
19988	AFGR64Opnd, AFGR64Opnd,	19988	AFGR64Opnd, AFGR64Opnd,
19989	/* FABS_D32_MM */	19989	/* FABS_D32_MM */
19990	AFGR64Opnd, AFGR64Opnd,	19990	AFGR64Opnd, AFGR64Opnd,
19991	/* FABS_D64 */	19991	/* FABS_D64 */
19992	FGR64Opnd, FGR64Opnd,	19992	FGR64Opnd, FGR64Opnd,
19993	/* FABS_D64_MM */	19993	/* FABS_D64_MM */
19994	FGR64Opnd, FGR64Opnd,	19994	FGR64Opnd, FGR64Opnd,
19995	/* FABS_S */	19995	/* FABS_S */
19996	FGR32Opnd, FGR32Opnd,	19996	FGR32Opnd, FGR32Opnd,
19997	/* FABS_S_MM */	19997	/* FABS_S_MM */
19998	FGR32Opnd, FGR32Opnd,	19998	FGR32Opnd, FGR32Opnd,
19999	/* FADD_D */	19999	/* FADD_D */
20000	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20000	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20001	/* FADD_D32 */	20001	/* FADD_D32 */
20002	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20002	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20003	/* FADD_D32_MM */	20003	/* FADD_D32_MM */
20004	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20004	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20005	/* FADD_D64 */	20005	/* FADD_D64 */
20006	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20006	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20007	/* FADD_D64_MM */	20007	/* FADD_D64_MM */
20008	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20008	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20009	/* FADD_PS64 */	20009	/* FADD_PS64 */
20010	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20010	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20011	/* FADD_S */	20011	/* FADD_S */
20012	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20012	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20013	/* FADD_S_MM */	20013	/* FADD_S_MM */
20014	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20014	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20015	/* FADD_S_MMR6 */	20015	/* FADD_S_MMR6 */
20016	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20016	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20017	/* FADD_W */	20017	/* FADD_W */
20018	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20018	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20019	/* FCAF_D */	20019	/* FCAF_D */
20020	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20020	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20021	/* FCAF_W */	20021	/* FCAF_W */
20022	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20022	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20023	/* FCEQ_D */	20023	/* FCEQ_D */
20024	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20024	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20025	/* FCEQ_W */	20025	/* FCEQ_W */
20026	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20026	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20027	/* FCLASS_D */	20027	/* FCLASS_D */
20028	MSA128DOpnd, MSA128DOpnd,	20028	MSA128DOpnd, MSA128DOpnd,
20029	/* FCLASS_W */	20029	/* FCLASS_W */
20030	MSA128WOpnd, MSA128WOpnd,	20030	MSA128WOpnd, MSA128WOpnd,
20031	/* FCLE_D */	20031	/* FCLE_D */
20032	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20032	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20033	/* FCLE_W */	20033	/* FCLE_W */
20034	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20034	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20035	/* FCLT_D */	20035	/* FCLT_D */
20036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20037	/* FCLT_W */	20037	/* FCLT_W */
20038	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20038	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20039	/* FCMP_D32 */	20039	/* FCMP_D32 */
20040	AFGR64, AFGR64, condcode,	20040	AFGR64, AFGR64, condcode,
20041	/* FCMP_D32_MM */	20041	/* FCMP_D32_MM */
20042	AFGR64, AFGR64, condcode,	20042	AFGR64, AFGR64, condcode,
20043	/* FCMP_D64 */	20043	/* FCMP_D64 */
20044	FGR64, FGR64, condcode,	20044	FGR64, FGR64, condcode,
20045	/* FCMP_S32 */	20045	/* FCMP_S32 */
20046	FGR32, FGR32, condcode,	20046	FGR32, FGR32, condcode,
20047	/* FCMP_S32_MM */	20047	/* FCMP_S32_MM */
20048	FGR32, FGR32, condcode,	20048	FGR32, FGR32, condcode,
20049	/* FCNE_D */	20049	/* FCNE_D */
20050	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20050	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20051	/* FCNE_W */	20051	/* FCNE_W */
20052	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20052	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20053	/* FCOR_D */	20053	/* FCOR_D */
20054	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20054	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20055	/* FCOR_W */	20055	/* FCOR_W */
20056	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20056	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20057	/* FCUEQ_D */	20057	/* FCUEQ_D */
20058	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20058	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20059	/* FCUEQ_W */	20059	/* FCUEQ_W */
20060	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20060	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20061	/* FCULE_D */	20061	/* FCULE_D */
20062	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20062	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20063	/* FCULE_W */	20063	/* FCULE_W */
20064	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20064	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20065	/* FCULT_D */	20065	/* FCULT_D */
20066	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20066	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20067	/* FCULT_W */	20067	/* FCULT_W */
20068	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20068	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20069	/* FCUNE_D */	20069	/* FCUNE_D */
20070	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20070	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20071	/* FCUNE_W */	20071	/* FCUNE_W */
20072	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20072	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20073	/* FCUN_D */	20073	/* FCUN_D */
20074	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20074	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20075	/* FCUN_W */	20075	/* FCUN_W */
20076	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20076	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20077	/* FDIV_D */	20077	/* FDIV_D */
20078	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20078	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20079	/* FDIV_D32 */	20079	/* FDIV_D32 */
20080	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20080	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20081	/* FDIV_D32_MM */	20081	/* FDIV_D32_MM */
20082	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20082	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20083	/* FDIV_D64 */	20083	/* FDIV_D64 */
20084	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20084	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20085	/* FDIV_D64_MM */	20085	/* FDIV_D64_MM */
20086	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20086	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20087	/* FDIV_S */	20087	/* FDIV_S */
20088	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20088	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20089	/* FDIV_S_MM */	20089	/* FDIV_S_MM */
20090	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20090	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20091	/* FDIV_S_MMR6 */	20091	/* FDIV_S_MMR6 */
20092	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20092	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20093	/* FDIV_W */	20093	/* FDIV_W */
20094	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20094	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20095	/* FEXDO_H */	20095	/* FEXDO_H */
20096	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	20096	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,
20097	/* FEXDO_W */	20097	/* FEXDO_W */
20098	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	20098	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,
20099	/* FEXP2_D */	20099	/* FEXP2_D */
20100	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20100	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20101	/* FEXP2_W */	20101	/* FEXP2_W */
20102	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20102	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20103	/* FEXUPL_D */	20103	/* FEXUPL_D */
20104	MSA128DOpnd, MSA128WOpnd,	20104	MSA128DOpnd, MSA128WOpnd,
20105	/* FEXUPL_W */	20105	/* FEXUPL_W */
20106	MSA128WOpnd, MSA128HOpnd,	20106	MSA128WOpnd, MSA128HOpnd,
20107	/* FEXUPR_D */	20107	/* FEXUPR_D */
20108	MSA128DOpnd, MSA128WOpnd,	20108	MSA128DOpnd, MSA128WOpnd,
20109	/* FEXUPR_W */	20109	/* FEXUPR_W */
20110	MSA128WOpnd, MSA128HOpnd,	20110	MSA128WOpnd, MSA128HOpnd,
20111	/* FFINT_S_D */	20111	/* FFINT_S_D */
20112	MSA128DOpnd, MSA128DOpnd,	20112	MSA128DOpnd, MSA128DOpnd,
20113	/* FFINT_S_W */	20113	/* FFINT_S_W */
20114	MSA128WOpnd, MSA128WOpnd,	20114	MSA128WOpnd, MSA128WOpnd,
20115	/* FFINT_U_D */	20115	/* FFINT_U_D */
20116	MSA128DOpnd, MSA128DOpnd,	20116	MSA128DOpnd, MSA128DOpnd,
20117	/* FFINT_U_W */	20117	/* FFINT_U_W */
20118	MSA128WOpnd, MSA128WOpnd,	20118	MSA128WOpnd, MSA128WOpnd,
20119	/* FFQL_D */	20119	/* FFQL_D */
20120	MSA128DOpnd, MSA128WOpnd,	20120	MSA128DOpnd, MSA128WOpnd,
20121	/* FFQL_W */	20121	/* FFQL_W */
20122	MSA128WOpnd, MSA128HOpnd,	20122	MSA128WOpnd, MSA128HOpnd,
20123	/* FFQR_D */	20123	/* FFQR_D */
20124	MSA128DOpnd, MSA128WOpnd,	20124	MSA128DOpnd, MSA128WOpnd,
20125	/* FFQR_W */	20125	/* FFQR_W */
20126	MSA128WOpnd, MSA128HOpnd,	20126	MSA128WOpnd, MSA128HOpnd,
20127	/* FILL_B */	20127	/* FILL_B */
20128	MSA128BOpnd, GPR32Opnd,	20128	MSA128BOpnd, GPR32Opnd,
20129	/* FILL_D */	20129	/* FILL_D */
20130	MSA128DOpnd, GPR64Opnd,	20130	MSA128DOpnd, GPR64Opnd,
20131	/* FILL_H */	20131	/* FILL_H */
20132	MSA128HOpnd, GPR32Opnd,	20132	MSA128HOpnd, GPR32Opnd,
20133	/* FILL_W */	20133	/* FILL_W */
20134	MSA128WOpnd, GPR32Opnd,	20134	MSA128WOpnd, GPR32Opnd,
20135	/* FLOG2_D */	20135	/* FLOG2_D */
20136	MSA128DOpnd, MSA128DOpnd,	20136	MSA128DOpnd, MSA128DOpnd,
20137	/* FLOG2_W */	20137	/* FLOG2_W */
20138	MSA128WOpnd, MSA128WOpnd,	20138	MSA128WOpnd, MSA128WOpnd,
20139	/* FLOOR_L_D64 */	20139	/* FLOOR_L_D64 */
20140	FGR64Opnd, FGR64Opnd,	20140	FGR64Opnd, FGR64Opnd,
20141	/* FLOOR_L_D_MMR6 */	20141	/* FLOOR_L_D_MMR6 */
20142	FGR64Opnd, FGR64Opnd,	20142	FGR64Opnd, FGR64Opnd,
20143	/* FLOOR_L_S */	20143	/* FLOOR_L_S */
20144	FGR64Opnd, FGR32Opnd,	20144	FGR64Opnd, FGR32Opnd,
20145	/* FLOOR_L_S_MMR6 */	20145	/* FLOOR_L_S_MMR6 */
20146	FGR64Opnd, FGR32Opnd,	20146	FGR64Opnd, FGR32Opnd,
20147	/* FLOOR_W_D32 */	20147	/* FLOOR_W_D32 */
20148	FGR32Opnd, AFGR64Opnd,	20148	FGR32Opnd, AFGR64Opnd,
20149	/* FLOOR_W_D64 */	20149	/* FLOOR_W_D64 */
20150	FGR32Opnd, FGR64Opnd,	20150	FGR32Opnd, FGR64Opnd,
20151	/* FLOOR_W_D_MMR6 */	20151	/* FLOOR_W_D_MMR6 */
20152	FGR32Opnd, AFGR64Opnd,	20152	FGR32Opnd, AFGR64Opnd,
20153	/* FLOOR_W_MM */	20153	/* FLOOR_W_MM */
20154	FGR32Opnd, AFGR64Opnd,	20154	FGR32Opnd, AFGR64Opnd,
20155	/* FLOOR_W_S */	20155	/* FLOOR_W_S */
20156	FGR32Opnd, FGR32Opnd,	20156	FGR32Opnd, FGR32Opnd,
20157	/* FLOOR_W_S_MM */	20157	/* FLOOR_W_S_MM */
20158	FGR32Opnd, FGR32Opnd,	20158	FGR32Opnd, FGR32Opnd,
20159	/* FLOOR_W_S_MMR6 */	20159	/* FLOOR_W_S_MMR6 */
20160	FGR32Opnd, FGR32Opnd,	20160	FGR32Opnd, FGR32Opnd,
20161	/* FMADD_D */	20161	/* FMADD_D */
20162	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20162	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20163	/* FMADD_W */	20163	/* FMADD_W */
20164	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20164	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20165	/* FMAX_A_D */	20165	/* FMAX_A_D */
20166	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20166	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20167	/* FMAX_A_W */	20167	/* FMAX_A_W */
20168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20169	/* FMAX_D */	20169	/* FMAX_D */
20170	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20170	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20171	/* FMAX_W */	20171	/* FMAX_W */
20172	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20172	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20173	/* FMIN_A_D */	20173	/* FMIN_A_D */
20174	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20174	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20175	/* FMIN_A_W */	20175	/* FMIN_A_W */
20176	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20176	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20177	/* FMIN_D */	20177	/* FMIN_D */
20178	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20178	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20179	/* FMIN_W */	20179	/* FMIN_W */
20180	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20180	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20181	/* FMOV_D32 */	20181	/* FMOV_D32 */
20182	AFGR64Opnd, AFGR64Opnd,	20182	AFGR64Opnd, AFGR64Opnd,
20183	/* FMOV_D32_MM */	20183	/* FMOV_D32_MM */
20184	AFGR64Opnd, AFGR64Opnd,	20184	AFGR64Opnd, AFGR64Opnd,
20185	/* FMOV_D64 */	20185	/* FMOV_D64 */
20186	FGR64Opnd, FGR64Opnd,	20186	FGR64Opnd, FGR64Opnd,
20187	/* FMOV_D64_MM */	20187	/* FMOV_D64_MM */
20188	FGR64Opnd, FGR64Opnd,	20188	FGR64Opnd, FGR64Opnd,
20189	/* FMOV_D_MMR6 */	20189	/* FMOV_D_MMR6 */
20190	FGR64Opnd, FGR64Opnd,	20190	FGR64Opnd, FGR64Opnd,
20191	/* FMOV_S */	20191	/* FMOV_S */
20192	FGR32Opnd, FGR32Opnd,	20192	FGR32Opnd, FGR32Opnd,
20193	/* FMOV_S_MM */	20193	/* FMOV_S_MM */
20194	FGR32Opnd, FGR32Opnd,	20194	FGR32Opnd, FGR32Opnd,
20195	/* FMOV_S_MMR6 */	20195	/* FMOV_S_MMR6 */
20196	FGR32Opnd, FGR32Opnd,	20196	FGR32Opnd, FGR32Opnd,
20197	/* FMSUB_D */	20197	/* FMSUB_D */
20198	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20198	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20199	/* FMSUB_W */	20199	/* FMSUB_W */
20200	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20200	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20201	/* FMUL_D */	20201	/* FMUL_D */
20202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20203	/* FMUL_D32 */	20203	/* FMUL_D32 */
20204	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20204	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20205	/* FMUL_D32_MM */	20205	/* FMUL_D32_MM */
20206	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20206	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20207	/* FMUL_D64 */	20207	/* FMUL_D64 */
20208	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20208	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20209	/* FMUL_D64_MM */	20209	/* FMUL_D64_MM */
20210	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20210	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20211	/* FMUL_PS64 */	20211	/* FMUL_PS64 */
20212	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20212	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20213	/* FMUL_S */	20213	/* FMUL_S */
20214	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20214	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20215	/* FMUL_S_MM */	20215	/* FMUL_S_MM */
20216	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20216	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20217	/* FMUL_S_MMR6 */	20217	/* FMUL_S_MMR6 */
20218	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20218	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20219	/* FMUL_W */	20219	/* FMUL_W */
20220	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20220	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20221	/* FNEG_D32 */	20221	/* FNEG_D32 */
20222	AFGR64Opnd, AFGR64Opnd,	20222	AFGR64Opnd, AFGR64Opnd,
20223	/* FNEG_D32_MM */	20223	/* FNEG_D32_MM */
20224	AFGR64Opnd, AFGR64Opnd,	20224	AFGR64Opnd, AFGR64Opnd,
20225	/* FNEG_D64 */	20225	/* FNEG_D64 */
20226	FGR64Opnd, FGR64Opnd,	20226	FGR64Opnd, FGR64Opnd,
20227	/* FNEG_D64_MM */	20227	/* FNEG_D64_MM */
20228	FGR64Opnd, FGR64Opnd,	20228	FGR64Opnd, FGR64Opnd,
20229	/* FNEG_S */	20229	/* FNEG_S */
20230	FGR32Opnd, FGR32Opnd,	20230	FGR32Opnd, FGR32Opnd,
20231	/* FNEG_S_MM */	20231	/* FNEG_S_MM */
20232	FGR32Opnd, FGR32Opnd,	20232	FGR32Opnd, FGR32Opnd,
20233	/* FNEG_S_MMR6 */	20233	/* FNEG_S_MMR6 */
20234	FGR32Opnd, FGR32Opnd,	20234	FGR32Opnd, FGR32Opnd,
20235	/* FORK */	20235	/* FORK */
20236	GPR32Opnd, GPR32Opnd, GPR32Opnd,	20236	GPR32Opnd, GPR32Opnd, GPR32Opnd,
20237	/* FRCP_D */	20237	/* FRCP_D */
20238	MSA128DOpnd, MSA128DOpnd,	20238	MSA128DOpnd, MSA128DOpnd,
20239	/* FRCP_W */	20239	/* FRCP_W */
20240	MSA128WOpnd, MSA128WOpnd,	20240	MSA128WOpnd, MSA128WOpnd,
20241	/* FRINT_D */	20241	/* FRINT_D */
20242	MSA128DOpnd, MSA128DOpnd,	20242	MSA128DOpnd, MSA128DOpnd,
20243	/* FRINT_W */	20243	/* FRINT_W */
20244	MSA128WOpnd, MSA128WOpnd,	20244	MSA128WOpnd, MSA128WOpnd,
20245	/* FRSQRT_D */	20245	/* FRSQRT_D */
20246	MSA128DOpnd, MSA128DOpnd,	20246	MSA128DOpnd, MSA128DOpnd,
20247	/* FRSQRT_W */	20247	/* FRSQRT_W */
20248	MSA128WOpnd, MSA128WOpnd,	20248	MSA128WOpnd, MSA128WOpnd,
20249	/* FSAF_D */	20249	/* FSAF_D */
20250	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20250	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20251	/* FSAF_W */	20251	/* FSAF_W */
20252	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20252	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20253	/* FSEQ_D */	20253	/* FSEQ_D */
20254	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20254	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20255	/* FSEQ_W */	20255	/* FSEQ_W */
20256	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20256	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20257	/* FSLE_D */	20257	/* FSLE_D */
20258	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20258	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20259	/* FSLE_W */	20259	/* FSLE_W */
20260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20261	/* FSLT_D */	20261	/* FSLT_D */
20262	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20262	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20263	/* FSLT_W */	20263	/* FSLT_W */
20264	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20264	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20265	/* FSNE_D */	20265	/* FSNE_D */
20266	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20266	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20267	/* FSNE_W */	20267	/* FSNE_W */
20268	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20268	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20269	/* FSOR_D */	20269	/* FSOR_D */
20270	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20270	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20271	/* FSOR_W */	20271	/* FSOR_W */
20272	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20272	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20273	/* FSQRT_D */	20273	/* FSQRT_D */
20274	MSA128DOpnd, MSA128DOpnd,	20274	MSA128DOpnd, MSA128DOpnd,
20275	/* FSQRT_D32 */	20275	/* FSQRT_D32 */
20276	AFGR64Opnd, AFGR64Opnd,	20276	AFGR64Opnd, AFGR64Opnd,
20277	/* FSQRT_D32_MM */	20277	/* FSQRT_D32_MM */
20278	AFGR64Opnd, AFGR64Opnd,	20278	AFGR64Opnd, AFGR64Opnd,
20279	/* FSQRT_D64 */	20279	/* FSQRT_D64 */
20280	FGR64Opnd, FGR64Opnd,	20280	FGR64Opnd, FGR64Opnd,
20281	/* FSQRT_D64_MM */	20281	/* FSQRT_D64_MM */
20282	FGR64Opnd, FGR64Opnd,	20282	FGR64Opnd, FGR64Opnd,
20283	/* FSQRT_S */	20283	/* FSQRT_S */
20284	FGR32Opnd, FGR32Opnd,	20284	FGR32Opnd, FGR32Opnd,
20285	/* FSQRT_S_MM */	20285	/* FSQRT_S_MM */
20286	FGR32Opnd, FGR32Opnd,	20286	FGR32Opnd, FGR32Opnd,
20287	/* FSQRT_W */	20287	/* FSQRT_W */
20288	MSA128WOpnd, MSA128WOpnd,	20288	MSA128WOpnd, MSA128WOpnd,
20289	/* FSUB_D */	20289	/* FSUB_D */
20290	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20290	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20291	/* FSUB_D32 */	20291	/* FSUB_D32 */
20292	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20292	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20293	/* FSUB_D32_MM */	20293	/* FSUB_D32_MM */
20294	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20294	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20295	/* FSUB_D64 */	20295	/* FSUB_D64 */
20296	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20296	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20297	/* FSUB_D64_MM */	20297	/* FSUB_D64_MM */
20298	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20298	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20299	/* FSUB_PS64 */	20299	/* FSUB_PS64 */
20300	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20300	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20301	/* FSUB_S */	20301	/* FSUB_S */
20302	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20302	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20303	/* FSUB_S_MM */	20303	/* FSUB_S_MM */
20304	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20304	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20305	/* FSUB_S_MMR6 */	20305	/* FSUB_S_MMR6 */
20306	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20306	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20307	/* FSUB_W */	20307	/* FSUB_W */
20308	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20308	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20309	/* FSUEQ_D */	20309	/* FSUEQ_D */
20310	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20310	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20311	/* FSUEQ_W */	20311	/* FSUEQ_W */
20312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20313	/* FSULE_D */	20313	/* FSULE_D */
20314	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20314	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20315	/* FSULE_W */	20315	/* FSULE_W */
20316	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20316	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20317	/* FSULT_D */	20317	/* FSULT_D */
20318	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20318	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20319	/* FSULT_W */	20319	/* FSULT_W */
20320	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20320	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20321	/* FSUNE_D */	20321	/* FSUNE_D */
20322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20323	/* FSUNE_W */	20323	/* FSUNE_W */
20324	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20324	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20325	/* FSUN_D */	20325	/* FSUN_D */
20326	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20326	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20327	/* FSUN_W */	20327	/* FSUN_W */
20328	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20328	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20329	/* FTINT_S_D */	20329	/* FTINT_S_D */
20330	MSA128DOpnd, MSA128DOpnd,	20330	MSA128DOpnd, MSA128DOpnd,
20331	/* FTINT_S_W */	20331	/* FTINT_S_W */
20332	MSA128WOpnd, MSA128WOpnd,	20332	MSA128WOpnd, MSA128WOpnd,
20333	/* FTINT_U_D */	20333	/* FTINT_U_D */
20334	MSA128DOpnd, MSA128DOpnd,	20334	MSA128DOpnd, MSA128DOpnd,
20335	/* FTINT_U_W */	20335	/* FTINT_U_W */
20336	MSA128WOpnd, MSA128WOpnd,	20336	MSA128WOpnd, MSA128WOpnd,
20337	/* FTQ_H */	20337	/* FTQ_H */
20338	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	20338	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,
20339	/* FTQ_W */	20339	/* FTQ_W */
20340	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	20340	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,
20341	/* FTRUNC_S_D */	20341	/* FTRUNC_S_D */
20342	MSA128DOpnd, MSA128DOpnd,	20342	MSA128DOpnd, MSA128DOpnd,
20343	/* FTRUNC_S_W */	20343	/* FTRUNC_S_W */
20344	MSA128WOpnd, MSA128WOpnd,	20344	MSA128WOpnd, MSA128WOpnd,
20345	/* FTRUNC_U_D */	20345	/* FTRUNC_U_D */
20346	MSA128DOpnd, MSA128DOpnd,	20346	MSA128DOpnd, MSA128DOpnd,
20347	/* FTRUNC_U_W */	20347	/* FTRUNC_U_W */
20348	MSA128WOpnd, MSA128WOpnd,	20348	MSA128WOpnd, MSA128WOpnd,
20349	/* GINVI */	20349	/* GINVI */
20350	GPR32Opnd,	20350	GPR32Opnd,
20351	/* GINVI_MMR6 */	20351	/* GINVI_MMR6 */
20352	GPR32Opnd,	20352	GPR32Opnd,
20353	/* GINVT */	20353	/* GINVT */
20354	GPR32Opnd, uimm2,	20354	GPR32Opnd, uimm2,
20355	/* GINVT_MMR6 */	20355	/* GINVT_MMR6 */
20356	GPR32Opnd, uimm2,	20356	GPR32Opnd, uimm2,
20357	/* HADD_S_D */	20357	/* HADD_S_D */
20358	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	20358	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20359	/* HADD_S_H */	20359	/* HADD_S_H */
20360	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	20360	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20361	/* HADD_S_W */	20361	/* HADD_S_W */
20362	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	20362	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20363	/* HADD_U_D */	20363	/* HADD_U_D */
20364	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	20364	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20365	/* HADD_U_H */	20365	/* HADD_U_H */
20366	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	20366	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20367	/* HADD_U_W */	20367	/* HADD_U_W */
20368	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	20368	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20369	/* HSUB_S_D */	20369	/* HSUB_S_D */
20370	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	20370	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20371	/* HSUB_S_H */	20371	/* HSUB_S_H */
20372	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	20372	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20373	/* HSUB_S_W */	20373	/* HSUB_S_W */
20374	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	20374	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20375	/* HSUB_U_D */	20375	/* HSUB_U_D */
20376	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	20376	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20377	/* HSUB_U_H */	20377	/* HSUB_U_H */
20378	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	20378	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20379	/* HSUB_U_W */	20379	/* HSUB_U_W */
20380	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	20380	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20381	/* HYPCALL */	20381	/* HYPCALL */
20382	uimm10,	20382	uimm10,
20383	/* HYPCALL_MM */	20383	/* HYPCALL_MM */
20384	uimm10,	20384	uimm10,
20385	/* ILVEV_B */	20385	/* ILVEV_B */
20386	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20386	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20387	/* ILVEV_D */	20387	/* ILVEV_D */
20388	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20388	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20389	/* ILVEV_H */	20389	/* ILVEV_H */
20390	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20390	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20391	/* ILVEV_W */	20391	/* ILVEV_W */
20392	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20392	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20393	/* ILVL_B */	20393	/* ILVL_B */
20394	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20394	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20395	/* ILVL_D */	20395	/* ILVL_D */
20396	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20396	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20397	/* ILVL_H */	20397	/* ILVL_H */
20398	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20398	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20399	/* ILVL_W */	20399	/* ILVL_W */
20400	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20400	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20401	/* ILVOD_B */	20401	/* ILVOD_B */
20402	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20402	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20403	/* ILVOD_D */	20403	/* ILVOD_D */
20404	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20404	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20405	/* ILVOD_H */	20405	/* ILVOD_H */
20406	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20406	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20407	/* ILVOD_W */	20407	/* ILVOD_W */
20408	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20408	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20409	/* ILVR_B */	20409	/* ILVR_B */
20410	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20410	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20411	/* ILVR_D */	20411	/* ILVR_D */
20412	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20412	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20413	/* ILVR_H */	20413	/* ILVR_H */
20414	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20414	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20415	/* ILVR_W */	20415	/* ILVR_W */
20416	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20416	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20417	/* INS */	20417	/* INS */
20418	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	20418	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20419	/* INSERT_B */	20419	/* INSERT_B */
20420	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,	20420	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,
20421	/* INSERT_D */	20421	/* INSERT_D */
20422	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,	20422	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,
20423	/* INSERT_H */	20423	/* INSERT_H */
20424	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,	20424	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,
20425	/* INSERT_W */	20425	/* INSERT_W */
20426	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,	20426	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,
20427	/* INSV */	20427	/* INSV */
20428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	20428	GPR32Opnd, GPR32Opnd, GPR32Opnd,
20429	/* INSVE_B */	20429	/* INSVE_B */
20430	MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,	20430	MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,
20431	/* INSVE_D */	20431	/* INSVE_D */
20432	MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,	20432	MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,
20433	/* INSVE_H */	20433	/* INSVE_H */
20434	MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,	20434	MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,
20435	/* INSVE_W */	20435	/* INSVE_W */
20436	MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,	20436	MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,
20437	/* INSV_MM */	20437	/* INSV_MM */
20438	GPR32Opnd, GPR32Opnd, GPR32Opnd,	20438	GPR32Opnd, GPR32Opnd, GPR32Opnd,
20439	/* INS_MM */	20439	/* INS_MM */
20440	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	20440	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20441	/* INS_MMR6 */	20441	/* INS_MMR6 */
20442	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	20442	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20443	/* J */	20443	/* J */
20444	jmptarget,	20444	jmptarget,
20445	/* JAL */	20445	/* JAL */
20446	calltarget,	20446	calltarget,
20447	/* JALR */	20447	/* JALR */
20448	GPR32Opnd, GPR32Opnd,	20448	GPR32Opnd, GPR32Opnd,
20449	/* JALR16_MM */	20449	/* JALR16_MM */
20450	GPR32Opnd,	20450	GPR32Opnd,
20451	/* JALR64 */	20451	/* JALR64 */
20452	GPR64Opnd, GPR64Opnd,	20452	GPR64Opnd, GPR64Opnd,
20453	/* JALRC16_MMR6 */	20453	/* JALRC16_MMR6 */
20454	GPR32Opnd,	20454	GPR32Opnd,
20455	/* JALRC_HB_MMR6 */	20455	/* JALRC_HB_MMR6 */
20456	GPR32Opnd, GPR32Opnd,	20456	GPR32Opnd, GPR32Opnd,
20457	/* JALRC_MMR6 */	20457	/* JALRC_MMR6 */
20458	GPR32Opnd, GPR32Opnd,	20458	GPR32Opnd, GPR32Opnd,
20459	/* JALRS16_MM */	20459	/* JALRS16_MM */
20460	GPR32Opnd,	20460	GPR32Opnd,
20461	/* JALRS_MM */	20461	/* JALRS_MM */
20462	GPR32Opnd, GPR32Opnd,	20462	GPR32Opnd, GPR32Opnd,
20463	/* JALR_HB */	20463	/* JALR_HB */
20464	GPR32Opnd, GPR32Opnd,	20464	GPR32Opnd, GPR32Opnd,
20465	/* JALR_HB64 */	20465	/* JALR_HB64 */
20466	GPR64Opnd, GPR64Opnd,	20466	GPR64Opnd, GPR64Opnd,
20467	/* JALR_MM */	20467	/* JALR_MM */
20468	GPR32Opnd, GPR32Opnd,	20468	GPR32Opnd, GPR32Opnd,
20469	/* JALS_MM */	20469	/* JALS_MM */
20470	calltarget_mm,	20470	calltarget_mm,
20471	/* JALX */	20471	/* JALX */
20472	calltarget,	20472	calltarget,
20473	/* JALX_MM */	20473	/* JALX_MM */
20474	calltarget,	20474	calltarget,
20475	/* JAL_MM */	20475	/* JAL_MM */
20476	calltarget_mm,	20476	calltarget_mm,
20477	/* JIALC */	20477	/* JIALC */
20478	GPR32Opnd, calloffset16,	20478	GPR32Opnd, calloffset16,
20479	/* JIALC64 */	20479	/* JIALC64 */
20480	GPR64Opnd, calloffset16,	20480	GPR64Opnd, calloffset16,
20481	/* JIALC_MMR6 */	20481	/* JIALC_MMR6 */
20482	GPR32Opnd, calloffset16,	20482	GPR32Opnd, calloffset16,
20483	/* JIC */	20483	/* JIC */
20484	GPR32Opnd, jmpoffset16,	20484	GPR32Opnd, jmpoffset16,
20485	/* JIC64 */	20485	/* JIC64 */
20486	GPR64Opnd, jmpoffset16,	20486	GPR64Opnd, jmpoffset16,
20487	/* JIC_MMR6 */	20487	/* JIC_MMR6 */
20488	GPR32Opnd, jmpoffset16,	20488	GPR32Opnd, jmpoffset16,
20489	/* JR */	20489	/* JR */
20490	GPR32Opnd,	20490	GPR32Opnd,
20491	/* JR16_MM */	20491	/* JR16_MM */
20492	GPR32Opnd,	20492	GPR32Opnd,
20493	/* JR64 */	20493	/* JR64 */
20494	GPR64Opnd,	20494	GPR64Opnd,
20495	/* JRADDIUSP */	20495	/* JRADDIUSP */
20496	uimm5_lsl2,	20496	uimm5_lsl2,
20497	/* JRC16_MM */	20497	/* JRC16_MM */
20498	GPR32Opnd,	20498	GPR32Opnd,
20499	/* JRC16_MMR6 */	20499	/* JRC16_MMR6 */
20500	GPR32Opnd,	20500	GPR32Opnd,
20501	/* JRCADDIUSP_MMR6 */	20501	/* JRCADDIUSP_MMR6 */
20502	uimm5_lsl2,	20502	uimm5_lsl2,
20503	/* JR_HB */	20503	/* JR_HB */
20504	GPR32Opnd,	20504	GPR32Opnd,
20505	/* JR_HB64 */	20505	/* JR_HB64 */
20506	GPR64Opnd,	20506	GPR64Opnd,
20507	/* JR_HB64_R6 */	20507	/* JR_HB64_R6 */
20508	GPR64Opnd,	20508	GPR64Opnd,
20509	/* JR_HB_R6 */	20509	/* JR_HB_R6 */
20510	GPR32Opnd,	20510	GPR32Opnd,
20511	/* JR_MM */	20511	/* JR_MM */
20512	GPR32Opnd,	20512	GPR32Opnd,
20513	/* J_MM */	20513	/* J_MM */
20514	jmptarget_mm,	20514	jmptarget_mm,
20515	/* Jal16 */	20515	/* Jal16 */
20516	uimm26,	20516	uimm26,
20517	/* JalB16 */	20517	/* JalB16 */
20518	uimm26,	20518	uimm26,
20519	/* JrRa16 */	20519	/* JrRa16 */
20520	/* JrcRa16 */	20520	/* JrcRa16 */
20521	/* JrcRx16 */	20521	/* JrcRx16 */
20522	CPU16Regs,	20522	CPU16Regs,
20523	/* JumpLinkReg16 */	20523	/* JumpLinkReg16 */
20524	CPU16Regs,	20524	CPU16Regs,
20525	/* LB */	20525	/* LB */
20526	GPR32Opnd, -1, simm16,	20526	GPR32Opnd, -1, simm16,
20527	/* LB64 */	20527	/* LB64 */
20528	GPR64Opnd, -1, simm16,	20528	GPR64Opnd, -1, simm16,
20529	/* LBE */	20529	/* LBE */
20530	GPR32Opnd, -1, simm9,	20530	GPR32Opnd, -1, simm9,
20531	/* LBE_MM */	20531	/* LBE_MM */
20532	GPR32Opnd, -1, simm16,	20532	GPR32Opnd, -1, simm16,
20533	/* LBU16_MM */	20533	/* LBU16_MM */
20534	GPRMM16Opnd, -1, simm4,	20534	GPRMM16Opnd, -1, simm4,
20535	/* LBUX */	20535	/* LBUX */
20536	GPR32Opnd, -1, -1,	20536	GPR32Opnd, -1, -1,
20537	/* LBUX_MM */	20537	/* LBUX_MM */
20538	GPR32Opnd, -1, -1,	20538	GPR32Opnd, -1, -1,
20539	/* LBU_MMR6 */	20539	/* LBU_MMR6 */
20540	GPR32Opnd, -1, simm16,	20540	GPR32Opnd, -1, simm16,
20541	/* LB_MM */	20541	/* LB_MM */
20542	GPR32Opnd, -1, simm16,	20542	GPR32Opnd, -1, simm16,
20543	/* LB_MMR6 */	20543	/* LB_MMR6 */
20544	GPR32Opnd, -1, simm16,	20544	GPR32Opnd, -1, simm16,
20545	/* LBu */	20545	/* LBu */
20546	GPR32Opnd, -1, simm16,	20546	GPR32Opnd, -1, simm16,
20547	/* LBu64 */	20547	/* LBu64 */
20548	GPR64Opnd, -1, simm16,	20548	GPR64Opnd, -1, simm16,
20549	/* LBuE */	20549	/* LBuE */
20550	GPR32Opnd, -1, simm9,	20550	GPR32Opnd, -1, simm9,
20551	/* LBuE_MM */	20551	/* LBuE_MM */
20552	GPR32Opnd, -1, simm16,	20552	GPR32Opnd, -1, simm16,
20553	/* LBu_MM */	20553	/* LBu_MM */
20554	GPR32Opnd, -1, simm16,	20554	GPR32Opnd, -1, simm16,
20555	/* LD */	20555	/* LD */
20556	GPR64Opnd, -1, simm16,	20556	GPR64Opnd, -1, simm16,
20557	/* LDC1 */	20557	/* LDC1 */
20558	AFGR64Opnd, -1, simm16,	20558	AFGR64Opnd, -1, simm16,
20559	/* LDC164 */	20559	/* LDC164 */
20560	FGR64Opnd, -1, simm16,	20560	FGR64Opnd, -1, simm16,
20561	/* LDC1_D64_MMR6 */	20561	/* LDC1_D64_MMR6 */
20562	FGR64Opnd, -1, simm16,	20562	FGR64Opnd, -1, simm16,
20563	/* LDC1_MM_D32 */	20563	/* LDC1_MM_D32 */
20564	AFGR64Opnd, -1, simm16,	20564	AFGR64Opnd, -1, simm16,
20565	/* LDC1_MM_D64 */	20565	/* LDC1_MM_D64 */
20566	FGR64Opnd, -1, simm16,	20566	FGR64Opnd, -1, simm16,
20567	/* LDC2 */	20567	/* LDC2 */
20568	COP2Opnd, -1, simm16,	20568	COP2Opnd, -1, simm16,
20569	/* LDC2_MMR6 */	20569	/* LDC2_MMR6 */
20570	COP2Opnd, GPR32, simm11,	20570	COP2Opnd, GPR32, simm11,
20571	/* LDC2_R6 */	20571	/* LDC2_R6 */
20572	COP2Opnd, -1, simm11,	20572	COP2Opnd, -1, simm11,
20573	/* LDC3 */	20573	/* LDC3 */
20574	COP3Opnd, -1, simm16,	20574	COP3Opnd, -1, simm16,
20575	/* LDI_B */	20575	/* LDI_B */
20576	MSA128BOpnd, vsplat_simm10,	20576	MSA128BOpnd, vsplat_simm10,
20577	/* LDI_D */	20577	/* LDI_D */
20578	MSA128DOpnd, vsplat_simm10,	20578	MSA128DOpnd, vsplat_simm10,
20579	/* LDI_H */	20579	/* LDI_H */
20580	MSA128HOpnd, vsplat_simm10,	20580	MSA128HOpnd, vsplat_simm10,
20581	/* LDI_W */	20581	/* LDI_W */
20582	MSA128WOpnd, vsplat_simm10,	20582	MSA128WOpnd, vsplat_simm10,
20583	/* LDL */	20583	/* LDL */
20584	GPR64Opnd, -1, simm16, GPR64Opnd,	20584	GPR64Opnd, -1, simm16, GPR64Opnd,
20585	/* LDPC */	20585	/* LDPC */
20586	GPR64Opnd, simm18_lsl3,	20586	GPR64Opnd, simm18_lsl3,
20587	/* LDR */	20587	/* LDR */
20588	GPR64Opnd, -1, simm16, GPR64Opnd,	20588	GPR64Opnd, -1, simm16, GPR64Opnd,
20589	/* LDXC1 */	20589	/* LDXC1 */
20590	AFGR64Opnd, -1, -1,	20590	AFGR64Opnd, -1, -1,
20591	/* LDXC164 */	20591	/* LDXC164 */
20592	FGR64Opnd, -1, -1,	20592	FGR64Opnd, -1, -1,
20593	/* LD_B */	20593	/* LD_B */
20594	MSA128BOpnd, -1, simm10,	20594	MSA128BOpnd, -1, simm10,
20595	/* LD_D */	20595	/* LD_D */
20596	MSA128DOpnd, -1, simm10_lsl3,	20596	MSA128DOpnd, -1, simm10_lsl3,
20597	/* LD_H */	20597	/* LD_H */
20598	MSA128HOpnd, -1, simm10_lsl1,	20598	MSA128HOpnd, -1, simm10_lsl1,
20599	/* LD_W */	20599	/* LD_W */
20600	MSA128WOpnd, -1, simm10_lsl2,	20600	MSA128WOpnd, -1, simm10_lsl2,
20601	/* LEA_ADDiu */	20601	/* LEA_ADDiu */
20602	GPR32Opnd, -1, simm16,	20602	GPR32Opnd, -1, simm16,
20603	/* LEA_ADDiu64 */	20603	/* LEA_ADDiu64 */
20604	GPR64Opnd, -1, simm16,	20604	GPR64Opnd, -1, simm16,
20605	/* LEA_ADDiu_MM */	20605	/* LEA_ADDiu_MM */
20606	GPR32Opnd, -1, simm16,	20606	GPR32Opnd, -1, simm16,
20607	/* LH */	20607	/* LH */
20608	GPR32Opnd, -1, simm16,	20608	GPR32Opnd, -1, simm16,
20609	/* LH64 */	20609	/* LH64 */
20610	GPR64Opnd, -1, simm16,	20610	GPR64Opnd, -1, simm16,
20611	/* LHE */	20611	/* LHE */
20612	GPR32Opnd, -1, simm9,	20612	GPR32Opnd, -1, simm9,
20613	/* LHE_MM */	20613	/* LHE_MM */
20614	GPR32Opnd, -1, simm9,	20614	GPR32Opnd, -1, simm9,
20615	/* LHU16_MM */	20615	/* LHU16_MM */
20616	GPRMM16Opnd, -1, simm4,	20616	GPRMM16Opnd, -1, simm4,
20617	/* LHX */	20617	/* LHX */
20618	GPR32Opnd, -1, -1,	20618	GPR32Opnd, -1, -1,
20619	/* LHX_MM */	20619	/* LHX_MM */
20620	GPR32Opnd, -1, -1,	20620	GPR32Opnd, -1, -1,
20621	/* LH_MM */	20621	/* LH_MM */
20622	GPR32Opnd, -1, simm16,	20622	GPR32Opnd, -1, simm16,
20623	/* LHu */	20623	/* LHu */
20624	GPR32Opnd, -1, simm16,	20624	GPR32Opnd, -1, simm16,
20625	/* LHu64 */	20625	/* LHu64 */
20626	GPR64Opnd, -1, simm16,	20626	GPR64Opnd, -1, simm16,
20627	/* LHuE */	20627	/* LHuE */
20628	GPR32Opnd, -1, simm9,	20628	GPR32Opnd, -1, simm9,
20629	/* LHuE_MM */	20629	/* LHuE_MM */
20630	GPR32Opnd, -1, simm9,	20630	GPR32Opnd, -1, simm9,
20631	/* LHu_MM */	20631	/* LHu_MM */
20632	GPR32Opnd, -1, simm16,	20632	GPR32Opnd, -1, simm16,
20633	/* LI16_MM */	20633	/* LI16_MM */
20634	GPRMM16Opnd, li16_imm,	20634	GPRMM16Opnd, li16_imm,
20635	/* LI16_MMR6 */	20635	/* LI16_MMR6 */
20636	GPRMM16Opnd, li16_imm,	20636	GPRMM16Opnd, li16_imm,
20637	/* LL */	20637	/* LL */
20638	GPR32Opnd, -1, simm16,	20638	GPR32Opnd, -1, simm16,
20639	/* LL64 */	20639	/* LL64 */
20640	GPR32Opnd, -1, simm16,	20640	GPR32Opnd, -1, simm16,
20641	/* LL64_R6 */	20641	/* LL64_R6 */
20642	GPR32Opnd, -1, simm9,	20642	GPR32Opnd, -1, simm9,
20643	/* LLD */	20643	/* LLD */
20644	GPR64Opnd, -1, simm16,	20644	GPR64Opnd, -1, simm16,
20645	/* LLD_R6 */	20645	/* LLD_R6 */
20646	GPR64Opnd, -1, simm9,	20646	GPR64Opnd, -1, simm9,
20647	/* LLE */	20647	/* LLE */
20648	GPR32Opnd, -1, simm9,	20648	GPR32Opnd, -1, simm9,
20649	/* LLE_MM */	20649	/* LLE_MM */
20650	GPR32Opnd, -1, simm9,	20650	GPR32Opnd, -1, simm9,
20651	/* LL_MM */	20651	/* LL_MM */
20652	GPR32Opnd, -1, simm12,	20652	GPR32Opnd, -1, simm12,
20653	/* LL_MMR6 */	20653	/* LL_MMR6 */
20654	GPR32Opnd, -1, simm9,	20654	GPR32Opnd, -1, simm9,
20655	/* LL_R6 */	20655	/* LL_R6 */
20656	GPR32Opnd, -1, simm9,	20656	GPR32Opnd, -1, simm9,
20657	/* LSA */	20657	/* LSA */
20658	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	20658	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20659	/* LSA_MMR6 */	20659	/* LSA_MMR6 */
20660	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	20660	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20661	/* LSA_R6 */	20661	/* LSA_R6 */
20662	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	20662	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20663	/* LUI_MMR6 */	20663	/* LUI_MMR6 */
20664	GPR32Opnd, uimm16,	20664	GPR32Opnd, uimm16,
20665	/* LUXC1 */	20665	/* LUXC1 */
20666	AFGR64Opnd, -1, -1,	20666	AFGR64Opnd, -1, -1,
20667	/* LUXC164 */	20667	/* LUXC164 */
20668	FGR64Opnd, -1, -1,	20668	FGR64Opnd, -1, -1,
20669	/* LUXC1_MM */	20669	/* LUXC1_MM */
20670	FGR64Opnd, -1, -1,	20670	FGR64Opnd, -1, -1,
20671	/* LUi */	20671	/* LUi */
20672	GPR32Opnd, uimm16_relaxed,	20672	GPR32Opnd, uimm16_relaxed,
20673	/* LUi64 */	20673	/* LUi64 */
20674	GPR64Opnd, uimm16_64_relaxed,	20674	GPR64Opnd, uimm16_64_relaxed,
20675	/* LUi_MM */	20675	/* LUi_MM */
20676	GPR32Opnd, uimm16_relaxed,	20676	GPR32Opnd, uimm16_relaxed,
20677	/* LW */	20677	/* LW */
20678	GPR32Opnd, -1, simm16,	20678	GPR32Opnd, -1, simm16,
20679	/* LW16_MM */	20679	/* LW16_MM */
20680	GPRMM16Opnd, -1, simm4,	20680	GPRMM16Opnd, -1, simm4,
20681	/* LW64 */	20681	/* LW64 */
20682	GPR64Opnd, -1, simm16,	20682	GPR64Opnd, -1, simm16,
20683	/* LWC1 */	20683	/* LWC1 */
20684	FGR32Opnd, -1, simm16,	20684	FGR32Opnd, -1, simm16,
20685	/* LWC1_MM */	20685	/* LWC1_MM */
20686	FGR32Opnd, -1, simm16,	20686	FGR32Opnd, -1, simm16,
20687	/* LWC2 */	20687	/* LWC2 */
20688	COP2Opnd, -1, simm16,	20688	COP2Opnd, -1, simm16,
20689	/* LWC2_MMR6 */	20689	/* LWC2_MMR6 */
20690	COP2Opnd, GPR32, simm11,	20690	COP2Opnd, GPR32, simm11,
20691	/* LWC2_R6 */	20691	/* LWC2_R6 */
20692	COP2Opnd, -1, simm11,	20692	COP2Opnd, -1, simm11,
20693	/* LWC3 */	20693	/* LWC3 */
20694	COP3Opnd, -1, simm16,	20694	COP3Opnd, -1, simm16,
20695	/* LWDSP */	20695	/* LWDSP */
20696	DSPROpnd, -1, simm16,	20696	DSPROpnd, -1, simm16,
20697	/* LWDSP_MM */	20697	/* LWDSP_MM */
20698	DSPROpnd, -1, simm16,	20698	DSPROpnd, -1, simm16,
20699	/* LWE */	20699	/* LWE */
20700	GPR32Opnd, -1, simm9,	20700	GPR32Opnd, -1, simm9,
20701	/* LWE_MM */	20701	/* LWE_MM */
20702	GPR32Opnd, -1, simm9,	20702	GPR32Opnd, -1, simm9,
20703	/* LWGP_MM */	20703	/* LWGP_MM */
20704	GPRMM16Opnd, -1, simm7_lsl2,	20704	GPRMM16Opnd, -1, simm7_lsl2,
20705	/* LWL */	20705	/* LWL */
20706	GPR32Opnd, -1, simm16, GPR32Opnd,	20706	GPR32Opnd, -1, simm16, GPR32Opnd,
20707	/* LWL64 */	20707	/* LWL64 */
20708	GPR64Opnd, -1, simm16, GPR64Opnd,	20708	GPR64Opnd, -1, simm16, GPR64Opnd,
20709	/* LWLE */	20709	/* LWLE */
20710	GPR32Opnd, -1, simm9, GPR32Opnd,	20710	GPR32Opnd, -1, simm9, GPR32Opnd,
20711	/* LWLE_MM */	20711	/* LWLE_MM */
20712	GPR32Opnd, -1, simm9, GPR32Opnd,	20712	GPR32Opnd, -1, simm9, GPR32Opnd,
20713	/* LWL_MM */	20713	/* LWL_MM */
20714	GPR32Opnd, -1, simm12, GPR32Opnd,	20714	GPR32Opnd, -1, simm12, GPR32Opnd,
20715	/* LWM16_MM */	20715	/* LWM16_MM */
20716	reglist16, -1, uimm8,	20716	reglist16, -1, uimm8,
20717	/* LWM16_MMR6 */	20717	/* LWM16_MMR6 */
20718	reglist16, -1, uimm8,	20718	reglist16, -1, uimm8,
20719	/* LWM32_MM */	20719	/* LWM32_MM */
20720	reglist, -1, simm12,	20720	reglist, -1, simm12,
20721	/* LWPC */	20721	/* LWPC */
20722	GPR32Opnd, simm19_lsl2,	20722	GPR32Opnd, simm19_lsl2,
20723	/* LWPC_MMR6 */	20723	/* LWPC_MMR6 */
20724	GPR32Opnd, simm19_lsl2,	20724	GPR32Opnd, simm19_lsl2,
20725	/* LWP_MM */	20725	/* LWP_MM */
20726	GPR32Opnd, GPR32Opnd, -1, simm12,	20726	GPR32Opnd, GPR32Opnd, -1, simm12,
20727	/* LWR */	20727	/* LWR */
20728	GPR32Opnd, -1, simm16, GPR32Opnd,	20728	GPR32Opnd, -1, simm16, GPR32Opnd,
20729	/* LWR64 */	20729	/* LWR64 */
20730	GPR64Opnd, -1, simm16, GPR64Opnd,	20730	GPR64Opnd, -1, simm16, GPR64Opnd,
20731	/* LWRE */	20731	/* LWRE */
20732	GPR32Opnd, -1, simm9, GPR32Opnd,	20732	GPR32Opnd, -1, simm9, GPR32Opnd,
20733	/* LWRE_MM */	20733	/* LWRE_MM */
20734	GPR32Opnd, -1, simm9, GPR32Opnd,	20734	GPR32Opnd, -1, simm9, GPR32Opnd,
20735	/* LWR_MM */	20735	/* LWR_MM */
20736	GPR32Opnd, -1, simm12, GPR32Opnd,	20736	GPR32Opnd, -1, simm12, GPR32Opnd,
20737	/* LWSP_MM */	20737	/* LWSP_MM */
20738	GPR32Opnd, -1, simm5,	20738	GPR32Opnd, -1, simm5,
20739	/* LWUPC */	20739	/* LWUPC */
20740	GPR32Opnd, simm19_lsl2,	20740	GPR32Opnd, simm19_lsl2,
20741	/* LWU_MM */	20741	/* LWU_MM */
20742	GPR32Opnd, -1, simm12,	20742	GPR32Opnd, -1, simm12,
20743	/* LWX */	20743	/* LWX */
20744	GPR32Opnd, -1, -1,	20744	GPR32Opnd, -1, -1,
20745	/* LWXC1 */	20745	/* LWXC1 */
20746	FGR32Opnd, -1, -1,	20746	FGR32Opnd, -1, -1,
20747	/* LWXC1_MM */	20747	/* LWXC1_MM */
20748	FGR32Opnd, -1, -1,	20748	FGR32Opnd, -1, -1,
20749	/* LWXS_MM */	20749	/* LWXS_MM */
20750	GPR32Opnd, -1, -1,	20750	GPR32Opnd, -1, -1,
20751	/* LWX_MM */	20751	/* LWX_MM */
20752	GPR32Opnd, -1, -1,	20752	GPR32Opnd, -1, -1,
20753	/* LW_MM */	20753	/* LW_MM */
20754	GPR32Opnd, -1, simm16,	20754	GPR32Opnd, -1, simm16,
20755	/* LW_MMR6 */	20755	/* LW_MMR6 */
20756	GPR32Opnd, -1, simm16,	20756	GPR32Opnd, -1, simm16,
20757	/* LWu */	20757	/* LWu */
20758	GPR64Opnd, -1, simm16,	20758	GPR64Opnd, -1, simm16,
20759	/* LbRxRyOffMemX16 */	20759	/* LbRxRyOffMemX16 */
20760	CPU16Regs, CPU16Regs, simm16,	20760	CPU16Regs, CPU16Regs, simm16,
20761	/* LbuRxRyOffMemX16 */	20761	/* LbuRxRyOffMemX16 */
20762	CPU16Regs, CPU16Regs, simm16,	20762	CPU16Regs, CPU16Regs, simm16,
20763	/* LhRxRyOffMemX16 */	20763	/* LhRxRyOffMemX16 */
20764	CPU16Regs, CPU16Regs, simm16,	20764	CPU16Regs, CPU16Regs, simm16,
20765	/* LhuRxRyOffMemX16 */	20765	/* LhuRxRyOffMemX16 */
20766	CPU16Regs, CPU16Regs, simm16,	20766	CPU16Regs, CPU16Regs, simm16,
20767	/* LiRxImm16 */	20767	/* LiRxImm16 */
20768	CPU16Regs, simm16,	20768	CPU16Regs, simm16,
20769	/* LiRxImmAlignX16 */	20769	/* LiRxImmAlignX16 */
20770	CPU16Regs, simm16,	20770	CPU16Regs, simm16,
20771	/* LiRxImmX16 */	20771	/* LiRxImmX16 */
20772	CPU16Regs, simm16,	20772	CPU16Regs, simm16,
20773	/* LwRxPcTcp16 */	20773	/* LwRxPcTcp16 */
20774	CPU16Regs, pcrel16, i32imm,	20774	CPU16Regs, pcrel16, i32imm,
20775	/* LwRxPcTcpX16 */	20775	/* LwRxPcTcpX16 */
20776	CPU16Regs, pcrel16, i32imm,	20776	CPU16Regs, pcrel16, i32imm,
20777	/* LwRxRyOffMemX16 */	20777	/* LwRxRyOffMemX16 */
20778	CPU16Regs, CPU16Regs, simm16,	20778	CPU16Regs, CPU16Regs, simm16,
20779	/* LwRxSpImmX16 */	20779	/* LwRxSpImmX16 */
20780	CPU16Regs, CPU16RegsPlusSP, simm16,	20780	CPU16Regs, CPU16RegsPlusSP, simm16,
20781	/* MADD */	20781	/* MADD */
20782	GPR32Opnd, GPR32Opnd,	20782	GPR32Opnd, GPR32Opnd,
20783	/* MADDF_D */	20783	/* MADDF_D */
20784	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	20784	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
20785	/* MADDF_D_MMR6 */	20785	/* MADDF_D_MMR6 */
20786	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	20786	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
20787	/* MADDF_S */	20787	/* MADDF_S */
20788	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	20788	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
20789	/* MADDF_S_MMR6 */	20789	/* MADDF_S_MMR6 */
20790	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	20790	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
20791	/* MADDR_Q_H */	20791	/* MADDR_Q_H */
20792	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20792	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20793	/* MADDR_Q_W */	20793	/* MADDR_Q_W */
20794	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20794	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20795	/* MADDU */	20795	/* MADDU */
20796	GPR32Opnd, GPR32Opnd,	20796	GPR32Opnd, GPR32Opnd,
20797	/* MADDU_DSP */	20797	/* MADDU_DSP */
20798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20799	/* MADDU_DSP_MM */	20799	/* MADDU_DSP_MM */
20800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20801	/* MADDU_MM */	20801	/* MADDU_MM */
20802	GPR32Opnd, GPR32Opnd,	20802	GPR32Opnd, GPR32Opnd,
20803	/* MADDV_B */	20803	/* MADDV_B */
20804	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20804	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20805	/* MADDV_D */	20805	/* MADDV_D */
20806	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20806	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20807	/* MADDV_H */	20807	/* MADDV_H */
20808	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20808	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20809	/* MADDV_W */	20809	/* MADDV_W */
20810	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20810	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20811	/* MADD_D32 */	20811	/* MADD_D32 */
20812	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20812	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20813	/* MADD_D32_MM */	20813	/* MADD_D32_MM */
20814	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	20814	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20815	/* MADD_D64 */	20815	/* MADD_D64 */
20816	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	20816	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
20817	/* MADD_DSP */	20817	/* MADD_DSP */
20818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20819	/* MADD_DSP_MM */	20819	/* MADD_DSP_MM */
20820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20821	/* MADD_MM */	20821	/* MADD_MM */
20822	GPR32Opnd, GPR32Opnd,	20822	GPR32Opnd, GPR32Opnd,
20823	/* MADD_Q_H */	20823	/* MADD_Q_H */
20824	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20824	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20825	/* MADD_Q_W */	20825	/* MADD_Q_W */
20826	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20826	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20827	/* MADD_S */	20827	/* MADD_S */
20828	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	20828	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
20829	/* MADD_S_MM */	20829	/* MADD_S_MM */
20830	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	20830	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
20831	/* MAQ_SA_W_PHL */	20831	/* MAQ_SA_W_PHL */
20832	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20832	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20833	/* MAQ_SA_W_PHL_MM */	20833	/* MAQ_SA_W_PHL_MM */
20834	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20834	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20835	/* MAQ_SA_W_PHR */	20835	/* MAQ_SA_W_PHR */
20836	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20836	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20837	/* MAQ_SA_W_PHR_MM */	20837	/* MAQ_SA_W_PHR_MM */
20838	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20838	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20839	/* MAQ_S_W_PHL */	20839	/* MAQ_S_W_PHL */
20840	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20840	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20841	/* MAQ_S_W_PHL_MM */	20841	/* MAQ_S_W_PHL_MM */
20842	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20842	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20843	/* MAQ_S_W_PHR */	20843	/* MAQ_S_W_PHR */
20844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20845	/* MAQ_S_W_PHR_MM */	20845	/* MAQ_S_W_PHR_MM */
20846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	20846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20847	/* MAXA_D */	20847	/* MAXA_D */
20848	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20848	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20849	/* MAXA_D_MMR6 */	20849	/* MAXA_D_MMR6 */
20850	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20850	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20851	/* MAXA_S */	20851	/* MAXA_S */
20852	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20852	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20853	/* MAXA_S_MMR6 */	20853	/* MAXA_S_MMR6 */
20854	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20854	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20855	/* MAXI_S_B */	20855	/* MAXI_S_B */
20856	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	20856	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
20857	/* MAXI_S_D */	20857	/* MAXI_S_D */
20858	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	20858	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
20859	/* MAXI_S_H */	20859	/* MAXI_S_H */
20860	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	20860	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
20861	/* MAXI_S_W */	20861	/* MAXI_S_W */
20862	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	20862	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
20863	/* MAXI_U_B */	20863	/* MAXI_U_B */
20864	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	20864	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
20865	/* MAXI_U_D */	20865	/* MAXI_U_D */
20866	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	20866	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
20867	/* MAXI_U_H */	20867	/* MAXI_U_H */
20868	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	20868	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
20869	/* MAXI_U_W */	20869	/* MAXI_U_W */
20870	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	20870	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
20871	/* MAX_A_B */	20871	/* MAX_A_B */
20872	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20872	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20873	/* MAX_A_D */	20873	/* MAX_A_D */
20874	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20874	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20875	/* MAX_A_H */	20875	/* MAX_A_H */
20876	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20876	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20877	/* MAX_A_W */	20877	/* MAX_A_W */
20878	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20878	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20879	/* MAX_D */	20879	/* MAX_D */
20880	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20880	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20881	/* MAX_D_MMR6 */	20881	/* MAX_D_MMR6 */
20882	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20882	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20883	/* MAX_S */	20883	/* MAX_S */
20884	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20884	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20885	/* MAX_S_B */	20885	/* MAX_S_B */
20886	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20886	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20887	/* MAX_S_D */	20887	/* MAX_S_D */
20888	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20888	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20889	/* MAX_S_H */	20889	/* MAX_S_H */
20890	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20890	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20891	/* MAX_S_MMR6 */	20891	/* MAX_S_MMR6 */
20892	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20892	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20893	/* MAX_S_W */	20893	/* MAX_S_W */
20894	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20894	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20895	/* MAX_U_B */	20895	/* MAX_U_B */
20896	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20896	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20897	/* MAX_U_D */	20897	/* MAX_U_D */
20898	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20898	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20899	/* MAX_U_H */	20899	/* MAX_U_H */
20900	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20900	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20901	/* MAX_U_W */	20901	/* MAX_U_W */
20902	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20902	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20903	/* MFC0 */	20903	/* MFC0 */
20904	GPR32Opnd, COP0Opnd, uimm3,	20904	GPR32Opnd, COP0Opnd, uimm3,
20905	/* MFC0_MMR6 */	20905	/* MFC0_MMR6 */
20906	GPR32Opnd, COP0Opnd, uimm3,	20906	GPR32Opnd, COP0Opnd, uimm3,
20907	/* MFC1 */	20907	/* MFC1 */
20908	GPR32Opnd, FGR32Opnd,	20908	GPR32Opnd, FGR32Opnd,
20909	/* MFC1_D64 */	20909	/* MFC1_D64 */
20910	GPR32Opnd, FGR64Opnd,	20910	GPR32Opnd, FGR64Opnd,
20911	/* MFC1_MM */	20911	/* MFC1_MM */
20912	GPR32Opnd, FGR32Opnd,	20912	GPR32Opnd, FGR32Opnd,
20913	/* MFC1_MMR6 */	20913	/* MFC1_MMR6 */
20914	GPR32Opnd, FGR32Opnd,	20914	GPR32Opnd, FGR32Opnd,
20915	/* MFC2 */	20915	/* MFC2 */
20916	GPR32Opnd, COP2Opnd, uimm3,	20916	GPR32Opnd, COP2Opnd, uimm3,
20917	/* MFC2_MMR6 */	20917	/* MFC2_MMR6 */
20918	GPR32Opnd, COP2Opnd,	20918	GPR32Opnd, COP2Opnd,
20919	/* MFGC0 */	20919	/* MFGC0 */
20920	GPR32Opnd, COP0Opnd, uimm3,	20920	GPR32Opnd, COP0Opnd, uimm3,
20921	/* MFGC0_MM */	20921	/* MFGC0_MM */
20922	GPR32Opnd, COP0Opnd, uimm3,	20922	GPR32Opnd, COP0Opnd, uimm3,
20923	/* MFHC0_MMR6 */	20923	/* MFHC0_MMR6 */
20924	GPR32Opnd, COP0Opnd, uimm3,	20924	GPR32Opnd, COP0Opnd, uimm3,
20925	/* MFHC1_D32 */	20925	/* MFHC1_D32 */
20926	GPR32Opnd, AFGR64Opnd,	20926	GPR32Opnd, AFGR64Opnd,
20927	/* MFHC1_D32_MM */	20927	/* MFHC1_D32_MM */
20928	GPR32Opnd, AFGR64Opnd,	20928	GPR32Opnd, AFGR64Opnd,
20929	/* MFHC1_D64 */	20929	/* MFHC1_D64 */
20930	GPR32Opnd, FGR64Opnd,	20930	GPR32Opnd, FGR64Opnd,
20931	/* MFHC1_D64_MM */	20931	/* MFHC1_D64_MM */
20932	GPR32Opnd, FGR64Opnd,	20932	GPR32Opnd, FGR64Opnd,
20933	/* MFHC2_MMR6 */	20933	/* MFHC2_MMR6 */
20934	GPR32Opnd, COP2Opnd,	20934	GPR32Opnd, COP2Opnd,
20935	/* MFHGC0 */	20935	/* MFHGC0 */
20936	GPR32Opnd, COP0Opnd, uimm3,	20936	GPR32Opnd, COP0Opnd, uimm3,
20937	/* MFHGC0_MM */	20937	/* MFHGC0_MM */
20938	GPR32Opnd, COP0Opnd, uimm3,	20938	GPR32Opnd, COP0Opnd, uimm3,
20939	/* MFHI */	20939	/* MFHI */
20940	GPR32Opnd,	20940	GPR32Opnd,
20941	/* MFHI16_MM */	20941	/* MFHI16_MM */
20942	GPR32Opnd,	20942	GPR32Opnd,
20943	/* MFHI64 */	20943	/* MFHI64 */
20944	GPR64Opnd,	20944	GPR64Opnd,
20945	/* MFHI_DSP */	20945	/* MFHI_DSP */
20946	GPR32Opnd, ACC64DSPOpnd,	20946	GPR32Opnd, ACC64DSPOpnd,
20947	/* MFHI_DSP_MM */	20947	/* MFHI_DSP_MM */
20948	GPR32Opnd, ACC64DSPOpnd,	20948	GPR32Opnd, ACC64DSPOpnd,
20949	/* MFHI_MM */	20949	/* MFHI_MM */
20950	GPR32Opnd,	20950	GPR32Opnd,
20951	/* MFLO */	20951	/* MFLO */
20952	GPR32Opnd,	20952	GPR32Opnd,
20953	/* MFLO16_MM */	20953	/* MFLO16_MM */
20954	GPR32Opnd,	20954	GPR32Opnd,
20955	/* MFLO64 */	20955	/* MFLO64 */
20956	GPR64Opnd,	20956	GPR64Opnd,
20957	/* MFLO_DSP */	20957	/* MFLO_DSP */
20958	GPR32Opnd, ACC64DSPOpnd,	20958	GPR32Opnd, ACC64DSPOpnd,
20959	/* MFLO_DSP_MM */	20959	/* MFLO_DSP_MM */
20960	GPR32Opnd, ACC64DSPOpnd,	20960	GPR32Opnd, ACC64DSPOpnd,
20961	/* MFLO_MM */	20961	/* MFLO_MM */
20962	GPR32Opnd,	20962	GPR32Opnd,
20963	/* MFTR */	20963	/* MFTR */
20964	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	20964	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,
20965	/* MINA_D */	20965	/* MINA_D */
20966	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20966	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20967	/* MINA_D_MMR6 */	20967	/* MINA_D_MMR6 */
20968	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20968	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20969	/* MINA_S */	20969	/* MINA_S */
20970	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20970	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20971	/* MINA_S_MMR6 */	20971	/* MINA_S_MMR6 */
20972	FGR32Opnd, FGR32Opnd, FGR32Opnd,	20972	FGR32Opnd, FGR32Opnd, FGR32Opnd,
20973	/* MINI_S_B */	20973	/* MINI_S_B */
20974	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	20974	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
20975	/* MINI_S_D */	20975	/* MINI_S_D */
20976	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	20976	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
20977	/* MINI_S_H */	20977	/* MINI_S_H */
20978	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	20978	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
20979	/* MINI_S_W */	20979	/* MINI_S_W */
20980	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	20980	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
20981	/* MINI_U_B */	20981	/* MINI_U_B */
20982	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	20982	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
20983	/* MINI_U_D */	20983	/* MINI_U_D */
20984	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	20984	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
20985	/* MINI_U_H */	20985	/* MINI_U_H */
20986	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	20986	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
20987	/* MINI_U_W */	20987	/* MINI_U_W */
20988	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	20988	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
20989	/* MIN_A_B */	20989	/* MIN_A_B */
20990	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	20990	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20991	/* MIN_A_D */	20991	/* MIN_A_D */
20992	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	20992	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20993	/* MIN_A_H */	20993	/* MIN_A_H */
20994	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	20994	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20995	/* MIN_A_W */	20995	/* MIN_A_W */
20996	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	20996	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20997	/* MIN_D */	20997	/* MIN_D */
20998	FGR64Opnd, FGR64Opnd, FGR64Opnd,	20998	FGR64Opnd, FGR64Opnd, FGR64Opnd,
20999	/* MIN_D_MMR6 */	20999	/* MIN_D_MMR6 */
21000	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21000	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21001	/* MIN_S */	21001	/* MIN_S */
21002	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21002	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21003	/* MIN_S_B */	21003	/* MIN_S_B */
21004	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21004	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21005	/* MIN_S_D */	21005	/* MIN_S_D */
21006	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21006	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21007	/* MIN_S_H */	21007	/* MIN_S_H */
21008	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21008	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21009	/* MIN_S_MMR6 */	21009	/* MIN_S_MMR6 */
21010	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21010	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21011	/* MIN_S_W */	21011	/* MIN_S_W */
21012	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21012	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21013	/* MIN_U_B */	21013	/* MIN_U_B */
21014	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21014	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21015	/* MIN_U_D */	21015	/* MIN_U_D */
21016	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21016	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21017	/* MIN_U_H */	21017	/* MIN_U_H */
21018	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21018	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21019	/* MIN_U_W */	21019	/* MIN_U_W */
21020	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21020	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21021	/* MOD */	21021	/* MOD */
21022	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21022	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21023	/* MODSUB */	21023	/* MODSUB */
21024	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21024	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21025	/* MODSUB_MM */	21025	/* MODSUB_MM */
21026	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21026	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21027	/* MODU */	21027	/* MODU */
21028	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21028	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21029	/* MODU_MMR6 */	21029	/* MODU_MMR6 */
21030	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21030	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21031	/* MOD_MMR6 */	21031	/* MOD_MMR6 */
21032	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21032	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21033	/* MOD_S_B */	21033	/* MOD_S_B */
21034	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21034	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21035	/* MOD_S_D */	21035	/* MOD_S_D */
21036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21037	/* MOD_S_H */	21037	/* MOD_S_H */
21038	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21038	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21039	/* MOD_S_W */	21039	/* MOD_S_W */
21040	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21040	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21041	/* MOD_U_B */	21041	/* MOD_U_B */
21042	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21042	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21043	/* MOD_U_D */	21043	/* MOD_U_D */
21044	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21044	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21045	/* MOD_U_H */	21045	/* MOD_U_H */
21046	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21046	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21047	/* MOD_U_W */	21047	/* MOD_U_W */
21048	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21048	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21049	/* MOVE16_MM */	21049	/* MOVE16_MM */
21050	GPR32Opnd, GPR32Opnd,	21050	GPR32Opnd, GPR32Opnd,
21051	/* MOVE16_MMR6 */	21051	/* MOVE16_MMR6 */
21052	GPR32Opnd, GPR32Opnd,	21052	GPR32Opnd, GPR32Opnd,
21053	/* MOVEP_MM */	21053	/* MOVEP_MM */
21054	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	21054	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,
21055	/* MOVEP_MMR6 */	21055	/* MOVEP_MMR6 */
21056	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	21056	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,
21057	/* MOVE_V */	21057	/* MOVE_V */
21058	MSA128BOpnd, MSA128BOpnd,	21058	MSA128BOpnd, MSA128BOpnd,
21059	/* MOVF_D32 */	21059	/* MOVF_D32 */
21060	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	21060	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21061	/* MOVF_D32_MM */	21061	/* MOVF_D32_MM */
21062	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	21062	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21063	/* MOVF_D64 */	21063	/* MOVF_D64 */
21064	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	21064	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,
21065	/* MOVF_I */	21065	/* MOVF_I */
21066	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	21066	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21067	/* MOVF_I64 */	21067	/* MOVF_I64 */
21068	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	21068	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,
21069	/* MOVF_I_MM */	21069	/* MOVF_I_MM */
21070	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	21070	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21071	/* MOVF_S */	21071	/* MOVF_S */
21072	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	21072	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21073	/* MOVF_S_MM */	21073	/* MOVF_S_MM */
21074	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	21074	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21075	/* MOVN_I64_D64 */	21075	/* MOVN_I64_D64 */
21076	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	21076	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,
21077	/* MOVN_I64_I */	21077	/* MOVN_I64_I */
21078	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	21078	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,
21079	/* MOVN_I64_I64 */	21079	/* MOVN_I64_I64 */
21080	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	21080	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
21081	/* MOVN_I64_S */	21081	/* MOVN_I64_S */
21082	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	21082	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,
21083	/* MOVN_I_D32 */	21083	/* MOVN_I_D32 */
21084	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	21084	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21085	/* MOVN_I_D32_MM */	21085	/* MOVN_I_D32_MM */
21086	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	21086	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21087	/* MOVN_I_D64 */	21087	/* MOVN_I_D64 */
21088	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	21088	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,
21089	/* MOVN_I_I */	21089	/* MOVN_I_I */
21090	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	21090	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21091	/* MOVN_I_I64 */	21091	/* MOVN_I_I64 */
21092	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	21092	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,
21093	/* MOVN_I_MM */	21093	/* MOVN_I_MM */
21094	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	21094	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21095	/* MOVN_I_S */	21095	/* MOVN_I_S */
21096	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	21096	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21097	/* MOVN_I_S_MM */	21097	/* MOVN_I_S_MM */
21098	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	21098	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21099	/* MOVT_D32 */	21099	/* MOVT_D32 */
21100	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	21100	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21101	/* MOVT_D32_MM */	21101	/* MOVT_D32_MM */
21102	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	21102	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21103	/* MOVT_D64 */	21103	/* MOVT_D64 */
21104	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	21104	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,
21105	/* MOVT_I */	21105	/* MOVT_I */
21106	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	21106	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21107	/* MOVT_I64 */	21107	/* MOVT_I64 */
21108	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	21108	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,
21109	/* MOVT_I_MM */	21109	/* MOVT_I_MM */
21110	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	21110	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21111	/* MOVT_S */	21111	/* MOVT_S */
21112	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	21112	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21113	/* MOVT_S_MM */	21113	/* MOVT_S_MM */
21114	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	21114	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21115	/* MOVZ_I64_D64 */	21115	/* MOVZ_I64_D64 */
21116	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	21116	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,
21117	/* MOVZ_I64_I */	21117	/* MOVZ_I64_I */
21118	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	21118	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,
21119	/* MOVZ_I64_I64 */	21119	/* MOVZ_I64_I64 */
21120	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	21120	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
21121	/* MOVZ_I64_S */	21121	/* MOVZ_I64_S */
21122	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	21122	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,
21123	/* MOVZ_I_D32 */	21123	/* MOVZ_I_D32 */
21124	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	21124	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21125	/* MOVZ_I_D32_MM */	21125	/* MOVZ_I_D32_MM */
21126	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	21126	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21127	/* MOVZ_I_D64 */	21127	/* MOVZ_I_D64 */
21128	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	21128	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,
21129	/* MOVZ_I_I */	21129	/* MOVZ_I_I */
21130	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	21130	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21131	/* MOVZ_I_I64 */	21131	/* MOVZ_I_I64 */
21132	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	21132	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,
21133	/* MOVZ_I_MM */	21133	/* MOVZ_I_MM */
21134	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	21134	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21135	/* MOVZ_I_S */	21135	/* MOVZ_I_S */
21136	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	21136	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21137	/* MOVZ_I_S_MM */	21137	/* MOVZ_I_S_MM */
21138	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	21138	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21139	/* MSUB */	21139	/* MSUB */
21140	GPR32Opnd, GPR32Opnd,	21140	GPR32Opnd, GPR32Opnd,
21141	/* MSUBF_D */	21141	/* MSUBF_D */
21142	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21142	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21143	/* MSUBF_D_MMR6 */	21143	/* MSUBF_D_MMR6 */
21144	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21144	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21145	/* MSUBF_S */	21145	/* MSUBF_S */
21146	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21146	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21147	/* MSUBF_S_MMR6 */	21147	/* MSUBF_S_MMR6 */
21148	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21148	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21149	/* MSUBR_Q_H */	21149	/* MSUBR_Q_H */
21150	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21150	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21151	/* MSUBR_Q_W */	21151	/* MSUBR_Q_W */
21152	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21152	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21153	/* MSUBU */	21153	/* MSUBU */
21154	GPR32Opnd, GPR32Opnd,	21154	GPR32Opnd, GPR32Opnd,
21155	/* MSUBU_DSP */	21155	/* MSUBU_DSP */
21156	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21156	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21157	/* MSUBU_DSP_MM */	21157	/* MSUBU_DSP_MM */
21158	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21158	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21159	/* MSUBU_MM */	21159	/* MSUBU_MM */
21160	GPR32Opnd, GPR32Opnd,	21160	GPR32Opnd, GPR32Opnd,
21161	/* MSUBV_B */	21161	/* MSUBV_B */
21162	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21162	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21163	/* MSUBV_D */	21163	/* MSUBV_D */
21164	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21164	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21165	/* MSUBV_H */	21165	/* MSUBV_H */
21166	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21166	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21167	/* MSUBV_W */	21167	/* MSUBV_W */
21168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21169	/* MSUB_D32 */	21169	/* MSUB_D32 */
21170	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21170	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21171	/* MSUB_D32_MM */	21171	/* MSUB_D32_MM */
21172	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21172	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21173	/* MSUB_D64 */	21173	/* MSUB_D64 */
21174	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21174	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21175	/* MSUB_DSP */	21175	/* MSUB_DSP */
21176	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21176	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21177	/* MSUB_DSP_MM */	21177	/* MSUB_DSP_MM */
21178	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21178	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21179	/* MSUB_MM */	21179	/* MSUB_MM */
21180	GPR32Opnd, GPR32Opnd,	21180	GPR32Opnd, GPR32Opnd,
21181	/* MSUB_Q_H */	21181	/* MSUB_Q_H */
21182	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21182	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21183	/* MSUB_Q_W */	21183	/* MSUB_Q_W */
21184	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21184	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21185	/* MSUB_S */	21185	/* MSUB_S */
21186	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21186	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21187	/* MSUB_S_MM */	21187	/* MSUB_S_MM */
21188	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21188	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21189	/* MTC0 */	21189	/* MTC0 */
21190	COP0Opnd, GPR32Opnd, uimm3,	21190	COP0Opnd, GPR32Opnd, uimm3,
21191	/* MTC0_MMR6 */	21191	/* MTC0_MMR6 */
21192	COP0Opnd, GPR32Opnd, uimm3,	21192	COP0Opnd, GPR32Opnd, uimm3,
21193	/* MTC1 */	21193	/* MTC1 */
21194	FGR32Opnd, GPR32Opnd,	21194	FGR32Opnd, GPR32Opnd,
21195	/* MTC1_D64 */	21195	/* MTC1_D64 */
21196	FGR64Opnd, GPR32Opnd,	21196	FGR64Opnd, GPR32Opnd,
21197	/* MTC1_D64_MM */	21197	/* MTC1_D64_MM */
21198	FGR64Opnd, GPR32Opnd,	21198	FGR64Opnd, GPR32Opnd,
21199	/* MTC1_MM */	21199	/* MTC1_MM */
21200	FGR32Opnd, GPR32Opnd,	21200	FGR32Opnd, GPR32Opnd,
21201	/* MTC1_MMR6 */	21201	/* MTC1_MMR6 */
21202	FGR32Opnd, GPR32Opnd,	21202	FGR32Opnd, GPR32Opnd,
21203	/* MTC2 */	21203	/* MTC2 */
21204	COP2Opnd, GPR32Opnd, uimm3,	21204	COP2Opnd, GPR32Opnd, uimm3,
21205	/* MTC2_MMR6 */	21205	/* MTC2_MMR6 */
21206	COP2Opnd, GPR32Opnd,	21206	COP2Opnd, GPR32Opnd,
21207	/* MTGC0 */	21207	/* MTGC0 */
21208	COP0Opnd, GPR32Opnd, uimm3,	21208	COP0Opnd, GPR32Opnd, uimm3,
21209	/* MTGC0_MM */	21209	/* MTGC0_MM */
21210	COP0Opnd, GPR32Opnd, uimm3,	21210	COP0Opnd, GPR32Opnd, uimm3,
21211	/* MTHC0_MMR6 */	21211	/* MTHC0_MMR6 */
21212	COP0Opnd, GPR32Opnd, uimm3,	21212	COP0Opnd, GPR32Opnd, uimm3,
21213	/* MTHC1_D32 */	21213	/* MTHC1_D32 */
21214	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	21214	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,
21215	/* MTHC1_D32_MM */	21215	/* MTHC1_D32_MM */
21216	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	21216	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,
21217	/* MTHC1_D64 */	21217	/* MTHC1_D64 */
21218	FGR64Opnd, FGR64Opnd, GPR32Opnd,	21218	FGR64Opnd, FGR64Opnd, GPR32Opnd,
21219	/* MTHC1_D64_MM */	21219	/* MTHC1_D64_MM */
21220	FGR64Opnd, FGR64Opnd, GPR32Opnd,	21220	FGR64Opnd, FGR64Opnd, GPR32Opnd,
21221	/* MTHC2_MMR6 */	21221	/* MTHC2_MMR6 */
21222	COP2Opnd, GPR32Opnd,	21222	COP2Opnd, GPR32Opnd,
21223	/* MTHGC0 */	21223	/* MTHGC0 */
21224	COP0Opnd, GPR32Opnd, uimm3,	21224	COP0Opnd, GPR32Opnd, uimm3,
21225	/* MTHGC0_MM */	21225	/* MTHGC0_MM */
21226	COP0Opnd, GPR32Opnd, uimm3,	21226	COP0Opnd, GPR32Opnd, uimm3,
21227	/* MTHI */	21227	/* MTHI */
21228	GPR32Opnd,	21228	GPR32Opnd,
21229	/* MTHI64 */	21229	/* MTHI64 */
21230	GPR64Opnd,	21230	GPR64Opnd,
21231	/* MTHI_DSP */	21231	/* MTHI_DSP */
21232	HI32DSPOpnd, GPR32Opnd,	21232	HI32DSPOpnd, GPR32Opnd,
21233	/* MTHI_DSP_MM */	21233	/* MTHI_DSP_MM */
21234	HI32DSPOpnd, GPR32Opnd,	21234	HI32DSPOpnd, GPR32Opnd,
21235	/* MTHI_MM */	21235	/* MTHI_MM */
21236	GPR32Opnd,	21236	GPR32Opnd,
21237	/* MTHLIP */	21237	/* MTHLIP */
21238	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	21238	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21239	/* MTHLIP_MM */	21239	/* MTHLIP_MM */
21240	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	21240	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21241	/* MTLO */	21241	/* MTLO */
21242	GPR32Opnd,	21242	GPR32Opnd,
21243	/* MTLO64 */	21243	/* MTLO64 */
21244	GPR64Opnd,	21244	GPR64Opnd,
21245	/* MTLO_DSP */	21245	/* MTLO_DSP */
21246	LO32DSPOpnd, GPR32Opnd,	21246	LO32DSPOpnd, GPR32Opnd,
21247	/* MTLO_DSP_MM */	21247	/* MTLO_DSP_MM */
21248	LO32DSPOpnd, GPR32Opnd,	21248	LO32DSPOpnd, GPR32Opnd,
21249	/* MTLO_MM */	21249	/* MTLO_MM */
21250	GPR32Opnd,	21250	GPR32Opnd,
21251	/* MTM0 */	21251	/* MTM0 */
21252	GPR64Opnd,	21252	GPR64Opnd,
21253	/* MTM1 */	21253	/* MTM1 */
21254	GPR64Opnd,	21254	GPR64Opnd,
21255	/* MTM2 */	21255	/* MTM2 */
21256	GPR64Opnd,	21256	GPR64Opnd,
21257	/* MTP0 */	21257	/* MTP0 */
21258	GPR64Opnd,	21258	GPR64Opnd,
21259	/* MTP1 */	21259	/* MTP1 */
21260	GPR64Opnd,	21260	GPR64Opnd,
21261	/* MTP2 */	21261	/* MTP2 */
21262	GPR64Opnd,	21262	GPR64Opnd,
21263	/* MTTR */	21263	/* MTTR */
21264	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	21264	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,
21265	/* MUH */	21265	/* MUH */
21266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21266	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21267	/* MUHU */	21267	/* MUHU */
21268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21268	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21269	/* MUHU_MMR6 */	21269	/* MUHU_MMR6 */
21270	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21270	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21271	/* MUH_MMR6 */	21271	/* MUH_MMR6 */
21272	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21272	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21273	/* MUL */	21273	/* MUL */
21274	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21274	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21275	/* MULEQ_S_W_PHL */	21275	/* MULEQ_S_W_PHL */
21276	GPR32Opnd, DSPROpnd, DSPROpnd,	21276	GPR32Opnd, DSPROpnd, DSPROpnd,
21277	/* MULEQ_S_W_PHL_MM */	21277	/* MULEQ_S_W_PHL_MM */
21278	GPR32Opnd, DSPROpnd, DSPROpnd,	21278	GPR32Opnd, DSPROpnd, DSPROpnd,
21279	/* MULEQ_S_W_PHR */	21279	/* MULEQ_S_W_PHR */
21280	GPR32Opnd, DSPROpnd, DSPROpnd,	21280	GPR32Opnd, DSPROpnd, DSPROpnd,
21281	/* MULEQ_S_W_PHR_MM */	21281	/* MULEQ_S_W_PHR_MM */
21282	GPR32Opnd, DSPROpnd, DSPROpnd,	21282	GPR32Opnd, DSPROpnd, DSPROpnd,
21283	/* MULEU_S_PH_QBL */	21283	/* MULEU_S_PH_QBL */
21284	DSPROpnd, DSPROpnd, DSPROpnd,	21284	DSPROpnd, DSPROpnd, DSPROpnd,
21285	/* MULEU_S_PH_QBL_MM */	21285	/* MULEU_S_PH_QBL_MM */
21286	DSPROpnd, DSPROpnd, DSPROpnd,	21286	DSPROpnd, DSPROpnd, DSPROpnd,
21287	/* MULEU_S_PH_QBR */	21287	/* MULEU_S_PH_QBR */
21288	DSPROpnd, DSPROpnd, DSPROpnd,	21288	DSPROpnd, DSPROpnd, DSPROpnd,
21289	/* MULEU_S_PH_QBR_MM */	21289	/* MULEU_S_PH_QBR_MM */
21290	DSPROpnd, DSPROpnd, DSPROpnd,	21290	DSPROpnd, DSPROpnd, DSPROpnd,
21291	/* MULQ_RS_PH */	21291	/* MULQ_RS_PH */
21292	DSPROpnd, DSPROpnd, DSPROpnd,	21292	DSPROpnd, DSPROpnd, DSPROpnd,
21293	/* MULQ_RS_PH_MM */	21293	/* MULQ_RS_PH_MM */
21294	DSPROpnd, DSPROpnd, DSPROpnd,	21294	DSPROpnd, DSPROpnd, DSPROpnd,
21295	/* MULQ_RS_W */	21295	/* MULQ_RS_W */
21296	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21296	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21297	/* MULQ_RS_W_MMR2 */	21297	/* MULQ_RS_W_MMR2 */
21298	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21298	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21299	/* MULQ_S_PH */	21299	/* MULQ_S_PH */
21300	DSPROpnd, DSPROpnd, DSPROpnd,	21300	DSPROpnd, DSPROpnd, DSPROpnd,
21301	/* MULQ_S_PH_MMR2 */	21301	/* MULQ_S_PH_MMR2 */
21302	DSPROpnd, DSPROpnd, DSPROpnd,	21302	DSPROpnd, DSPROpnd, DSPROpnd,
21303	/* MULQ_S_W */	21303	/* MULQ_S_W */
21304	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21304	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21305	/* MULQ_S_W_MMR2 */	21305	/* MULQ_S_W_MMR2 */
21306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21306	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21307	/* MULR_PS64 */	21307	/* MULR_PS64 */
21308	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21308	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21309	/* MULR_Q_H */	21309	/* MULR_Q_H */
21310	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21310	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21311	/* MULR_Q_W */	21311	/* MULR_Q_W */
21312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21313	/* MULSAQ_S_W_PH */	21313	/* MULSAQ_S_W_PH */
21314	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21314	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21315	/* MULSAQ_S_W_PH_MM */	21315	/* MULSAQ_S_W_PH_MM */
21316	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21316	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21317	/* MULSA_W_PH */	21317	/* MULSA_W_PH */
21318	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21318	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21319	/* MULSA_W_PH_MMR2 */	21319	/* MULSA_W_PH_MMR2 */
21320	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	21320	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21321	/* MULT */	21321	/* MULT */
21322	GPR32Opnd, GPR32Opnd,	21322	GPR32Opnd, GPR32Opnd,
21323	/* MULTU_DSP */	21323	/* MULTU_DSP */
21324	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	21324	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21325	/* MULTU_DSP_MM */	21325	/* MULTU_DSP_MM */
21326	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	21326	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21327	/* MULT_DSP */	21327	/* MULT_DSP */
21328	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	21328	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21329	/* MULT_DSP_MM */	21329	/* MULT_DSP_MM */
21330	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	21330	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21331	/* MULT_MM */	21331	/* MULT_MM */
21332	GPR32Opnd, GPR32Opnd,	21332	GPR32Opnd, GPR32Opnd,
21333	/* MULTu */	21333	/* MULTu */
21334	GPR32Opnd, GPR32Opnd,	21334	GPR32Opnd, GPR32Opnd,
21335	/* MULTu_MM */	21335	/* MULTu_MM */
21336	GPR32Opnd, GPR32Opnd,	21336	GPR32Opnd, GPR32Opnd,
21337	/* MULU */	21337	/* MULU */
21338	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21338	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21339	/* MULU_MMR6 */	21339	/* MULU_MMR6 */
21340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21340	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21341	/* MULV_B */	21341	/* MULV_B */
21342	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21342	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21343	/* MULV_D */	21343	/* MULV_D */
21344	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21344	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21345	/* MULV_H */	21345	/* MULV_H */
21346	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21346	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21347	/* MULV_W */	21347	/* MULV_W */
21348	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21348	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21349	/* MUL_MM */	21349	/* MUL_MM */
21350	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21350	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21351	/* MUL_MMR6 */	21351	/* MUL_MMR6 */
21352	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21352	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21353	/* MUL_PH */	21353	/* MUL_PH */
21354	DSPROpnd, DSPROpnd, DSPROpnd,	21354	DSPROpnd, DSPROpnd, DSPROpnd,
21355	/* MUL_PH_MMR2 */	21355	/* MUL_PH_MMR2 */
21356	DSPROpnd, DSPROpnd, DSPROpnd,	21356	DSPROpnd, DSPROpnd, DSPROpnd,
21357	/* MUL_Q_H */	21357	/* MUL_Q_H */
21358	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21358	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21359	/* MUL_Q_W */	21359	/* MUL_Q_W */
21360	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21360	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21361	/* MUL_R6 */	21361	/* MUL_R6 */
21362	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21362	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21363	/* MUL_S_PH */	21363	/* MUL_S_PH */
21364	DSPROpnd, DSPROpnd, DSPROpnd,	21364	DSPROpnd, DSPROpnd, DSPROpnd,
21365	/* MUL_S_PH_MMR2 */	21365	/* MUL_S_PH_MMR2 */
21366	DSPROpnd, DSPROpnd, DSPROpnd,	21366	DSPROpnd, DSPROpnd, DSPROpnd,
21367	/* Mfhi16 */	21367	/* Mfhi16 */
21368	CPU16Regs,	21368	CPU16Regs,
21369	/* Mflo16 */	21369	/* Mflo16 */
21370	CPU16Regs,	21370	CPU16Regs,
21371	/* Move32R16 */	21371	/* Move32R16 */
21372	GPR32, CPU16Regs,	21372	GPR32, CPU16Regs,
21373	/* MoveR3216 */	21373	/* MoveR3216 */
21374	CPU16Regs, GPR32,	21374	CPU16Regs, GPR32,
21375	/* NLOC_B */	21375	/* NLOC_B */
21376	MSA128BOpnd, MSA128BOpnd,	21376	MSA128BOpnd, MSA128BOpnd,
21377	/* NLOC_D */	21377	/* NLOC_D */
21378	MSA128DOpnd, MSA128DOpnd,	21378	MSA128DOpnd, MSA128DOpnd,
21379	/* NLOC_H */	21379	/* NLOC_H */
21380	MSA128HOpnd, MSA128HOpnd,	21380	MSA128HOpnd, MSA128HOpnd,
21381	/* NLOC_W */	21381	/* NLOC_W */
21382	MSA128WOpnd, MSA128WOpnd,	21382	MSA128WOpnd, MSA128WOpnd,
21383	/* NLZC_B */	21383	/* NLZC_B */
21384	MSA128BOpnd, MSA128BOpnd,	21384	MSA128BOpnd, MSA128BOpnd,
21385	/* NLZC_D */	21385	/* NLZC_D */
21386	MSA128DOpnd, MSA128DOpnd,	21386	MSA128DOpnd, MSA128DOpnd,
21387	/* NLZC_H */	21387	/* NLZC_H */
21388	MSA128HOpnd, MSA128HOpnd,	21388	MSA128HOpnd, MSA128HOpnd,
21389	/* NLZC_W */	21389	/* NLZC_W */
21390	MSA128WOpnd, MSA128WOpnd,	21390	MSA128WOpnd, MSA128WOpnd,
21391	/* NMADD_D32 */	21391	/* NMADD_D32 */
21392	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21392	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21393	/* NMADD_D32_MM */	21393	/* NMADD_D32_MM */
21394	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21394	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21395	/* NMADD_D64 */	21395	/* NMADD_D64 */
21396	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21396	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21397	/* NMADD_S */	21397	/* NMADD_S */
21398	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21398	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21399	/* NMADD_S_MM */	21399	/* NMADD_S_MM */
21400	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21400	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21401	/* NMSUB_D32 */	21401	/* NMSUB_D32 */
21402	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21402	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21403	/* NMSUB_D32_MM */	21403	/* NMSUB_D32_MM */
21404	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	21404	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21405	/* NMSUB_D64 */	21405	/* NMSUB_D64 */
21406	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21406	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21407	/* NMSUB_S */	21407	/* NMSUB_S */
21408	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21408	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21409	/* NMSUB_S_MM */	21409	/* NMSUB_S_MM */
21410	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	21410	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21411	/* NOR */	21411	/* NOR */
21412	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21412	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21413	/* NOR64 */	21413	/* NOR64 */
21414	GPR64Opnd, GPR64Opnd, GPR64Opnd,	21414	GPR64Opnd, GPR64Opnd, GPR64Opnd,
21415	/* NORI_B */	21415	/* NORI_B */
21416	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	21416	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
21417	/* NOR_MM */	21417	/* NOR_MM */
21418	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21418	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21419	/* NOR_MMR6 */	21419	/* NOR_MMR6 */
21420	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21420	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21421	/* NOR_V */	21421	/* NOR_V */
21422	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21422	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21423	/* NOT16_MM */	21423	/* NOT16_MM */
21424	GPRMM16Opnd, GPRMM16Opnd,	21424	GPRMM16Opnd, GPRMM16Opnd,
21425	/* NOT16_MMR6 */	21425	/* NOT16_MMR6 */
21426	GPRMM16Opnd, GPRMM16Opnd,	21426	GPRMM16Opnd, GPRMM16Opnd,
21427	/* NegRxRy16 */	21427	/* NegRxRy16 */
21428	CPU16Regs, CPU16Regs,	21428	CPU16Regs, CPU16Regs,
21429	/* NotRxRy16 */	21429	/* NotRxRy16 */
21430	CPU16Regs, CPU16Regs,	21430	CPU16Regs, CPU16Regs,
21431	/* OR */	21431	/* OR */
21432	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21432	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21433	/* OR16_MM */	21433	/* OR16_MM */
21434	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	21434	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
21435	/* OR16_MMR6 */	21435	/* OR16_MMR6 */
21436	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	21436	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
21437	/* OR64 */	21437	/* OR64 */
21438	GPR64Opnd, GPR64Opnd, GPR64Opnd,	21438	GPR64Opnd, GPR64Opnd, GPR64Opnd,
21439	/* ORI_B */	21439	/* ORI_B */
21440	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	21440	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
21441	/* ORI_MMR6 */	21441	/* ORI_MMR6 */
21442	GPR32Opnd, GPR32Opnd, uimm16,	21442	GPR32Opnd, GPR32Opnd, uimm16,
21443	/* OR_MM */	21443	/* OR_MM */
21444	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21444	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21445	/* OR_MMR6 */	21445	/* OR_MMR6 */
21446	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21446	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21447	/* OR_V */	21447	/* OR_V */
21448	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21448	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21449	/* ORi */	21449	/* ORi */
21450	GPR32Opnd, GPR32Opnd, uimm16,	21450	GPR32Opnd, GPR32Opnd, uimm16,
21451	/* ORi64 */	21451	/* ORi64 */
21452	GPR64Opnd, GPR64Opnd, uimm16_64,	21452	GPR64Opnd, GPR64Opnd, uimm16_64,
21453	/* ORi_MM */	21453	/* ORi_MM */
21454	GPR32Opnd, GPR32Opnd, uimm16,	21454	GPR32Opnd, GPR32Opnd, uimm16,
21455	/* OrRxRxRy16 */	21455	/* OrRxRxRy16 */
21456	CPU16Regs, CPU16Regs, CPU16Regs,	21456	CPU16Regs, CPU16Regs, CPU16Regs,
21457	/* PACKRL_PH */	21457	/* PACKRL_PH */
21458	DSPROpnd, DSPROpnd, DSPROpnd,	21458	DSPROpnd, DSPROpnd, DSPROpnd,
21459	/* PACKRL_PH_MM */	21459	/* PACKRL_PH_MM */
21460	DSPROpnd, DSPROpnd, DSPROpnd,	21460	DSPROpnd, DSPROpnd, DSPROpnd,
21461	/* PAUSE */	21461	/* PAUSE */
21462	/* PAUSE_MM */	21462	/* PAUSE_MM */
21463	/* PAUSE_MMR6 */	21463	/* PAUSE_MMR6 */
21464	/* PCKEV_B */	21464	/* PCKEV_B */
21465	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21465	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21466	/* PCKEV_D */	21466	/* PCKEV_D */
21467	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21467	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21468	/* PCKEV_H */	21468	/* PCKEV_H */
21469	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21469	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21470	/* PCKEV_W */	21470	/* PCKEV_W */
21471	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21471	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21472	/* PCKOD_B */	21472	/* PCKOD_B */
21473	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	21473	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21474	/* PCKOD_D */	21474	/* PCKOD_D */
21475	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	21475	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21476	/* PCKOD_H */	21476	/* PCKOD_H */
21477	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	21477	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21478	/* PCKOD_W */	21478	/* PCKOD_W */
21479	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	21479	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21480	/* PCNT_B */	21480	/* PCNT_B */
21481	MSA128BOpnd, MSA128BOpnd,	21481	MSA128BOpnd, MSA128BOpnd,
21482	/* PCNT_D */	21482	/* PCNT_D */
21483	MSA128DOpnd, MSA128DOpnd,	21483	MSA128DOpnd, MSA128DOpnd,
21484	/* PCNT_H */	21484	/* PCNT_H */
21485	MSA128HOpnd, MSA128HOpnd,	21485	MSA128HOpnd, MSA128HOpnd,
21486	/* PCNT_W */	21486	/* PCNT_W */
21487	MSA128WOpnd, MSA128WOpnd,	21487	MSA128WOpnd, MSA128WOpnd,
21488	/* PICK_PH */	21488	/* PICK_PH */
21489	DSPROpnd, DSPROpnd, DSPROpnd,	21489	DSPROpnd, DSPROpnd, DSPROpnd,
21490	/* PICK_PH_MM */	21490	/* PICK_PH_MM */
21491	DSPROpnd, DSPROpnd, DSPROpnd,	21491	DSPROpnd, DSPROpnd, DSPROpnd,
21492	/* PICK_QB */	21492	/* PICK_QB */
21493	DSPROpnd, DSPROpnd, DSPROpnd,	21493	DSPROpnd, DSPROpnd, DSPROpnd,
21494	/* PICK_QB_MM */	21494	/* PICK_QB_MM */
21495	DSPROpnd, DSPROpnd, DSPROpnd,	21495	DSPROpnd, DSPROpnd, DSPROpnd,
21496	/* PLL_PS64 */	21496	/* PLL_PS64 */
21497	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21497	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21498	/* PLU_PS64 */	21498	/* PLU_PS64 */
21499	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21499	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21500	/* POP */	21500	/* POP */
21501	GPR32Opnd, GPR32Opnd,	21501	GPR32Opnd, GPR32Opnd,
21502	/* PRECEQU_PH_QBL */	21502	/* PRECEQU_PH_QBL */
21503	DSPROpnd, DSPROpnd,	21503	DSPROpnd, DSPROpnd,
21504	/* PRECEQU_PH_QBLA */	21504	/* PRECEQU_PH_QBLA */
21505	DSPROpnd, DSPROpnd,	21505	DSPROpnd, DSPROpnd,
21506	/* PRECEQU_PH_QBLA_MM */	21506	/* PRECEQU_PH_QBLA_MM */
21507	DSPROpnd, DSPROpnd,	21507	DSPROpnd, DSPROpnd,
21508	/* PRECEQU_PH_QBL_MM */	21508	/* PRECEQU_PH_QBL_MM */
21509	DSPROpnd, DSPROpnd,	21509	DSPROpnd, DSPROpnd,
21510	/* PRECEQU_PH_QBR */	21510	/* PRECEQU_PH_QBR */
21511	DSPROpnd, DSPROpnd,	21511	DSPROpnd, DSPROpnd,
21512	/* PRECEQU_PH_QBRA */	21512	/* PRECEQU_PH_QBRA */
21513	DSPROpnd, DSPROpnd,	21513	DSPROpnd, DSPROpnd,
21514	/* PRECEQU_PH_QBRA_MM */	21514	/* PRECEQU_PH_QBRA_MM */
21515	DSPROpnd, DSPROpnd,	21515	DSPROpnd, DSPROpnd,
21516	/* PRECEQU_PH_QBR_MM */	21516	/* PRECEQU_PH_QBR_MM */
21517	DSPROpnd, DSPROpnd,	21517	DSPROpnd, DSPROpnd,
21518	/* PRECEQ_W_PHL */	21518	/* PRECEQ_W_PHL */
21519	GPR32Opnd, DSPROpnd,	21519	GPR32Opnd, DSPROpnd,
21520	/* PRECEQ_W_PHL_MM */	21520	/* PRECEQ_W_PHL_MM */
21521	GPR32Opnd, DSPROpnd,	21521	GPR32Opnd, DSPROpnd,
21522	/* PRECEQ_W_PHR */	21522	/* PRECEQ_W_PHR */
21523	GPR32Opnd, DSPROpnd,	21523	GPR32Opnd, DSPROpnd,
21524	/* PRECEQ_W_PHR_MM */	21524	/* PRECEQ_W_PHR_MM */
21525	GPR32Opnd, DSPROpnd,	21525	GPR32Opnd, DSPROpnd,
21526	/* PRECEU_PH_QBL */	21526	/* PRECEU_PH_QBL */
21527	DSPROpnd, DSPROpnd,	21527	DSPROpnd, DSPROpnd,
21528	/* PRECEU_PH_QBLA */	21528	/* PRECEU_PH_QBLA */
21529	DSPROpnd, DSPROpnd,	21529	DSPROpnd, DSPROpnd,
21530	/* PRECEU_PH_QBLA_MM */	21530	/* PRECEU_PH_QBLA_MM */
21531	DSPROpnd, DSPROpnd,	21531	DSPROpnd, DSPROpnd,
21532	/* PRECEU_PH_QBL_MM */	21532	/* PRECEU_PH_QBL_MM */
21533	DSPROpnd, DSPROpnd,	21533	DSPROpnd, DSPROpnd,
21534	/* PRECEU_PH_QBR */	21534	/* PRECEU_PH_QBR */
21535	DSPROpnd, DSPROpnd,	21535	DSPROpnd, DSPROpnd,
21536	/* PRECEU_PH_QBRA */	21536	/* PRECEU_PH_QBRA */
21537	DSPROpnd, DSPROpnd,	21537	DSPROpnd, DSPROpnd,
21538	/* PRECEU_PH_QBRA_MM */	21538	/* PRECEU_PH_QBRA_MM */
21539	DSPROpnd, DSPROpnd,	21539	DSPROpnd, DSPROpnd,
21540	/* PRECEU_PH_QBR_MM */	21540	/* PRECEU_PH_QBR_MM */
21541	DSPROpnd, DSPROpnd,	21541	DSPROpnd, DSPROpnd,
21542	/* PRECRQU_S_QB_PH */	21542	/* PRECRQU_S_QB_PH */
21543	DSPROpnd, DSPROpnd, DSPROpnd,	21543	DSPROpnd, DSPROpnd, DSPROpnd,
21544	/* PRECRQU_S_QB_PH_MM */	21544	/* PRECRQU_S_QB_PH_MM */
21545	DSPROpnd, DSPROpnd, DSPROpnd,	21545	DSPROpnd, DSPROpnd, DSPROpnd,
21546	/* PRECRQ_PH_W */	21546	/* PRECRQ_PH_W */
21547	DSPROpnd, GPR32Opnd, GPR32Opnd,	21547	DSPROpnd, GPR32Opnd, GPR32Opnd,
21548	/* PRECRQ_PH_W_MM */	21548	/* PRECRQ_PH_W_MM */
21549	DSPROpnd, GPR32Opnd, GPR32Opnd,	21549	DSPROpnd, GPR32Opnd, GPR32Opnd,
21550	/* PRECRQ_QB_PH */	21550	/* PRECRQ_QB_PH */
21551	DSPROpnd, DSPROpnd, DSPROpnd,	21551	DSPROpnd, DSPROpnd, DSPROpnd,
21552	/* PRECRQ_QB_PH_MM */	21552	/* PRECRQ_QB_PH_MM */
21553	DSPROpnd, DSPROpnd, DSPROpnd,	21553	DSPROpnd, DSPROpnd, DSPROpnd,
21554	/* PRECRQ_RS_PH_W */	21554	/* PRECRQ_RS_PH_W */
21555	DSPROpnd, GPR32Opnd, GPR32Opnd,	21555	DSPROpnd, GPR32Opnd, GPR32Opnd,
21556	/* PRECRQ_RS_PH_W_MM */	21556	/* PRECRQ_RS_PH_W_MM */
21557	DSPROpnd, GPR32Opnd, GPR32Opnd,	21557	DSPROpnd, GPR32Opnd, GPR32Opnd,
21558	/* PRECR_QB_PH */	21558	/* PRECR_QB_PH */
21559	DSPROpnd, DSPROpnd, DSPROpnd,	21559	DSPROpnd, DSPROpnd, DSPROpnd,
21560	/* PRECR_QB_PH_MMR2 */	21560	/* PRECR_QB_PH_MMR2 */
21561	DSPROpnd, DSPROpnd, DSPROpnd,	21561	DSPROpnd, DSPROpnd, DSPROpnd,
21562	/* PRECR_SRA_PH_W */	21562	/* PRECR_SRA_PH_W */
21563	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	21563	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21564	/* PRECR_SRA_PH_W_MMR2 */	21564	/* PRECR_SRA_PH_W_MMR2 */
21565	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	21565	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21566	/* PRECR_SRA_R_PH_W */	21566	/* PRECR_SRA_R_PH_W */
21567	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	21567	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21568	/* PRECR_SRA_R_PH_W_MMR2 */	21568	/* PRECR_SRA_R_PH_W_MMR2 */
21569	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	21569	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21570	/* PREF */	21570	/* PREF */
21571	-1, simm16, uimm5,	21571	-1, simm16, uimm5,
21572	/* PREFE */	21572	/* PREFE */
21573	-1, simm9, uimm5,	21573	-1, simm9, uimm5,
21574	/* PREFE_MM */	21574	/* PREFE_MM */
21575	-1, simm9, uimm5,	21575	-1, simm9, uimm5,
21576	/* PREFX_MM */	21576	/* PREFX_MM */
21577	-1, -1, uimm5,	21577	-1, -1, uimm5,
21578	/* PREF_MM */	21578	/* PREF_MM */
21579	-1, simm12, uimm5,	21579	-1, simm12, uimm5,
21580	/* PREF_MMR6 */	21580	/* PREF_MMR6 */
21581	-1, simm12, uimm5,	21581	-1, simm12, uimm5,
21582	/* PREF_R6 */	21582	/* PREF_R6 */
21583	-1, simm9, uimm5,	21583	-1, simm9, uimm5,
21584	/* PREPEND */	21584	/* PREPEND */
21585	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	21585	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
21586	/* PREPEND_MMR2 */	21586	/* PREPEND_MMR2 */
21587	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	21587	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
21588	/* PUL_PS64 */	21588	/* PUL_PS64 */
21589	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21589	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21590	/* PUU_PS64 */	21590	/* PUU_PS64 */
21591	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21591	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21592	/* RADDU_W_QB */	21592	/* RADDU_W_QB */
21593	GPR32Opnd, DSPROpnd,	21593	GPR32Opnd, DSPROpnd,
21594	/* RADDU_W_QB_MM */	21594	/* RADDU_W_QB_MM */
21595	GPR32Opnd, DSPROpnd,	21595	GPR32Opnd, DSPROpnd,
21596	/* RDDSP */	21596	/* RDDSP */
21597	GPR32Opnd, uimm10,	21597	GPR32Opnd, uimm10,
21598	/* RDDSP_MM */	21598	/* RDDSP_MM */
21599	GPR32Opnd, uimm7,	21599	GPR32Opnd, uimm7,
21600	/* RDHWR */	21600	/* RDHWR */
21601	GPR32Opnd, HWRegsOpnd, uimm8,	21601	GPR32Opnd, HWRegsOpnd, uimm8,
21602	/* RDHWR64 */	21602	/* RDHWR64 */
21603	GPR64Opnd, HWRegsOpnd, uimm8,	21603	GPR64Opnd, HWRegsOpnd, uimm8,
21604	/* RDHWR_MM */	21604	/* RDHWR_MM */
21605	GPR32Opnd, HWRegsOpnd, uimm8,	21605	GPR32Opnd, HWRegsOpnd, uimm8,
21606	/* RDHWR_MMR6 */	21606	/* RDHWR_MMR6 */
21607	GPR32Opnd, HWRegsOpnd, uimm3,	21607	GPR32Opnd, HWRegsOpnd, uimm3,
21608	/* RDPGPR_MMR6 */	21608	/* RDPGPR_MMR6 */
21609	GPR32Opnd, GPR32Opnd,	21609	GPR32Opnd, GPR32Opnd,
21610	/* RECIP_D32 */	21610	/* RECIP_D32 */
21611	AFGR64Opnd, AFGR64Opnd,	21611	AFGR64Opnd, AFGR64Opnd,
21612	/* RECIP_D32_MM */	21612	/* RECIP_D32_MM */
21613	AFGR64Opnd, AFGR64Opnd,	21613	AFGR64Opnd, AFGR64Opnd,
21614	/* RECIP_D64 */	21614	/* RECIP_D64 */
21615	FGR64Opnd, FGR64Opnd,	21615	FGR64Opnd, FGR64Opnd,
21616	/* RECIP_D64_MM */	21616	/* RECIP_D64_MM */
21617	FGR64Opnd, FGR64Opnd,	21617	FGR64Opnd, FGR64Opnd,
21618	/* RECIP_S */	21618	/* RECIP_S */
21619	FGR32Opnd, FGR32Opnd,	21619	FGR32Opnd, FGR32Opnd,
21620	/* RECIP_S_MM */	21620	/* RECIP_S_MM */
21621	FGR32Opnd, FGR32Opnd,	21621	FGR32Opnd, FGR32Opnd,
21622	/* REPLV_PH */	21622	/* REPLV_PH */
21623	DSPROpnd, GPR32Opnd,	21623	DSPROpnd, GPR32Opnd,
21624	/* REPLV_PH_MM */	21624	/* REPLV_PH_MM */
21625	DSPROpnd, GPR32Opnd,	21625	DSPROpnd, GPR32Opnd,
21626	/* REPLV_QB */	21626	/* REPLV_QB */
21627	DSPROpnd, GPR32Opnd,	21627	DSPROpnd, GPR32Opnd,
21628	/* REPLV_QB_MM */	21628	/* REPLV_QB_MM */
21629	DSPROpnd, GPR32Opnd,	21629	DSPROpnd, GPR32Opnd,
21630	/* REPL_PH */	21630	/* REPL_PH */
21631	DSPROpnd, simm10,	21631	DSPROpnd, simm10,
21632	/* REPL_PH_MM */	21632	/* REPL_PH_MM */
21633	DSPROpnd, simm10,	21633	DSPROpnd, simm10,
21634	/* REPL_QB */	21634	/* REPL_QB */
21635	DSPROpnd, uimm8,	21635	DSPROpnd, uimm8,
21636	/* REPL_QB_MM */	21636	/* REPL_QB_MM */
21637	DSPROpnd, uimm8,	21637	DSPROpnd, uimm8,
21638	/* RINT_D */	21638	/* RINT_D */
21639	FGR64Opnd, FGR64Opnd,	21639	FGR64Opnd, FGR64Opnd,
21640	/* RINT_D_MMR6 */	21640	/* RINT_D_MMR6 */
21641	FGR64Opnd, FGR64Opnd,	21641	FGR64Opnd, FGR64Opnd,
21642	/* RINT_S */	21642	/* RINT_S */
21643	FGR32Opnd, FGR32Opnd,	21643	FGR32Opnd, FGR32Opnd,
21644	/* RINT_S_MMR6 */	21644	/* RINT_S_MMR6 */
21645	FGR32Opnd, FGR32Opnd,	21645	FGR32Opnd, FGR32Opnd,
21646	/* ROTR */	21646	/* ROTR */
21647	GPR32Opnd, GPR32Opnd, uimm5,	21647	GPR32Opnd, GPR32Opnd, uimm5,
21648	/* ROTRV */	21648	/* ROTRV */
21649	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21649	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21650	/* ROTRV_MM */	21650	/* ROTRV_MM */
21651	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21651	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21652	/* ROTR_MM */	21652	/* ROTR_MM */
21653	GPR32Opnd, GPR32Opnd, uimm5,	21653	GPR32Opnd, GPR32Opnd, uimm5,
21654	/* ROUND_L_D64 */	21654	/* ROUND_L_D64 */
21655	FGR64Opnd, FGR64Opnd,	21655	FGR64Opnd, FGR64Opnd,
21656	/* ROUND_L_D_MMR6 */	21656	/* ROUND_L_D_MMR6 */
21657	FGR64Opnd, FGR64Opnd,	21657	FGR64Opnd, FGR64Opnd,
21658	/* ROUND_L_S */	21658	/* ROUND_L_S */
21659	FGR64Opnd, FGR32Opnd,	21659	FGR64Opnd, FGR32Opnd,
21660	/* ROUND_L_S_MMR6 */	21660	/* ROUND_L_S_MMR6 */
21661	FGR64Opnd, FGR32Opnd,	21661	FGR64Opnd, FGR32Opnd,
21662	/* ROUND_W_D32 */	21662	/* ROUND_W_D32 */
21663	FGR32Opnd, AFGR64Opnd,	21663	FGR32Opnd, AFGR64Opnd,
21664	/* ROUND_W_D64 */	21664	/* ROUND_W_D64 */
21665	FGR32Opnd, FGR64Opnd,	21665	FGR32Opnd, FGR64Opnd,
21666	/* ROUND_W_D_MMR6 */	21666	/* ROUND_W_D_MMR6 */
21667	FGR64Opnd, FGR64Opnd,	21667	FGR64Opnd, FGR64Opnd,
21668	/* ROUND_W_MM */	21668	/* ROUND_W_MM */
21669	FGR32Opnd, AFGR64Opnd,	21669	FGR32Opnd, AFGR64Opnd,
21670	/* ROUND_W_S */	21670	/* ROUND_W_S */
21671	FGR32Opnd, FGR32Opnd,	21671	FGR32Opnd, FGR32Opnd,
21672	/* ROUND_W_S_MM */	21672	/* ROUND_W_S_MM */
21673	FGR32Opnd, FGR32Opnd,	21673	FGR32Opnd, FGR32Opnd,
21674	/* ROUND_W_S_MMR6 */	21674	/* ROUND_W_S_MMR6 */
21675	FGR32Opnd, FGR32Opnd,	21675	FGR32Opnd, FGR32Opnd,
21676	/* RSQRT_D32 */	21676	/* RSQRT_D32 */
21677	AFGR64Opnd, AFGR64Opnd,	21677	AFGR64Opnd, AFGR64Opnd,
21678	/* RSQRT_D32_MM */	21678	/* RSQRT_D32_MM */
21679	AFGR64Opnd, AFGR64Opnd,	21679	AFGR64Opnd, AFGR64Opnd,
21680	/* RSQRT_D64 */	21680	/* RSQRT_D64 */
21681	FGR64Opnd, FGR64Opnd,	21681	FGR64Opnd, FGR64Opnd,
21682	/* RSQRT_D64_MM */	21682	/* RSQRT_D64_MM */
21683	FGR64Opnd, FGR64Opnd,	21683	FGR64Opnd, FGR64Opnd,
21684	/* RSQRT_S */	21684	/* RSQRT_S */
21685	FGR32Opnd, FGR32Opnd,	21685	FGR32Opnd, FGR32Opnd,
21686	/* RSQRT_S_MM */	21686	/* RSQRT_S_MM */
21687	FGR32Opnd, FGR32Opnd,	21687	FGR32Opnd, FGR32Opnd,
21688	/* Restore16 */	21688	/* Restore16 */
21689	/* RestoreX16 */	21689	/* RestoreX16 */
21690	/* SAA */	21690	/* SAA */
21691	GPR64Opnd, GPR64Opnd,	21691	GPR64Opnd, GPR64Opnd,
21692	/* SAAD */	21692	/* SAAD */
21693	GPR64Opnd, GPR64Opnd,	21693	GPR64Opnd, GPR64Opnd,
21694	/* SAT_S_B */	21694	/* SAT_S_B */
21695	MSA128BOpnd, MSA128BOpnd, uimm3,	21695	MSA128BOpnd, MSA128BOpnd, uimm3,
21696	/* SAT_S_D */	21696	/* SAT_S_D */
21697	MSA128DOpnd, MSA128DOpnd, uimm6,	21697	MSA128DOpnd, MSA128DOpnd, uimm6,
21698	/* SAT_S_H */	21698	/* SAT_S_H */
21699	MSA128HOpnd, MSA128HOpnd, uimm4,	21699	MSA128HOpnd, MSA128HOpnd, uimm4,
21700	/* SAT_S_W */	21700	/* SAT_S_W */
21701	MSA128WOpnd, MSA128WOpnd, uimm5,	21701	MSA128WOpnd, MSA128WOpnd, uimm5,
21702	/* SAT_U_B */	21702	/* SAT_U_B */
21703	MSA128BOpnd, MSA128BOpnd, uimm3,	21703	MSA128BOpnd, MSA128BOpnd, uimm3,
21704	/* SAT_U_D */	21704	/* SAT_U_D */
21705	MSA128DOpnd, MSA128DOpnd, uimm6,	21705	MSA128DOpnd, MSA128DOpnd, uimm6,
21706	/* SAT_U_H */	21706	/* SAT_U_H */
21707	MSA128HOpnd, MSA128HOpnd, uimm4,	21707	MSA128HOpnd, MSA128HOpnd, uimm4,
21708	/* SAT_U_W */	21708	/* SAT_U_W */
21709	MSA128WOpnd, MSA128WOpnd, uimm5,	21709	MSA128WOpnd, MSA128WOpnd, uimm5,
21710	/* SB */	21710	/* SB */
21711	GPR32Opnd, -1, simm16,	21711	GPR32Opnd, -1, simm16,
21712	/* SB16_MM */	21712	/* SB16_MM */
21713	GPRMM16OpndZero, -1, simm4,	21713	GPRMM16OpndZero, -1, simm4,
21714	/* SB16_MMR6 */	21714	/* SB16_MMR6 */
21715	GPRMM16OpndZero, -1, simm4,	21715	GPRMM16OpndZero, -1, simm4,
21716	/* SB64 */	21716	/* SB64 */
21717	GPR64Opnd, -1, simm16,	21717	GPR64Opnd, -1, simm16,
21718	/* SBE */	21718	/* SBE */
21719	GPR32Opnd, -1, simm9,	21719	GPR32Opnd, -1, simm9,
21720	/* SBE_MM */	21720	/* SBE_MM */
21721	GPR32Opnd, -1, simm9,	21721	GPR32Opnd, -1, simm9,
21722	/* SB_MM */	21722	/* SB_MM */
21723	GPR32Opnd, -1, simm16,	21723	GPR32Opnd, -1, simm16,
21724	/* SB_MMR6 */	21724	/* SB_MMR6 */
21725	GPR32Opnd, -1, simm16,	21725	GPR32Opnd, -1, simm16,
21726	/* SC */	21726	/* SC */
21727	GPR32Opnd, GPR32Opnd, -1, simm16,	21727	GPR32Opnd, GPR32Opnd, -1, simm16,
21728	/* SC64 */	21728	/* SC64 */
21729	GPR32Opnd, GPR32Opnd, -1, simm16,	21729	GPR32Opnd, GPR32Opnd, -1, simm16,
21730	/* SC64_R6 */	21730	/* SC64_R6 */
21731	GPR32Opnd, GPR32Opnd, -1, simm9,	21731	GPR32Opnd, GPR32Opnd, -1, simm9,
21732	/* SCD */	21732	/* SCD */
21733	GPR64Opnd, GPR64Opnd, -1, simm16,	21733	GPR64Opnd, GPR64Opnd, -1, simm16,
21734	/* SCD_R6 */	21734	/* SCD_R6 */
21735	GPR64Opnd, GPR64Opnd, -1, simm9,	21735	GPR64Opnd, GPR64Opnd, -1, simm9,
21736	/* SCE */	21736	/* SCE */
21737	GPR32Opnd, GPR32Opnd, -1, simm9,	21737	GPR32Opnd, GPR32Opnd, -1, simm9,
21738	/* SCE_MM */	21738	/* SCE_MM */
21739	GPR32Opnd, GPR32Opnd, -1, simm9,	21739	GPR32Opnd, GPR32Opnd, -1, simm9,
21740	/* SC_MM */	21740	/* SC_MM */
21741	GPR32Opnd, GPR32Opnd, -1, simm12,	21741	GPR32Opnd, GPR32Opnd, -1, simm12,
21742	/* SC_MMR6 */	21742	/* SC_MMR6 */
21743	GPR32Opnd, GPR32Opnd, -1, simm9,	21743	GPR32Opnd, GPR32Opnd, -1, simm9,
21744	/* SC_R6 */	21744	/* SC_R6 */
21745	GPR32Opnd, GPR32Opnd, -1, simm9,	21745	GPR32Opnd, GPR32Opnd, -1, simm9,
21746	/* SD */	21746	/* SD */
21747	GPR64Opnd, -1, simm16,	21747	GPR64Opnd, -1, simm16,
21748	/* SDBBP */	21748	/* SDBBP */
21749	uimm20,	21749	uimm20,
21750	/* SDBBP16_MM */	21750	/* SDBBP16_MM */
21751	uimm4,	21751	uimm4,
21752	/* SDBBP16_MMR6 */	21752	/* SDBBP16_MMR6 */
21753	uimm4,	21753	uimm4,
21754	/* SDBBP_MM */	21754	/* SDBBP_MM */
21755	uimm10,	21755	uimm10,
21756	/* SDBBP_MMR6 */	21756	/* SDBBP_MMR6 */
21757	uimm20,	21757	uimm20,
21758	/* SDBBP_R6 */	21758	/* SDBBP_R6 */
21759	uimm20,	21759	uimm20,
21760	/* SDC1 */	21760	/* SDC1 */
21761	AFGR64Opnd, -1, simm16,	21761	AFGR64Opnd, -1, simm16,
21762	/* SDC164 */	21762	/* SDC164 */
21763	FGR64Opnd, -1, simm16,	21763	FGR64Opnd, -1, simm16,
21764	/* SDC1_D64_MMR6 */	21764	/* SDC1_D64_MMR6 */
21765	FGR64Opnd, -1, simm16,	21765	FGR64Opnd, -1, simm16,
21766	/* SDC1_MM_D32 */	21766	/* SDC1_MM_D32 */
21767	AFGR64Opnd, -1, simm16,	21767	AFGR64Opnd, -1, simm16,
21768	/* SDC1_MM_D64 */	21768	/* SDC1_MM_D64 */
21769	FGR64Opnd, -1, simm16,	21769	FGR64Opnd, -1, simm16,
21770	/* SDC2 */	21770	/* SDC2 */
21771	COP2Opnd, -1, simm16,	21771	COP2Opnd, -1, simm16,
21772	/* SDC2_MMR6 */	21772	/* SDC2_MMR6 */
21773	COP2Opnd, GPR32, simm11,	21773	COP2Opnd, GPR32, simm11,
21774	/* SDC2_R6 */	21774	/* SDC2_R6 */
21775	COP2Opnd, -1, simm11,	21775	COP2Opnd, -1, simm11,
21776	/* SDC3 */	21776	/* SDC3 */
21777	COP3Opnd, -1, simm16,	21777	COP3Opnd, -1, simm16,
21778	/* SDIV */	21778	/* SDIV */
21779	GPR32Opnd, GPR32Opnd,	21779	GPR32Opnd, GPR32Opnd,
21780	/* SDIV_MM */	21780	/* SDIV_MM */
21781	GPR32Opnd, GPR32Opnd,	21781	GPR32Opnd, GPR32Opnd,
21782	/* SDL */	21782	/* SDL */
21783	GPR64Opnd, -1, simm16,	21783	GPR64Opnd, -1, simm16,
21784	/* SDR */	21784	/* SDR */
21785	GPR64Opnd, -1, simm16,	21785	GPR64Opnd, -1, simm16,
21786	/* SDXC1 */	21786	/* SDXC1 */
21787	AFGR64Opnd, -1, -1,	21787	AFGR64Opnd, -1, -1,
21788	/* SDXC164 */	21788	/* SDXC164 */
21789	FGR64Opnd, -1, -1,	21789	FGR64Opnd, -1, -1,
21790	/* SEB */	21790	/* SEB */
21791	GPR32Opnd, GPR32Opnd,	21791	GPR32Opnd, GPR32Opnd,
21792	/* SEB64 */	21792	/* SEB64 */
21793	GPR64Opnd, GPR64Opnd,	21793	GPR64Opnd, GPR64Opnd,
21794	/* SEB_MM */	21794	/* SEB_MM */
21795	GPR32Opnd, GPR32Opnd,	21795	GPR32Opnd, GPR32Opnd,
21796	/* SEH */	21796	/* SEH */
21797	GPR32Opnd, GPR32Opnd,	21797	GPR32Opnd, GPR32Opnd,
21798	/* SEH64 */	21798	/* SEH64 */
21799	GPR64Opnd, GPR64Opnd,	21799	GPR64Opnd, GPR64Opnd,
21800	/* SEH_MM */	21800	/* SEH_MM */
21801	GPR32Opnd, GPR32Opnd,	21801	GPR32Opnd, GPR32Opnd,
21802	/* SELEQZ */	21802	/* SELEQZ */
21803	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21803	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21804	/* SELEQZ64 */	21804	/* SELEQZ64 */
21805	GPR64Opnd, GPR64Opnd, GPR64Opnd,	21805	GPR64Opnd, GPR64Opnd, GPR64Opnd,
21806	/* SELEQZ_D */	21806	/* SELEQZ_D */
21807	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21807	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21808	/* SELEQZ_D_MMR6 */	21808	/* SELEQZ_D_MMR6 */
21809	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21809	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21810	/* SELEQZ_MMR6 */	21810	/* SELEQZ_MMR6 */
21811	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21811	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21812	/* SELEQZ_S */	21812	/* SELEQZ_S */
21813	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21813	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21814	/* SELEQZ_S_MMR6 */	21814	/* SELEQZ_S_MMR6 */
21815	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21815	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21816	/* SELNEZ */	21816	/* SELNEZ */
21817	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21817	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21818	/* SELNEZ64 */	21818	/* SELNEZ64 */
21819	GPR64Opnd, GPR64Opnd, GPR64Opnd,	21819	GPR64Opnd, GPR64Opnd, GPR64Opnd,
21820	/* SELNEZ_D */	21820	/* SELNEZ_D */
21821	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21821	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21822	/* SELNEZ_D_MMR6 */	21822	/* SELNEZ_D_MMR6 */
21823	FGR64Opnd, FGR64Opnd, FGR64Opnd,	21823	FGR64Opnd, FGR64Opnd, FGR64Opnd,
21824	/* SELNEZ_MMR6 */	21824	/* SELNEZ_MMR6 */
21825	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21825	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21826	/* SELNEZ_S */	21826	/* SELNEZ_S */
21827	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21827	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21828	/* SELNEZ_S_MMR6 */	21828	/* SELNEZ_S_MMR6 */
21829	FGR32Opnd, FGR32Opnd, FGR32Opnd,	21829	FGR32Opnd, FGR32Opnd, FGR32Opnd,
21830	/* SEL_D */	21830	/* SEL_D */
21831	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21831	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21832	/* SEL_D_MMR6 */	21832	/* SEL_D_MMR6 */
21833	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	21833	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21834	/* SEL_S */	21834	/* SEL_S */
21835	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	21835	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,
21836	/* SEL_S_MMR6 */	21836	/* SEL_S_MMR6 */
21837	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	21837	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,
21838	/* SEQ */	21838	/* SEQ */
21839	GPR64Opnd, GPR64Opnd, GPR64Opnd,	21839	GPR64Opnd, GPR64Opnd, GPR64Opnd,
21840	/* SEQi */	21840	/* SEQi */
21841	GPR64Opnd, GPR64Opnd, simm10_64,	21841	GPR64Opnd, GPR64Opnd, simm10_64,
21842	/* SH */	21842	/* SH */
21843	GPR32Opnd, -1, simm16,	21843	GPR32Opnd, -1, simm16,
21844	/* SH16_MM */	21844	/* SH16_MM */
21845	GPRMM16OpndZero, -1, simm4,	21845	GPRMM16OpndZero, -1, simm4,
21846	/* SH16_MMR6 */	21846	/* SH16_MMR6 */
21847	GPRMM16OpndZero, -1, simm4,	21847	GPRMM16OpndZero, -1, simm4,
21848	/* SH64 */	21848	/* SH64 */
21849	GPR64Opnd, -1, simm16,	21849	GPR64Opnd, -1, simm16,
21850	/* SHE */	21850	/* SHE */
21851	GPR32Opnd, -1, simm9,	21851	GPR32Opnd, -1, simm9,
21852	/* SHE_MM */	21852	/* SHE_MM */
21853	GPR32Opnd, -1, simm9,	21853	GPR32Opnd, -1, simm9,
21854	/* SHF_B */	21854	/* SHF_B */
21855	MSA128BOpnd, MSA128BOpnd, uimm8,	21855	MSA128BOpnd, MSA128BOpnd, uimm8,
21856	/* SHF_H */	21856	/* SHF_H */
21857	MSA128HOpnd, MSA128HOpnd, uimm8,	21857	MSA128HOpnd, MSA128HOpnd, uimm8,
21858	/* SHF_W */	21858	/* SHF_W */
21859	MSA128WOpnd, MSA128WOpnd, uimm8,	21859	MSA128WOpnd, MSA128WOpnd, uimm8,
21860	/* SHILO */	21860	/* SHILO */
21861	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	21861	ACC64DSPOpnd, simm6, ACC64DSPOpnd,
21862	/* SHILOV */	21862	/* SHILOV */
21863	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	21863	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21864	/* SHILOV_MM */	21864	/* SHILOV_MM */
21865	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	21865	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21866	/* SHILO_MM */	21866	/* SHILO_MM */
21867	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	21867	ACC64DSPOpnd, simm6, ACC64DSPOpnd,
21868	/* SHLLV_PH */	21868	/* SHLLV_PH */
21869	DSPROpnd, DSPROpnd, GPR32Opnd,	21869	DSPROpnd, DSPROpnd, GPR32Opnd,
21870	/* SHLLV_PH_MM */	21870	/* SHLLV_PH_MM */
21871	DSPROpnd, DSPROpnd, GPR32Opnd,	21871	DSPROpnd, DSPROpnd, GPR32Opnd,
21872	/* SHLLV_QB */	21872	/* SHLLV_QB */
21873	DSPROpnd, DSPROpnd, GPR32Opnd,	21873	DSPROpnd, DSPROpnd, GPR32Opnd,
21874	/* SHLLV_QB_MM */	21874	/* SHLLV_QB_MM */
21875	DSPROpnd, DSPROpnd, GPR32Opnd,	21875	DSPROpnd, DSPROpnd, GPR32Opnd,
21876	/* SHLLV_S_PH */	21876	/* SHLLV_S_PH */
21877	DSPROpnd, DSPROpnd, GPR32Opnd,	21877	DSPROpnd, DSPROpnd, GPR32Opnd,
21878	/* SHLLV_S_PH_MM */	21878	/* SHLLV_S_PH_MM */
21879	DSPROpnd, DSPROpnd, GPR32Opnd,	21879	DSPROpnd, DSPROpnd, GPR32Opnd,
21880	/* SHLLV_S_W */	21880	/* SHLLV_S_W */
21881	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21881	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21882	/* SHLLV_S_W_MM */	21882	/* SHLLV_S_W_MM */
21883	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21883	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21884	/* SHLL_PH */	21884	/* SHLL_PH */
21885	DSPROpnd, DSPROpnd, uimm4,	21885	DSPROpnd, DSPROpnd, uimm4,
21886	/* SHLL_PH_MM */	21886	/* SHLL_PH_MM */
21887	DSPROpnd, DSPROpnd, uimm4,	21887	DSPROpnd, DSPROpnd, uimm4,
21888	/* SHLL_QB */	21888	/* SHLL_QB */
21889	DSPROpnd, DSPROpnd, uimm3,	21889	DSPROpnd, DSPROpnd, uimm3,
21890	/* SHLL_QB_MM */	21890	/* SHLL_QB_MM */
21891	DSPROpnd, DSPROpnd, uimm3,	21891	DSPROpnd, DSPROpnd, uimm3,
21892	/* SHLL_S_PH */	21892	/* SHLL_S_PH */
21893	DSPROpnd, DSPROpnd, uimm4,	21893	DSPROpnd, DSPROpnd, uimm4,
21894	/* SHLL_S_PH_MM */	21894	/* SHLL_S_PH_MM */
21895	DSPROpnd, DSPROpnd, uimm4,	21895	DSPROpnd, DSPROpnd, uimm4,
21896	/* SHLL_S_W */	21896	/* SHLL_S_W */
21897	GPR32Opnd, GPR32Opnd, uimm5,	21897	GPR32Opnd, GPR32Opnd, uimm5,
21898	/* SHLL_S_W_MM */	21898	/* SHLL_S_W_MM */
21899	GPR32Opnd, GPR32Opnd, uimm5,	21899	GPR32Opnd, GPR32Opnd, uimm5,
21900	/* SHRAV_PH */	21900	/* SHRAV_PH */
21901	DSPROpnd, DSPROpnd, GPR32Opnd,	21901	DSPROpnd, DSPROpnd, GPR32Opnd,
21902	/* SHRAV_PH_MM */	21902	/* SHRAV_PH_MM */
21903	DSPROpnd, DSPROpnd, GPR32Opnd,	21903	DSPROpnd, DSPROpnd, GPR32Opnd,
21904	/* SHRAV_QB */	21904	/* SHRAV_QB */
21905	DSPROpnd, DSPROpnd, GPR32Opnd,	21905	DSPROpnd, DSPROpnd, GPR32Opnd,
21906	/* SHRAV_QB_MMR2 */	21906	/* SHRAV_QB_MMR2 */
21907	DSPROpnd, DSPROpnd, GPR32Opnd,	21907	DSPROpnd, DSPROpnd, GPR32Opnd,
21908	/* SHRAV_R_PH */	21908	/* SHRAV_R_PH */
21909	DSPROpnd, DSPROpnd, GPR32Opnd,	21909	DSPROpnd, DSPROpnd, GPR32Opnd,
21910	/* SHRAV_R_PH_MM */	21910	/* SHRAV_R_PH_MM */
21911	DSPROpnd, DSPROpnd, GPR32Opnd,	21911	DSPROpnd, DSPROpnd, GPR32Opnd,
21912	/* SHRAV_R_QB */	21912	/* SHRAV_R_QB */
21913	DSPROpnd, DSPROpnd, GPR32Opnd,	21913	DSPROpnd, DSPROpnd, GPR32Opnd,
21914	/* SHRAV_R_QB_MMR2 */	21914	/* SHRAV_R_QB_MMR2 */
21915	DSPROpnd, DSPROpnd, GPR32Opnd,	21915	DSPROpnd, DSPROpnd, GPR32Opnd,
21916	/* SHRAV_R_W */	21916	/* SHRAV_R_W */
21917	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21917	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21918	/* SHRAV_R_W_MM */	21918	/* SHRAV_R_W_MM */
21919	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21919	GPR32Opnd, GPR32Opnd, GPR32Opnd,
21920	/* SHRA_PH */	21920	/* SHRA_PH */
21921	DSPROpnd, DSPROpnd, uimm4,	21921	DSPROpnd, DSPROpnd, uimm4,
21922	/* SHRA_PH_MM */	21922	/* SHRA_PH_MM */
21923	DSPROpnd, DSPROpnd, uimm4,	21923	DSPROpnd, DSPROpnd, uimm4,
21924	/* SHRA_QB */	21924	/* SHRA_QB */
21925	DSPROpnd, DSPROpnd, uimm3,	21925	DSPROpnd, DSPROpnd, uimm3,
21926	/* SHRA_QB_MMR2 */	21926	/* SHRA_QB_MMR2 */
21927	DSPROpnd, DSPROpnd, uimm3,	21927	DSPROpnd, DSPROpnd, uimm3,
21928	/* SHRA_R_PH */	21928	/* SHRA_R_PH */
21929	DSPROpnd, DSPROpnd, uimm4,	21929	DSPROpnd, DSPROpnd, uimm4,
21930	/* SHRA_R_PH_MM */	21930	/* SHRA_R_PH_MM */
21931	DSPROpnd, DSPROpnd, uimm4,	21931	DSPROpnd, DSPROpnd, uimm4,
21932	/* SHRA_R_QB */	21932	/* SHRA_R_QB */
21933	DSPROpnd, DSPROpnd, uimm3,	21933	DSPROpnd, DSPROpnd, uimm3,
21934	/* SHRA_R_QB_MMR2 */	21934	/* SHRA_R_QB_MMR2 */
21935	DSPROpnd, DSPROpnd, uimm3,	21935	DSPROpnd, DSPROpnd, uimm3,
21936	/* SHRA_R_W */	21936	/* SHRA_R_W */
21937	GPR32Opnd, GPR32Opnd, uimm5,	21937	GPR32Opnd, GPR32Opnd, uimm5,
21938	/* SHRA_R_W_MM */	21938	/* SHRA_R_W_MM */
21939	GPR32Opnd, GPR32Opnd, uimm5,	21939	GPR32Opnd, GPR32Opnd, uimm5,
21940	/* SHRLV_PH */	21940	/* SHRLV_PH */
21941	DSPROpnd, DSPROpnd, GPR32Opnd,	21941	DSPROpnd, DSPROpnd, GPR32Opnd,
21942	/* SHRLV_PH_MMR2 */	21942	/* SHRLV_PH_MMR2 */
21943	DSPROpnd, DSPROpnd, GPR32Opnd,	21943	DSPROpnd, DSPROpnd, GPR32Opnd,
21944	/* SHRLV_QB */	21944	/* SHRLV_QB */
21945	DSPROpnd, DSPROpnd, GPR32Opnd,	21945	DSPROpnd, DSPROpnd, GPR32Opnd,
21946	/* SHRLV_QB_MM */	21946	/* SHRLV_QB_MM */
21947	DSPROpnd, DSPROpnd, GPR32Opnd,	21947	DSPROpnd, DSPROpnd, GPR32Opnd,
21948	/* SHRL_PH */	21948	/* SHRL_PH */
21949	DSPROpnd, DSPROpnd, uimm4,	21949	DSPROpnd, DSPROpnd, uimm4,
21950	/* SHRL_PH_MMR2 */	21950	/* SHRL_PH_MMR2 */
21951	DSPROpnd, DSPROpnd, uimm4,	21951	DSPROpnd, DSPROpnd, uimm4,
21952	/* SHRL_QB */	21952	/* SHRL_QB */
21953	DSPROpnd, DSPROpnd, uimm3,	21953	DSPROpnd, DSPROpnd, uimm3,
21954	/* SHRL_QB_MM */	21954	/* SHRL_QB_MM */
21955	DSPROpnd, DSPROpnd, uimm3,	21955	DSPROpnd, DSPROpnd, uimm3,
21956	/* SH_MM */	21956	/* SH_MM */
21957	GPR32Opnd, -1, simm16,	21957	GPR32Opnd, -1, simm16,
21958	/* SH_MMR6 */	21958	/* SH_MMR6 */
21959	GPR32Opnd, -1, simm16,	21959	GPR32Opnd, -1, simm16,
21960	/* SIGRIE */	21960	/* SIGRIE */
21961	uimm16,	21961	uimm16,
21962	/* SIGRIE_MMR6 */	21962	/* SIGRIE_MMR6 */
21963	uimm16,	21963	uimm16,
21964	/* SLDI_B */	21964	/* SLDI_B */
21965	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,	21965	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,
21966	/* SLDI_D */	21966	/* SLDI_D */
21967	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,	21967	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,
21968	/* SLDI_H */	21968	/* SLDI_H */
21969	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,	21969	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,
21970	/* SLDI_W */	21970	/* SLDI_W */
21971	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,	21971	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,
21972	/* SLD_B */	21972	/* SLD_B */
21973	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	21973	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,
21974	/* SLD_D */	21974	/* SLD_D */
21975	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	21975	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,
21976	/* SLD_H */	21976	/* SLD_H */
21977	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	21977	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,
21978	/* SLD_W */	21978	/* SLD_W */
21979	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	21979	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,
21980	/* SLL */	21980	/* SLL */
21981	GPR32Opnd, GPR32Opnd, uimm5,	21981	GPR32Opnd, GPR32Opnd, uimm5,
21982	/* SLL16_MM */	21982	/* SLL16_MM */
21983	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	21983	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
21984	/* SLL16_MMR6 */	21984	/* SLL16_MMR6 */
21985	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	21985	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
21986	/* SLL64_32 */	21986	/* SLL64_32 */
21987	GPR64, GPR32,	21987	GPR64, GPR32,
21988	/* SLL64_64 */	21988	/* SLL64_64 */
21989	GPR64, GPR64,	21989	GPR64, GPR64,
21990	/* SLLI_B */	21990	/* SLLI_B */
21991	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	21991	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
21992	/* SLLI_D */	21992	/* SLLI_D */
21993	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	21993	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
21994	/* SLLI_H */	21994	/* SLLI_H */
21995	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	21995	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
21996	/* SLLI_W */	21996	/* SLLI_W */
21997	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	21997	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
21998	/* SLLV */	21998	/* SLLV */
21999	GPR32Opnd, GPR32Opnd, GPR32Opnd,	21999	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22000	/* SLLV_MM */	22000	/* SLLV_MM */
22001	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22001	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22002	/* SLL_B */	22002	/* SLL_B */
22003	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22003	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22004	/* SLL_D */	22004	/* SLL_D */
22005	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22005	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22006	/* SLL_H */	22006	/* SLL_H */
22007	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22007	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22008	/* SLL_MM */	22008	/* SLL_MM */
22009	GPR32Opnd, GPR32Opnd, uimm5,	22009	GPR32Opnd, GPR32Opnd, uimm5,
22010	/* SLL_MMR6 */	22010	/* SLL_MMR6 */
22011	GPR32Opnd, GPR32Opnd, uimm5,	22011	GPR32Opnd, GPR32Opnd, uimm5,
22012	/* SLL_W */	22012	/* SLL_W */
22013	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22013	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22014	/* SLT */	22014	/* SLT */
22015	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22015	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22016	/* SLT64 */	22016	/* SLT64 */
22017	GPR32Opnd, GPR64Opnd, GPR64Opnd,	22017	GPR32Opnd, GPR64Opnd, GPR64Opnd,
22018	/* SLT_MM */	22018	/* SLT_MM */
22019	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22019	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22020	/* SLTi */	22020	/* SLTi */
22021	GPR32Opnd, GPR32Opnd, simm16,	22021	GPR32Opnd, GPR32Opnd, simm16,
22022	/* SLTi64 */	22022	/* SLTi64 */
22023	GPR32Opnd, GPR64Opnd, simm16_64,	22023	GPR32Opnd, GPR64Opnd, simm16_64,
22024	/* SLTi_MM */	22024	/* SLTi_MM */
22025	GPR32Opnd, GPR32Opnd, simm16,	22025	GPR32Opnd, GPR32Opnd, simm16,
22026	/* SLTiu */	22026	/* SLTiu */
22027	GPR32Opnd, GPR32Opnd, simm16,	22027	GPR32Opnd, GPR32Opnd, simm16,
22028	/* SLTiu64 */	22028	/* SLTiu64 */
22029	GPR32Opnd, GPR64Opnd, simm16_64,	22029	GPR32Opnd, GPR64Opnd, simm16_64,
22030	/* SLTiu_MM */	22030	/* SLTiu_MM */
22031	GPR32Opnd, GPR32Opnd, simm16,	22031	GPR32Opnd, GPR32Opnd, simm16,
22032	/* SLTu */	22032	/* SLTu */
22033	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22033	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22034	/* SLTu64 */	22034	/* SLTu64 */
22035	GPR32Opnd, GPR64Opnd, GPR64Opnd,	22035	GPR32Opnd, GPR64Opnd, GPR64Opnd,
22036	/* SLTu_MM */	22036	/* SLTu_MM */
22037	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22037	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22038	/* SNE */	22038	/* SNE */
22039	GPR64Opnd, GPR64Opnd, GPR64Opnd,	22039	GPR64Opnd, GPR64Opnd, GPR64Opnd,
22040	/* SNEi */	22040	/* SNEi */
22041	GPR64Opnd, GPR64Opnd, simm10_64,	22041	GPR64Opnd, GPR64Opnd, simm10_64,
22042	/* SPLATI_B */	22042	/* SPLATI_B */
22043	MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,	22043	MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,
22044	/* SPLATI_D */	22044	/* SPLATI_D */
22045	MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,	22045	MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,
22046	/* SPLATI_H */	22046	/* SPLATI_H */
22047	MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,	22047	MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,
22048	/* SPLATI_W */	22048	/* SPLATI_W */
22049	MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,	22049	MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,
22050	/* SPLAT_B */	22050	/* SPLAT_B */
22051	MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	22051	MSA128BOpnd, MSA128BOpnd, GPR32Opnd,
22052	/* SPLAT_D */	22052	/* SPLAT_D */
22053	MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	22053	MSA128DOpnd, MSA128DOpnd, GPR32Opnd,
22054	/* SPLAT_H */	22054	/* SPLAT_H */
22055	MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	22055	MSA128HOpnd, MSA128HOpnd, GPR32Opnd,
22056	/* SPLAT_W */	22056	/* SPLAT_W */
22057	MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	22057	MSA128WOpnd, MSA128WOpnd, GPR32Opnd,
22058	/* SRA */	22058	/* SRA */
22059	GPR32Opnd, GPR32Opnd, uimm5,	22059	GPR32Opnd, GPR32Opnd, uimm5,
22060	/* SRAI_B */	22060	/* SRAI_B */
22061	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	22061	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
22062	/* SRAI_D */	22062	/* SRAI_D */
22063	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	22063	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
22064	/* SRAI_H */	22064	/* SRAI_H */
22065	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	22065	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
22066	/* SRAI_W */	22066	/* SRAI_W */
22067	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	22067	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22068	/* SRARI_B */	22068	/* SRARI_B */
22069	MSA128BOpnd, MSA128BOpnd, uimm3,	22069	MSA128BOpnd, MSA128BOpnd, uimm3,
22070	/* SRARI_D */	22070	/* SRARI_D */
22071	MSA128DOpnd, MSA128DOpnd, uimm6,	22071	MSA128DOpnd, MSA128DOpnd, uimm6,
22072	/* SRARI_H */	22072	/* SRARI_H */
22073	MSA128HOpnd, MSA128HOpnd, uimm4,	22073	MSA128HOpnd, MSA128HOpnd, uimm4,
22074	/* SRARI_W */	22074	/* SRARI_W */
22075	MSA128WOpnd, MSA128WOpnd, uimm5,	22075	MSA128WOpnd, MSA128WOpnd, uimm5,
22076	/* SRAR_B */	22076	/* SRAR_B */
22077	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22077	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22078	/* SRAR_D */	22078	/* SRAR_D */
22079	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22079	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22080	/* SRAR_H */	22080	/* SRAR_H */
22081	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22081	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22082	/* SRAR_W */	22082	/* SRAR_W */
22083	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22083	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22084	/* SRAV */	22084	/* SRAV */
22085	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22085	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22086	/* SRAV_MM */	22086	/* SRAV_MM */
22087	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22087	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22088	/* SRA_B */	22088	/* SRA_B */
22089	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22089	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22090	/* SRA_D */	22090	/* SRA_D */
22091	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22091	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22092	/* SRA_H */	22092	/* SRA_H */
22093	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22093	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22094	/* SRA_MM */	22094	/* SRA_MM */
22095	GPR32Opnd, GPR32Opnd, uimm5,	22095	GPR32Opnd, GPR32Opnd, uimm5,
22096	/* SRA_W */	22096	/* SRA_W */
22097	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22097	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22098	/* SRL */	22098	/* SRL */
22099	GPR32Opnd, GPR32Opnd, uimm5,	22099	GPR32Opnd, GPR32Opnd, uimm5,
22100	/* SRL16_MM */	22100	/* SRL16_MM */
22101	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	22101	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22102	/* SRL16_MMR6 */	22102	/* SRL16_MMR6 */
22103	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	22103	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22104	/* SRLI_B */	22104	/* SRLI_B */
22105	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	22105	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
22106	/* SRLI_D */	22106	/* SRLI_D */
22107	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	22107	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
22108	/* SRLI_H */	22108	/* SRLI_H */
22109	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	22109	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
22110	/* SRLI_W */	22110	/* SRLI_W */
22111	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	22111	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22112	/* SRLRI_B */	22112	/* SRLRI_B */
22113	MSA128BOpnd, MSA128BOpnd, uimm3,	22113	MSA128BOpnd, MSA128BOpnd, uimm3,
22114	/* SRLRI_D */	22114	/* SRLRI_D */
22115	MSA128DOpnd, MSA128DOpnd, uimm6,	22115	MSA128DOpnd, MSA128DOpnd, uimm6,
22116	/* SRLRI_H */	22116	/* SRLRI_H */
22117	MSA128HOpnd, MSA128HOpnd, uimm4,	22117	MSA128HOpnd, MSA128HOpnd, uimm4,
22118	/* SRLRI_W */	22118	/* SRLRI_W */
22119	MSA128WOpnd, MSA128WOpnd, uimm5,	22119	MSA128WOpnd, MSA128WOpnd, uimm5,
22120	/* SRLR_B */	22120	/* SRLR_B */
22121	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22121	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22122	/* SRLR_D */	22122	/* SRLR_D */
22123	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22123	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22124	/* SRLR_H */	22124	/* SRLR_H */
22125	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22125	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22126	/* SRLR_W */	22126	/* SRLR_W */
22127	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22127	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22128	/* SRLV */	22128	/* SRLV */
22129	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22129	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22130	/* SRLV_MM */	22130	/* SRLV_MM */
22131	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22131	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22132	/* SRL_B */	22132	/* SRL_B */
22133	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22133	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22134	/* SRL_D */	22134	/* SRL_D */
22135	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22135	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22136	/* SRL_H */	22136	/* SRL_H */
22137	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22137	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22138	/* SRL_MM */	22138	/* SRL_MM */
22139	GPR32Opnd, GPR32Opnd, uimm5,	22139	GPR32Opnd, GPR32Opnd, uimm5,
22140	/* SRL_W */	22140	/* SRL_W */
22141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22142	/* SSNOP */	22142	/* SSNOP */
22143	/* SSNOP_MM */	22143	/* SSNOP_MM */
22144	/* SSNOP_MMR6 */	22144	/* SSNOP_MMR6 */
22145	/* ST_B */	22145	/* ST_B */
22146	MSA128BOpnd, -1, simm10,	22146	MSA128BOpnd, -1, simm10,
22147	/* ST_D */	22147	/* ST_D */
22148	MSA128DOpnd, -1, simm10_lsl3,	22148	MSA128DOpnd, -1, simm10_lsl3,
22149	/* ST_H */	22149	/* ST_H */
22150	MSA128HOpnd, -1, simm10_lsl1,	22150	MSA128HOpnd, -1, simm10_lsl1,
22151	/* ST_W */	22151	/* ST_W */
22152	MSA128WOpnd, -1, simm10_lsl2,	22152	MSA128WOpnd, -1, simm10_lsl2,
22153	/* SUB */	22153	/* SUB */
22154	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22154	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22155	/* SUBQH_PH */	22155	/* SUBQH_PH */
22156	DSPROpnd, DSPROpnd, DSPROpnd,	22156	DSPROpnd, DSPROpnd, DSPROpnd,
22157	/* SUBQH_PH_MMR2 */	22157	/* SUBQH_PH_MMR2 */
22158	DSPROpnd, DSPROpnd, DSPROpnd,	22158	DSPROpnd, DSPROpnd, DSPROpnd,
22159	/* SUBQH_R_PH */	22159	/* SUBQH_R_PH */
22160	DSPROpnd, DSPROpnd, DSPROpnd,	22160	DSPROpnd, DSPROpnd, DSPROpnd,
22161	/* SUBQH_R_PH_MMR2 */	22161	/* SUBQH_R_PH_MMR2 */
22162	DSPROpnd, DSPROpnd, DSPROpnd,	22162	DSPROpnd, DSPROpnd, DSPROpnd,
22163	/* SUBQH_R_W */	22163	/* SUBQH_R_W */
22164	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22164	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22165	/* SUBQH_R_W_MMR2 */	22165	/* SUBQH_R_W_MMR2 */
22166	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22166	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22167	/* SUBQH_W */	22167	/* SUBQH_W */
22168	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22168	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22169	/* SUBQH_W_MMR2 */	22169	/* SUBQH_W_MMR2 */
22170	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22170	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22171	/* SUBQ_PH */	22171	/* SUBQ_PH */
22172	DSPROpnd, DSPROpnd, DSPROpnd,	22172	DSPROpnd, DSPROpnd, DSPROpnd,
22173	/* SUBQ_PH_MM */	22173	/* SUBQ_PH_MM */
22174	DSPROpnd, DSPROpnd, DSPROpnd,	22174	DSPROpnd, DSPROpnd, DSPROpnd,
22175	/* SUBQ_S_PH */	22175	/* SUBQ_S_PH */
22176	DSPROpnd, DSPROpnd, DSPROpnd,	22176	DSPROpnd, DSPROpnd, DSPROpnd,
22177	/* SUBQ_S_PH_MM */	22177	/* SUBQ_S_PH_MM */
22178	DSPROpnd, DSPROpnd, DSPROpnd,	22178	DSPROpnd, DSPROpnd, DSPROpnd,
22179	/* SUBQ_S_W */	22179	/* SUBQ_S_W */
22180	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22180	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22181	/* SUBQ_S_W_MM */	22181	/* SUBQ_S_W_MM */
22182	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22182	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22183	/* SUBSUS_U_B */	22183	/* SUBSUS_U_B */
22184	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22184	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22185	/* SUBSUS_U_D */	22185	/* SUBSUS_U_D */
22186	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22186	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22187	/* SUBSUS_U_H */	22187	/* SUBSUS_U_H */
22188	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22188	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22189	/* SUBSUS_U_W */	22189	/* SUBSUS_U_W */
22190	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22190	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22191	/* SUBSUU_S_B */	22191	/* SUBSUU_S_B */
22192	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22192	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22193	/* SUBSUU_S_D */	22193	/* SUBSUU_S_D */
22194	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22194	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22195	/* SUBSUU_S_H */	22195	/* SUBSUU_S_H */
22196	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22196	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22197	/* SUBSUU_S_W */	22197	/* SUBSUU_S_W */
22198	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22198	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22199	/* SUBS_S_B */	22199	/* SUBS_S_B */
22200	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22200	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22201	/* SUBS_S_D */	22201	/* SUBS_S_D */
22202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22203	/* SUBS_S_H */	22203	/* SUBS_S_H */
22204	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22204	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22205	/* SUBS_S_W */	22205	/* SUBS_S_W */
22206	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22206	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22207	/* SUBS_U_B */	22207	/* SUBS_U_B */
22208	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22208	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22209	/* SUBS_U_D */	22209	/* SUBS_U_D */
22210	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22210	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22211	/* SUBS_U_H */	22211	/* SUBS_U_H */
22212	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22212	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22213	/* SUBS_U_W */	22213	/* SUBS_U_W */
22214	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22214	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22215	/* SUBU16_MM */	22215	/* SUBU16_MM */
22216	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	22216	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22217	/* SUBU16_MMR6 */	22217	/* SUBU16_MMR6 */
22218	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	22218	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22219	/* SUBUH_QB */	22219	/* SUBUH_QB */
22220	DSPROpnd, DSPROpnd, DSPROpnd,	22220	DSPROpnd, DSPROpnd, DSPROpnd,
22221	/* SUBUH_QB_MMR2 */	22221	/* SUBUH_QB_MMR2 */
22222	DSPROpnd, DSPROpnd, DSPROpnd,	22222	DSPROpnd, DSPROpnd, DSPROpnd,
22223	/* SUBUH_R_QB */	22223	/* SUBUH_R_QB */
22224	DSPROpnd, DSPROpnd, DSPROpnd,	22224	DSPROpnd, DSPROpnd, DSPROpnd,
22225	/* SUBUH_R_QB_MMR2 */	22225	/* SUBUH_R_QB_MMR2 */
22226	DSPROpnd, DSPROpnd, DSPROpnd,	22226	DSPROpnd, DSPROpnd, DSPROpnd,
22227	/* SUBU_MMR6 */	22227	/* SUBU_MMR6 */
22228	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22228	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22229	/* SUBU_PH */	22229	/* SUBU_PH */
22230	DSPROpnd, DSPROpnd, DSPROpnd,	22230	DSPROpnd, DSPROpnd, DSPROpnd,
22231	/* SUBU_PH_MMR2 */	22231	/* SUBU_PH_MMR2 */
22232	DSPROpnd, DSPROpnd, DSPROpnd,	22232	DSPROpnd, DSPROpnd, DSPROpnd,
22233	/* SUBU_QB */	22233	/* SUBU_QB */
22234	DSPROpnd, DSPROpnd, DSPROpnd,	22234	DSPROpnd, DSPROpnd, DSPROpnd,
22235	/* SUBU_QB_MM */	22235	/* SUBU_QB_MM */
22236	DSPROpnd, DSPROpnd, DSPROpnd,	22236	DSPROpnd, DSPROpnd, DSPROpnd,
22237	/* SUBU_S_PH */	22237	/* SUBU_S_PH */
22238	DSPROpnd, DSPROpnd, DSPROpnd,	22238	DSPROpnd, DSPROpnd, DSPROpnd,
22239	/* SUBU_S_PH_MMR2 */	22239	/* SUBU_S_PH_MMR2 */
22240	DSPROpnd, DSPROpnd, DSPROpnd,	22240	DSPROpnd, DSPROpnd, DSPROpnd,
22241	/* SUBU_S_QB */	22241	/* SUBU_S_QB */
22242	DSPROpnd, DSPROpnd, DSPROpnd,	22242	DSPROpnd, DSPROpnd, DSPROpnd,
22243	/* SUBU_S_QB_MM */	22243	/* SUBU_S_QB_MM */
22244	DSPROpnd, DSPROpnd, DSPROpnd,	22244	DSPROpnd, DSPROpnd, DSPROpnd,
22245	/* SUBVI_B */	22245	/* SUBVI_B */
22246	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	22246	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
22247	/* SUBVI_D */	22247	/* SUBVI_D */
22248	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	22248	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
22249	/* SUBVI_H */	22249	/* SUBVI_H */
22250	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	22250	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
22251	/* SUBVI_W */	22251	/* SUBVI_W */
22252	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	22252	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22253	/* SUBV_B */	22253	/* SUBV_B */
22254	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22254	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22255	/* SUBV_D */	22255	/* SUBV_D */
22256	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22256	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22257	/* SUBV_H */	22257	/* SUBV_H */
22258	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22258	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22259	/* SUBV_W */	22259	/* SUBV_W */
22260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22261	/* SUB_MM */	22261	/* SUB_MM */
22262	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22262	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22263	/* SUB_MMR6 */	22263	/* SUB_MMR6 */
22264	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22264	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22265	/* SUBu */	22265	/* SUBu */
22266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22266	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22267	/* SUBu_MM */	22267	/* SUBu_MM */
22268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22268	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22269	/* SUXC1 */	22269	/* SUXC1 */
22270	AFGR64Opnd, -1, -1,	22270	AFGR64Opnd, -1, -1,
22271	/* SUXC164 */	22271	/* SUXC164 */
22272	FGR64Opnd, -1, -1,	22272	FGR64Opnd, -1, -1,
22273	/* SUXC1_MM */	22273	/* SUXC1_MM */
22274	FGR64Opnd, -1, -1,	22274	FGR64Opnd, -1, -1,
22275	/* SW */	22275	/* SW */
22276	GPR32Opnd, -1, simm16,	22276	GPR32Opnd, -1, simm16,
22277	/* SW16_MM */	22277	/* SW16_MM */
22278	GPRMM16OpndZero, -1, simm4,	22278	GPRMM16OpndZero, -1, simm4,
22279	/* SW16_MMR6 */	22279	/* SW16_MMR6 */
22280	GPRMM16OpndZero, -1, simm4,	22280	GPRMM16OpndZero, -1, simm4,
22281	/* SW64 */	22281	/* SW64 */
22282	GPR64Opnd, -1, simm16,	22282	GPR64Opnd, -1, simm16,
22283	/* SWC1 */	22283	/* SWC1 */
22284	FGR32Opnd, -1, simm16,	22284	FGR32Opnd, -1, simm16,
22285	/* SWC1_MM */	22285	/* SWC1_MM */
22286	FGR32Opnd, -1, simm16,	22286	FGR32Opnd, -1, simm16,
22287	/* SWC2 */	22287	/* SWC2 */
22288	COP2Opnd, -1, simm16,	22288	COP2Opnd, -1, simm16,
22289	/* SWC2_MMR6 */	22289	/* SWC2_MMR6 */
22290	COP2Opnd, GPR32, simm11,	22290	COP2Opnd, GPR32, simm11,
22291	/* SWC2_R6 */	22291	/* SWC2_R6 */
22292	COP2Opnd, -1, simm11,	22292	COP2Opnd, -1, simm11,
22293	/* SWC3 */	22293	/* SWC3 */
22294	COP3Opnd, -1, simm16,	22294	COP3Opnd, -1, simm16,
22295	/* SWDSP */	22295	/* SWDSP */
22296	DSPROpnd, -1, simm16,	22296	DSPROpnd, -1, simm16,
22297	/* SWDSP_MM */	22297	/* SWDSP_MM */
22298	DSPROpnd, -1, simm16,	22298	DSPROpnd, -1, simm16,
22299	/* SWE */	22299	/* SWE */
22300	GPR32Opnd, -1, simm9,	22300	GPR32Opnd, -1, simm9,
22301	/* SWE_MM */	22301	/* SWE_MM */
22302	GPR32Opnd, -1, simm9,	22302	GPR32Opnd, -1, simm9,
22303	/* SWL */	22303	/* SWL */
22304	GPR32Opnd, -1, simm16,	22304	GPR32Opnd, -1, simm16,
22305	/* SWL64 */	22305	/* SWL64 */
22306	GPR64Opnd, -1, simm16,	22306	GPR64Opnd, -1, simm16,
22307	/* SWLE */	22307	/* SWLE */
22308	GPR32Opnd, -1, simm9,	22308	GPR32Opnd, -1, simm9,
22309	/* SWLE_MM */	22309	/* SWLE_MM */
22310	GPR32Opnd, -1, simm9,	22310	GPR32Opnd, -1, simm9,
22311	/* SWL_MM */	22311	/* SWL_MM */
22312	GPR32Opnd, -1, simm12,	22312	GPR32Opnd, -1, simm12,
22313	/* SWM16_MM */	22313	/* SWM16_MM */
22314	reglist16, -1, uimm8,	22314	reglist16, -1, uimm8,
22315	/* SWM16_MMR6 */	22315	/* SWM16_MMR6 */
22316	reglist16, -1, uimm8,	22316	reglist16, -1, uimm8,
22317	/* SWM32_MM */	22317	/* SWM32_MM */
22318	reglist, -1, simm12,	22318	reglist, -1, simm12,
22319	/* SWP_MM */	22319	/* SWP_MM */
22320	GPR32Opnd, GPR32Opnd, -1, simm12,	22320	GPR32Opnd, GPR32Opnd, -1, simm12,
22321	/* SWR */	22321	/* SWR */
22322	GPR32Opnd, -1, simm16,	22322	GPR32Opnd, -1, simm16,
22323	/* SWR64 */	22323	/* SWR64 */
22324	GPR64Opnd, -1, simm16,	22324	GPR64Opnd, -1, simm16,
22325	/* SWRE */	22325	/* SWRE */
22326	GPR32Opnd, -1, simm9,	22326	GPR32Opnd, -1, simm9,
22327	/* SWRE_MM */	22327	/* SWRE_MM */
22328	GPR32Opnd, -1, simm9,	22328	GPR32Opnd, -1, simm9,
22329	/* SWR_MM */	22329	/* SWR_MM */
22330	GPR32Opnd, -1, simm12,	22330	GPR32Opnd, -1, simm12,
22331	/* SWSP_MM */	22331	/* SWSP_MM */
22332	GPR32Opnd, -1, simm5,	22332	GPR32Opnd, -1, simm5,
22333	/* SWSP_MMR6 */	22333	/* SWSP_MMR6 */
22334	GPR32Opnd, -1, simm5,	22334	GPR32Opnd, -1, simm5,
22335	/* SWXC1 */	22335	/* SWXC1 */
22336	FGR32Opnd, -1, -1,	22336	FGR32Opnd, -1, -1,
22337	/* SWXC1_MM */	22337	/* SWXC1_MM */
22338	FGR32Opnd, -1, -1,	22338	FGR32Opnd, -1, -1,
22339	/* SW_MM */	22339	/* SW_MM */
22340	GPR32Opnd, -1, simm16,	22340	GPR32Opnd, -1, simm16,
22341	/* SW_MMR6 */	22341	/* SW_MMR6 */
22342	GPR32Opnd, -1, simm16,	22342	GPR32Opnd, -1, simm16,
22343	/* SYNC */	22343	/* SYNC */
22344	uimm5,	22344	uimm5,
22345	/* SYNCI */	22345	/* SYNCI */
22346	-1, simm16,	22346	-1, simm16,
22347	/* SYNCI_MM */	22347	/* SYNCI_MM */
22348	-1, simm16,	22348	-1, simm16,
22349	/* SYNCI_MMR6 */	22349	/* SYNCI_MMR6 */
22350	-1, simm16,	22350	-1, simm16,
22351	/* SYNC_MM */	22351	/* SYNC_MM */
22352	uimm5,	22352	uimm5,
22353	/* SYNC_MMR6 */	22353	/* SYNC_MMR6 */
22354	uimm5,	22354	uimm5,
22355	/* SYSCALL */	22355	/* SYSCALL */
22356	uimm20,	22356	uimm20,
22357	/* SYSCALL_MM */	22357	/* SYSCALL_MM */
22358	uimm10,	22358	uimm10,
22359	/* Save16 */	22359	/* Save16 */
22360	/* SaveX16 */	22360	/* SaveX16 */
22361	/* SbRxRyOffMemX16 */	22361	/* SbRxRyOffMemX16 */
22362	CPU16Regs, CPU16Regs, simm16,	22362	CPU16Regs, CPU16Regs, simm16,
22363	/* SebRx16 */	22363	/* SebRx16 */
22364	CPU16Regs, CPU16Regs,	22364	CPU16Regs, CPU16Regs,
22365	/* SehRx16 */	22365	/* SehRx16 */
22366	CPU16Regs, CPU16Regs,	22366	CPU16Regs, CPU16Regs,
22367	/* ShRxRyOffMemX16 */	22367	/* ShRxRyOffMemX16 */
22368	CPU16Regs, CPU16Regs, simm16,	22368	CPU16Regs, CPU16Regs, simm16,
22369	/* SllX16 */	22369	/* SllX16 */
22370	CPU16Regs, CPU16Regs, uimm5,	22370	CPU16Regs, CPU16Regs, uimm5,
22371	/* SllvRxRy16 */	22371	/* SllvRxRy16 */
22372	CPU16Regs, CPU16Regs, CPU16Regs,	22372	CPU16Regs, CPU16Regs, CPU16Regs,
22373	/* SltRxRy16 */	22373	/* SltRxRy16 */
22374	CPU16Regs, CPU16Regs,	22374	CPU16Regs, CPU16Regs,
22375	/* SltiRxImm16 */	22375	/* SltiRxImm16 */
22376	CPU16Regs, simm16,	22376	CPU16Regs, simm16,
22377	/* SltiRxImmX16 */	22377	/* SltiRxImmX16 */
22378	CPU16Regs, simm16,	22378	CPU16Regs, simm16,
22379	/* SltiuRxImm16 */	22379	/* SltiuRxImm16 */
22380	CPU16Regs, simm16,	22380	CPU16Regs, simm16,
22381	/* SltiuRxImmX16 */	22381	/* SltiuRxImmX16 */
22382	CPU16Regs, simm16,	22382	CPU16Regs, simm16,
22383	/* SltuRxRy16 */	22383	/* SltuRxRy16 */
22384	CPU16Regs, CPU16Regs,	22384	CPU16Regs, CPU16Regs,
22385	/* SraX16 */	22385	/* SraX16 */
22386	CPU16Regs, CPU16Regs, uimm5,	22386	CPU16Regs, CPU16Regs, uimm5,
22387	/* SravRxRy16 */	22387	/* SravRxRy16 */
22388	CPU16Regs, CPU16Regs, CPU16Regs,	22388	CPU16Regs, CPU16Regs, CPU16Regs,
22389	/* SrlX16 */	22389	/* SrlX16 */
22390	CPU16Regs, CPU16Regs, uimm5,	22390	CPU16Regs, CPU16Regs, uimm5,
22391	/* SrlvRxRy16 */	22391	/* SrlvRxRy16 */
22392	CPU16Regs, CPU16Regs, CPU16Regs,	22392	CPU16Regs, CPU16Regs, CPU16Regs,
22393	/* SubuRxRyRz16 */	22393	/* SubuRxRyRz16 */
22394	CPU16Regs, CPU16Regs, CPU16Regs,	22394	CPU16Regs, CPU16Regs, CPU16Regs,
22395	/* SwRxRyOffMemX16 */	22395	/* SwRxRyOffMemX16 */
22396	CPU16Regs, CPU16Regs, simm16,	22396	CPU16Regs, CPU16Regs, simm16,
22397	/* SwRxSpImmX16 */	22397	/* SwRxSpImmX16 */
22398	CPU16Regs, CPU16RegsPlusSP, simm16,	22398	CPU16Regs, CPU16RegsPlusSP, simm16,
22399	/* TEQ */	22399	/* TEQ */
22400	GPR32Opnd, GPR32Opnd, uimm10,	22400	GPR32Opnd, GPR32Opnd, uimm10,
22401	/* TEQI */	22401	/* TEQI */
22402	GPR32Opnd, simm16,	22402	GPR32Opnd, simm16,
22403	/* TEQI_MM */	22403	/* TEQI_MM */
22404	GPR32Opnd, simm16,	22404	GPR32Opnd, simm16,
22405	/* TEQ_MM */	22405	/* TEQ_MM */
22406	GPR32Opnd, GPR32Opnd, uimm4,	22406	GPR32Opnd, GPR32Opnd, uimm4,
22407	/* TGE */	22407	/* TGE */
22408	GPR32Opnd, GPR32Opnd, uimm10,	22408	GPR32Opnd, GPR32Opnd, uimm10,
22409	/* TGEI */	22409	/* TGEI */
22410	GPR32Opnd, simm16,	22410	GPR32Opnd, simm16,
22411	/* TGEIU */	22411	/* TGEIU */
22412	GPR32Opnd, simm16,	22412	GPR32Opnd, simm16,
22413	/* TGEIU_MM */	22413	/* TGEIU_MM */
22414	GPR32Opnd, simm16,	22414	GPR32Opnd, simm16,
22415	/* TGEI_MM */	22415	/* TGEI_MM */
22416	GPR32Opnd, simm16,	22416	GPR32Opnd, simm16,
22417	/* TGEU */	22417	/* TGEU */
22418	GPR32Opnd, GPR32Opnd, uimm10,	22418	GPR32Opnd, GPR32Opnd, uimm10,
22419	/* TGEU_MM */	22419	/* TGEU_MM */
22420	GPR32Opnd, GPR32Opnd, uimm4,	22420	GPR32Opnd, GPR32Opnd, uimm4,
22421	/* TGE_MM */	22421	/* TGE_MM */
22422	GPR32Opnd, GPR32Opnd, uimm4,	22422	GPR32Opnd, GPR32Opnd, uimm4,
22423	/* TLBGINV */	22423	/* TLBGINV */
22424	/* TLBGINVF */	22424	/* TLBGINVF */
22425	/* TLBGINVF_MM */	22425	/* TLBGINVF_MM */
22426	/* TLBGINV_MM */	22426	/* TLBGINV_MM */
22427	/* TLBGP */	22427	/* TLBGP */
22428	/* TLBGP_MM */	22428	/* TLBGP_MM */
22429	/* TLBGR */	22429	/* TLBGR */
22430	/* TLBGR_MM */	22430	/* TLBGR_MM */
22431	/* TLBGWI */	22431	/* TLBGWI */
22432	/* TLBGWI_MM */	22432	/* TLBGWI_MM */
22433	/* TLBGWR */	22433	/* TLBGWR */
22434	/* TLBGWR_MM */	22434	/* TLBGWR_MM */
22435	/* TLBINV */	22435	/* TLBINV */
22436	/* TLBINVF */	22436	/* TLBINVF */
22437	/* TLBINVF_MMR6 */	22437	/* TLBINVF_MMR6 */
22438	/* TLBINV_MMR6 */	22438	/* TLBINV_MMR6 */
22439	/* TLBP */	22439	/* TLBP */
22440	/* TLBP_MM */	22440	/* TLBP_MM */
22441	/* TLBR */	22441	/* TLBR */
22442	/* TLBR_MM */	22442	/* TLBR_MM */
22443	/* TLBWI */	22443	/* TLBWI */
22444	/* TLBWI_MM */	22444	/* TLBWI_MM */
22445	/* TLBWR */	22445	/* TLBWR */
22446	/* TLBWR_MM */	22446	/* TLBWR_MM */
22447	/* TLT */	22447	/* TLT */
22448	GPR32Opnd, GPR32Opnd, uimm10,	22448	GPR32Opnd, GPR32Opnd, uimm10,
22449	/* TLTI */	22449	/* TLTI */
22450	GPR32Opnd, simm16,	22450	GPR32Opnd, simm16,
22451	/* TLTIU_MM */	22451	/* TLTIU_MM */
22452	GPR32Opnd, simm16,	22452	GPR32Opnd, simm16,
22453	/* TLTI_MM */	22453	/* TLTI_MM */
22454	GPR32Opnd, simm16,	22454	GPR32Opnd, simm16,
22455	/* TLTU */	22455	/* TLTU */
22456	GPR32Opnd, GPR32Opnd, uimm10,	22456	GPR32Opnd, GPR32Opnd, uimm10,
22457	/* TLTU_MM */	22457	/* TLTU_MM */
22458	GPR32Opnd, GPR32Opnd, uimm4,	22458	GPR32Opnd, GPR32Opnd, uimm4,
22459	/* TLT_MM */	22459	/* TLT_MM */
22460	GPR32Opnd, GPR32Opnd, uimm4,	22460	GPR32Opnd, GPR32Opnd, uimm4,
22461	/* TNE */	22461	/* TNE */
22462	GPR32Opnd, GPR32Opnd, uimm10,	22462	GPR32Opnd, GPR32Opnd, uimm10,
22463	/* TNEI */	22463	/* TNEI */
22464	GPR32Opnd, simm16,	22464	GPR32Opnd, simm16,
22465	/* TNEI_MM */	22465	/* TNEI_MM */
22466	GPR32Opnd, simm16,	22466	GPR32Opnd, simm16,
22467	/* TNE_MM */	22467	/* TNE_MM */
22468	GPR32Opnd, GPR32Opnd, uimm4,	22468	GPR32Opnd, GPR32Opnd, uimm4,
22469	/* TRUNC_L_D64 */	22469	/* TRUNC_L_D64 */
22470	FGR64Opnd, FGR64Opnd,	22470	FGR64Opnd, FGR64Opnd,
22471	/* TRUNC_L_D_MMR6 */	22471	/* TRUNC_L_D_MMR6 */
22472	FGR64Opnd, FGR64Opnd,	22472	FGR64Opnd, FGR64Opnd,
22473	/* TRUNC_L_S */	22473	/* TRUNC_L_S */
22474	FGR64Opnd, FGR32Opnd,	22474	FGR64Opnd, FGR32Opnd,
22475	/* TRUNC_L_S_MMR6 */	22475	/* TRUNC_L_S_MMR6 */
22476	FGR64Opnd, FGR32Opnd,	22476	FGR64Opnd, FGR32Opnd,
22477	/* TRUNC_W_D32 */	22477	/* TRUNC_W_D32 */
22478	FGR32Opnd, AFGR64Opnd,	22478	FGR32Opnd, AFGR64Opnd,
22479	/* TRUNC_W_D64 */	22479	/* TRUNC_W_D64 */
22480	FGR32Opnd, FGR64Opnd,	22480	FGR32Opnd, FGR64Opnd,
22481	/* TRUNC_W_D_MMR6 */	22481	/* TRUNC_W_D_MMR6 */
22482	FGR32Opnd, FGR64Opnd,	22482	FGR32Opnd, FGR64Opnd,
22483	/* TRUNC_W_MM */	22483	/* TRUNC_W_MM */
22484	FGR32Opnd, AFGR64Opnd,	22484	FGR32Opnd, AFGR64Opnd,
22485	/* TRUNC_W_S */	22485	/* TRUNC_W_S */
22486	FGR32Opnd, FGR32Opnd,	22486	FGR32Opnd, FGR32Opnd,
22487	/* TRUNC_W_S_MM */	22487	/* TRUNC_W_S_MM */
22488	FGR32Opnd, FGR32Opnd,	22488	FGR32Opnd, FGR32Opnd,
22489	/* TRUNC_W_S_MMR6 */	22489	/* TRUNC_W_S_MMR6 */
22490	FGR32Opnd, FGR32Opnd,	22490	FGR32Opnd, FGR32Opnd,
22491	/* TTLTIU */	22491	/* TTLTIU */
22492	GPR32Opnd, simm16,	22492	GPR32Opnd, simm16,
22493	/* UDIV */	22493	/* UDIV */
22494	GPR32Opnd, GPR32Opnd,	22494	GPR32Opnd, GPR32Opnd,
22495	/* UDIV_MM */	22495	/* UDIV_MM */
22496	GPR32Opnd, GPR32Opnd,	22496	GPR32Opnd, GPR32Opnd,
22497	/* V3MULU */	22497	/* V3MULU */
22498	GPR64Opnd, GPR64Opnd, GPR64Opnd,	22498	GPR64Opnd, GPR64Opnd, GPR64Opnd,
22499	/* VMM0 */	22499	/* VMM0 */
22500	GPR64Opnd, GPR64Opnd, GPR64Opnd,	22500	GPR64Opnd, GPR64Opnd, GPR64Opnd,
22501	/* VMULU */	22501	/* VMULU */
22502	GPR64Opnd, GPR64Opnd, GPR64Opnd,	22502	GPR64Opnd, GPR64Opnd, GPR64Opnd,
22503	/* VSHF_B */	22503	/* VSHF_B */
22504	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22504	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22505	/* VSHF_D */	22505	/* VSHF_D */
22506	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	22506	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22507	/* VSHF_H */	22507	/* VSHF_H */
22508	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	22508	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22509	/* VSHF_W */	22509	/* VSHF_W */
22510	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	22510	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22511	/* WAIT */	22511	/* WAIT */
22512	/* WAIT_MM */	22512	/* WAIT_MM */
22513	uimm10,	22513	uimm10,
22514	/* WAIT_MMR6 */	22514	/* WAIT_MMR6 */
22515	uimm10,	22515	uimm10,
22516	/* WRDSP */	22516	/* WRDSP */
22517	GPR32Opnd, uimm10,	22517	GPR32Opnd, uimm10,
22518	/* WRDSP_MM */	22518	/* WRDSP_MM */
22519	GPR32Opnd, uimm7,	22519	GPR32Opnd, uimm7,
22520	/* WRPGPR_MMR6 */	22520	/* WRPGPR_MMR6 */
22521	GPR32Opnd, GPR32Opnd,	22521	GPR32Opnd, GPR32Opnd,
22522	/* WSBH */	22522	/* WSBH */
22523	GPR32Opnd, GPR32Opnd,	22523	GPR32Opnd, GPR32Opnd,
22524	/* WSBH_MM */	22524	/* WSBH_MM */
22525	GPR32Opnd, GPR32Opnd,	22525	GPR32Opnd, GPR32Opnd,
22526	/* WSBH_MMR6 */	22526	/* WSBH_MMR6 */
22527	GPR32Opnd, GPR32Opnd,	22527	GPR32Opnd, GPR32Opnd,
22528	/* XOR */	22528	/* XOR */
22529	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22529	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22530	/* XOR16_MM */	22530	/* XOR16_MM */
22531	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	22531	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22532	/* XOR16_MMR6 */	22532	/* XOR16_MMR6 */
22533	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	22533	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22534	/* XOR64 */	22534	/* XOR64 */
22535	GPR64Opnd, GPR64Opnd, GPR64Opnd,	22535	GPR64Opnd, GPR64Opnd, GPR64Opnd,
22536	/* XORI_B */	22536	/* XORI_B */
22537	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	22537	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
22538	/* XORI_MMR6 */	22538	/* XORI_MMR6 */
22539	GPR32Opnd, GPR32Opnd, uimm16,	22539	GPR32Opnd, GPR32Opnd, uimm16,
22540	/* XOR_MM */	22540	/* XOR_MM */
22541	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22541	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22542	/* XOR_MMR6 */	22542	/* XOR_MMR6 */
22543	GPR32Opnd, GPR32Opnd, GPR32Opnd,	22543	GPR32Opnd, GPR32Opnd, GPR32Opnd,
22544	/* XOR_V */	22544	/* XOR_V */
22545	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	22545	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22546	/* XORi */	22546	/* XORi */
22547	GPR32Opnd, GPR32Opnd, uimm16,	22547	GPR32Opnd, GPR32Opnd, uimm16,
22548	/* XORi64 */	22548	/* XORi64 */
22549	GPR64Opnd, GPR64Opnd, uimm16_64,	22549	GPR64Opnd, GPR64Opnd, uimm16_64,
22550	/* XORi_MM */	22550	/* XORi_MM */
22551	GPR32Opnd, GPR32Opnd, uimm16,	22551	GPR32Opnd, GPR32Opnd, uimm16,
22552	/* XorRxRxRy16 */	22552	/* XorRxRxRy16 */
22553	CPU16Regs, CPU16Regs, CPU16Regs,	22553	CPU16Regs, CPU16Regs, CPU16Regs,
22554	/* YIELD */	22554	/* YIELD */
22555	GPR32Opnd, GPR32Opnd,	22555	GPR32Opnd, GPR32Opnd,
22556	};	22556	};
22557	return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];	22557	return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
22558	}	22558	}
22559	} // end namespace Mips	22559	} // end namespace Mips
22560	} // end namespace llvm	22560	} // end namespace llvm
22561	#endif // GET_INSTRINFO_OPERAND_TYPE	22561	#endif // GET_INSTRINFO_OPERAND_TYPE
22562		22562
22563	#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE	22563	#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
22564	#undef GET_INSTRINFO_MEM_OPERAND_SIZE	22564	#undef GET_INSTRINFO_MEM_OPERAND_SIZE
22565	namespace llvm {	22565	namespace llvm {
22566	namespace Mips {	22566	namespace Mips {
22567	LLVM_READONLY	22567	LLVM_READONLY
22568	static int getMemOperandSize(int OpType) {	22568	static int getMemOperandSize(int OpType) {
22569	switch (OpType) {	22569	switch (OpType) {
22570	default: return 0;	22570	default: return 0;
22571	}	22571	}
22572	}	22572	}
22573	} // end namespace Mips	22573	} // end namespace Mips
22574	} // end namespace llvm	22574	} // end namespace llvm
22575	#endif // GET_INSTRINFO_MEM_OPERAND_SIZE	22575	#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
22576		22576
22577	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	22577	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22578	#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	22578	#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22579	namespace llvm {	22579	namespace llvm {
22580	namespace Mips {	22580	namespace Mips {
22581	LLVM_READONLY static unsigned	22581	LLVM_READONLY static unsigned
22582	getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {	22582	getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
22583	return LogicalOpIdx;	22583	return LogicalOpIdx;
22584	}	22584	}
22585	LLVM_READONLY static inline unsigned	22585	LLVM_READONLY static inline unsigned
22586	getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {	22586	getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
22587	auto S = 0U;	22587	auto S = 0U;
22588	for (auto i = 0U; i < LogicalOpIdx; ++i)	22588	for (auto i = 0U; i < LogicalOpIdx; ++i)
22589	S += getLogicalOperandSize(Opcode, i);	22589	S += getLogicalOperandSize(Opcode, i);
22590	return S;	22590	return S;
22591	}	22591	}
22592	} // end namespace Mips	22592	} // end namespace Mips
22593	} // end namespace llvm	22593	} // end namespace llvm
22594	#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	22594	#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22595		22595
22596	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	22596	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22597	#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	22597	#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22598	namespace llvm {	22598	namespace llvm {
22599	namespace Mips {	22599	namespace Mips {
22600	LLVM_READONLY static int	22600	LLVM_READONLY static int
22601	getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {	22601	getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
22602	return -1;	22602	return -1;
22603	}	22603	}
22604	} // end namespace Mips	22604	} // end namespace Mips
22605	} // end namespace llvm	22605	} // end namespace llvm
22606	#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	22606	#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22607		22607
22608	#ifdef GET_INSTRINFO_MC_HELPER_DECLS	22608	#ifdef GET_INSTRINFO_MC_HELPER_DECLS
22609	#undef GET_INSTRINFO_MC_HELPER_DECLS	22609	#undef GET_INSTRINFO_MC_HELPER_DECLS
22610		22610
22611	namespace llvm {	22611	namespace llvm {
22612	class MCInst;	22612	class MCInst;
22613	class FeatureBitset;	22613	class FeatureBitset;
22614		22614
22615	namespace Mips_MC {	22615	namespace Mips_MC {
22616		22616
22617	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);	22617	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
22618		22618
22619	} // end namespace Mips_MC	22619	} // end namespace Mips_MC
22620	} // end namespace llvm	22620	} // end namespace llvm
22621		22621
22622	#endif // GET_INSTRINFO_MC_HELPER_DECLS	22622	#endif // GET_INSTRINFO_MC_HELPER_DECLS
22623		22623
22624	#ifdef GET_INSTRINFO_MC_HELPERS	22624	#ifdef GET_INSTRINFO_MC_HELPERS
22625	#undef GET_INSTRINFO_MC_HELPERS	22625	#undef GET_INSTRINFO_MC_HELPERS
22626		22626
22627	namespace llvm {	22627	namespace llvm {
22628	namespace Mips_MC {	22628	namespace Mips_MC {
22629		22629
22630	} // end namespace Mips_MC	22630	} // end namespace Mips_MC
22631	} // end namespace llvm	22631	} // end namespace llvm
22632		22632
22633	#endif // GET_GENISTRINFO_MC_HELPERS	22633	#endif // GET_GENISTRINFO_MC_HELPERS
22634		22634
22635	#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)	22635	#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)
22636	#define GET_COMPUTE_FEATURES	22636	#define GET_COMPUTE_FEATURES
22637	#endif	22637	#endif
22638	#ifdef GET_COMPUTE_FEATURES	22638	#ifdef GET_COMPUTE_FEATURES
22639	#undef GET_COMPUTE_FEATURES	22639	#undef GET_COMPUTE_FEATURES
22640	namespace llvm {	22640	namespace llvm {
22641	namespace Mips_MC {	22641	namespace Mips_MC {
22642		22642
22643	// Bits for subtarget features that participate in instruction matching.	22643	// Bits for subtarget features that participate in instruction matching.
22644	enum SubtargetFeatureBits : uint8_t {	22644	enum SubtargetFeatureBits : uint8_t {
22645	Feature_HasMips2Bit = 11,	22645	Feature_HasMips2Bit = 11,
22646	Feature_HasMips3_32Bit = 14,	22646	Feature_HasMips3_32Bit = 14,
22647	Feature_HasMips3_32r2Bit = 15,	22647	Feature_HasMips3_32r2Bit = 15,
22648	Feature_HasMips3Bit = 12,	22648	Feature_HasMips3Bit = 12,
22649	Feature_NotMips3Bit = 47,	22649	Feature_NotMips3Bit = 47,
22650	Feature_HasMips4_32Bit = 16,	22650	Feature_HasMips4_32Bit = 16,
22651	Feature_NotMips4_32Bit = 48,	22651	Feature_NotMips4_32Bit = 48,
22652	Feature_HasMips4_32r2Bit = 17,	22652	Feature_HasMips4_32r2Bit = 17,
22653	Feature_HasMips5_32r2Bit = 18,	22653	Feature_HasMips5_32r2Bit = 18,
22654	Feature_HasMips32Bit = 19,	22654	Feature_HasMips32Bit = 19,
22655	Feature_HasMips32r2Bit = 20,	22655	Feature_HasMips32r2Bit = 20,
22656	Feature_HasMips32r5Bit = 21,	22656	Feature_HasMips32r5Bit = 21,
22657	Feature_HasMips32r6Bit = 22,	22657	Feature_HasMips32r6Bit = 22,
22658	Feature_NotMips32r6Bit = 49,	22658	Feature_NotMips32r6Bit = 49,
22659	Feature_IsGP64bitBit = 33,	22659	Feature_IsGP64bitBit = 33,
22660	Feature_IsGP32bitBit = 32,	22660	Feature_IsGP32bitBit = 32,
22661	Feature_IsPTR64bitBit = 37,	22661	Feature_IsPTR64bitBit = 37,
22662	Feature_IsPTR32bitBit = 36,	22662	Feature_IsPTR32bitBit = 36,
22663	Feature_HasMips64Bit = 23,	22663	Feature_HasMips64Bit = 23,
22664	Feature_NotMips64Bit = 50,	22664	Feature_NotMips64Bit = 50,
22665	Feature_HasMips64r2Bit = 24,	22665	Feature_HasMips64r2Bit = 24,
22666	Feature_HasMips64r5Bit = 25,	22666	Feature_HasMips64r5Bit = 25,
22667	Feature_HasMips64r6Bit = 26,	22667	Feature_HasMips64r6Bit = 26,
22668	Feature_NotMips64r6Bit = 51,	22668	Feature_NotMips64r6Bit = 51,
22669	Feature_InMips16ModeBit = 30,	22669	Feature_InMips16ModeBit = 30,
22670	Feature_NotInMips16ModeBit = 46,	22670	Feature_NotInMips16ModeBit = 46,
22671	Feature_HasCnMipsBit = 1,	22671	Feature_HasCnMipsBit = 1,
22672	Feature_NotCnMipsBit = 42,	22672	Feature_NotCnMipsBit = 42,
22673	Feature_HasCnMipsPBit = 2,	22673	Feature_HasCnMipsPBit = 2,
22674	Feature_NotCnMipsPBit = 43,	22674	Feature_NotCnMipsPBit = 43,
22675	Feature_IsSym32Bit = 39,	22675	Feature_IsSym32Bit = 39,
22676	Feature_IsSym64Bit = 40,	22676	Feature_IsSym64Bit = 40,
22677	Feature_HasStdEncBit = 27,	22677	Feature_HasStdEncBit = 27,
22678	Feature_InMicroMipsBit = 29,	22678	Feature_InMicroMipsBit = 29,
22679	Feature_NotInMicroMipsBit = 45,	22679	Feature_NotInMicroMipsBit = 45,
22680	Feature_HasEVABit = 6,	22680	Feature_HasEVABit = 6,
22681	Feature_HasMSABit = 8,	22681	Feature_HasMSABit = 8,
22682	Feature_HasMadd4Bit = 10,	22682	Feature_HasMadd4Bit = 10,
22683	Feature_HasMTBit = 9,	22683	Feature_HasMTBit = 9,
22684	Feature_UseIndirectJumpsHazardBit = 52,	22684	Feature_UseIndirectJumpsHazardBit = 52,
22685	Feature_NoIndirectJumpGuardsBit = 41,	22685	Feature_NoIndirectJumpGuardsBit = 41,
22686	Feature_HasCRCBit = 0,	22686	Feature_HasCRCBit = 0,
22687	Feature_HasVirtBit = 28,	22687	Feature_HasVirtBit = 28,
22688	Feature_HasGINVBit = 7,	22688	Feature_HasGINVBit = 7,
22689	Feature_IsFP64bitBit = 31,	22689	Feature_IsFP64bitBit = 31,
22690	Feature_NotFP64bitBit = 44,	22690	Feature_NotFP64bitBit = 44,
22691	Feature_IsSingleFloatBit = 38,	22691	Feature_IsSingleFloatBit = 38,
22692	Feature_IsNotSingleFloatBit = 34,	22692	Feature_IsNotSingleFloatBit = 34,
22693	Feature_IsNotSoftFloatBit = 35,	22693	Feature_IsNotSoftFloatBit = 35,
22694	Feature_HasMips3DBit = 13,	22694	Feature_HasMips3DBit = 13,
22695	Feature_HasDSPBit = 3,	22695	Feature_HasDSPBit = 3,
22696	Feature_HasDSPR2Bit = 4,	22696	Feature_HasDSPR2Bit = 4,
22697	Feature_HasDSPR3Bit = 5,	22697	Feature_HasDSPR3Bit = 5,
22698	};	22698	};
22699		22699
22700	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {	22700	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
22701	FeatureBitset Features;	22701	FeatureBitset Features;
22702	if (FB[Mips::FeatureMips2])	22702	if (FB[Mips::FeatureMips2])
22703	Features.set(Feature_HasMips2Bit);	22703	Features.set(Feature_HasMips2Bit);
22704	if (FB[Mips::FeatureMips3_32])	22704	if (FB[Mips::FeatureMips3_32])
22705	Features.set(Feature_HasMips3_32Bit);	22705	Features.set(Feature_HasMips3_32Bit);
22706	if (FB[Mips::FeatureMips3_32r2])	22706	if (FB[Mips::FeatureMips3_32r2])
22707	Features.set(Feature_HasMips3_32r2Bit);	22707	Features.set(Feature_HasMips3_32r2Bit);
22708	if (FB[Mips::FeatureMips3])	22708	if (FB[Mips::FeatureMips3])
22709	Features.set(Feature_HasMips3Bit);	22709	Features.set(Feature_HasMips3Bit);
22710	if (!FB[Mips::FeatureMips3])	22710	if (!FB[Mips::FeatureMips3])
22711	Features.set(Feature_NotMips3Bit);	22711	Features.set(Feature_NotMips3Bit);
22712	if (FB[Mips::FeatureMips4_32])	22712	if (FB[Mips::FeatureMips4_32])
22713	Features.set(Feature_HasMips4_32Bit);	22713	Features.set(Feature_HasMips4_32Bit);
22714	if (!FB[Mips::FeatureMips4_32])	22714	if (!FB[Mips::FeatureMips4_32])
22715	Features.set(Feature_NotMips4_32Bit);	22715	Features.set(Feature_NotMips4_32Bit);
22716	if (FB[Mips::FeatureMips4_32r2])	22716	if (FB[Mips::FeatureMips4_32r2])
22717	Features.set(Feature_HasMips4_32r2Bit);	22717	Features.set(Feature_HasMips4_32r2Bit);
22718	if (FB[Mips::FeatureMips5_32r2])	22718	if (FB[Mips::FeatureMips5_32r2])
22719	Features.set(Feature_HasMips5_32r2Bit);	22719	Features.set(Feature_HasMips5_32r2Bit);
22720	if (FB[Mips::FeatureMips32])	22720	if (FB[Mips::FeatureMips32])
22721	Features.set(Feature_HasMips32Bit);	22721	Features.set(Feature_HasMips32Bit);
22722	if (FB[Mips::FeatureMips32r2])	22722	if (FB[Mips::FeatureMips32r2])
22723	Features.set(Feature_HasMips32r2Bit);	22723	Features.set(Feature_HasMips32r2Bit);
22724	if (FB[Mips::FeatureMips32r5])	22724	if (FB[Mips::FeatureMips32r5])
22725	Features.set(Feature_HasMips32r5Bit);	22725	Features.set(Feature_HasMips32r5Bit);
22726	if (FB[Mips::FeatureMips32r6])	22726	if (FB[Mips::FeatureMips32r6])
22727	Features.set(Feature_HasMips32r6Bit);	22727	Features.set(Feature_HasMips32r6Bit);
22728	if (!FB[Mips::FeatureMips32r6])	22728	if (!FB[Mips::FeatureMips32r6])
22729	Features.set(Feature_NotMips32r6Bit);	22729	Features.set(Feature_NotMips32r6Bit);
22730	if (FB[Mips::FeatureGP64Bit])	22730	if (FB[Mips::FeatureGP64Bit])
22731	Features.set(Feature_IsGP64bitBit);	22731	Features.set(Feature_IsGP64bitBit);
22732	if (!FB[Mips::FeatureGP64Bit])	22732	if (!FB[Mips::FeatureGP64Bit])
22733	Features.set(Feature_IsGP32bitBit);	22733	Features.set(Feature_IsGP32bitBit);
22734	if (FB[Mips::FeaturePTR64Bit])	22734	if (FB[Mips::FeaturePTR64Bit])
22735	Features.set(Feature_IsPTR64bitBit);	22735	Features.set(Feature_IsPTR64bitBit);
22736	if (!FB[Mips::FeaturePTR64Bit])	22736	if (!FB[Mips::FeaturePTR64Bit])
22737	Features.set(Feature_IsPTR32bitBit);	22737	Features.set(Feature_IsPTR32bitBit);
22738	if (FB[Mips::FeatureMips64])	22738	if (FB[Mips::FeatureMips64])
22739	Features.set(Feature_HasMips64Bit);	22739	Features.set(Feature_HasMips64Bit);
22740	if (!FB[Mips::FeatureMips64])	22740	if (!FB[Mips::FeatureMips64])
22741	Features.set(Feature_NotMips64Bit);	22741	Features.set(Feature_NotMips64Bit);
22742	if (FB[Mips::FeatureMips64r2])	22742	if (FB[Mips::FeatureMips64r2])
22743	Features.set(Feature_HasMips64r2Bit);	22743	Features.set(Feature_HasMips64r2Bit);
22744	if (FB[Mips::FeatureMips64r5])	22744	if (FB[Mips::FeatureMips64r5])
22745	Features.set(Feature_HasMips64r5Bit);	22745	Features.set(Feature_HasMips64r5Bit);
22746	if (FB[Mips::FeatureMips64r6])	22746	if (FB[Mips::FeatureMips64r6])
22747	Features.set(Feature_HasMips64r6Bit);	22747	Features.set(Feature_HasMips64r6Bit);
22748	if (!FB[Mips::FeatureMips64r6])	22748	if (!FB[Mips::FeatureMips64r6])
22749	Features.set(Feature_NotMips64r6Bit);	22749	Features.set(Feature_NotMips64r6Bit);
22750	if (FB[Mips::FeatureMips16])	22750	if (FB[Mips::FeatureMips16])
22751	Features.set(Feature_InMips16ModeBit);	22751	Features.set(Feature_InMips16ModeBit);
22752	if (!FB[Mips::FeatureMips16])	22752	if (!FB[Mips::FeatureMips16])
22753	Features.set(Feature_NotInMips16ModeBit);	22753	Features.set(Feature_NotInMips16ModeBit);
22754	if (FB[Mips::FeatureCnMips])	22754	if (FB[Mips::FeatureCnMips])
22755	Features.set(Feature_HasCnMipsBit);	22755	Features.set(Feature_HasCnMipsBit);
22756	if (!FB[Mips::FeatureCnMips])	22756	if (!FB[Mips::FeatureCnMips])
22757	Features.set(Feature_NotCnMipsBit);	22757	Features.set(Feature_NotCnMipsBit);
22758	if (FB[Mips::FeatureCnMipsP])	22758	if (FB[Mips::FeatureCnMipsP])
22759	Features.set(Feature_HasCnMipsPBit);	22759	Features.set(Feature_HasCnMipsPBit);
22760	if (!FB[Mips::FeatureCnMipsP])	22760	if (!FB[Mips::FeatureCnMipsP])
22761	Features.set(Feature_NotCnMipsPBit);	22761	Features.set(Feature_NotCnMipsPBit);
22762	if (FB[Mips::FeatureSym32])	22762	if (FB[Mips::FeatureSym32])
22763	Features.set(Feature_IsSym32Bit);	22763	Features.set(Feature_IsSym32Bit);
22764	if (!FB[Mips::FeatureSym32])	22764	if (!FB[Mips::FeatureSym32])
22765	Features.set(Feature_IsSym64Bit);	22765	Features.set(Feature_IsSym64Bit);
22766	if (!FB[Mips::FeatureMips16])	22766	if (!FB[Mips::FeatureMips16])
22767	Features.set(Feature_HasStdEncBit);	22767	Features.set(Feature_HasStdEncBit);
22768	if (FB[Mips::FeatureMicroMips])	22768	if (FB[Mips::FeatureMicroMips])
22769	Features.set(Feature_InMicroMipsBit);	22769	Features.set(Feature_InMicroMipsBit);
22770	if (!FB[Mips::FeatureMicroMips])	22770	if (!FB[Mips::FeatureMicroMips])
22771	Features.set(Feature_NotInMicroMipsBit);	22771	Features.set(Feature_NotInMicroMipsBit);
22772	if (FB[Mips::FeatureEVA])	22772	if (FB[Mips::FeatureEVA])
22773	Features.set(Feature_HasEVABit);	22773	Features.set(Feature_HasEVABit);
22774	if (FB[Mips::FeatureMSA])	22774	if (FB[Mips::FeatureMSA])
22775	Features.set(Feature_HasMSABit);	22775	Features.set(Feature_HasMSABit);
22776	if (!FB[Mips::FeatureNoMadd4])	22776	if (!FB[Mips::FeatureNoMadd4])
22777	Features.set(Feature_HasMadd4Bit);	22777	Features.set(Feature_HasMadd4Bit);
22778	if (FB[Mips::FeatureMT])	22778	if (FB[Mips::FeatureMT])
22779	Features.set(Feature_HasMTBit);	22779	Features.set(Feature_HasMTBit);
22780	if (FB[Mips::FeatureUseIndirectJumpsHazard])	22780	if (FB[Mips::FeatureUseIndirectJumpsHazard])
22781	Features.set(Feature_UseIndirectJumpsHazardBit);	22781	Features.set(Feature_UseIndirectJumpsHazardBit);
22782	if (!FB[Mips::FeatureUseIndirectJumpsHazard])	22782	if (!FB[Mips::FeatureUseIndirectJumpsHazard])
22783	Features.set(Feature_NoIndirectJumpGuardsBit);	22783	Features.set(Feature_NoIndirectJumpGuardsBit);
22784	if (FB[Mips::FeatureCRC])	22784	if (FB[Mips::FeatureCRC])
22785	Features.set(Feature_HasCRCBit);	22785	Features.set(Feature_HasCRCBit);
22786	if (FB[Mips::FeatureVirt])	22786	if (FB[Mips::FeatureVirt])
22787	Features.set(Feature_HasVirtBit);	22787	Features.set(Feature_HasVirtBit);
22788	if (FB[Mips::FeatureGINV])	22788	if (FB[Mips::FeatureGINV])
22789	Features.set(Feature_HasGINVBit);	22789	Features.set(Feature_HasGINVBit);
22790	if (FB[Mips::FeatureFP64Bit])	22790	if (FB[Mips::FeatureFP64Bit])
22791	Features.set(Feature_IsFP64bitBit);	22791	Features.set(Feature_IsFP64bitBit);
22792	if (!FB[Mips::FeatureFP64Bit])	22792	if (!FB[Mips::FeatureFP64Bit])
22793	Features.set(Feature_NotFP64bitBit);	22793	Features.set(Feature_NotFP64bitBit);
22794	if (FB[Mips::FeatureSingleFloat])	22794	if (FB[Mips::FeatureSingleFloat])
22795	Features.set(Feature_IsSingleFloatBit);	22795	Features.set(Feature_IsSingleFloatBit);
22796	if (!FB[Mips::FeatureSingleFloat])	22796	if (!FB[Mips::FeatureSingleFloat])
22797	Features.set(Feature_IsNotSingleFloatBit);	22797	Features.set(Feature_IsNotSingleFloatBit);
22798	if (!FB[Mips::FeatureSoftFloat])	22798	if (!FB[Mips::FeatureSoftFloat])
22799	Features.set(Feature_IsNotSoftFloatBit);	22799	Features.set(Feature_IsNotSoftFloatBit);
22800	if (FB[Mips::FeatureMips3D])	22800	if (FB[Mips::FeatureMips3D])
22801	Features.set(Feature_HasMips3DBit);	22801	Features.set(Feature_HasMips3DBit);
22802	if (FB[Mips::FeatureDSP])	22802	if (FB[Mips::FeatureDSP])
22803	Features.set(Feature_HasDSPBit);	22803	Features.set(Feature_HasDSPBit);
22804	if (FB[Mips::FeatureDSPR2])	22804	if (FB[Mips::FeatureDSPR2])
22805	Features.set(Feature_HasDSPR2Bit);	22805	Features.set(Feature_HasDSPR2Bit);
22806	if (FB[Mips::FeatureDSPR3])	22806	if (FB[Mips::FeatureDSPR3])
22807	Features.set(Feature_HasDSPR3Bit);	22807	Features.set(Feature_HasDSPR3Bit);
22808	return Features;	22808	return Features;
22809	}	22809	}
22810		22810
22811	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {	22811	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
22812	enum : uint8_t {	22812	enum : uint8_t {
22813	CEFBS_None,	22813	CEFBS_None,
22814	CEFBS_HasCnMips,	22814	CEFBS_HasCnMips,
22815	CEFBS_HasCnMipsP,	22815	CEFBS_HasCnMipsP,
22816	CEFBS_HasDSP,	22816	CEFBS_HasDSP,
22817	CEFBS_HasDSPR2,	22817	CEFBS_HasDSPR2,
22818	CEFBS_HasMSA,	22818	CEFBS_HasMSA,
22819	CEFBS_HasMT,	22819	CEFBS_HasMT,
22820	CEFBS_InMicroMips,	22820	CEFBS_InMicroMips,
22821	CEFBS_InMips16Mode,	22821	CEFBS_InMips16Mode,
22822	CEFBS_IsGP32bit,	22822	CEFBS_IsGP32bit,
22823	CEFBS_IsGP64bit,	22823	CEFBS_IsGP64bit,
22824	CEFBS_IsNotSoftFloat,	22824	CEFBS_IsNotSoftFloat,
22825	CEFBS_NotCnMips,	22825	CEFBS_NotCnMips,
22826	CEFBS_NotInMips16Mode,	22826	CEFBS_NotInMips16Mode,
22827	CEFBS_HasDSP_NotInMicroMips,	22827	CEFBS_HasDSP_NotInMicroMips,
22828	CEFBS_HasStdEnc_HasMSA,	22828	CEFBS_HasStdEnc_HasMSA,
22829	CEFBS_HasStdEnc_HasMips32,	22829	CEFBS_HasStdEnc_HasMips32,
22830	CEFBS_HasStdEnc_HasMips32r6,	22830	CEFBS_HasStdEnc_HasMips32r6,
22831	CEFBS_HasStdEnc_HasMips64,	22831	CEFBS_HasStdEnc_HasMips64,
22832	CEFBS_HasStdEnc_HasMips64r6,	22832	CEFBS_HasStdEnc_HasMips64r6,
22833	CEFBS_HasStdEnc_IsNotSoftFloat,	22833	CEFBS_HasStdEnc_IsNotSoftFloat,
22834	CEFBS_HasStdEnc_NotInMicroMips,	22834	CEFBS_HasStdEnc_NotInMicroMips,
22835	CEFBS_HasStdEnc_NotMips3,	22835	CEFBS_HasStdEnc_NotMips3,
22836	CEFBS_HasStdEnc_NotMips4_32,	22836	CEFBS_HasStdEnc_NotMips4_32,
22837	CEFBS_InMicroMips_HasDSP,	22837	CEFBS_InMicroMips_HasDSP,
22838	CEFBS_InMicroMips_HasDSPR2,	22838	CEFBS_InMicroMips_HasDSPR2,
22839	CEFBS_InMicroMips_HasDSPR3,	22839	CEFBS_InMicroMips_HasDSPR3,
22840	CEFBS_InMicroMips_HasEVA,	22840	CEFBS_InMicroMips_HasEVA,
22841	CEFBS_InMicroMips_HasMips32r6,	22841	CEFBS_InMicroMips_HasMips32r6,
22842	CEFBS_InMicroMips_IsNotSoftFloat,	22842	CEFBS_InMicroMips_IsNotSoftFloat,
22843	CEFBS_InMicroMips_NotMips32r6,	22843	CEFBS_InMicroMips_NotMips32r6,
22844	CEFBS_IsFP64bit_IsNotSoftFloat,	22844	CEFBS_IsFP64bit_IsNotSoftFloat,
22845	CEFBS_IsGP32bit_NotInMicroMips,	22845	CEFBS_IsGP32bit_NotInMicroMips,
22846	CEFBS_NotFP64bit_IsNotSoftFloat,	22846	CEFBS_NotFP64bit_IsNotSoftFloat,
22847	CEFBS_NotInMips16Mode_HasDSP,	22847	CEFBS_NotInMips16Mode_HasDSP,
22848	CEFBS_NotInMips16Mode_IsGP64bit,	22848	CEFBS_NotInMips16Mode_IsGP64bit,
22849	CEFBS_NotInMips16Mode_IsNotSoftFloat,	22849	CEFBS_NotInMips16Mode_IsNotSoftFloat,
22850	CEFBS_NotInMips16Mode_IsPTR64bit,	22850	CEFBS_NotInMips16Mode_IsPTR64bit,
22851	CEFBS_HasMips3_NotMips64r6_NotCnMips,	22851	CEFBS_HasMips3_NotMips64r6_NotCnMips,
22852	CEFBS_HasMips64_HasCnMips_NotInMicroMips,	22852	CEFBS_HasMips64_HasCnMips_NotInMicroMips,
22853	CEFBS_HasStdEnc_HasMSA_HasMips64,	22853	CEFBS_HasStdEnc_HasMSA_HasMips64,
22854	CEFBS_HasStdEnc_HasMT_NotInMicroMips,	22854	CEFBS_HasStdEnc_HasMT_NotInMicroMips,
22855	CEFBS_HasStdEnc_HasMips2_NotInMicroMips,	22855	CEFBS_HasStdEnc_HasMips2_NotInMicroMips,
22856	CEFBS_HasStdEnc_HasMips3_NotInMicroMips,	22856	CEFBS_HasStdEnc_HasMips3_NotInMicroMips,
22857	CEFBS_HasStdEnc_HasMips32_NotInMicroMips,	22857	CEFBS_HasStdEnc_HasMips32_NotInMicroMips,
22858	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,	22858	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
22859	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,	22859	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
22860	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,	22860	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
22861	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,	22861	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
22862	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,	22862	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
22863	CEFBS_HasStdEnc_HasMips64r5_HasVirt,	22863	CEFBS_HasStdEnc_HasMips64r5_HasVirt,
22864	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,	22864	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
22865	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,	22865	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,
22866	CEFBS_HasStdEnc_IsGP64bit_HasMips3,	22866	CEFBS_HasStdEnc_IsGP64bit_HasMips3,
22867	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,	22867	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,
22868	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,	22868	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,
22869	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,	22869	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,
22870	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,	22870	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22871	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,	22871	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,
22872	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,	22872	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,
22873	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,	22873	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
22874	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,	22874	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,
22875	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,	22875	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,
22876	CEFBS_InMicroMips_HasMips32r5_HasVirt,	22876	CEFBS_InMicroMips_HasMips32r5_HasVirt,
22877	CEFBS_InMicroMips_HasMips32r6_HasGINV,	22877	CEFBS_InMicroMips_HasMips32r6_HasGINV,
22878	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,	22878	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
22879	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,	22879	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22880	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,	22880	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,
22881	CEFBS_InMicroMips_NotMips32r6_HasDSP,	22881	CEFBS_InMicroMips_NotMips32r6_HasDSP,
22882	CEFBS_InMicroMips_NotMips32r6_HasEVA,	22882	CEFBS_InMicroMips_NotMips32r6_HasEVA,
22883	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,	22883	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
22884	CEFBS_InMicroMips_NotMips32r6_NotMips64r6,	22884	CEFBS_InMicroMips_NotMips32r6_NotMips64r6,
22885	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,	22885	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,
22886	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,	22886	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,
22887	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,	22887	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,
22888	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,	22888	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
22889	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,	22889	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,
22890	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,	22890	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,
22891	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22891	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22892	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,	22892	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
22893	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,	22893	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,
22894	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,	22894	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
22895	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,	22895	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,
22896	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,	22896	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
22897	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,	22897	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
22898	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,	22898	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
22899	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,	22899	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
22900	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,	22900	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
22901	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,	22901	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
22902	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,	22902	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
22903	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,	22903	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
22904	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	22904	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
22905	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	22905	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
22906	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,	22906	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
22907	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,	22907	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
22908	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,	22908	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22909	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,	22909	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
22910	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,	22910	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
22911	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,	22911	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
22912	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,	22912	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,
22913	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,	22913	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
22914	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,	22914	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,
22915	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,	22915	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,
22916	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,	22916	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,
22917	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,	22917	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
22918	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	22918	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
22919	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,	22919	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
22920	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,	22920	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
22921	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	22921	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
22922	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22922	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22923	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,	22923	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
22924	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	22924	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
22925	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	22925	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
22926	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	22926	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
22927	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22927	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22928	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	22928	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
22929	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	22929	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
22930	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,	22930	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
22931	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	22931	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
22932	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	22932	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
22933	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,	22933	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,
22934	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,	22934	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
22935	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	22935	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
22936	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	22936	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
22937	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	22937	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
22938	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22938	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22939	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,	22939	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,
22940	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,	22940	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,
22941	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22941	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,	22942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
22943	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22943	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22944	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	22944	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
22945	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22945	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22946	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	22946	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
22947	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	22947	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
22948	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	22948	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
22949	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22949	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22950	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	22950	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
22951	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	22951	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
22952	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22952	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22953	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22953	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22954	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	22954	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
22955	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	22955	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
22956	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,	22956	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
22957	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22957	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22958	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22958	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22959	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22959	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22960	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22960	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22961	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22961	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22962	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22962	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22963	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22963	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22964	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	22964	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
22965	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	22965	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
22966	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	22966	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
22967	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	22967	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
22968	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	22968	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
22969	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	22969	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
22970	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	22970	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
22971	};	22971	};
22972		22972
22973	static constexpr FeatureBitset FeatureBitsets[] = {	22973	static constexpr FeatureBitset FeatureBitsets[] = {
22974	{}, // CEFBS_None	22974	{}, // CEFBS_None
22975	{Feature_HasCnMipsBit, },	22975	{Feature_HasCnMipsBit, },
22976	{Feature_HasCnMipsPBit, },	22976	{Feature_HasCnMipsPBit, },
22977	{Feature_HasDSPBit, },	22977	{Feature_HasDSPBit, },
22978	{Feature_HasDSPR2Bit, },	22978	{Feature_HasDSPR2Bit, },
22979	{Feature_HasMSABit, },	22979	{Feature_HasMSABit, },
22980	{Feature_HasMTBit, },	22980	{Feature_HasMTBit, },
22981	{Feature_InMicroMipsBit, },	22981	{Feature_InMicroMipsBit, },
22982	{Feature_InMips16ModeBit, },	22982	{Feature_InMips16ModeBit, },
22983	{Feature_IsGP32bitBit, },	22983	{Feature_IsGP32bitBit, },
22984	{Feature_IsGP64bitBit, },	22984	{Feature_IsGP64bitBit, },
22985	{Feature_IsNotSoftFloatBit, },	22985	{Feature_IsNotSoftFloatBit, },
22986	{Feature_NotCnMipsBit, },	22986	{Feature_NotCnMipsBit, },
22987	{Feature_NotInMips16ModeBit, },	22987	{Feature_NotInMips16ModeBit, },
22988	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },	22988	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
22989	{Feature_HasStdEncBit, Feature_HasMSABit, },	22989	{Feature_HasStdEncBit, Feature_HasMSABit, },
22990	{Feature_HasStdEncBit, Feature_HasMips32Bit, },	22990	{Feature_HasStdEncBit, Feature_HasMips32Bit, },
22991	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, },	22991	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, },
22992	{Feature_HasStdEncBit, Feature_HasMips64Bit, },	22992	{Feature_HasStdEncBit, Feature_HasMips64Bit, },
22993	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, },	22993	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, },
22994	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },	22994	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
22995	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },	22995	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
22996	{Feature_HasStdEncBit, Feature_NotMips3Bit, },	22996	{Feature_HasStdEncBit, Feature_NotMips3Bit, },
22997	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },	22997	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
22998	{Feature_InMicroMipsBit, Feature_HasDSPBit, },	22998	{Feature_InMicroMipsBit, Feature_HasDSPBit, },
22999	{Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },	22999	{Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },
23000	{Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },	23000	{Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },
23001	{Feature_InMicroMipsBit, Feature_HasEVABit, },	23001	{Feature_InMicroMipsBit, Feature_HasEVABit, },
23002	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },	23002	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },
23003	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },	23003	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
23004	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },	23004	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
23005	{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	23005	{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23006	{Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },	23006	{Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },
23007	{Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	23007	{Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23008	{Feature_NotInMips16ModeBit, Feature_HasDSPBit, },	23008	{Feature_NotInMips16ModeBit, Feature_HasDSPBit, },
23009	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },	23009	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },
23010	{Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },	23010	{Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },
23011	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },	23011	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },
23012	{Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },	23012	{Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },
23013	{Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },	23013	{Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },
23014	{Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },	23014	{Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },
23015	{Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },	23015	{Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },
23016	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },	23016	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },
23017	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },	23017	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },
23018	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },	23018	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },
23019	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },	23019	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },
23020	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },	23020	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },
23021	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	23021	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23022	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },	23022	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },
23023	{Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },	23023	{Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },
23024	{Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },	23024	{Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },
23025	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	23025	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
23026	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },	23026	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
23027	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },	23027	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },
23028	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },	23028	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },
23029	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },	23029	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },
23030	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },	23030	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },
23031	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23031	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23032	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	23032	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23033	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },	23033	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
23034	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23034	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23035	{Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },	23035	{Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },
23036	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23036	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23037	{Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },	23037	{Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },
23038	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },	23038	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },
23039	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	23039	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
23040	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	23040	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23041	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	23041	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23042	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },	23042	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },
23043	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },	23043	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },
23044	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	23044	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23045	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23045	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23046	{Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	23046	{Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23047	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },	23047	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
23048	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },	23048	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },
23049	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },	23049	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },
23050	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },	23050	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },
23051	{Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	23051	{Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23052	{Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23052	{Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23053	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23053	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23054	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	23054	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
23055	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23055	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23056	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23056	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23057	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23057	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23058	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23058	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23059	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	23059	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
23060	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	23060	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23061	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },	23061	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },
23062	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	23062	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
23063	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },	23063	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },
23064	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23064	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23065	{Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23065	{Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23066	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23066	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23067	{Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23067	{Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23068	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	23068	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
23069	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23069	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23070	{Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	23070	{Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23071	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	23071	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23072	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	23072	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
23073	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23073	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23074	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23074	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23075	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	23075	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
23076	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	23076	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23077	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	23077	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23078	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	23078	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
23079	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23079	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23080	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23080	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23081	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23081	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23082	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23082	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23083	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23083	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23084	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23084	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23085	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23085	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23086	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	23086	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23087	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23087	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23088	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23088	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23089	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23089	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23090	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23090	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23091	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23091	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23092	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23092	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23093	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23093	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23094	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	23094	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23095	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23095	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23096	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23096	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23097	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23097	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23098	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23098	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23099	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23099	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23100	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	23100	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
23101	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	23101	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
23102	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23102	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23103	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	23103	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
23104	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23104	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23105	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	23105	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23106	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23106	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23107	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23107	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23108	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23108	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23109	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	23109	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23110	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23110	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23111	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23111	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23112	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23112	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23113	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23113	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23114	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23114	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23115	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	23115	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23116	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	23116	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23117	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },	23117	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },
23118	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23118	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23119	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23119	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23120	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23120	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23121	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23121	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23122	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23122	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23123	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23123	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23124	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23124	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23125	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	23125	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23126	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	23126	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23127	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	23127	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23128	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	23128	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23129	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	23129	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23130	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	23130	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23131	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	23131	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23132	};	23132	};
23133	static uint8_t RequiredFeaturesRefs[] = {	23133	static uint8_t RequiredFeaturesRefs[] = {
23134	CEFBS_None, // PHI = 0	23134	CEFBS_None, // PHI = 0
23135	CEFBS_None, // INLINEASM = 1	23135	CEFBS_None, // INLINEASM = 1
23136	CEFBS_None, // INLINEASM_BR = 2	23136	CEFBS_None, // INLINEASM_BR = 2
23137	CEFBS_None, // CFI_INSTRUCTION = 3	23137	CEFBS_None, // CFI_INSTRUCTION = 3
23138	CEFBS_None, // EH_LABEL = 4	23138	CEFBS_None, // EH_LABEL = 4
23139	CEFBS_None, // GC_LABEL = 5	23139	CEFBS_None, // GC_LABEL = 5
23140	CEFBS_None, // ANNOTATION_LABEL = 6	23140	CEFBS_None, // ANNOTATION_LABEL = 6
23141	CEFBS_None, // KILL = 7	23141	CEFBS_None, // KILL = 7
23142	CEFBS_None, // EXTRACT_SUBREG = 8	23142	CEFBS_None, // EXTRACT_SUBREG = 8
23143	CEFBS_None, // INSERT_SUBREG = 9	23143	CEFBS_None, // INSERT_SUBREG = 9
23144	CEFBS_None, // IMPLICIT_DEF = 10	23144	CEFBS_None, // IMPLICIT_DEF = 10
23145	CEFBS_None, // SUBREG_TO_REG = 11	23145	CEFBS_None, // SUBREG_TO_REG = 11
23146	CEFBS_None, // COPY_TO_REGCLASS = 12	23146	CEFBS_None, // COPY_TO_REGCLASS = 12
23147	CEFBS_None, // DBG_VALUE = 13	23147	CEFBS_None, // DBG_VALUE = 13
23148	CEFBS_None, // DBG_VALUE_LIST = 14	23148	CEFBS_None, // DBG_VALUE_LIST = 14
23149	CEFBS_None, // DBG_INSTR_REF = 15	23149	CEFBS_None, // DBG_INSTR_REF = 15
23150	CEFBS_None, // DBG_PHI = 16	23150	CEFBS_None, // DBG_PHI = 16
23151	CEFBS_None, // DBG_LABEL = 17	23151	CEFBS_None, // DBG_LABEL = 17
23152	CEFBS_None, // REG_SEQUENCE = 18	23152	CEFBS_None, // REG_SEQUENCE = 18
23153	CEFBS_None, // COPY = 19	23153	CEFBS_None, // COPY = 19
23154	CEFBS_None, // BUNDLE = 20	23154	CEFBS_None, // BUNDLE = 20
23155	CEFBS_None, // LIFETIME_START = 21	23155	CEFBS_None, // LIFETIME_START = 21
23156	CEFBS_None, // LIFETIME_END = 22	23156	CEFBS_None, // LIFETIME_END = 22
23157	CEFBS_None, // PSEUDO_PROBE = 23	23157	CEFBS_None, // PSEUDO_PROBE = 23
23158	CEFBS_None, // ARITH_FENCE = 24	23158	CEFBS_None, // ARITH_FENCE = 24
23159	CEFBS_None, // STACKMAP = 25	23159	CEFBS_None, // STACKMAP = 25
23160	CEFBS_None, // FENTRY_CALL = 26	23160	CEFBS_None, // FENTRY_CALL = 26
23161	CEFBS_None, // PATCHPOINT = 27	23161	CEFBS_None, // PATCHPOINT = 27
23162	CEFBS_None, // LOAD_STACK_GUARD = 28	23162	CEFBS_None, // LOAD_STACK_GUARD = 28
23163	CEFBS_None, // PREALLOCATED_SETUP = 29	23163	CEFBS_None, // PREALLOCATED_SETUP = 29
23164	CEFBS_None, // PREALLOCATED_ARG = 30	23164	CEFBS_None, // PREALLOCATED_ARG = 30
23165	CEFBS_None, // STATEPOINT = 31	23165	CEFBS_None, // STATEPOINT = 31
23166	CEFBS_None, // LOCAL_ESCAPE = 32	23166	CEFBS_None, // LOCAL_ESCAPE = 32
23167	CEFBS_None, // FAULTING_OP = 33	23167	CEFBS_None, // FAULTING_OP = 33
23168	CEFBS_None, // PATCHABLE_OP = 34	23168	CEFBS_None, // PATCHABLE_OP = 34
23169	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35	23169	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
23170	CEFBS_None, // PATCHABLE_RET = 36	23170	CEFBS_None, // PATCHABLE_RET = 36
23171	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37	23171	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
23172	CEFBS_None, // PATCHABLE_TAIL_CALL = 38	23172	CEFBS_None, // PATCHABLE_TAIL_CALL = 38
23173	CEFBS_None, // PATCHABLE_EVENT_CALL = 39	23173	CEFBS_None, // PATCHABLE_EVENT_CALL = 39
23174	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40	23174	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
23175	CEFBS_None, // ICALL_BRANCH_FUNNEL = 41	23175	CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
23176	CEFBS_None, // MEMBARRIER = 42	23176	CEFBS_None, // MEMBARRIER = 42
23177	CEFBS_None, // G_ASSERT_SEXT = 43	23177	CEFBS_None, // G_ASSERT_SEXT = 43
23178	CEFBS_None, // G_ASSERT_ZEXT = 44	23178	CEFBS_None, // G_ASSERT_ZEXT = 44
23179	CEFBS_None, // G_ASSERT_ALIGN = 45	23179	CEFBS_None, // G_ASSERT_ALIGN = 45
23180	CEFBS_None, // G_ADD = 46	23180	CEFBS_None, // G_ADD = 46
23181	CEFBS_None, // G_SUB = 47	23181	CEFBS_None, // G_SUB = 47
23182	CEFBS_None, // G_MUL = 48	23182	CEFBS_None, // G_MUL = 48
23183	CEFBS_None, // G_SDIV = 49	23183	CEFBS_None, // G_SDIV = 49
23184	CEFBS_None, // G_UDIV = 50	23184	CEFBS_None, // G_UDIV = 50
23185	CEFBS_None, // G_SREM = 51	23185	CEFBS_None, // G_SREM = 51
23186	CEFBS_None, // G_UREM = 52	23186	CEFBS_None, // G_UREM = 52
23187	CEFBS_None, // G_SDIVREM = 53	23187	CEFBS_None, // G_SDIVREM = 53
23188	CEFBS_None, // G_UDIVREM = 54	23188	CEFBS_None, // G_UDIVREM = 54
23189	CEFBS_None, // G_AND = 55	23189	CEFBS_None, // G_AND = 55
23190	CEFBS_None, // G_OR = 56	23190	CEFBS_None, // G_OR = 56
23191	CEFBS_None, // G_XOR = 57	23191	CEFBS_None, // G_XOR = 57
23192	CEFBS_None, // G_IMPLICIT_DEF = 58	23192	CEFBS_None, // G_IMPLICIT_DEF = 58
23193	CEFBS_None, // G_PHI = 59	23193	CEFBS_None, // G_PHI = 59
23194	CEFBS_None, // G_FRAME_INDEX = 60	23194	CEFBS_None, // G_FRAME_INDEX = 60
23195	CEFBS_None, // G_GLOBAL_VALUE = 61	23195	CEFBS_None, // G_GLOBAL_VALUE = 61
23196	CEFBS_None, // G_CONSTANT_POOL = 62	23196	CEFBS_None, // G_CONSTANT_POOL = 62
23197	CEFBS_None, // G_EXTRACT = 63	23197	CEFBS_None, // G_EXTRACT = 63
23198	CEFBS_None, // G_UNMERGE_VALUES = 64	23198	CEFBS_None, // G_UNMERGE_VALUES = 64
23199	CEFBS_None, // G_INSERT = 65	23199	CEFBS_None, // G_INSERT = 65
23200	CEFBS_None, // G_MERGE_VALUES = 66	23200	CEFBS_None, // G_MERGE_VALUES = 66
23201	CEFBS_None, // G_BUILD_VECTOR = 67	23201	CEFBS_None, // G_BUILD_VECTOR = 67
23202	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 68	23202	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 68
23203	CEFBS_None, // G_CONCAT_VECTORS = 69	23203	CEFBS_None, // G_CONCAT_VECTORS = 69
23204	CEFBS_None, // G_PTRTOINT = 70	23204	CEFBS_None, // G_PTRTOINT = 70
23205	CEFBS_None, // G_INTTOPTR = 71	23205	CEFBS_None, // G_INTTOPTR = 71
23206	CEFBS_None, // G_BITCAST = 72	23206	CEFBS_None, // G_BITCAST = 72
23207	CEFBS_None, // G_FREEZE = 73	23207	CEFBS_None, // G_FREEZE = 73
23208	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 74	23208	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 74
23209	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 75	23209	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 75
23210	CEFBS_None, // G_INTRINSIC_TRUNC = 76	23210	CEFBS_None, // G_INTRINSIC_TRUNC = 76
23211	CEFBS_None, // G_INTRINSIC_ROUND = 77	23211	CEFBS_None, // G_INTRINSIC_ROUND = 77
23212	CEFBS_None, // G_INTRINSIC_LRINT = 78	23212	CEFBS_None, // G_INTRINSIC_LRINT = 78
23213	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 79	23213	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 79
23214	CEFBS_None, // G_READCYCLECOUNTER = 80	23214	CEFBS_None, // G_READCYCLECOUNTER = 80
23215	CEFBS_None, // G_LOAD = 81	23215	CEFBS_None, // G_LOAD = 81
23216	CEFBS_None, // G_SEXTLOAD = 82	23216	CEFBS_None, // G_SEXTLOAD = 82
23217	CEFBS_None, // G_ZEXTLOAD = 83	23217	CEFBS_None, // G_ZEXTLOAD = 83
23218	CEFBS_None, // G_INDEXED_LOAD = 84	23218	CEFBS_None, // G_INDEXED_LOAD = 84
23219	CEFBS_None, // G_INDEXED_SEXTLOAD = 85	23219	CEFBS_None, // G_INDEXED_SEXTLOAD = 85
23220	CEFBS_None, // G_INDEXED_ZEXTLOAD = 86	23220	CEFBS_None, // G_INDEXED_ZEXTLOAD = 86
23221	CEFBS_None, // G_STORE = 87	23221	CEFBS_None, // G_STORE = 87
23222	CEFBS_None, // G_INDEXED_STORE = 88	23222	CEFBS_None, // G_INDEXED_STORE = 88
23223	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89	23223	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89
23224	CEFBS_None, // G_ATOMIC_CMPXCHG = 90	23224	CEFBS_None, // G_ATOMIC_CMPXCHG = 90
23225	CEFBS_None, // G_ATOMICRMW_XCHG = 91	23225	CEFBS_None, // G_ATOMICRMW_XCHG = 91
23226	CEFBS_None, // G_ATOMICRMW_ADD = 92	23226	CEFBS_None, // G_ATOMICRMW_ADD = 92
23227	CEFBS_None, // G_ATOMICRMW_SUB = 93	23227	CEFBS_None, // G_ATOMICRMW_SUB = 93
23228	CEFBS_None, // G_ATOMICRMW_AND = 94	23228	CEFBS_None, // G_ATOMICRMW_AND = 94
23229	CEFBS_None, // G_ATOMICRMW_NAND = 95	23229	CEFBS_None, // G_ATOMICRMW_NAND = 95
23230	CEFBS_None, // G_ATOMICRMW_OR = 96	23230	CEFBS_None, // G_ATOMICRMW_OR = 96
23231	CEFBS_None, // G_ATOMICRMW_XOR = 97	23231	CEFBS_None, // G_ATOMICRMW_XOR = 97
23232	CEFBS_None, // G_ATOMICRMW_MAX = 98	23232	CEFBS_None, // G_ATOMICRMW_MAX = 98
23233	CEFBS_None, // G_ATOMICRMW_MIN = 99	23233	CEFBS_None, // G_ATOMICRMW_MIN = 99
23234	CEFBS_None, // G_ATOMICRMW_UMAX = 100	23234	CEFBS_None, // G_ATOMICRMW_UMAX = 100
23235	CEFBS_None, // G_ATOMICRMW_UMIN = 101	23235	CEFBS_None, // G_ATOMICRMW_UMIN = 101
23236	CEFBS_None, // G_ATOMICRMW_FADD = 102	23236	CEFBS_None, // G_ATOMICRMW_FADD = 102
23237	CEFBS_None, // G_ATOMICRMW_FSUB = 103	23237	CEFBS_None, // G_ATOMICRMW_FSUB = 103
23238	CEFBS_None, // G_ATOMICRMW_FMAX = 104	23238	CEFBS_None, // G_ATOMICRMW_FMAX = 104
23239	CEFBS_None, // G_ATOMICRMW_FMIN = 105	23239	CEFBS_None, // G_ATOMICRMW_FMIN = 105
23240	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 106	23240	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 106
23241	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 107	23241	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 107
23242	CEFBS_None, // G_FENCE = 108	23242	CEFBS_None, // G_FENCE = 108
23243	CEFBS_None, // G_BRCOND = 109	23243	CEFBS_None, // G_BRCOND = 109
23244	CEFBS_None, // G_BRINDIRECT = 110	23244	CEFBS_None, // G_BRINDIRECT = 110
23245	CEFBS_None, // G_INVOKE_REGION_START = 111	23245	CEFBS_None, // G_INVOKE_REGION_START = 111
23246	CEFBS_None, // G_INTRINSIC = 112	23246	CEFBS_None, // G_INTRINSIC = 112
23247	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 113	23247	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 113
23248	CEFBS_None, // G_ANYEXT = 114	23248	CEFBS_None, // G_ANYEXT = 114
23249	CEFBS_None, // G_TRUNC = 115	23249	CEFBS_None, // G_TRUNC = 115
23250	CEFBS_None, // G_CONSTANT = 116	23250	CEFBS_None, // G_CONSTANT = 116
23251	CEFBS_None, // G_FCONSTANT = 117	23251	CEFBS_None, // G_FCONSTANT = 117
23252	CEFBS_None, // G_VASTART = 118	23252	CEFBS_None, // G_VASTART = 118
23253	CEFBS_None, // G_VAARG = 119	23253	CEFBS_None, // G_VAARG = 119
23254	CEFBS_None, // G_SEXT = 120	23254	CEFBS_None, // G_SEXT = 120
23255	CEFBS_None, // G_SEXT_INREG = 121	23255	CEFBS_None, // G_SEXT_INREG = 121
23256	CEFBS_None, // G_ZEXT = 122	23256	CEFBS_None, // G_ZEXT = 122
23257	CEFBS_None, // G_SHL = 123	23257	CEFBS_None, // G_SHL = 123
23258	CEFBS_None, // G_LSHR = 124	23258	CEFBS_None, // G_LSHR = 124
23259	CEFBS_None, // G_ASHR = 125	23259	CEFBS_None, // G_ASHR = 125
23260	CEFBS_None, // G_FSHL = 126	23260	CEFBS_None, // G_FSHL = 126
23261	CEFBS_None, // G_FSHR = 127	23261	CEFBS_None, // G_FSHR = 127
23262	CEFBS_None, // G_ROTR = 128	23262	CEFBS_None, // G_ROTR = 128
23263	CEFBS_None, // G_ROTL = 129	23263	CEFBS_None, // G_ROTL = 129
23264	CEFBS_None, // G_ICMP = 130	23264	CEFBS_None, // G_ICMP = 130
23265	CEFBS_None, // G_FCMP = 131	23265	CEFBS_None, // G_FCMP = 131
23266	CEFBS_None, // G_SELECT = 132	23266	CEFBS_None, // G_SELECT = 132
23267	CEFBS_None, // G_UADDO = 133	23267	CEFBS_None, // G_UADDO = 133
23268	CEFBS_None, // G_UADDE = 134	23268	CEFBS_None, // G_UADDE = 134
23269	CEFBS_None, // G_USUBO = 135	23269	CEFBS_None, // G_USUBO = 135
23270	CEFBS_None, // G_USUBE = 136	23270	CEFBS_None, // G_USUBE = 136
23271	CEFBS_None, // G_SADDO = 137	23271	CEFBS_None, // G_SADDO = 137
23272	CEFBS_None, // G_SADDE = 138	23272	CEFBS_None, // G_SADDE = 138
23273	CEFBS_None, // G_SSUBO = 139	23273	CEFBS_None, // G_SSUBO = 139
23274	CEFBS_None, // G_SSUBE = 140	23274	CEFBS_None, // G_SSUBE = 140
23275	CEFBS_None, // G_UMULO = 141	23275	CEFBS_None, // G_UMULO = 141
23276	CEFBS_None, // G_SMULO = 142	23276	CEFBS_None, // G_SMULO = 142
23277	CEFBS_None, // G_UMULH = 143	23277	CEFBS_None, // G_UMULH = 143
23278	CEFBS_None, // G_SMULH = 144	23278	CEFBS_None, // G_SMULH = 144
23279	CEFBS_None, // G_UADDSAT = 145	23279	CEFBS_None, // G_UADDSAT = 145
23280	CEFBS_None, // G_SADDSAT = 146	23280	CEFBS_None, // G_SADDSAT = 146
23281	CEFBS_None, // G_USUBSAT = 147	23281	CEFBS_None, // G_USUBSAT = 147
23282	CEFBS_None, // G_SSUBSAT = 148	23282	CEFBS_None, // G_SSUBSAT = 148
23283	CEFBS_None, // G_USHLSAT = 149	23283	CEFBS_None, // G_USHLSAT = 149
23284	CEFBS_None, // G_SSHLSAT = 150	23284	CEFBS_None, // G_SSHLSAT = 150
23285	CEFBS_None, // G_SMULFIX = 151	23285	CEFBS_None, // G_SMULFIX = 151
23286	CEFBS_None, // G_UMULFIX = 152	23286	CEFBS_None, // G_UMULFIX = 152
23287	CEFBS_None, // G_SMULFIXSAT = 153	23287	CEFBS_None, // G_SMULFIXSAT = 153
23288	CEFBS_None, // G_UMULFIXSAT = 154	23288	CEFBS_None, // G_UMULFIXSAT = 154
23289	CEFBS_None, // G_SDIVFIX = 155	23289	CEFBS_None, // G_SDIVFIX = 155
23290	CEFBS_None, // G_UDIVFIX = 156	23290	CEFBS_None, // G_UDIVFIX = 156
23291	CEFBS_None, // G_SDIVFIXSAT = 157	23291	CEFBS_None, // G_SDIVFIXSAT = 157
23292	CEFBS_None, // G_UDIVFIXSAT = 158	23292	CEFBS_None, // G_UDIVFIXSAT = 158
23293	CEFBS_None, // G_FADD = 159	23293	CEFBS_None, // G_FADD = 159
23294	CEFBS_None, // G_FSUB = 160	23294	CEFBS_None, // G_FSUB = 160
23295	CEFBS_None, // G_FMUL = 161	23295	CEFBS_None, // G_FMUL = 161
23296	CEFBS_None, // G_FMA = 162	23296	CEFBS_None, // G_FMA = 162
23297	CEFBS_None, // G_FMAD = 163	23297	CEFBS_None, // G_FMAD = 163
23298	CEFBS_None, // G_FDIV = 164	23298	CEFBS_None, // G_FDIV = 164
23299	CEFBS_None, // G_FREM = 165	23299	CEFBS_None, // G_FREM = 165
23300	CEFBS_None, // G_FPOW = 166	23300	CEFBS_None, // G_FPOW = 166
23301	CEFBS_None, // G_FPOWI = 167	23301	CEFBS_None, // G_FPOWI = 167
23302	CEFBS_None, // G_FEXP = 168	23302	CEFBS_None, // G_FEXP = 168
23303	CEFBS_None, // G_FEXP2 = 169	23303	CEFBS_None, // G_FEXP2 = 169
23304	CEFBS_None, // G_FLOG = 170	23304	CEFBS_None, // G_FLOG = 170
23305	CEFBS_None, // G_FLOG2 = 171	23305	CEFBS_None, // G_FLOG2 = 171
23306	CEFBS_None, // G_FLOG10 = 172	23306	CEFBS_None, // G_FLOG10 = 172
23307	CEFBS_None, // G_FLDEXP = 173	23307	CEFBS_None, // G_FLDEXP = 173
23308	CEFBS_None, // G_FFREXP = 174	23308	CEFBS_None, // G_FFREXP = 174
23309	CEFBS_None, // G_FNEG = 175	23309	CEFBS_None, // G_FNEG = 175
23310	CEFBS_None, // G_FPEXT = 176	23310	CEFBS_None, // G_FPEXT = 176
23311	CEFBS_None, // G_FPTRUNC = 177	23311	CEFBS_None, // G_FPTRUNC = 177
23312	CEFBS_None, // G_FPTOSI = 178	23312	CEFBS_None, // G_FPTOSI = 178
23313	CEFBS_None, // G_FPTOUI = 179	23313	CEFBS_None, // G_FPTOUI = 179
23314	CEFBS_None, // G_SITOFP = 180	23314	CEFBS_None, // G_SITOFP = 180
23315	CEFBS_None, // G_UITOFP = 181	23315	CEFBS_None, // G_UITOFP = 181
23316	CEFBS_None, // G_FABS = 182	23316	CEFBS_None, // G_FABS = 182
23317	CEFBS_None, // G_FCOPYSIGN = 183	23317	CEFBS_None, // G_FCOPYSIGN = 183
23318	CEFBS_None, // G_IS_FPCLASS = 184	23318	CEFBS_None, // G_IS_FPCLASS = 184
23319	CEFBS_None, // G_FCANONICALIZE = 185	23319	CEFBS_None, // G_FCANONICALIZE = 185
23320	CEFBS_None, // G_FMINNUM = 186	23320	CEFBS_None, // G_FMINNUM = 186
23321	CEFBS_None, // G_FMAXNUM = 187	23321	CEFBS_None, // G_FMAXNUM = 187
23322	CEFBS_None, // G_FMINNUM_IEEE = 188	23322	CEFBS_None, // G_FMINNUM_IEEE = 188
23323	CEFBS_None, // G_FMAXNUM_IEEE = 189	23323	CEFBS_None, // G_FMAXNUM_IEEE = 189
23324	CEFBS_None, // G_FMINIMUM = 190	23324	CEFBS_None, // G_FMINIMUM = 190
23325	CEFBS_None, // G_FMAXIMUM = 191	23325	CEFBS_None, // G_FMAXIMUM = 191
23326	CEFBS_None, // G_PTR_ADD = 192	23326	CEFBS_None, // G_PTR_ADD = 192
23327	CEFBS_None, // G_PTRMASK = 193	23327	CEFBS_None, // G_PTRMASK = 193
23328	CEFBS_None, // G_SMIN = 194	23328	CEFBS_None, // G_SMIN = 194
23329	CEFBS_None, // G_SMAX = 195	23329	CEFBS_None, // G_SMAX = 195
23330	CEFBS_None, // G_UMIN = 196	23330	CEFBS_None, // G_UMIN = 196
23331	CEFBS_None, // G_UMAX = 197	23331	CEFBS_None, // G_UMAX = 197
23332	CEFBS_None, // G_ABS = 198	23332	CEFBS_None, // G_ABS = 198
23333	CEFBS_None, // G_LROUND = 199	23333	CEFBS_None, // G_LROUND = 199
23334	CEFBS_None, // G_LLROUND = 200	23334	CEFBS_None, // G_LLROUND = 200
23335	CEFBS_None, // G_BR = 201	23335	CEFBS_None, // G_BR = 201
23336	CEFBS_None, // G_BRJT = 202	23336	CEFBS_None, // G_BRJT = 202
23337	CEFBS_None, // G_INSERT_VECTOR_ELT = 203	23337	CEFBS_None, // G_INSERT_VECTOR_ELT = 203
23338	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 204	23338	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 204
23339	CEFBS_None, // G_SHUFFLE_VECTOR = 205	23339	CEFBS_None, // G_SHUFFLE_VECTOR = 205
23340	CEFBS_None, // G_CTTZ = 206	23340	CEFBS_None, // G_CTTZ = 206
23341	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 207	23341	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 207
23342	CEFBS_None, // G_CTLZ = 208	23342	CEFBS_None, // G_CTLZ = 208
23343	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 209	23343	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 209
23344	CEFBS_None, // G_CTPOP = 210	23344	CEFBS_None, // G_CTPOP = 210
23345	CEFBS_None, // G_BSWAP = 211	23345	CEFBS_None, // G_BSWAP = 211
23346	CEFBS_None, // G_BITREVERSE = 212	23346	CEFBS_None, // G_BITREVERSE = 212
23347	CEFBS_None, // G_FCEIL = 213	23347	CEFBS_None, // G_FCEIL = 213
23348	CEFBS_None, // G_FCOS = 214	23348	CEFBS_None, // G_FCOS = 214
23349	CEFBS_None, // G_FSIN = 215	23349	CEFBS_None, // G_FSIN = 215
23350	CEFBS_None, // G_FSQRT = 216	23350	CEFBS_None, // G_FSQRT = 216
23351	CEFBS_None, // G_FFLOOR = 217	23351	CEFBS_None, // G_FFLOOR = 217
23352	CEFBS_None, // G_FRINT = 218	23352	CEFBS_None, // G_FRINT = 218
23353	CEFBS_None, // G_FNEARBYINT = 219	23353	CEFBS_None, // G_FNEARBYINT = 219
23354	CEFBS_None, // G_ADDRSPACE_CAST = 220	23354	CEFBS_None, // G_ADDRSPACE_CAST = 220
23355	CEFBS_None, // G_BLOCK_ADDR = 221	23355	CEFBS_None, // G_BLOCK_ADDR = 221
23356	CEFBS_None, // G_JUMP_TABLE = 222	23356	CEFBS_None, // G_JUMP_TABLE = 222
23357	CEFBS_None, // G_DYN_STACKALLOC = 223	23357	CEFBS_None, // G_DYN_STACKALLOC = 223
23358	CEFBS_None, // G_STRICT_FADD = 224	23358	CEFBS_None, // G_STRICT_FADD = 224
23359	CEFBS_None, // G_STRICT_FSUB = 225	23359	CEFBS_None, // G_STRICT_FSUB = 225
23360	CEFBS_None, // G_STRICT_FMUL = 226	23360	CEFBS_None, // G_STRICT_FMUL = 226
23361	CEFBS_None, // G_STRICT_FDIV = 227	23361	CEFBS_None, // G_STRICT_FDIV = 227
23362	CEFBS_None, // G_STRICT_FREM = 228	23362	CEFBS_None, // G_STRICT_FREM = 228
23363	CEFBS_None, // G_STRICT_FMA = 229	23363	CEFBS_None, // G_STRICT_FMA = 229
23364	CEFBS_None, // G_STRICT_FSQRT = 230	23364	CEFBS_None, // G_STRICT_FSQRT = 230
23365	CEFBS_None, // G_STRICT_FLDEXP = 231	23365	CEFBS_None, // G_STRICT_FLDEXP = 231
23366	CEFBS_None, // G_READ_REGISTER = 232	23366	CEFBS_None, // G_READ_REGISTER = 232
23367	CEFBS_None, // G_WRITE_REGISTER = 233	23367	CEFBS_None, // G_WRITE_REGISTER = 233
23368	CEFBS_None, // G_MEMCPY = 234	23368	CEFBS_None, // G_MEMCPY = 234
23369	CEFBS_None, // G_MEMCPY_INLINE = 235	23369	CEFBS_None, // G_MEMCPY_INLINE = 235
23370	CEFBS_None, // G_MEMMOVE = 236	23370	CEFBS_None, // G_MEMMOVE = 236
23371	CEFBS_None, // G_MEMSET = 237	23371	CEFBS_None, // G_MEMSET = 237
23372	CEFBS_None, // G_BZERO = 238	23372	CEFBS_None, // G_BZERO = 238
23373	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 239	23373	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 239
23374	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 240	23374	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 240
23375	CEFBS_None, // G_VECREDUCE_FADD = 241	23375	CEFBS_None, // G_VECREDUCE_FADD = 241
23376	CEFBS_None, // G_VECREDUCE_FMUL = 242	23376	CEFBS_None, // G_VECREDUCE_FMUL = 242
23377	CEFBS_None, // G_VECREDUCE_FMAX = 243	23377	CEFBS_None, // G_VECREDUCE_FMAX = 243
23378	CEFBS_None, // G_VECREDUCE_FMIN = 244	23378	CEFBS_None, // G_VECREDUCE_FMIN = 244
23379	CEFBS_None, // G_VECREDUCE_ADD = 245	23379	CEFBS_None, // G_VECREDUCE_ADD = 245
23380	CEFBS_None, // G_VECREDUCE_MUL = 246	23380	CEFBS_None, // G_VECREDUCE_MUL = 246
23381	CEFBS_None, // G_VECREDUCE_AND = 247	23381	CEFBS_None, // G_VECREDUCE_AND = 247
23382	CEFBS_None, // G_VECREDUCE_OR = 248	23382	CEFBS_None, // G_VECREDUCE_OR = 248
23383	CEFBS_None, // G_VECREDUCE_XOR = 249	23383	CEFBS_None, // G_VECREDUCE_XOR = 249
23384	CEFBS_None, // G_VECREDUCE_SMAX = 250	23384	CEFBS_None, // G_VECREDUCE_SMAX = 250
23385	CEFBS_None, // G_VECREDUCE_SMIN = 251	23385	CEFBS_None, // G_VECREDUCE_SMIN = 251
23386	CEFBS_None, // G_VECREDUCE_UMAX = 252	23386	CEFBS_None, // G_VECREDUCE_UMAX = 252
23387	CEFBS_None, // G_VECREDUCE_UMIN = 253	23387	CEFBS_None, // G_VECREDUCE_UMIN = 253
23388	CEFBS_None, // G_SBFX = 254	23388	CEFBS_None, // G_SBFX = 254
23389	CEFBS_None, // G_UBFX = 255	23389	CEFBS_None, // G_UBFX = 255
23390	CEFBS_None, // ABSMacro = 256	23390	CEFBS_None, // ABSMacro = 256
23391	CEFBS_None, // ADJCALLSTACKDOWN = 257	23391	CEFBS_None, // ADJCALLSTACKDOWN = 257
23392	CEFBS_None, // ADJCALLSTACKUP = 258	23392	CEFBS_None, // ADJCALLSTACKUP = 258
23393	CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 259	23393	CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 259
23394	CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 260	23394	CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 260
23395	CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 261	23395	CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 261
23396	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 262	23396	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 262
23397	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 263	23397	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 263
23398	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 264	23398	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 264
23399	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 265	23399	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 265
23400	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 266	23400	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 266
23401	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 267	23401	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 267
23402	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 268	23402	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 268
23403	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 269	23403	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 269
23404	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 270	23404	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 270
23405	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 271	23405	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 271
23406	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 272	23406	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 272
23407	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 273	23407	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 273
23408	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 274	23408	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 274
23409	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 275	23409	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 275
23410	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 276	23410	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 276
23411	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 277	23411	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 277
23412	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 278	23412	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 278
23413	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 279	23413	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 279
23414	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 280	23414	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 280
23415	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 281	23415	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 281
23416	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 282	23416	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 282
23417	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 283	23417	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 283
23418	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 284	23418	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 284
23419	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 285	23419	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 285
23420	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 286	23420	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 286
23421	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 287	23421	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 287
23422	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 288	23422	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 288
23423	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 289	23423	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 289
23424	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 290	23424	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 290
23425	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 291	23425	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 291
23426	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 292	23426	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 292
23427	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 293	23427	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 293
23428	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 294	23428	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 294
23429	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 295	23429	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 295
23430	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 296	23430	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 296
23431	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 297	23431	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 297
23432	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 298	23432	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 298
23433	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 299	23433	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 299
23434	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 300	23434	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 300
23435	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 301	23435	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 301
23436	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 302	23436	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 302
23437	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 303	23437	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 303
23438	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 304	23438	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 304
23439	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 305	23439	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 305
23440	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 306	23440	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 306
23441	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 307	23441	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 307
23442	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 308	23442	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 308
23443	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 309	23443	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 309
23444	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 310	23444	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 310
23445	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 311	23445	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 311
23446	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 312	23446	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 312
23447	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 313	23447	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 313
23448	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 314	23448	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 314
23449	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 315	23449	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 315
23450	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 316	23450	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 316
23451	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 317	23451	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 317
23452	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 318	23452	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 318
23453	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 319	23453	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 319
23454	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 320	23454	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 320
23455	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 321	23455	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 321
23456	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 322	23456	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 322
23457	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 323	23457	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 323
23458	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 324	23458	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 324
23459	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 325	23459	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 325
23460	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 326	23460	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 326
23461	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 327	23461	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 327
23462	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 328	23462	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 328
23463	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 329	23463	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 329
23464	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 330	23464	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 330
23465	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 331	23465	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 331
23466	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 332	23466	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 332
23467	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 333	23467	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 333
23468	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 334	23468	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 334
23469	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 335	23469	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 335
23470	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 336	23470	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 336
23471	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 337	23471	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 337
23472	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 338	23472	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 338
23473	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 339	23473	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 339
23474	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 340	23474	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 340
23475	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 341	23475	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 341
23476	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 342	23476	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 342
23477	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 343	23477	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 343
23478	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 344	23478	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 344
23479	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 345	23479	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 345
23480	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 346	23480	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 346
23481	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 347	23481	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 347
23482	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 348	23482	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 348
23483	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 349	23483	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 349
23484	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 350	23484	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 350
23485	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 351	23485	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 351
23486	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 352	23486	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 352
23487	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 353	23487	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 353
23488	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 354	23488	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 354
23489	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 355	23489	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 355
23490	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 356	23490	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 356
23491	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 357	23491	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 357
23492	CEFBS_HasStdEnc_NotInMicroMips, // B = 358	23492	CEFBS_HasStdEnc_NotInMicroMips, // B = 358
23493	CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 359	23493	CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 359
23494	CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 360	23494	CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 360
23495	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 361	23495	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 361
23496	CEFBS_None, // BGE = 362	23496	CEFBS_None, // BGE = 362
23497	CEFBS_None, // BGEImmMacro = 363	23497	CEFBS_None, // BGEImmMacro = 363
23498	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 364	23498	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 364
23499	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 365	23499	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 365
23500	CEFBS_None, // BGEU = 366	23500	CEFBS_None, // BGEU = 366
23501	CEFBS_None, // BGEUImmMacro = 367	23501	CEFBS_None, // BGEUImmMacro = 367
23502	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 368	23502	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 368
23503	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 369	23503	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 369
23504	CEFBS_None, // BGT = 370	23504	CEFBS_None, // BGT = 370
23505	CEFBS_None, // BGTImmMacro = 371	23505	CEFBS_None, // BGTImmMacro = 371
23506	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 372	23506	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 372
23507	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 373	23507	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 373
23508	CEFBS_None, // BGTU = 374	23508	CEFBS_None, // BGTU = 374
23509	CEFBS_None, // BGTUImmMacro = 375	23509	CEFBS_None, // BGTUImmMacro = 375
23510	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 376	23510	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 376
23511	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 377	23511	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 377
23512	CEFBS_None, // BLE = 378	23512	CEFBS_None, // BLE = 378
23513	CEFBS_None, // BLEImmMacro = 379	23513	CEFBS_None, // BLEImmMacro = 379
23514	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 380	23514	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 380
23515	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 381	23515	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 381
23516	CEFBS_None, // BLEU = 382	23516	CEFBS_None, // BLEU = 382
23517	CEFBS_None, // BLEUImmMacro = 383	23517	CEFBS_None, // BLEUImmMacro = 383
23518	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 384	23518	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 384
23519	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 385	23519	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 385
23520	CEFBS_None, // BLT = 386	23520	CEFBS_None, // BLT = 386
23521	CEFBS_None, // BLTImmMacro = 387	23521	CEFBS_None, // BLTImmMacro = 387
23522	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 388	23522	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 388
23523	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 389	23523	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 389
23524	CEFBS_None, // BLTU = 390	23524	CEFBS_None, // BLTU = 390
23525	CEFBS_None, // BLTUImmMacro = 391	23525	CEFBS_None, // BLTUImmMacro = 391
23526	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 392	23526	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 392
23527	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 393	23527	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 393
23528	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 394	23528	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 394
23529	CEFBS_None, // BPOSGE32_PSEUDO = 395	23529	CEFBS_None, // BPOSGE32_PSEUDO = 395
23530	CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 396	23530	CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 396
23531	CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 397	23531	CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 397
23532	CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 398	23532	CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 398
23533	CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 399	23533	CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 399
23534	CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 400	23534	CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 400
23535	CEFBS_InMicroMips_NotMips32r6, // B_MM = 401	23535	CEFBS_InMicroMips_NotMips32r6, // B_MM = 401
23536	CEFBS_None, // B_MMR6_Pseudo = 402	23536	CEFBS_None, // B_MMR6_Pseudo = 402
23537	CEFBS_InMicroMips, // B_MM_Pseudo = 403	23537	CEFBS_InMicroMips, // B_MM_Pseudo = 403
23538	CEFBS_None, // BeqImm = 404	23538	CEFBS_None, // BeqImm = 404
23539	CEFBS_None, // BneImm = 405	23539	CEFBS_None, // BneImm = 405
23540	CEFBS_InMips16Mode, // BteqzT8CmpX16 = 406	23540	CEFBS_InMips16Mode, // BteqzT8CmpX16 = 406
23541	CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 407	23541	CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 407
23542	CEFBS_InMips16Mode, // BteqzT8SltX16 = 408	23542	CEFBS_InMips16Mode, // BteqzT8SltX16 = 408
23543	CEFBS_InMips16Mode, // BteqzT8SltiX16 = 409	23543	CEFBS_InMips16Mode, // BteqzT8SltiX16 = 409
23544	CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 410	23544	CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 410
23545	CEFBS_InMips16Mode, // BteqzT8SltuX16 = 411	23545	CEFBS_InMips16Mode, // BteqzT8SltuX16 = 411
23546	CEFBS_InMips16Mode, // BtnezT8CmpX16 = 412	23546	CEFBS_InMips16Mode, // BtnezT8CmpX16 = 412
23547	CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 413	23547	CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 413
23548	CEFBS_InMips16Mode, // BtnezT8SltX16 = 414	23548	CEFBS_InMips16Mode, // BtnezT8SltX16 = 414
23549	CEFBS_InMips16Mode, // BtnezT8SltiX16 = 415	23549	CEFBS_InMips16Mode, // BtnezT8SltiX16 = 415
23550	CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 416	23550	CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 416
23551	CEFBS_InMips16Mode, // BtnezT8SltuX16 = 417	23551	CEFBS_InMips16Mode, // BtnezT8SltuX16 = 417
23552	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 418	23552	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 418
23553	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 419	23553	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 419
23554	CEFBS_HasMT, // CFTC1 = 420	23554	CEFBS_HasMT, // CFTC1 = 420
23555	CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 421	23555	CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 421
23556	CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 422	23556	CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 422
23557	CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 423	23557	CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 423
23558	CEFBS_HasMT, // CTTC1 = 424	23558	CEFBS_HasMT, // CTTC1 = 424
23559	CEFBS_InMips16Mode, // Constant32 = 425	23559	CEFBS_InMips16Mode, // Constant32 = 425
23560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 426	23560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 426
23561	CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 427	23561	CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 427
23562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 428	23562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 428
23563	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 429	23563	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 429
23564	CEFBS_HasStdEnc_HasMips64, // DROL = 430	23564	CEFBS_HasStdEnc_HasMips64, // DROL = 430
23565	CEFBS_HasStdEnc_HasMips64, // DROLImm = 431	23565	CEFBS_HasStdEnc_HasMips64, // DROLImm = 431
23566	CEFBS_HasStdEnc_HasMips64, // DROR = 432	23566	CEFBS_HasStdEnc_HasMips64, // DROR = 432
23567	CEFBS_HasStdEnc_HasMips64, // DRORImm = 433	23567	CEFBS_HasStdEnc_HasMips64, // DRORImm = 433
23568	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 434	23568	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 434
23569	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 435	23569	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 435
23570	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 436	23570	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 436
23571	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 437	23571	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 437
23572	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 438	23572	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 438
23573	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 439	23573	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 439
23574	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 440	23574	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 440
23575	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 441	23575	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 441
23576	CEFBS_NotInMips16Mode, // ERet = 442	23576	CEFBS_NotInMips16Mode, // ERet = 442
23577	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 443	23577	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 443
23578	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 444	23578	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 444
23579	CEFBS_HasStdEnc_HasMSA, // FABS_D = 445	23579	CEFBS_HasStdEnc_HasMSA, // FABS_D = 445
23580	CEFBS_HasStdEnc_HasMSA, // FABS_W = 446	23580	CEFBS_HasStdEnc_HasMSA, // FABS_W = 446
23581	CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 447	23581	CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 447
23582	CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 448	23582	CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 448
23583	CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 449	23583	CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 449
23584	CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 450	23584	CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 450
23585	CEFBS_InMips16Mode, // GotPrologue16 = 451	23585	CEFBS_InMips16Mode, // GotPrologue16 = 451
23586	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 452	23586	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 452
23587	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 453	23587	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 453
23588	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 454	23588	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 454
23589	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 455	23589	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 455
23590	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 456	23590	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 456
23591	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 457	23591	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 457
23592	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 458	23592	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 458
23593	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 459	23593	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 459
23594	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 460	23594	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 460
23595	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 461	23595	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 461
23596	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 462	23596	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 462
23597	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 463	23597	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 463
23598	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 464	23598	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 464
23599	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 465	23599	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 465
23600	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 466	23600	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 466
23601	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 467	23601	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 467
23602	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 468	23602	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 468
23603	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 469	23603	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 469
23604	CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 470	23604	CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 470
23605	CEFBS_None, // JalOneReg = 471	23605	CEFBS_None, // JalOneReg = 471
23606	CEFBS_None, // JalTwoReg = 472	23606	CEFBS_None, // JalTwoReg = 472
23607	CEFBS_HasStdEnc_NotMips3, // LDMacro = 473	23607	CEFBS_HasStdEnc_NotMips3, // LDMacro = 473
23608	CEFBS_NotInMips16Mode, // LDR_D = 474	23608	CEFBS_NotInMips16Mode, // LDR_D = 474
23609	CEFBS_NotInMips16Mode, // LDR_W = 475	23609	CEFBS_NotInMips16Mode, // LDR_W = 475
23610	CEFBS_HasMSA, // LD_F16 = 476	23610	CEFBS_HasMSA, // LD_F16 = 476
23611	CEFBS_NotInMips16Mode, // LOAD_ACC128 = 477	23611	CEFBS_NotInMips16Mode, // LOAD_ACC128 = 477
23612	CEFBS_NotInMips16Mode, // LOAD_ACC64 = 478	23612	CEFBS_NotInMips16Mode, // LOAD_ACC64 = 478
23613	CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 479	23613	CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 479
23614	CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 480	23614	CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 480
23615	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 481	23615	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 481
23616	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 482	23616	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 482
23617	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 483	23617	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 483
23618	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 484	23618	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 484
23619	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 485	23619	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 485
23620	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 486	23620	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 486
23621	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 487	23621	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 487
23622	CEFBS_InMicroMips, // LWM_MM = 488	23622	CEFBS_InMicroMips, // LWM_MM = 488
23623	CEFBS_None, // LoadAddrImm32 = 489	23623	CEFBS_None, // LoadAddrImm32 = 489
23624	CEFBS_None, // LoadAddrImm64 = 490	23624	CEFBS_None, // LoadAddrImm64 = 490
23625	CEFBS_None, // LoadAddrReg32 = 491	23625	CEFBS_None, // LoadAddrReg32 = 491
23626	CEFBS_None, // LoadAddrReg64 = 492	23626	CEFBS_None, // LoadAddrReg64 = 492
23627	CEFBS_None, // LoadImm32 = 493	23627	CEFBS_None, // LoadImm32 = 493
23628	CEFBS_None, // LoadImm64 = 494	23628	CEFBS_None, // LoadImm64 = 494
23629	CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 495	23629	CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 495
23630	CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 496	23630	CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 496
23631	CEFBS_None, // LoadImmDoubleGPR = 497	23631	CEFBS_None, // LoadImmDoubleGPR = 497
23632	CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 498	23632	CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 498
23633	CEFBS_None, // LoadImmSingleGPR = 499	23633	CEFBS_None, // LoadImmSingleGPR = 499
23634	CEFBS_InMips16Mode, // LwConstant32 = 500	23634	CEFBS_InMips16Mode, // LwConstant32 = 500
23635	CEFBS_HasMT, // MFTACX = 501	23635	CEFBS_HasMT, // MFTACX = 501
23636	CEFBS_HasMT, // MFTC0 = 502	23636	CEFBS_HasMT, // MFTC0 = 502
23637	CEFBS_HasMT, // MFTC1 = 503	23637	CEFBS_HasMT, // MFTC1 = 503
23638	CEFBS_HasMT, // MFTDSP = 504	23638	CEFBS_HasMT, // MFTDSP = 504
23639	CEFBS_HasMT, // MFTGPR = 505	23639	CEFBS_HasMT, // MFTGPR = 505
23640	CEFBS_HasMT, // MFTHC1 = 506	23640	CEFBS_HasMT, // MFTHC1 = 506
23641	CEFBS_HasMT, // MFTHI = 507	23641	CEFBS_HasMT, // MFTHI = 507
23642	CEFBS_HasMT, // MFTLO = 508	23642	CEFBS_HasMT, // MFTLO = 508
23643	CEFBS_None, // MIPSeh_return32 = 509	23643	CEFBS_None, // MIPSeh_return32 = 509
23644	CEFBS_None, // MIPSeh_return64 = 510	23644	CEFBS_None, // MIPSeh_return64 = 510
23645	CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 511	23645	CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 511
23646	CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 512	23646	CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 512
23647	CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 513	23647	CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 513
23648	CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 514	23648	CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 514
23649	CEFBS_HasMT, // MTTACX = 515	23649	CEFBS_HasMT, // MTTACX = 515
23650	CEFBS_HasMT, // MTTC0 = 516	23650	CEFBS_HasMT, // MTTC0 = 516
23651	CEFBS_HasMT, // MTTC1 = 517	23651	CEFBS_HasMT, // MTTC1 = 517
23652	CEFBS_HasMT, // MTTDSP = 518	23652	CEFBS_HasMT, // MTTDSP = 518
23653	CEFBS_HasMT, // MTTGPR = 519	23653	CEFBS_HasMT, // MTTGPR = 519
23654	CEFBS_HasMT, // MTTHC1 = 520	23654	CEFBS_HasMT, // MTTHC1 = 520
23655	CEFBS_HasMT, // MTTHI = 521	23655	CEFBS_HasMT, // MTTHI = 521
23656	CEFBS_HasMT, // MTTLO = 522	23656	CEFBS_HasMT, // MTTLO = 522
23657	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 523	23657	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 523
23658	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 524	23658	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 524
23659	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 525	23659	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 525
23660	CEFBS_InMips16Mode, // MultRxRy16 = 526	23660	CEFBS_InMips16Mode, // MultRxRy16 = 526
23661	CEFBS_InMips16Mode, // MultRxRyRz16 = 527	23661	CEFBS_InMips16Mode, // MultRxRyRz16 = 527
23662	CEFBS_InMips16Mode, // MultuRxRy16 = 528	23662	CEFBS_InMips16Mode, // MultuRxRy16 = 528
23663	CEFBS_InMips16Mode, // MultuRxRyRz16 = 529	23663	CEFBS_InMips16Mode, // MultuRxRyRz16 = 529
23664	CEFBS_HasStdEnc_NotInMicroMips, // NOP = 530	23664	CEFBS_HasStdEnc_NotInMicroMips, // NOP = 530
23665	CEFBS_IsGP32bit, // NORImm = 531	23665	CEFBS_IsGP32bit, // NORImm = 531
23666	CEFBS_IsGP64bit, // NORImm64 = 532	23666	CEFBS_IsGP64bit, // NORImm64 = 532
23667	CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 533	23667	CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 533
23668	CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 534	23668	CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 534
23669	CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 535	23669	CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 535
23670	CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 536	23670	CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 536
23671	CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 537	23671	CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 537
23672	CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 538	23672	CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 538
23673	CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 539	23673	CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 539
23674	CEFBS_HasDSP, // PseudoCMPU_LE_QB = 540	23674	CEFBS_HasDSP, // PseudoCMPU_LE_QB = 540
23675	CEFBS_HasDSP, // PseudoCMPU_LT_QB = 541	23675	CEFBS_HasDSP, // PseudoCMPU_LT_QB = 541
23676	CEFBS_HasDSP, // PseudoCMP_EQ_PH = 542	23676	CEFBS_HasDSP, // PseudoCMP_EQ_PH = 542
23677	CEFBS_HasDSP, // PseudoCMP_LE_PH = 543	23677	CEFBS_HasDSP, // PseudoCMP_LE_PH = 543
23678	CEFBS_HasDSP, // PseudoCMP_LT_PH = 544	23678	CEFBS_HasDSP, // PseudoCMP_LT_PH = 544
23679	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 545	23679	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 545
23680	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 546	23680	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 546
23681	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 547	23681	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 547
23682	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 548	23682	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 548
23683	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 549	23683	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 549
23684	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 550	23684	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 550
23685	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 551	23685	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 551
23686	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 552	23686	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 552
23687	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 553	23687	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 553
23688	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 554	23688	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 554
23689	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 555	23689	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 555
23690	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 556	23690	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 556
23691	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 557	23691	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 557
23692	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 558	23692	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 558
23693	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 559	23693	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 559
23694	CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 560	23694	CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 560
23695	CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 561	23695	CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 561
23696	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 562	23696	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 562
23697	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 563	23697	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 563
23698	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 564	23698	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 564
23699	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 565	23699	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 565
23700	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 566	23700	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 566
23701	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 567	23701	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 567
23702	CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 568	23702	CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 568
23703	CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 569	23703	CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 569
23704	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 570	23704	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 570
23705	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 571	23705	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 571
23706	CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 572	23706	CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 572
23707	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 573	23707	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 573
23708	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 574	23708	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 574
23709	CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 575	23709	CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 575
23710	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 576	23710	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 576
23711	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 577	23711	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 577
23712	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 578	23712	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 578
23713	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 579	23713	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 579
23714	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 580	23714	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 580
23715	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 581	23715	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 581
23716	CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 582	23716	CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 582
23717	CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 583	23717	CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 583
23718	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 584	23718	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 584
23719	CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 585	23719	CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 585
23720	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 586	23720	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 586
23721	CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 587	23721	CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 587
23722	CEFBS_HasDSP, // PseudoPICK_PH = 588	23722	CEFBS_HasDSP, // PseudoPICK_PH = 588
23723	CEFBS_HasDSP, // PseudoPICK_QB = 589	23723	CEFBS_HasDSP, // PseudoPICK_QB = 589
23724	CEFBS_None, // PseudoReturn = 590	23724	CEFBS_None, // PseudoReturn = 590
23725	CEFBS_IsGP64bit, // PseudoReturn64 = 591	23725	CEFBS_IsGP64bit, // PseudoReturn64 = 591
23726	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 592	23726	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 592
23727	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 593	23727	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 593
23728	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 594	23728	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 594
23729	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 595	23729	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 595
23730	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 596	23730	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 596
23731	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 597	23731	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 597
23732	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 598	23732	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 598
23733	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 599	23733	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 599
23734	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 600	23734	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 600
23735	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 601	23735	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 601
23736	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 602	23736	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 602
23737	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 603	23737	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 603
23738	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 604	23738	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 604
23739	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 605	23739	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 605
23740	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 606	23740	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 606
23741	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 607	23741	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 607
23742	CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 608	23742	CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 608
23743	CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 609	23743	CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 609
23744	CEFBS_None, // PseudoTRUNC_W_S = 610	23744	CEFBS_None, // PseudoTRUNC_W_S = 610
23745	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 611	23745	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 611
23746	CEFBS_None, // ROL = 612	23746	CEFBS_None, // ROL = 612
23747	CEFBS_None, // ROLImm = 613	23747	CEFBS_None, // ROLImm = 613
23748	CEFBS_None, // ROR = 614	23748	CEFBS_None, // ROR = 614
23749	CEFBS_None, // RORImm = 615	23749	CEFBS_None, // RORImm = 615
23750	CEFBS_NotInMips16Mode, // RetRA = 616	23750	CEFBS_NotInMips16Mode, // RetRA = 616
23751	CEFBS_InMips16Mode, // RetRA16 = 617	23751	CEFBS_InMips16Mode, // RetRA16 = 617
23752	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 618	23752	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 618
23753	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 619	23753	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 619
23754	CEFBS_HasStdEnc_NotMips3, // SDMacro = 620	23754	CEFBS_HasStdEnc_NotMips3, // SDMacro = 620
23755	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 621	23755	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 621
23756	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 622	23756	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 622
23757	CEFBS_NotCnMips, // SEQIMacro = 623	23757	CEFBS_NotCnMips, // SEQIMacro = 623
23758	CEFBS_NotCnMips, // SEQMacro = 624	23758	CEFBS_NotCnMips, // SEQMacro = 624
23759	CEFBS_HasStdEnc_NotInMicroMips, // SGE = 625	23759	CEFBS_HasStdEnc_NotInMicroMips, // SGE = 625
23760	CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 626	23760	CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 626
23761	CEFBS_IsGP64bit, // SGEImm64 = 627	23761	CEFBS_IsGP64bit, // SGEImm64 = 627
23762	CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 628	23762	CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 628
23763	CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 629	23763	CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 629
23764	CEFBS_IsGP64bit, // SGEUImm64 = 630	23764	CEFBS_IsGP64bit, // SGEUImm64 = 630
23765	CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 631	23765	CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 631
23766	CEFBS_IsGP64bit, // SGTImm64 = 632	23766	CEFBS_IsGP64bit, // SGTImm64 = 632
23767	CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 633	23767	CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 633
23768	CEFBS_IsGP64bit, // SGTUImm64 = 634	23768	CEFBS_IsGP64bit, // SGTUImm64 = 634
23769	CEFBS_HasStdEnc_NotInMicroMips, // SLE = 635	23769	CEFBS_HasStdEnc_NotInMicroMips, // SLE = 635
23770	CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 636	23770	CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 636
23771	CEFBS_IsGP64bit, // SLEImm64 = 637	23771	CEFBS_IsGP64bit, // SLEImm64 = 637
23772	CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 638	23772	CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 638
23773	CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 639	23773	CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 639
23774	CEFBS_IsGP64bit, // SLEUImm64 = 640	23774	CEFBS_IsGP64bit, // SLEUImm64 = 640
23775	CEFBS_IsGP64bit, // SLTImm64 = 641	23775	CEFBS_IsGP64bit, // SLTImm64 = 641
23776	CEFBS_IsGP64bit, // SLTUImm64 = 642	23776	CEFBS_IsGP64bit, // SLTUImm64 = 642
23777	CEFBS_NotCnMips, // SNEIMacro = 643	23777	CEFBS_NotCnMips, // SNEIMacro = 643
23778	CEFBS_NotCnMips, // SNEMacro = 644	23778	CEFBS_NotCnMips, // SNEMacro = 644
23779	CEFBS_None, // SNZ_B_PSEUDO = 645	23779	CEFBS_None, // SNZ_B_PSEUDO = 645
23780	CEFBS_None, // SNZ_D_PSEUDO = 646	23780	CEFBS_None, // SNZ_D_PSEUDO = 646
23781	CEFBS_None, // SNZ_H_PSEUDO = 647	23781	CEFBS_None, // SNZ_H_PSEUDO = 647
23782	CEFBS_None, // SNZ_V_PSEUDO = 648	23782	CEFBS_None, // SNZ_V_PSEUDO = 648
23783	CEFBS_None, // SNZ_W_PSEUDO = 649	23783	CEFBS_None, // SNZ_W_PSEUDO = 649
23784	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 650	23784	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 650
23785	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 651	23785	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 651
23786	CEFBS_NotInMips16Mode, // STORE_ACC128 = 652	23786	CEFBS_NotInMips16Mode, // STORE_ACC128 = 652
23787	CEFBS_NotInMips16Mode, // STORE_ACC64 = 653	23787	CEFBS_NotInMips16Mode, // STORE_ACC64 = 653
23788	CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 654	23788	CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 654
23789	CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 655	23789	CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 655
23790	CEFBS_NotInMips16Mode, // STR_D = 656	23790	CEFBS_NotInMips16Mode, // STR_D = 656
23791	CEFBS_NotInMips16Mode, // STR_W = 657	23791	CEFBS_NotInMips16Mode, // STR_W = 657
23792	CEFBS_HasMSA, // ST_F16 = 658	23792	CEFBS_HasMSA, // ST_F16 = 658
23793	CEFBS_InMicroMips, // SWM_MM = 659	23793	CEFBS_InMicroMips, // SWM_MM = 659
23794	CEFBS_None, // SZ_B_PSEUDO = 660	23794	CEFBS_None, // SZ_B_PSEUDO = 660
23795	CEFBS_None, // SZ_D_PSEUDO = 661	23795	CEFBS_None, // SZ_D_PSEUDO = 661
23796	CEFBS_None, // SZ_H_PSEUDO = 662	23796	CEFBS_None, // SZ_H_PSEUDO = 662
23797	CEFBS_None, // SZ_V_PSEUDO = 663	23797	CEFBS_None, // SZ_V_PSEUDO = 663
23798	CEFBS_None, // SZ_W_PSEUDO = 664	23798	CEFBS_None, // SZ_W_PSEUDO = 664
23799	CEFBS_HasCnMipsP, // SaaAddr = 665	23799	CEFBS_HasCnMipsP, // SaaAddr = 665
23800	CEFBS_HasCnMipsP, // SaadAddr = 666	23800	CEFBS_HasCnMipsP, // SaadAddr = 666
23801	CEFBS_InMips16Mode, // SelBeqZ = 667	23801	CEFBS_InMips16Mode, // SelBeqZ = 667
23802	CEFBS_InMips16Mode, // SelBneZ = 668	23802	CEFBS_InMips16Mode, // SelBneZ = 668
23803	CEFBS_InMips16Mode, // SelTBteqZCmp = 669	23803	CEFBS_InMips16Mode, // SelTBteqZCmp = 669
23804	CEFBS_InMips16Mode, // SelTBteqZCmpi = 670	23804	CEFBS_InMips16Mode, // SelTBteqZCmpi = 670
23805	CEFBS_InMips16Mode, // SelTBteqZSlt = 671	23805	CEFBS_InMips16Mode, // SelTBteqZSlt = 671
23806	CEFBS_InMips16Mode, // SelTBteqZSlti = 672	23806	CEFBS_InMips16Mode, // SelTBteqZSlti = 672
23807	CEFBS_InMips16Mode, // SelTBteqZSltiu = 673	23807	CEFBS_InMips16Mode, // SelTBteqZSltiu = 673
23808	CEFBS_InMips16Mode, // SelTBteqZSltu = 674	23808	CEFBS_InMips16Mode, // SelTBteqZSltu = 674
23809	CEFBS_InMips16Mode, // SelTBtneZCmp = 675	23809	CEFBS_InMips16Mode, // SelTBtneZCmp = 675
23810	CEFBS_InMips16Mode, // SelTBtneZCmpi = 676	23810	CEFBS_InMips16Mode, // SelTBtneZCmpi = 676
23811	CEFBS_InMips16Mode, // SelTBtneZSlt = 677	23811	CEFBS_InMips16Mode, // SelTBtneZSlt = 677
23812	CEFBS_InMips16Mode, // SelTBtneZSlti = 678	23812	CEFBS_InMips16Mode, // SelTBtneZSlti = 678
23813	CEFBS_InMips16Mode, // SelTBtneZSltiu = 679	23813	CEFBS_InMips16Mode, // SelTBtneZSltiu = 679
23814	CEFBS_InMips16Mode, // SelTBtneZSltu = 680	23814	CEFBS_InMips16Mode, // SelTBtneZSltu = 680
23815	CEFBS_InMips16Mode, // SltCCRxRy16 = 681	23815	CEFBS_InMips16Mode, // SltCCRxRy16 = 681
23816	CEFBS_InMips16Mode, // SltiCCRxImmX16 = 682	23816	CEFBS_InMips16Mode, // SltiCCRxImmX16 = 682
23817	CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 683	23817	CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 683
23818	CEFBS_InMips16Mode, // SltuCCRxRy16 = 684	23818	CEFBS_InMips16Mode, // SltuCCRxRy16 = 684
23819	CEFBS_InMips16Mode, // SltuRxRyRz16 = 685	23819	CEFBS_InMips16Mode, // SltuRxRyRz16 = 685
23820	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 686	23820	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 686
23821	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 687	23821	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 687
23822	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 688	23822	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 688
23823	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 689	23823	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 689
23824	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 690	23824	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 690
23825	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 691	23825	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 691
23826	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 692	23826	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 692
23827	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 693	23827	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 693
23828	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 694	23828	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 694
23829	CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 695	23829	CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 695
23830	CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 696	23830	CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 696
23831	CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 697	23831	CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 697
23832	CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 698	23832	CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 698
23833	CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 699	23833	CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 699
23834	CEFBS_InMicroMips, // TRAP_MM = 700	23834	CEFBS_InMicroMips, // TRAP_MM = 700
23835	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 701	23835	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 701
23836	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 702	23836	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 702
23837	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 703	23837	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 703
23838	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 704	23838	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 704
23839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 705	23839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 705
23840	CEFBS_None, // Ulh = 706	23840	CEFBS_None, // Ulh = 706
23841	CEFBS_None, // Ulhu = 707	23841	CEFBS_None, // Ulhu = 707
23842	CEFBS_None, // Ulw = 708	23842	CEFBS_None, // Ulw = 708
23843	CEFBS_None, // Ush = 709	23843	CEFBS_None, // Ush = 709
23844	CEFBS_None, // Usw = 710	23844	CEFBS_None, // Usw = 710
23845	CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 711	23845	CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 711
23846	CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 712	23846	CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 712
23847	CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 713	23847	CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 713
23848	CEFBS_HasDSP, // ABSQ_S_PH = 714	23848	CEFBS_HasDSP, // ABSQ_S_PH = 714
23849	CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 715	23849	CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 715
23850	CEFBS_HasDSPR2, // ABSQ_S_QB = 716	23850	CEFBS_HasDSPR2, // ABSQ_S_QB = 716
23851	CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 717	23851	CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 717
23852	CEFBS_HasDSP, // ABSQ_S_W = 718	23852	CEFBS_HasDSP, // ABSQ_S_W = 718
23853	CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 719	23853	CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 719
23854	CEFBS_HasStdEnc_NotInMicroMips, // ADD = 720	23854	CEFBS_HasStdEnc_NotInMicroMips, // ADD = 720
23855	CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 721	23855	CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 721
23856	CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 722	23856	CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 722
23857	CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 723	23857	CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 723
23858	CEFBS_InMicroMips, // ADDIUR1SP_MM = 724	23858	CEFBS_InMicroMips, // ADDIUR1SP_MM = 724
23859	CEFBS_InMicroMips, // ADDIUR2_MM = 725	23859	CEFBS_InMicroMips, // ADDIUR2_MM = 725
23860	CEFBS_InMicroMips, // ADDIUS5_MM = 726	23860	CEFBS_InMicroMips, // ADDIUS5_MM = 726
23861	CEFBS_InMicroMips, // ADDIUSP_MM = 727	23861	CEFBS_InMicroMips, // ADDIUSP_MM = 727
23862	CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 728	23862	CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 728
23863	CEFBS_HasDSPR2, // ADDQH_PH = 729	23863	CEFBS_HasDSPR2, // ADDQH_PH = 729
23864	CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 730	23864	CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 730
23865	CEFBS_HasDSPR2, // ADDQH_R_PH = 731	23865	CEFBS_HasDSPR2, // ADDQH_R_PH = 731
23866	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 732	23866	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 732
23867	CEFBS_HasDSPR2, // ADDQH_R_W = 733	23867	CEFBS_HasDSPR2, // ADDQH_R_W = 733
23868	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 734	23868	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 734
23869	CEFBS_HasDSPR2, // ADDQH_W = 735	23869	CEFBS_HasDSPR2, // ADDQH_W = 735
23870	CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 736	23870	CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 736
23871	CEFBS_HasDSP, // ADDQ_PH = 737	23871	CEFBS_HasDSP, // ADDQ_PH = 737
23872	CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 738	23872	CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 738
23873	CEFBS_HasDSP, // ADDQ_S_PH = 739	23873	CEFBS_HasDSP, // ADDQ_S_PH = 739
23874	CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 740	23874	CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 740
23875	CEFBS_HasDSP, // ADDQ_S_W = 741	23875	CEFBS_HasDSP, // ADDQ_S_W = 741
23876	CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 742	23876	CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 742
23877	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 743	23877	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 743
23878	CEFBS_HasDSP, // ADDSC = 744	23878	CEFBS_HasDSP, // ADDSC = 744
23879	CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 745	23879	CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 745
23880	CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 746	23880	CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 746
23881	CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 747	23881	CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 747
23882	CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 748	23882	CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 748
23883	CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 749	23883	CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 749
23884	CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 750	23884	CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 750
23885	CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 751	23885	CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 751
23886	CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 752	23886	CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 752
23887	CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 753	23887	CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 753
23888	CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 754	23888	CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 754
23889	CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 755	23889	CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 755
23890	CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 756	23890	CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 756
23891	CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 757	23891	CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 757
23892	CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 758	23892	CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 758
23893	CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 759	23893	CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 759
23894	CEFBS_HasDSPR2, // ADDUH_QB = 760	23894	CEFBS_HasDSPR2, // ADDUH_QB = 760
23895	CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 761	23895	CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 761
23896	CEFBS_HasDSPR2, // ADDUH_R_QB = 762	23896	CEFBS_HasDSPR2, // ADDUH_R_QB = 762
23897	CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 763	23897	CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 763
23898	CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 764	23898	CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 764
23899	CEFBS_HasDSPR2, // ADDU_PH = 765	23899	CEFBS_HasDSPR2, // ADDU_PH = 765
23900	CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 766	23900	CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 766
23901	CEFBS_HasDSP, // ADDU_QB = 767	23901	CEFBS_HasDSP, // ADDU_QB = 767
23902	CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 768	23902	CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 768
23903	CEFBS_HasDSPR2, // ADDU_S_PH = 769	23903	CEFBS_HasDSPR2, // ADDU_S_PH = 769
23904	CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 770	23904	CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 770
23905	CEFBS_HasDSP, // ADDU_S_QB = 771	23905	CEFBS_HasDSP, // ADDU_S_QB = 771
23906	CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 772	23906	CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 772
23907	CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 773	23907	CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 773
23908	CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 774	23908	CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 774
23909	CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 775	23909	CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 775
23910	CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 776	23910	CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 776
23911	CEFBS_HasStdEnc_HasMSA, // ADDV_B = 777	23911	CEFBS_HasStdEnc_HasMSA, // ADDV_B = 777
23912	CEFBS_HasStdEnc_HasMSA, // ADDV_D = 778	23912	CEFBS_HasStdEnc_HasMSA, // ADDV_D = 778
23913	CEFBS_HasStdEnc_HasMSA, // ADDV_H = 779	23913	CEFBS_HasStdEnc_HasMSA, // ADDV_H = 779
23914	CEFBS_HasStdEnc_HasMSA, // ADDV_W = 780	23914	CEFBS_HasStdEnc_HasMSA, // ADDV_W = 780
23915	CEFBS_HasDSP, // ADDWC = 781	23915	CEFBS_HasDSP, // ADDWC = 781
23916	CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 782	23916	CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 782
23917	CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 783	23917	CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 783
23918	CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 784	23918	CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 784
23919	CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 785	23919	CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 785
23920	CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 786	23920	CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 786
23921	CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 787	23921	CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 787
23922	CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 788	23922	CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 788
23923	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 789	23923	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 789
23924	CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 790	23924	CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 790
23925	CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 791	23925	CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 791
23926	CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 792	23926	CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 792
23927	CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 793	23927	CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 793
23928	CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 794	23928	CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 794
23929	CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 795	23929	CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 795
23930	CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 796	23930	CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 796
23931	CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 797	23931	CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 797
23932	CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 798	23932	CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 798
23933	CEFBS_HasStdEnc_NotInMicroMips, // AND = 799	23933	CEFBS_HasStdEnc_NotInMicroMips, // AND = 799
23934	CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 800	23934	CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 800
23935	CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 801	23935	CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 801
23936	CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 802	23936	CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 802
23937	CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 803	23937	CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 803
23938	CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 804	23938	CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 804
23939	CEFBS_HasStdEnc_HasMSA, // ANDI_B = 805	23939	CEFBS_HasStdEnc_HasMSA, // ANDI_B = 805
23940	CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 806	23940	CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 806
23941	CEFBS_InMicroMips_NotMips32r6, // AND_MM = 807	23941	CEFBS_InMicroMips_NotMips32r6, // AND_MM = 807
23942	CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 808	23942	CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 808
23943	CEFBS_HasStdEnc_HasMSA, // AND_V = 809	23943	CEFBS_HasStdEnc_HasMSA, // AND_V = 809
23944	CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 810	23944	CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 810
23945	CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 811	23945	CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 811
23946	CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 812	23946	CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 812
23947	CEFBS_HasDSPR2, // APPEND = 813	23947	CEFBS_HasDSPR2, // APPEND = 813
23948	CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 814	23948	CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 814
23949	CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 815	23949	CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 815
23950	CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 816	23950	CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 816
23951	CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 817	23951	CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 817
23952	CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 818	23952	CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 818
23953	CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 819	23953	CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 819
23954	CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 820	23954	CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 820
23955	CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 821	23955	CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 821
23956	CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 822	23956	CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 822
23957	CEFBS_HasStdEnc_HasMips32r6, // AUI = 823	23957	CEFBS_HasStdEnc_HasMips32r6, // AUI = 823
23958	CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 824	23958	CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 824
23959	CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 825	23959	CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 825
23960	CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 826	23960	CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 826
23961	CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 827	23961	CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 827
23962	CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 828	23962	CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 828
23963	CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 829	23963	CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 829
23964	CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 830	23964	CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 830
23965	CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 831	23965	CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 831
23966	CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 832	23966	CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 832
23967	CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 833	23967	CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 833
23968	CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 834	23968	CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 834
23969	CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 835	23969	CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 835
23970	CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 836	23970	CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 836
23971	CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 837	23971	CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 837
23972	CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 838	23972	CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 838
23973	CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 839	23973	CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 839
23974	CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 840	23974	CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 840
23975	CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 841	23975	CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 841
23976	CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 842	23976	CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 842
23977	CEFBS_InMips16Mode, // AddiuRxImmX16 = 843	23977	CEFBS_InMips16Mode, // AddiuRxImmX16 = 843
23978	CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 844	23978	CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 844
23979	CEFBS_InMips16Mode, // AddiuRxRxImm16 = 845	23979	CEFBS_InMips16Mode, // AddiuRxRxImm16 = 845
23980	CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 846	23980	CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 846
23981	CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 847	23981	CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 847
23982	CEFBS_InMips16Mode, // AddiuSpImm16 = 848	23982	CEFBS_InMips16Mode, // AddiuSpImm16 = 848
23983	CEFBS_InMips16Mode, // AddiuSpImmX16 = 849	23983	CEFBS_InMips16Mode, // AddiuSpImmX16 = 849
23984	CEFBS_InMips16Mode, // AdduRxRyRz16 = 850	23984	CEFBS_InMips16Mode, // AdduRxRyRz16 = 850
23985	CEFBS_InMips16Mode, // AndRxRxRy16 = 851	23985	CEFBS_InMips16Mode, // AndRxRxRy16 = 851
23986	CEFBS_InMicroMips, // B16_MM = 852	23986	CEFBS_InMicroMips, // B16_MM = 852
23987	CEFBS_HasCnMips, // BADDu = 853	23987	CEFBS_HasCnMips, // BADDu = 853
23988	CEFBS_HasStdEnc_HasMips32r6, // BAL = 854	23988	CEFBS_HasStdEnc_HasMips32r6, // BAL = 854
23989	CEFBS_HasStdEnc_HasMips32r6, // BALC = 855	23989	CEFBS_HasStdEnc_HasMips32r6, // BALC = 855
23990	CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 856	23990	CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 856
23991	CEFBS_HasDSPR2, // BALIGN = 857	23991	CEFBS_HasDSPR2, // BALIGN = 857
23992	CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 858	23992	CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 858
23993	CEFBS_HasCnMips, // BBIT0 = 859	23993	CEFBS_HasCnMips, // BBIT0 = 859
23994	CEFBS_HasCnMips, // BBIT032 = 860	23994	CEFBS_HasCnMips, // BBIT032 = 860
23995	CEFBS_HasCnMips, // BBIT1 = 861	23995	CEFBS_HasCnMips, // BBIT1 = 861
23996	CEFBS_HasCnMips, // BBIT132 = 862	23996	CEFBS_HasCnMips, // BBIT132 = 862
23997	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 863	23997	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 863
23998	CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 864	23998	CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 864
23999	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 865	23999	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 865
24000	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 866	24000	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 866
24001	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 867	24001	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 867
24002	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 868	24002	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 868
24003	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 869	24003	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 869
24004	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 870	24004	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 870
24005	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 871	24005	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 871
24006	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 872	24006	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 872
24007	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 873	24007	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 873
24008	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 874	24008	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 874
24009	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 875	24009	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 875
24010	CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 876	24010	CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 876
24011	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 877	24011	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 877
24012	CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 878	24012	CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 878
24013	CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 879	24013	CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 879
24014	CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 880	24014	CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 880
24015	CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 881	24015	CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 881
24016	CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 882	24016	CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 882
24017	CEFBS_HasStdEnc_HasMSA, // BCLR_B = 883	24017	CEFBS_HasStdEnc_HasMSA, // BCLR_B = 883
24018	CEFBS_HasStdEnc_HasMSA, // BCLR_D = 884	24018	CEFBS_HasStdEnc_HasMSA, // BCLR_D = 884
24019	CEFBS_HasStdEnc_HasMSA, // BCLR_H = 885	24019	CEFBS_HasStdEnc_HasMSA, // BCLR_H = 885
24020	CEFBS_HasStdEnc_HasMSA, // BCLR_W = 886	24020	CEFBS_HasStdEnc_HasMSA, // BCLR_W = 886
24021	CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 887	24021	CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 887
24022	CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 888	24022	CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 888
24023	CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 889	24023	CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 889
24024	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 890	24024	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 890
24025	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 891	24025	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 891
24026	CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 892	24026	CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 892
24027	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 893	24027	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 893
24028	CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 894	24028	CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 894
24029	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 895	24029	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 895
24030	CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 896	24030	CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 896
24031	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 897	24031	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 897
24032	CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 898	24032	CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 898
24033	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 899	24033	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 899
24034	CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 900	24034	CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 900
24035	CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 901	24035	CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 901
24036	CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 902	24036	CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 902
24037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 903	24037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 903
24038	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 904	24038	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 904
24039	CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 905	24039	CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 905
24040	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 906	24040	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 906
24041	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 907	24041	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 907
24042	CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 908	24042	CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 908
24043	CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 909	24043	CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 909
24044	CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 910	24044	CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 910
24045	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 911	24045	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 911
24046	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 912	24046	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 912
24047	CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 913	24047	CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 913
24048	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 914	24048	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 914
24049	CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 915	24049	CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 915
24050	CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 916	24050	CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 916
24051	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 917	24051	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 917
24052	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 918	24052	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 918
24053	CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 919	24053	CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 919
24054	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 920	24054	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 920
24055	CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 921	24055	CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 921
24056	CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 922	24056	CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 922
24057	CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 923	24057	CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 923
24058	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 924	24058	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 924
24059	CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 925	24059	CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 925
24060	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 926	24060	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 926
24061	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 927	24061	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 927
24062	CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 928	24062	CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 928
24063	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 929	24063	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 929
24064	CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 930	24064	CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 930
24065	CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 931	24065	CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 931
24066	CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 932	24066	CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 932
24067	CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 933	24067	CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 933
24068	CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 934	24068	CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 934
24069	CEFBS_HasStdEnc_HasMSA, // BINSL_B = 935	24069	CEFBS_HasStdEnc_HasMSA, // BINSL_B = 935
24070	CEFBS_HasStdEnc_HasMSA, // BINSL_D = 936	24070	CEFBS_HasStdEnc_HasMSA, // BINSL_D = 936
24071	CEFBS_HasStdEnc_HasMSA, // BINSL_H = 937	24071	CEFBS_HasStdEnc_HasMSA, // BINSL_H = 937
24072	CEFBS_HasStdEnc_HasMSA, // BINSL_W = 938	24072	CEFBS_HasStdEnc_HasMSA, // BINSL_W = 938
24073	CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 939	24073	CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 939
24074	CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 940	24074	CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 940
24075	CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 941	24075	CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 941
24076	CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 942	24076	CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 942
24077	CEFBS_HasStdEnc_HasMSA, // BINSR_B = 943	24077	CEFBS_HasStdEnc_HasMSA, // BINSR_B = 943
24078	CEFBS_HasStdEnc_HasMSA, // BINSR_D = 944	24078	CEFBS_HasStdEnc_HasMSA, // BINSR_D = 944
24079	CEFBS_HasStdEnc_HasMSA, // BINSR_H = 945	24079	CEFBS_HasStdEnc_HasMSA, // BINSR_H = 945
24080	CEFBS_HasStdEnc_HasMSA, // BINSR_W = 946	24080	CEFBS_HasStdEnc_HasMSA, // BINSR_W = 946
24081	CEFBS_HasDSP, // BITREV = 947	24081	CEFBS_HasDSP, // BITREV = 947
24082	CEFBS_InMicroMips_HasDSP, // BITREV_MM = 948	24082	CEFBS_InMicroMips_HasDSP, // BITREV_MM = 948
24083	CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 949	24083	CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 949
24084	CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 950	24084	CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 950
24085	CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 951	24085	CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 951
24086	CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 952	24086	CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 952
24087	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 953	24087	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 953
24088	CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 954	24088	CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 954
24089	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 955	24089	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 955
24090	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 956	24090	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 956
24091	CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 957	24091	CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 957
24092	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 958	24092	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 958
24093	CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 959	24093	CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 959
24094	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 960	24094	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 960
24095	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 961	24095	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 961
24096	CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 962	24096	CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 962
24097	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 963	24097	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 963
24098	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 964	24098	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 964
24099	CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 965	24099	CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 965
24100	CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 966	24100	CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 966
24101	CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 967	24101	CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 967
24102	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 968	24102	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 968
24103	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 969	24103	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 969
24104	CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 970	24104	CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 970
24105	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 971	24105	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 971
24106	CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 972	24106	CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 972
24107	CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 973	24107	CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 973
24108	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 974	24108	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 974
24109	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 975	24109	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 975
24110	CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 976	24110	CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 976
24111	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 977	24111	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 977
24112	CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 978	24112	CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 978
24113	CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 979	24113	CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 979
24114	CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 980	24114	CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 980
24115	CEFBS_HasStdEnc_HasMSA, // BMZI_B = 981	24115	CEFBS_HasStdEnc_HasMSA, // BMZI_B = 981
24116	CEFBS_HasStdEnc_HasMSA, // BMZ_V = 982	24116	CEFBS_HasStdEnc_HasMSA, // BMZ_V = 982
24117	CEFBS_HasStdEnc_NotInMicroMips, // BNE = 983	24117	CEFBS_HasStdEnc_NotInMicroMips, // BNE = 983
24118	CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 984	24118	CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 984
24119	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 985	24119	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 985
24120	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 986	24120	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 986
24121	CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 987	24121	CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 987
24122	CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 988	24122	CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 988
24123	CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 989	24123	CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 989
24124	CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 990	24124	CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 990
24125	CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 991	24125	CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 991
24126	CEFBS_HasStdEnc_HasMSA, // BNEG_B = 992	24126	CEFBS_HasStdEnc_HasMSA, // BNEG_B = 992
24127	CEFBS_HasStdEnc_HasMSA, // BNEG_D = 993	24127	CEFBS_HasStdEnc_HasMSA, // BNEG_D = 993
24128	CEFBS_HasStdEnc_HasMSA, // BNEG_H = 994	24128	CEFBS_HasStdEnc_HasMSA, // BNEG_H = 994
24129	CEFBS_HasStdEnc_HasMSA, // BNEG_W = 995	24129	CEFBS_HasStdEnc_HasMSA, // BNEG_W = 995
24130	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 996	24130	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 996
24131	CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 997	24131	CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 997
24132	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 998	24132	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 998
24133	CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 999	24133	CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 999
24134	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1000	24134	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1000
24135	CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1001	24135	CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1001
24136	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1002	24136	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1002
24137	CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1003	24137	CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1003
24138	CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1004	24138	CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1004
24139	CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1005	24139	CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1005
24140	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1006	24140	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1006
24141	CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1007	24141	CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1007
24142	CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1008	24142	CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1008
24143	CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1009	24143	CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1009
24144	CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1010	24144	CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1010
24145	CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1011	24145	CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1011
24146	CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1012	24146	CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1012
24147	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1013	24147	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1013
24148	CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1014	24148	CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1014
24149	CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1015	24149	CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1015
24150	CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1016	24150	CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1016
24151	CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1017	24151	CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1017
24152	CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1018	24152	CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1018
24153	CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1019	24153	CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1019
24154	CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1020	24154	CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1020
24155	CEFBS_InMicroMips, // BREAK_MM = 1021	24155	CEFBS_InMicroMips, // BREAK_MM = 1021
24156	CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1022	24156	CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1022
24157	CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1023	24157	CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1023
24158	CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1024	24158	CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1024
24159	CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1025	24159	CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1025
24160	CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1026	24160	CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1026
24161	CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1027	24161	CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1027
24162	CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1028	24162	CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1028
24163	CEFBS_HasStdEnc_HasMSA, // BSET_B = 1029	24163	CEFBS_HasStdEnc_HasMSA, // BSET_B = 1029
24164	CEFBS_HasStdEnc_HasMSA, // BSET_D = 1030	24164	CEFBS_HasStdEnc_HasMSA, // BSET_D = 1030
24165	CEFBS_HasStdEnc_HasMSA, // BSET_H = 1031	24165	CEFBS_HasStdEnc_HasMSA, // BSET_H = 1031
24166	CEFBS_HasStdEnc_HasMSA, // BSET_W = 1032	24166	CEFBS_HasStdEnc_HasMSA, // BSET_W = 1032
24167	CEFBS_HasStdEnc_HasMSA, // BZ_B = 1033	24167	CEFBS_HasStdEnc_HasMSA, // BZ_B = 1033
24168	CEFBS_HasStdEnc_HasMSA, // BZ_D = 1034	24168	CEFBS_HasStdEnc_HasMSA, // BZ_D = 1034
24169	CEFBS_HasStdEnc_HasMSA, // BZ_H = 1035	24169	CEFBS_HasStdEnc_HasMSA, // BZ_H = 1035
24170	CEFBS_HasStdEnc_HasMSA, // BZ_V = 1036	24170	CEFBS_HasStdEnc_HasMSA, // BZ_V = 1036
24171	CEFBS_HasStdEnc_HasMSA, // BZ_W = 1037	24171	CEFBS_HasStdEnc_HasMSA, // BZ_W = 1037
24172	CEFBS_InMips16Mode, // BeqzRxImm16 = 1038	24172	CEFBS_InMips16Mode, // BeqzRxImm16 = 1038
24173	CEFBS_InMips16Mode, // BeqzRxImmX16 = 1039	24173	CEFBS_InMips16Mode, // BeqzRxImmX16 = 1039
24174	CEFBS_InMips16Mode, // Bimm16 = 1040	24174	CEFBS_InMips16Mode, // Bimm16 = 1040
24175	CEFBS_InMips16Mode, // BimmX16 = 1041	24175	CEFBS_InMips16Mode, // BimmX16 = 1041
24176	CEFBS_InMips16Mode, // BnezRxImm16 = 1042	24176	CEFBS_InMips16Mode, // BnezRxImm16 = 1042
24177	CEFBS_InMips16Mode, // BnezRxImmX16 = 1043	24177	CEFBS_InMips16Mode, // BnezRxImmX16 = 1043
24178	CEFBS_InMips16Mode, // Break16 = 1044	24178	CEFBS_InMips16Mode, // Break16 = 1044
24179	CEFBS_InMips16Mode, // Bteqz16 = 1045	24179	CEFBS_InMips16Mode, // Bteqz16 = 1045
24180	CEFBS_InMips16Mode, // BteqzX16 = 1046	24180	CEFBS_InMips16Mode, // BteqzX16 = 1046
24181	CEFBS_InMips16Mode, // Btnez16 = 1047	24181	CEFBS_InMips16Mode, // Btnez16 = 1047
24182	CEFBS_InMips16Mode, // BtnezX16 = 1048	24182	CEFBS_InMips16Mode, // BtnezX16 = 1048
24183	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1049	24183	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1049
24184	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1050	24184	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1050
24185	CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1051	24185	CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1051
24186	CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1052	24186	CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1052
24187	CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1053	24187	CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1053
24188	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1054	24188	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1054
24189	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1055	24189	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1055
24190	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1056	24190	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1056
24191	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1057	24191	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1057
24192	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1058	24192	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1058
24193	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1059	24193	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1059
24194	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1060	24194	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1060
24195	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1061	24195	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1061
24196	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1062	24196	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1062
24197	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1063	24197	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1063
24198	CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1064	24198	CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1064
24199	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1065	24199	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1065
24200	CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1066	24200	CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1066
24201	CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1067	24201	CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1067
24202	CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1068	24202	CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1068
24203	CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1069	24203	CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1069
24204	CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1070	24204	CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1070
24205	CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1071	24205	CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1071
24206	CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1072	24206	CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1072
24207	CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1073	24207	CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1073
24208	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1074	24208	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1074
24209	CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1075	24209	CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1075
24210	CEFBS_InMicroMips, // CFC2_MM = 1076	24210	CEFBS_InMicroMips, // CFC2_MM = 1076
24211	CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1077	24211	CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1077
24212	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1078	24212	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1078
24213	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1079	24213	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1079
24214	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1080	24214	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1080
24215	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1081	24215	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1081
24216	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1082	24216	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1082
24217	CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1083	24217	CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1083
24218	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1084	24218	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1084
24219	CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1085	24219	CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1085
24220	CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1086	24220	CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1086
24221	CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1087	24221	CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1087
24222	CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1088	24222	CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1088
24223	CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1089	24223	CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1089
24224	CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1090	24224	CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1090
24225	CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1091	24225	CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1091
24226	CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1092	24226	CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1092
24227	CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1093	24227	CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1093
24228	CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1094	24228	CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1094
24229	CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1095	24229	CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1095
24230	CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1096	24230	CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1096
24231	CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1097	24231	CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1097
24232	CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1098	24232	CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1098
24233	CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1099	24233	CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1099
24234	CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1100	24234	CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1100
24235	CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1101	24235	CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1101
24236	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1102	24236	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1102
24237	CEFBS_InMicroMips, // CLO_MM = 1103	24237	CEFBS_InMicroMips, // CLO_MM = 1103
24238	CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1104	24238	CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1104
24239	CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1105	24239	CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1105
24240	CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1106	24240	CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1106
24241	CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1107	24241	CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1107
24242	CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1108	24242	CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1108
24243	CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1109	24243	CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1109
24244	CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1110	24244	CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1110
24245	CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1111	24245	CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1111
24246	CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1112	24246	CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1112
24247	CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1113	24247	CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1113
24248	CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1114	24248	CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1114
24249	CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1115	24249	CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1115
24250	CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1116	24250	CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1116
24251	CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1117	24251	CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1117
24252	CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1118	24252	CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1118
24253	CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1119	24253	CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1119
24254	CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1120	24254	CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1120
24255	CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1121	24255	CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1121
24256	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1122	24256	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1122
24257	CEFBS_InMicroMips, // CLZ_MM = 1123	24257	CEFBS_InMicroMips, // CLZ_MM = 1123
24258	CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1124	24258	CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1124
24259	CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1125	24259	CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1125
24260	CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1126	24260	CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1126
24261	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1127	24261	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1127
24262	CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1128	24262	CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1128
24263	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1129	24263	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1129
24264	CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1130	24264	CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1130
24265	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1131	24265	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1131
24266	CEFBS_HasDSP, // CMPGU_EQ_QB = 1132	24266	CEFBS_HasDSP, // CMPGU_EQ_QB = 1132
24267	CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1133	24267	CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1133
24268	CEFBS_HasDSP, // CMPGU_LE_QB = 1134	24268	CEFBS_HasDSP, // CMPGU_LE_QB = 1134
24269	CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1135	24269	CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1135
24270	CEFBS_HasDSP, // CMPGU_LT_QB = 1136	24270	CEFBS_HasDSP, // CMPGU_LT_QB = 1136
24271	CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1137	24271	CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1137
24272	CEFBS_HasDSP, // CMPU_EQ_QB = 1138	24272	CEFBS_HasDSP, // CMPU_EQ_QB = 1138
24273	CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1139	24273	CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1139
24274	CEFBS_HasDSP, // CMPU_LE_QB = 1140	24274	CEFBS_HasDSP, // CMPU_LE_QB = 1140
24275	CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1141	24275	CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1141
24276	CEFBS_HasDSP, // CMPU_LT_QB = 1142	24276	CEFBS_HasDSP, // CMPU_LT_QB = 1142
24277	CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1143	24277	CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1143
24278	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1144	24278	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1144
24279	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1145	24279	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1145
24280	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1146	24280	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1146
24281	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1147	24281	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1147
24282	CEFBS_HasDSP, // CMP_EQ_PH = 1148	24282	CEFBS_HasDSP, // CMP_EQ_PH = 1148
24283	CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1149	24283	CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1149
24284	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1150	24284	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1150
24285	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1151	24285	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1151
24286	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1152	24286	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1152
24287	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1153	24287	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1153
24288	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1154	24288	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1154
24289	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1155	24289	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1155
24290	CEFBS_HasDSP, // CMP_LE_PH = 1156	24290	CEFBS_HasDSP, // CMP_LE_PH = 1156
24291	CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1157	24291	CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1157
24292	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1158	24292	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1158
24293	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1159	24293	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1159
24294	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1160	24294	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1160
24295	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1161	24295	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1161
24296	CEFBS_HasDSP, // CMP_LT_PH = 1162	24296	CEFBS_HasDSP, // CMP_LT_PH = 1162
24297	CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1163	24297	CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1163
24298	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1164	24298	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1164
24299	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1165	24299	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1165
24300	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1166	24300	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1166
24301	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1167	24301	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1167
24302	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1168	24302	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1168
24303	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1169	24303	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1169
24304	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1170	24304	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1170
24305	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1171	24305	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1171
24306	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1172	24306	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1172
24307	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1173	24307	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1173
24308	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1174	24308	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1174
24309	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1175	24309	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1175
24310	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1176	24310	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1176
24311	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1177	24311	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1177
24312	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1178	24312	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1178
24313	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1179	24313	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1179
24314	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1180	24314	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1180
24315	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1181	24315	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1181
24316	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1182	24316	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1182
24317	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1183	24317	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1183
24318	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1184	24318	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1184
24319	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1185	24319	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1185
24320	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1186	24320	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1186
24321	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1187	24321	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1187
24322	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1188	24322	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1188
24323	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1189	24323	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1189
24324	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1190	24324	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1190
24325	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1191	24325	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1191
24326	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1192	24326	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1192
24327	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1193	24327	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1193
24328	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1194	24328	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1194
24329	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1195	24329	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1195
24330	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1196	24330	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1196
24331	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1197	24331	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1197
24332	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1198	24332	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1198
24333	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1199	24333	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1199
24334	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1200	24334	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1200
24335	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1201	24335	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1201
24336	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1202	24336	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1202
24337	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1203	24337	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1203
24338	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1204	24338	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1204
24339	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1205	24339	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1205
24340	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1206	24340	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1206
24341	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1207	24341	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1207
24342	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1208	24342	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1208
24343	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1209	24343	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1209
24344	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1210	24344	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1210
24345	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1211	24345	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1211
24346	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1212	24346	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1212
24347	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1213	24347	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1213
24348	CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1214	24348	CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1214
24349	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1215	24349	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1215
24350	CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1216	24350	CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1216
24351	CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1217	24351	CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1217
24352	CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1218	24352	CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1218
24353	CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1219	24353	CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1219
24354	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1220	24354	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1220
24355	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1221	24355	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1221
24356	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1222	24356	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1222
24357	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1223	24357	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1223
24358	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1224	24358	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1224
24359	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1225	24359	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1225
24360	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1226	24360	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1226
24361	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1227	24361	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1227
24362	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1228	24362	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1228
24363	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1229	24363	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1229
24364	CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1230	24364	CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1230
24365	CEFBS_InMicroMips, // CTC2_MM = 1231	24365	CEFBS_InMicroMips, // CTC2_MM = 1231
24366	CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1232	24366	CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1232
24367	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1233	24367	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1233
24368	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1234	24368	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1234
24369	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1235	24369	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1235
24370	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1236	24370	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1236
24371	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1237	24371	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1237
24372	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1238	24372	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1238
24373	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1239	24373	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1239
24374	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1240	24374	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1240
24375	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1241	24375	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1241
24376	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1242	24376	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1242
24377	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1243	24377	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1243
24378	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1244	24378	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1244
24379	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1245	24379	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1245
24380	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1246	24380	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1246
24381	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1247	24381	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1247
24382	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1248	24382	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1248
24383	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1249	24383	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1249
24384	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1250	24384	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1250
24385	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1251	24385	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1251
24386	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1252	24386	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1252
24387	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1253	24387	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1253
24388	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1254	24388	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1254
24389	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1255	24389	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1255
24390	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1256	24390	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1256
24391	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1257	24391	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1257
24392	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1258	24392	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1258
24393	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1259	24393	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1259
24394	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1260	24394	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1260
24395	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1261	24395	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1261
24396	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1262	24396	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1262
24397	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1263	24397	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1263
24398	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1264	24398	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1264
24399	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1265	24399	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1265
24400	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1266	24400	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1266
24401	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1267	24401	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1267
24402	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1268	24402	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1268
24403	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1269	24403	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1269
24404	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1270	24404	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1270
24405	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1271	24405	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1271
24406	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1272	24406	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1272
24407	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1273	24407	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1273
24408	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1274	24408	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1274
24409	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1275	24409	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1275
24410	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1276	24410	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1276
24411	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1277	24411	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1277
24412	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1278	24412	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1278
24413	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1279	24413	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1279
24414	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1280	24414	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1280
24415	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1281	24415	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1281
24416	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1282	24416	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1282
24417	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1283	24417	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1283
24418	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1284	24418	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1284
24419	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1285	24419	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1285
24420	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1286	24420	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1286
24421	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1287	24421	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1287
24422	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1288	24422	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1288
24423	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1289	24423	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1289
24424	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1290	24424	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1290
24425	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1291	24425	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1291
24426	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1292	24426	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1292
24427	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1293	24427	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1293
24428	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1294	24428	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1294
24429	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1295	24429	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1295
24430	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1296	24430	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1296
24431	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1297	24431	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1297
24432	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1298	24432	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1298
24433	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1299	24433	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1299
24434	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1300	24434	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1300
24435	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1301	24435	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1301
24436	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1302	24436	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1302
24437	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1303	24437	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1303
24438	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1304	24438	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1304
24439	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1305	24439	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1305
24440	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1306	24440	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1306
24441	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1307	24441	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1307
24442	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1308	24442	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1308
24443	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1309	24443	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1309
24444	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1310	24444	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1310
24445	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1311	24445	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1311
24446	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1312	24446	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1312
24447	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1313	24447	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1313
24448	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1314	24448	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1314
24449	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1315	24449	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1315
24450	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1316	24450	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1316
24451	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1317	24451	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1317
24452	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1318	24452	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1318
24453	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1319	24453	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1319
24454	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1320	24454	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1320
24455	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1321	24455	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1321
24456	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1322	24456	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1322
24457	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1323	24457	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1323
24458	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1324	24458	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1324
24459	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1325	24459	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1325
24460	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1326	24460	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1326
24461	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1327	24461	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1327
24462	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1328	24462	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1328
24463	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1329	24463	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1329
24464	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1330	24464	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1330
24465	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1331	24465	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1331
24466	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1332	24466	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1332
24467	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1333	24467	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1333
24468	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1334	24468	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1334
24469	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1335	24469	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1335
24470	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1336	24470	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1336
24471	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1337	24471	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1337
24472	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1338	24472	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1338
24473	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1339	24473	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1339
24474	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1340	24474	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1340
24475	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1341	24475	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1341
24476	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1342	24476	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1342
24477	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1343	24477	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1343
24478	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1344	24478	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1344
24479	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1345	24479	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1345
24480	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1346	24480	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1346
24481	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1347	24481	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1347
24482	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1348	24482	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1348
24483	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1349	24483	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1349
24484	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1350	24484	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1350
24485	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1351	24485	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1351
24486	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1352	24486	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1352
24487	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1353	24487	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1353
24488	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1354	24488	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1354
24489	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1355	24489	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1355
24490	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1356	24490	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1356
24491	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1357	24491	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1357
24492	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1358	24492	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1358
24493	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1359	24493	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1359
24494	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1360	24494	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1360
24495	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1361	24495	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1361
24496	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1362	24496	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1362
24497	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1363	24497	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1363
24498	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1364	24498	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1364
24499	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1365	24499	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1365
24500	CEFBS_InMips16Mode, // CmpRxRy16 = 1366	24500	CEFBS_InMips16Mode, // CmpRxRy16 = 1366
24501	CEFBS_InMips16Mode, // CmpiRxImm16 = 1367	24501	CEFBS_InMips16Mode, // CmpiRxImm16 = 1367
24502	CEFBS_InMips16Mode, // CmpiRxImmX16 = 1368	24502	CEFBS_InMips16Mode, // CmpiRxImmX16 = 1368
24503	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1369	24503	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1369
24504	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1370	24504	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1370
24505	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1371	24505	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1371
24506	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1372	24506	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1372
24507	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1373	24507	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1373
24508	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1374	24508	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1374
24509	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1375	24509	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1375
24510	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1376	24510	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1376
24511	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1377	24511	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1377
24512	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1378	24512	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1378
24513	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1379	24513	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1379
24514	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1380	24514	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1380
24515	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1381	24515	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1381
24516	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1382	24516	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1382
24517	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1383	24517	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1383
24518	CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1384	24518	CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1384
24519	CEFBS_InMicroMips, // DERET_MM = 1385	24519	CEFBS_InMicroMips, // DERET_MM = 1385
24520	CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1386	24520	CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1386
24521	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1387	24521	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1387
24522	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1388	24522	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1388
24523	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1389	24523	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1389
24524	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1390	24524	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1390
24525	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1391	24525	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1391
24526	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1392	24526	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1392
24527	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1393	24527	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1393
24528	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1394	24528	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1394
24529	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1395	24529	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1395
24530	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1396	24530	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1396
24531	CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1397	24531	CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1397
24532	CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1398	24532	CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1398
24533	CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1399	24533	CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1399
24534	CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1400	24534	CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1400
24535	CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1401	24535	CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1401
24536	CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1402	24536	CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1402
24537	CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1403	24537	CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1403
24538	CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1404	24538	CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1404
24539	CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1405	24539	CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1405
24540	CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1406	24540	CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1406
24541	CEFBS_InMicroMips, // DI_MM = 1407	24541	CEFBS_InMicroMips, // DI_MM = 1407
24542	CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1408	24542	CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1408
24543	CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1409	24543	CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1409
24544	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1410	24544	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1410
24545	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1411	24545	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1411
24546	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1412	24546	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1412
24547	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1413	24547	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1413
24548	CEFBS_HasCnMips, // DMFC2_OCTEON = 1414	24548	CEFBS_HasCnMips, // DMFC2_OCTEON = 1414
24549	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1415	24549	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1415
24550	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1416	24550	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1416
24551	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1417	24551	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1417
24552	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1418	24552	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1418
24553	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1419	24553	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1419
24554	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1420	24554	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1420
24555	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1421	24555	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1421
24556	CEFBS_HasCnMips, // DMTC2_OCTEON = 1422	24556	CEFBS_HasCnMips, // DMTC2_OCTEON = 1422
24557	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1423	24557	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1423
24558	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1424	24558	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1424
24559	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1425	24559	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1425
24560	CEFBS_HasCnMips, // DMUL = 1426	24560	CEFBS_HasCnMips, // DMUL = 1426
24561	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1427	24561	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1427
24562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1428	24562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1428
24563	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1429	24563	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1429
24564	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1430	24564	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1430
24565	CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1431	24565	CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1431
24566	CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1432	24566	CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1432
24567	CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1433	24567	CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1433
24568	CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1434	24568	CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1434
24569	CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1435	24569	CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1435
24570	CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1436	24570	CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1436
24571	CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1437	24571	CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1437
24572	CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1438	24572	CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1438
24573	CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1439	24573	CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1439
24574	CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1440	24574	CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1440
24575	CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1441	24575	CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1441
24576	CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1442	24576	CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1442
24577	CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1443	24577	CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1443
24578	CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1444	24578	CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1444
24579	CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1445	24579	CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1445
24580	CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1446	24580	CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1446
24581	CEFBS_HasDSP, // DPAQ_SA_L_W = 1447	24581	CEFBS_HasDSP, // DPAQ_SA_L_W = 1447
24582	CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1448	24582	CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1448
24583	CEFBS_HasDSP, // DPAQ_S_W_PH = 1449	24583	CEFBS_HasDSP, // DPAQ_S_W_PH = 1449
24584	CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1450	24584	CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1450
24585	CEFBS_HasDSP, // DPAU_H_QBL = 1451	24585	CEFBS_HasDSP, // DPAU_H_QBL = 1451
24586	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1452	24586	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1452
24587	CEFBS_HasDSP, // DPAU_H_QBR = 1453	24587	CEFBS_HasDSP, // DPAU_H_QBR = 1453
24588	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1454	24588	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1454
24589	CEFBS_HasDSPR2, // DPAX_W_PH = 1455	24589	CEFBS_HasDSPR2, // DPAX_W_PH = 1455
24590	CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1456	24590	CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1456
24591	CEFBS_HasDSPR2, // DPA_W_PH = 1457	24591	CEFBS_HasDSPR2, // DPA_W_PH = 1457
24592	CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1458	24592	CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1458
24593	CEFBS_HasCnMips, // DPOP = 1459	24593	CEFBS_HasCnMips, // DPOP = 1459
24594	CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1460	24594	CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1460
24595	CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1461	24595	CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1461
24596	CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1462	24596	CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1462
24597	CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1463	24597	CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1463
24598	CEFBS_HasDSP, // DPSQ_SA_L_W = 1464	24598	CEFBS_HasDSP, // DPSQ_SA_L_W = 1464
24599	CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1465	24599	CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1465
24600	CEFBS_HasDSP, // DPSQ_S_W_PH = 1466	24600	CEFBS_HasDSP, // DPSQ_S_W_PH = 1466
24601	CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1467	24601	CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1467
24602	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1468	24602	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1468
24603	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1469	24603	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1469
24604	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1470	24604	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1470
24605	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1471	24605	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1471
24606	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1472	24606	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1472
24607	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1473	24607	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1473
24608	CEFBS_HasDSP, // DPSU_H_QBL = 1474	24608	CEFBS_HasDSP, // DPSU_H_QBL = 1474
24609	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1475	24609	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1475
24610	CEFBS_HasDSP, // DPSU_H_QBR = 1476	24610	CEFBS_HasDSP, // DPSU_H_QBR = 1476
24611	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1477	24611	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1477
24612	CEFBS_HasDSPR2, // DPSX_W_PH = 1478	24612	CEFBS_HasDSPR2, // DPSX_W_PH = 1478
24613	CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1479	24613	CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1479
24614	CEFBS_HasDSPR2, // DPS_W_PH = 1480	24614	CEFBS_HasDSPR2, // DPS_W_PH = 1480
24615	CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1481	24615	CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1481
24616	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1482	24616	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1482
24617	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1483	24617	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1483
24618	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1484	24618	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1484
24619	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1485	24619	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1485
24620	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1486	24620	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1486
24621	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1487	24621	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1487
24622	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1488	24622	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1488
24623	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1489	24623	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1489
24624	CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1490	24624	CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1490
24625	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1491	24625	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1491
24626	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1492	24626	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1492
24627	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1493	24627	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1493
24628	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1494	24628	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1494
24629	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1495	24629	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1495
24630	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1496	24630	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1496
24631	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1497	24631	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1497
24632	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1498	24632	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1498
24633	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1499	24633	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1499
24634	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1500	24634	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1500
24635	CEFBS_HasStdEnc_HasMips32r6, // DVP = 1501	24635	CEFBS_HasStdEnc_HasMips32r6, // DVP = 1501
24636	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1502	24636	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1502
24637	CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1503	24637	CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1503
24638	CEFBS_InMips16Mode, // DivRxRy16 = 1504	24638	CEFBS_InMips16Mode, // DivRxRy16 = 1504
24639	CEFBS_InMips16Mode, // DivuRxRy16 = 1505	24639	CEFBS_InMips16Mode, // DivuRxRy16 = 1505
24640	CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1506	24640	CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1506
24641	CEFBS_InMicroMips, // EHB_MM = 1507	24641	CEFBS_InMicroMips, // EHB_MM = 1507
24642	CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1508	24642	CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1508
24643	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1509	24643	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1509
24644	CEFBS_InMicroMips, // EI_MM = 1510	24644	CEFBS_InMicroMips, // EI_MM = 1510
24645	CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1511	24645	CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1511
24646	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1512	24646	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1512
24647	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1513	24647	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1513
24648	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1514	24648	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1514
24649	CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1515	24649	CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1515
24650	CEFBS_InMicroMips, // ERET_MM = 1516	24650	CEFBS_InMicroMips, // ERET_MM = 1516
24651	CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1517	24651	CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1517
24652	CEFBS_HasStdEnc_HasMips32r6, // EVP = 1518	24652	CEFBS_HasStdEnc_HasMips32r6, // EVP = 1518
24653	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1519	24653	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1519
24654	CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1520	24654	CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1520
24655	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1521	24655	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1521
24656	CEFBS_HasDSP, // EXTP = 1522	24656	CEFBS_HasDSP, // EXTP = 1522
24657	CEFBS_HasDSP, // EXTPDP = 1523	24657	CEFBS_HasDSP, // EXTPDP = 1523
24658	CEFBS_HasDSP, // EXTPDPV = 1524	24658	CEFBS_HasDSP, // EXTPDPV = 1524
24659	CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1525	24659	CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1525
24660	CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1526	24660	CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1526
24661	CEFBS_HasDSP, // EXTPV = 1527	24661	CEFBS_HasDSP, // EXTPV = 1527
24662	CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1528	24662	CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1528
24663	CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1529	24663	CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1529
24664	CEFBS_HasDSP, // EXTRV_RS_W = 1530	24664	CEFBS_HasDSP, // EXTRV_RS_W = 1530
24665	CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1531	24665	CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1531
24666	CEFBS_HasDSP, // EXTRV_R_W = 1532	24666	CEFBS_HasDSP, // EXTRV_R_W = 1532
24667	CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1533	24667	CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1533
24668	CEFBS_HasDSP, // EXTRV_S_H = 1534	24668	CEFBS_HasDSP, // EXTRV_S_H = 1534
24669	CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1535	24669	CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1535
24670	CEFBS_HasDSP, // EXTRV_W = 1536	24670	CEFBS_HasDSP, // EXTRV_W = 1536
24671	CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1537	24671	CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1537
24672	CEFBS_HasDSP, // EXTR_RS_W = 1538	24672	CEFBS_HasDSP, // EXTR_RS_W = 1538
24673	CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1539	24673	CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1539
24674	CEFBS_HasDSP, // EXTR_R_W = 1540	24674	CEFBS_HasDSP, // EXTR_R_W = 1540
24675	CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1541	24675	CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1541
24676	CEFBS_HasDSP, // EXTR_S_H = 1542	24676	CEFBS_HasDSP, // EXTR_S_H = 1542
24677	CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1543	24677	CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1543
24678	CEFBS_HasDSP, // EXTR_W = 1544	24678	CEFBS_HasDSP, // EXTR_W = 1544
24679	CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1545	24679	CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1545
24680	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1546	24680	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1546
24681	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1547	24681	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1547
24682	CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1548	24682	CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1548
24683	CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1549	24683	CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1549
24684	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1550	24684	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1550
24685	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1551	24685	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1551
24686	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1552	24686	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1552
24687	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1553	24687	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1553
24688	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1554	24688	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1554
24689	CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1555	24689	CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1555
24690	CEFBS_HasStdEnc_HasMSA, // FADD_D = 1556	24690	CEFBS_HasStdEnc_HasMSA, // FADD_D = 1556
24691	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1557	24691	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1557
24692	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1558	24692	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1558
24693	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1559	24693	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1559
24694	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1560	24694	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1560
24695	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1561	24695	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1561
24696	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1562	24696	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1562
24697	CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1563	24697	CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1563
24698	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1564	24698	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1564
24699	CEFBS_HasStdEnc_HasMSA, // FADD_W = 1565	24699	CEFBS_HasStdEnc_HasMSA, // FADD_W = 1565
24700	CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1566	24700	CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1566
24701	CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1567	24701	CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1567
24702	CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1568	24702	CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1568
24703	CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1569	24703	CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1569
24704	CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1570	24704	CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1570
24705	CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1571	24705	CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1571
24706	CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1572	24706	CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1572
24707	CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1573	24707	CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1573
24708	CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1574	24708	CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1574
24709	CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1575	24709	CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1575
24710	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1576	24710	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1576
24711	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1577	24711	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1577
24712	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1578	24712	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1578
24713	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1579	24713	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1579
24714	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1580	24714	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1580
24715	CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1581	24715	CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1581
24716	CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1582	24716	CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1582
24717	CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1583	24717	CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1583
24718	CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1584	24718	CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1584
24719	CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1585	24719	CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1585
24720	CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1586	24720	CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1586
24721	CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1587	24721	CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1587
24722	CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1588	24722	CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1588
24723	CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1589	24723	CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1589
24724	CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1590	24724	CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1590
24725	CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1591	24725	CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1591
24726	CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1592	24726	CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1592
24727	CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1593	24727	CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1593
24728	CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1594	24728	CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1594
24729	CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1595	24729	CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1595
24730	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1596	24730	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1596
24731	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1597	24731	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1597
24732	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1598	24732	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1598
24733	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1599	24733	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1599
24734	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1600	24734	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1600
24735	CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1601	24735	CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1601
24736	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1602	24736	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1602
24737	CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1603	24737	CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1603
24738	CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1604	24738	CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1604
24739	CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1605	24739	CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1605
24740	CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1606	24740	CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1606
24741	CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1607	24741	CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1607
24742	CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1608	24742	CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1608
24743	CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1609	24743	CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1609
24744	CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1610	24744	CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1610
24745	CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1611	24745	CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1611
24746	CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1612	24746	CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1612
24747	CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1613	24747	CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1613
24748	CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1614	24748	CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1614
24749	CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1615	24749	CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1615
24750	CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1616	24750	CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1616
24751	CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1617	24751	CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1617
24752	CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1618	24752	CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1618
24753	CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1619	24753	CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1619
24754	CEFBS_HasStdEnc_HasMSA, // FILL_B = 1620	24754	CEFBS_HasStdEnc_HasMSA, // FILL_B = 1620
24755	CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1621	24755	CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1621
24756	CEFBS_HasStdEnc_HasMSA, // FILL_H = 1622	24756	CEFBS_HasStdEnc_HasMSA, // FILL_H = 1622
24757	CEFBS_HasStdEnc_HasMSA, // FILL_W = 1623	24757	CEFBS_HasStdEnc_HasMSA, // FILL_W = 1623
24758	CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1624	24758	CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1624
24759	CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1625	24759	CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1625
24760	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1626	24760	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1626
24761	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1627	24761	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1627
24762	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1628	24762	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1628
24763	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1629	24763	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1629
24764	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1630	24764	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1630
24765	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1631	24765	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1631
24766	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1632	24766	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1632
24767	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1633	24767	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1633
24768	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1634	24768	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1634
24769	CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1635	24769	CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1635
24770	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1636	24770	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1636
24771	CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1637	24771	CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1637
24772	CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1638	24772	CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1638
24773	CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1639	24773	CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1639
24774	CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1640	24774	CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1640
24775	CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1641	24775	CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1641
24776	CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1642	24776	CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1642
24777	CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1643	24777	CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1643
24778	CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1644	24778	CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1644
24779	CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1645	24779	CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1645
24780	CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1646	24780	CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1646
24781	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1647	24781	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1647
24782	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1648	24782	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1648
24783	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1649	24783	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1649
24784	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1650	24784	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1650
24785	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1651	24785	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1651
24786	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1652	24786	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1652
24787	CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1653	24787	CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1653
24788	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1654	24788	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1654
24789	CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1655	24789	CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1655
24790	CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1656	24790	CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1656
24791	CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1657	24791	CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1657
24792	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1658	24792	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1658
24793	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1659	24793	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1659
24794	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1660	24794	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1660
24795	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1661	24795	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1661
24796	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1662	24796	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1662
24797	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1663	24797	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1663
24798	CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1664	24798	CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1664
24799	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1665	24799	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1665
24800	CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1666	24800	CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1666
24801	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1667	24801	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1667
24802	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1668	24802	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1668
24803	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1669	24803	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1669
24804	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1670	24804	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1670
24805	CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1671	24805	CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1671
24806	CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1672	24806	CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1672
24807	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1673	24807	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1673
24808	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1674	24808	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1674
24809	CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1675	24809	CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1675
24810	CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1676	24810	CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1676
24811	CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1677	24811	CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1677
24812	CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1678	24812	CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1678
24813	CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1679	24813	CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1679
24814	CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1680	24814	CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1680
24815	CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1681	24815	CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1681
24816	CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1682	24816	CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1682
24817	CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1683	24817	CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1683
24818	CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1684	24818	CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1684
24819	CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1685	24819	CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1685
24820	CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1686	24820	CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1686
24821	CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1687	24821	CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1687
24822	CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1688	24822	CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1688
24823	CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1689	24823	CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1689
24824	CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1690	24824	CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1690
24825	CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1691	24825	CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1691
24826	CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1692	24826	CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1692
24827	CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1693	24827	CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1693
24828	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1694	24828	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1694
24829	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1695	24829	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1695
24830	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1696	24830	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1696
24831	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1697	24831	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1697
24832	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1698	24832	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1698
24833	CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1699	24833	CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1699
24834	CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1700	24834	CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1700
24835	CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1701	24835	CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1701
24836	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1702	24836	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1702
24837	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1703	24837	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1703
24838	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1704	24838	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1704
24839	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1705	24839	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1705
24840	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1706	24840	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1706
24841	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1707	24841	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1707
24842	CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1708	24842	CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1708
24843	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1709	24843	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1709
24844	CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1710	24844	CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1710
24845	CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1711	24845	CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1711
24846	CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1712	24846	CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1712
24847	CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1713	24847	CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1713
24848	CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1714	24848	CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1714
24849	CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1715	24849	CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1715
24850	CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1716	24850	CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1716
24851	CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1717	24851	CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1717
24852	CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1718	24852	CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1718
24853	CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1719	24853	CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1719
24854	CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1720	24854	CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1720
24855	CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1721	24855	CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1721
24856	CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1722	24856	CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1722
24857	CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1723	24857	CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1723
24858	CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1724	24858	CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1724
24859	CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1725	24859	CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1725
24860	CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1726	24860	CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1726
24861	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1727	24861	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1727
24862	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1728	24862	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1728
24863	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1729	24863	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1729
24864	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1730	24864	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1730
24865	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1731	24865	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1731
24866	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1732	24866	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1732
24867	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1733	24867	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1733
24868	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1734	24868	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1734
24869	CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1735	24869	CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1735
24870	CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1736	24870	CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1736
24871	CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1737	24871	CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1737
24872	CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1738	24872	CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1738
24873	CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1739	24873	CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1739
24874	CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1740	24874	CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1740
24875	CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1741	24875	CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1741
24876	CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1742	24876	CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1742
24877	CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1743	24877	CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1743
24878	CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1744	24878	CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1744
24879	CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1745	24879	CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1745
24880	CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1746	24880	CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1746
24881	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1747	24881	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1747
24882	CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1748	24882	CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1748
24883	CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1749	24883	CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1749
24884	CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1750	24884	CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1750
24885	CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1751	24885	CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1751
24886	CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1752	24886	CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1752
24887	CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1753	24887	CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1753
24888	CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1754	24888	CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1754
24889	CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1755	24889	CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1755
24890	CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1756	24890	CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1756
24891	CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1757	24891	CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1757
24892	CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1758	24892	CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1758
24893	CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1759	24893	CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1759
24894	CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1760	24894	CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1760
24895	CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1761	24895	CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1761
24896	CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1762	24896	CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1762
24897	CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1763	24897	CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1763
24898	CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1764	24898	CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1764
24899	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1765	24899	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1765
24900	CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1766	24900	CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1766
24901	CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1767	24901	CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1767
24902	CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1768	24902	CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1768
24903	CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1769	24903	CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1769
24904	CEFBS_HasDSP, // INSV = 1770	24904	CEFBS_HasDSP, // INSV = 1770
24905	CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1771	24905	CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1771
24906	CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1772	24906	CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1772
24907	CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1773	24907	CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1773
24908	CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1774	24908	CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1774
24909	CEFBS_InMicroMips_HasDSP, // INSV_MM = 1775	24909	CEFBS_InMicroMips_HasDSP, // INSV_MM = 1775
24910	CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1776	24910	CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1776
24911	CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1777	24911	CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1777
24912	CEFBS_HasStdEnc_NotInMicroMips, // J = 1778	24912	CEFBS_HasStdEnc_NotInMicroMips, // J = 1778
24913	CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1779	24913	CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1779
24914	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1780	24914	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1780
24915	CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1781	24915	CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1781
24916	CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1782	24916	CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1782
24917	CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1783	24917	CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1783
24918	CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1784	24918	CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1784
24919	CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1785	24919	CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1785
24920	CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1786	24920	CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1786
24921	CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1787	24921	CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1787
24922	CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1788	24922	CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1788
24923	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1789	24923	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1789
24924	CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1790	24924	CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1790
24925	CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1791	24925	CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1791
24926	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1792	24926	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1792
24927	CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1793	24927	CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1793
24928	CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1794	24928	CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1794
24929	CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1795	24929	CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1795
24930	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1796	24930	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1796
24931	CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1797	24931	CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1797
24932	CEFBS_HasStdEnc_HasMips32r6, // JIC = 1798	24932	CEFBS_HasStdEnc_HasMips32r6, // JIC = 1798
24933	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1799	24933	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1799
24934	CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1800	24934	CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1800
24935	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1801	24935	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1801
24936	CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1802	24936	CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1802
24937	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1803	24937	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1803
24938	CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1804	24938	CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1804
24939	CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1805	24939	CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1805
24940	CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1806	24940	CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1806
24941	CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1807	24941	CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1807
24942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1808	24942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1808
24943	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1809	24943	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1809
24944	CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1810	24944	CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1810
24945	CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1811	24945	CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1811
24946	CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1812	24946	CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1812
24947	CEFBS_InMicroMips_NotMips32r6, // J_MM = 1813	24947	CEFBS_InMicroMips_NotMips32r6, // J_MM = 1813
24948	CEFBS_InMips16Mode, // Jal16 = 1814	24948	CEFBS_InMips16Mode, // Jal16 = 1814
24949	CEFBS_InMips16Mode, // JalB16 = 1815	24949	CEFBS_InMips16Mode, // JalB16 = 1815
24950	CEFBS_InMips16Mode, // JrRa16 = 1816	24950	CEFBS_InMips16Mode, // JrRa16 = 1816
24951	CEFBS_InMips16Mode, // JrcRa16 = 1817	24951	CEFBS_InMips16Mode, // JrcRa16 = 1817
24952	CEFBS_InMips16Mode, // JrcRx16 = 1818	24952	CEFBS_InMips16Mode, // JrcRx16 = 1818
24953	CEFBS_InMips16Mode, // JumpLinkReg16 = 1819	24953	CEFBS_InMips16Mode, // JumpLinkReg16 = 1819
24954	CEFBS_HasStdEnc_NotInMicroMips, // LB = 1820	24954	CEFBS_HasStdEnc_NotInMicroMips, // LB = 1820
24955	CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1821	24955	CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1821
24956	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1822	24956	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1822
24957	CEFBS_InMicroMips_HasEVA, // LBE_MM = 1823	24957	CEFBS_InMicroMips_HasEVA, // LBE_MM = 1823
24958	CEFBS_InMicroMips, // LBU16_MM = 1824	24958	CEFBS_InMicroMips, // LBU16_MM = 1824
24959	CEFBS_HasDSP, // LBUX = 1825	24959	CEFBS_HasDSP, // LBUX = 1825
24960	CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1826	24960	CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1826
24961	CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1827	24961	CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1827
24962	CEFBS_InMicroMips, // LB_MM = 1828	24962	CEFBS_InMicroMips, // LB_MM = 1828
24963	CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1829	24963	CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1829
24964	CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1830	24964	CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1830
24965	CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1831	24965	CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1831
24966	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1832	24966	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1832
24967	CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1833	24967	CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1833
24968	CEFBS_InMicroMips, // LBu_MM = 1834	24968	CEFBS_InMicroMips, // LBu_MM = 1834
24969	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1835	24969	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1835
24970	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1836	24970	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1836
24971	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1837	24971	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1837
24972	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1838	24972	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1838
24973	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1839	24973	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1839
24974	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1840	24974	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1840
24975	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1841	24975	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1841
24976	CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1842	24976	CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1842
24977	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1843	24977	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1843
24978	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1844	24978	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1844
24979	CEFBS_HasStdEnc_HasMSA, // LDI_B = 1845	24979	CEFBS_HasStdEnc_HasMSA, // LDI_B = 1845
24980	CEFBS_HasStdEnc_HasMSA, // LDI_D = 1846	24980	CEFBS_HasStdEnc_HasMSA, // LDI_D = 1846
24981	CEFBS_HasStdEnc_HasMSA, // LDI_H = 1847	24981	CEFBS_HasStdEnc_HasMSA, // LDI_H = 1847
24982	CEFBS_HasStdEnc_HasMSA, // LDI_W = 1848	24982	CEFBS_HasStdEnc_HasMSA, // LDI_W = 1848
24983	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1849	24983	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1849
24984	CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1850	24984	CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1850
24985	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1851	24985	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1851
24986	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1852	24986	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1852
24987	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1853	24987	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1853
24988	CEFBS_HasStdEnc_HasMSA, // LD_B = 1854	24988	CEFBS_HasStdEnc_HasMSA, // LD_B = 1854
24989	CEFBS_HasStdEnc_HasMSA, // LD_D = 1855	24989	CEFBS_HasStdEnc_HasMSA, // LD_D = 1855
24990	CEFBS_HasStdEnc_HasMSA, // LD_H = 1856	24990	CEFBS_HasStdEnc_HasMSA, // LD_H = 1856
24991	CEFBS_HasStdEnc_HasMSA, // LD_W = 1857	24991	CEFBS_HasStdEnc_HasMSA, // LD_W = 1857
24992	CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1858	24992	CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1858
24993	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1859	24993	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1859
24994	CEFBS_InMicroMips, // LEA_ADDiu_MM = 1860	24994	CEFBS_InMicroMips, // LEA_ADDiu_MM = 1860
24995	CEFBS_HasStdEnc_NotInMicroMips, // LH = 1861	24995	CEFBS_HasStdEnc_NotInMicroMips, // LH = 1861
24996	CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1862	24996	CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1862
24997	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1863	24997	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1863
24998	CEFBS_InMicroMips_HasEVA, // LHE_MM = 1864	24998	CEFBS_InMicroMips_HasEVA, // LHE_MM = 1864
24999	CEFBS_InMicroMips, // LHU16_MM = 1865	24999	CEFBS_InMicroMips, // LHU16_MM = 1865
25000	CEFBS_HasDSP, // LHX = 1866	25000	CEFBS_HasDSP, // LHX = 1866
25001	CEFBS_InMicroMips_HasDSP, // LHX_MM = 1867	25001	CEFBS_InMicroMips_HasDSP, // LHX_MM = 1867
25002	CEFBS_InMicroMips, // LH_MM = 1868	25002	CEFBS_InMicroMips, // LH_MM = 1868
25003	CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1869	25003	CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1869
25004	CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1870	25004	CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1870
25005	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1871	25005	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1871
25006	CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1872	25006	CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1872
25007	CEFBS_InMicroMips, // LHu_MM = 1873	25007	CEFBS_InMicroMips, // LHu_MM = 1873
25008	CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1874	25008	CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1874
25009	CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1875	25009	CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1875
25010	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1876	25010	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1876
25011	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1877	25011	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1877
25012	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1878	25012	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1878
25013	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1879	25013	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1879
25014	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1880	25014	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1880
25015	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1881	25015	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1881
25016	CEFBS_InMicroMips_HasEVA, // LLE_MM = 1882	25016	CEFBS_InMicroMips_HasEVA, // LLE_MM = 1882
25017	CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1883	25017	CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1883
25018	CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1884	25018	CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1884
25019	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1885	25019	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1885
25020	CEFBS_HasStdEnc_HasMSA, // LSA = 1886	25020	CEFBS_HasStdEnc_HasMSA, // LSA = 1886
25021	CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1887	25021	CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1887
25022	CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1888	25022	CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1888
25023	CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1889	25023	CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1889
25024	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1890	25024	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1890
25025	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1891	25025	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1891
25026	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1892	25026	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1892
25027	CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1893	25027	CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1893
25028	CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1894	25028	CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1894
25029	CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1895	25029	CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1895
25030	CEFBS_HasStdEnc_NotInMicroMips, // LW = 1896	25030	CEFBS_HasStdEnc_NotInMicroMips, // LW = 1896
25031	CEFBS_InMicroMips, // LW16_MM = 1897	25031	CEFBS_InMicroMips, // LW16_MM = 1897
25032	CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1898	25032	CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1898
25033	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1899	25033	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1899
25034	CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1900	25034	CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1900
25035	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1901	25035	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1901
25036	CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1902	25036	CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1902
25037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1903	25037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1903
25038	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1904	25038	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1904
25039	CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1905	25039	CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1905
25040	CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1906	25040	CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1906
25041	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1907	25041	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1907
25042	CEFBS_InMicroMips_HasEVA, // LWE_MM = 1908	25042	CEFBS_InMicroMips_HasEVA, // LWE_MM = 1908
25043	CEFBS_InMicroMips, // LWGP_MM = 1909	25043	CEFBS_InMicroMips, // LWGP_MM = 1909
25044	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1910	25044	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1910
25045	CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1911	25045	CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1911
25046	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1912	25046	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1912
25047	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1913	25047	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1913
25048	CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1914	25048	CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1914
25049	CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1915	25049	CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1915
25050	CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1916	25050	CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1916
25051	CEFBS_InMicroMips, // LWM32_MM = 1917	25051	CEFBS_InMicroMips, // LWM32_MM = 1917
25052	CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1918	25052	CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1918
25053	CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1919	25053	CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1919
25054	CEFBS_InMicroMips, // LWP_MM = 1920	25054	CEFBS_InMicroMips, // LWP_MM = 1920
25055	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1921	25055	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1921
25056	CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1922	25056	CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1922
25057	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1923	25057	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1923
25058	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1924	25058	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1924
25059	CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1925	25059	CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1925
25060	CEFBS_InMicroMips, // LWSP_MM = 1926	25060	CEFBS_InMicroMips, // LWSP_MM = 1926
25061	CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1927	25061	CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1927
25062	CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1928	25062	CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1928
25063	CEFBS_HasDSP, // LWX = 1929	25063	CEFBS_HasDSP, // LWX = 1929
25064	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1930	25064	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1930
25065	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1931	25065	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1931
25066	CEFBS_InMicroMips, // LWXS_MM = 1932	25066	CEFBS_InMicroMips, // LWXS_MM = 1932
25067	CEFBS_InMicroMips_HasDSP, // LWX_MM = 1933	25067	CEFBS_InMicroMips_HasDSP, // LWX_MM = 1933
25068	CEFBS_InMicroMips, // LW_MM = 1934	25068	CEFBS_InMicroMips, // LW_MM = 1934
25069	CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1935	25069	CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1935
25070	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1936	25070	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1936
25071	CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1937	25071	CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1937
25072	CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1938	25072	CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1938
25073	CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1939	25073	CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1939
25074	CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1940	25074	CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1940
25075	CEFBS_InMips16Mode, // LiRxImm16 = 1941	25075	CEFBS_InMips16Mode, // LiRxImm16 = 1941
25076	CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1942	25076	CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1942
25077	CEFBS_InMips16Mode, // LiRxImmX16 = 1943	25077	CEFBS_InMips16Mode, // LiRxImmX16 = 1943
25078	CEFBS_InMips16Mode, // LwRxPcTcp16 = 1944	25078	CEFBS_InMips16Mode, // LwRxPcTcp16 = 1944
25079	CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1945	25079	CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1945
25080	CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1946	25080	CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1946
25081	CEFBS_InMips16Mode, // LwRxSpImmX16 = 1947	25081	CEFBS_InMips16Mode, // LwRxSpImmX16 = 1947
25082	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1948	25082	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1948
25083	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1949	25083	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1949
25084	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1950	25084	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1950
25085	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1951	25085	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1951
25086	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1952	25086	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1952
25087	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1953	25087	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1953
25088	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1954	25088	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1954
25089	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1955	25089	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1955
25090	CEFBS_HasDSP, // MADDU_DSP = 1956	25090	CEFBS_HasDSP, // MADDU_DSP = 1956
25091	CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1957	25091	CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1957
25092	CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1958	25092	CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1958
25093	CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1959	25093	CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1959
25094	CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1960	25094	CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1960
25095	CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1961	25095	CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1961
25096	CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1962	25096	CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1962
25097	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1963	25097	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1963
25098	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1964	25098	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1964
25099	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1965	25099	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1965
25100	CEFBS_HasDSP, // MADD_DSP = 1966	25100	CEFBS_HasDSP, // MADD_DSP = 1966
25101	CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1967	25101	CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1967
25102	CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1968	25102	CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1968
25103	CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1969	25103	CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1969
25104	CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1970	25104	CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1970
25105	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1971	25105	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1971
25106	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1972	25106	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1972
25107	CEFBS_HasDSP, // MAQ_SA_W_PHL = 1973	25107	CEFBS_HasDSP, // MAQ_SA_W_PHL = 1973
25108	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1974	25108	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1974
25109	CEFBS_HasDSP, // MAQ_SA_W_PHR = 1975	25109	CEFBS_HasDSP, // MAQ_SA_W_PHR = 1975
25110	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1976	25110	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1976
25111	CEFBS_HasDSP, // MAQ_S_W_PHL = 1977	25111	CEFBS_HasDSP, // MAQ_S_W_PHL = 1977
25112	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1978	25112	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1978
25113	CEFBS_HasDSP, // MAQ_S_W_PHR = 1979	25113	CEFBS_HasDSP, // MAQ_S_W_PHR = 1979
25114	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1980	25114	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1980
25115	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1981	25115	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1981
25116	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1982	25116	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1982
25117	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1983	25117	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1983
25118	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1984	25118	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1984
25119	CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1985	25119	CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1985
25120	CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1986	25120	CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1986
25121	CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1987	25121	CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1987
25122	CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1988	25122	CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1988
25123	CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1989	25123	CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1989
25124	CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1990	25124	CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1990
25125	CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1991	25125	CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1991
25126	CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1992	25126	CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1992
25127	CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1993	25127	CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1993
25128	CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1994	25128	CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1994
25129	CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1995	25129	CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1995
25130	CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1996	25130	CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1996
25131	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1997	25131	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1997
25132	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1998	25132	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1998
25133	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1999	25133	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1999
25134	CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2000	25134	CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2000
25135	CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2001	25135	CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2001
25136	CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2002	25136	CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2002
25137	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2003	25137	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2003
25138	CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2004	25138	CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2004
25139	CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2005	25139	CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2005
25140	CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2006	25140	CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2006
25141	CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2007	25141	CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2007
25142	CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2008	25142	CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2008
25143	CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2009	25143	CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2009
25144	CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2010	25144	CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2010
25145	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2011	25145	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2011
25146	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2012	25146	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2012
25147	CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2013	25147	CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2013
25148	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2014	25148	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2014
25149	CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2015	25149	CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2015
25150	CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2016	25150	CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2016
25151	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2017	25151	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2017
25152	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2018	25152	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2018
25153	CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2019	25153	CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2019
25154	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2020	25154	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2020
25155	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2021	25155	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2021
25156	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2022	25156	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2022
25157	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2023	25157	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2023
25158	CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2024	25158	CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2024
25159	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2025	25159	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2025
25160	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2026	25160	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2026
25161	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2027	25161	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2027
25162	CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2028	25162	CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2028
25163	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2029	25163	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2029
25164	CEFBS_HasDSP, // MFHI_DSP = 2030	25164	CEFBS_HasDSP, // MFHI_DSP = 2030
25165	CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2031	25165	CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2031
25166	CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2032	25166	CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2032
25167	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2033	25167	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2033
25168	CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2034	25168	CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2034
25169	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2035	25169	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2035
25170	CEFBS_HasDSP, // MFLO_DSP = 2036	25170	CEFBS_HasDSP, // MFLO_DSP = 2036
25171	CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2037	25171	CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2037
25172	CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2038	25172	CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2038
25173	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2039	25173	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2039
25174	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2040	25174	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2040
25175	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2041	25175	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2041
25176	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2042	25176	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2042
25177	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2043	25177	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2043
25178	CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2044	25178	CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2044
25179	CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2045	25179	CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2045
25180	CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2046	25180	CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2046
25181	CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2047	25181	CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2047
25182	CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2048	25182	CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2048
25183	CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2049	25183	CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2049
25184	CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2050	25184	CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2050
25185	CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2051	25185	CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2051
25186	CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2052	25186	CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2052
25187	CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2053	25187	CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2053
25188	CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2054	25188	CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2054
25189	CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2055	25189	CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2055
25190	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2056	25190	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2056
25191	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2057	25191	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2057
25192	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2058	25192	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2058
25193	CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2059	25193	CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2059
25194	CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2060	25194	CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2060
25195	CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2061	25195	CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2061
25196	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2062	25196	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2062
25197	CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2063	25197	CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2063
25198	CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2064	25198	CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2064
25199	CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2065	25199	CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2065
25200	CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2066	25200	CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2066
25201	CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2067	25201	CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2067
25202	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2068	25202	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2068
25203	CEFBS_HasDSP, // MODSUB = 2069	25203	CEFBS_HasDSP, // MODSUB = 2069
25204	CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2070	25204	CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2070
25205	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2071	25205	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2071
25206	CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2072	25206	CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2072
25207	CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2073	25207	CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2073
25208	CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2074	25208	CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2074
25209	CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2075	25209	CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2075
25210	CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2076	25210	CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2076
25211	CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2077	25211	CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2077
25212	CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2078	25212	CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2078
25213	CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2079	25213	CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2079
25214	CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2080	25214	CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2080
25215	CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2081	25215	CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2081
25216	CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2082	25216	CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2082
25217	CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2083	25217	CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2083
25218	CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2084	25218	CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2084
25219	CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2085	25219	CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2085
25220	CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2086	25220	CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2086
25221	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2087	25221	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2087
25222	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2088	25222	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2088
25223	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2089	25223	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2089
25224	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2090	25224	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2090
25225	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2091	25225	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2091
25226	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2092	25226	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2092
25227	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2093	25227	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2093
25228	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2094	25228	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2094
25229	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2095	25229	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2095
25230	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2096	25230	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2096
25231	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2097	25231	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2097
25232	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2098	25232	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2098
25233	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2099	25233	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2099
25234	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2100	25234	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2100
25235	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2101	25235	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2101
25236	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2102	25236	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2102
25237	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2103	25237	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2103
25238	CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2104	25238	CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2104
25239	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2105	25239	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2105
25240	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2106	25240	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2106
25241	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2107	25241	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2107
25242	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2108	25242	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2108
25243	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2109	25243	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2109
25244	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2110	25244	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2110
25245	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2111	25245	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2111
25246	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2112	25246	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2112
25247	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2113	25247	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2113
25248	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2114	25248	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2114
25249	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2115	25249	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2115
25250	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2116	25250	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2116
25251	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2117	25251	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2117
25252	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2118	25252	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2118
25253	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2119	25253	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2119
25254	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2120	25254	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2120
25255	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2121	25255	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2121
25256	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2122	25256	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2122
25257	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2123	25257	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2123
25258	CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2124	25258	CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2124
25259	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2125	25259	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2125
25260	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2126	25260	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2126
25261	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2127	25261	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2127
25262	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2128	25262	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2128
25263	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2129	25263	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2129
25264	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2130	25264	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2130
25265	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2131	25265	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2131
25266	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2132	25266	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2132
25267	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2133	25267	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2133
25268	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2134	25268	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2134
25269	CEFBS_HasDSP, // MSUBU_DSP = 2135	25269	CEFBS_HasDSP, // MSUBU_DSP = 2135
25270	CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2136	25270	CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2136
25271	CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2137	25271	CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2137
25272	CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2138	25272	CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2138
25273	CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2139	25273	CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2139
25274	CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2140	25274	CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2140
25275	CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2141	25275	CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2141
25276	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2142	25276	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2142
25277	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2143	25277	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2143
25278	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2144	25278	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2144
25279	CEFBS_HasDSP, // MSUB_DSP = 2145	25279	CEFBS_HasDSP, // MSUB_DSP = 2145
25280	CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2146	25280	CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2146
25281	CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2147	25281	CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2147
25282	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2148	25282	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2148
25283	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2149	25283	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2149
25284	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2150	25284	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2150
25285	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2151	25285	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2151
25286	CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2152	25286	CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2152
25287	CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2153	25287	CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2153
25288	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2154	25288	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2154
25289	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2155	25289	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2155
25290	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2156	25290	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2156
25291	CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2157	25291	CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2157
25292	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2158	25292	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2158
25293	CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2159	25293	CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2159
25294	CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2160	25294	CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2160
25295	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2161	25295	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2161
25296	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2162	25296	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2162
25297	CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2163	25297	CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2163
25298	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2164	25298	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2164
25299	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2165	25299	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2165
25300	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2166	25300	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2166
25301	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2167	25301	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2167
25302	CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2168	25302	CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2168
25303	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2169	25303	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2169
25304	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2170	25304	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2170
25305	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2171	25305	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2171
25306	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2172	25306	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2172
25307	CEFBS_HasDSP, // MTHI_DSP = 2173	25307	CEFBS_HasDSP, // MTHI_DSP = 2173
25308	CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2174	25308	CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2174
25309	CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2175	25309	CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2175
25310	CEFBS_HasDSP, // MTHLIP = 2176	25310	CEFBS_HasDSP, // MTHLIP = 2176
25311	CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2177	25311	CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2177
25312	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2178	25312	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2178
25313	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2179	25313	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2179
25314	CEFBS_HasDSP, // MTLO_DSP = 2180	25314	CEFBS_HasDSP, // MTLO_DSP = 2180
25315	CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2181	25315	CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2181
25316	CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2182	25316	CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2182
25317	CEFBS_HasCnMips, // MTM0 = 2183	25317	CEFBS_HasCnMips, // MTM0 = 2183
25318	CEFBS_HasCnMips, // MTM1 = 2184	25318	CEFBS_HasCnMips, // MTM1 = 2184
25319	CEFBS_HasCnMips, // MTM2 = 2185	25319	CEFBS_HasCnMips, // MTM2 = 2185
25320	CEFBS_HasCnMips, // MTP0 = 2186	25320	CEFBS_HasCnMips, // MTP0 = 2186
25321	CEFBS_HasCnMips, // MTP1 = 2187	25321	CEFBS_HasCnMips, // MTP1 = 2187
25322	CEFBS_HasCnMips, // MTP2 = 2188	25322	CEFBS_HasCnMips, // MTP2 = 2188
25323	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2189	25323	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2189
25324	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2190	25324	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2190
25325	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2191	25325	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2191
25326	CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2192	25326	CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2192
25327	CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2193	25327	CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2193
25328	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2194	25328	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2194
25329	CEFBS_HasDSP, // MULEQ_S_W_PHL = 2195	25329	CEFBS_HasDSP, // MULEQ_S_W_PHL = 2195
25330	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2196	25330	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2196
25331	CEFBS_HasDSP, // MULEQ_S_W_PHR = 2197	25331	CEFBS_HasDSP, // MULEQ_S_W_PHR = 2197
25332	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2198	25332	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2198
25333	CEFBS_HasDSP, // MULEU_S_PH_QBL = 2199	25333	CEFBS_HasDSP, // MULEU_S_PH_QBL = 2199
25334	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2200	25334	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2200
25335	CEFBS_HasDSP, // MULEU_S_PH_QBR = 2201	25335	CEFBS_HasDSP, // MULEU_S_PH_QBR = 2201
25336	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2202	25336	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2202
25337	CEFBS_HasDSP, // MULQ_RS_PH = 2203	25337	CEFBS_HasDSP, // MULQ_RS_PH = 2203
25338	CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2204	25338	CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2204
25339	CEFBS_HasDSPR2, // MULQ_RS_W = 2205	25339	CEFBS_HasDSPR2, // MULQ_RS_W = 2205
25340	CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2206	25340	CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2206
25341	CEFBS_HasDSPR2, // MULQ_S_PH = 2207	25341	CEFBS_HasDSPR2, // MULQ_S_PH = 2207
25342	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2208	25342	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2208
25343	CEFBS_HasDSPR2, // MULQ_S_W = 2209	25343	CEFBS_HasDSPR2, // MULQ_S_W = 2209
25344	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2210	25344	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2210
25345	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2211	25345	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2211
25346	CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2212	25346	CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2212
25347	CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2213	25347	CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2213
25348	CEFBS_HasDSP, // MULSAQ_S_W_PH = 2214	25348	CEFBS_HasDSP, // MULSAQ_S_W_PH = 2214
25349	CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2215	25349	CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2215
25350	CEFBS_HasDSPR2, // MULSA_W_PH = 2216	25350	CEFBS_HasDSPR2, // MULSA_W_PH = 2216
25351	CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2217	25351	CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2217
25352	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2218	25352	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2218
25353	CEFBS_HasDSP, // MULTU_DSP = 2219	25353	CEFBS_HasDSP, // MULTU_DSP = 2219
25354	CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2220	25354	CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2220
25355	CEFBS_HasDSP, // MULT_DSP = 2221	25355	CEFBS_HasDSP, // MULT_DSP = 2221
25356	CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2222	25356	CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2222
25357	CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2223	25357	CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2223
25358	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2224	25358	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2224
25359	CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2225	25359	CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2225
25360	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2226	25360	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2226
25361	CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2227	25361	CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2227
25362	CEFBS_HasStdEnc_HasMSA, // MULV_B = 2228	25362	CEFBS_HasStdEnc_HasMSA, // MULV_B = 2228
25363	CEFBS_HasStdEnc_HasMSA, // MULV_D = 2229	25363	CEFBS_HasStdEnc_HasMSA, // MULV_D = 2229
25364	CEFBS_HasStdEnc_HasMSA, // MULV_H = 2230	25364	CEFBS_HasStdEnc_HasMSA, // MULV_H = 2230
25365	CEFBS_HasStdEnc_HasMSA, // MULV_W = 2231	25365	CEFBS_HasStdEnc_HasMSA, // MULV_W = 2231
25366	CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2232	25366	CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2232
25367	CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2233	25367	CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2233
25368	CEFBS_HasDSPR2, // MUL_PH = 2234	25368	CEFBS_HasDSPR2, // MUL_PH = 2234
25369	CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2235	25369	CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2235
25370	CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2236	25370	CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2236
25371	CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2237	25371	CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2237
25372	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2238	25372	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2238
25373	CEFBS_HasDSPR2, // MUL_S_PH = 2239	25373	CEFBS_HasDSPR2, // MUL_S_PH = 2239
25374	CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2240	25374	CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2240
25375	CEFBS_InMips16Mode, // Mfhi16 = 2241	25375	CEFBS_InMips16Mode, // Mfhi16 = 2241
25376	CEFBS_InMips16Mode, // Mflo16 = 2242	25376	CEFBS_InMips16Mode, // Mflo16 = 2242
25377	CEFBS_InMips16Mode, // Move32R16 = 2243	25377	CEFBS_InMips16Mode, // Move32R16 = 2243
25378	CEFBS_InMips16Mode, // MoveR3216 = 2244	25378	CEFBS_InMips16Mode, // MoveR3216 = 2244
25379	CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2245	25379	CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2245
25380	CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2246	25380	CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2246
25381	CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2247	25381	CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2247
25382	CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2248	25382	CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2248
25383	CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2249	25383	CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2249
25384	CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2250	25384	CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2250
25385	CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2251	25385	CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2251
25386	CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2252	25386	CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2252
25387	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2253	25387	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2253
25388	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2254	25388	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2254
25389	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2255	25389	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2255
25390	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2256	25390	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2256
25391	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2257	25391	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2257
25392	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2258	25392	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2258
25393	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2259	25393	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2259
25394	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2260	25394	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2260
25395	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2261	25395	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2261
25396	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2262	25396	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2262
25397	CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2263	25397	CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2263
25398	CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2264	25398	CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2264
25399	CEFBS_HasStdEnc_HasMSA, // NORI_B = 2265	25399	CEFBS_HasStdEnc_HasMSA, // NORI_B = 2265
25400	CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2266	25400	CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2266
25401	CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2267	25401	CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2267
25402	CEFBS_HasStdEnc_HasMSA, // NOR_V = 2268	25402	CEFBS_HasStdEnc_HasMSA, // NOR_V = 2268
25403	CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2269	25403	CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2269
25404	CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2270	25404	CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2270
25405	CEFBS_InMips16Mode, // NegRxRy16 = 2271	25405	CEFBS_InMips16Mode, // NegRxRy16 = 2271
25406	CEFBS_InMips16Mode, // NotRxRy16 = 2272	25406	CEFBS_InMips16Mode, // NotRxRy16 = 2272
25407	CEFBS_HasStdEnc_NotInMicroMips, // OR = 2273	25407	CEFBS_HasStdEnc_NotInMicroMips, // OR = 2273
25408	CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2274	25408	CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2274
25409	CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2275	25409	CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2275
25410	CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2276	25410	CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2276
25411	CEFBS_HasStdEnc_HasMSA, // ORI_B = 2277	25411	CEFBS_HasStdEnc_HasMSA, // ORI_B = 2277
25412	CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2278	25412	CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2278
25413	CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2279	25413	CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2279
25414	CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2280	25414	CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2280
25415	CEFBS_HasStdEnc_HasMSA, // OR_V = 2281	25415	CEFBS_HasStdEnc_HasMSA, // OR_V = 2281
25416	CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2282	25416	CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2282
25417	CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2283	25417	CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2283
25418	CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2284	25418	CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2284
25419	CEFBS_InMips16Mode, // OrRxRxRy16 = 2285	25419	CEFBS_InMips16Mode, // OrRxRxRy16 = 2285
25420	CEFBS_HasDSP, // PACKRL_PH = 2286	25420	CEFBS_HasDSP, // PACKRL_PH = 2286
25421	CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2287	25421	CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2287
25422	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2288	25422	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2288
25423	CEFBS_InMicroMips, // PAUSE_MM = 2289	25423	CEFBS_InMicroMips, // PAUSE_MM = 2289
25424	CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2290	25424	CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2290
25425	CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2291	25425	CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2291
25426	CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2292	25426	CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2292
25427	CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2293	25427	CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2293
25428	CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2294	25428	CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2294
25429	CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2295	25429	CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2295
25430	CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2296	25430	CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2296
25431	CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2297	25431	CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2297
25432	CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2298	25432	CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2298
25433	CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2299	25433	CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2299
25434	CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2300	25434	CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2300
25435	CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2301	25435	CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2301
25436	CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2302	25436	CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2302
25437	CEFBS_HasDSP, // PICK_PH = 2303	25437	CEFBS_HasDSP, // PICK_PH = 2303
25438	CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2304	25438	CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2304
25439	CEFBS_HasDSP, // PICK_QB = 2305	25439	CEFBS_HasDSP, // PICK_QB = 2305
25440	CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2306	25440	CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2306
25441	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2307	25441	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2307
25442	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2308	25442	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2308
25443	CEFBS_HasCnMips, // POP = 2309	25443	CEFBS_HasCnMips, // POP = 2309
25444	CEFBS_HasDSP, // PRECEQU_PH_QBL = 2310	25444	CEFBS_HasDSP, // PRECEQU_PH_QBL = 2310
25445	CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2311	25445	CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2311
25446	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2312	25446	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2312
25447	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2313	25447	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2313
25448	CEFBS_HasDSP, // PRECEQU_PH_QBR = 2314	25448	CEFBS_HasDSP, // PRECEQU_PH_QBR = 2314
25449	CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2315	25449	CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2315
25450	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2316	25450	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2316
25451	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2317	25451	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2317
25452	CEFBS_HasDSP, // PRECEQ_W_PHL = 2318	25452	CEFBS_HasDSP, // PRECEQ_W_PHL = 2318
25453	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2319	25453	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2319
25454	CEFBS_HasDSP, // PRECEQ_W_PHR = 2320	25454	CEFBS_HasDSP, // PRECEQ_W_PHR = 2320
25455	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2321	25455	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2321
25456	CEFBS_HasDSP, // PRECEU_PH_QBL = 2322	25456	CEFBS_HasDSP, // PRECEU_PH_QBL = 2322
25457	CEFBS_HasDSP, // PRECEU_PH_QBLA = 2323	25457	CEFBS_HasDSP, // PRECEU_PH_QBLA = 2323
25458	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2324	25458	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2324
25459	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2325	25459	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2325
25460	CEFBS_HasDSP, // PRECEU_PH_QBR = 2326	25460	CEFBS_HasDSP, // PRECEU_PH_QBR = 2326
25461	CEFBS_HasDSP, // PRECEU_PH_QBRA = 2327	25461	CEFBS_HasDSP, // PRECEU_PH_QBRA = 2327
25462	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2328	25462	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2328
25463	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2329	25463	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2329
25464	CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2330	25464	CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2330
25465	CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2331	25465	CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2331
25466	CEFBS_HasDSP, // PRECRQ_PH_W = 2332	25466	CEFBS_HasDSP, // PRECRQ_PH_W = 2332
25467	CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2333	25467	CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2333
25468	CEFBS_HasDSP, // PRECRQ_QB_PH = 2334	25468	CEFBS_HasDSP, // PRECRQ_QB_PH = 2334
25469	CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2335	25469	CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2335
25470	CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2336	25470	CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2336
25471	CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2337	25471	CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2337
25472	CEFBS_HasDSPR2, // PRECR_QB_PH = 2338	25472	CEFBS_HasDSPR2, // PRECR_QB_PH = 2338
25473	CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2339	25473	CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2339
25474	CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2340	25474	CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2340
25475	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2341	25475	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2341
25476	CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2342	25476	CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2342
25477	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2343	25477	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2343
25478	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2344	25478	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2344
25479	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2345	25479	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2345
25480	CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2346	25480	CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2346
25481	CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2347	25481	CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2347
25482	CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2348	25482	CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2348
25483	CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2349	25483	CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2349
25484	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2350	25484	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2350
25485	CEFBS_HasDSPR2, // PREPEND = 2351	25485	CEFBS_HasDSPR2, // PREPEND = 2351
25486	CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2352	25486	CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2352
25487	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2353	25487	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2353
25488	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2354	25488	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2354
25489	CEFBS_HasDSP, // RADDU_W_QB = 2355	25489	CEFBS_HasDSP, // RADDU_W_QB = 2355
25490	CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2356	25490	CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2356
25491	CEFBS_HasDSP, // RDDSP = 2357	25491	CEFBS_HasDSP, // RDDSP = 2357
25492	CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2358	25492	CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2358
25493	CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2359	25493	CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2359
25494	CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2360	25494	CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2360
25495	CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2361	25495	CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2361
25496	CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2362	25496	CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2362
25497	CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2363	25497	CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2363
25498	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2364	25498	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2364
25499	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2365	25499	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2365
25500	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2366	25500	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2366
25501	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2367	25501	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2367
25502	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2368	25502	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2368
25503	CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2369	25503	CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2369
25504	CEFBS_HasDSP, // REPLV_PH = 2370	25504	CEFBS_HasDSP, // REPLV_PH = 2370
25505	CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2371	25505	CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2371
25506	CEFBS_HasDSP, // REPLV_QB = 2372	25506	CEFBS_HasDSP, // REPLV_QB = 2372
25507	CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2373	25507	CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2373
25508	CEFBS_HasDSP, // REPL_PH = 2374	25508	CEFBS_HasDSP, // REPL_PH = 2374
25509	CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2375	25509	CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2375
25510	CEFBS_HasDSP, // REPL_QB = 2376	25510	CEFBS_HasDSP, // REPL_QB = 2376
25511	CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2377	25511	CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2377
25512	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2378	25512	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2378
25513	CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2379	25513	CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2379
25514	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2380	25514	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2380
25515	CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2381	25515	CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2381
25516	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2382	25516	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2382
25517	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2383	25517	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2383
25518	CEFBS_InMicroMips, // ROTRV_MM = 2384	25518	CEFBS_InMicroMips, // ROTRV_MM = 2384
25519	CEFBS_InMicroMips, // ROTR_MM = 2385	25519	CEFBS_InMicroMips, // ROTR_MM = 2385
25520	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2386	25520	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2386
25521	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2387	25521	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2387
25522	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2388	25522	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2388
25523	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2389	25523	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2389
25524	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2390	25524	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2390
25525	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2391	25525	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2391
25526	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2392	25526	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2392
25527	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2393	25527	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2393
25528	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2394	25528	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2394
25529	CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2395	25529	CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2395
25530	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2396	25530	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2396
25531	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2397	25531	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2397
25532	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2398	25532	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2398
25533	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2399	25533	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2399
25534	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2400	25534	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2400
25535	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2401	25535	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2401
25536	CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2402	25536	CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2402
25537	CEFBS_InMips16Mode, // Restore16 = 2403	25537	CEFBS_InMips16Mode, // Restore16 = 2403
25538	CEFBS_InMips16Mode, // RestoreX16 = 2404	25538	CEFBS_InMips16Mode, // RestoreX16 = 2404
25539	CEFBS_HasCnMipsP, // SAA = 2405	25539	CEFBS_HasCnMipsP, // SAA = 2405
25540	CEFBS_HasCnMipsP, // SAAD = 2406	25540	CEFBS_HasCnMipsP, // SAAD = 2406
25541	CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2407	25541	CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2407
25542	CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2408	25542	CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2408
25543	CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2409	25543	CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2409
25544	CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2410	25544	CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2410
25545	CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2411	25545	CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2411
25546	CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2412	25546	CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2412
25547	CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2413	25547	CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2413
25548	CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2414	25548	CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2414
25549	CEFBS_HasStdEnc_NotInMicroMips, // SB = 2415	25549	CEFBS_HasStdEnc_NotInMicroMips, // SB = 2415
25550	CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2416	25550	CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2416
25551	CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2417	25551	CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2417
25552	CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2418	25552	CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2418
25553	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2419	25553	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2419
25554	CEFBS_InMicroMips_HasEVA, // SBE_MM = 2420	25554	CEFBS_InMicroMips_HasEVA, // SBE_MM = 2420
25555	CEFBS_InMicroMips, // SB_MM = 2421	25555	CEFBS_InMicroMips, // SB_MM = 2421
25556	CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2422	25556	CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2422
25557	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2423	25557	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2423
25558	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2424	25558	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2424
25559	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2425	25559	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2425
25560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2426	25560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2426
25561	CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2427	25561	CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2427
25562	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2428	25562	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2428
25563	CEFBS_InMicroMips_HasEVA, // SCE_MM = 2429	25563	CEFBS_InMicroMips_HasEVA, // SCE_MM = 2429
25564	CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2430	25564	CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2430
25565	CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2431	25565	CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2431
25566	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2432	25566	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2432
25567	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2433	25567	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2433
25568	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2434	25568	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2434
25569	CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2435	25569	CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2435
25570	CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2436	25570	CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2436
25571	CEFBS_InMicroMips, // SDBBP_MM = 2437	25571	CEFBS_InMicroMips, // SDBBP_MM = 2437
25572	CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2438	25572	CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2438
25573	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2439	25573	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2439
25574	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2440	25574	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2440
25575	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2441	25575	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2441
25576	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2442	25576	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2442
25577	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2443	25577	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2443
25578	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2444	25578	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2444
25579	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2445	25579	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2445
25580	CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2446	25580	CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2446
25581	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2447	25581	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2447
25582	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2448	25582	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2448
25583	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2449	25583	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2449
25584	CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2450	25584	CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2450
25585	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2451	25585	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2451
25586	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2452	25586	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2452
25587	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2453	25587	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2453
25588	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2454	25588	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2454
25589	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2455	25589	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2455
25590	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2456	25590	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2456
25591	CEFBS_InMicroMips, // SEB_MM = 2457	25591	CEFBS_InMicroMips, // SEB_MM = 2457
25592	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2458	25592	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2458
25593	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2459	25593	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2459
25594	CEFBS_InMicroMips, // SEH_MM = 2460	25594	CEFBS_InMicroMips, // SEH_MM = 2460
25595	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2461	25595	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2461
25596	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2462	25596	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2462
25597	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2463	25597	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2463
25598	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2464	25598	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2464
25599	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2465	25599	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2465
25600	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2466	25600	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2466
25601	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2467	25601	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2467
25602	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2468	25602	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2468
25603	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2469	25603	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2469
25604	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2470	25604	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2470
25605	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2471	25605	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2471
25606	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2472	25606	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2472
25607	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2473	25607	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2473
25608	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2474	25608	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2474
25609	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2475	25609	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2475
25610	CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2476	25610	CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2476
25611	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2477	25611	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2477
25612	CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2478	25612	CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2478
25613	CEFBS_HasCnMips, // SEQ = 2479	25613	CEFBS_HasCnMips, // SEQ = 2479
25614	CEFBS_HasCnMips, // SEQi = 2480	25614	CEFBS_HasCnMips, // SEQi = 2480
25615	CEFBS_HasStdEnc_NotInMicroMips, // SH = 2481	25615	CEFBS_HasStdEnc_NotInMicroMips, // SH = 2481
25616	CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2482	25616	CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2482
25617	CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2483	25617	CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2483
25618	CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2484	25618	CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2484
25619	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2485	25619	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2485
25620	CEFBS_InMicroMips_HasEVA, // SHE_MM = 2486	25620	CEFBS_InMicroMips_HasEVA, // SHE_MM = 2486
25621	CEFBS_HasStdEnc_HasMSA, // SHF_B = 2487	25621	CEFBS_HasStdEnc_HasMSA, // SHF_B = 2487
25622	CEFBS_HasStdEnc_HasMSA, // SHF_H = 2488	25622	CEFBS_HasStdEnc_HasMSA, // SHF_H = 2488
25623	CEFBS_HasStdEnc_HasMSA, // SHF_W = 2489	25623	CEFBS_HasStdEnc_HasMSA, // SHF_W = 2489
25624	CEFBS_HasDSP, // SHILO = 2490	25624	CEFBS_HasDSP, // SHILO = 2490
25625	CEFBS_HasDSP, // SHILOV = 2491	25625	CEFBS_HasDSP, // SHILOV = 2491
25626	CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2492	25626	CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2492
25627	CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2493	25627	CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2493
25628	CEFBS_HasDSP, // SHLLV_PH = 2494	25628	CEFBS_HasDSP, // SHLLV_PH = 2494
25629	CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2495	25629	CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2495
25630	CEFBS_HasDSP, // SHLLV_QB = 2496	25630	CEFBS_HasDSP, // SHLLV_QB = 2496
25631	CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2497	25631	CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2497
25632	CEFBS_HasDSP, // SHLLV_S_PH = 2498	25632	CEFBS_HasDSP, // SHLLV_S_PH = 2498
25633	CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2499	25633	CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2499
25634	CEFBS_HasDSP, // SHLLV_S_W = 2500	25634	CEFBS_HasDSP, // SHLLV_S_W = 2500
25635	CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2501	25635	CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2501
25636	CEFBS_HasDSP, // SHLL_PH = 2502	25636	CEFBS_HasDSP, // SHLL_PH = 2502
25637	CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2503	25637	CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2503
25638	CEFBS_HasDSP, // SHLL_QB = 2504	25638	CEFBS_HasDSP, // SHLL_QB = 2504
25639	CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2505	25639	CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2505
25640	CEFBS_HasDSP, // SHLL_S_PH = 2506	25640	CEFBS_HasDSP, // SHLL_S_PH = 2506
25641	CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2507	25641	CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2507
25642	CEFBS_HasDSP, // SHLL_S_W = 2508	25642	CEFBS_HasDSP, // SHLL_S_W = 2508
25643	CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2509	25643	CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2509
25644	CEFBS_HasDSP, // SHRAV_PH = 2510	25644	CEFBS_HasDSP, // SHRAV_PH = 2510
25645	CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2511	25645	CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2511
25646	CEFBS_HasDSPR2, // SHRAV_QB = 2512	25646	CEFBS_HasDSPR2, // SHRAV_QB = 2512
25647	CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2513	25647	CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2513
25648	CEFBS_HasDSP, // SHRAV_R_PH = 2514	25648	CEFBS_HasDSP, // SHRAV_R_PH = 2514
25649	CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2515	25649	CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2515
25650	CEFBS_HasDSPR2, // SHRAV_R_QB = 2516	25650	CEFBS_HasDSPR2, // SHRAV_R_QB = 2516
25651	CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2517	25651	CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2517
25652	CEFBS_HasDSP, // SHRAV_R_W = 2518	25652	CEFBS_HasDSP, // SHRAV_R_W = 2518
25653	CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2519	25653	CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2519
25654	CEFBS_HasDSP, // SHRA_PH = 2520	25654	CEFBS_HasDSP, // SHRA_PH = 2520
25655	CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2521	25655	CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2521
25656	CEFBS_HasDSPR2, // SHRA_QB = 2522	25656	CEFBS_HasDSPR2, // SHRA_QB = 2522
25657	CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2523	25657	CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2523
25658	CEFBS_HasDSP, // SHRA_R_PH = 2524	25658	CEFBS_HasDSP, // SHRA_R_PH = 2524
25659	CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2525	25659	CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2525
25660	CEFBS_HasDSPR2, // SHRA_R_QB = 2526	25660	CEFBS_HasDSPR2, // SHRA_R_QB = 2526
25661	CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2527	25661	CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2527
25662	CEFBS_HasDSP, // SHRA_R_W = 2528	25662	CEFBS_HasDSP, // SHRA_R_W = 2528
25663	CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2529	25663	CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2529
25664	CEFBS_HasDSPR2, // SHRLV_PH = 2530	25664	CEFBS_HasDSPR2, // SHRLV_PH = 2530
25665	CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2531	25665	CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2531
25666	CEFBS_HasDSP, // SHRLV_QB = 2532	25666	CEFBS_HasDSP, // SHRLV_QB = 2532
25667	CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2533	25667	CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2533
25668	CEFBS_HasDSPR2, // SHRL_PH = 2534	25668	CEFBS_HasDSPR2, // SHRL_PH = 2534
25669	CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2535	25669	CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2535
25670	CEFBS_HasDSP, // SHRL_QB = 2536	25670	CEFBS_HasDSP, // SHRL_QB = 2536
25671	CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2537	25671	CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2537
25672	CEFBS_InMicroMips, // SH_MM = 2538	25672	CEFBS_InMicroMips, // SH_MM = 2538
25673	CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2539	25673	CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2539
25674	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2540	25674	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2540
25675	CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2541	25675	CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2541
25676	CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2542	25676	CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2542
25677	CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2543	25677	CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2543
25678	CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2544	25678	CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2544
25679	CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2545	25679	CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2545
25680	CEFBS_HasStdEnc_HasMSA, // SLD_B = 2546	25680	CEFBS_HasStdEnc_HasMSA, // SLD_B = 2546
25681	CEFBS_HasStdEnc_HasMSA, // SLD_D = 2547	25681	CEFBS_HasStdEnc_HasMSA, // SLD_D = 2547
25682	CEFBS_HasStdEnc_HasMSA, // SLD_H = 2548	25682	CEFBS_HasStdEnc_HasMSA, // SLD_H = 2548
25683	CEFBS_HasStdEnc_HasMSA, // SLD_W = 2549	25683	CEFBS_HasStdEnc_HasMSA, // SLD_W = 2549
25684	CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2550	25684	CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2550
25685	CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2551	25685	CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2551
25686	CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2552	25686	CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2552
25687	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2553	25687	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2553
25688	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2554	25688	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2554
25689	CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2555	25689	CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2555
25690	CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2556	25690	CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2556
25691	CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2557	25691	CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2557
25692	CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2558	25692	CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2558
25693	CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2559	25693	CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2559
25694	CEFBS_InMicroMips, // SLLV_MM = 2560	25694	CEFBS_InMicroMips, // SLLV_MM = 2560
25695	CEFBS_HasStdEnc_HasMSA, // SLL_B = 2561	25695	CEFBS_HasStdEnc_HasMSA, // SLL_B = 2561
25696	CEFBS_HasStdEnc_HasMSA, // SLL_D = 2562	25696	CEFBS_HasStdEnc_HasMSA, // SLL_D = 2562
25697	CEFBS_HasStdEnc_HasMSA, // SLL_H = 2563	25697	CEFBS_HasStdEnc_HasMSA, // SLL_H = 2563
25698	CEFBS_InMicroMips, // SLL_MM = 2564	25698	CEFBS_InMicroMips, // SLL_MM = 2564
25699	CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2565	25699	CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2565
25700	CEFBS_HasStdEnc_HasMSA, // SLL_W = 2566	25700	CEFBS_HasStdEnc_HasMSA, // SLL_W = 2566
25701	CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2567	25701	CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2567
25702	CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2568	25702	CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2568
25703	CEFBS_InMicroMips, // SLT_MM = 2569	25703	CEFBS_InMicroMips, // SLT_MM = 2569
25704	CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2570	25704	CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2570
25705	CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2571	25705	CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2571
25706	CEFBS_InMicroMips, // SLTi_MM = 2572	25706	CEFBS_InMicroMips, // SLTi_MM = 2572
25707	CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2573	25707	CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2573
25708	CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2574	25708	CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2574
25709	CEFBS_InMicroMips, // SLTiu_MM = 2575	25709	CEFBS_InMicroMips, // SLTiu_MM = 2575
25710	CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2576	25710	CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2576
25711	CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2577	25711	CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2577
25712	CEFBS_InMicroMips, // SLTu_MM = 2578	25712	CEFBS_InMicroMips, // SLTu_MM = 2578
25713	CEFBS_HasCnMips, // SNE = 2579	25713	CEFBS_HasCnMips, // SNE = 2579
25714	CEFBS_HasCnMips, // SNEi = 2580	25714	CEFBS_HasCnMips, // SNEi = 2580
25715	CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2581	25715	CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2581
25716	CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2582	25716	CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2582
25717	CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2583	25717	CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2583
25718	CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2584	25718	CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2584
25719	CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2585	25719	CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2585
25720	CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2586	25720	CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2586
25721	CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2587	25721	CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2587
25722	CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2588	25722	CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2588
25723	CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2589	25723	CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2589
25724	CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2590	25724	CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2590
25725	CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2591	25725	CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2591
25726	CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2592	25726	CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2592
25727	CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2593	25727	CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2593
25728	CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2594	25728	CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2594
25729	CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2595	25729	CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2595
25730	CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2596	25730	CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2596
25731	CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2597	25731	CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2597
25732	CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2598	25732	CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2598
25733	CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2599	25733	CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2599
25734	CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2600	25734	CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2600
25735	CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2601	25735	CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2601
25736	CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2602	25736	CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2602
25737	CEFBS_InMicroMips, // SRAV_MM = 2603	25737	CEFBS_InMicroMips, // SRAV_MM = 2603
25738	CEFBS_HasStdEnc_HasMSA, // SRA_B = 2604	25738	CEFBS_HasStdEnc_HasMSA, // SRA_B = 2604
25739	CEFBS_HasStdEnc_HasMSA, // SRA_D = 2605	25739	CEFBS_HasStdEnc_HasMSA, // SRA_D = 2605
25740	CEFBS_HasStdEnc_HasMSA, // SRA_H = 2606	25740	CEFBS_HasStdEnc_HasMSA, // SRA_H = 2606
25741	CEFBS_InMicroMips, // SRA_MM = 2607	25741	CEFBS_InMicroMips, // SRA_MM = 2607
25742	CEFBS_HasStdEnc_HasMSA, // SRA_W = 2608	25742	CEFBS_HasStdEnc_HasMSA, // SRA_W = 2608
25743	CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2609	25743	CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2609
25744	CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2610	25744	CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2610
25745	CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2611	25745	CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2611
25746	CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2612	25746	CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2612
25747	CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2613	25747	CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2613
25748	CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2614	25748	CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2614
25749	CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2615	25749	CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2615
25750	CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2616	25750	CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2616
25751	CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2617	25751	CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2617
25752	CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2618	25752	CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2618
25753	CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2619	25753	CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2619
25754	CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2620	25754	CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2620
25755	CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2621	25755	CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2621
25756	CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2622	25756	CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2622
25757	CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2623	25757	CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2623
25758	CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2624	25758	CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2624
25759	CEFBS_InMicroMips, // SRLV_MM = 2625	25759	CEFBS_InMicroMips, // SRLV_MM = 2625
25760	CEFBS_HasStdEnc_HasMSA, // SRL_B = 2626	25760	CEFBS_HasStdEnc_HasMSA, // SRL_B = 2626
25761	CEFBS_HasStdEnc_HasMSA, // SRL_D = 2627	25761	CEFBS_HasStdEnc_HasMSA, // SRL_D = 2627
25762	CEFBS_HasStdEnc_HasMSA, // SRL_H = 2628	25762	CEFBS_HasStdEnc_HasMSA, // SRL_H = 2628
25763	CEFBS_InMicroMips, // SRL_MM = 2629	25763	CEFBS_InMicroMips, // SRL_MM = 2629
25764	CEFBS_HasStdEnc_HasMSA, // SRL_W = 2630	25764	CEFBS_HasStdEnc_HasMSA, // SRL_W = 2630
25765	CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2631	25765	CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2631
25766	CEFBS_InMicroMips, // SSNOP_MM = 2632	25766	CEFBS_InMicroMips, // SSNOP_MM = 2632
25767	CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2633	25767	CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2633
25768	CEFBS_HasStdEnc_HasMSA, // ST_B = 2634	25768	CEFBS_HasStdEnc_HasMSA, // ST_B = 2634
25769	CEFBS_HasStdEnc_HasMSA, // ST_D = 2635	25769	CEFBS_HasStdEnc_HasMSA, // ST_D = 2635
25770	CEFBS_HasStdEnc_HasMSA, // ST_H = 2636	25770	CEFBS_HasStdEnc_HasMSA, // ST_H = 2636
25771	CEFBS_HasStdEnc_HasMSA, // ST_W = 2637	25771	CEFBS_HasStdEnc_HasMSA, // ST_W = 2637
25772	CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2638	25772	CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2638
25773	CEFBS_HasDSPR2, // SUBQH_PH = 2639	25773	CEFBS_HasDSPR2, // SUBQH_PH = 2639
25774	CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2640	25774	CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2640
25775	CEFBS_HasDSPR2, // SUBQH_R_PH = 2641	25775	CEFBS_HasDSPR2, // SUBQH_R_PH = 2641
25776	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2642	25776	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2642
25777	CEFBS_HasDSPR2, // SUBQH_R_W = 2643	25777	CEFBS_HasDSPR2, // SUBQH_R_W = 2643
25778	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2644	25778	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2644
25779	CEFBS_HasDSPR2, // SUBQH_W = 2645	25779	CEFBS_HasDSPR2, // SUBQH_W = 2645
25780	CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2646	25780	CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2646
25781	CEFBS_HasDSP, // SUBQ_PH = 2647	25781	CEFBS_HasDSP, // SUBQ_PH = 2647
25782	CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2648	25782	CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2648
25783	CEFBS_HasDSP, // SUBQ_S_PH = 2649	25783	CEFBS_HasDSP, // SUBQ_S_PH = 2649
25784	CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2650	25784	CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2650
25785	CEFBS_HasDSP, // SUBQ_S_W = 2651	25785	CEFBS_HasDSP, // SUBQ_S_W = 2651
25786	CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2652	25786	CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2652
25787	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2653	25787	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2653
25788	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2654	25788	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2654
25789	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2655	25789	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2655
25790	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2656	25790	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2656
25791	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2657	25791	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2657
25792	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2658	25792	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2658
25793	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2659	25793	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2659
25794	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2660	25794	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2660
25795	CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2661	25795	CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2661
25796	CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2662	25796	CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2662
25797	CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2663	25797	CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2663
25798	CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2664	25798	CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2664
25799	CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2665	25799	CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2665
25800	CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2666	25800	CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2666
25801	CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2667	25801	CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2667
25802	CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2668	25802	CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2668
25803	CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2669	25803	CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2669
25804	CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2670	25804	CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2670
25805	CEFBS_HasDSPR2, // SUBUH_QB = 2671	25805	CEFBS_HasDSPR2, // SUBUH_QB = 2671
25806	CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2672	25806	CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2672
25807	CEFBS_HasDSPR2, // SUBUH_R_QB = 2673	25807	CEFBS_HasDSPR2, // SUBUH_R_QB = 2673
25808	CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2674	25808	CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2674
25809	CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2675	25809	CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2675
25810	CEFBS_HasDSPR2, // SUBU_PH = 2676	25810	CEFBS_HasDSPR2, // SUBU_PH = 2676
25811	CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2677	25811	CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2677
25812	CEFBS_HasDSP, // SUBU_QB = 2678	25812	CEFBS_HasDSP, // SUBU_QB = 2678
25813	CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2679	25813	CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2679
25814	CEFBS_HasDSPR2, // SUBU_S_PH = 2680	25814	CEFBS_HasDSPR2, // SUBU_S_PH = 2680
25815	CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2681	25815	CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2681
25816	CEFBS_HasDSP, // SUBU_S_QB = 2682	25816	CEFBS_HasDSP, // SUBU_S_QB = 2682
25817	CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2683	25817	CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2683
25818	CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2684	25818	CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2684
25819	CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2685	25819	CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2685
25820	CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2686	25820	CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2686
25821	CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2687	25821	CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2687
25822	CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2688	25822	CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2688
25823	CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2689	25823	CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2689
25824	CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2690	25824	CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2690
25825	CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2691	25825	CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2691
25826	CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2692	25826	CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2692
25827	CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2693	25827	CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2693
25828	CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2694	25828	CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2694
25829	CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2695	25829	CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2695
25830	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2696	25830	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2696
25831	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2697	25831	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2697
25832	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2698	25832	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2698
25833	CEFBS_HasStdEnc_NotInMicroMips, // SW = 2699	25833	CEFBS_HasStdEnc_NotInMicroMips, // SW = 2699
25834	CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2700	25834	CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2700
25835	CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2701	25835	CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2701
25836	CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2702	25836	CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2702
25837	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2703	25837	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2703
25838	CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2704	25838	CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2704
25839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2705	25839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2705
25840	CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2706	25840	CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2706
25841	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2707	25841	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2707
25842	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2708	25842	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2708
25843	CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2709	25843	CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2709
25844	CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2710	25844	CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2710
25845	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2711	25845	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2711
25846	CEFBS_InMicroMips_HasEVA, // SWE_MM = 2712	25846	CEFBS_InMicroMips_HasEVA, // SWE_MM = 2712
25847	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2713	25847	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2713
25848	CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2714	25848	CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2714
25849	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2715	25849	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2715
25850	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2716	25850	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2716
25851	CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2717	25851	CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2717
25852	CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2718	25852	CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2718
25853	CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2719	25853	CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2719
25854	CEFBS_InMicroMips, // SWM32_MM = 2720	25854	CEFBS_InMicroMips, // SWM32_MM = 2720
25855	CEFBS_InMicroMips, // SWP_MM = 2721	25855	CEFBS_InMicroMips, // SWP_MM = 2721
25856	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2722	25856	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2722
25857	CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2723	25857	CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2723
25858	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2724	25858	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2724
25859	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2725	25859	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2725
25860	CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2726	25860	CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2726
25861	CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2727	25861	CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2727
25862	CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2728	25862	CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2728
25863	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2729	25863	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2729
25864	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2730	25864	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2730
25865	CEFBS_InMicroMips, // SW_MM = 2731	25865	CEFBS_InMicroMips, // SW_MM = 2731
25866	CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2732	25866	CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2732
25867	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2733	25867	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2733
25868	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2734	25868	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2734
25869	CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2735	25869	CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2735
25870	CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2736	25870	CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2736
25871	CEFBS_InMicroMips, // SYNC_MM = 2737	25871	CEFBS_InMicroMips, // SYNC_MM = 2737
25872	CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2738	25872	CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2738
25873	CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2739	25873	CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2739
25874	CEFBS_InMicroMips, // SYSCALL_MM = 2740	25874	CEFBS_InMicroMips, // SYSCALL_MM = 2740
25875	CEFBS_InMips16Mode, // Save16 = 2741	25875	CEFBS_InMips16Mode, // Save16 = 2741
25876	CEFBS_InMips16Mode, // SaveX16 = 2742	25876	CEFBS_InMips16Mode, // SaveX16 = 2742
25877	CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2743	25877	CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2743
25878	CEFBS_InMips16Mode, // SebRx16 = 2744	25878	CEFBS_InMips16Mode, // SebRx16 = 2744
25879	CEFBS_InMips16Mode, // SehRx16 = 2745	25879	CEFBS_InMips16Mode, // SehRx16 = 2745
25880	CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2746	25880	CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2746
25881	CEFBS_InMips16Mode, // SllX16 = 2747	25881	CEFBS_InMips16Mode, // SllX16 = 2747
25882	CEFBS_InMips16Mode, // SllvRxRy16 = 2748	25882	CEFBS_InMips16Mode, // SllvRxRy16 = 2748
25883	CEFBS_InMips16Mode, // SltRxRy16 = 2749	25883	CEFBS_InMips16Mode, // SltRxRy16 = 2749
25884	CEFBS_InMips16Mode, // SltiRxImm16 = 2750	25884	CEFBS_InMips16Mode, // SltiRxImm16 = 2750
25885	CEFBS_InMips16Mode, // SltiRxImmX16 = 2751	25885	CEFBS_InMips16Mode, // SltiRxImmX16 = 2751
25886	CEFBS_InMips16Mode, // SltiuRxImm16 = 2752	25886	CEFBS_InMips16Mode, // SltiuRxImm16 = 2752
25887	CEFBS_InMips16Mode, // SltiuRxImmX16 = 2753	25887	CEFBS_InMips16Mode, // SltiuRxImmX16 = 2753
25888	CEFBS_InMips16Mode, // SltuRxRy16 = 2754	25888	CEFBS_InMips16Mode, // SltuRxRy16 = 2754
25889	CEFBS_InMips16Mode, // SraX16 = 2755	25889	CEFBS_InMips16Mode, // SraX16 = 2755
25890	CEFBS_InMips16Mode, // SravRxRy16 = 2756	25890	CEFBS_InMips16Mode, // SravRxRy16 = 2756
25891	CEFBS_InMips16Mode, // SrlX16 = 2757	25891	CEFBS_InMips16Mode, // SrlX16 = 2757
25892	CEFBS_InMips16Mode, // SrlvRxRy16 = 2758	25892	CEFBS_InMips16Mode, // SrlvRxRy16 = 2758
25893	CEFBS_InMips16Mode, // SubuRxRyRz16 = 2759	25893	CEFBS_InMips16Mode, // SubuRxRyRz16 = 2759
25894	CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2760	25894	CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2760
25895	CEFBS_InMips16Mode, // SwRxSpImmX16 = 2761	25895	CEFBS_InMips16Mode, // SwRxSpImmX16 = 2761
25896	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2762	25896	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2762
25897	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2763	25897	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2763
25898	CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2764	25898	CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2764
25899	CEFBS_InMicroMips, // TEQ_MM = 2765	25899	CEFBS_InMicroMips, // TEQ_MM = 2765
25900	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2766	25900	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2766
25901	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2767	25901	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2767
25902	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2768	25902	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2768
25903	CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2769	25903	CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2769
25904	CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2770	25904	CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2770
25905	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2771	25905	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2771
25906	CEFBS_InMicroMips, // TGEU_MM = 2772	25906	CEFBS_InMicroMips, // TGEU_MM = 2772
25907	CEFBS_InMicroMips, // TGE_MM = 2773	25907	CEFBS_InMicroMips, // TGE_MM = 2773
25908	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2774	25908	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2774
25909	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2775	25909	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2775
25910	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2776	25910	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2776
25911	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2777	25911	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2777
25912	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2778	25912	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2778
25913	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2779	25913	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2779
25914	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2780	25914	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2780
25915	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2781	25915	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2781
25916	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2782	25916	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2782
25917	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2783	25917	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2783
25918	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2784	25918	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2784
25919	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2785	25919	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2785
25920	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2786	25920	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2786
25921	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2787	25921	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2787
25922	CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2788	25922	CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2788
25923	CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2789	25923	CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2789
25924	CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2790	25924	CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2790
25925	CEFBS_InMicroMips, // TLBP_MM = 2791	25925	CEFBS_InMicroMips, // TLBP_MM = 2791
25926	CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2792	25926	CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2792
25927	CEFBS_InMicroMips, // TLBR_MM = 2793	25927	CEFBS_InMicroMips, // TLBR_MM = 2793
25928	CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2794	25928	CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2794
25929	CEFBS_InMicroMips, // TLBWI_MM = 2795	25929	CEFBS_InMicroMips, // TLBWI_MM = 2795
25930	CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2796	25930	CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2796
25931	CEFBS_InMicroMips, // TLBWR_MM = 2797	25931	CEFBS_InMicroMips, // TLBWR_MM = 2797
25932	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2798	25932	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2798
25933	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2799	25933	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2799
25934	CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2800	25934	CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2800
25935	CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2801	25935	CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2801
25936	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2802	25936	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2802
25937	CEFBS_InMicroMips, // TLTU_MM = 2803	25937	CEFBS_InMicroMips, // TLTU_MM = 2803
25938	CEFBS_InMicroMips, // TLT_MM = 2804	25938	CEFBS_InMicroMips, // TLT_MM = 2804
25939	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2805	25939	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2805
25940	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2806	25940	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2806
25941	CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2807	25941	CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2807
25942	CEFBS_InMicroMips, // TNE_MM = 2808	25942	CEFBS_InMicroMips, // TNE_MM = 2808
25943	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2809	25943	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2809
25944	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2810	25944	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2810
25945	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2811	25945	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2811
25946	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2812	25946	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2812
25947	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2813	25947	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2813
25948	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2814	25948	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2814
25949	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2815	25949	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2815
25950	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2816	25950	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2816
25951	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2817	25951	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2817
25952	CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2818	25952	CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2818
25953	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2819	25953	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2819
25954	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2820	25954	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2820
25955	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2821	25955	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2821
25956	CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2822	25956	CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2822
25957	CEFBS_HasCnMips, // V3MULU = 2823	25957	CEFBS_HasCnMips, // V3MULU = 2823
25958	CEFBS_HasCnMips, // VMM0 = 2824	25958	CEFBS_HasCnMips, // VMM0 = 2824
25959	CEFBS_HasCnMips, // VMULU = 2825	25959	CEFBS_HasCnMips, // VMULU = 2825
25960	CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2826	25960	CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2826
25961	CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2827	25961	CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2827
25962	CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2828	25962	CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2828
25963	CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2829	25963	CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2829
25964	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2830	25964	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2830
25965	CEFBS_InMicroMips, // WAIT_MM = 2831	25965	CEFBS_InMicroMips, // WAIT_MM = 2831
25966	CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2832	25966	CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2832
25967	CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2833	25967	CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2833
25968	CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2834	25968	CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2834
25969	CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2835	25969	CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2835
25970	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2836	25970	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2836
25971	CEFBS_InMicroMips, // WSBH_MM = 2837	25971	CEFBS_InMicroMips, // WSBH_MM = 2837
25972	CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2838	25972	CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2838
25973	CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2839	25973	CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2839
25974	CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2840	25974	CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2840
25975	CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2841	25975	CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2841
25976	CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2842	25976	CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2842
25977	CEFBS_HasStdEnc_HasMSA, // XORI_B = 2843	25977	CEFBS_HasStdEnc_HasMSA, // XORI_B = 2843
25978	CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2844	25978	CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2844
25979	CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2845	25979	CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2845
25980	CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2846	25980	CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2846
25981	CEFBS_HasStdEnc_HasMSA, // XOR_V = 2847	25981	CEFBS_HasStdEnc_HasMSA, // XOR_V = 2847
25982	CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2848	25982	CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2848
25983	CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2849	25983	CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2849
25984	CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2850	25984	CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2850
25985	CEFBS_InMips16Mode, // XorRxRxRy16 = 2851	25985	CEFBS_InMips16Mode, // XorRxRxRy16 = 2851
25986	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2852	25986	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2852
25987	};	25987	};
25988		25988
25989	assert(Opcode < 2853);	25989	assert(Opcode < 2853);
25990	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];	25990	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
25991	}	25991	}
25992		25992
25993	} // end namespace Mips_MC	25993	} // end namespace Mips_MC
25994	} // end namespace llvm	25994	} // end namespace llvm
25995	#endif // GET_COMPUTE_FEATURES	25995	#endif // GET_COMPUTE_FEATURES
25996		25996
25997	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER	25997	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
25998	#undef ENABLE_INSTR_PREDICATE_VERIFIER	25998	#undef ENABLE_INSTR_PREDICATE_VERIFIER
25999	#include	25999	#include
26000		26000
26001	namespace llvm {	26001	namespace llvm {
26002	namespace Mips_MC {	26002	namespace Mips_MC {
26003		26003
26004	#ifndef NDEBUG	26004	#ifndef NDEBUG
26005	static const char *SubtargetFeatureNames[] = {	26005	static const char *SubtargetFeatureNames[] = {
26006	"Feature_HasCRC",	26006	"Feature_HasCRC",
26007	"Feature_HasCnMips",	26007	"Feature_HasCnMips",
26008	"Feature_HasCnMipsP",	26008	"Feature_HasCnMipsP",
26009	"Feature_HasDSP",	26009	"Feature_HasDSP",
26010	"Feature_HasDSPR2",	26010	"Feature_HasDSPR2",
26011	"Feature_HasDSPR3",	26011	"Feature_HasDSPR3",
26012	"Feature_HasEVA",	26012	"Feature_HasEVA",
26013	"Feature_HasGINV",	26013	"Feature_HasGINV",
26014	"Feature_HasMSA",	26014	"Feature_HasMSA",
26015	"Feature_HasMT",	26015	"Feature_HasMT",
26016	"Feature_HasMadd4",	26016	"Feature_HasMadd4",
26017	"Feature_HasMips2",	26017	"Feature_HasMips2",
26018	"Feature_HasMips3",	26018	"Feature_HasMips3",
26019	"Feature_HasMips3D",	26019	"Feature_HasMips3D",
26020	"Feature_HasMips3_32",	26020	"Feature_HasMips3_32",
26021	"Feature_HasMips3_32r2",	26021	"Feature_HasMips3_32r2",
26022	"Feature_HasMips4_32",	26022	"Feature_HasMips4_32",
26023	"Feature_HasMips4_32r2",	26023	"Feature_HasMips4_32r2",
26024	"Feature_HasMips5_32r2",	26024	"Feature_HasMips5_32r2",
26025	"Feature_HasMips32",	26025	"Feature_HasMips32",
26026	"Feature_HasMips32r2",	26026	"Feature_HasMips32r2",
26027	"Feature_HasMips32r5",	26027	"Feature_HasMips32r5",
26028	"Feature_HasMips32r6",	26028	"Feature_HasMips32r6",
26029	"Feature_HasMips64",	26029	"Feature_HasMips64",
26030	"Feature_HasMips64r2",	26030	"Feature_HasMips64r2",
26031	"Feature_HasMips64r5",	26031	"Feature_HasMips64r5",
26032	"Feature_HasMips64r6",	26032	"Feature_HasMips64r6",
26033	"Feature_HasStdEnc",	26033	"Feature_HasStdEnc",
26034	"Feature_HasVirt",	26034	"Feature_HasVirt",
26035	"Feature_InMicroMips",	26035	"Feature_InMicroMips",
26036	"Feature_InMips16Mode",	26036	"Feature_InMips16Mode",
26037	"Feature_IsFP64bit",	26037	"Feature_IsFP64bit",
26038	"Feature_IsGP32bit",	26038	"Feature_IsGP32bit",
26039	"Feature_IsGP64bit",	26039	"Feature_IsGP64bit",
26040	"Feature_IsNotSingleFloat",	26040	"Feature_IsNotSingleFloat",
26041	"Feature_IsNotSoftFloat",	26041	"Feature_IsNotSoftFloat",
26042	"Feature_IsPTR32bit",	26042	"Feature_IsPTR32bit",
26043	"Feature_IsPTR64bit",	26043	"Feature_IsPTR64bit",
26044	"Feature_IsSingleFloat",	26044	"Feature_IsSingleFloat",
26045	"Feature_IsSym32",	26045	"Feature_IsSym32",
26046	"Feature_IsSym64",	26046	"Feature_IsSym64",
26047	"Feature_NoIndirectJumpGuards",	26047	"Feature_NoIndirectJumpGuards",
26048	"Feature_NotCnMips",	26048	"Feature_NotCnMips",
26049	"Feature_NotCnMipsP",	26049	"Feature_NotCnMipsP",
26050	"Feature_NotFP64bit",	26050	"Feature_NotFP64bit",
26051	"Feature_NotInMicroMips",	26051	"Feature_NotInMicroMips",
26052	"Feature_NotInMips16Mode",	26052	"Feature_NotInMips16Mode",
26053	"Feature_NotMips3",	26053	"Feature_NotMips3",
26054	"Feature_NotMips4_32",	26054	"Feature_NotMips4_32",
26055	"Feature_NotMips32r6",	26055	"Feature_NotMips32r6",
26056	"Feature_NotMips64",	26056	"Feature_NotMips64",
26057	"Feature_NotMips64r6",	26057	"Feature_NotMips64r6",
26058	"Feature_UseIndirectJumpsHazard",	26058	"Feature_UseIndirectJumpsHazard",
26059	nullptr	26059	nullptr
26060	};	26060	};
26061		26061
26062	#endif // NDEBUG	26062	#endif // NDEBUG
26063		26063
26064	void verifyInstructionPredicates(	26064	void verifyInstructionPredicates(
26065	unsigned Opcode, const FeatureBitset &Features) {	26065	unsigned Opcode, const FeatureBitset &Features) {
26066	#ifndef NDEBUG	26066	#ifndef NDEBUG
26067	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);	26067	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
26068	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);	26068	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
26069	FeatureBitset MissingFeatures =	26069	FeatureBitset MissingFeatures =
26070	(AvailableFeatures & RequiredFeatures) ^	26070	(AvailableFeatures & RequiredFeatures) ^
26071	RequiredFeatures;	26071	RequiredFeatures;
26072	if (MissingFeatures.any()) {	26072	if (MissingFeatures.any()) {
26073	std::ostringstream Msg;	26073	std::ostringstream Msg;
26074	Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]	26074	Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]
26075	<< " instruction but the ";	26075	<< " instruction but the ";
26076	for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)	26076	for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
26077	if (MissingFeatures.test(i))	26077	if (MissingFeatures.test(i))
26078	Msg << SubtargetFeatureNames[i] << " ";	26078	Msg << SubtargetFeatureNames[i] << " ";
26079	Msg << "predicate(s) are not met";	26079	Msg << "predicate(s) are not met";
26080	report_fatal_error(Msg.str().c_str());	26080	report_fatal_error(Msg.str().c_str());
26081	}	26081	}
26082	#endif // NDEBUG	26082	#endif // NDEBUG
26083	}	26083	}
26084	} // end namespace Mips_MC	26084	} // end namespace Mips_MC
26085	} // end namespace llvm	26085	} // end namespace llvm
26086	#endif // ENABLE_INSTR_PREDICATE_VERIFIER	26086	#endif // ENABLE_INSTR_PREDICATE_VERIFIER
26087		26087
26088	#ifdef GET_INSTRMAP_INFO	26088	#ifdef GET_INSTRMAP_INFO
26089	#undef GET_INSTRMAP_INFO	26089	#undef GET_INSTRMAP_INFO
26090	namespace llvm {	26090	namespace llvm {
26091		26091
26092	namespace Mips {	26092	namespace Mips {
26093		26093
26094	enum Arch {	26094	enum Arch {
26095	Arch_dsp,	26095	Arch_dsp,
26096	Arch_mmdsp,	26096	Arch_mmdsp,
26097	Arch_mipsr6,	26097	Arch_mipsr6,
26098	Arch_micromipsr6,	26098	Arch_micromipsr6,
26099	Arch_se,	26099	Arch_se,
26100	Arch_micromips	26100	Arch_micromips
26101	};	26101	};
26102		26102
26103	// Dsp2MicroMips	26103	// Dsp2MicroMips
26104	LLVM_READONLY	26104	LLVM_READONLY
26105	int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {	26105	int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {
26106	static const uint16_t Dsp2MicroMipsTable[][3] = {	26106	static const uint16_t Dsp2MicroMipsTable[][3] = {
26107	{ Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },	26107	{ Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },
26108	{ Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },	26108	{ Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },
26109	{ Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },	26109	{ Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },
26110	{ Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },	26110	{ Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },
26111	{ Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },	26111	{ Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },
26112	{ Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },	26112	{ Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },
26113	{ Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },	26113	{ Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },
26114	{ Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },	26114	{ Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },
26115	{ Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },	26115	{ Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },
26116	{ Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },	26116	{ Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },
26117	{ Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },	26117	{ Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },
26118	{ Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },	26118	{ Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },
26119	{ Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },	26119	{ Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },
26120	{ Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },	26120	{ Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },
26121	{ Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },	26121	{ Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },
26122	{ Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },	26122	{ Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },
26123	{ Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },	26123	{ Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },
26124	{ Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },	26124	{ Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },
26125	{ Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },	26125	{ Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },
26126	{ Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },	26126	{ Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },
26127	{ Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },	26127	{ Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },
26128	{ Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },	26128	{ Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },
26129	{ Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },	26129	{ Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },
26130	{ Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },	26130	{ Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },
26131	{ Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },	26131	{ Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },
26132	{ Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },	26132	{ Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },
26133	{ Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },	26133	{ Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },
26134	{ Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },	26134	{ Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },
26135	{ Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },	26135	{ Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },
26136	{ Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },	26136	{ Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },
26137	{ Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },	26137	{ Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },
26138	{ Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },	26138	{ Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },
26139	{ Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },	26139	{ Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },
26140	{ Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },	26140	{ Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },
26141	{ Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },	26141	{ Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },
26142	{ Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },	26142	{ Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },
26143	{ Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },	26143	{ Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },
26144	{ Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },	26144	{ Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },
26145	{ Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },	26145	{ Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },
26146	{ Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },	26146	{ Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },
26147	{ Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },	26147	{ Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },
26148	{ Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },	26148	{ Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },
26149	{ Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },	26149	{ Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },
26150	{ Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },	26150	{ Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },
26151	{ Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },	26151	{ Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },
26152	{ Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },	26152	{ Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },
26153	{ Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },	26153	{ Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },
26154	{ Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },	26154	{ Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },
26155	{ Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },	26155	{ Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },
26156	{ Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },	26156	{ Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },
26157	{ Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },	26157	{ Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },
26158	{ Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },	26158	{ Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },
26159	{ Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },	26159	{ Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },
26160	{ Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },	26160	{ Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },
26161	{ Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },	26161	{ Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },
26162	{ Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },	26162	{ Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },
26163	{ Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },	26163	{ Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },
26164	{ Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },	26164	{ Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },
26165	{ Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },	26165	{ Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },
26166	{ Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },	26166	{ Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },
26167	{ Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },	26167	{ Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },
26168	{ Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },	26168	{ Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },
26169	{ Mips::INSV, Mips::INSV, Mips::INSV_MM },	26169	{ Mips::INSV, Mips::INSV, Mips::INSV_MM },
26170	{ Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },	26170	{ Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },
26171	{ Mips::LHX, Mips::LHX, Mips::LHX_MM },	26171	{ Mips::LHX, Mips::LHX, Mips::LHX_MM },
26172	{ Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },	26172	{ Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },
26173	{ Mips::LWX, Mips::LWX, Mips::LWX_MM },	26173	{ Mips::LWX, Mips::LWX, Mips::LWX_MM },
26174	{ Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },	26174	{ Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },
26175	{ Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },	26175	{ Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },
26176	{ Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },	26176	{ Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },
26177	{ Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },	26177	{ Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },
26178	{ Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },	26178	{ Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },
26179	{ Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },	26179	{ Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },
26180	{ Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },	26180	{ Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },
26181	{ Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },	26181	{ Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },
26182	{ Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },	26182	{ Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },
26183	{ Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },	26183	{ Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },
26184	{ Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },	26184	{ Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },
26185	{ Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },	26185	{ Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },
26186	{ Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },	26186	{ Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },
26187	{ Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },	26187	{ Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },
26188	{ Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },	26188	{ Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },
26189	{ Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },	26189	{ Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },
26190	{ Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },	26190	{ Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },
26191	{ Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },	26191	{ Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },
26192	{ Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },	26192	{ Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },
26193	{ Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },	26193	{ Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },
26194	{ Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },	26194	{ Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },
26195	{ Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },	26195	{ Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },
26196	{ Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },	26196	{ Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },
26197	{ Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },	26197	{ Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },
26198	{ Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },	26198	{ Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },
26199	{ Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },	26199	{ Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },
26200	{ Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },	26200	{ Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },
26201	{ Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },	26201	{ Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },
26202	{ Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },	26202	{ Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },
26203	{ Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },	26203	{ Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },
26204	{ Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },	26204	{ Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },
26205	{ Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },	26205	{ Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },
26206	{ Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },	26206	{ Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },
26207	{ Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },	26207	{ Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },
26208	{ Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },	26208	{ Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },
26209	{ Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },	26209	{ Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },
26210	{ Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },	26210	{ Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },
26211	{ Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },	26211	{ Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },
26212	{ Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },	26212	{ Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },
26213	{ Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },	26213	{ Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },
26214	{ Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },	26214	{ Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },
26215	{ Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },	26215	{ Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },
26216	{ Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },	26216	{ Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },
26217	{ Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },	26217	{ Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },
26218	{ Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },	26218	{ Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },
26219	{ Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },	26219	{ Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },
26220	{ Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },	26220	{ Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },
26221	{ Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },	26221	{ Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },
26222	{ Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },	26222	{ Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },
26223	{ Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },	26223	{ Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },
26224	{ Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },	26224	{ Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },
26225	{ Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },	26225	{ Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },
26226	{ Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },	26226	{ Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },
26227	{ Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },	26227	{ Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },
26228	{ Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },	26228	{ Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },
26229	{ Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },	26229	{ Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },
26230	{ Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },	26230	{ Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },
26231	{ Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },	26231	{ Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },
26232	{ Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },	26232	{ Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },
26233	{ Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },	26233	{ Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },
26234	{ Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },	26234	{ Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },
26235	{ Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },	26235	{ Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },
26236	{ Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },	26236	{ Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },
26237	{ Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },	26237	{ Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },
26238	{ Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },	26238	{ Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },
26239	{ Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },	26239	{ Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },
26240	{ Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },	26240	{ Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },
26241	{ Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },	26241	{ Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },
26242	{ Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },	26242	{ Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },
26243	{ Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },	26243	{ Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },
26244	{ Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },	26244	{ Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },
26245	{ Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },	26245	{ Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },
26246	{ Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },	26246	{ Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },
26247	{ Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },	26247	{ Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },
26248	{ Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },	26248	{ Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },
26249	{ Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },	26249	{ Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },
26250	{ Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },	26250	{ Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },
26251	{ Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },	26251	{ Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },
26252	{ Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },	26252	{ Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },
26253	{ Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },	26253	{ Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },
26254	{ Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },	26254	{ Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },
26255	{ Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },	26255	{ Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },
26256	{ Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },	26256	{ Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },
26257	{ Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },	26257	{ Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },
26258	{ Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },	26258	{ Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },
26259	{ Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },	26259	{ Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },
26260	{ Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },	26260	{ Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },
26261	{ Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },	26261	{ Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },
26262	{ Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },	26262	{ Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },
26263	{ Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },	26263	{ Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },
26264	{ Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },	26264	{ Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },
26265	{ Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },	26265	{ Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },
26266	{ Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },	26266	{ Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },
26267	}; // End of Dsp2MicroMipsTable	26267	}; // End of Dsp2MicroMipsTable
26268		26268
26269	unsigned mid;	26269	unsigned mid;
26270	unsigned start = 0;	26270	unsigned start = 0;
26271	unsigned end = 160;	26271	unsigned end = 160;
26272	while (start < end) {	26272	while (start < end) {
26273	mid = start + (end - start) / 2;	26273	mid = start + (end - start) / 2;
26274	if (Opcode == Dsp2MicroMipsTable[mid][0]) {	26274	if (Opcode == Dsp2MicroMipsTable[mid][0]) {
26275	break;	26275	break;
26276	}	26276	}
26277	if (Opcode < Dsp2MicroMipsTable[mid][0])	26277	if (Opcode < Dsp2MicroMipsTable[mid][0])
26278	end = mid;	26278	end = mid;
26279	else	26279	else
26280	start = mid + 1;	26280	start = mid + 1;
26281	}	26281	}
26282	if (start == end)	26282	if (start == end)
26283	return -1; // Instruction doesn't exist in this table.	26283	return -1; // Instruction doesn't exist in this table.
26284		26284
26285	if (inArch == Arch_dsp)	26285	if (inArch == Arch_dsp)
26286	return Dsp2MicroMipsTable[mid][1];	26286	return Dsp2MicroMipsTable[mid][1];
26287	if (inArch == Arch_mmdsp)	26287	if (inArch == Arch_mmdsp)
26288	return Dsp2MicroMipsTable[mid][2];	26288	return Dsp2MicroMipsTable[mid][2];
26289	return -1;}	26289	return -1;}
26290		26290
26291	// MipsR62MicroMipsR6	26291	// MipsR62MicroMipsR6
26292	LLVM_READONLY	26292	LLVM_READONLY
26293	int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	26293	int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
26294	static const uint16_t MipsR62MicroMipsR6Table[][3] = {	26294	static const uint16_t MipsR62MicroMipsR6Table[][3] = {
26295	{ Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },	26295	{ Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },
26296	{ Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },	26296	{ Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },
26297	{ Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },	26297	{ Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },
26298	{ Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },	26298	{ Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },
26299	{ Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },	26299	{ Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },
26300	{ Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },	26300	{ Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },
26301	{ Mips::BC, Mips::BC, Mips::BC_MMR6 },	26301	{ Mips::BC, Mips::BC, Mips::BC_MMR6 },
26302	{ Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },	26302	{ Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },
26303	{ Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },	26303	{ Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },
26304	{ Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },	26304	{ Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },
26305	{ Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },	26305	{ Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },
26306	{ Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },	26306	{ Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },
26307	{ Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },	26307	{ Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },
26308	{ Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },	26308	{ Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },
26309	{ Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },	26309	{ Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },
26310	{ Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },	26310	{ Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },
26311	{ Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },	26311	{ Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },
26312	{ Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },	26312	{ Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },
26313	{ Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },	26313	{ Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },
26314	{ Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },	26314	{ Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },
26315	{ Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },	26315	{ Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },
26316	{ Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },	26316	{ Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },
26317	{ Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },	26317	{ Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },
26318	{ Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },	26318	{ Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },
26319	{ Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },	26319	{ Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },
26320	{ Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },	26320	{ Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },
26321	{ Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },	26321	{ Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },
26322	{ Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },	26322	{ Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },
26323	{ Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },	26323	{ Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },
26324	{ Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },	26324	{ Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },
26325	{ Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },	26325	{ Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },
26326	{ Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },	26326	{ Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },
26327	{ Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },	26327	{ Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },
26328	{ Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },	26328	{ Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },
26329	{ Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },	26329	{ Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },
26330	{ Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },	26330	{ Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },
26331	{ Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },	26331	{ Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },
26332	{ Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },	26332	{ Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },
26333	{ Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },	26333	{ Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },
26334	{ Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },	26334	{ Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },
26335	{ Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },	26335	{ Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },
26336	{ Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },	26336	{ Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },
26337	{ Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },	26337	{ Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },
26338	{ Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },	26338	{ Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },
26339	{ Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },	26339	{ Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },
26340	{ Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },	26340	{ Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },
26341	{ Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },	26341	{ Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },
26342	{ Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },	26342	{ Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },
26343	{ Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },	26343	{ Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },
26344	{ Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },	26344	{ Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },
26345	{ Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },	26345	{ Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },
26346	{ Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },	26346	{ Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },
26347	{ Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },	26347	{ Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },
26348	{ Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },	26348	{ Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },
26349	{ Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },	26349	{ Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },
26350	{ Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },	26350	{ Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },
26351	{ Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },	26351	{ Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },
26352	{ Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },	26352	{ Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },
26353	{ Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },	26353	{ Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },
26354	{ Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },	26354	{ Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },
26355	{ Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },	26355	{ Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },
26356	{ Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },	26356	{ Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },
26357	{ Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },	26357	{ Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },
26358	{ Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },	26358	{ Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },
26359	{ Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },	26359	{ Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },
26360	{ Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },	26360	{ Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },
26361	{ Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },	26361	{ Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },
26362	{ Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },	26362	{ Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },
26363	{ Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },	26363	{ Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },
26364	{ Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },	26364	{ Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },
26365	{ Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },	26365	{ Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },
26366	{ Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },	26366	{ Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },
26367	{ Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },	26367	{ Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },
26368	{ Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },	26368	{ Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },
26369	{ Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },	26369	{ Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },
26370	{ Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },	26370	{ Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },
26371	{ Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },	26371	{ Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },
26372	{ Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },	26372	{ Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },
26373	{ Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },	26373	{ Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },
26374	{ Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },	26374	{ Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },
26375	{ Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },	26375	{ Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },
26376	{ Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },	26376	{ Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },
26377	{ Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },	26377	{ Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },
26378	{ Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },	26378	{ Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },
26379	{ Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },	26379	{ Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },
26380	{ Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },	26380	{ Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },
26381	{ Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },	26381	{ Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },
26382	{ Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },	26382	{ Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },
26383	{ Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },	26383	{ Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },
26384	{ Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },	26384	{ Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },
26385	{ Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },	26385	{ Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },
26386	{ Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },	26386	{ Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },
26387	{ Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },	26387	{ Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },
26388	{ Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },	26388	{ Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },
26389	{ Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },	26389	{ Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },
26390	{ Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },	26390	{ Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },
26391	}; // End of MipsR62MicroMipsR6Table	26391	}; // End of MipsR62MicroMipsR6Table
26392		26392
26393	unsigned mid;	26393	unsigned mid;
26394	unsigned start = 0;	26394	unsigned start = 0;
26395	unsigned end = 96;	26395	unsigned end = 96;
26396	while (start < end) {	26396	while (start < end) {
26397	mid = start + (end - start) / 2;	26397	mid = start + (end - start) / 2;
26398	if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {	26398	if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {
26399	break;	26399	break;
26400	}	26400	}
26401	if (Opcode < MipsR62MicroMipsR6Table[mid][0])	26401	if (Opcode < MipsR62MicroMipsR6Table[mid][0])
26402	end = mid;	26402	end = mid;
26403	else	26403	else
26404	start = mid + 1;	26404	start = mid + 1;
26405	}	26405	}
26406	if (start == end)	26406	if (start == end)
26407	return -1; // Instruction doesn't exist in this table.	26407	return -1; // Instruction doesn't exist in this table.
26408		26408
26409	if (inArch == Arch_mipsr6)	26409	if (inArch == Arch_mipsr6)
26410	return MipsR62MicroMipsR6Table[mid][1];	26410	return MipsR62MicroMipsR6Table[mid][1];
26411	if (inArch == Arch_micromipsr6)	26411	if (inArch == Arch_micromipsr6)
26412	return MipsR62MicroMipsR6Table[mid][2];	26412	return MipsR62MicroMipsR6Table[mid][2];
26413	return -1;}	26413	return -1;}
26414		26414
26415	// Std2MicroMips	26415	// Std2MicroMips
26416	LLVM_READONLY	26416	LLVM_READONLY
26417	int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {	26417	int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {
26418	static const uint16_t Std2MicroMipsTable[][3] = {	26418	static const uint16_t Std2MicroMipsTable[][3] = {
26419	{ Mips::ADD, Mips::ADD, Mips::ADD_MM },	26419	{ Mips::ADD, Mips::ADD, Mips::ADD_MM },
26420	{ Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },	26420	{ Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },
26421	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },	26421	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },
26422	{ Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },	26422	{ Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },
26423	{ Mips::AND, Mips::AND, Mips::AND_MM },	26423	{ Mips::AND, Mips::AND, Mips::AND_MM },
26424	{ Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },	26424	{ Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },
26425	{ Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },	26425	{ Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },
26426	{ Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },	26426	{ Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },
26427	{ Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },	26427	{ Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },
26428	{ Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },	26428	{ Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },
26429	{ Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },	26429	{ Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },
26430	{ Mips::BEQL, Mips::BEQL, (uint16_t)-1U },	26430	{ Mips::BEQL, Mips::BEQL, (uint16_t)-1U },
26431	{ Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },	26431	{ Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },
26432	{ Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },	26432	{ Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },
26433	{ Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },	26433	{ Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },
26434	{ Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },	26434	{ Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },
26435	{ Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },	26435	{ Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },
26436	{ Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },	26436	{ Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },
26437	{ Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },	26437	{ Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },
26438	{ Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },	26438	{ Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },
26439	{ Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },	26439	{ Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },
26440	{ Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },	26440	{ Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },
26441	{ Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },	26441	{ Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },
26442	{ Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },	26442	{ Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },
26443	{ Mips::BNE, Mips::BNE, Mips::BNE_MM },	26443	{ Mips::BNE, Mips::BNE, Mips::BNE_MM },
26444	{ Mips::BNEL, Mips::BNEL, (uint16_t)-1U },	26444	{ Mips::BNEL, Mips::BNEL, (uint16_t)-1U },
26445	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },	26445	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },
26446	{ Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },	26446	{ Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },
26447	{ Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },	26447	{ Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },
26448	{ Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },	26448	{ Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },
26449	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },	26449	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },
26450	{ Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },	26450	{ Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },
26451	{ Mips::CLO, Mips::CLO, Mips::CLO_MM },	26451	{ Mips::CLO, Mips::CLO, Mips::CLO_MM },
26452	{ Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },	26452	{ Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },
26453	{ Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },	26453	{ Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },
26454	{ Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },	26454	{ Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },
26455	{ Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },	26455	{ Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },
26456	{ Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },	26456	{ Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },
26457	{ Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },	26457	{ Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },
26458	{ Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },	26458	{ Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },
26459	{ Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },	26459	{ Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },
26460	{ Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },	26460	{ Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },
26461	{ Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },	26461	{ Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },
26462	{ Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },	26462	{ Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },
26463	{ Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },	26463	{ Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },
26464	{ Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },	26464	{ Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },
26465	{ Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },	26465	{ Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },
26466	{ Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },	26466	{ Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },
26467	{ Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },	26467	{ Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },
26468	{ Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },	26468	{ Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },
26469	{ Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },	26469	{ Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },
26470	{ Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },	26470	{ Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },
26471	{ Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },	26471	{ Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },
26472	{ Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },	26472	{ Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },
26473	{ Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },	26473	{ Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },
26474	{ Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },	26474	{ Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },
26475	{ Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },	26475	{ Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },
26476	{ Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },	26476	{ Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },
26477	{ Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },	26477	{ Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },
26478	{ Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },	26478	{ Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },
26479	{ Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },	26479	{ Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },
26480	{ Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },	26480	{ Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },
26481	{ Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },	26481	{ Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },
26482	{ Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },	26482	{ Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },
26483	{ Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },	26483	{ Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },
26484	{ Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },	26484	{ Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },
26485	{ Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },	26485	{ Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },
26486	{ Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },	26486	{ Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },
26487	{ Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },	26487	{ Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },
26488	{ Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },	26488	{ Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },
26489	{ Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },	26489	{ Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },
26490	{ Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },	26490	{ Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },
26491	{ Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },	26491	{ Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },
26492	{ Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },	26492	{ Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },
26493	{ Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },	26493	{ Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },
26494	{ Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },	26494	{ Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },
26495	{ Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },	26495	{ Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },
26496	{ Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },	26496	{ Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },
26497	{ Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },	26497	{ Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },
26498	{ Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },	26498	{ Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },
26499	{ Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },	26499	{ Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },
26500	{ Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },	26500	{ Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },
26501	{ Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },	26501	{ Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },
26502	{ Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },	26502	{ Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },
26503	{ Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },	26503	{ Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },
26504	{ Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },	26504	{ Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },
26505	{ Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },	26505	{ Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },
26506	{ Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },	26506	{ Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },
26507	{ Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },	26507	{ Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },
26508	{ Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },	26508	{ Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },
26509	{ Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },	26509	{ Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },
26510	{ Mips::DERET, Mips::DERET, Mips::DERET_MM },	26510	{ Mips::DERET, Mips::DERET, Mips::DERET_MM },
26511	{ Mips::DI, Mips::DI, Mips::DI_MM },	26511	{ Mips::DI, Mips::DI, Mips::DI_MM },
26512	{ Mips::EHB, Mips::EHB, Mips::EHB_MM },	26512	{ Mips::EHB, Mips::EHB, Mips::EHB_MM },
26513	{ Mips::EI, Mips::EI, Mips::EI_MM },	26513	{ Mips::EI, Mips::EI, Mips::EI_MM },
26514	{ Mips::ERET, Mips::ERET, Mips::ERET_MM },	26514	{ Mips::ERET, Mips::ERET, Mips::ERET_MM },
26515	{ Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },	26515	{ Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },
26516	{ Mips::EXT, Mips::EXT, Mips::EXT_MM },	26516	{ Mips::EXT, Mips::EXT, Mips::EXT_MM },
26517	{ Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },	26517	{ Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },
26518	{ Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },	26518	{ Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },
26519	{ Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },	26519	{ Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },
26520	{ Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },	26520	{ Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },
26521	{ Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },	26521	{ Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },
26522	{ Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },	26522	{ Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },
26523	{ Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },	26523	{ Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },
26524	{ Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },	26524	{ Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },
26525	{ Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },	26525	{ Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },
26526	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },	26526	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },
26527	{ Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },	26527	{ Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },
26528	{ Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },	26528	{ Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },
26529	{ Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },	26529	{ Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },
26530	{ Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },	26530	{ Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
26531	{ Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },	26531	{ Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },
26532	{ Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },	26532	{ Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },
26533	{ Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },	26533	{ Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },
26534	{ Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },	26534	{ Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },
26535	{ Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },	26535	{ Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },
26536	{ Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },	26536	{ Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },
26537	{ Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },	26537	{ Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },
26538	{ Mips::INS, Mips::INS, Mips::INS_MM },	26538	{ Mips::INS, Mips::INS, Mips::INS_MM },
26539	{ Mips::J, Mips::J, Mips::J_MM },	26539	{ Mips::J, Mips::J, Mips::J_MM },
26540	{ Mips::JAL, Mips::JAL, Mips::JAL_MM },	26540	{ Mips::JAL, Mips::JAL, Mips::JAL_MM },
26541	{ Mips::JALX, Mips::JALX, Mips::JALX_MM },	26541	{ Mips::JALX, Mips::JALX, Mips::JALX_MM },
26542	{ Mips::JR, Mips::JR, Mips::JR_MM },	26542	{ Mips::JR, Mips::JR, Mips::JR_MM },
26543	{ Mips::LB, Mips::LB, Mips::LB_MM },	26543	{ Mips::LB, Mips::LB, Mips::LB_MM },
26544	{ Mips::LBE, Mips::LBE, Mips::LBE_MM },	26544	{ Mips::LBE, Mips::LBE, Mips::LBE_MM },
26545	{ Mips::LBu, Mips::LBu, Mips::LBu_MM },	26545	{ Mips::LBu, Mips::LBu, Mips::LBu_MM },
26546	{ Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },	26546	{ Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },
26547	{ Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },	26547	{ Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },
26548	{ Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },	26548	{ Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },
26549	{ Mips::LH, Mips::LH, Mips::LH_MM },	26549	{ Mips::LH, Mips::LH, Mips::LH_MM },
26550	{ Mips::LHE, Mips::LHE, Mips::LHE_MM },	26550	{ Mips::LHE, Mips::LHE, Mips::LHE_MM },
26551	{ Mips::LHu, Mips::LHu, Mips::LHu_MM },	26551	{ Mips::LHu, Mips::LHu, Mips::LHu_MM },
26552	{ Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },	26552	{ Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },
26553	{ Mips::LLE, Mips::LLE, Mips::LLE_MM },	26553	{ Mips::LLE, Mips::LLE, Mips::LLE_MM },
26554	{ Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },	26554	{ Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },
26555	{ Mips::LUi, Mips::LUi, Mips::LUi_MM },	26555	{ Mips::LUi, Mips::LUi, Mips::LUi_MM },
26556	{ Mips::LW, Mips::LW, Mips::LW_MM },	26556	{ Mips::LW, Mips::LW, Mips::LW_MM },
26557	{ Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },	26557	{ Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },
26558	{ Mips::LWE, Mips::LWE, Mips::LWE_MM },	26558	{ Mips::LWE, Mips::LWE, Mips::LWE_MM },
26559	{ Mips::LWL, Mips::LWL, Mips::LWL_MM },	26559	{ Mips::LWL, Mips::LWL, Mips::LWL_MM },
26560	{ Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },	26560	{ Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },
26561	{ Mips::LWR, Mips::LWR, Mips::LWR_MM },	26561	{ Mips::LWR, Mips::LWR, Mips::LWR_MM },
26562	{ Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },	26562	{ Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },
26563	{ Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },	26563	{ Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },
26564	{ Mips::LWu, Mips::LWu, Mips::LWU_MM },	26564	{ Mips::LWu, Mips::LWu, Mips::LWU_MM },
26565	{ Mips::MADD, Mips::MADD, Mips::MADD_MM },	26565	{ Mips::MADD, Mips::MADD, Mips::MADD_MM },
26566	{ Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },	26566	{ Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },
26567	{ Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },	26567	{ Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },
26568	{ Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },	26568	{ Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },
26569	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },	26569	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },
26570	{ Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },	26570	{ Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },
26571	{ Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },	26571	{ Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },
26572	{ Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },	26572	{ Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },
26573	{ Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },	26573	{ Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },
26574	{ Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },	26574	{ Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },
26575	{ Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },	26575	{ Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },
26576	{ Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },	26576	{ Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },
26577	{ Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },	26577	{ Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },
26578	{ Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },	26578	{ Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },
26579	{ Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },	26579	{ Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },
26580	{ Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },	26580	{ Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },
26581	{ Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },	26581	{ Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },
26582	{ Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },	26582	{ Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },
26583	{ Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },	26583	{ Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },
26584	{ Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },	26584	{ Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },
26585	{ Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },	26585	{ Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },
26586	{ Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },	26586	{ Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },
26587	{ Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },	26587	{ Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },
26588	{ Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },	26588	{ Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },
26589	{ Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },	26589	{ Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },
26590	{ Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },	26590	{ Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },
26591	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },	26591	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },
26592	{ Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },	26592	{ Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },
26593	{ Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },	26593	{ Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },
26594	{ Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },	26594	{ Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },
26595	{ Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },	26595	{ Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },
26596	{ Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },	26596	{ Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },
26597	{ Mips::MUL, Mips::MUL, Mips::MUL_MM },	26597	{ Mips::MUL, Mips::MUL, Mips::MUL_MM },
26598	{ Mips::MULT, Mips::MULT, Mips::MULT_MM },	26598	{ Mips::MULT, Mips::MULT, Mips::MULT_MM },
26599	{ Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },	26599	{ Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },
26600	{ Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },	26600	{ Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },
26601	{ Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },	26601	{ Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },
26602	{ Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },	26602	{ Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },
26603	{ Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },	26603	{ Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },
26604	{ Mips::NOR, Mips::NOR, Mips::NOR_MM },	26604	{ Mips::NOR, Mips::NOR, Mips::NOR_MM },
26605	{ Mips::OR, Mips::OR, Mips::OR_MM },	26605	{ Mips::OR, Mips::OR, Mips::OR_MM },
26606	{ Mips::ORi, Mips::ORi, Mips::ORi_MM },	26606	{ Mips::ORi, Mips::ORi, Mips::ORi_MM },
26607	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },	26607	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },
26608	{ Mips::PREF, Mips::PREF, Mips::PREF_MM },	26608	{ Mips::PREF, Mips::PREF, Mips::PREF_MM },
26609	{ Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },	26609	{ Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },
26610	{ Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },	26610	{ Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },
26611	{ Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },	26611	{ Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },
26612	{ Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },	26612	{ Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },
26613	{ Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },	26613	{ Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },
26614	{ Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },	26614	{ Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },
26615	{ Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },	26615	{ Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },
26616	{ Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },	26616	{ Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },
26617	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },	26617	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },
26618	{ Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },	26618	{ Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },
26619	{ Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },	26619	{ Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },
26620	{ Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },	26620	{ Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },
26621	{ Mips::SB, Mips::SB, Mips::SB_MM },	26621	{ Mips::SB, Mips::SB, Mips::SB_MM },
26622	{ Mips::SBE, Mips::SBE, Mips::SBE_MM },	26622	{ Mips::SBE, Mips::SBE, Mips::SBE_MM },
26623	{ Mips::SCE, Mips::SCE, Mips::SCE_MM },	26623	{ Mips::SCE, Mips::SCE, Mips::SCE_MM },
26624	{ Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },	26624	{ Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },
26625	{ Mips::SDC1, Mips::SDC1, (uint16_t)-1U },	26625	{ Mips::SDC1, Mips::SDC1, (uint16_t)-1U },
26626	{ Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },	26626	{ Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },
26627	{ Mips::SEB, Mips::SEB, Mips::SEB_MM },	26627	{ Mips::SEB, Mips::SEB, Mips::SEB_MM },
26628	{ Mips::SEH, Mips::SEH, Mips::SEH_MM },	26628	{ Mips::SEH, Mips::SEH, Mips::SEH_MM },
26629	{ Mips::SH, Mips::SH, Mips::SH_MM },	26629	{ Mips::SH, Mips::SH, Mips::SH_MM },
26630	{ Mips::SHE, Mips::SHE, Mips::SHE_MM },	26630	{ Mips::SHE, Mips::SHE, Mips::SHE_MM },
26631	{ Mips::SLL, Mips::SLL, Mips::SLL_MM },	26631	{ Mips::SLL, Mips::SLL, Mips::SLL_MM },
26632	{ Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },	26632	{ Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },
26633	{ Mips::SLT, Mips::SLT, Mips::SLT_MM },	26633	{ Mips::SLT, Mips::SLT, Mips::SLT_MM },
26634	{ Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },	26634	{ Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },
26635	{ Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },	26635	{ Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },
26636	{ Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },	26636	{ Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
26637	{ Mips::SRA, Mips::SRA, Mips::SRA_MM },	26637	{ Mips::SRA, Mips::SRA, Mips::SRA_MM },
26638	{ Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },	26638	{ Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },
26639	{ Mips::SRL, Mips::SRL, Mips::SRL_MM },	26639	{ Mips::SRL, Mips::SRL, Mips::SRL_MM },
26640	{ Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },	26640	{ Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },
26641	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },	26641	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },
26642	{ Mips::SUB, Mips::SUB, Mips::SUB_MM },	26642	{ Mips::SUB, Mips::SUB, Mips::SUB_MM },
26643	{ Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },	26643	{ Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },
26644	{ Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },	26644	{ Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },
26645	{ Mips::SW, Mips::SW, Mips::SW_MM },	26645	{ Mips::SW, Mips::SW, Mips::SW_MM },
26646	{ Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },	26646	{ Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },
26647	{ Mips::SWE, Mips::SWE, Mips::SWE_MM },	26647	{ Mips::SWE, Mips::SWE, Mips::SWE_MM },
26648	{ Mips::SWL, Mips::SWL, Mips::SWL_MM },	26648	{ Mips::SWL, Mips::SWL, Mips::SWL_MM },
26649	{ Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },	26649	{ Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },
26650	{ Mips::SWR, Mips::SWR, Mips::SWR_MM },	26650	{ Mips::SWR, Mips::SWR, Mips::SWR_MM },
26651	{ Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },	26651	{ Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },
26652	{ Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },	26652	{ Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },
26653	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },	26653	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },
26654	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },	26654	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },
26655	{ Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },	26655	{ Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },
26656	{ Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },	26656	{ Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },
26657	{ Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },	26657	{ Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },
26658	{ Mips::TGE, Mips::TGE, Mips::TGE_MM },	26658	{ Mips::TGE, Mips::TGE, Mips::TGE_MM },
26659	{ Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },	26659	{ Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },
26660	{ Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },	26660	{ Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },
26661	{ Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },	26661	{ Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },
26662	{ Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },	26662	{ Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },
26663	{ Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },	26663	{ Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },
26664	{ Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },	26664	{ Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },
26665	{ Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },	26665	{ Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },
26666	{ Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },	26666	{ Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },
26667	{ Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },	26667	{ Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },
26668	{ Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },	26668	{ Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },
26669	{ Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },	26669	{ Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },
26670	{ Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },	26670	{ Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },
26671	{ Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },	26671	{ Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },
26672	{ Mips::TLT, Mips::TLT, Mips::TLT_MM },	26672	{ Mips::TLT, Mips::TLT, Mips::TLT_MM },
26673	{ Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },	26673	{ Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },
26674	{ Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },	26674	{ Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },
26675	{ Mips::TNE, Mips::TNE, Mips::TNE_MM },	26675	{ Mips::TNE, Mips::TNE, Mips::TNE_MM },
26676	{ Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },	26676	{ Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },
26677	{ Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },	26677	{ Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },
26678	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },	26678	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },
26679	{ Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },	26679	{ Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },
26680	{ Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },	26680	{ Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },
26681	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },	26681	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },
26682	{ Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },	26682	{ Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },
26683	{ Mips::XOR, Mips::XOR, Mips::XOR_MM },	26683	{ Mips::XOR, Mips::XOR, Mips::XOR_MM },
26684	{ Mips::XORi, Mips::XORi, Mips::XORi_MM },	26684	{ Mips::XORi, Mips::XORi, Mips::XORi_MM },
26685	}; // End of Std2MicroMipsTable	26685	}; // End of Std2MicroMipsTable
26686		26686
26687	unsigned mid;	26687	unsigned mid;
26688	unsigned start = 0;	26688	unsigned start = 0;
26689	unsigned end = 266;	26689	unsigned end = 266;
26690	while (start < end) {	26690	while (start < end) {
26691	mid = start + (end - start) / 2;	26691	mid = start + (end - start) / 2;
26692	if (Opcode == Std2MicroMipsTable[mid][0]) {	26692	if (Opcode == Std2MicroMipsTable[mid][0]) {
26693	break;	26693	break;
26694	}	26694	}
26695	if (Opcode < Std2MicroMipsTable[mid][0])	26695	if (Opcode < Std2MicroMipsTable[mid][0])
26696	end = mid;	26696	end = mid;
26697	else	26697	else
26698	start = mid + 1;	26698	start = mid + 1;
26699	}	26699	}
26700	if (start == end)	26700	if (start == end)
26701	return -1; // Instruction doesn't exist in this table.	26701	return -1; // Instruction doesn't exist in this table.
26702		26702
26703	if (inArch == Arch_se)	26703	if (inArch == Arch_se)
26704	return Std2MicroMipsTable[mid][1];	26704	return Std2MicroMipsTable[mid][1];
26705	if (inArch == Arch_micromips)	26705	if (inArch == Arch_micromips)
26706	return Std2MicroMipsTable[mid][2];	26706	return Std2MicroMipsTable[mid][2];
26707	return -1;}	26707	return -1;}
26708		26708
26709	// Std2MicroMipsR6	26709	// Std2MicroMipsR6
26710	LLVM_READONLY	26710	LLVM_READONLY
26711	int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	26711	int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
26712	static const uint16_t Std2MicroMipsR6Table[][3] = {	26712	static const uint16_t Std2MicroMipsR6Table[][3] = {
26713	{ Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },	26713	{ Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },
26714	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },	26714	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },
26715	{ Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },	26715	{ Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },
26716	{ Mips::AND, Mips::AND, Mips::AND_MMR6 },	26716	{ Mips::AND, Mips::AND, Mips::AND_MMR6 },
26717	{ Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },	26717	{ Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },
26718	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },	26718	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },
26719	{ Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },	26719	{ Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },
26720	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },	26720	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },
26721	{ Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },	26721	{ Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },
26722	{ Mips::DI, Mips::DI, Mips::DI_MMR6 },	26722	{ Mips::DI, Mips::DI, Mips::DI_MMR6 },
26723	{ Mips::EI, Mips::EI, Mips::EI_MMR6 },	26723	{ Mips::EI, Mips::EI, Mips::EI_MMR6 },
26724	{ Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },	26724	{ Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },
26725	{ Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },	26725	{ Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },
26726	{ Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },	26726	{ Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },
26727	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },	26727	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },
26728	{ Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },	26728	{ Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },
26729	{ Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },	26729	{ Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },
26730	{ Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },	26730	{ Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },
26731	{ Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },	26731	{ Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },
26732	{ Mips::INS, Mips::INS, Mips::INS_MMR6 },	26732	{ Mips::INS, Mips::INS, Mips::INS_MMR6 },
26733	{ Mips::LDC1, Mips::LDC1, (uint16_t)-1U },	26733	{ Mips::LDC1, Mips::LDC1, (uint16_t)-1U },
26734	{ Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },	26734	{ Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },
26735	{ Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },	26735	{ Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },
26736	{ Mips::LW, Mips::LW, Mips::LW_MMR6 },	26736	{ Mips::LW, Mips::LW, Mips::LW_MMR6 },
26737	{ Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },	26737	{ Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },
26738	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },	26738	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },
26739	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },	26739	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },
26740	{ Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },	26740	{ Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },
26741	{ Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },	26741	{ Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },
26742	{ Mips::OR, Mips::OR, Mips::OR_MMR6 },	26742	{ Mips::OR, Mips::OR, Mips::OR_MMR6 },
26743	{ Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },	26743	{ Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },
26744	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },	26744	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },
26745	{ Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },	26745	{ Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },
26746	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },	26746	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },
26747	{ Mips::SB, Mips::SB, Mips::SB_MMR6 },	26747	{ Mips::SB, Mips::SB, Mips::SB_MMR6 },
26748	{ Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },	26748	{ Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },
26749	{ Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },	26749	{ Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },
26750	{ Mips::SEB, Mips::SEB, (uint16_t)-1U },	26750	{ Mips::SEB, Mips::SEB, (uint16_t)-1U },
26751	{ Mips::SEH, Mips::SEH, (uint16_t)-1U },	26751	{ Mips::SEH, Mips::SEH, (uint16_t)-1U },
26752	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },	26752	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },
26753	{ Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },	26753	{ Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },
26754	{ Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },	26754	{ Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },
26755	{ Mips::SW, Mips::SW, Mips::SW_MMR6 },	26755	{ Mips::SW, Mips::SW, Mips::SW_MMR6 },
26756	{ Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },	26756	{ Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },
26757	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },	26757	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },
26758	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },	26758	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },
26759	{ Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },	26759	{ Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },
26760	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },	26760	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },
26761	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },	26761	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },
26762	{ Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },	26762	{ Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },
26763	{ Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },	26763	{ Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },
26764	}; // End of Std2MicroMipsR6Table	26764	}; // End of Std2MicroMipsR6Table
26765		26765
26766	unsigned mid;	26766	unsigned mid;
26767	unsigned start = 0;	26767	unsigned start = 0;
26768	unsigned end = 51;	26768	unsigned end = 51;
26769	while (start < end) {	26769	while (start < end) {
26770	mid = start + (end - start) / 2;	26770	mid = start + (end - start) / 2;
26771	if (Opcode == Std2MicroMipsR6Table[mid][0]) {	26771	if (Opcode == Std2MicroMipsR6Table[mid][0]) {
26772	break;	26772	break;
26773	}	26773	}
26774	if (Opcode < Std2MicroMipsR6Table[mid][0])	26774	if (Opcode < Std2MicroMipsR6Table[mid][0])
26775	end = mid;	26775	end = mid;
26776	else	26776	else
26777	start = mid + 1;	26777	start = mid + 1;
26778	}	26778	}
26779	if (start == end)	26779	if (start == end)
26780	return -1; // Instruction doesn't exist in this table.	26780	return -1; // Instruction doesn't exist in this table.
26781		26781
26782	if (inArch == Arch_se)	26782	if (inArch == Arch_se)
26783	return Std2MicroMipsR6Table[mid][1];	26783	return Std2MicroMipsR6Table[mid][1];
26784	if (inArch == Arch_micromipsr6)	26784	if (inArch == Arch_micromipsr6)
26785	return Std2MicroMipsR6Table[mid][2];	26785	return Std2MicroMipsR6Table[mid][2];
26786	return -1;}	26786	return -1;}
26787		26787
26788	} // end namespace Mips	26788	} // end namespace Mips
26789	} // end namespace llvm	26789	} // end namespace llvm
26790	#endif // GET_INSTRMAP_INFO	26790	#endif // GET_INSTRMAP_INFO
26791		26791
26792		26792

Side By Side Comparison

Line Number	../DebugInfoTest/example_mips_dbg.ll	Hit count	Line Number	../DebugInfoTest/example_mips.ll	Hit count
1	/===- TableGen'erated file -------------------------------------- C++ --===\	---	1	/===- TableGen'erated file -------------------------------------- C++ --===\	---
2	\|* *\|	---	2	\|* *\|	---
3	\|* Target Instruction Enum Values and Descriptors *\|	---	3	\|* Target Instruction Enum Values and Descriptors *\|	---
4	\|* *\|	---	4	\|* *\|	---
5	\|* Automatically generated file, do not edit! *\|	---	5	\|* Automatically generated file, do not edit! *\|	---
6	\|* *\|	---	6	\|* *\|	---
7	\===----------------------------------------------------------------------===/	---	7	\===----------------------------------------------------------------------===/	---
8		---	8		---
9	#ifdef GET_INSTRINFO_ENUM	---	9	#ifdef GET_INSTRINFO_ENUM	---
10	#undef GET_INSTRINFO_ENUM	---	10	#undef GET_INSTRINFO_ENUM	---
11	namespace llvm {	---	11	namespace llvm {	---
12		---	12		---
13	namespace Mips {	---	13	namespace Mips {	---
14	enum {	---	14	enum {	---
15	PHI = 0,	---	15	PHI = 0,	---
16	INLINEASM = 1,	---	16	INLINEASM = 1,	---
17	INLINEASM_BR = 2,	---	17	INLINEASM_BR = 2,	---
18	CFI_INSTRUCTION = 3,	---	18	CFI_INSTRUCTION = 3,	---
19	EH_LABEL = 4,	---	19	EH_LABEL = 4,	---
20	GC_LABEL = 5,	---	20	GC_LABEL = 5,	---
21	ANNOTATION_LABEL = 6,	---	21	ANNOTATION_LABEL = 6,	---
22	KILL = 7,	---	22	KILL = 7,	---
23	EXTRACT_SUBREG = 8,	---	23	EXTRACT_SUBREG = 8,	---
24	INSERT_SUBREG = 9,	---	24	INSERT_SUBREG = 9,	---
25	IMPLICIT_DEF = 10,	---	25	IMPLICIT_DEF = 10,	---
26	SUBREG_TO_REG = 11,	---	26	SUBREG_TO_REG = 11,	---
27	COPY_TO_REGCLASS = 12,	---	27	COPY_TO_REGCLASS = 12,	---
28	DBG_VALUE = 13,	---	28	DBG_VALUE = 13,	---
29	DBG_VALUE_LIST = 14,	---	29	DBG_VALUE_LIST = 14,	---
30	DBG_INSTR_REF = 15,	---	30	DBG_INSTR_REF = 15,	---
31	DBG_PHI = 16,	---	31	DBG_PHI = 16,	---
32	DBG_LABEL = 17,	---	32	DBG_LABEL = 17,	---
33	REG_SEQUENCE = 18,	---	33	REG_SEQUENCE = 18,	---
34	COPY = 19,	---	34	COPY = 19,	---
35	BUNDLE = 20,	---	35	BUNDLE = 20,	---
36	LIFETIME_START = 21,	---	36	LIFETIME_START = 21,	---
37	LIFETIME_END = 22,	---	37	LIFETIME_END = 22,	---
38	PSEUDO_PROBE = 23,	---	38	PSEUDO_PROBE = 23,	---
39	ARITH_FENCE = 24,	---	39	ARITH_FENCE = 24,	---
40	STACKMAP = 25,	---	40	STACKMAP = 25,	---
41	FENTRY_CALL = 26,	---	41	FENTRY_CALL = 26,	---
42	PATCHPOINT = 27,	---	42	PATCHPOINT = 27,	---
43	LOAD_STACK_GUARD = 28,	---	43	LOAD_STACK_GUARD = 28,	---
44	PREALLOCATED_SETUP = 29,	---	44	PREALLOCATED_SETUP = 29,	---
45	PREALLOCATED_ARG = 30,	---	45	PREALLOCATED_ARG = 30,	---
46	STATEPOINT = 31,	---	46	STATEPOINT = 31,	---
47	LOCAL_ESCAPE = 32,	---	47	LOCAL_ESCAPE = 32,	---
48	FAULTING_OP = 33,	---	48	FAULTING_OP = 33,	---
49	PATCHABLE_OP = 34,	---	49	PATCHABLE_OP = 34,	---
50	PATCHABLE_FUNCTION_ENTER = 35,	---	50	PATCHABLE_FUNCTION_ENTER = 35,	---
51	PATCHABLE_RET = 36,	---	51	PATCHABLE_RET = 36,	---
52	PATCHABLE_FUNCTION_EXIT = 37,	---	52	PATCHABLE_FUNCTION_EXIT = 37,	---
53	PATCHABLE_TAIL_CALL = 38,	---	53	PATCHABLE_TAIL_CALL = 38,	---
54	PATCHABLE_EVENT_CALL = 39,	---	54	PATCHABLE_EVENT_CALL = 39,	---
55	PATCHABLE_TYPED_EVENT_CALL = 40,	---	55	PATCHABLE_TYPED_EVENT_CALL = 40,	---
56	ICALL_BRANCH_FUNNEL = 41,	---	56	ICALL_BRANCH_FUNNEL = 41,	---
57	MEMBARRIER = 42,	---	57	MEMBARRIER = 42,	---
58	G_ASSERT_SEXT = 43,	---	58	G_ASSERT_SEXT = 43,	---
59	G_ASSERT_ZEXT = 44,	---	59	G_ASSERT_ZEXT = 44,	---
60	G_ASSERT_ALIGN = 45,	---	60	G_ASSERT_ALIGN = 45,	---
61	G_ADD = 46,	---	61	G_ADD = 46,	---
62	G_SUB = 47,	---	62	G_SUB = 47,	---
63	G_MUL = 48,	---	63	G_MUL = 48,	---
64	G_SDIV = 49,	---	64	G_SDIV = 49,	---
65	G_UDIV = 50,	---	65	G_UDIV = 50,	---
66	G_SREM = 51,	---	66	G_SREM = 51,	---
67	G_UREM = 52,	---	67	G_UREM = 52,	---
68	G_SDIVREM = 53,	---	68	G_SDIVREM = 53,	---
69	G_UDIVREM = 54,	---	69	G_UDIVREM = 54,	---
70	G_AND = 55,	---	70	G_AND = 55,	---
71	G_OR = 56,	---	71	G_OR = 56,	---
72	G_XOR = 57,	---	72	G_XOR = 57,	---
73	G_IMPLICIT_DEF = 58,	---	73	G_IMPLICIT_DEF = 58,	---
74	G_PHI = 59,	---	74	G_PHI = 59,	---
75	G_FRAME_INDEX = 60,	---	75	G_FRAME_INDEX = 60,	---
76	G_GLOBAL_VALUE = 61,	---	76	G_GLOBAL_VALUE = 61,	---
77	G_CONSTANT_POOL = 62,	---	77	G_CONSTANT_POOL = 62,	---
78	G_EXTRACT = 63,	---	78	G_EXTRACT = 63,	---
79	G_UNMERGE_VALUES = 64,	---	79	G_UNMERGE_VALUES = 64,	---
80	G_INSERT = 65,	---	80	G_INSERT = 65,	---
81	G_MERGE_VALUES = 66,	---	81	G_MERGE_VALUES = 66,	---
82	G_BUILD_VECTOR = 67,	---	82	G_BUILD_VECTOR = 67,	---
83	G_BUILD_VECTOR_TRUNC = 68,	---	83	G_BUILD_VECTOR_TRUNC = 68,	---
84	G_CONCAT_VECTORS = 69,	---	84	G_CONCAT_VECTORS = 69,	---
85	G_PTRTOINT = 70,	---	85	G_PTRTOINT = 70,	---
86	G_INTTOPTR = 71,	---	86	G_INTTOPTR = 71,	---
87	G_BITCAST = 72,	---	87	G_BITCAST = 72,	---
88	G_FREEZE = 73,	---	88	G_FREEZE = 73,	---
89	G_CONSTANT_FOLD_BARRIER = 74,	---	89	G_CONSTANT_FOLD_BARRIER = 74,	---
90	G_INTRINSIC_FPTRUNC_ROUND = 75,	---	90	G_INTRINSIC_FPTRUNC_ROUND = 75,	---
91	G_INTRINSIC_TRUNC = 76,	---	91	G_INTRINSIC_TRUNC = 76,	---
92	G_INTRINSIC_ROUND = 77,	---	92	G_INTRINSIC_ROUND = 77,	---
93	G_INTRINSIC_LRINT = 78,	---	93	G_INTRINSIC_LRINT = 78,	---
94	G_INTRINSIC_ROUNDEVEN = 79,	---	94	G_INTRINSIC_ROUNDEVEN = 79,	---
95	G_READCYCLECOUNTER = 80,	---	95	G_READCYCLECOUNTER = 80,	---
96	G_LOAD = 81,	---	96	G_LOAD = 81,	---
97	G_SEXTLOAD = 82,	---	97	G_SEXTLOAD = 82,	---
98	G_ZEXTLOAD = 83,	---	98	G_ZEXTLOAD = 83,	---
99	G_INDEXED_LOAD = 84,	---	99	G_INDEXED_LOAD = 84,	---
100	G_INDEXED_SEXTLOAD = 85,	---	100	G_INDEXED_SEXTLOAD = 85,	---
101	G_INDEXED_ZEXTLOAD = 86,	---	101	G_INDEXED_ZEXTLOAD = 86,	---
102	G_STORE = 87,	---	102	G_STORE = 87,	---
103	G_INDEXED_STORE = 88,	---	103	G_INDEXED_STORE = 88,	---
104	G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89,	---	104	G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89,	---
105	G_ATOMIC_CMPXCHG = 90,	---	105	G_ATOMIC_CMPXCHG = 90,	---
106	G_ATOMICRMW_XCHG = 91,	---	106	G_ATOMICRMW_XCHG = 91,	---
107	G_ATOMICRMW_ADD = 92,	---	107	G_ATOMICRMW_ADD = 92,	---
108	G_ATOMICRMW_SUB = 93,	---	108	G_ATOMICRMW_SUB = 93,	---
109	G_ATOMICRMW_AND = 94,	---	109	G_ATOMICRMW_AND = 94,	---
110	G_ATOMICRMW_NAND = 95,	---	110	G_ATOMICRMW_NAND = 95,	---
111	G_ATOMICRMW_OR = 96,	---	111	G_ATOMICRMW_OR = 96,	---
112	G_ATOMICRMW_XOR = 97,	---	112	G_ATOMICRMW_XOR = 97,	---
113	G_ATOMICRMW_MAX = 98,	---	113	G_ATOMICRMW_MAX = 98,	---
114	G_ATOMICRMW_MIN = 99,	---	114	G_ATOMICRMW_MIN = 99,	---
115	G_ATOMICRMW_UMAX = 100,	---	115	G_ATOMICRMW_UMAX = 100,	---
116	G_ATOMICRMW_UMIN = 101,	---	116	G_ATOMICRMW_UMIN = 101,	---
117	G_ATOMICRMW_FADD = 102,	---	117	G_ATOMICRMW_FADD = 102,	---
118	G_ATOMICRMW_FSUB = 103,	---	118	G_ATOMICRMW_FSUB = 103,	---
119	G_ATOMICRMW_FMAX = 104,	---	119	G_ATOMICRMW_FMAX = 104,	---
120	G_ATOMICRMW_FMIN = 105,	---	120	G_ATOMICRMW_FMIN = 105,	---
121	G_ATOMICRMW_UINC_WRAP = 106,	---	121	G_ATOMICRMW_UINC_WRAP = 106,	---
122	G_ATOMICRMW_UDEC_WRAP = 107,	---	122	G_ATOMICRMW_UDEC_WRAP = 107,	---
123	G_FENCE = 108,	---	123	G_FENCE = 108,	---
124	G_BRCOND = 109,	---	124	G_BRCOND = 109,	---
125	G_BRINDIRECT = 110,	---	125	G_BRINDIRECT = 110,	---
126	G_INVOKE_REGION_START = 111,	---	126	G_INVOKE_REGION_START = 111,	---
127	G_INTRINSIC = 112,	---	127	G_INTRINSIC = 112,	---
128	G_INTRINSIC_W_SIDE_EFFECTS = 113,	---	128	G_INTRINSIC_W_SIDE_EFFECTS = 113,	---
129	G_ANYEXT = 114,	---	129	G_ANYEXT = 114,	---
130	G_TRUNC = 115,	---	130	G_TRUNC = 115,	---
131	G_CONSTANT = 116,	---	131	G_CONSTANT = 116,	---
132	G_FCONSTANT = 117,	---	132	G_FCONSTANT = 117,	---
133	G_VASTART = 118,	---	133	G_VASTART = 118,	---
134	G_VAARG = 119,	---	134	G_VAARG = 119,	---
135	G_SEXT = 120,	---	135	G_SEXT = 120,	---
136	G_SEXT_INREG = 121,	---	136	G_SEXT_INREG = 121,	---
137	G_ZEXT = 122,	---	137	G_ZEXT = 122,	---
138	G_SHL = 123,	---	138	G_SHL = 123,	---
139	G_LSHR = 124,	---	139	G_LSHR = 124,	---
140	G_ASHR = 125,	---	140	G_ASHR = 125,	---
141	G_FSHL = 126,	---	141	G_FSHL = 126,	---
142	G_FSHR = 127,	---	142	G_FSHR = 127,	---
143	G_ROTR = 128,	---	143	G_ROTR = 128,	---
144	G_ROTL = 129,	---	144	G_ROTL = 129,	---
145	G_ICMP = 130,	---	145	G_ICMP = 130,	---
146	G_FCMP = 131,	---	146	G_FCMP = 131,	---
147	G_SELECT = 132,	---	147	G_SELECT = 132,	---
148	G_UADDO = 133,	---	148	G_UADDO = 133,	---
149	G_UADDE = 134,	---	149	G_UADDE = 134,	---
150	G_USUBO = 135,	---	150	G_USUBO = 135,	---
151	G_USUBE = 136,	---	151	G_USUBE = 136,	---
152	G_SADDO = 137,	---	152	G_SADDO = 137,	---
153	G_SADDE = 138,	---	153	G_SADDE = 138,	---
154	G_SSUBO = 139,	---	154	G_SSUBO = 139,	---
155	G_SSUBE = 140,	---	155	G_SSUBE = 140,	---
156	G_UMULO = 141,	---	156	G_UMULO = 141,	---
157	G_SMULO = 142,	---	157	G_SMULO = 142,	---
158	G_UMULH = 143,	---	158	G_UMULH = 143,	---
159	G_SMULH = 144,	---	159	G_SMULH = 144,	---
160	G_UADDSAT = 145,	---	160	G_UADDSAT = 145,	---
161	G_SADDSAT = 146,	---	161	G_SADDSAT = 146,	---
162	G_USUBSAT = 147,	---	162	G_USUBSAT = 147,	---
163	G_SSUBSAT = 148,	---	163	G_SSUBSAT = 148,	---
164	G_USHLSAT = 149,	---	164	G_USHLSAT = 149,	---
165	G_SSHLSAT = 150,	---	165	G_SSHLSAT = 150,	---
166	G_SMULFIX = 151,	---	166	G_SMULFIX = 151,	---
167	G_UMULFIX = 152,	---	167	G_UMULFIX = 152,	---
168	G_SMULFIXSAT = 153,	---	168	G_SMULFIXSAT = 153,	---
169	G_UMULFIXSAT = 154,	---	169	G_UMULFIXSAT = 154,	---
170	G_SDIVFIX = 155,	---	170	G_SDIVFIX = 155,	---
171	G_UDIVFIX = 156,	---	171	G_UDIVFIX = 156,	---
172	G_SDIVFIXSAT = 157,	---	172	G_SDIVFIXSAT = 157,	---
173	G_UDIVFIXSAT = 158,	---	173	G_UDIVFIXSAT = 158,	---
174	G_FADD = 159,	---	174	G_FADD = 159,	---
175	G_FSUB = 160,	---	175	G_FSUB = 160,	---
176	G_FMUL = 161,	---	176	G_FMUL = 161,	---
177	G_FMA = 162,	---	177	G_FMA = 162,	---
178	G_FMAD = 163,	---	178	G_FMAD = 163,	---
179	G_FDIV = 164,	---	179	G_FDIV = 164,	---
180	G_FREM = 165,	---	180	G_FREM = 165,	---
181	G_FPOW = 166,	---	181	G_FPOW = 166,	---
182	G_FPOWI = 167,	---	182	G_FPOWI = 167,	---
183	G_FEXP = 168,	---	183	G_FEXP = 168,	---
184	G_FEXP2 = 169,	---	184	G_FEXP2 = 169,	---
185	G_FLOG = 170,	---	185	G_FLOG = 170,	---
186	G_FLOG2 = 171,	---	186	G_FLOG2 = 171,	---
187	G_FLOG10 = 172,	---	187	G_FLOG10 = 172,	---
188	G_FLDEXP = 173,	---	188	G_FLDEXP = 173,	---
189	G_FFREXP = 174,	---	189	G_FFREXP = 174,	---
190	G_FNEG = 175,	---	190	G_FNEG = 175,	---
191	G_FPEXT = 176,	---	191	G_FPEXT = 176,	---
192	G_FPTRUNC = 177,	---	192	G_FPTRUNC = 177,	---
193	G_FPTOSI = 178,	---	193	G_FPTOSI = 178,	---
194	G_FPTOUI = 179,	---	194	G_FPTOUI = 179,	---
195	G_SITOFP = 180,	---	195	G_SITOFP = 180,	---
196	G_UITOFP = 181,	---	196	G_UITOFP = 181,	---
197	G_FABS = 182,	---	197	G_FABS = 182,	---
198	G_FCOPYSIGN = 183,	---	198	G_FCOPYSIGN = 183,	---
199	G_IS_FPCLASS = 184,	---	199	G_IS_FPCLASS = 184,	---
200	G_FCANONICALIZE = 185,	---	200	G_FCANONICALIZE = 185,	---
201	G_FMINNUM = 186,	---	201	G_FMINNUM = 186,	---
202	G_FMAXNUM = 187,	---	202	G_FMAXNUM = 187,	---
203	G_FMINNUM_IEEE = 188,	---	203	G_FMINNUM_IEEE = 188,	---
204	G_FMAXNUM_IEEE = 189,	---	204	G_FMAXNUM_IEEE = 189,	---
205	G_FMINIMUM = 190,	---	205	G_FMINIMUM = 190,	---
206	G_FMAXIMUM = 191,	---	206	G_FMAXIMUM = 191,	---
207	G_PTR_ADD = 192,	---	207	G_PTR_ADD = 192,	---
208	G_PTRMASK = 193,	---	208	G_PTRMASK = 193,	---
209	G_SMIN = 194,	---	209	G_SMIN = 194,	---
210	G_SMAX = 195,	---	210	G_SMAX = 195,	---
211	G_UMIN = 196,	---	211	G_UMIN = 196,	---
212	G_UMAX = 197,	---	212	G_UMAX = 197,	---
213	G_ABS = 198,	---	213	G_ABS = 198,	---
214	G_LROUND = 199,	---	214	G_LROUND = 199,	---
215	G_LLROUND = 200,	---	215	G_LLROUND = 200,	---
216	G_BR = 201,	---	216	G_BR = 201,	---
217	G_BRJT = 202,	---	217	G_BRJT = 202,	---
218	G_INSERT_VECTOR_ELT = 203,	---	218	G_INSERT_VECTOR_ELT = 203,	---
219	G_EXTRACT_VECTOR_ELT = 204,	---	219	G_EXTRACT_VECTOR_ELT = 204,	---
220	G_SHUFFLE_VECTOR = 205,	---	220	G_SHUFFLE_VECTOR = 205,	---
221	G_CTTZ = 206,	---	221	G_CTTZ = 206,	---
222	G_CTTZ_ZERO_UNDEF = 207,	---	222	G_CTTZ_ZERO_UNDEF = 207,	---
223	G_CTLZ = 208,	---	223	G_CTLZ = 208,	---
224	G_CTLZ_ZERO_UNDEF = 209,	---	224	G_CTLZ_ZERO_UNDEF = 209,	---
225	G_CTPOP = 210,	---	225	G_CTPOP = 210,	---
226	G_BSWAP = 211,	---	226	G_BSWAP = 211,	---
227	G_BITREVERSE = 212,	---	227	G_BITREVERSE = 212,	---
228	G_FCEIL = 213,	---	228	G_FCEIL = 213,	---
229	G_FCOS = 214,	---	229	G_FCOS = 214,	---
230	G_FSIN = 215,	---	230	G_FSIN = 215,	---
231	G_FSQRT = 216,	---	231	G_FSQRT = 216,	---
232	G_FFLOOR = 217,	---	232	G_FFLOOR = 217,	---
233	G_FRINT = 218,	---	233	G_FRINT = 218,	---
234	G_FNEARBYINT = 219,	---	234	G_FNEARBYINT = 219,	---
235	G_ADDRSPACE_CAST = 220,	---	235	G_ADDRSPACE_CAST = 220,	---
236	G_BLOCK_ADDR = 221,	---	236	G_BLOCK_ADDR = 221,	---
237	G_JUMP_TABLE = 222,	---	237	G_JUMP_TABLE = 222,	---
238	G_DYN_STACKALLOC = 223,	---	238	G_DYN_STACKALLOC = 223,	---
239	G_STRICT_FADD = 224,	---	239	G_STRICT_FADD = 224,	---
240	G_STRICT_FSUB = 225,	---	240	G_STRICT_FSUB = 225,	---
241	G_STRICT_FMUL = 226,	---	241	G_STRICT_FMUL = 226,	---
242	G_STRICT_FDIV = 227,	---	242	G_STRICT_FDIV = 227,	---
243	G_STRICT_FREM = 228,	---	243	G_STRICT_FREM = 228,	---
244	G_STRICT_FMA = 229,	---	244	G_STRICT_FMA = 229,	---
245	G_STRICT_FSQRT = 230,	---	245	G_STRICT_FSQRT = 230,	---
246	G_STRICT_FLDEXP = 231,	---	246	G_STRICT_FLDEXP = 231,	---
247	G_READ_REGISTER = 232,	---	247	G_READ_REGISTER = 232,	---
248	G_WRITE_REGISTER = 233,	---	248	G_WRITE_REGISTER = 233,	---
249	G_MEMCPY = 234,	---	249	G_MEMCPY = 234,	---
250	G_MEMCPY_INLINE = 235,	---	250	G_MEMCPY_INLINE = 235,	---
251	G_MEMMOVE = 236,	---	251	G_MEMMOVE = 236,	---
252	G_MEMSET = 237,	---	252	G_MEMSET = 237,	---
253	G_BZERO = 238,	---	253	G_BZERO = 238,	---
254	G_VECREDUCE_SEQ_FADD = 239,	---	254	G_VECREDUCE_SEQ_FADD = 239,	---
255	G_VECREDUCE_SEQ_FMUL = 240,	---	255	G_VECREDUCE_SEQ_FMUL = 240,	---
256	G_VECREDUCE_FADD = 241,	---	256	G_VECREDUCE_FADD = 241,	---
257	G_VECREDUCE_FMUL = 242,	---	257	G_VECREDUCE_FMUL = 242,	---
258	G_VECREDUCE_FMAX = 243,	---	258	G_VECREDUCE_FMAX = 243,	---
259	G_VECREDUCE_FMIN = 244,	---	259	G_VECREDUCE_FMIN = 244,	---
260	G_VECREDUCE_ADD = 245,	---	260	G_VECREDUCE_ADD = 245,	---
261	G_VECREDUCE_MUL = 246,	---	261	G_VECREDUCE_MUL = 246,	---
262	G_VECREDUCE_AND = 247,	---	262	G_VECREDUCE_AND = 247,	---
263	G_VECREDUCE_OR = 248,	---	263	G_VECREDUCE_OR = 248,	---
264	G_VECREDUCE_XOR = 249,	---	264	G_VECREDUCE_XOR = 249,	---
265	G_VECREDUCE_SMAX = 250,	---	265	G_VECREDUCE_SMAX = 250,	---
266	G_VECREDUCE_SMIN = 251,	---	266	G_VECREDUCE_SMIN = 251,	---
267	G_VECREDUCE_UMAX = 252,	---	267	G_VECREDUCE_UMAX = 252,	---
268	G_VECREDUCE_UMIN = 253,	---	268	G_VECREDUCE_UMIN = 253,	---
269	G_SBFX = 254,	---	269	G_SBFX = 254,	---
270	G_UBFX = 255,	---	270	G_UBFX = 255,	---
271	ABSMacro = 256,	---	271	ABSMacro = 256,	---
272	ADJCALLSTACKDOWN = 257,	---	272	ADJCALLSTACKDOWN = 257,	---
273	ADJCALLSTACKUP = 258,	---	273	ADJCALLSTACKUP = 258,	---
274	AND_V_D_PSEUDO = 259,	---	274	AND_V_D_PSEUDO = 259,	---
275	AND_V_H_PSEUDO = 260,	---	275	AND_V_H_PSEUDO = 260,	---
276	AND_V_W_PSEUDO = 261,	---	276	AND_V_W_PSEUDO = 261,	---
277	ATOMIC_CMP_SWAP_I16 = 262,	---	277	ATOMIC_CMP_SWAP_I16 = 262,	---
278	ATOMIC_CMP_SWAP_I16_POSTRA = 263,	---	278	ATOMIC_CMP_SWAP_I16_POSTRA = 263,	---
279	ATOMIC_CMP_SWAP_I32 = 264,	---	279	ATOMIC_CMP_SWAP_I32 = 264,	---
280	ATOMIC_CMP_SWAP_I32_POSTRA = 265,	---	280	ATOMIC_CMP_SWAP_I32_POSTRA = 265,	---
281	ATOMIC_CMP_SWAP_I64 = 266,	---	281	ATOMIC_CMP_SWAP_I64 = 266,	---
282	ATOMIC_CMP_SWAP_I64_POSTRA = 267,	---	282	ATOMIC_CMP_SWAP_I64_POSTRA = 267,	---
283	ATOMIC_CMP_SWAP_I8 = 268,	---	283	ATOMIC_CMP_SWAP_I8 = 268,	---
284	ATOMIC_CMP_SWAP_I8_POSTRA = 269,	---	284	ATOMIC_CMP_SWAP_I8_POSTRA = 269,	---
285	ATOMIC_LOAD_ADD_I16 = 270,	---	285	ATOMIC_LOAD_ADD_I16 = 270,	---
286	ATOMIC_LOAD_ADD_I16_POSTRA = 271,	---	286	ATOMIC_LOAD_ADD_I16_POSTRA = 271,	---
287	ATOMIC_LOAD_ADD_I32 = 272,	---	287	ATOMIC_LOAD_ADD_I32 = 272,	---
288	ATOMIC_LOAD_ADD_I32_POSTRA = 273,	---	288	ATOMIC_LOAD_ADD_I32_POSTRA = 273,	---
289	ATOMIC_LOAD_ADD_I64 = 274,	---	289	ATOMIC_LOAD_ADD_I64 = 274,	---
290	ATOMIC_LOAD_ADD_I64_POSTRA = 275,	---	290	ATOMIC_LOAD_ADD_I64_POSTRA = 275,	---
291	ATOMIC_LOAD_ADD_I8 = 276,	---	291	ATOMIC_LOAD_ADD_I8 = 276,	---
292	ATOMIC_LOAD_ADD_I8_POSTRA = 277,	---	292	ATOMIC_LOAD_ADD_I8_POSTRA = 277,	---
293	ATOMIC_LOAD_AND_I16 = 278,	---	293	ATOMIC_LOAD_AND_I16 = 278,	---
294	ATOMIC_LOAD_AND_I16_POSTRA = 279,	---	294	ATOMIC_LOAD_AND_I16_POSTRA = 279,	---
295	ATOMIC_LOAD_AND_I32 = 280,	---	295	ATOMIC_LOAD_AND_I32 = 280,	---
296	ATOMIC_LOAD_AND_I32_POSTRA = 281,	---	296	ATOMIC_LOAD_AND_I32_POSTRA = 281,	---
297	ATOMIC_LOAD_AND_I64 = 282,	---	297	ATOMIC_LOAD_AND_I64 = 282,	---
298	ATOMIC_LOAD_AND_I64_POSTRA = 283,	---	298	ATOMIC_LOAD_AND_I64_POSTRA = 283,	---
299	ATOMIC_LOAD_AND_I8 = 284,	---	299	ATOMIC_LOAD_AND_I8 = 284,	---
300	ATOMIC_LOAD_AND_I8_POSTRA = 285,	---	300	ATOMIC_LOAD_AND_I8_POSTRA = 285,	---
301	ATOMIC_LOAD_MAX_I16 = 286,	---	301	ATOMIC_LOAD_MAX_I16 = 286,	---
302	ATOMIC_LOAD_MAX_I16_POSTRA = 287,	---	302	ATOMIC_LOAD_MAX_I16_POSTRA = 287,	---
303	ATOMIC_LOAD_MAX_I32 = 288,	---	303	ATOMIC_LOAD_MAX_I32 = 288,	---
304	ATOMIC_LOAD_MAX_I32_POSTRA = 289,	---	304	ATOMIC_LOAD_MAX_I32_POSTRA = 289,	---
305	ATOMIC_LOAD_MAX_I64 = 290,	---	305	ATOMIC_LOAD_MAX_I64 = 290,	---
306	ATOMIC_LOAD_MAX_I64_POSTRA = 291,	---	306	ATOMIC_LOAD_MAX_I64_POSTRA = 291,	---
307	ATOMIC_LOAD_MAX_I8 = 292,	---	307	ATOMIC_LOAD_MAX_I8 = 292,	---
308	ATOMIC_LOAD_MAX_I8_POSTRA = 293,	---	308	ATOMIC_LOAD_MAX_I8_POSTRA = 293,	---
309	ATOMIC_LOAD_MIN_I16 = 294,	---	309	ATOMIC_LOAD_MIN_I16 = 294,	---
310	ATOMIC_LOAD_MIN_I16_POSTRA = 295,	---	310	ATOMIC_LOAD_MIN_I16_POSTRA = 295,	---
311	ATOMIC_LOAD_MIN_I32 = 296,	---	311	ATOMIC_LOAD_MIN_I32 = 296,	---
312	ATOMIC_LOAD_MIN_I32_POSTRA = 297,	---	312	ATOMIC_LOAD_MIN_I32_POSTRA = 297,	---
313	ATOMIC_LOAD_MIN_I64 = 298,	---	313	ATOMIC_LOAD_MIN_I64 = 298,	---
314	ATOMIC_LOAD_MIN_I64_POSTRA = 299,	---	314	ATOMIC_LOAD_MIN_I64_POSTRA = 299,	---
315	ATOMIC_LOAD_MIN_I8 = 300,	---	315	ATOMIC_LOAD_MIN_I8 = 300,	---
316	ATOMIC_LOAD_MIN_I8_POSTRA = 301,	---	316	ATOMIC_LOAD_MIN_I8_POSTRA = 301,	---
317	ATOMIC_LOAD_NAND_I16 = 302,	---	317	ATOMIC_LOAD_NAND_I16 = 302,	---
318	ATOMIC_LOAD_NAND_I16_POSTRA = 303,	---	318	ATOMIC_LOAD_NAND_I16_POSTRA = 303,	---
319	ATOMIC_LOAD_NAND_I32 = 304,	---	319	ATOMIC_LOAD_NAND_I32 = 304,	---
320	ATOMIC_LOAD_NAND_I32_POSTRA = 305,	---	320	ATOMIC_LOAD_NAND_I32_POSTRA = 305,	---
321	ATOMIC_LOAD_NAND_I64 = 306,	---	321	ATOMIC_LOAD_NAND_I64 = 306,	---
322	ATOMIC_LOAD_NAND_I64_POSTRA = 307,	---	322	ATOMIC_LOAD_NAND_I64_POSTRA = 307,	---
323	ATOMIC_LOAD_NAND_I8 = 308,	---	323	ATOMIC_LOAD_NAND_I8 = 308,	---
324	ATOMIC_LOAD_NAND_I8_POSTRA = 309,	---	324	ATOMIC_LOAD_NAND_I8_POSTRA = 309,	---
325	ATOMIC_LOAD_OR_I16 = 310,	---	325	ATOMIC_LOAD_OR_I16 = 310,	---
326	ATOMIC_LOAD_OR_I16_POSTRA = 311,	---	326	ATOMIC_LOAD_OR_I16_POSTRA = 311,	---
327	ATOMIC_LOAD_OR_I32 = 312,	---	327	ATOMIC_LOAD_OR_I32 = 312,	---
328	ATOMIC_LOAD_OR_I32_POSTRA = 313,	---	328	ATOMIC_LOAD_OR_I32_POSTRA = 313,	---
329	ATOMIC_LOAD_OR_I64 = 314,	---	329	ATOMIC_LOAD_OR_I64 = 314,	---
330	ATOMIC_LOAD_OR_I64_POSTRA = 315,	---	330	ATOMIC_LOAD_OR_I64_POSTRA = 315,	---
331	ATOMIC_LOAD_OR_I8 = 316,	---	331	ATOMIC_LOAD_OR_I8 = 316,	---
332	ATOMIC_LOAD_OR_I8_POSTRA = 317,	---	332	ATOMIC_LOAD_OR_I8_POSTRA = 317,	---
333	ATOMIC_LOAD_SUB_I16 = 318,	---	333	ATOMIC_LOAD_SUB_I16 = 318,	---
334	ATOMIC_LOAD_SUB_I16_POSTRA = 319,	---	334	ATOMIC_LOAD_SUB_I16_POSTRA = 319,	---
335	ATOMIC_LOAD_SUB_I32 = 320,	---	335	ATOMIC_LOAD_SUB_I32 = 320,	---
336	ATOMIC_LOAD_SUB_I32_POSTRA = 321,	---	336	ATOMIC_LOAD_SUB_I32_POSTRA = 321,	---
337	ATOMIC_LOAD_SUB_I64 = 322,	---	337	ATOMIC_LOAD_SUB_I64 = 322,	---
338	ATOMIC_LOAD_SUB_I64_POSTRA = 323,	---	338	ATOMIC_LOAD_SUB_I64_POSTRA = 323,	---
339	ATOMIC_LOAD_SUB_I8 = 324,	---	339	ATOMIC_LOAD_SUB_I8 = 324,	---
340	ATOMIC_LOAD_SUB_I8_POSTRA = 325,	---	340	ATOMIC_LOAD_SUB_I8_POSTRA = 325,	---
341	ATOMIC_LOAD_UMAX_I16 = 326,	---	341	ATOMIC_LOAD_UMAX_I16 = 326,	---
342	ATOMIC_LOAD_UMAX_I16_POSTRA = 327,	---	342	ATOMIC_LOAD_UMAX_I16_POSTRA = 327,	---
343	ATOMIC_LOAD_UMAX_I32 = 328,	---	343	ATOMIC_LOAD_UMAX_I32 = 328,	---
344	ATOMIC_LOAD_UMAX_I32_POSTRA = 329,	---	344	ATOMIC_LOAD_UMAX_I32_POSTRA = 329,	---
345	ATOMIC_LOAD_UMAX_I64 = 330,	---	345	ATOMIC_LOAD_UMAX_I64 = 330,	---
346	ATOMIC_LOAD_UMAX_I64_POSTRA = 331,	---	346	ATOMIC_LOAD_UMAX_I64_POSTRA = 331,	---
347	ATOMIC_LOAD_UMAX_I8 = 332,	---	347	ATOMIC_LOAD_UMAX_I8 = 332,	---
348	ATOMIC_LOAD_UMAX_I8_POSTRA = 333,	---	348	ATOMIC_LOAD_UMAX_I8_POSTRA = 333,	---
349	ATOMIC_LOAD_UMIN_I16 = 334,	---	349	ATOMIC_LOAD_UMIN_I16 = 334,	---
350	ATOMIC_LOAD_UMIN_I16_POSTRA = 335,	---	350	ATOMIC_LOAD_UMIN_I16_POSTRA = 335,	---
351	ATOMIC_LOAD_UMIN_I32 = 336,	---	351	ATOMIC_LOAD_UMIN_I32 = 336,	---
352	ATOMIC_LOAD_UMIN_I32_POSTRA = 337,	---	352	ATOMIC_LOAD_UMIN_I32_POSTRA = 337,	---
353	ATOMIC_LOAD_UMIN_I64 = 338,	---	353	ATOMIC_LOAD_UMIN_I64 = 338,	---
354	ATOMIC_LOAD_UMIN_I64_POSTRA = 339,	---	354	ATOMIC_LOAD_UMIN_I64_POSTRA = 339,	---
355	ATOMIC_LOAD_UMIN_I8 = 340,	---	355	ATOMIC_LOAD_UMIN_I8 = 340,	---
356	ATOMIC_LOAD_UMIN_I8_POSTRA = 341,	---	356	ATOMIC_LOAD_UMIN_I8_POSTRA = 341,	---
357	ATOMIC_LOAD_XOR_I16 = 342,	---	357	ATOMIC_LOAD_XOR_I16 = 342,	---
358	ATOMIC_LOAD_XOR_I16_POSTRA = 343,	---	358	ATOMIC_LOAD_XOR_I16_POSTRA = 343,	---
359	ATOMIC_LOAD_XOR_I32 = 344,	---	359	ATOMIC_LOAD_XOR_I32 = 344,	---
360	ATOMIC_LOAD_XOR_I32_POSTRA = 345,	---	360	ATOMIC_LOAD_XOR_I32_POSTRA = 345,	---
361	ATOMIC_LOAD_XOR_I64 = 346,	---	361	ATOMIC_LOAD_XOR_I64 = 346,	---
362	ATOMIC_LOAD_XOR_I64_POSTRA = 347,	---	362	ATOMIC_LOAD_XOR_I64_POSTRA = 347,	---
363	ATOMIC_LOAD_XOR_I8 = 348,	---	363	ATOMIC_LOAD_XOR_I8 = 348,	---
364	ATOMIC_LOAD_XOR_I8_POSTRA = 349,	---	364	ATOMIC_LOAD_XOR_I8_POSTRA = 349,	---
365	ATOMIC_SWAP_I16 = 350,	---	365	ATOMIC_SWAP_I16 = 350,	---
366	ATOMIC_SWAP_I16_POSTRA = 351,	---	366	ATOMIC_SWAP_I16_POSTRA = 351,	---
367	ATOMIC_SWAP_I32 = 352,	---	367	ATOMIC_SWAP_I32 = 352,	---
368	ATOMIC_SWAP_I32_POSTRA = 353,	---	368	ATOMIC_SWAP_I32_POSTRA = 353,	---
369	ATOMIC_SWAP_I64 = 354,	---	369	ATOMIC_SWAP_I64 = 354,	---
370	ATOMIC_SWAP_I64_POSTRA = 355,	---	370	ATOMIC_SWAP_I64_POSTRA = 355,	---
371	ATOMIC_SWAP_I8 = 356,	---	371	ATOMIC_SWAP_I8 = 356,	---
372	ATOMIC_SWAP_I8_POSTRA = 357,	---	372	ATOMIC_SWAP_I8_POSTRA = 357,	---
373	B = 358,	---	373	B = 358,	---
374	BAL_BR = 359,	---	374	BAL_BR = 359,	---
375	BAL_BR_MM = 360,	---	375	BAL_BR_MM = 360,	---
376	BEQLImmMacro = 361,	---	376	BEQLImmMacro = 361,	---
377	BGE = 362,	---	377	BGE = 362,	---
378	BGEImmMacro = 363,	---	378	BGEImmMacro = 363,	---
379	BGEL = 364,	---	379	BGEL = 364,	---
380	BGELImmMacro = 365,	---	380	BGELImmMacro = 365,	---
381	BGEU = 366,	---	381	BGEU = 366,	---
382	BGEUImmMacro = 367,	---	382	BGEUImmMacro = 367,	---
383	BGEUL = 368,	---	383	BGEUL = 368,	---
384	BGEULImmMacro = 369,	---	384	BGEULImmMacro = 369,	---
385	BGT = 370,	---	385	BGT = 370,	---
386	BGTImmMacro = 371,	---	386	BGTImmMacro = 371,	---
387	BGTL = 372,	---	387	BGTL = 372,	---
388	BGTLImmMacro = 373,	---	388	BGTLImmMacro = 373,	---
389	BGTU = 374,	---	389	BGTU = 374,	---
390	BGTUImmMacro = 375,	---	390	BGTUImmMacro = 375,	---
391	BGTUL = 376,	---	391	BGTUL = 376,	---
392	BGTULImmMacro = 377,	---	392	BGTULImmMacro = 377,	---
393	BLE = 378,	---	393	BLE = 378,	---
394	BLEImmMacro = 379,	---	394	BLEImmMacro = 379,	---
395	BLEL = 380,	---	395	BLEL = 380,	---
396	BLELImmMacro = 381,	---	396	BLELImmMacro = 381,	---
397	BLEU = 382,	---	397	BLEU = 382,	---
398	BLEUImmMacro = 383,	---	398	BLEUImmMacro = 383,	---
399	BLEUL = 384,	---	399	BLEUL = 384,	---
400	BLEULImmMacro = 385,	---	400	BLEULImmMacro = 385,	---
401	BLT = 386,	---	401	BLT = 386,	---
402	BLTImmMacro = 387,	---	402	BLTImmMacro = 387,	---
403	BLTL = 388,	---	403	BLTL = 388,	---
404	BLTLImmMacro = 389,	---	404	BLTLImmMacro = 389,	---
405	BLTU = 390,	---	405	BLTU = 390,	---
406	BLTUImmMacro = 391,	---	406	BLTUImmMacro = 391,	---
407	BLTUL = 392,	---	407	BLTUL = 392,	---
408	BLTULImmMacro = 393,	---	408	BLTULImmMacro = 393,	---
409	BNELImmMacro = 394,	---	409	BNELImmMacro = 394,	---
410	BPOSGE32_PSEUDO = 395,	---	410	BPOSGE32_PSEUDO = 395,	---
411	BSEL_D_PSEUDO = 396,	---	411	BSEL_D_PSEUDO = 396,	---
412	BSEL_FD_PSEUDO = 397,	---	412	BSEL_FD_PSEUDO = 397,	---
413	BSEL_FW_PSEUDO = 398,	---	413	BSEL_FW_PSEUDO = 398,	---
414	BSEL_H_PSEUDO = 399,	---	414	BSEL_H_PSEUDO = 399,	---
415	BSEL_W_PSEUDO = 400,	---	415	BSEL_W_PSEUDO = 400,	---
416	B_MM = 401,	---	416	B_MM = 401,	---
417	B_MMR6_Pseudo = 402,	---	417	B_MMR6_Pseudo = 402,	---
418	B_MM_Pseudo = 403,	---	418	B_MM_Pseudo = 403,	---
419	BeqImm = 404,	---	419	BeqImm = 404,	---
420	BneImm = 405,	---	420	BneImm = 405,	---
421	BteqzT8CmpX16 = 406,	---	421	BteqzT8CmpX16 = 406,	---
422	BteqzT8CmpiX16 = 407,	---	422	BteqzT8CmpiX16 = 407,	---
423	BteqzT8SltX16 = 408,	---	423	BteqzT8SltX16 = 408,	---
424	BteqzT8SltiX16 = 409,	---	424	BteqzT8SltiX16 = 409,	---
425	BteqzT8SltiuX16 = 410,	---	425	BteqzT8SltiuX16 = 410,	---
426	BteqzT8SltuX16 = 411,	---	426	BteqzT8SltuX16 = 411,	---
427	BtnezT8CmpX16 = 412,	---	427	BtnezT8CmpX16 = 412,	---
428	BtnezT8CmpiX16 = 413,	---	428	BtnezT8CmpiX16 = 413,	---
429	BtnezT8SltX16 = 414,	---	429	BtnezT8SltX16 = 414,	---
430	BtnezT8SltiX16 = 415,	---	430	BtnezT8SltiX16 = 415,	---
431	BtnezT8SltiuX16 = 416,	---	431	BtnezT8SltiuX16 = 416,	---
432	BtnezT8SltuX16 = 417,	---	432	BtnezT8SltuX16 = 417,	---
433	BuildPairF64 = 418,	---	433	BuildPairF64 = 418,	---
434	BuildPairF64_64 = 419,	---	434	BuildPairF64_64 = 419,	---
435	CFTC1 = 420,	---	435	CFTC1 = 420,	---
436	CONSTPOOL_ENTRY = 421,	---	436	CONSTPOOL_ENTRY = 421,	---
437	COPY_FD_PSEUDO = 422,	---	437	COPY_FD_PSEUDO = 422,	---
438	COPY_FW_PSEUDO = 423,	---	438	COPY_FW_PSEUDO = 423,	---
439	CTTC1 = 424,	---	439	CTTC1 = 424,	---
440	Constant32 = 425,	---	440	Constant32 = 425,	---
441	DMULImmMacro = 426,	---	441	DMULImmMacro = 426,	---
442	DMULMacro = 427,	---	442	DMULMacro = 427,	---
443	DMULOMacro = 428,	---	443	DMULOMacro = 428,	---
444	DMULOUMacro = 429,	---	444	DMULOUMacro = 429,	---
445	DROL = 430,	---	445	DROL = 430,	---
446	DROLImm = 431,	---	446	DROLImm = 431,	---
447	DROR = 432,	---	447	DROR = 432,	---
448	DRORImm = 433,	---	448	DRORImm = 433,	---
449	DSDivIMacro = 434,	---	449	DSDivIMacro = 434,	---
450	DSDivMacro = 435,	---	450	DSDivMacro = 435,	---
451	DSRemIMacro = 436,	---	451	DSRemIMacro = 436,	---
452	DSRemMacro = 437,	---	452	DSRemMacro = 437,	---
453	DUDivIMacro = 438,	---	453	DUDivIMacro = 438,	---
454	DUDivMacro = 439,	---	454	DUDivMacro = 439,	---
455	DURemIMacro = 440,	---	455	DURemIMacro = 440,	---
456	DURemMacro = 441,	---	456	DURemMacro = 441,	---
457	ERet = 442,	---	457	ERet = 442,	---
458	ExtractElementF64 = 443,	---	458	ExtractElementF64 = 443,	---
459	ExtractElementF64_64 = 444,	---	459	ExtractElementF64_64 = 444,	---
460	FABS_D = 445,	---	460	FABS_D = 445,	---
461	FABS_W = 446,	---	461	FABS_W = 446,	---
462	FEXP2_D_1_PSEUDO = 447,	---	462	FEXP2_D_1_PSEUDO = 447,	---
463	FEXP2_W_1_PSEUDO = 448,	---	463	FEXP2_W_1_PSEUDO = 448,	---
464	FILL_FD_PSEUDO = 449,	---	464	FILL_FD_PSEUDO = 449,	---
465	FILL_FW_PSEUDO = 450,	---	465	FILL_FW_PSEUDO = 450,	---
466	GotPrologue16 = 451,	---	466	GotPrologue16 = 451,	---
467	INSERT_B_VIDX64_PSEUDO = 452,	---	467	INSERT_B_VIDX64_PSEUDO = 452,	---
468	INSERT_B_VIDX_PSEUDO = 453,	---	468	INSERT_B_VIDX_PSEUDO = 453,	---
469	INSERT_D_VIDX64_PSEUDO = 454,	---	469	INSERT_D_VIDX64_PSEUDO = 454,	---
470	INSERT_D_VIDX_PSEUDO = 455,	---	470	INSERT_D_VIDX_PSEUDO = 455,	---
471	INSERT_FD_PSEUDO = 456,	---	471	INSERT_FD_PSEUDO = 456,	---
472	INSERT_FD_VIDX64_PSEUDO = 457,	---	472	INSERT_FD_VIDX64_PSEUDO = 457,	---
473	INSERT_FD_VIDX_PSEUDO = 458,	---	473	INSERT_FD_VIDX_PSEUDO = 458,	---
474	INSERT_FW_PSEUDO = 459,	---	474	INSERT_FW_PSEUDO = 459,	---
475	INSERT_FW_VIDX64_PSEUDO = 460,	---	475	INSERT_FW_VIDX64_PSEUDO = 460,	---
476	INSERT_FW_VIDX_PSEUDO = 461,	---	476	INSERT_FW_VIDX_PSEUDO = 461,	---
477	INSERT_H_VIDX64_PSEUDO = 462,	---	477	INSERT_H_VIDX64_PSEUDO = 462,	---
478	INSERT_H_VIDX_PSEUDO = 463,	---	478	INSERT_H_VIDX_PSEUDO = 463,	---
479	INSERT_W_VIDX64_PSEUDO = 464,	---	479	INSERT_W_VIDX64_PSEUDO = 464,	---
480	INSERT_W_VIDX_PSEUDO = 465,	---	480	INSERT_W_VIDX_PSEUDO = 465,	---
481	JALR64Pseudo = 466,	---	481	JALR64Pseudo = 466,	---
482	JALRHB64Pseudo = 467,	---	482	JALRHB64Pseudo = 467,	---
483	JALRHBPseudo = 468,	---	483	JALRHBPseudo = 468,	---
484	JALRPseudo = 469,	---	484	JALRPseudo = 469,	---
485	JAL_MMR6 = 470,	---	485	JAL_MMR6 = 470,	---
486	JalOneReg = 471,	---	486	JalOneReg = 471,	---
487	JalTwoReg = 472,	---	487	JalTwoReg = 472,	---
488	LDMacro = 473,	---	488	LDMacro = 473,	---
489	LDR_D = 474,	---	489	LDR_D = 474,	---
490	LDR_W = 475,	---	490	LDR_W = 475,	---
491	LD_F16 = 476,	---	491	LD_F16 = 476,	---
492	LOAD_ACC128 = 477,	---	492	LOAD_ACC128 = 477,	---
493	LOAD_ACC64 = 478,	---	493	LOAD_ACC64 = 478,	---
494	LOAD_ACC64DSP = 479,	---	494	LOAD_ACC64DSP = 479,	---
495	LOAD_CCOND_DSP = 480,	---	495	LOAD_CCOND_DSP = 480,	---
496	LONG_BRANCH_ADDiu = 481,	---	496	LONG_BRANCH_ADDiu = 481,	---
497	LONG_BRANCH_ADDiu2Op = 482,	---	497	LONG_BRANCH_ADDiu2Op = 482,	---
498	LONG_BRANCH_DADDiu = 483,	---	498	LONG_BRANCH_DADDiu = 483,	---
499	LONG_BRANCH_DADDiu2Op = 484,	---	499	LONG_BRANCH_DADDiu2Op = 484,	---
500	LONG_BRANCH_LUi = 485,	---	500	LONG_BRANCH_LUi = 485,	---
501	LONG_BRANCH_LUi2Op = 486,	---	501	LONG_BRANCH_LUi2Op = 486,	---
502	LONG_BRANCH_LUi2Op_64 = 487,	---	502	LONG_BRANCH_LUi2Op_64 = 487,	---
503	LWM_MM = 488,	---	503	LWM_MM = 488,	---
504	LoadAddrImm32 = 489,	---	504	LoadAddrImm32 = 489,	---
505	LoadAddrImm64 = 490,	---	505	LoadAddrImm64 = 490,	---
506	LoadAddrReg32 = 491,	---	506	LoadAddrReg32 = 491,	---
507	LoadAddrReg64 = 492,	---	507	LoadAddrReg64 = 492,	---
508	LoadImm32 = 493,	---	508	LoadImm32 = 493,	---
509	LoadImm64 = 494,	---	509	LoadImm64 = 494,	---
510	LoadImmDoubleFGR = 495,	---	510	LoadImmDoubleFGR = 495,	---
511	LoadImmDoubleFGR_32 = 496,	---	511	LoadImmDoubleFGR_32 = 496,	---
512	LoadImmDoubleGPR = 497,	---	512	LoadImmDoubleGPR = 497,	---
513	LoadImmSingleFGR = 498,	---	513	LoadImmSingleFGR = 498,	---
514	LoadImmSingleGPR = 499,	---	514	LoadImmSingleGPR = 499,	---
515	LwConstant32 = 500,	---	515	LwConstant32 = 500,	---
516	MFTACX = 501,	---	516	MFTACX = 501,	---
517	MFTC0 = 502,	---	517	MFTC0 = 502,	---
518	MFTC1 = 503,	---	518	MFTC1 = 503,	---
519	MFTDSP = 504,	---	519	MFTDSP = 504,	---
520	MFTGPR = 505,	---	520	MFTGPR = 505,	---
521	MFTHC1 = 506,	---	521	MFTHC1 = 506,	---
522	MFTHI = 507,	---	522	MFTHI = 507,	---
523	MFTLO = 508,	---	523	MFTLO = 508,	---
524	MIPSeh_return32 = 509,	---	524	MIPSeh_return32 = 509,	---
525	MIPSeh_return64 = 510,	---	525	MIPSeh_return64 = 510,	---
526	MSA_FP_EXTEND_D_PSEUDO = 511,	---	526	MSA_FP_EXTEND_D_PSEUDO = 511,	---
527	MSA_FP_EXTEND_W_PSEUDO = 512,	---	527	MSA_FP_EXTEND_W_PSEUDO = 512,	---
528	MSA_FP_ROUND_D_PSEUDO = 513,	---	528	MSA_FP_ROUND_D_PSEUDO = 513,	---
529	MSA_FP_ROUND_W_PSEUDO = 514,	---	529	MSA_FP_ROUND_W_PSEUDO = 514,	---
530	MTTACX = 515,	---	530	MTTACX = 515,	---
531	MTTC0 = 516,	---	531	MTTC0 = 516,	---
532	MTTC1 = 517,	---	532	MTTC1 = 517,	---
533	MTTDSP = 518,	---	533	MTTDSP = 518,	---
534	MTTGPR = 519,	---	534	MTTGPR = 519,	---
535	MTTHC1 = 520,	---	535	MTTHC1 = 520,	---
536	MTTHI = 521,	---	536	MTTHI = 521,	---
537	MTTLO = 522,	---	537	MTTLO = 522,	---
538	MULImmMacro = 523,	---	538	MULImmMacro = 523,	---
539	MULOMacro = 524,	---	539	MULOMacro = 524,	---
540	MULOUMacro = 525,	---	540	MULOUMacro = 525,	---
541	MultRxRy16 = 526,	---	541	MultRxRy16 = 526,	---
542	MultRxRyRz16 = 527,	---	542	MultRxRyRz16 = 527,	---
543	MultuRxRy16 = 528,	---	543	MultuRxRy16 = 528,	---
544	MultuRxRyRz16 = 529,	---	544	MultuRxRyRz16 = 529,	---
545	NOP = 530,	---	545	NOP = 530,	---
546	NORImm = 531,	---	546	NORImm = 531,	---
547	NORImm64 = 532,	---	547	NORImm64 = 532,	---
548	NOR_V_D_PSEUDO = 533,	---	548	NOR_V_D_PSEUDO = 533,	---
549	NOR_V_H_PSEUDO = 534,	---	549	NOR_V_H_PSEUDO = 534,	---
550	NOR_V_W_PSEUDO = 535,	---	550	NOR_V_W_PSEUDO = 535,	---
551	OR_V_D_PSEUDO = 536,	---	551	OR_V_D_PSEUDO = 536,	---
552	OR_V_H_PSEUDO = 537,	---	552	OR_V_H_PSEUDO = 537,	---
553	OR_V_W_PSEUDO = 538,	---	553	OR_V_W_PSEUDO = 538,	---
554	PseudoCMPU_EQ_QB = 539,	---	554	PseudoCMPU_EQ_QB = 539,	---
555	PseudoCMPU_LE_QB = 540,	---	555	PseudoCMPU_LE_QB = 540,	---
556	PseudoCMPU_LT_QB = 541,	---	556	PseudoCMPU_LT_QB = 541,	---
557	PseudoCMP_EQ_PH = 542,	---	557	PseudoCMP_EQ_PH = 542,	---
558	PseudoCMP_LE_PH = 543,	---	558	PseudoCMP_LE_PH = 543,	---
559	PseudoCMP_LT_PH = 544,	---	559	PseudoCMP_LT_PH = 544,	---
560	PseudoCVT_D32_W = 545,	---	560	PseudoCVT_D32_W = 545,	---
561	PseudoCVT_D64_L = 546,	---	561	PseudoCVT_D64_L = 546,	---
562	PseudoCVT_D64_W = 547,	---	562	PseudoCVT_D64_W = 547,	---
563	PseudoCVT_S_L = 548,	---	563	PseudoCVT_S_L = 548,	---
564	PseudoCVT_S_W = 549,	---	564	PseudoCVT_S_W = 549,	---
565	PseudoDMULT = 550,	---	565	PseudoDMULT = 550,	---
566	PseudoDMULTu = 551,	---	566	PseudoDMULTu = 551,	---
567	PseudoDSDIV = 552,	---	567	PseudoDSDIV = 552,	---
568	PseudoDUDIV = 553,	---	568	PseudoDUDIV = 553,	---
569	PseudoD_SELECT_I = 554,	---	569	PseudoD_SELECT_I = 554,	---
570	PseudoD_SELECT_I64 = 555,	---	570	PseudoD_SELECT_I64 = 555,	---
571	PseudoIndirectBranch = 556,	---	571	PseudoIndirectBranch = 556,	---
572	PseudoIndirectBranch64 = 557,	---	572	PseudoIndirectBranch64 = 557,	---
573	PseudoIndirectBranch64R6 = 558,	---	573	PseudoIndirectBranch64R6 = 558,	---
574	PseudoIndirectBranchR6 = 559,	---	574	PseudoIndirectBranchR6 = 559,	---
575	PseudoIndirectBranch_MM = 560,	---	575	PseudoIndirectBranch_MM = 560,	---
576	PseudoIndirectBranch_MMR6 = 561,	---	576	PseudoIndirectBranch_MMR6 = 561,	---
577	PseudoIndirectHazardBranch = 562,	---	577	PseudoIndirectHazardBranch = 562,	---
578	PseudoIndirectHazardBranch64 = 563,	---	578	PseudoIndirectHazardBranch64 = 563,	---
579	PseudoIndrectHazardBranch64R6 = 564,	---	579	PseudoIndrectHazardBranch64R6 = 564,	---
580	PseudoIndrectHazardBranchR6 = 565,	---	580	PseudoIndrectHazardBranchR6 = 565,	---
581	PseudoMADD = 566,	---	581	PseudoMADD = 566,	---
582	PseudoMADDU = 567,	---	582	PseudoMADDU = 567,	---
583	PseudoMADDU_MM = 568,	---	583	PseudoMADDU_MM = 568,	---
584	PseudoMADD_MM = 569,	---	584	PseudoMADD_MM = 569,	---
585	PseudoMFHI = 570,	---	585	PseudoMFHI = 570,	---
586	PseudoMFHI64 = 571,	---	586	PseudoMFHI64 = 571,	---
587	PseudoMFHI_MM = 572,	---	587	PseudoMFHI_MM = 572,	---
588	PseudoMFLO = 573,	---	588	PseudoMFLO = 573,	---
589	PseudoMFLO64 = 574,	---	589	PseudoMFLO64 = 574,	---
590	PseudoMFLO_MM = 575,	---	590	PseudoMFLO_MM = 575,	---
591	PseudoMSUB = 576,	---	591	PseudoMSUB = 576,	---
592	PseudoMSUBU = 577,	---	592	PseudoMSUBU = 577,	---
593	PseudoMSUBU_MM = 578,	---	593	PseudoMSUBU_MM = 578,	---
594	PseudoMSUB_MM = 579,	---	594	PseudoMSUB_MM = 579,	---
595	PseudoMTLOHI = 580,	---	595	PseudoMTLOHI = 580,	---
596	PseudoMTLOHI64 = 581,	---	596	PseudoMTLOHI64 = 581,	---
597	PseudoMTLOHI_DSP = 582,	---	597	PseudoMTLOHI_DSP = 582,	---
598	PseudoMTLOHI_MM = 583,	---	598	PseudoMTLOHI_MM = 583,	---
599	PseudoMULT = 584,	---	599	PseudoMULT = 584,	---
600	PseudoMULT_MM = 585,	---	600	PseudoMULT_MM = 585,	---
601	PseudoMULTu = 586,	---	601	PseudoMULTu = 586,	---
602	PseudoMULTu_MM = 587,	---	602	PseudoMULTu_MM = 587,	---
603	PseudoPICK_PH = 588,	---	603	PseudoPICK_PH = 588,	---
604	PseudoPICK_QB = 589,	---	604	PseudoPICK_QB = 589,	---
605	PseudoReturn = 590,	---	605	PseudoReturn = 590,	---
606	PseudoReturn64 = 591,	---	606	PseudoReturn64 = 591,	---
607	PseudoSDIV = 592,	---	607	PseudoSDIV = 592,	---
608	PseudoSELECTFP_F_D32 = 593,	---	608	PseudoSELECTFP_F_D32 = 593,	---
609	PseudoSELECTFP_F_D64 = 594,	---	609	PseudoSELECTFP_F_D64 = 594,	---
610	PseudoSELECTFP_F_I = 595,	---	610	PseudoSELECTFP_F_I = 595,	---
611	PseudoSELECTFP_F_I64 = 596,	---	611	PseudoSELECTFP_F_I64 = 596,	---
612	PseudoSELECTFP_F_S = 597,	---	612	PseudoSELECTFP_F_S = 597,	---
613	PseudoSELECTFP_T_D32 = 598,	---	613	PseudoSELECTFP_T_D32 = 598,	---
614	PseudoSELECTFP_T_D64 = 599,	---	614	PseudoSELECTFP_T_D64 = 599,	---
615	PseudoSELECTFP_T_I = 600,	---	615	PseudoSELECTFP_T_I = 600,	---
616	PseudoSELECTFP_T_I64 = 601,	---	616	PseudoSELECTFP_T_I64 = 601,	---
617	PseudoSELECTFP_T_S = 602,	---	617	PseudoSELECTFP_T_S = 602,	---
618	PseudoSELECT_D32 = 603,	---	618	PseudoSELECT_D32 = 603,	---
619	PseudoSELECT_D64 = 604,	---	619	PseudoSELECT_D64 = 604,	---
620	PseudoSELECT_I = 605,	---	620	PseudoSELECT_I = 605,	---
621	PseudoSELECT_I64 = 606,	---	621	PseudoSELECT_I64 = 606,	---
622	PseudoSELECT_S = 607,	---	622	PseudoSELECT_S = 607,	---
623	PseudoTRUNC_W_D = 608,	---	623	PseudoTRUNC_W_D = 608,	---
624	PseudoTRUNC_W_D32 = 609,	---	624	PseudoTRUNC_W_D32 = 609,	---
625	PseudoTRUNC_W_S = 610,	---	625	PseudoTRUNC_W_S = 610,	---
626	PseudoUDIV = 611,	---	626	PseudoUDIV = 611,	---
627	ROL = 612,	---	627	ROL = 612,	---
628	ROLImm = 613,	---	628	ROLImm = 613,	---
629	ROR = 614,	---	629	ROR = 614,	---
630	RORImm = 615,	---	630	RORImm = 615,	---
631	RetRA = 616,	---	631	RetRA = 616,	---
632	RetRA16 = 617,	---	632	RetRA16 = 617,	---
633	SDC1_M1 = 618,	---	633	SDC1_M1 = 618,	---
634	SDIV_MM_Pseudo = 619,	---	634	SDIV_MM_Pseudo = 619,	---
635	SDMacro = 620,	---	635	SDMacro = 620,	---
636	SDivIMacro = 621,	---	636	SDivIMacro = 621,	---
637	SDivMacro = 622,	---	637	SDivMacro = 622,	---
638	SEQIMacro = 623,	---	638	SEQIMacro = 623,	---
639	SEQMacro = 624,	---	639	SEQMacro = 624,	---
640	SGE = 625,	---	640	SGE = 625,	---
641	SGEImm = 626,	---	641	SGEImm = 626,	---
642	SGEImm64 = 627,	---	642	SGEImm64 = 627,	---
643	SGEU = 628,	---	643	SGEU = 628,	---
644	SGEUImm = 629,	---	644	SGEUImm = 629,	---
645	SGEUImm64 = 630,	---	645	SGEUImm64 = 630,	---
646	SGTImm = 631,	---	646	SGTImm = 631,	---
647	SGTImm64 = 632,	---	647	SGTImm64 = 632,	---
648	SGTUImm = 633,	---	648	SGTUImm = 633,	---
649	SGTUImm64 = 634,	---	649	SGTUImm64 = 634,	---
650	SLE = 635,	---	650	SLE = 635,	---
651	SLEImm = 636,	---	651	SLEImm = 636,	---
652	SLEImm64 = 637,	---	652	SLEImm64 = 637,	---
653	SLEU = 638,	---	653	SLEU = 638,	---
654	SLEUImm = 639,	---	654	SLEUImm = 639,	---
655	SLEUImm64 = 640,	---	655	SLEUImm64 = 640,	---
656	SLTImm64 = 641,	---	656	SLTImm64 = 641,	---
657	SLTUImm64 = 642,	---	657	SLTUImm64 = 642,	---
658	SNEIMacro = 643,	---	658	SNEIMacro = 643,	---
659	SNEMacro = 644,	---	659	SNEMacro = 644,	---
660	SNZ_B_PSEUDO = 645,	---	660	SNZ_B_PSEUDO = 645,	---
661	SNZ_D_PSEUDO = 646,	---	661	SNZ_D_PSEUDO = 646,	---
662	SNZ_H_PSEUDO = 647,	---	662	SNZ_H_PSEUDO = 647,	---
663	SNZ_V_PSEUDO = 648,	---	663	SNZ_V_PSEUDO = 648,	---
664	SNZ_W_PSEUDO = 649,	---	664	SNZ_W_PSEUDO = 649,	---
665	SRemIMacro = 650,	---	665	SRemIMacro = 650,	---
666	SRemMacro = 651,	---	666	SRemMacro = 651,	---
667	STORE_ACC128 = 652,	---	667	STORE_ACC128 = 652,	---
668	STORE_ACC64 = 653,	---	668	STORE_ACC64 = 653,	---
669	STORE_ACC64DSP = 654,	---	669	STORE_ACC64DSP = 654,	---
670	STORE_CCOND_DSP = 655,	---	670	STORE_CCOND_DSP = 655,	---
671	STR_D = 656,	---	671	STR_D = 656,	---
672	STR_W = 657,	---	672	STR_W = 657,	---
673	ST_F16 = 658,	---	673	ST_F16 = 658,	---
674	SWM_MM = 659,	---	674	SWM_MM = 659,	---
675	SZ_B_PSEUDO = 660,	---	675	SZ_B_PSEUDO = 660,	---
676	SZ_D_PSEUDO = 661,	---	676	SZ_D_PSEUDO = 661,	---
677	SZ_H_PSEUDO = 662,	---	677	SZ_H_PSEUDO = 662,	---
678	SZ_V_PSEUDO = 663,	---	678	SZ_V_PSEUDO = 663,	---
679	SZ_W_PSEUDO = 664,	---	679	SZ_W_PSEUDO = 664,	---
680	SaaAddr = 665,	---	680	SaaAddr = 665,	---
681	SaadAddr = 666,	---	681	SaadAddr = 666,	---
682	SelBeqZ = 667,	---	682	SelBeqZ = 667,	---
683	SelBneZ = 668,	---	683	SelBneZ = 668,	---
684	SelTBteqZCmp = 669,	---	684	SelTBteqZCmp = 669,	---
685	SelTBteqZCmpi = 670,	---	685	SelTBteqZCmpi = 670,	---
686	SelTBteqZSlt = 671,	---	686	SelTBteqZSlt = 671,	---
687	SelTBteqZSlti = 672,	---	687	SelTBteqZSlti = 672,	---
688	SelTBteqZSltiu = 673,	---	688	SelTBteqZSltiu = 673,	---
689	SelTBteqZSltu = 674,	---	689	SelTBteqZSltu = 674,	---
690	SelTBtneZCmp = 675,	---	690	SelTBtneZCmp = 675,	---
691	SelTBtneZCmpi = 676,	---	691	SelTBtneZCmpi = 676,	---
692	SelTBtneZSlt = 677,	---	692	SelTBtneZSlt = 677,	---
693	SelTBtneZSlti = 678,	---	693	SelTBtneZSlti = 678,	---
694	SelTBtneZSltiu = 679,	---	694	SelTBtneZSltiu = 679,	---
695	SelTBtneZSltu = 680,	---	695	SelTBtneZSltu = 680,	---
696	SltCCRxRy16 = 681,	---	696	SltCCRxRy16 = 681,	---
697	SltiCCRxImmX16 = 682,	---	697	SltiCCRxImmX16 = 682,	---
698	SltiuCCRxImmX16 = 683,	---	698	SltiuCCRxImmX16 = 683,	---
699	SltuCCRxRy16 = 684,	---	699	SltuCCRxRy16 = 684,	---
700	SltuRxRyRz16 = 685,	---	700	SltuRxRyRz16 = 685,	---
701	TAILCALL = 686,	---	701	TAILCALL = 686,	---
702	TAILCALL64R6REG = 687,	---	702	TAILCALL64R6REG = 687,	---
703	TAILCALLHB64R6REG = 688,	---	703	TAILCALLHB64R6REG = 688,	---
704	TAILCALLHBR6REG = 689,	---	704	TAILCALLHBR6REG = 689,	---
705	TAILCALLR6REG = 690,	---	705	TAILCALLR6REG = 690,	---
706	TAILCALLREG = 691,	---	706	TAILCALLREG = 691,	---
707	TAILCALLREG64 = 692,	---	707	TAILCALLREG64 = 692,	---
708	TAILCALLREGHB = 693,	---	708	TAILCALLREGHB = 693,	---
709	TAILCALLREGHB64 = 694,	---	709	TAILCALLREGHB64 = 694,	---
710	TAILCALLREG_MM = 695,	---	710	TAILCALLREG_MM = 695,	---
711	TAILCALLREG_MMR6 = 696,	---	711	TAILCALLREG_MMR6 = 696,	---
712	TAILCALL_MM = 697,	---	712	TAILCALL_MM = 697,	---
713	TAILCALL_MMR6 = 698,	---	713	TAILCALL_MMR6 = 698,	---
714	TRAP = 699,	---	714	TRAP = 699,	---
715	TRAP_MM = 700,	---	715	TRAP_MM = 700,	---
716	UDIV_MM_Pseudo = 701,	---	716	UDIV_MM_Pseudo = 701,	---
717	UDivIMacro = 702,	---	717	UDivIMacro = 702,	---
718	UDivMacro = 703,	---	718	UDivMacro = 703,	---
719	URemIMacro = 704,	---	719	URemIMacro = 704,	---
720	URemMacro = 705,	---	720	URemMacro = 705,	---
721	Ulh = 706,	---	721	Ulh = 706,	---
722	Ulhu = 707,	---	722	Ulhu = 707,	---
723	Ulw = 708,	---	723	Ulw = 708,	---
724	Ush = 709,	---	724	Ush = 709,	---
725	Usw = 710,	---	725	Usw = 710,	---
726	XOR_V_D_PSEUDO = 711,	---	726	XOR_V_D_PSEUDO = 711,	---
727	XOR_V_H_PSEUDO = 712,	---	727	XOR_V_H_PSEUDO = 712,	---
728	XOR_V_W_PSEUDO = 713,	---	728	XOR_V_W_PSEUDO = 713,	---
729	ABSQ_S_PH = 714,	---	729	ABSQ_S_PH = 714,	---
730	ABSQ_S_PH_MM = 715,	---	730	ABSQ_S_PH_MM = 715,	---
731	ABSQ_S_QB = 716,	---	731	ABSQ_S_QB = 716,	---
732	ABSQ_S_QB_MMR2 = 717,	---	732	ABSQ_S_QB_MMR2 = 717,	---
733	ABSQ_S_W = 718,	---	733	ABSQ_S_W = 718,	---
734	ABSQ_S_W_MM = 719,	---	734	ABSQ_S_W_MM = 719,	---
735	ADD = 720,	---	735	ADD = 720,	---
736	ADDIUPC = 721,	---	736	ADDIUPC = 721,	---
737	ADDIUPC_MM = 722,	---	737	ADDIUPC_MM = 722,	---
738	ADDIUPC_MMR6 = 723,	---	738	ADDIUPC_MMR6 = 723,	---
739	ADDIUR1SP_MM = 724,	---	739	ADDIUR1SP_MM = 724,	---
740	ADDIUR2_MM = 725,	---	740	ADDIUR2_MM = 725,	---
741	ADDIUS5_MM = 726,	---	741	ADDIUS5_MM = 726,	---
742	ADDIUSP_MM = 727,	---	742	ADDIUSP_MM = 727,	---
743	ADDIU_MMR6 = 728,	---	743	ADDIU_MMR6 = 728,	---
744	ADDQH_PH = 729,	---	744	ADDQH_PH = 729,	---
745	ADDQH_PH_MMR2 = 730,	---	745	ADDQH_PH_MMR2 = 730,	---
746	ADDQH_R_PH = 731,	---	746	ADDQH_R_PH = 731,	---
747	ADDQH_R_PH_MMR2 = 732,	---	747	ADDQH_R_PH_MMR2 = 732,	---
748	ADDQH_R_W = 733,	---	748	ADDQH_R_W = 733,	---
749	ADDQH_R_W_MMR2 = 734,	---	749	ADDQH_R_W_MMR2 = 734,	---
750	ADDQH_W = 735,	---	750	ADDQH_W = 735,	---
751	ADDQH_W_MMR2 = 736,	---	751	ADDQH_W_MMR2 = 736,	---
752	ADDQ_PH = 737,	---	752	ADDQ_PH = 737,	---
753	ADDQ_PH_MM = 738,	---	753	ADDQ_PH_MM = 738,	---
754	ADDQ_S_PH = 739,	---	754	ADDQ_S_PH = 739,	---
755	ADDQ_S_PH_MM = 740,	---	755	ADDQ_S_PH_MM = 740,	---
756	ADDQ_S_W = 741,	---	756	ADDQ_S_W = 741,	---
757	ADDQ_S_W_MM = 742,	---	757	ADDQ_S_W_MM = 742,	---
758	ADDR_PS64 = 743,	---	758	ADDR_PS64 = 743,	---
759	ADDSC = 744,	---	759	ADDSC = 744,	---
760	ADDSC_MM = 745,	---	760	ADDSC_MM = 745,	---
761	ADDS_A_B = 746,	---	761	ADDS_A_B = 746,	---
762	ADDS_A_D = 747,	---	762	ADDS_A_D = 747,	---
763	ADDS_A_H = 748,	---	763	ADDS_A_H = 748,	---
764	ADDS_A_W = 749,	---	764	ADDS_A_W = 749,	---
765	ADDS_S_B = 750,	---	765	ADDS_S_B = 750,	---
766	ADDS_S_D = 751,	---	766	ADDS_S_D = 751,	---
767	ADDS_S_H = 752,	---	767	ADDS_S_H = 752,	---
768	ADDS_S_W = 753,	---	768	ADDS_S_W = 753,	---
769	ADDS_U_B = 754,	---	769	ADDS_U_B = 754,	---
770	ADDS_U_D = 755,	---	770	ADDS_U_D = 755,	---
771	ADDS_U_H = 756,	---	771	ADDS_U_H = 756,	---
772	ADDS_U_W = 757,	---	772	ADDS_U_W = 757,	---
773	ADDU16_MM = 758,	---	773	ADDU16_MM = 758,	---
774	ADDU16_MMR6 = 759,	---	774	ADDU16_MMR6 = 759,	---
775	ADDUH_QB = 760,	---	775	ADDUH_QB = 760,	---
776	ADDUH_QB_MMR2 = 761,	---	776	ADDUH_QB_MMR2 = 761,	---
777	ADDUH_R_QB = 762,	---	777	ADDUH_R_QB = 762,	---
778	ADDUH_R_QB_MMR2 = 763,	---	778	ADDUH_R_QB_MMR2 = 763,	---
779	ADDU_MMR6 = 764,	---	779	ADDU_MMR6 = 764,	---
780	ADDU_PH = 765,	---	780	ADDU_PH = 765,	---
781	ADDU_PH_MMR2 = 766,	---	781	ADDU_PH_MMR2 = 766,	---
782	ADDU_QB = 767,	---	782	ADDU_QB = 767,	---
783	ADDU_QB_MM = 768,	---	783	ADDU_QB_MM = 768,	---
784	ADDU_S_PH = 769,	---	784	ADDU_S_PH = 769,	---
785	ADDU_S_PH_MMR2 = 770,	---	785	ADDU_S_PH_MMR2 = 770,	---
786	ADDU_S_QB = 771,	---	786	ADDU_S_QB = 771,	---
787	ADDU_S_QB_MM = 772,	---	787	ADDU_S_QB_MM = 772,	---
788	ADDVI_B = 773,	---	788	ADDVI_B = 773,	---
789	ADDVI_D = 774,	---	789	ADDVI_D = 774,	---
790	ADDVI_H = 775,	---	790	ADDVI_H = 775,	---
791	ADDVI_W = 776,	---	791	ADDVI_W = 776,	---
792	ADDV_B = 777,	---	792	ADDV_B = 777,	---
793	ADDV_D = 778,	---	793	ADDV_D = 778,	---
794	ADDV_H = 779,	---	794	ADDV_H = 779,	---
795	ADDV_W = 780,	---	795	ADDV_W = 780,	---
796	ADDWC = 781,	---	796	ADDWC = 781,	---
797	ADDWC_MM = 782,	---	797	ADDWC_MM = 782,	---
798	ADD_A_B = 783,	---	798	ADD_A_B = 783,	---
799	ADD_A_D = 784,	---	799	ADD_A_D = 784,	---
800	ADD_A_H = 785,	---	800	ADD_A_H = 785,	---
801	ADD_A_W = 786,	---	801	ADD_A_W = 786,	---
802	ADD_MM = 787,	---	802	ADD_MM = 787,	---
803	ADD_MMR6 = 788,	---	803	ADD_MMR6 = 788,	---
804	ADDi = 789,	---	804	ADDi = 789,	---
805	ADDi_MM = 790,	---	805	ADDi_MM = 790,	---
806	ADDiu = 791,	---	806	ADDiu = 791,	---
807	ADDiu_MM = 792,	---	807	ADDiu_MM = 792,	---
808	ADDu = 793,	---	808	ADDu = 793,	---
809	ADDu_MM = 794,	---	809	ADDu_MM = 794,	---
810	ALIGN = 795,	---	810	ALIGN = 795,	---
811	ALIGN_MMR6 = 796,	---	811	ALIGN_MMR6 = 796,	---
812	ALUIPC = 797,	---	812	ALUIPC = 797,	---
813	ALUIPC_MMR6 = 798,	---	813	ALUIPC_MMR6 = 798,	---
814	AND = 799,	---	814	AND = 799,	---
815	AND16_MM = 800,	---	815	AND16_MM = 800,	---
816	AND16_MMR6 = 801,	---	816	AND16_MMR6 = 801,	---
817	AND64 = 802,	---	817	AND64 = 802,	---
818	ANDI16_MM = 803,	---	818	ANDI16_MM = 803,	---
819	ANDI16_MMR6 = 804,	---	819	ANDI16_MMR6 = 804,	---
820	ANDI_B = 805,	---	820	ANDI_B = 805,	---
821	ANDI_MMR6 = 806,	---	821	ANDI_MMR6 = 806,	---
822	AND_MM = 807,	---	822	AND_MM = 807,	---
823	AND_MMR6 = 808,	---	823	AND_MMR6 = 808,	---
824	AND_V = 809,	---	824	AND_V = 809,	---
825	ANDi = 810,	---	825	ANDi = 810,	---
826	ANDi64 = 811,	---	826	ANDi64 = 811,	---
827	ANDi_MM = 812,	---	827	ANDi_MM = 812,	---
828	APPEND = 813,	---	828	APPEND = 813,	---
829	APPEND_MMR2 = 814,	---	829	APPEND_MMR2 = 814,	---
830	ASUB_S_B = 815,	---	830	ASUB_S_B = 815,	---
831	ASUB_S_D = 816,	---	831	ASUB_S_D = 816,	---
832	ASUB_S_H = 817,	---	832	ASUB_S_H = 817,	---
833	ASUB_S_W = 818,	---	833	ASUB_S_W = 818,	---
834	ASUB_U_B = 819,	---	834	ASUB_U_B = 819,	---
835	ASUB_U_D = 820,	---	835	ASUB_U_D = 820,	---
836	ASUB_U_H = 821,	---	836	ASUB_U_H = 821,	---
837	ASUB_U_W = 822,	---	837	ASUB_U_W = 822,	---
838	AUI = 823,	---	838	AUI = 823,	---
839	AUIPC = 824,	---	839	AUIPC = 824,	---
840	AUIPC_MMR6 = 825,	---	840	AUIPC_MMR6 = 825,	---
841	AUI_MMR6 = 826,	---	841	AUI_MMR6 = 826,	---
842	AVER_S_B = 827,	---	842	AVER_S_B = 827,	---
843	AVER_S_D = 828,	---	843	AVER_S_D = 828,	---
844	AVER_S_H = 829,	---	844	AVER_S_H = 829,	---
845	AVER_S_W = 830,	---	845	AVER_S_W = 830,	---
846	AVER_U_B = 831,	---	846	AVER_U_B = 831,	---
847	AVER_U_D = 832,	---	847	AVER_U_D = 832,	---
848	AVER_U_H = 833,	---	848	AVER_U_H = 833,	---
849	AVER_U_W = 834,	---	849	AVER_U_W = 834,	---
850	AVE_S_B = 835,	---	850	AVE_S_B = 835,	---
851	AVE_S_D = 836,	---	851	AVE_S_D = 836,	---
852	AVE_S_H = 837,	---	852	AVE_S_H = 837,	---
853	AVE_S_W = 838,	---	853	AVE_S_W = 838,	---
854	AVE_U_B = 839,	---	854	AVE_U_B = 839,	---
855	AVE_U_D = 840,	---	855	AVE_U_D = 840,	---
856	AVE_U_H = 841,	---	856	AVE_U_H = 841,	---
857	AVE_U_W = 842,	---	857	AVE_U_W = 842,	---
858	AddiuRxImmX16 = 843,	---	858	AddiuRxImmX16 = 843,	---
859	AddiuRxPcImmX16 = 844,	---	859	AddiuRxPcImmX16 = 844,	---
860	AddiuRxRxImm16 = 845,	---	860	AddiuRxRxImm16 = 845,	---
861	AddiuRxRxImmX16 = 846,	---	861	AddiuRxRxImmX16 = 846,	---
862	AddiuRxRyOffMemX16 = 847,	---	862	AddiuRxRyOffMemX16 = 847,	---
863	AddiuSpImm16 = 848,	---	863	AddiuSpImm16 = 848,	---
864	AddiuSpImmX16 = 849,	---	864	AddiuSpImmX16 = 849,	---
865	AdduRxRyRz16 = 850,	---	865	AdduRxRyRz16 = 850,	---
866	AndRxRxRy16 = 851,	---	866	AndRxRxRy16 = 851,	---
867	B16_MM = 852,	---	867	B16_MM = 852,	---
868	BADDu = 853,	---	868	BADDu = 853,	---
869	BAL = 854,	---	869	BAL = 854,	---
870	BALC = 855,	---	870	BALC = 855,	---
871	BALC_MMR6 = 856,	---	871	BALC_MMR6 = 856,	---
872	BALIGN = 857,	---	872	BALIGN = 857,	---
873	BALIGN_MMR2 = 858,	---	873	BALIGN_MMR2 = 858,	---
874	BBIT0 = 859,	---	874	BBIT0 = 859,	---
875	BBIT032 = 860,	---	875	BBIT032 = 860,	---
876	BBIT1 = 861,	---	876	BBIT1 = 861,	---
877	BBIT132 = 862,	---	877	BBIT132 = 862,	---
878	BC = 863,	---	878	BC = 863,	---
879	BC16_MMR6 = 864,	---	879	BC16_MMR6 = 864,	---
880	BC1EQZ = 865,	---	880	BC1EQZ = 865,	---
881	BC1EQZC_MMR6 = 866,	---	881	BC1EQZC_MMR6 = 866,	---
882	BC1F = 867,	---	882	BC1F = 867,	---
883	BC1FL = 868,	---	883	BC1FL = 868,	---
884	BC1F_MM = 869,	---	884	BC1F_MM = 869,	---
885	BC1NEZ = 870,	---	885	BC1NEZ = 870,	---
886	BC1NEZC_MMR6 = 871,	---	886	BC1NEZC_MMR6 = 871,	---
887	BC1T = 872,	---	887	BC1T = 872,	---
888	BC1TL = 873,	---	888	BC1TL = 873,	---
889	BC1T_MM = 874,	---	889	BC1T_MM = 874,	---
890	BC2EQZ = 875,	---	890	BC2EQZ = 875,	---
891	BC2EQZC_MMR6 = 876,	---	891	BC2EQZC_MMR6 = 876,	---
892	BC2NEZ = 877,	---	892	BC2NEZ = 877,	---
893	BC2NEZC_MMR6 = 878,	---	893	BC2NEZC_MMR6 = 878,	---
894	BCLRI_B = 879,	---	894	BCLRI_B = 879,	---
895	BCLRI_D = 880,	---	895	BCLRI_D = 880,	---
896	BCLRI_H = 881,	---	896	BCLRI_H = 881,	---
897	BCLRI_W = 882,	---	897	BCLRI_W = 882,	---
898	BCLR_B = 883,	---	898	BCLR_B = 883,	---
899	BCLR_D = 884,	---	899	BCLR_D = 884,	---
900	BCLR_H = 885,	---	900	BCLR_H = 885,	---
901	BCLR_W = 886,	---	901	BCLR_W = 886,	---
902	BC_MMR6 = 887,	---	902	BC_MMR6 = 887,	---
903	BEQ = 888,	---	903	BEQ = 888,	---
904	BEQ64 = 889,	---	904	BEQ64 = 889,	---
905	BEQC = 890,	---	905	BEQC = 890,	---
906	BEQC64 = 891,	---	906	BEQC64 = 891,	---
907	BEQC_MMR6 = 892,	---	907	BEQC_MMR6 = 892,	---
908	BEQL = 893,	---	908	BEQL = 893,	---
909	BEQZ16_MM = 894,	---	909	BEQZ16_MM = 894,	---
910	BEQZALC = 895,	---	910	BEQZALC = 895,	---
911	BEQZALC_MMR6 = 896,	---	911	BEQZALC_MMR6 = 896,	---
912	BEQZC = 897,	---	912	BEQZC = 897,	---
913	BEQZC16_MMR6 = 898,	---	913	BEQZC16_MMR6 = 898,	---
914	BEQZC64 = 899,	---	914	BEQZC64 = 899,	---
915	BEQZC_MM = 900,	---	915	BEQZC_MM = 900,	---
916	BEQZC_MMR6 = 901,	---	916	BEQZC_MMR6 = 901,	---
917	BEQ_MM = 902,	---	917	BEQ_MM = 902,	---
918	BGEC = 903,	---	918	BGEC = 903,	---
919	BGEC64 = 904,	---	919	BGEC64 = 904,	---
920	BGEC_MMR6 = 905,	---	920	BGEC_MMR6 = 905,	---
921	BGEUC = 906,	---	921	BGEUC = 906,	---
922	BGEUC64 = 907,	---	922	BGEUC64 = 907,	---
923	BGEUC_MMR6 = 908,	---	923	BGEUC_MMR6 = 908,	---
924	BGEZ = 909,	---	924	BGEZ = 909,	---
925	BGEZ64 = 910,	---	925	BGEZ64 = 910,	---
926	BGEZAL = 911,	---	926	BGEZAL = 911,	---
927	BGEZALC = 912,	---	927	BGEZALC = 912,	---
928	BGEZALC_MMR6 = 913,	---	928	BGEZALC_MMR6 = 913,	---
929	BGEZALL = 914,	---	929	BGEZALL = 914,	---
930	BGEZALS_MM = 915,	---	930	BGEZALS_MM = 915,	---
931	BGEZAL_MM = 916,	---	931	BGEZAL_MM = 916,	---
932	BGEZC = 917,	---	932	BGEZC = 917,	---
933	BGEZC64 = 918,	---	933	BGEZC64 = 918,	---
934	BGEZC_MMR6 = 919,	---	934	BGEZC_MMR6 = 919,	---
935	BGEZL = 920,	---	935	BGEZL = 920,	---
936	BGEZ_MM = 921,	---	936	BGEZ_MM = 921,	---
937	BGTZ = 922,	---	937	BGTZ = 922,	---
938	BGTZ64 = 923,	---	938	BGTZ64 = 923,	---
939	BGTZALC = 924,	---	939	BGTZALC = 924,	---
940	BGTZALC_MMR6 = 925,	---	940	BGTZALC_MMR6 = 925,	---
941	BGTZC = 926,	---	941	BGTZC = 926,	---
942	BGTZC64 = 927,	---	942	BGTZC64 = 927,	---
943	BGTZC_MMR6 = 928,	---	943	BGTZC_MMR6 = 928,	---
944	BGTZL = 929,	---	944	BGTZL = 929,	---
945	BGTZ_MM = 930,	---	945	BGTZ_MM = 930,	---
946	BINSLI_B = 931,	---	946	BINSLI_B = 931,	---
947	BINSLI_D = 932,	---	947	BINSLI_D = 932,	---
948	BINSLI_H = 933,	---	948	BINSLI_H = 933,	---
949	BINSLI_W = 934,	---	949	BINSLI_W = 934,	---
950	BINSL_B = 935,	---	950	BINSL_B = 935,	---
951	BINSL_D = 936,	---	951	BINSL_D = 936,	---
952	BINSL_H = 937,	---	952	BINSL_H = 937,	---
953	BINSL_W = 938,	---	953	BINSL_W = 938,	---
954	BINSRI_B = 939,	---	954	BINSRI_B = 939,	---
955	BINSRI_D = 940,	---	955	BINSRI_D = 940,	---
956	BINSRI_H = 941,	---	956	BINSRI_H = 941,	---
957	BINSRI_W = 942,	---	957	BINSRI_W = 942,	---
958	BINSR_B = 943,	---	958	BINSR_B = 943,	---
959	BINSR_D = 944,	---	959	BINSR_D = 944,	---
960	BINSR_H = 945,	---	960	BINSR_H = 945,	---
961	BINSR_W = 946,	---	961	BINSR_W = 946,	---
962	BITREV = 947,	---	962	BITREV = 947,	---
963	BITREV_MM = 948,	---	963	BITREV_MM = 948,	---
964	BITSWAP = 949,	---	964	BITSWAP = 949,	---
965	BITSWAP_MMR6 = 950,	---	965	BITSWAP_MMR6 = 950,	---
966	BLEZ = 951,	---	966	BLEZ = 951,	---
967	BLEZ64 = 952,	---	967	BLEZ64 = 952,	---
968	BLEZALC = 953,	---	968	BLEZALC = 953,	---
969	BLEZALC_MMR6 = 954,	---	969	BLEZALC_MMR6 = 954,	---
970	BLEZC = 955,	---	970	BLEZC = 955,	---
971	BLEZC64 = 956,	---	971	BLEZC64 = 956,	---
972	BLEZC_MMR6 = 957,	---	972	BLEZC_MMR6 = 957,	---
973	BLEZL = 958,	---	973	BLEZL = 958,	---
974	BLEZ_MM = 959,	---	974	BLEZ_MM = 959,	---
975	BLTC = 960,	---	975	BLTC = 960,	---
976	BLTC64 = 961,	---	976	BLTC64 = 961,	---
977	BLTC_MMR6 = 962,	---	977	BLTC_MMR6 = 962,	---
978	BLTUC = 963,	---	978	BLTUC = 963,	---
979	BLTUC64 = 964,	---	979	BLTUC64 = 964,	---
980	BLTUC_MMR6 = 965,	---	980	BLTUC_MMR6 = 965,	---
981	BLTZ = 966,	---	981	BLTZ = 966,	---
982	BLTZ64 = 967,	---	982	BLTZ64 = 967,	---
983	BLTZAL = 968,	---	983	BLTZAL = 968,	---
984	BLTZALC = 969,	---	984	BLTZALC = 969,	---
985	BLTZALC_MMR6 = 970,	---	985	BLTZALC_MMR6 = 970,	---
986	BLTZALL = 971,	---	986	BLTZALL = 971,	---
987	BLTZALS_MM = 972,	---	987	BLTZALS_MM = 972,	---
988	BLTZAL_MM = 973,	---	988	BLTZAL_MM = 973,	---
989	BLTZC = 974,	---	989	BLTZC = 974,	---
990	BLTZC64 = 975,	---	990	BLTZC64 = 975,	---
991	BLTZC_MMR6 = 976,	---	991	BLTZC_MMR6 = 976,	---
992	BLTZL = 977,	---	992	BLTZL = 977,	---
993	BLTZ_MM = 978,	---	993	BLTZ_MM = 978,	---
994	BMNZI_B = 979,	---	994	BMNZI_B = 979,	---
995	BMNZ_V = 980,	---	995	BMNZ_V = 980,	---
996	BMZI_B = 981,	---	996	BMZI_B = 981,	---
997	BMZ_V = 982,	---	997	BMZ_V = 982,	---
998	BNE = 983,	---	998	BNE = 983,	---
999	BNE64 = 984,	---	999	BNE64 = 984,	---
1000	BNEC = 985,	---	1000	BNEC = 985,	---
1001	BNEC64 = 986,	---	1001	BNEC64 = 986,	---
1002	BNEC_MMR6 = 987,	---	1002	BNEC_MMR6 = 987,	---
1003	BNEGI_B = 988,	---	1003	BNEGI_B = 988,	---
1004	BNEGI_D = 989,	---	1004	BNEGI_D = 989,	---
1005	BNEGI_H = 990,	---	1005	BNEGI_H = 990,	---
1006	BNEGI_W = 991,	---	1006	BNEGI_W = 991,	---
1007	BNEG_B = 992,	---	1007	BNEG_B = 992,	---
1008	BNEG_D = 993,	---	1008	BNEG_D = 993,	---
1009	BNEG_H = 994,	---	1009	BNEG_H = 994,	---
1010	BNEG_W = 995,	---	1010	BNEG_W = 995,	---
1011	BNEL = 996,	---	1011	BNEL = 996,	---
1012	BNEZ16_MM = 997,	---	1012	BNEZ16_MM = 997,	---
1013	BNEZALC = 998,	---	1013	BNEZALC = 998,	---
1014	BNEZALC_MMR6 = 999,	---	1014	BNEZALC_MMR6 = 999,	---
1015	BNEZC = 1000,	---	1015	BNEZC = 1000,	---
1016	BNEZC16_MMR6 = 1001,	---	1016	BNEZC16_MMR6 = 1001,	---
1017	BNEZC64 = 1002,	---	1017	BNEZC64 = 1002,	---
1018	BNEZC_MM = 1003,	---	1018	BNEZC_MM = 1003,	---
1019	BNEZC_MMR6 = 1004,	---	1019	BNEZC_MMR6 = 1004,	---
1020	BNE_MM = 1005,	---	1020	BNE_MM = 1005,	---
1021	BNVC = 1006,	---	1021	BNVC = 1006,	---
1022	BNVC_MMR6 = 1007,	---	1022	BNVC_MMR6 = 1007,	---
1023	BNZ_B = 1008,	---	1023	BNZ_B = 1008,	---
1024	BNZ_D = 1009,	---	1024	BNZ_D = 1009,	---
1025	BNZ_H = 1010,	---	1025	BNZ_H = 1010,	---
1026	BNZ_V = 1011,	---	1026	BNZ_V = 1011,	---
1027	BNZ_W = 1012,	---	1027	BNZ_W = 1012,	---
1028	BOVC = 1013,	---	1028	BOVC = 1013,	---
1029	BOVC_MMR6 = 1014,	---	1029	BOVC_MMR6 = 1014,	---
1030	BPOSGE32 = 1015,	---	1030	BPOSGE32 = 1015,	---
1031	BPOSGE32C_MMR3 = 1016,	---	1031	BPOSGE32C_MMR3 = 1016,	---
1032	BPOSGE32_MM = 1017,	---	1032	BPOSGE32_MM = 1017,	---
1033	BREAK = 1018,	---	1033	BREAK = 1018,	---
1034	BREAK16_MM = 1019,	---	1034	BREAK16_MM = 1019,	---
1035	BREAK16_MMR6 = 1020,	---	1035	BREAK16_MMR6 = 1020,	---
1036	BREAK_MM = 1021,	---	1036	BREAK_MM = 1021,	---
1037	BREAK_MMR6 = 1022,	---	1037	BREAK_MMR6 = 1022,	---
1038	BSELI_B = 1023,	---	1038	BSELI_B = 1023,	---
1039	BSEL_V = 1024,	---	1039	BSEL_V = 1024,	---
1040	BSETI_B = 1025,	---	1040	BSETI_B = 1025,	---
1041	BSETI_D = 1026,	---	1041	BSETI_D = 1026,	---
1042	BSETI_H = 1027,	---	1042	BSETI_H = 1027,	---
1043	BSETI_W = 1028,	---	1043	BSETI_W = 1028,	---
1044	BSET_B = 1029,	---	1044	BSET_B = 1029,	---
1045	BSET_D = 1030,	---	1045	BSET_D = 1030,	---
1046	BSET_H = 1031,	---	1046	BSET_H = 1031,	---
1047	BSET_W = 1032,	---	1047	BSET_W = 1032,	---
1048	BZ_B = 1033,	---	1048	BZ_B = 1033,	---
1049	BZ_D = 1034,	---	1049	BZ_D = 1034,	---
1050	BZ_H = 1035,	---	1050	BZ_H = 1035,	---
1051	BZ_V = 1036,	---	1051	BZ_V = 1036,	---
1052	BZ_W = 1037,	---	1052	BZ_W = 1037,	---
1053	BeqzRxImm16 = 1038,	---	1053	BeqzRxImm16 = 1038,	---
1054	BeqzRxImmX16 = 1039,	---	1054	BeqzRxImmX16 = 1039,	---
1055	Bimm16 = 1040,	---	1055	Bimm16 = 1040,	---
1056	BimmX16 = 1041,	---	1056	BimmX16 = 1041,	---
1057	BnezRxImm16 = 1042,	---	1057	BnezRxImm16 = 1042,	---
1058	BnezRxImmX16 = 1043,	---	1058	BnezRxImmX16 = 1043,	---
1059	Break16 = 1044,	---	1059	Break16 = 1044,	---
1060	Bteqz16 = 1045,	---	1060	Bteqz16 = 1045,	---
1061	BteqzX16 = 1046,	---	1061	BteqzX16 = 1046,	---
1062	Btnez16 = 1047,	---	1062	Btnez16 = 1047,	---
1063	BtnezX16 = 1048,	---	1063	BtnezX16 = 1048,	---
1064	CACHE = 1049,	---	1064	CACHE = 1049,	---
1065	CACHEE = 1050,	---	1065	CACHEE = 1050,	---
1066	CACHEE_MM = 1051,	---	1066	CACHEE_MM = 1051,	---
1067	CACHE_MM = 1052,	---	1067	CACHE_MM = 1052,	---
1068	CACHE_MMR6 = 1053,	---	1068	CACHE_MMR6 = 1053,	---
1069	CACHE_R6 = 1054,	---	1069	CACHE_R6 = 1054,	---
1070	CEIL_L_D64 = 1055,	---	1070	CEIL_L_D64 = 1055,	---
1071	CEIL_L_D_MMR6 = 1056,	---	1071	CEIL_L_D_MMR6 = 1056,	---
1072	CEIL_L_S = 1057,	---	1072	CEIL_L_S = 1057,	---
1073	CEIL_L_S_MMR6 = 1058,	---	1073	CEIL_L_S_MMR6 = 1058,	---
1074	CEIL_W_D32 = 1059,	---	1074	CEIL_W_D32 = 1059,	---
1075	CEIL_W_D64 = 1060,	---	1075	CEIL_W_D64 = 1060,	---
1076	CEIL_W_D_MMR6 = 1061,	---	1076	CEIL_W_D_MMR6 = 1061,	---
1077	CEIL_W_MM = 1062,	---	1077	CEIL_W_MM = 1062,	---
1078	CEIL_W_S = 1063,	---	1078	CEIL_W_S = 1063,	---
1079	CEIL_W_S_MM = 1064,	---	1079	CEIL_W_S_MM = 1064,	---
1080	CEIL_W_S_MMR6 = 1065,	---	1080	CEIL_W_S_MMR6 = 1065,	---
1081	CEQI_B = 1066,	---	1081	CEQI_B = 1066,	---
1082	CEQI_D = 1067,	---	1082	CEQI_D = 1067,	---
1083	CEQI_H = 1068,	---	1083	CEQI_H = 1068,	---
1084	CEQI_W = 1069,	---	1084	CEQI_W = 1069,	---
1085	CEQ_B = 1070,	---	1085	CEQ_B = 1070,	---
1086	CEQ_D = 1071,	---	1086	CEQ_D = 1071,	---
1087	CEQ_H = 1072,	---	1087	CEQ_H = 1072,	---
1088	CEQ_W = 1073,	---	1088	CEQ_W = 1073,	---
1089	CFC1 = 1074,	---	1089	CFC1 = 1074,	---
1090	CFC1_MM = 1075,	---	1090	CFC1_MM = 1075,	---
1091	CFC2_MM = 1076,	---	1091	CFC2_MM = 1076,	---
1092	CFCMSA = 1077,	---	1092	CFCMSA = 1077,	---
1093	CINS = 1078,	---	1093	CINS = 1078,	---
1094	CINS32 = 1079,	---	1094	CINS32 = 1079,	---
1095	CINS64_32 = 1080,	---	1095	CINS64_32 = 1080,	---
1096	CINS_i32 = 1081,	---	1096	CINS_i32 = 1081,	---
1097	CLASS_D = 1082,	---	1097	CLASS_D = 1082,	---
1098	CLASS_D_MMR6 = 1083,	---	1098	CLASS_D_MMR6 = 1083,	---
1099	CLASS_S = 1084,	---	1099	CLASS_S = 1084,	---
1100	CLASS_S_MMR6 = 1085,	---	1100	CLASS_S_MMR6 = 1085,	---
1101	CLEI_S_B = 1086,	---	1101	CLEI_S_B = 1086,	---
1102	CLEI_S_D = 1087,	---	1102	CLEI_S_D = 1087,	---
1103	CLEI_S_H = 1088,	---	1103	CLEI_S_H = 1088,	---
1104	CLEI_S_W = 1089,	---	1104	CLEI_S_W = 1089,	---
1105	CLEI_U_B = 1090,	---	1105	CLEI_U_B = 1090,	---
1106	CLEI_U_D = 1091,	---	1106	CLEI_U_D = 1091,	---
1107	CLEI_U_H = 1092,	---	1107	CLEI_U_H = 1092,	---
1108	CLEI_U_W = 1093,	---	1108	CLEI_U_W = 1093,	---
1109	CLE_S_B = 1094,	---	1109	CLE_S_B = 1094,	---
1110	CLE_S_D = 1095,	---	1110	CLE_S_D = 1095,	---
1111	CLE_S_H = 1096,	---	1111	CLE_S_H = 1096,	---
1112	CLE_S_W = 1097,	---	1112	CLE_S_W = 1097,	---
1113	CLE_U_B = 1098,	---	1113	CLE_U_B = 1098,	---
1114	CLE_U_D = 1099,	---	1114	CLE_U_D = 1099,	---
1115	CLE_U_H = 1100,	---	1115	CLE_U_H = 1100,	---
1116	CLE_U_W = 1101,	---	1116	CLE_U_W = 1101,	---
1117	CLO = 1102,	---	1117	CLO = 1102,	---
1118	CLO_MM = 1103,	---	1118	CLO_MM = 1103,	---
1119	CLO_MMR6 = 1104,	---	1119	CLO_MMR6 = 1104,	---
1120	CLO_R6 = 1105,	---	1120	CLO_R6 = 1105,	---
1121	CLTI_S_B = 1106,	---	1121	CLTI_S_B = 1106,	---
1122	CLTI_S_D = 1107,	---	1122	CLTI_S_D = 1107,	---
1123	CLTI_S_H = 1108,	---	1123	CLTI_S_H = 1108,	---
1124	CLTI_S_W = 1109,	---	1124	CLTI_S_W = 1109,	---
1125	CLTI_U_B = 1110,	---	1125	CLTI_U_B = 1110,	---
1126	CLTI_U_D = 1111,	---	1126	CLTI_U_D = 1111,	---
1127	CLTI_U_H = 1112,	---	1127	CLTI_U_H = 1112,	---
1128	CLTI_U_W = 1113,	---	1128	CLTI_U_W = 1113,	---
1129	CLT_S_B = 1114,	---	1129	CLT_S_B = 1114,	---
1130	CLT_S_D = 1115,	---	1130	CLT_S_D = 1115,	---
1131	CLT_S_H = 1116,	---	1131	CLT_S_H = 1116,	---
1132	CLT_S_W = 1117,	---	1132	CLT_S_W = 1117,	---
1133	CLT_U_B = 1118,	---	1133	CLT_U_B = 1118,	---
1134	CLT_U_D = 1119,	---	1134	CLT_U_D = 1119,	---
1135	CLT_U_H = 1120,	---	1135	CLT_U_H = 1120,	---
1136	CLT_U_W = 1121,	---	1136	CLT_U_W = 1121,	---
1137	CLZ = 1122,	---	1137	CLZ = 1122,	---
1138	CLZ_MM = 1123,	---	1138	CLZ_MM = 1123,	---
1139	CLZ_MMR6 = 1124,	---	1139	CLZ_MMR6 = 1124,	---
1140	CLZ_R6 = 1125,	---	1140	CLZ_R6 = 1125,	---
1141	CMPGDU_EQ_QB = 1126,	---	1141	CMPGDU_EQ_QB = 1126,	---
1142	CMPGDU_EQ_QB_MMR2 = 1127,	---	1142	CMPGDU_EQ_QB_MMR2 = 1127,	---
1143	CMPGDU_LE_QB = 1128,	---	1143	CMPGDU_LE_QB = 1128,	---
1144	CMPGDU_LE_QB_MMR2 = 1129,	---	1144	CMPGDU_LE_QB_MMR2 = 1129,	---
1145	CMPGDU_LT_QB = 1130,	---	1145	CMPGDU_LT_QB = 1130,	---
1146	CMPGDU_LT_QB_MMR2 = 1131,	---	1146	CMPGDU_LT_QB_MMR2 = 1131,	---
1147	CMPGU_EQ_QB = 1132,	---	1147	CMPGU_EQ_QB = 1132,	---
1148	CMPGU_EQ_QB_MM = 1133,	---	1148	CMPGU_EQ_QB_MM = 1133,	---
1149	CMPGU_LE_QB = 1134,	---	1149	CMPGU_LE_QB = 1134,	---
1150	CMPGU_LE_QB_MM = 1135,	---	1150	CMPGU_LE_QB_MM = 1135,	---
1151	CMPGU_LT_QB = 1136,	---	1151	CMPGU_LT_QB = 1136,	---
1152	CMPGU_LT_QB_MM = 1137,	---	1152	CMPGU_LT_QB_MM = 1137,	---
1153	CMPU_EQ_QB = 1138,	---	1153	CMPU_EQ_QB = 1138,	---
1154	CMPU_EQ_QB_MM = 1139,	---	1154	CMPU_EQ_QB_MM = 1139,	---
1155	CMPU_LE_QB = 1140,	---	1155	CMPU_LE_QB = 1140,	---
1156	CMPU_LE_QB_MM = 1141,	---	1156	CMPU_LE_QB_MM = 1141,	---
1157	CMPU_LT_QB = 1142,	---	1157	CMPU_LT_QB = 1142,	---
1158	CMPU_LT_QB_MM = 1143,	---	1158	CMPU_LT_QB_MM = 1143,	---
1159	CMP_AF_D_MMR6 = 1144,	---	1159	CMP_AF_D_MMR6 = 1144,	---
1160	CMP_AF_S_MMR6 = 1145,	---	1160	CMP_AF_S_MMR6 = 1145,	---
1161	CMP_EQ_D = 1146,	---	1161	CMP_EQ_D = 1146,	---
1162	CMP_EQ_D_MMR6 = 1147,	---	1162	CMP_EQ_D_MMR6 = 1147,	---
1163	CMP_EQ_PH = 1148,	---	1163	CMP_EQ_PH = 1148,	---
1164	CMP_EQ_PH_MM = 1149,	---	1164	CMP_EQ_PH_MM = 1149,	---
1165	CMP_EQ_S = 1150,	---	1165	CMP_EQ_S = 1150,	---
1166	CMP_EQ_S_MMR6 = 1151,	---	1166	CMP_EQ_S_MMR6 = 1151,	---
1167	CMP_F_D = 1152,	---	1167	CMP_F_D = 1152,	---
1168	CMP_F_S = 1153,	---	1168	CMP_F_S = 1153,	---
1169	CMP_LE_D = 1154,	---	1169	CMP_LE_D = 1154,	---
1170	CMP_LE_D_MMR6 = 1155,	---	1170	CMP_LE_D_MMR6 = 1155,	---
1171	CMP_LE_PH = 1156,	---	1171	CMP_LE_PH = 1156,	---
1172	CMP_LE_PH_MM = 1157,	---	1172	CMP_LE_PH_MM = 1157,	---
1173	CMP_LE_S = 1158,	---	1173	CMP_LE_S = 1158,	---
1174	CMP_LE_S_MMR6 = 1159,	---	1174	CMP_LE_S_MMR6 = 1159,	---
1175	CMP_LT_D = 1160,	---	1175	CMP_LT_D = 1160,	---
1176	CMP_LT_D_MMR6 = 1161,	---	1176	CMP_LT_D_MMR6 = 1161,	---
1177	CMP_LT_PH = 1162,	---	1177	CMP_LT_PH = 1162,	---
1178	CMP_LT_PH_MM = 1163,	---	1178	CMP_LT_PH_MM = 1163,	---
1179	CMP_LT_S = 1164,	---	1179	CMP_LT_S = 1164,	---
1180	CMP_LT_S_MMR6 = 1165,	---	1180	CMP_LT_S_MMR6 = 1165,	---
1181	CMP_SAF_D = 1166,	---	1181	CMP_SAF_D = 1166,	---
1182	CMP_SAF_D_MMR6 = 1167,	---	1182	CMP_SAF_D_MMR6 = 1167,	---
1183	CMP_SAF_S = 1168,	---	1183	CMP_SAF_S = 1168,	---
1184	CMP_SAF_S_MMR6 = 1169,	---	1184	CMP_SAF_S_MMR6 = 1169,	---
1185	CMP_SEQ_D = 1170,	---	1185	CMP_SEQ_D = 1170,	---
1186	CMP_SEQ_D_MMR6 = 1171,	---	1186	CMP_SEQ_D_MMR6 = 1171,	---
1187	CMP_SEQ_S = 1172,	---	1187	CMP_SEQ_S = 1172,	---
1188	CMP_SEQ_S_MMR6 = 1173,	---	1188	CMP_SEQ_S_MMR6 = 1173,	---
1189	CMP_SLE_D = 1174,	---	1189	CMP_SLE_D = 1174,	---
1190	CMP_SLE_D_MMR6 = 1175,	---	1190	CMP_SLE_D_MMR6 = 1175,	---
1191	CMP_SLE_S = 1176,	---	1191	CMP_SLE_S = 1176,	---
1192	CMP_SLE_S_MMR6 = 1177,	---	1192	CMP_SLE_S_MMR6 = 1177,	---
1193	CMP_SLT_D = 1178,	---	1193	CMP_SLT_D = 1178,	---
1194	CMP_SLT_D_MMR6 = 1179,	---	1194	CMP_SLT_D_MMR6 = 1179,	---
1195	CMP_SLT_S = 1180,	---	1195	CMP_SLT_S = 1180,	---
1196	CMP_SLT_S_MMR6 = 1181,	---	1196	CMP_SLT_S_MMR6 = 1181,	---
1197	CMP_SUEQ_D = 1182,	---	1197	CMP_SUEQ_D = 1182,	---
1198	CMP_SUEQ_D_MMR6 = 1183,	---	1198	CMP_SUEQ_D_MMR6 = 1183,	---
1199	CMP_SUEQ_S = 1184,	---	1199	CMP_SUEQ_S = 1184,	---
1200	CMP_SUEQ_S_MMR6 = 1185,	---	1200	CMP_SUEQ_S_MMR6 = 1185,	---
1201	CMP_SULE_D = 1186,	---	1201	CMP_SULE_D = 1186,	---
1202	CMP_SULE_D_MMR6 = 1187,	---	1202	CMP_SULE_D_MMR6 = 1187,	---
1203	CMP_SULE_S = 1188,	---	1203	CMP_SULE_S = 1188,	---
1204	CMP_SULE_S_MMR6 = 1189,	---	1204	CMP_SULE_S_MMR6 = 1189,	---
1205	CMP_SULT_D = 1190,	---	1205	CMP_SULT_D = 1190,	---
1206	CMP_SULT_D_MMR6 = 1191,	---	1206	CMP_SULT_D_MMR6 = 1191,	---
1207	CMP_SULT_S = 1192,	---	1207	CMP_SULT_S = 1192,	---
1208	CMP_SULT_S_MMR6 = 1193,	---	1208	CMP_SULT_S_MMR6 = 1193,	---
1209	CMP_SUN_D = 1194,	---	1209	CMP_SUN_D = 1194,	---
1210	CMP_SUN_D_MMR6 = 1195,	---	1210	CMP_SUN_D_MMR6 = 1195,	---
1211	CMP_SUN_S = 1196,	---	1211	CMP_SUN_S = 1196,	---
1212	CMP_SUN_S_MMR6 = 1197,	---	1212	CMP_SUN_S_MMR6 = 1197,	---
1213	CMP_UEQ_D = 1198,	---	1213	CMP_UEQ_D = 1198,	---
1214	CMP_UEQ_D_MMR6 = 1199,	---	1214	CMP_UEQ_D_MMR6 = 1199,	---
1215	CMP_UEQ_S = 1200,	---	1215	CMP_UEQ_S = 1200,	---
1216	CMP_UEQ_S_MMR6 = 1201,	---	1216	CMP_UEQ_S_MMR6 = 1201,	---
1217	CMP_ULE_D = 1202,	---	1217	CMP_ULE_D = 1202,	---
1218	CMP_ULE_D_MMR6 = 1203,	---	1218	CMP_ULE_D_MMR6 = 1203,	---
1219	CMP_ULE_S = 1204,	---	1219	CMP_ULE_S = 1204,	---
1220	CMP_ULE_S_MMR6 = 1205,	---	1220	CMP_ULE_S_MMR6 = 1205,	---
1221	CMP_ULT_D = 1206,	---	1221	CMP_ULT_D = 1206,	---
1222	CMP_ULT_D_MMR6 = 1207,	---	1222	CMP_ULT_D_MMR6 = 1207,	---
1223	CMP_ULT_S = 1208,	---	1223	CMP_ULT_S = 1208,	---
1224	CMP_ULT_S_MMR6 = 1209,	---	1224	CMP_ULT_S_MMR6 = 1209,	---
1225	CMP_UN_D = 1210,	---	1225	CMP_UN_D = 1210,	---
1226	CMP_UN_D_MMR6 = 1211,	---	1226	CMP_UN_D_MMR6 = 1211,	---
1227	CMP_UN_S = 1212,	---	1227	CMP_UN_S = 1212,	---
1228	CMP_UN_S_MMR6 = 1213,	---	1228	CMP_UN_S_MMR6 = 1213,	---
1229	COPY_S_B = 1214,	---	1229	COPY_S_B = 1214,	---
1230	COPY_S_D = 1215,	---	1230	COPY_S_D = 1215,	---
1231	COPY_S_H = 1216,	---	1231	COPY_S_H = 1216,	---
1232	COPY_S_W = 1217,	---	1232	COPY_S_W = 1217,	---
1233	COPY_U_B = 1218,	---	1233	COPY_U_B = 1218,	---
1234	COPY_U_H = 1219,	---	1234	COPY_U_H = 1219,	---
1235	COPY_U_W = 1220,	---	1235	COPY_U_W = 1220,	---
1236	CRC32B = 1221,	---	1236	CRC32B = 1221,	---
1237	CRC32CB = 1222,	---	1237	CRC32CB = 1222,	---
1238	CRC32CD = 1223,	---	1238	CRC32CD = 1223,	---
1239	CRC32CH = 1224,	---	1239	CRC32CH = 1224,	---
1240	CRC32CW = 1225,	---	1240	CRC32CW = 1225,	---
1241	CRC32D = 1226,	---	1241	CRC32D = 1226,	---
1242	CRC32H = 1227,	---	1242	CRC32H = 1227,	---
1243	CRC32W = 1228,	---	1243	CRC32W = 1228,	---
1244	CTC1 = 1229,	---	1244	CTC1 = 1229,	---
1245	CTC1_MM = 1230,	---	1245	CTC1_MM = 1230,	---
1246	CTC2_MM = 1231,	---	1246	CTC2_MM = 1231,	---
1247	CTCMSA = 1232,	---	1247	CTCMSA = 1232,	---
1248	CVT_D32_S = 1233,	---	1248	CVT_D32_S = 1233,	---
1249	CVT_D32_S_MM = 1234,	---	1249	CVT_D32_S_MM = 1234,	---
1250	CVT_D32_W = 1235,	---	1250	CVT_D32_W = 1235,	---
1251	CVT_D32_W_MM = 1236,	---	1251	CVT_D32_W_MM = 1236,	---
1252	CVT_D64_L = 1237,	---	1252	CVT_D64_L = 1237,	---
1253	CVT_D64_S = 1238,	---	1253	CVT_D64_S = 1238,	---
1254	CVT_D64_S_MM = 1239,	---	1254	CVT_D64_S_MM = 1239,	---
1255	CVT_D64_W = 1240,	---	1255	CVT_D64_W = 1240,	---
1256	CVT_D64_W_MM = 1241,	---	1256	CVT_D64_W_MM = 1241,	---
1257	CVT_D_L_MMR6 = 1242,	---	1257	CVT_D_L_MMR6 = 1242,	---
1258	CVT_L_D64 = 1243,	---	1258	CVT_L_D64 = 1243,	---
1259	CVT_L_D64_MM = 1244,	---	1259	CVT_L_D64_MM = 1244,	---
1260	CVT_L_D_MMR6 = 1245,	---	1260	CVT_L_D_MMR6 = 1245,	---
1261	CVT_L_S = 1246,	---	1261	CVT_L_S = 1246,	---
1262	CVT_L_S_MM = 1247,	---	1262	CVT_L_S_MM = 1247,	---
1263	CVT_L_S_MMR6 = 1248,	---	1263	CVT_L_S_MMR6 = 1248,	---
1264	CVT_PS_PW64 = 1249,	---	1264	CVT_PS_PW64 = 1249,	---
1265	CVT_PS_S64 = 1250,	---	1265	CVT_PS_S64 = 1250,	---
1266	CVT_PW_PS64 = 1251,	---	1266	CVT_PW_PS64 = 1251,	---
1267	CVT_S_D32 = 1252,	---	1267	CVT_S_D32 = 1252,	---
1268	CVT_S_D32_MM = 1253,	---	1268	CVT_S_D32_MM = 1253,	---
1269	CVT_S_D64 = 1254,	---	1269	CVT_S_D64 = 1254,	---
1270	CVT_S_D64_MM = 1255,	---	1270	CVT_S_D64_MM = 1255,	---
1271	CVT_S_L = 1256,	---	1271	CVT_S_L = 1256,	---
1272	CVT_S_L_MMR6 = 1257,	---	1272	CVT_S_L_MMR6 = 1257,	---
1273	CVT_S_PL64 = 1258,	---	1273	CVT_S_PL64 = 1258,	---
1274	CVT_S_PU64 = 1259,	---	1274	CVT_S_PU64 = 1259,	---
1275	CVT_S_W = 1260,	---	1275	CVT_S_W = 1260,	---
1276	CVT_S_W_MM = 1261,	---	1276	CVT_S_W_MM = 1261,	---
1277	CVT_S_W_MMR6 = 1262,	---	1277	CVT_S_W_MMR6 = 1262,	---
1278	CVT_W_D32 = 1263,	---	1278	CVT_W_D32 = 1263,	---
1279	CVT_W_D32_MM = 1264,	---	1279	CVT_W_D32_MM = 1264,	---
1280	CVT_W_D64 = 1265,	---	1280	CVT_W_D64 = 1265,	---
1281	CVT_W_D64_MM = 1266,	---	1281	CVT_W_D64_MM = 1266,	---
1282	CVT_W_S = 1267,	---	1282	CVT_W_S = 1267,	---
1283	CVT_W_S_MM = 1268,	---	1283	CVT_W_S_MM = 1268,	---
1284	CVT_W_S_MMR6 = 1269,	---	1284	CVT_W_S_MMR6 = 1269,	---
1285	C_EQ_D32 = 1270,	---	1285	C_EQ_D32 = 1270,	---
1286	C_EQ_D32_MM = 1271,	---	1286	C_EQ_D32_MM = 1271,	---
1287	C_EQ_D64 = 1272,	---	1287	C_EQ_D64 = 1272,	---
1288	C_EQ_D64_MM = 1273,	---	1288	C_EQ_D64_MM = 1273,	---
1289	C_EQ_S = 1274,	---	1289	C_EQ_S = 1274,	---
1290	C_EQ_S_MM = 1275,	---	1290	C_EQ_S_MM = 1275,	---
1291	C_F_D32 = 1276,	---	1291	C_F_D32 = 1276,	---
1292	C_F_D32_MM = 1277,	---	1292	C_F_D32_MM = 1277,	---
1293	C_F_D64 = 1278,	---	1293	C_F_D64 = 1278,	---
1294	C_F_D64_MM = 1279,	---	1294	C_F_D64_MM = 1279,	---
1295	C_F_S = 1280,	---	1295	C_F_S = 1280,	---
1296	C_F_S_MM = 1281,	---	1296	C_F_S_MM = 1281,	---
1297	C_LE_D32 = 1282,	---	1297	C_LE_D32 = 1282,	---
1298	C_LE_D32_MM = 1283,	---	1298	C_LE_D32_MM = 1283,	---
1299	C_LE_D64 = 1284,	---	1299	C_LE_D64 = 1284,	---
1300	C_LE_D64_MM = 1285,	---	1300	C_LE_D64_MM = 1285,	---
1301	C_LE_S = 1286,	---	1301	C_LE_S = 1286,	---
1302	C_LE_S_MM = 1287,	---	1302	C_LE_S_MM = 1287,	---
1303	C_LT_D32 = 1288,	---	1303	C_LT_D32 = 1288,	---
1304	C_LT_D32_MM = 1289,	---	1304	C_LT_D32_MM = 1289,	---
1305	C_LT_D64 = 1290,	---	1305	C_LT_D64 = 1290,	---
1306	C_LT_D64_MM = 1291,	---	1306	C_LT_D64_MM = 1291,	---
1307	C_LT_S = 1292,	---	1307	C_LT_S = 1292,	---
1308	C_LT_S_MM = 1293,	---	1308	C_LT_S_MM = 1293,	---
1309	C_NGE_D32 = 1294,	---	1309	C_NGE_D32 = 1294,	---
1310	C_NGE_D32_MM = 1295,	---	1310	C_NGE_D32_MM = 1295,	---
1311	C_NGE_D64 = 1296,	---	1311	C_NGE_D64 = 1296,	---
1312	C_NGE_D64_MM = 1297,	---	1312	C_NGE_D64_MM = 1297,	---
1313	C_NGE_S = 1298,	---	1313	C_NGE_S = 1298,	---
1314	C_NGE_S_MM = 1299,	---	1314	C_NGE_S_MM = 1299,	---
1315	C_NGLE_D32 = 1300,	---	1315	C_NGLE_D32 = 1300,	---
1316	C_NGLE_D32_MM = 1301,	---	1316	C_NGLE_D32_MM = 1301,	---
1317	C_NGLE_D64 = 1302,	---	1317	C_NGLE_D64 = 1302,	---
1318	C_NGLE_D64_MM = 1303,	---	1318	C_NGLE_D64_MM = 1303,	---
1319	C_NGLE_S = 1304,	---	1319	C_NGLE_S = 1304,	---
1320	C_NGLE_S_MM = 1305,	---	1320	C_NGLE_S_MM = 1305,	---
1321	C_NGL_D32 = 1306,	---	1321	C_NGL_D32 = 1306,	---
1322	C_NGL_D32_MM = 1307,	---	1322	C_NGL_D32_MM = 1307,	---
1323	C_NGL_D64 = 1308,	---	1323	C_NGL_D64 = 1308,	---
1324	C_NGL_D64_MM = 1309,	---	1324	C_NGL_D64_MM = 1309,	---
1325	C_NGL_S = 1310,	---	1325	C_NGL_S = 1310,	---
1326	C_NGL_S_MM = 1311,	---	1326	C_NGL_S_MM = 1311,	---
1327	C_NGT_D32 = 1312,	---	1327	C_NGT_D32 = 1312,	---
1328	C_NGT_D32_MM = 1313,	---	1328	C_NGT_D32_MM = 1313,	---
1329	C_NGT_D64 = 1314,	---	1329	C_NGT_D64 = 1314,	---
1330	C_NGT_D64_MM = 1315,	---	1330	C_NGT_D64_MM = 1315,	---
1331	C_NGT_S = 1316,	---	1331	C_NGT_S = 1316,	---
1332	C_NGT_S_MM = 1317,	---	1332	C_NGT_S_MM = 1317,	---
1333	C_OLE_D32 = 1318,	---	1333	C_OLE_D32 = 1318,	---
1334	C_OLE_D32_MM = 1319,	---	1334	C_OLE_D32_MM = 1319,	---
1335	C_OLE_D64 = 1320,	---	1335	C_OLE_D64 = 1320,	---
1336	C_OLE_D64_MM = 1321,	---	1336	C_OLE_D64_MM = 1321,	---
1337	C_OLE_S = 1322,	---	1337	C_OLE_S = 1322,	---
1338	C_OLE_S_MM = 1323,	---	1338	C_OLE_S_MM = 1323,	---
1339	C_OLT_D32 = 1324,	---	1339	C_OLT_D32 = 1324,	---
1340	C_OLT_D32_MM = 1325,	---	1340	C_OLT_D32_MM = 1325,	---
1341	C_OLT_D64 = 1326,	---	1341	C_OLT_D64 = 1326,	---
1342	C_OLT_D64_MM = 1327,	---	1342	C_OLT_D64_MM = 1327,	---
1343	C_OLT_S = 1328,	---	1343	C_OLT_S = 1328,	---
1344	C_OLT_S_MM = 1329,	---	1344	C_OLT_S_MM = 1329,	---
1345	C_SEQ_D32 = 1330,	---	1345	C_SEQ_D32 = 1330,	---
1346	C_SEQ_D32_MM = 1331,	---	1346	C_SEQ_D32_MM = 1331,	---
1347	C_SEQ_D64 = 1332,	---	1347	C_SEQ_D64 = 1332,	---
1348	C_SEQ_D64_MM = 1333,	---	1348	C_SEQ_D64_MM = 1333,	---
1349	C_SEQ_S = 1334,	---	1349	C_SEQ_S = 1334,	---
1350	C_SEQ_S_MM = 1335,	---	1350	C_SEQ_S_MM = 1335,	---
1351	C_SF_D32 = 1336,	---	1351	C_SF_D32 = 1336,	---
1352	C_SF_D32_MM = 1337,	---	1352	C_SF_D32_MM = 1337,	---
1353	C_SF_D64 = 1338,	---	1353	C_SF_D64 = 1338,	---
1354	C_SF_D64_MM = 1339,	---	1354	C_SF_D64_MM = 1339,	---
1355	C_SF_S = 1340,	---	1355	C_SF_S = 1340,	---
1356	C_SF_S_MM = 1341,	---	1356	C_SF_S_MM = 1341,	---
1357	C_UEQ_D32 = 1342,	---	1357	C_UEQ_D32 = 1342,	---
1358	C_UEQ_D32_MM = 1343,	---	1358	C_UEQ_D32_MM = 1343,	---
1359	C_UEQ_D64 = 1344,	---	1359	C_UEQ_D64 = 1344,	---
1360	C_UEQ_D64_MM = 1345,	---	1360	C_UEQ_D64_MM = 1345,	---
1361	C_UEQ_S = 1346,	---	1361	C_UEQ_S = 1346,	---
1362	C_UEQ_S_MM = 1347,	---	1362	C_UEQ_S_MM = 1347,	---
1363	C_ULE_D32 = 1348,	---	1363	C_ULE_D32 = 1348,	---
1364	C_ULE_D32_MM = 1349,	---	1364	C_ULE_D32_MM = 1349,	---
1365	C_ULE_D64 = 1350,	---	1365	C_ULE_D64 = 1350,	---
1366	C_ULE_D64_MM = 1351,	---	1366	C_ULE_D64_MM = 1351,	---
1367	C_ULE_S = 1352,	---	1367	C_ULE_S = 1352,	---
1368	C_ULE_S_MM = 1353,	---	1368	C_ULE_S_MM = 1353,	---
1369	C_ULT_D32 = 1354,	---	1369	C_ULT_D32 = 1354,	---
1370	C_ULT_D32_MM = 1355,	---	1370	C_ULT_D32_MM = 1355,	---
1371	C_ULT_D64 = 1356,	---	1371	C_ULT_D64 = 1356,	---
1372	C_ULT_D64_MM = 1357,	---	1372	C_ULT_D64_MM = 1357,	---
1373	C_ULT_S = 1358,	---	1373	C_ULT_S = 1358,	---
1374	C_ULT_S_MM = 1359,	---	1374	C_ULT_S_MM = 1359,	---
1375	C_UN_D32 = 1360,	---	1375	C_UN_D32 = 1360,	---
1376	C_UN_D32_MM = 1361,	---	1376	C_UN_D32_MM = 1361,	---
1377	C_UN_D64 = 1362,	---	1377	C_UN_D64 = 1362,	---
1378	C_UN_D64_MM = 1363,	---	1378	C_UN_D64_MM = 1363,	---
1379	C_UN_S = 1364,	---	1379	C_UN_S = 1364,	---
1380	C_UN_S_MM = 1365,	---	1380	C_UN_S_MM = 1365,	---
1381	CmpRxRy16 = 1366,	---	1381	CmpRxRy16 = 1366,	---
1382	CmpiRxImm16 = 1367,	---	1382	CmpiRxImm16 = 1367,	---
1383	CmpiRxImmX16 = 1368,	---	1383	CmpiRxImmX16 = 1368,	---
1384	DADD = 1369,	---	1384	DADD = 1369,	---
1385	DADDi = 1370,	---	1385	DADDi = 1370,	---
1386	DADDiu = 1371,	---	1386	DADDiu = 1371,	---
1387	DADDu = 1372,	---	1387	DADDu = 1372,	---
1388	DAHI = 1373,	---	1388	DAHI = 1373,	---
1389	DALIGN = 1374,	---	1389	DALIGN = 1374,	---
1390	DATI = 1375,	---	1390	DATI = 1375,	---
1391	DAUI = 1376,	---	1391	DAUI = 1376,	---
1392	DBITSWAP = 1377,	---	1392	DBITSWAP = 1377,	---
1393	DCLO = 1378,	---	1393	DCLO = 1378,	---
1394	DCLO_R6 = 1379,	---	1394	DCLO_R6 = 1379,	---
1395	DCLZ = 1380,	---	1395	DCLZ = 1380,	---
1396	DCLZ_R6 = 1381,	---	1396	DCLZ_R6 = 1381,	---
1397	DDIV = 1382,	---	1397	DDIV = 1382,	---
1398	DDIVU = 1383,	---	1398	DDIVU = 1383,	---
1399	DERET = 1384,	---	1399	DERET = 1384,	---
1400	DERET_MM = 1385,	---	1400	DERET_MM = 1385,	---
1401	DERET_MMR6 = 1386,	---	1401	DERET_MMR6 = 1386,	---
1402	DEXT = 1387,	---	1402	DEXT = 1387,	---
1403	DEXT64_32 = 1388,	---	1403	DEXT64_32 = 1388,	---
1404	DEXTM = 1389,	---	1404	DEXTM = 1389,	---
1405	DEXTU = 1390,	---	1405	DEXTU = 1390,	---
1406	DI = 1391,	---	1406	DI = 1391,	---
1407	DINS = 1392,	---	1407	DINS = 1392,	---
1408	DINSM = 1393,	---	1408	DINSM = 1393,	---
1409	DINSU = 1394,	---	1409	DINSU = 1394,	---
1410	DIV = 1395,	---	1410	DIV = 1395,	---
1411	DIVU = 1396,	---	1411	DIVU = 1396,	---
1412	DIVU_MMR6 = 1397,	---	1412	DIVU_MMR6 = 1397,	---
1413	DIV_MMR6 = 1398,	---	1413	DIV_MMR6 = 1398,	---
1414	DIV_S_B = 1399,	---	1414	DIV_S_B = 1399,	---
1415	DIV_S_D = 1400,	---	1415	DIV_S_D = 1400,	---
1416	DIV_S_H = 1401,	---	1416	DIV_S_H = 1401,	---
1417	DIV_S_W = 1402,	---	1417	DIV_S_W = 1402,	---
1418	DIV_U_B = 1403,	---	1418	DIV_U_B = 1403,	---
1419	DIV_U_D = 1404,	---	1419	DIV_U_D = 1404,	---
1420	DIV_U_H = 1405,	---	1420	DIV_U_H = 1405,	---
1421	DIV_U_W = 1406,	---	1421	DIV_U_W = 1406,	---
1422	DI_MM = 1407,	---	1422	DI_MM = 1407,	---
1423	DI_MMR6 = 1408,	---	1423	DI_MMR6 = 1408,	---
1424	DLSA = 1409,	---	1424	DLSA = 1409,	---
1425	DLSA_R6 = 1410,	---	1425	DLSA_R6 = 1410,	---
1426	DMFC0 = 1411,	---	1426	DMFC0 = 1411,	---
1427	DMFC1 = 1412,	---	1427	DMFC1 = 1412,	---
1428	DMFC2 = 1413,	---	1428	DMFC2 = 1413,	---
1429	DMFC2_OCTEON = 1414,	---	1429	DMFC2_OCTEON = 1414,	---
1430	DMFGC0 = 1415,	---	1430	DMFGC0 = 1415,	---
1431	DMOD = 1416,	---	1431	DMOD = 1416,	---
1432	DMODU = 1417,	---	1432	DMODU = 1417,	---
1433	DMT = 1418,	---	1433	DMT = 1418,	---
1434	DMTC0 = 1419,	---	1434	DMTC0 = 1419,	---
1435	DMTC1 = 1420,	---	1435	DMTC1 = 1420,	---
1436	DMTC2 = 1421,	---	1436	DMTC2 = 1421,	---
1437	DMTC2_OCTEON = 1422,	---	1437	DMTC2_OCTEON = 1422,	---
1438	DMTGC0 = 1423,	---	1438	DMTGC0 = 1423,	---
1439	DMUH = 1424,	---	1439	DMUH = 1424,	---
1440	DMUHU = 1425,	---	1440	DMUHU = 1425,	---
1441	DMUL = 1426,	---	1441	DMUL = 1426,	---
1442	DMULT = 1427,	---	1442	DMULT = 1427,	---
1443	DMULTu = 1428,	---	1443	DMULTu = 1428,	---
1444	DMULU = 1429,	---	1444	DMULU = 1429,	---
1445	DMUL_R6 = 1430,	---	1445	DMUL_R6 = 1430,	---
1446	DOTP_S_D = 1431,	---	1446	DOTP_S_D = 1431,	---
1447	DOTP_S_H = 1432,	---	1447	DOTP_S_H = 1432,	---
1448	DOTP_S_W = 1433,	---	1448	DOTP_S_W = 1433,	---
1449	DOTP_U_D = 1434,	---	1449	DOTP_U_D = 1434,	---
1450	DOTP_U_H = 1435,	---	1450	DOTP_U_H = 1435,	---
1451	DOTP_U_W = 1436,	---	1451	DOTP_U_W = 1436,	---
1452	DPADD_S_D = 1437,	---	1452	DPADD_S_D = 1437,	---
1453	DPADD_S_H = 1438,	---	1453	DPADD_S_H = 1438,	---
1454	DPADD_S_W = 1439,	---	1454	DPADD_S_W = 1439,	---
1455	DPADD_U_D = 1440,	---	1455	DPADD_U_D = 1440,	---
1456	DPADD_U_H = 1441,	---	1456	DPADD_U_H = 1441,	---
1457	DPADD_U_W = 1442,	---	1457	DPADD_U_W = 1442,	---
1458	DPAQX_SA_W_PH = 1443,	---	1458	DPAQX_SA_W_PH = 1443,	---
1459	DPAQX_SA_W_PH_MMR2 = 1444,	---	1459	DPAQX_SA_W_PH_MMR2 = 1444,	---
1460	DPAQX_S_W_PH = 1445,	---	1460	DPAQX_S_W_PH = 1445,	---
1461	DPAQX_S_W_PH_MMR2 = 1446,	---	1461	DPAQX_S_W_PH_MMR2 = 1446,	---
1462	DPAQ_SA_L_W = 1447,	---	1462	DPAQ_SA_L_W = 1447,	---
1463	DPAQ_SA_L_W_MM = 1448,	---	1463	DPAQ_SA_L_W_MM = 1448,	---
1464	DPAQ_S_W_PH = 1449,	---	1464	DPAQ_S_W_PH = 1449,	---
1465	DPAQ_S_W_PH_MM = 1450,	---	1465	DPAQ_S_W_PH_MM = 1450,	---
1466	DPAU_H_QBL = 1451,	---	1466	DPAU_H_QBL = 1451,	---
1467	DPAU_H_QBL_MM = 1452,	---	1467	DPAU_H_QBL_MM = 1452,	---
1468	DPAU_H_QBR = 1453,	---	1468	DPAU_H_QBR = 1453,	---
1469	DPAU_H_QBR_MM = 1454,	---	1469	DPAU_H_QBR_MM = 1454,	---
1470	DPAX_W_PH = 1455,	---	1470	DPAX_W_PH = 1455,	---
1471	DPAX_W_PH_MMR2 = 1456,	---	1471	DPAX_W_PH_MMR2 = 1456,	---
1472	DPA_W_PH = 1457,	---	1472	DPA_W_PH = 1457,	---
1473	DPA_W_PH_MMR2 = 1458,	---	1473	DPA_W_PH_MMR2 = 1458,	---
1474	DPOP = 1459,	---	1474	DPOP = 1459,	---
1475	DPSQX_SA_W_PH = 1460,	---	1475	DPSQX_SA_W_PH = 1460,	---
1476	DPSQX_SA_W_PH_MMR2 = 1461,	---	1476	DPSQX_SA_W_PH_MMR2 = 1461,	---
1477	DPSQX_S_W_PH = 1462,	---	1477	DPSQX_S_W_PH = 1462,	---
1478	DPSQX_S_W_PH_MMR2 = 1463,	---	1478	DPSQX_S_W_PH_MMR2 = 1463,	---
1479	DPSQ_SA_L_W = 1464,	---	1479	DPSQ_SA_L_W = 1464,	---
1480	DPSQ_SA_L_W_MM = 1465,	---	1480	DPSQ_SA_L_W_MM = 1465,	---
1481	DPSQ_S_W_PH = 1466,	---	1481	DPSQ_S_W_PH = 1466,	---
1482	DPSQ_S_W_PH_MM = 1467,	---	1482	DPSQ_S_W_PH_MM = 1467,	---
1483	DPSUB_S_D = 1468,	---	1483	DPSUB_S_D = 1468,	---
1484	DPSUB_S_H = 1469,	---	1484	DPSUB_S_H = 1469,	---
1485	DPSUB_S_W = 1470,	---	1485	DPSUB_S_W = 1470,	---
1486	DPSUB_U_D = 1471,	---	1486	DPSUB_U_D = 1471,	---
1487	DPSUB_U_H = 1472,	---	1487	DPSUB_U_H = 1472,	---
1488	DPSUB_U_W = 1473,	---	1488	DPSUB_U_W = 1473,	---
1489	DPSU_H_QBL = 1474,	---	1489	DPSU_H_QBL = 1474,	---
1490	DPSU_H_QBL_MM = 1475,	---	1490	DPSU_H_QBL_MM = 1475,	---
1491	DPSU_H_QBR = 1476,	---	1491	DPSU_H_QBR = 1476,	---
1492	DPSU_H_QBR_MM = 1477,	---	1492	DPSU_H_QBR_MM = 1477,	---
1493	DPSX_W_PH = 1478,	---	1493	DPSX_W_PH = 1478,	---
1494	DPSX_W_PH_MMR2 = 1479,	---	1494	DPSX_W_PH_MMR2 = 1479,	---
1495	DPS_W_PH = 1480,	---	1495	DPS_W_PH = 1480,	---
1496	DPS_W_PH_MMR2 = 1481,	---	1496	DPS_W_PH_MMR2 = 1481,	---
1497	DROTR = 1482,	---	1497	DROTR = 1482,	---
1498	DROTR32 = 1483,	---	1498	DROTR32 = 1483,	---
1499	DROTRV = 1484,	---	1499	DROTRV = 1484,	---
1500	DSBH = 1485,	---	1500	DSBH = 1485,	---
1501	DSDIV = 1486,	---	1501	DSDIV = 1486,	---
1502	DSHD = 1487,	---	1502	DSHD = 1487,	---
1503	DSLL = 1488,	---	1503	DSLL = 1488,	---
1504	DSLL32 = 1489,	---	1504	DSLL32 = 1489,	---
1505	DSLL64_32 = 1490,	---	1505	DSLL64_32 = 1490,	---
1506	DSLLV = 1491,	---	1506	DSLLV = 1491,	---
1507	DSRA = 1492,	---	1507	DSRA = 1492,	---
1508	DSRA32 = 1493,	---	1508	DSRA32 = 1493,	---
1509	DSRAV = 1494,	---	1509	DSRAV = 1494,	---
1510	DSRL = 1495,	---	1510	DSRL = 1495,	---
1511	DSRL32 = 1496,	---	1511	DSRL32 = 1496,	---
1512	DSRLV = 1497,	---	1512	DSRLV = 1497,	---
1513	DSUB = 1498,	---	1513	DSUB = 1498,	---
1514	DSUBu = 1499,	---	1514	DSUBu = 1499,	---
1515	DUDIV = 1500,	---	1515	DUDIV = 1500,	---
1516	DVP = 1501,	---	1516	DVP = 1501,	---
1517	DVPE = 1502,	---	1517	DVPE = 1502,	---
1518	DVP_MMR6 = 1503,	---	1518	DVP_MMR6 = 1503,	---
1519	DivRxRy16 = 1504,	---	1519	DivRxRy16 = 1504,	---
1520	DivuRxRy16 = 1505,	---	1520	DivuRxRy16 = 1505,	---
1521	EHB = 1506,	---	1521	EHB = 1506,	---
1522	EHB_MM = 1507,	---	1522	EHB_MM = 1507,	---
1523	EHB_MMR6 = 1508,	---	1523	EHB_MMR6 = 1508,	---
1524	EI = 1509,	---	1524	EI = 1509,	---
1525	EI_MM = 1510,	---	1525	EI_MM = 1510,	---
1526	EI_MMR6 = 1511,	---	1526	EI_MMR6 = 1511,	---
1527	EMT = 1512,	---	1527	EMT = 1512,	---
1528	ERET = 1513,	---	1528	ERET = 1513,	---
1529	ERETNC = 1514,	---	1529	ERETNC = 1514,	---
1530	ERETNC_MMR6 = 1515,	---	1530	ERETNC_MMR6 = 1515,	---
1531	ERET_MM = 1516,	---	1531	ERET_MM = 1516,	---
1532	ERET_MMR6 = 1517,	---	1532	ERET_MMR6 = 1517,	---
1533	EVP = 1518,	---	1533	EVP = 1518,	---
1534	EVPE = 1519,	---	1534	EVPE = 1519,	---
1535	EVP_MMR6 = 1520,	---	1535	EVP_MMR6 = 1520,	---
1536	EXT = 1521,	---	1536	EXT = 1521,	---
1537	EXTP = 1522,	---	1537	EXTP = 1522,	---
1538	EXTPDP = 1523,	---	1538	EXTPDP = 1523,	---
1539	EXTPDPV = 1524,	---	1539	EXTPDPV = 1524,	---
1540	EXTPDPV_MM = 1525,	---	1540	EXTPDPV_MM = 1525,	---
1541	EXTPDP_MM = 1526,	---	1541	EXTPDP_MM = 1526,	---
1542	EXTPV = 1527,	---	1542	EXTPV = 1527,	---
1543	EXTPV_MM = 1528,	---	1543	EXTPV_MM = 1528,	---
1544	EXTP_MM = 1529,	---	1544	EXTP_MM = 1529,	---
1545	EXTRV_RS_W = 1530,	---	1545	EXTRV_RS_W = 1530,	---
1546	EXTRV_RS_W_MM = 1531,	---	1546	EXTRV_RS_W_MM = 1531,	---
1547	EXTRV_R_W = 1532,	---	1547	EXTRV_R_W = 1532,	---
1548	EXTRV_R_W_MM = 1533,	---	1548	EXTRV_R_W_MM = 1533,	---
1549	EXTRV_S_H = 1534,	---	1549	EXTRV_S_H = 1534,	---
1550	EXTRV_S_H_MM = 1535,	---	1550	EXTRV_S_H_MM = 1535,	---
1551	EXTRV_W = 1536,	---	1551	EXTRV_W = 1536,	---
1552	EXTRV_W_MM = 1537,	---	1552	EXTRV_W_MM = 1537,	---
1553	EXTR_RS_W = 1538,	---	1553	EXTR_RS_W = 1538,	---
1554	EXTR_RS_W_MM = 1539,	---	1554	EXTR_RS_W_MM = 1539,	---
1555	EXTR_R_W = 1540,	---	1555	EXTR_R_W = 1540,	---
1556	EXTR_R_W_MM = 1541,	---	1556	EXTR_R_W_MM = 1541,	---
1557	EXTR_S_H = 1542,	---	1557	EXTR_S_H = 1542,	---
1558	EXTR_S_H_MM = 1543,	---	1558	EXTR_S_H_MM = 1543,	---
1559	EXTR_W = 1544,	---	1559	EXTR_W = 1544,	---
1560	EXTR_W_MM = 1545,	---	1560	EXTR_W_MM = 1545,	---
1561	EXTS = 1546,	---	1561	EXTS = 1546,	---
1562	EXTS32 = 1547,	---	1562	EXTS32 = 1547,	---
1563	EXT_MM = 1548,	---	1563	EXT_MM = 1548,	---
1564	EXT_MMR6 = 1549,	---	1564	EXT_MMR6 = 1549,	---
1565	FABS_D32 = 1550,	---	1565	FABS_D32 = 1550,	---
1566	FABS_D32_MM = 1551,	---	1566	FABS_D32_MM = 1551,	---
1567	FABS_D64 = 1552,	---	1567	FABS_D64 = 1552,	---
1568	FABS_D64_MM = 1553,	---	1568	FABS_D64_MM = 1553,	---
1569	FABS_S = 1554,	---	1569	FABS_S = 1554,	---
1570	FABS_S_MM = 1555,	---	1570	FABS_S_MM = 1555,	---
1571	FADD_D = 1556,	---	1571	FADD_D = 1556,	---
1572	FADD_D32 = 1557,	---	1572	FADD_D32 = 1557,	---
1573	FADD_D32_MM = 1558,	---	1573	FADD_D32_MM = 1558,	---
1574	FADD_D64 = 1559,	---	1574	FADD_D64 = 1559,	---
1575	FADD_D64_MM = 1560,	---	1575	FADD_D64_MM = 1560,	---
1576	FADD_PS64 = 1561,	---	1576	FADD_PS64 = 1561,	---
1577	FADD_S = 1562,	---	1577	FADD_S = 1562,	---
1578	FADD_S_MM = 1563,	---	1578	FADD_S_MM = 1563,	---
1579	FADD_S_MMR6 = 1564,	---	1579	FADD_S_MMR6 = 1564,	---
1580	FADD_W = 1565,	---	1580	FADD_W = 1565,	---
1581	FCAF_D = 1566,	---	1581	FCAF_D = 1566,	---
1582	FCAF_W = 1567,	---	1582	FCAF_W = 1567,	---
1583	FCEQ_D = 1568,	---	1583	FCEQ_D = 1568,	---
1584	FCEQ_W = 1569,	---	1584	FCEQ_W = 1569,	---
1585	FCLASS_D = 1570,	---	1585	FCLASS_D = 1570,	---
1586	FCLASS_W = 1571,	---	1586	FCLASS_W = 1571,	---
1587	FCLE_D = 1572,	---	1587	FCLE_D = 1572,	---
1588	FCLE_W = 1573,	---	1588	FCLE_W = 1573,	---
1589	FCLT_D = 1574,	---	1589	FCLT_D = 1574,	---
1590	FCLT_W = 1575,	---	1590	FCLT_W = 1575,	---
1591	FCMP_D32 = 1576,	---	1591	FCMP_D32 = 1576,	---
1592	FCMP_D32_MM = 1577,	---	1592	FCMP_D32_MM = 1577,	---
1593	FCMP_D64 = 1578,	---	1593	FCMP_D64 = 1578,	---
1594	FCMP_S32 = 1579,	---	1594	FCMP_S32 = 1579,	---
1595	FCMP_S32_MM = 1580,	---	1595	FCMP_S32_MM = 1580,	---
1596	FCNE_D = 1581,	---	1596	FCNE_D = 1581,	---
1597	FCNE_W = 1582,	---	1597	FCNE_W = 1582,	---
1598	FCOR_D = 1583,	---	1598	FCOR_D = 1583,	---
1599	FCOR_W = 1584,	---	1599	FCOR_W = 1584,	---
1600	FCUEQ_D = 1585,	---	1600	FCUEQ_D = 1585,	---
1601	FCUEQ_W = 1586,	---	1601	FCUEQ_W = 1586,	---
1602	FCULE_D = 1587,	---	1602	FCULE_D = 1587,	---
1603	FCULE_W = 1588,	---	1603	FCULE_W = 1588,	---
1604	FCULT_D = 1589,	---	1604	FCULT_D = 1589,	---
1605	FCULT_W = 1590,	---	1605	FCULT_W = 1590,	---
1606	FCUNE_D = 1591,	---	1606	FCUNE_D = 1591,	---
1607	FCUNE_W = 1592,	---	1607	FCUNE_W = 1592,	---
1608	FCUN_D = 1593,	---	1608	FCUN_D = 1593,	---
1609	FCUN_W = 1594,	---	1609	FCUN_W = 1594,	---
1610	FDIV_D = 1595,	---	1610	FDIV_D = 1595,	---
1611	FDIV_D32 = 1596,	---	1611	FDIV_D32 = 1596,	---
1612	FDIV_D32_MM = 1597,	---	1612	FDIV_D32_MM = 1597,	---
1613	FDIV_D64 = 1598,	---	1613	FDIV_D64 = 1598,	---
1614	FDIV_D64_MM = 1599,	---	1614	FDIV_D64_MM = 1599,	---
1615	FDIV_S = 1600,	---	1615	FDIV_S = 1600,	---
1616	FDIV_S_MM = 1601,	---	1616	FDIV_S_MM = 1601,	---
1617	FDIV_S_MMR6 = 1602,	---	1617	FDIV_S_MMR6 = 1602,	---
1618	FDIV_W = 1603,	---	1618	FDIV_W = 1603,	---
1619	FEXDO_H = 1604,	---	1619	FEXDO_H = 1604,	---
1620	FEXDO_W = 1605,	---	1620	FEXDO_W = 1605,	---
1621	FEXP2_D = 1606,	---	1621	FEXP2_D = 1606,	---
1622	FEXP2_W = 1607,	---	1622	FEXP2_W = 1607,	---
1623	FEXUPL_D = 1608,	---	1623	FEXUPL_D = 1608,	---
1624	FEXUPL_W = 1609,	---	1624	FEXUPL_W = 1609,	---
1625	FEXUPR_D = 1610,	---	1625	FEXUPR_D = 1610,	---
1626	FEXUPR_W = 1611,	---	1626	FEXUPR_W = 1611,	---
1627	FFINT_S_D = 1612,	---	1627	FFINT_S_D = 1612,	---
1628	FFINT_S_W = 1613,	---	1628	FFINT_S_W = 1613,	---
1629	FFINT_U_D = 1614,	---	1629	FFINT_U_D = 1614,	---
1630	FFINT_U_W = 1615,	---	1630	FFINT_U_W = 1615,	---
1631	FFQL_D = 1616,	---	1631	FFQL_D = 1616,	---
1632	FFQL_W = 1617,	---	1632	FFQL_W = 1617,	---
1633	FFQR_D = 1618,	---	1633	FFQR_D = 1618,	---
1634	FFQR_W = 1619,	---	1634	FFQR_W = 1619,	---
1635	FILL_B = 1620,	---	1635	FILL_B = 1620,	---
1636	FILL_D = 1621,	---	1636	FILL_D = 1621,	---
1637	FILL_H = 1622,	---	1637	FILL_H = 1622,	---
1638	FILL_W = 1623,	---	1638	FILL_W = 1623,	---
1639	FLOG2_D = 1624,	---	1639	FLOG2_D = 1624,	---
1640	FLOG2_W = 1625,	---	1640	FLOG2_W = 1625,	---
1641	FLOOR_L_D64 = 1626,	---	1641	FLOOR_L_D64 = 1626,	---
1642	FLOOR_L_D_MMR6 = 1627,	---	1642	FLOOR_L_D_MMR6 = 1627,	---
1643	FLOOR_L_S = 1628,	---	1643	FLOOR_L_S = 1628,	---
1644	FLOOR_L_S_MMR6 = 1629,	---	1644	FLOOR_L_S_MMR6 = 1629,	---
1645	FLOOR_W_D32 = 1630,	---	1645	FLOOR_W_D32 = 1630,	---
1646	FLOOR_W_D64 = 1631,	---	1646	FLOOR_W_D64 = 1631,	---
1647	FLOOR_W_D_MMR6 = 1632,	---	1647	FLOOR_W_D_MMR6 = 1632,	---
1648	FLOOR_W_MM = 1633,	---	1648	FLOOR_W_MM = 1633,	---
1649	FLOOR_W_S = 1634,	---	1649	FLOOR_W_S = 1634,	---
1650	FLOOR_W_S_MM = 1635,	---	1650	FLOOR_W_S_MM = 1635,	---
1651	FLOOR_W_S_MMR6 = 1636,	---	1651	FLOOR_W_S_MMR6 = 1636,	---
1652	FMADD_D = 1637,	---	1652	FMADD_D = 1637,	---
1653	FMADD_W = 1638,	---	1653	FMADD_W = 1638,	---
1654	FMAX_A_D = 1639,	---	1654	FMAX_A_D = 1639,	---
1655	FMAX_A_W = 1640,	---	1655	FMAX_A_W = 1640,	---
1656	FMAX_D = 1641,	---	1656	FMAX_D = 1641,	---
1657	FMAX_W = 1642,	---	1657	FMAX_W = 1642,	---
1658	FMIN_A_D = 1643,	---	1658	FMIN_A_D = 1643,	---
1659	FMIN_A_W = 1644,	---	1659	FMIN_A_W = 1644,	---
1660	FMIN_D = 1645,	---	1660	FMIN_D = 1645,	---
1661	FMIN_W = 1646,	---	1661	FMIN_W = 1646,	---
1662	FMOV_D32 = 1647,	---	1662	FMOV_D32 = 1647,	---
1663	FMOV_D32_MM = 1648,	---	1663	FMOV_D32_MM = 1648,	---
1664	FMOV_D64 = 1649,	---	1664	FMOV_D64 = 1649,	---
1665	FMOV_D64_MM = 1650,	---	1665	FMOV_D64_MM = 1650,	---
1666	FMOV_D_MMR6 = 1651,	---	1666	FMOV_D_MMR6 = 1651,	---
1667	FMOV_S = 1652,	---	1667	FMOV_S = 1652,	---
1668	FMOV_S_MM = 1653,	---	1668	FMOV_S_MM = 1653,	---
1669	FMOV_S_MMR6 = 1654,	---	1669	FMOV_S_MMR6 = 1654,	---
1670	FMSUB_D = 1655,	---	1670	FMSUB_D = 1655,	---
1671	FMSUB_W = 1656,	---	1671	FMSUB_W = 1656,	---
1672	FMUL_D = 1657,	---	1672	FMUL_D = 1657,	---
1673	FMUL_D32 = 1658,	---	1673	FMUL_D32 = 1658,	---
1674	FMUL_D32_MM = 1659,	---	1674	FMUL_D32_MM = 1659,	---
1675	FMUL_D64 = 1660,	---	1675	FMUL_D64 = 1660,	---
1676	FMUL_D64_MM = 1661,	---	1676	FMUL_D64_MM = 1661,	---
1677	FMUL_PS64 = 1662,	---	1677	FMUL_PS64 = 1662,	---
1678	FMUL_S = 1663,	---	1678	FMUL_S = 1663,	---
1679	FMUL_S_MM = 1664,	---	1679	FMUL_S_MM = 1664,	---
1680	FMUL_S_MMR6 = 1665,	---	1680	FMUL_S_MMR6 = 1665,	---
1681	FMUL_W = 1666,	---	1681	FMUL_W = 1666,	---
1682	FNEG_D32 = 1667,	---	1682	FNEG_D32 = 1667,	---
1683	FNEG_D32_MM = 1668,	---	1683	FNEG_D32_MM = 1668,	---
1684	FNEG_D64 = 1669,	---	1684	FNEG_D64 = 1669,	---
1685	FNEG_D64_MM = 1670,	---	1685	FNEG_D64_MM = 1670,	---
1686	FNEG_S = 1671,	---	1686	FNEG_S = 1671,	---
1687	FNEG_S_MM = 1672,	---	1687	FNEG_S_MM = 1672,	---
1688	FNEG_S_MMR6 = 1673,	---	1688	FNEG_S_MMR6 = 1673,	---
1689	FORK = 1674,	---	1689	FORK = 1674,	---
1690	FRCP_D = 1675,	---	1690	FRCP_D = 1675,	---
1691	FRCP_W = 1676,	---	1691	FRCP_W = 1676,	---
1692	FRINT_D = 1677,	---	1692	FRINT_D = 1677,	---
1693	FRINT_W = 1678,	---	1693	FRINT_W = 1678,	---
1694	FRSQRT_D = 1679,	---	1694	FRSQRT_D = 1679,	---
1695	FRSQRT_W = 1680,	---	1695	FRSQRT_W = 1680,	---
1696	FSAF_D = 1681,	---	1696	FSAF_D = 1681,	---
1697	FSAF_W = 1682,	---	1697	FSAF_W = 1682,	---
1698	FSEQ_D = 1683,	---	1698	FSEQ_D = 1683,	---
1699	FSEQ_W = 1684,	---	1699	FSEQ_W = 1684,	---
1700	FSLE_D = 1685,	---	1700	FSLE_D = 1685,	---
1701	FSLE_W = 1686,	---	1701	FSLE_W = 1686,	---
1702	FSLT_D = 1687,	---	1702	FSLT_D = 1687,	---
1703	FSLT_W = 1688,	---	1703	FSLT_W = 1688,	---
1704	FSNE_D = 1689,	---	1704	FSNE_D = 1689,	---
1705	FSNE_W = 1690,	---	1705	FSNE_W = 1690,	---
1706	FSOR_D = 1691,	---	1706	FSOR_D = 1691,	---
1707	FSOR_W = 1692,	---	1707	FSOR_W = 1692,	---
1708	FSQRT_D = 1693,	---	1708	FSQRT_D = 1693,	---
1709	FSQRT_D32 = 1694,	---	1709	FSQRT_D32 = 1694,	---
1710	FSQRT_D32_MM = 1695,	---	1710	FSQRT_D32_MM = 1695,	---
1711	FSQRT_D64 = 1696,	---	1711	FSQRT_D64 = 1696,	---
1712	FSQRT_D64_MM = 1697,	---	1712	FSQRT_D64_MM = 1697,	---
1713	FSQRT_S = 1698,	---	1713	FSQRT_S = 1698,	---
1714	FSQRT_S_MM = 1699,	---	1714	FSQRT_S_MM = 1699,	---
1715	FSQRT_W = 1700,	---	1715	FSQRT_W = 1700,	---
1716	FSUB_D = 1701,	---	1716	FSUB_D = 1701,	---
1717	FSUB_D32 = 1702,	---	1717	FSUB_D32 = 1702,	---
1718	FSUB_D32_MM = 1703,	---	1718	FSUB_D32_MM = 1703,	---
1719	FSUB_D64 = 1704,	---	1719	FSUB_D64 = 1704,	---
1720	FSUB_D64_MM = 1705,	---	1720	FSUB_D64_MM = 1705,	---
1721	FSUB_PS64 = 1706,	---	1721	FSUB_PS64 = 1706,	---
1722	FSUB_S = 1707,	---	1722	FSUB_S = 1707,	---
1723	FSUB_S_MM = 1708,	---	1723	FSUB_S_MM = 1708,	---
1724	FSUB_S_MMR6 = 1709,	---	1724	FSUB_S_MMR6 = 1709,	---
1725	FSUB_W = 1710,	---	1725	FSUB_W = 1710,	---
1726	FSUEQ_D = 1711,	---	1726	FSUEQ_D = 1711,	---
1727	FSUEQ_W = 1712,	---	1727	FSUEQ_W = 1712,	---
1728	FSULE_D = 1713,	---	1728	FSULE_D = 1713,	---
1729	FSULE_W = 1714,	---	1729	FSULE_W = 1714,	---
1730	FSULT_D = 1715,	---	1730	FSULT_D = 1715,	---
1731	FSULT_W = 1716,	---	1731	FSULT_W = 1716,	---
1732	FSUNE_D = 1717,	---	1732	FSUNE_D = 1717,	---
1733	FSUNE_W = 1718,	---	1733	FSUNE_W = 1718,	---
1734	FSUN_D = 1719,	---	1734	FSUN_D = 1719,	---
1735	FSUN_W = 1720,	---	1735	FSUN_W = 1720,	---
1736	FTINT_S_D = 1721,	---	1736	FTINT_S_D = 1721,	---
1737	FTINT_S_W = 1722,	---	1737	FTINT_S_W = 1722,	---
1738	FTINT_U_D = 1723,	---	1738	FTINT_U_D = 1723,	---
1739	FTINT_U_W = 1724,	---	1739	FTINT_U_W = 1724,	---
1740	FTQ_H = 1725,	---	1740	FTQ_H = 1725,	---
1741	FTQ_W = 1726,	---	1741	FTQ_W = 1726,	---
1742	FTRUNC_S_D = 1727,	---	1742	FTRUNC_S_D = 1727,	---
1743	FTRUNC_S_W = 1728,	---	1743	FTRUNC_S_W = 1728,	---
1744	FTRUNC_U_D = 1729,	---	1744	FTRUNC_U_D = 1729,	---
1745	FTRUNC_U_W = 1730,	---	1745	FTRUNC_U_W = 1730,	---
1746	GINVI = 1731,	---	1746	GINVI = 1731,	---
1747	GINVI_MMR6 = 1732,	---	1747	GINVI_MMR6 = 1732,	---
1748	GINVT = 1733,	---	1748	GINVT = 1733,	---
1749	GINVT_MMR6 = 1734,	---	1749	GINVT_MMR6 = 1734,	---
1750	HADD_S_D = 1735,	---	1750	HADD_S_D = 1735,	---
1751	HADD_S_H = 1736,	---	1751	HADD_S_H = 1736,	---
1752	HADD_S_W = 1737,	---	1752	HADD_S_W = 1737,	---
1753	HADD_U_D = 1738,	---	1753	HADD_U_D = 1738,	---
1754	HADD_U_H = 1739,	---	1754	HADD_U_H = 1739,	---
1755	HADD_U_W = 1740,	---	1755	HADD_U_W = 1740,	---
1756	HSUB_S_D = 1741,	---	1756	HSUB_S_D = 1741,	---
1757	HSUB_S_H = 1742,	---	1757	HSUB_S_H = 1742,	---
1758	HSUB_S_W = 1743,	---	1758	HSUB_S_W = 1743,	---
1759	HSUB_U_D = 1744,	---	1759	HSUB_U_D = 1744,	---
1760	HSUB_U_H = 1745,	---	1760	HSUB_U_H = 1745,	---
1761	HSUB_U_W = 1746,	---	1761	HSUB_U_W = 1746,	---
1762	HYPCALL = 1747,	---	1762	HYPCALL = 1747,	---
1763	HYPCALL_MM = 1748,	---	1763	HYPCALL_MM = 1748,	---
1764	ILVEV_B = 1749,	---	1764	ILVEV_B = 1749,	---
1765	ILVEV_D = 1750,	---	1765	ILVEV_D = 1750,	---
1766	ILVEV_H = 1751,	---	1766	ILVEV_H = 1751,	---
1767	ILVEV_W = 1752,	---	1767	ILVEV_W = 1752,	---
1768	ILVL_B = 1753,	---	1768	ILVL_B = 1753,	---
1769	ILVL_D = 1754,	---	1769	ILVL_D = 1754,	---
1770	ILVL_H = 1755,	---	1770	ILVL_H = 1755,	---
1771	ILVL_W = 1756,	---	1771	ILVL_W = 1756,	---
1772	ILVOD_B = 1757,	---	1772	ILVOD_B = 1757,	---
1773	ILVOD_D = 1758,	---	1773	ILVOD_D = 1758,	---
1774	ILVOD_H = 1759,	---	1774	ILVOD_H = 1759,	---
1775	ILVOD_W = 1760,	---	1775	ILVOD_W = 1760,	---
1776	ILVR_B = 1761,	---	1776	ILVR_B = 1761,	---
1777	ILVR_D = 1762,	---	1777	ILVR_D = 1762,	---
1778	ILVR_H = 1763,	---	1778	ILVR_H = 1763,	---
1779	ILVR_W = 1764,	---	1779	ILVR_W = 1764,	---
1780	INS = 1765,	---	1780	INS = 1765,	---
1781	INSERT_B = 1766,	---	1781	INSERT_B = 1766,	---
1782	INSERT_D = 1767,	---	1782	INSERT_D = 1767,	---
1783	INSERT_H = 1768,	---	1783	INSERT_H = 1768,	---
1784	INSERT_W = 1769,	---	1784	INSERT_W = 1769,	---
1785	INSV = 1770,	---	1785	INSV = 1770,	---
1786	INSVE_B = 1771,	---	1786	INSVE_B = 1771,	---
1787	INSVE_D = 1772,	---	1787	INSVE_D = 1772,	---
1788	INSVE_H = 1773,	---	1788	INSVE_H = 1773,	---
1789	INSVE_W = 1774,	---	1789	INSVE_W = 1774,	---
1790	INSV_MM = 1775,	---	1790	INSV_MM = 1775,	---
1791	INS_MM = 1776,	---	1791	INS_MM = 1776,	---
1792	INS_MMR6 = 1777,	---	1792	INS_MMR6 = 1777,	---
1793	J = 1778,	---	1793	J = 1778,	---
1794	JAL = 1779,	---	1794	JAL = 1779,	---
1795	JALR = 1780,	---	1795	JALR = 1780,	---
1796	JALR16_MM = 1781,	---	1796	JALR16_MM = 1781,	---
1797	JALR64 = 1782,	---	1797	JALR64 = 1782,	---
1798	JALRC16_MMR6 = 1783,	---	1798	JALRC16_MMR6 = 1783,	---
1799	JALRC_HB_MMR6 = 1784,	---	1799	JALRC_HB_MMR6 = 1784,	---
1800	JALRC_MMR6 = 1785,	---	1800	JALRC_MMR6 = 1785,	---
1801	JALRS16_MM = 1786,	---	1801	JALRS16_MM = 1786,	---
1802	JALRS_MM = 1787,	---	1802	JALRS_MM = 1787,	---
1803	JALR_HB = 1788,	---	1803	JALR_HB = 1788,	---
1804	JALR_HB64 = 1789,	---	1804	JALR_HB64 = 1789,	---
1805	JALR_MM = 1790,	---	1805	JALR_MM = 1790,	---
1806	JALS_MM = 1791,	---	1806	JALS_MM = 1791,	---
1807	JALX = 1792,	---	1807	JALX = 1792,	---
1808	JALX_MM = 1793,	---	1808	JALX_MM = 1793,	---
1809	JAL_MM = 1794,	---	1809	JAL_MM = 1794,	---
1810	JIALC = 1795,	---	1810	JIALC = 1795,	---
1811	JIALC64 = 1796,	---	1811	JIALC64 = 1796,	---
1812	JIALC_MMR6 = 1797,	---	1812	JIALC_MMR6 = 1797,	---
1813	JIC = 1798,	---	1813	JIC = 1798,	---
1814	JIC64 = 1799,	---	1814	JIC64 = 1799,	---
1815	JIC_MMR6 = 1800,	---	1815	JIC_MMR6 = 1800,	---
1816	JR = 1801,	---	1816	JR = 1801,	---
1817	JR16_MM = 1802,	---	1817	JR16_MM = 1802,	---
1818	JR64 = 1803,	---	1818	JR64 = 1803,	---
1819	JRADDIUSP = 1804,	---	1819	JRADDIUSP = 1804,	---
1820	JRC16_MM = 1805,	---	1820	JRC16_MM = 1805,	---
1821	JRC16_MMR6 = 1806,	---	1821	JRC16_MMR6 = 1806,	---
1822	JRCADDIUSP_MMR6 = 1807,	---	1822	JRCADDIUSP_MMR6 = 1807,	---
1823	JR_HB = 1808,	---	1823	JR_HB = 1808,	---
1824	JR_HB64 = 1809,	---	1824	JR_HB64 = 1809,	---
1825	JR_HB64_R6 = 1810,	---	1825	JR_HB64_R6 = 1810,	---
1826	JR_HB_R6 = 1811,	---	1826	JR_HB_R6 = 1811,	---
1827	JR_MM = 1812,	---	1827	JR_MM = 1812,	---
1828	J_MM = 1813,	---	1828	J_MM = 1813,	---
1829	Jal16 = 1814,	---	1829	Jal16 = 1814,	---
1830	JalB16 = 1815,	---	1830	JalB16 = 1815,	---
1831	JrRa16 = 1816,	---	1831	JrRa16 = 1816,	---
1832	JrcRa16 = 1817,	---	1832	JrcRa16 = 1817,	---
1833	JrcRx16 = 1818,	---	1833	JrcRx16 = 1818,	---
1834	JumpLinkReg16 = 1819,	---	1834	JumpLinkReg16 = 1819,	---
1835	LB = 1820,	---	1835	LB = 1820,	---
1836	LB64 = 1821,	---	1836	LB64 = 1821,	---
1837	LBE = 1822,	---	1837	LBE = 1822,	---
1838	LBE_MM = 1823,	---	1838	LBE_MM = 1823,	---
1839	LBU16_MM = 1824,	---	1839	LBU16_MM = 1824,	---
1840	LBUX = 1825,	---	1840	LBUX = 1825,	---
1841	LBUX_MM = 1826,	---	1841	LBUX_MM = 1826,	---
1842	LBU_MMR6 = 1827,	---	1842	LBU_MMR6 = 1827,	---
1843	LB_MM = 1828,	---	1843	LB_MM = 1828,	---
1844	LB_MMR6 = 1829,	---	1844	LB_MMR6 = 1829,	---
1845	LBu = 1830,	---	1845	LBu = 1830,	---
1846	LBu64 = 1831,	---	1846	LBu64 = 1831,	---
1847	LBuE = 1832,	---	1847	LBuE = 1832,	---
1848	LBuE_MM = 1833,	---	1848	LBuE_MM = 1833,	---
1849	LBu_MM = 1834,	---	1849	LBu_MM = 1834,	---
1850	LD = 1835,	---	1850	LD = 1835,	---
1851	LDC1 = 1836,	---	1851	LDC1 = 1836,	---
1852	LDC164 = 1837,	---	1852	LDC164 = 1837,	---
1853	LDC1_D64_MMR6 = 1838,	---	1853	LDC1_D64_MMR6 = 1838,	---
1854	LDC1_MM_D32 = 1839,	---	1854	LDC1_MM_D32 = 1839,	---
1855	LDC1_MM_D64 = 1840,	---	1855	LDC1_MM_D64 = 1840,	---
1856	LDC2 = 1841,	---	1856	LDC2 = 1841,	---
1857	LDC2_MMR6 = 1842,	---	1857	LDC2_MMR6 = 1842,	---
1858	LDC2_R6 = 1843,	---	1858	LDC2_R6 = 1843,	---
1859	LDC3 = 1844,	---	1859	LDC3 = 1844,	---
1860	LDI_B = 1845,	---	1860	LDI_B = 1845,	---
1861	LDI_D = 1846,	---	1861	LDI_D = 1846,	---
1862	LDI_H = 1847,	---	1862	LDI_H = 1847,	---
1863	LDI_W = 1848,	---	1863	LDI_W = 1848,	---
1864	LDL = 1849,	---	1864	LDL = 1849,	---
1865	LDPC = 1850,	---	1865	LDPC = 1850,	---
1866	LDR = 1851,	---	1866	LDR = 1851,	---
1867	LDXC1 = 1852,	---	1867	LDXC1 = 1852,	---
1868	LDXC164 = 1853,	---	1868	LDXC164 = 1853,	---
1869	LD_B = 1854,	---	1869	LD_B = 1854,	---
1870	LD_D = 1855,	---	1870	LD_D = 1855,	---
1871	LD_H = 1856,	---	1871	LD_H = 1856,	---
1872	LD_W = 1857,	---	1872	LD_W = 1857,	---
1873	LEA_ADDiu = 1858,	---	1873	LEA_ADDiu = 1858,	---
1874	LEA_ADDiu64 = 1859,	---	1874	LEA_ADDiu64 = 1859,	---
1875	LEA_ADDiu_MM = 1860,	---	1875	LEA_ADDiu_MM = 1860,	---
1876	LH = 1861,	---	1876	LH = 1861,	---
1877	LH64 = 1862,	---	1877	LH64 = 1862,	---
1878	LHE = 1863,	---	1878	LHE = 1863,	---
1879	LHE_MM = 1864,	---	1879	LHE_MM = 1864,	---
1880	LHU16_MM = 1865,	---	1880	LHU16_MM = 1865,	---
1881	LHX = 1866,	---	1881	LHX = 1866,	---
1882	LHX_MM = 1867,	---	1882	LHX_MM = 1867,	---
1883	LH_MM = 1868,	---	1883	LH_MM = 1868,	---
1884	LHu = 1869,	---	1884	LHu = 1869,	---
1885	LHu64 = 1870,	---	1885	LHu64 = 1870,	---
1886	LHuE = 1871,	---	1886	LHuE = 1871,	---
1887	LHuE_MM = 1872,	---	1887	LHuE_MM = 1872,	---
1888	LHu_MM = 1873,	---	1888	LHu_MM = 1873,	---
1889	LI16_MM = 1874,	---	1889	LI16_MM = 1874,	---
1890	LI16_MMR6 = 1875,	---	1890	LI16_MMR6 = 1875,	---
1891	LL = 1876,	---	1891	LL = 1876,	---
1892	LL64 = 1877,	---	1892	LL64 = 1877,	---
1893	LL64_R6 = 1878,	---	1893	LL64_R6 = 1878,	---
1894	LLD = 1879,	---	1894	LLD = 1879,	---
1895	LLD_R6 = 1880,	---	1895	LLD_R6 = 1880,	---
1896	LLE = 1881,	---	1896	LLE = 1881,	---
1897	LLE_MM = 1882,	---	1897	LLE_MM = 1882,	---
1898	LL_MM = 1883,	---	1898	LL_MM = 1883,	---
1899	LL_MMR6 = 1884,	---	1899	LL_MMR6 = 1884,	---
1900	LL_R6 = 1885,	---	1900	LL_R6 = 1885,	---
1901	LSA = 1886,	---	1901	LSA = 1886,	---
1902	LSA_MMR6 = 1887,	---	1902	LSA_MMR6 = 1887,	---
1903	LSA_R6 = 1888,	---	1903	LSA_R6 = 1888,	---
1904	LUI_MMR6 = 1889,	---	1904	LUI_MMR6 = 1889,	---
1905	LUXC1 = 1890,	---	1905	LUXC1 = 1890,	---
1906	LUXC164 = 1891,	---	1906	LUXC164 = 1891,	---
1907	LUXC1_MM = 1892,	---	1907	LUXC1_MM = 1892,	---
1908	LUi = 1893,	---	1908	LUi = 1893,	---
1909	LUi64 = 1894,	---	1909	LUi64 = 1894,	---
1910	LUi_MM = 1895,	---	1910	LUi_MM = 1895,	---
1911	LW = 1896,	---	1911	LW = 1896,	---
1912	LW16_MM = 1897,	---	1912	LW16_MM = 1897,	---
1913	LW64 = 1898,	---	1913	LW64 = 1898,	---
1914	LWC1 = 1899,	---	1914	LWC1 = 1899,	---
1915	LWC1_MM = 1900,	---	1915	LWC1_MM = 1900,	---
1916	LWC2 = 1901,	---	1916	LWC2 = 1901,	---
1917	LWC2_MMR6 = 1902,	---	1917	LWC2_MMR6 = 1902,	---
1918	LWC2_R6 = 1903,	---	1918	LWC2_R6 = 1903,	---
1919	LWC3 = 1904,	---	1919	LWC3 = 1904,	---
1920	LWDSP = 1905,	---	1920	LWDSP = 1905,	---
1921	LWDSP_MM = 1906,	---	1921	LWDSP_MM = 1906,	---
1922	LWE = 1907,	---	1922	LWE = 1907,	---
1923	LWE_MM = 1908,	---	1923	LWE_MM = 1908,	---
1924	LWGP_MM = 1909,	---	1924	LWGP_MM = 1909,	---
1925	LWL = 1910,	---	1925	LWL = 1910,	---
1926	LWL64 = 1911,	---	1926	LWL64 = 1911,	---
1927	LWLE = 1912,	---	1927	LWLE = 1912,	---
1928	LWLE_MM = 1913,	---	1928	LWLE_MM = 1913,	---
1929	LWL_MM = 1914,	---	1929	LWL_MM = 1914,	---
1930	LWM16_MM = 1915,	---	1930	LWM16_MM = 1915,	---
1931	LWM16_MMR6 = 1916,	---	1931	LWM16_MMR6 = 1916,	---
1932	LWM32_MM = 1917,	---	1932	LWM32_MM = 1917,	---
1933	LWPC = 1918,	---	1933	LWPC = 1918,	---
1934	LWPC_MMR6 = 1919,	---	1934	LWPC_MMR6 = 1919,	---
1935	LWP_MM = 1920,	---	1935	LWP_MM = 1920,	---
1936	LWR = 1921,	---	1936	LWR = 1921,	---
1937	LWR64 = 1922,	---	1937	LWR64 = 1922,	---
1938	LWRE = 1923,	---	1938	LWRE = 1923,	---
1939	LWRE_MM = 1924,	---	1939	LWRE_MM = 1924,	---
1940	LWR_MM = 1925,	---	1940	LWR_MM = 1925,	---
1941	LWSP_MM = 1926,	---	1941	LWSP_MM = 1926,	---
1942	LWUPC = 1927,	---	1942	LWUPC = 1927,	---
1943	LWU_MM = 1928,	---	1943	LWU_MM = 1928,	---
1944	LWX = 1929,	---	1944	LWX = 1929,	---
1945	LWXC1 = 1930,	---	1945	LWXC1 = 1930,	---
1946	LWXC1_MM = 1931,	---	1946	LWXC1_MM = 1931,	---
1947	LWXS_MM = 1932,	---	1947	LWXS_MM = 1932,	---
1948	LWX_MM = 1933,	---	1948	LWX_MM = 1933,	---
1949	LW_MM = 1934,	---	1949	LW_MM = 1934,	---
1950	LW_MMR6 = 1935,	---	1950	LW_MMR6 = 1935,	---
1951	LWu = 1936,	---	1951	LWu = 1936,	---
1952	LbRxRyOffMemX16 = 1937,	---	1952	LbRxRyOffMemX16 = 1937,	---
1953	LbuRxRyOffMemX16 = 1938,	---	1953	LbuRxRyOffMemX16 = 1938,	---
1954	LhRxRyOffMemX16 = 1939,	---	1954	LhRxRyOffMemX16 = 1939,	---
1955	LhuRxRyOffMemX16 = 1940,	---	1955	LhuRxRyOffMemX16 = 1940,	---
1956	LiRxImm16 = 1941,	---	1956	LiRxImm16 = 1941,	---
1957	LiRxImmAlignX16 = 1942,	---	1957	LiRxImmAlignX16 = 1942,	---
1958	LiRxImmX16 = 1943,	---	1958	LiRxImmX16 = 1943,	---
1959	LwRxPcTcp16 = 1944,	---	1959	LwRxPcTcp16 = 1944,	---
1960	LwRxPcTcpX16 = 1945,	---	1960	LwRxPcTcpX16 = 1945,	---
1961	LwRxRyOffMemX16 = 1946,	---	1961	LwRxRyOffMemX16 = 1946,	---
1962	LwRxSpImmX16 = 1947,	---	1962	LwRxSpImmX16 = 1947,	---
1963	MADD = 1948,	---	1963	MADD = 1948,	---
1964	MADDF_D = 1949,	---	1964	MADDF_D = 1949,	---
1965	MADDF_D_MMR6 = 1950,	---	1965	MADDF_D_MMR6 = 1950,	---
1966	MADDF_S = 1951,	---	1966	MADDF_S = 1951,	---
1967	MADDF_S_MMR6 = 1952,	---	1967	MADDF_S_MMR6 = 1952,	---
1968	MADDR_Q_H = 1953,	---	1968	MADDR_Q_H = 1953,	---
1969	MADDR_Q_W = 1954,	---	1969	MADDR_Q_W = 1954,	---
1970	MADDU = 1955,	---	1970	MADDU = 1955,	---
1971	MADDU_DSP = 1956,	---	1971	MADDU_DSP = 1956,	---
1972	MADDU_DSP_MM = 1957,	---	1972	MADDU_DSP_MM = 1957,	---
1973	MADDU_MM = 1958,	---	1973	MADDU_MM = 1958,	---
1974	MADDV_B = 1959,	---	1974	MADDV_B = 1959,	---
1975	MADDV_D = 1960,	---	1975	MADDV_D = 1960,	---
1976	MADDV_H = 1961,	---	1976	MADDV_H = 1961,	---
1977	MADDV_W = 1962,	---	1977	MADDV_W = 1962,	---
1978	MADD_D32 = 1963,	---	1978	MADD_D32 = 1963,	---
1979	MADD_D32_MM = 1964,	---	1979	MADD_D32_MM = 1964,	---
1980	MADD_D64 = 1965,	---	1980	MADD_D64 = 1965,	---
1981	MADD_DSP = 1966,	---	1981	MADD_DSP = 1966,	---
1982	MADD_DSP_MM = 1967,	---	1982	MADD_DSP_MM = 1967,	---
1983	MADD_MM = 1968,	---	1983	MADD_MM = 1968,	---
1984	MADD_Q_H = 1969,	---	1984	MADD_Q_H = 1969,	---
1985	MADD_Q_W = 1970,	---	1985	MADD_Q_W = 1970,	---
1986	MADD_S = 1971,	---	1986	MADD_S = 1971,	---
1987	MADD_S_MM = 1972,	---	1987	MADD_S_MM = 1972,	---
1988	MAQ_SA_W_PHL = 1973,	---	1988	MAQ_SA_W_PHL = 1973,	---
1989	MAQ_SA_W_PHL_MM = 1974,	---	1989	MAQ_SA_W_PHL_MM = 1974,	---
1990	MAQ_SA_W_PHR = 1975,	---	1990	MAQ_SA_W_PHR = 1975,	---
1991	MAQ_SA_W_PHR_MM = 1976,	---	1991	MAQ_SA_W_PHR_MM = 1976,	---
1992	MAQ_S_W_PHL = 1977,	---	1992	MAQ_S_W_PHL = 1977,	---
1993	MAQ_S_W_PHL_MM = 1978,	---	1993	MAQ_S_W_PHL_MM = 1978,	---
1994	MAQ_S_W_PHR = 1979,	---	1994	MAQ_S_W_PHR = 1979,	---
1995	MAQ_S_W_PHR_MM = 1980,	---	1995	MAQ_S_W_PHR_MM = 1980,	---
1996	MAXA_D = 1981,	---	1996	MAXA_D = 1981,	---
1997	MAXA_D_MMR6 = 1982,	---	1997	MAXA_D_MMR6 = 1982,	---
1998	MAXA_S = 1983,	---	1998	MAXA_S = 1983,	---
1999	MAXA_S_MMR6 = 1984,	---	1999	MAXA_S_MMR6 = 1984,	---
2000	MAXI_S_B = 1985,	---	2000	MAXI_S_B = 1985,	---
2001	MAXI_S_D = 1986,	---	2001	MAXI_S_D = 1986,	---
2002	MAXI_S_H = 1987,	---	2002	MAXI_S_H = 1987,	---
2003	MAXI_S_W = 1988,	---	2003	MAXI_S_W = 1988,	---
2004	MAXI_U_B = 1989,	---	2004	MAXI_U_B = 1989,	---
2005	MAXI_U_D = 1990,	---	2005	MAXI_U_D = 1990,	---
2006	MAXI_U_H = 1991,	---	2006	MAXI_U_H = 1991,	---
2007	MAXI_U_W = 1992,	---	2007	MAXI_U_W = 1992,	---
2008	MAX_A_B = 1993,	---	2008	MAX_A_B = 1993,	---
2009	MAX_A_D = 1994,	---	2009	MAX_A_D = 1994,	---
2010	MAX_A_H = 1995,	---	2010	MAX_A_H = 1995,	---
2011	MAX_A_W = 1996,	---	2011	MAX_A_W = 1996,	---
2012	MAX_D = 1997,	---	2012	MAX_D = 1997,	---
2013	MAX_D_MMR6 = 1998,	---	2013	MAX_D_MMR6 = 1998,	---
2014	MAX_S = 1999,	---	2014	MAX_S = 1999,	---
2015	MAX_S_B = 2000,	---	2015	MAX_S_B = 2000,	---
2016	MAX_S_D = 2001,	---	2016	MAX_S_D = 2001,	---
2017	MAX_S_H = 2002,	---	2017	MAX_S_H = 2002,	---
2018	MAX_S_MMR6 = 2003,	---	2018	MAX_S_MMR6 = 2003,	---
2019	MAX_S_W = 2004,	---	2019	MAX_S_W = 2004,	---
2020	MAX_U_B = 2005,	---	2020	MAX_U_B = 2005,	---
2021	MAX_U_D = 2006,	---	2021	MAX_U_D = 2006,	---
2022	MAX_U_H = 2007,	---	2022	MAX_U_H = 2007,	---
2023	MAX_U_W = 2008,	---	2023	MAX_U_W = 2008,	---
2024	MFC0 = 2009,	---	2024	MFC0 = 2009,	---
2025	MFC0_MMR6 = 2010,	---	2025	MFC0_MMR6 = 2010,	---
2026	MFC1 = 2011,	---	2026	MFC1 = 2011,	---
2027	MFC1_D64 = 2012,	---	2027	MFC1_D64 = 2012,	---
2028	MFC1_MM = 2013,	---	2028	MFC1_MM = 2013,	---
2029	MFC1_MMR6 = 2014,	---	2029	MFC1_MMR6 = 2014,	---
2030	MFC2 = 2015,	---	2030	MFC2 = 2015,	---
2031	MFC2_MMR6 = 2016,	---	2031	MFC2_MMR6 = 2016,	---
2032	MFGC0 = 2017,	---	2032	MFGC0 = 2017,	---
2033	MFGC0_MM = 2018,	---	2033	MFGC0_MM = 2018,	---
2034	MFHC0_MMR6 = 2019,	---	2034	MFHC0_MMR6 = 2019,	---
2035	MFHC1_D32 = 2020,	---	2035	MFHC1_D32 = 2020,	---
2036	MFHC1_D32_MM = 2021,	---	2036	MFHC1_D32_MM = 2021,	---
2037	MFHC1_D64 = 2022,	---	2037	MFHC1_D64 = 2022,	---
2038	MFHC1_D64_MM = 2023,	---	2038	MFHC1_D64_MM = 2023,	---
2039	MFHC2_MMR6 = 2024,	---	2039	MFHC2_MMR6 = 2024,	---
2040	MFHGC0 = 2025,	---	2040	MFHGC0 = 2025,	---
2041	MFHGC0_MM = 2026,	---	2041	MFHGC0_MM = 2026,	---
2042	MFHI = 2027,	---	2042	MFHI = 2027,	---
2043	MFHI16_MM = 2028,	---	2043	MFHI16_MM = 2028,	---
2044	MFHI64 = 2029,	---	2044	MFHI64 = 2029,	---
2045	MFHI_DSP = 2030,	---	2045	MFHI_DSP = 2030,	---
2046	MFHI_DSP_MM = 2031,	---	2046	MFHI_DSP_MM = 2031,	---
2047	MFHI_MM = 2032,	---	2047	MFHI_MM = 2032,	---
2048	MFLO = 2033,	---	2048	MFLO = 2033,	---
2049	MFLO16_MM = 2034,	---	2049	MFLO16_MM = 2034,	---
2050	MFLO64 = 2035,	---	2050	MFLO64 = 2035,	---
2051	MFLO_DSP = 2036,	---	2051	MFLO_DSP = 2036,	---
2052	MFLO_DSP_MM = 2037,	---	2052	MFLO_DSP_MM = 2037,	---
2053	MFLO_MM = 2038,	---	2053	MFLO_MM = 2038,	---
2054	MFTR = 2039,	---	2054	MFTR = 2039,	---
2055	MINA_D = 2040,	---	2055	MINA_D = 2040,	---
2056	MINA_D_MMR6 = 2041,	---	2056	MINA_D_MMR6 = 2041,	---
2057	MINA_S = 2042,	---	2057	MINA_S = 2042,	---
2058	MINA_S_MMR6 = 2043,	---	2058	MINA_S_MMR6 = 2043,	---
2059	MINI_S_B = 2044,	---	2059	MINI_S_B = 2044,	---
2060	MINI_S_D = 2045,	---	2060	MINI_S_D = 2045,	---
2061	MINI_S_H = 2046,	---	2061	MINI_S_H = 2046,	---
2062	MINI_S_W = 2047,	---	2062	MINI_S_W = 2047,	---
2063	MINI_U_B = 2048,	---	2063	MINI_U_B = 2048,	---
2064	MINI_U_D = 2049,	---	2064	MINI_U_D = 2049,	---
2065	MINI_U_H = 2050,	---	2065	MINI_U_H = 2050,	---
2066	MINI_U_W = 2051,	---	2066	MINI_U_W = 2051,	---
2067	MIN_A_B = 2052,	---	2067	MIN_A_B = 2052,	---
2068	MIN_A_D = 2053,	---	2068	MIN_A_D = 2053,	---
2069	MIN_A_H = 2054,	---	2069	MIN_A_H = 2054,	---
2070	MIN_A_W = 2055,	---	2070	MIN_A_W = 2055,	---
2071	MIN_D = 2056,	---	2071	MIN_D = 2056,	---
2072	MIN_D_MMR6 = 2057,	---	2072	MIN_D_MMR6 = 2057,	---
2073	MIN_S = 2058,	---	2073	MIN_S = 2058,	---
2074	MIN_S_B = 2059,	---	2074	MIN_S_B = 2059,	---
2075	MIN_S_D = 2060,	---	2075	MIN_S_D = 2060,	---
2076	MIN_S_H = 2061,	---	2076	MIN_S_H = 2061,	---
2077	MIN_S_MMR6 = 2062,	---	2077	MIN_S_MMR6 = 2062,	---
2078	MIN_S_W = 2063,	---	2078	MIN_S_W = 2063,	---
2079	MIN_U_B = 2064,	---	2079	MIN_U_B = 2064,	---
2080	MIN_U_D = 2065,	---	2080	MIN_U_D = 2065,	---
2081	MIN_U_H = 2066,	---	2081	MIN_U_H = 2066,	---
2082	MIN_U_W = 2067,	---	2082	MIN_U_W = 2067,	---
2083	MOD = 2068,	---	2083	MOD = 2068,	---
2084	MODSUB = 2069,	---	2084	MODSUB = 2069,	---
2085	MODSUB_MM = 2070,	---	2085	MODSUB_MM = 2070,	---
2086	MODU = 2071,	---	2086	MODU = 2071,	---
2087	MODU_MMR6 = 2072,	---	2087	MODU_MMR6 = 2072,	---
2088	MOD_MMR6 = 2073,	---	2088	MOD_MMR6 = 2073,	---
2089	MOD_S_B = 2074,	---	2089	MOD_S_B = 2074,	---
2090	MOD_S_D = 2075,	---	2090	MOD_S_D = 2075,	---
2091	MOD_S_H = 2076,	---	2091	MOD_S_H = 2076,	---
2092	MOD_S_W = 2077,	---	2092	MOD_S_W = 2077,	---
2093	MOD_U_B = 2078,	---	2093	MOD_U_B = 2078,	---
2094	MOD_U_D = 2079,	---	2094	MOD_U_D = 2079,	---
2095	MOD_U_H = 2080,	---	2095	MOD_U_H = 2080,	---
2096	MOD_U_W = 2081,	---	2096	MOD_U_W = 2081,	---
2097	MOVE16_MM = 2082,	---	2097	MOVE16_MM = 2082,	---
2098	MOVE16_MMR6 = 2083,	---	2098	MOVE16_MMR6 = 2083,	---
2099	MOVEP_MM = 2084,	---	2099	MOVEP_MM = 2084,	---
2100	MOVEP_MMR6 = 2085,	---	2100	MOVEP_MMR6 = 2085,	---
2101	MOVE_V = 2086,	---	2101	MOVE_V = 2086,	---
2102	MOVF_D32 = 2087,	---	2102	MOVF_D32 = 2087,	---
2103	MOVF_D32_MM = 2088,	---	2103	MOVF_D32_MM = 2088,	---
2104	MOVF_D64 = 2089,	---	2104	MOVF_D64 = 2089,	---
2105	MOVF_I = 2090,	---	2105	MOVF_I = 2090,	---
2106	MOVF_I64 = 2091,	---	2106	MOVF_I64 = 2091,	---
2107	MOVF_I_MM = 2092,	---	2107	MOVF_I_MM = 2092,	---
2108	MOVF_S = 2093,	---	2108	MOVF_S = 2093,	---
2109	MOVF_S_MM = 2094,	---	2109	MOVF_S_MM = 2094,	---
2110	MOVN_I64_D64 = 2095,	---	2110	MOVN_I64_D64 = 2095,	---
2111	MOVN_I64_I = 2096,	---	2111	MOVN_I64_I = 2096,	---
2112	MOVN_I64_I64 = 2097,	---	2112	MOVN_I64_I64 = 2097,	---
2113	MOVN_I64_S = 2098,	---	2113	MOVN_I64_S = 2098,	---
2114	MOVN_I_D32 = 2099,	---	2114	MOVN_I_D32 = 2099,	---
2115	MOVN_I_D32_MM = 2100,	---	2115	MOVN_I_D32_MM = 2100,	---
2116	MOVN_I_D64 = 2101,	---	2116	MOVN_I_D64 = 2101,	---
2117	MOVN_I_I = 2102,	---	2117	MOVN_I_I = 2102,	---
2118	MOVN_I_I64 = 2103,	---	2118	MOVN_I_I64 = 2103,	---
2119	MOVN_I_MM = 2104,	---	2119	MOVN_I_MM = 2104,	---
2120	MOVN_I_S = 2105,	---	2120	MOVN_I_S = 2105,	---
2121	MOVN_I_S_MM = 2106,	---	2121	MOVN_I_S_MM = 2106,	---
2122	MOVT_D32 = 2107,	---	2122	MOVT_D32 = 2107,	---
2123	MOVT_D32_MM = 2108,	---	2123	MOVT_D32_MM = 2108,	---
2124	MOVT_D64 = 2109,	---	2124	MOVT_D64 = 2109,	---
2125	MOVT_I = 2110,	---	2125	MOVT_I = 2110,	---
2126	MOVT_I64 = 2111,	---	2126	MOVT_I64 = 2111,	---
2127	MOVT_I_MM = 2112,	---	2127	MOVT_I_MM = 2112,	---
2128	MOVT_S = 2113,	---	2128	MOVT_S = 2113,	---
2129	MOVT_S_MM = 2114,	---	2129	MOVT_S_MM = 2114,	---
2130	MOVZ_I64_D64 = 2115,	---	2130	MOVZ_I64_D64 = 2115,	---
2131	MOVZ_I64_I = 2116,	---	2131	MOVZ_I64_I = 2116,	---
2132	MOVZ_I64_I64 = 2117,	---	2132	MOVZ_I64_I64 = 2117,	---
2133	MOVZ_I64_S = 2118,	---	2133	MOVZ_I64_S = 2118,	---
2134	MOVZ_I_D32 = 2119,	---	2134	MOVZ_I_D32 = 2119,	---
2135	MOVZ_I_D32_MM = 2120,	---	2135	MOVZ_I_D32_MM = 2120,	---
2136	MOVZ_I_D64 = 2121,	---	2136	MOVZ_I_D64 = 2121,	---
2137	MOVZ_I_I = 2122,	---	2137	MOVZ_I_I = 2122,	---
2138	MOVZ_I_I64 = 2123,	---	2138	MOVZ_I_I64 = 2123,	---
2139	MOVZ_I_MM = 2124,	---	2139	MOVZ_I_MM = 2124,	---
2140	MOVZ_I_S = 2125,	---	2140	MOVZ_I_S = 2125,	---
2141	MOVZ_I_S_MM = 2126,	---	2141	MOVZ_I_S_MM = 2126,	---
2142	MSUB = 2127,	---	2142	MSUB = 2127,	---
2143	MSUBF_D = 2128,	---	2143	MSUBF_D = 2128,	---
2144	MSUBF_D_MMR6 = 2129,	---	2144	MSUBF_D_MMR6 = 2129,	---
2145	MSUBF_S = 2130,	---	2145	MSUBF_S = 2130,	---
2146	MSUBF_S_MMR6 = 2131,	---	2146	MSUBF_S_MMR6 = 2131,	---
2147	MSUBR_Q_H = 2132,	---	2147	MSUBR_Q_H = 2132,	---
2148	MSUBR_Q_W = 2133,	---	2148	MSUBR_Q_W = 2133,	---
2149	MSUBU = 2134,	---	2149	MSUBU = 2134,	---
2150	MSUBU_DSP = 2135,	---	2150	MSUBU_DSP = 2135,	---
2151	MSUBU_DSP_MM = 2136,	---	2151	MSUBU_DSP_MM = 2136,	---
2152	MSUBU_MM = 2137,	---	2152	MSUBU_MM = 2137,	---
2153	MSUBV_B = 2138,	---	2153	MSUBV_B = 2138,	---
2154	MSUBV_D = 2139,	---	2154	MSUBV_D = 2139,	---
2155	MSUBV_H = 2140,	---	2155	MSUBV_H = 2140,	---
2156	MSUBV_W = 2141,	---	2156	MSUBV_W = 2141,	---
2157	MSUB_D32 = 2142,	---	2157	MSUB_D32 = 2142,	---
2158	MSUB_D32_MM = 2143,	---	2158	MSUB_D32_MM = 2143,	---
2159	MSUB_D64 = 2144,	---	2159	MSUB_D64 = 2144,	---
2160	MSUB_DSP = 2145,	---	2160	MSUB_DSP = 2145,	---
2161	MSUB_DSP_MM = 2146,	---	2161	MSUB_DSP_MM = 2146,	---
2162	MSUB_MM = 2147,	---	2162	MSUB_MM = 2147,	---
2163	MSUB_Q_H = 2148,	---	2163	MSUB_Q_H = 2148,	---
2164	MSUB_Q_W = 2149,	---	2164	MSUB_Q_W = 2149,	---
2165	MSUB_S = 2150,	---	2165	MSUB_S = 2150,	---
2166	MSUB_S_MM = 2151,	---	2166	MSUB_S_MM = 2151,	---
2167	MTC0 = 2152,	---	2167	MTC0 = 2152,	---
2168	MTC0_MMR6 = 2153,	---	2168	MTC0_MMR6 = 2153,	---
2169	MTC1 = 2154,	---	2169	MTC1 = 2154,	---
2170	MTC1_D64 = 2155,	---	2170	MTC1_D64 = 2155,	---
2171	MTC1_D64_MM = 2156,	---	2171	MTC1_D64_MM = 2156,	---
2172	MTC1_MM = 2157,	---	2172	MTC1_MM = 2157,	---
2173	MTC1_MMR6 = 2158,	---	2173	MTC1_MMR6 = 2158,	---
2174	MTC2 = 2159,	---	2174	MTC2 = 2159,	---
2175	MTC2_MMR6 = 2160,	---	2175	MTC2_MMR6 = 2160,	---
2176	MTGC0 = 2161,	---	2176	MTGC0 = 2161,	---
2177	MTGC0_MM = 2162,	---	2177	MTGC0_MM = 2162,	---
2178	MTHC0_MMR6 = 2163,	---	2178	MTHC0_MMR6 = 2163,	---
2179	MTHC1_D32 = 2164,	---	2179	MTHC1_D32 = 2164,	---
2180	MTHC1_D32_MM = 2165,	---	2180	MTHC1_D32_MM = 2165,	---
2181	MTHC1_D64 = 2166,	---	2181	MTHC1_D64 = 2166,	---
2182	MTHC1_D64_MM = 2167,	---	2182	MTHC1_D64_MM = 2167,	---
2183	MTHC2_MMR6 = 2168,	---	2183	MTHC2_MMR6 = 2168,	---
2184	MTHGC0 = 2169,	---	2184	MTHGC0 = 2169,	---
2185	MTHGC0_MM = 2170,	---	2185	MTHGC0_MM = 2170,	---
2186	MTHI = 2171,	---	2186	MTHI = 2171,	---
2187	MTHI64 = 2172,	---	2187	MTHI64 = 2172,	---
2188	MTHI_DSP = 2173,	---	2188	MTHI_DSP = 2173,	---
2189	MTHI_DSP_MM = 2174,	---	2189	MTHI_DSP_MM = 2174,	---
2190	MTHI_MM = 2175,	---	2190	MTHI_MM = 2175,	---
2191	MTHLIP = 2176,	---	2191	MTHLIP = 2176,	---
2192	MTHLIP_MM = 2177,	---	2192	MTHLIP_MM = 2177,	---
2193	MTLO = 2178,	---	2193	MTLO = 2178,	---
2194	MTLO64 = 2179,	---	2194	MTLO64 = 2179,	---
2195	MTLO_DSP = 2180,	---	2195	MTLO_DSP = 2180,	---
2196	MTLO_DSP_MM = 2181,	---	2196	MTLO_DSP_MM = 2181,	---
2197	MTLO_MM = 2182,	---	2197	MTLO_MM = 2182,	---
2198	MTM0 = 2183,	---	2198	MTM0 = 2183,	---
2199	MTM1 = 2184,	---	2199	MTM1 = 2184,	---
2200	MTM2 = 2185,	---	2200	MTM2 = 2185,	---
2201	MTP0 = 2186,	---	2201	MTP0 = 2186,	---
2202	MTP1 = 2187,	---	2202	MTP1 = 2187,	---
2203	MTP2 = 2188,	---	2203	MTP2 = 2188,	---
2204	MTTR = 2189,	---	2204	MTTR = 2189,	---
2205	MUH = 2190,	---	2205	MUH = 2190,	---
2206	MUHU = 2191,	---	2206	MUHU = 2191,	---
2207	MUHU_MMR6 = 2192,	---	2207	MUHU_MMR6 = 2192,	---
2208	MUH_MMR6 = 2193,	---	2208	MUH_MMR6 = 2193,	---
2209	MUL = 2194,	---	2209	MUL = 2194,	---
2210	MULEQ_S_W_PHL = 2195,	---	2210	MULEQ_S_W_PHL = 2195,	---
2211	MULEQ_S_W_PHL_MM = 2196,	---	2211	MULEQ_S_W_PHL_MM = 2196,	---
2212	MULEQ_S_W_PHR = 2197,	---	2212	MULEQ_S_W_PHR = 2197,	---
2213	MULEQ_S_W_PHR_MM = 2198,	---	2213	MULEQ_S_W_PHR_MM = 2198,	---
2214	MULEU_S_PH_QBL = 2199,	---	2214	MULEU_S_PH_QBL = 2199,	---
2215	MULEU_S_PH_QBL_MM = 2200,	---	2215	MULEU_S_PH_QBL_MM = 2200,	---
2216	MULEU_S_PH_QBR = 2201,	---	2216	MULEU_S_PH_QBR = 2201,	---
2217	MULEU_S_PH_QBR_MM = 2202,	---	2217	MULEU_S_PH_QBR_MM = 2202,	---
2218	MULQ_RS_PH = 2203,	---	2218	MULQ_RS_PH = 2203,	---
2219	MULQ_RS_PH_MM = 2204,	---	2219	MULQ_RS_PH_MM = 2204,	---
2220	MULQ_RS_W = 2205,	---	2220	MULQ_RS_W = 2205,	---
2221	MULQ_RS_W_MMR2 = 2206,	---	2221	MULQ_RS_W_MMR2 = 2206,	---
2222	MULQ_S_PH = 2207,	---	2222	MULQ_S_PH = 2207,	---
2223	MULQ_S_PH_MMR2 = 2208,	---	2223	MULQ_S_PH_MMR2 = 2208,	---
2224	MULQ_S_W = 2209,	---	2224	MULQ_S_W = 2209,	---
2225	MULQ_S_W_MMR2 = 2210,	---	2225	MULQ_S_W_MMR2 = 2210,	---
2226	MULR_PS64 = 2211,	---	2226	MULR_PS64 = 2211,	---
2227	MULR_Q_H = 2212,	---	2227	MULR_Q_H = 2212,	---
2228	MULR_Q_W = 2213,	---	2228	MULR_Q_W = 2213,	---
2229	MULSAQ_S_W_PH = 2214,	---	2229	MULSAQ_S_W_PH = 2214,	---
2230	MULSAQ_S_W_PH_MM = 2215,	---	2230	MULSAQ_S_W_PH_MM = 2215,	---
2231	MULSA_W_PH = 2216,	---	2231	MULSA_W_PH = 2216,	---
2232	MULSA_W_PH_MMR2 = 2217,	---	2232	MULSA_W_PH_MMR2 = 2217,	---
2233	MULT = 2218,	---	2233	MULT = 2218,	---
2234	MULTU_DSP = 2219,	---	2234	MULTU_DSP = 2219,	---
2235	MULTU_DSP_MM = 2220,	---	2235	MULTU_DSP_MM = 2220,	---
2236	MULT_DSP = 2221,	---	2236	MULT_DSP = 2221,	---
2237	MULT_DSP_MM = 2222,	---	2237	MULT_DSP_MM = 2222,	---
2238	MULT_MM = 2223,	---	2238	MULT_MM = 2223,	---
2239	MULTu = 2224,	---	2239	MULTu = 2224,	---
2240	MULTu_MM = 2225,	---	2240	MULTu_MM = 2225,	---
2241	MULU = 2226,	---	2241	MULU = 2226,	---
2242	MULU_MMR6 = 2227,	---	2242	MULU_MMR6 = 2227,	---
2243	MULV_B = 2228,	---	2243	MULV_B = 2228,	---
2244	MULV_D = 2229,	---	2244	MULV_D = 2229,	---
2245	MULV_H = 2230,	---	2245	MULV_H = 2230,	---
2246	MULV_W = 2231,	---	2246	MULV_W = 2231,	---
2247	MUL_MM = 2232,	---	2247	MUL_MM = 2232,	---
2248	MUL_MMR6 = 2233,	---	2248	MUL_MMR6 = 2233,	---
2249	MUL_PH = 2234,	---	2249	MUL_PH = 2234,	---
2250	MUL_PH_MMR2 = 2235,	---	2250	MUL_PH_MMR2 = 2235,	---
2251	MUL_Q_H = 2236,	---	2251	MUL_Q_H = 2236,	---
2252	MUL_Q_W = 2237,	---	2252	MUL_Q_W = 2237,	---
2253	MUL_R6 = 2238,	---	2253	MUL_R6 = 2238,	---
2254	MUL_S_PH = 2239,	---	2254	MUL_S_PH = 2239,	---
2255	MUL_S_PH_MMR2 = 2240,	---	2255	MUL_S_PH_MMR2 = 2240,	---
2256	Mfhi16 = 2241,	---	2256	Mfhi16 = 2241,	---
2257	Mflo16 = 2242,	---	2257	Mflo16 = 2242,	---
2258	Move32R16 = 2243,	---	2258	Move32R16 = 2243,	---
2259	MoveR3216 = 2244,	---	2259	MoveR3216 = 2244,	---
2260	NLOC_B = 2245,	---	2260	NLOC_B = 2245,	---
2261	NLOC_D = 2246,	---	2261	NLOC_D = 2246,	---
2262	NLOC_H = 2247,	---	2262	NLOC_H = 2247,	---
2263	NLOC_W = 2248,	---	2263	NLOC_W = 2248,	---
2264	NLZC_B = 2249,	---	2264	NLZC_B = 2249,	---
2265	NLZC_D = 2250,	---	2265	NLZC_D = 2250,	---
2266	NLZC_H = 2251,	---	2266	NLZC_H = 2251,	---
2267	NLZC_W = 2252,	---	2267	NLZC_W = 2252,	---
2268	NMADD_D32 = 2253,	---	2268	NMADD_D32 = 2253,	---
2269	NMADD_D32_MM = 2254,	---	2269	NMADD_D32_MM = 2254,	---
2270	NMADD_D64 = 2255,	---	2270	NMADD_D64 = 2255,	---
2271	NMADD_S = 2256,	---	2271	NMADD_S = 2256,	---
2272	NMADD_S_MM = 2257,	---	2272	NMADD_S_MM = 2257,	---
2273	NMSUB_D32 = 2258,	---	2273	NMSUB_D32 = 2258,	---
2274	NMSUB_D32_MM = 2259,	---	2274	NMSUB_D32_MM = 2259,	---
2275	NMSUB_D64 = 2260,	---	2275	NMSUB_D64 = 2260,	---
2276	NMSUB_S = 2261,	---	2276	NMSUB_S = 2261,	---
2277	NMSUB_S_MM = 2262,	---	2277	NMSUB_S_MM = 2262,	---
2278	NOR = 2263,	---	2278	NOR = 2263,	---
2279	NOR64 = 2264,	---	2279	NOR64 = 2264,	---
2280	NORI_B = 2265,	---	2280	NORI_B = 2265,	---
2281	NOR_MM = 2266,	---	2281	NOR_MM = 2266,	---
2282	NOR_MMR6 = 2267,	---	2282	NOR_MMR6 = 2267,	---
2283	NOR_V = 2268,	---	2283	NOR_V = 2268,	---
2284	NOT16_MM = 2269,	---	2284	NOT16_MM = 2269,	---
2285	NOT16_MMR6 = 2270,	---	2285	NOT16_MMR6 = 2270,	---
2286	NegRxRy16 = 2271,	---	2286	NegRxRy16 = 2271,	---
2287	NotRxRy16 = 2272,	---	2287	NotRxRy16 = 2272,	---
2288	OR = 2273,	---	2288	OR = 2273,	---
2289	OR16_MM = 2274,	---	2289	OR16_MM = 2274,	---
2290	OR16_MMR6 = 2275,	---	2290	OR16_MMR6 = 2275,	---
2291	OR64 = 2276,	---	2291	OR64 = 2276,	---
2292	ORI_B = 2277,	---	2292	ORI_B = 2277,	---
2293	ORI_MMR6 = 2278,	---	2293	ORI_MMR6 = 2278,	---
2294	OR_MM = 2279,	---	2294	OR_MM = 2279,	---
2295	OR_MMR6 = 2280,	---	2295	OR_MMR6 = 2280,	---
2296	OR_V = 2281,	---	2296	OR_V = 2281,	---
2297	ORi = 2282,	---	2297	ORi = 2282,	---
2298	ORi64 = 2283,	---	2298	ORi64 = 2283,	---
2299	ORi_MM = 2284,	---	2299	ORi_MM = 2284,	---
2300	OrRxRxRy16 = 2285,	---	2300	OrRxRxRy16 = 2285,	---
2301	PACKRL_PH = 2286,	---	2301	PACKRL_PH = 2286,	---
2302	PACKRL_PH_MM = 2287,	---	2302	PACKRL_PH_MM = 2287,	---
2303	PAUSE = 2288,	---	2303	PAUSE = 2288,	---
2304	PAUSE_MM = 2289,	---	2304	PAUSE_MM = 2289,	---
2305	PAUSE_MMR6 = 2290,	---	2305	PAUSE_MMR6 = 2290,	---
2306	PCKEV_B = 2291,	---	2306	PCKEV_B = 2291,	---
2307	PCKEV_D = 2292,	---	2307	PCKEV_D = 2292,	---
2308	PCKEV_H = 2293,	---	2308	PCKEV_H = 2293,	---
2309	PCKEV_W = 2294,	---	2309	PCKEV_W = 2294,	---
2310	PCKOD_B = 2295,	---	2310	PCKOD_B = 2295,	---
2311	PCKOD_D = 2296,	---	2311	PCKOD_D = 2296,	---
2312	PCKOD_H = 2297,	---	2312	PCKOD_H = 2297,	---
2313	PCKOD_W = 2298,	---	2313	PCKOD_W = 2298,	---
2314	PCNT_B = 2299,	---	2314	PCNT_B = 2299,	---
2315	PCNT_D = 2300,	---	2315	PCNT_D = 2300,	---
2316	PCNT_H = 2301,	---	2316	PCNT_H = 2301,	---
2317	PCNT_W = 2302,	---	2317	PCNT_W = 2302,	---
2318	PICK_PH = 2303,	---	2318	PICK_PH = 2303,	---
2319	PICK_PH_MM = 2304,	---	2319	PICK_PH_MM = 2304,	---
2320	PICK_QB = 2305,	---	2320	PICK_QB = 2305,	---
2321	PICK_QB_MM = 2306,	---	2321	PICK_QB_MM = 2306,	---
2322	PLL_PS64 = 2307,	---	2322	PLL_PS64 = 2307,	---
2323	PLU_PS64 = 2308,	---	2323	PLU_PS64 = 2308,	---
2324	POP = 2309,	---	2324	POP = 2309,	---
2325	PRECEQU_PH_QBL = 2310,	---	2325	PRECEQU_PH_QBL = 2310,	---
2326	PRECEQU_PH_QBLA = 2311,	---	2326	PRECEQU_PH_QBLA = 2311,	---
2327	PRECEQU_PH_QBLA_MM = 2312,	---	2327	PRECEQU_PH_QBLA_MM = 2312,	---
2328	PRECEQU_PH_QBL_MM = 2313,	---	2328	PRECEQU_PH_QBL_MM = 2313,	---
2329	PRECEQU_PH_QBR = 2314,	---	2329	PRECEQU_PH_QBR = 2314,	---
2330	PRECEQU_PH_QBRA = 2315,	---	2330	PRECEQU_PH_QBRA = 2315,	---
2331	PRECEQU_PH_QBRA_MM = 2316,	---	2331	PRECEQU_PH_QBRA_MM = 2316,	---
2332	PRECEQU_PH_QBR_MM = 2317,	---	2332	PRECEQU_PH_QBR_MM = 2317,	---
2333	PRECEQ_W_PHL = 2318,	---	2333	PRECEQ_W_PHL = 2318,	---
2334	PRECEQ_W_PHL_MM = 2319,	---	2334	PRECEQ_W_PHL_MM = 2319,	---
2335	PRECEQ_W_PHR = 2320,	---	2335	PRECEQ_W_PHR = 2320,	---
2336	PRECEQ_W_PHR_MM = 2321,	---	2336	PRECEQ_W_PHR_MM = 2321,	---
2337	PRECEU_PH_QBL = 2322,	---	2337	PRECEU_PH_QBL = 2322,	---
2338	PRECEU_PH_QBLA = 2323,	---	2338	PRECEU_PH_QBLA = 2323,	---
2339	PRECEU_PH_QBLA_MM = 2324,	---	2339	PRECEU_PH_QBLA_MM = 2324,	---
2340	PRECEU_PH_QBL_MM = 2325,	---	2340	PRECEU_PH_QBL_MM = 2325,	---
2341	PRECEU_PH_QBR = 2326,	---	2341	PRECEU_PH_QBR = 2326,	---
2342	PRECEU_PH_QBRA = 2327,	---	2342	PRECEU_PH_QBRA = 2327,	---
2343	PRECEU_PH_QBRA_MM = 2328,	---	2343	PRECEU_PH_QBRA_MM = 2328,	---
2344	PRECEU_PH_QBR_MM = 2329,	---	2344	PRECEU_PH_QBR_MM = 2329,	---
2345	PRECRQU_S_QB_PH = 2330,	---	2345	PRECRQU_S_QB_PH = 2330,	---
2346	PRECRQU_S_QB_PH_MM = 2331,	---	2346	PRECRQU_S_QB_PH_MM = 2331,	---
2347	PRECRQ_PH_W = 2332,	---	2347	PRECRQ_PH_W = 2332,	---
2348	PRECRQ_PH_W_MM = 2333,	---	2348	PRECRQ_PH_W_MM = 2333,	---
2349	PRECRQ_QB_PH = 2334,	---	2349	PRECRQ_QB_PH = 2334,	---
2350	PRECRQ_QB_PH_MM = 2335,	---	2350	PRECRQ_QB_PH_MM = 2335,	---
2351	PRECRQ_RS_PH_W = 2336,	---	2351	PRECRQ_RS_PH_W = 2336,	---
2352	PRECRQ_RS_PH_W_MM = 2337,	---	2352	PRECRQ_RS_PH_W_MM = 2337,	---
2353	PRECR_QB_PH = 2338,	---	2353	PRECR_QB_PH = 2338,	---
2354	PRECR_QB_PH_MMR2 = 2339,	---	2354	PRECR_QB_PH_MMR2 = 2339,	---
2355	PRECR_SRA_PH_W = 2340,	---	2355	PRECR_SRA_PH_W = 2340,	---
2356	PRECR_SRA_PH_W_MMR2 = 2341,	---	2356	PRECR_SRA_PH_W_MMR2 = 2341,	---
2357	PRECR_SRA_R_PH_W = 2342,	---	2357	PRECR_SRA_R_PH_W = 2342,	---
2358	PRECR_SRA_R_PH_W_MMR2 = 2343,	---	2358	PRECR_SRA_R_PH_W_MMR2 = 2343,	---
2359	PREF = 2344,	---	2359	PREF = 2344,	---
2360	PREFE = 2345,	---	2360	PREFE = 2345,	---
2361	PREFE_MM = 2346,	---	2361	PREFE_MM = 2346,	---
2362	PREFX_MM = 2347,	---	2362	PREFX_MM = 2347,	---
2363	PREF_MM = 2348,	---	2363	PREF_MM = 2348,	---
2364	PREF_MMR6 = 2349,	---	2364	PREF_MMR6 = 2349,	---
2365	PREF_R6 = 2350,	---	2365	PREF_R6 = 2350,	---
2366	PREPEND = 2351,	---	2366	PREPEND = 2351,	---
2367	PREPEND_MMR2 = 2352,	---	2367	PREPEND_MMR2 = 2352,	---
2368	PUL_PS64 = 2353,	---	2368	PUL_PS64 = 2353,	---
2369	PUU_PS64 = 2354,	---	2369	PUU_PS64 = 2354,	---
2370	RADDU_W_QB = 2355,	---	2370	RADDU_W_QB = 2355,	---
2371	RADDU_W_QB_MM = 2356,	---	2371	RADDU_W_QB_MM = 2356,	---
2372	RDDSP = 2357,	---	2372	RDDSP = 2357,	---
2373	RDDSP_MM = 2358,	---	2373	RDDSP_MM = 2358,	---
2374	RDHWR = 2359,	---	2374	RDHWR = 2359,	---
2375	RDHWR64 = 2360,	---	2375	RDHWR64 = 2360,	---
2376	RDHWR_MM = 2361,	---	2376	RDHWR_MM = 2361,	---
2377	RDHWR_MMR6 = 2362,	---	2377	RDHWR_MMR6 = 2362,	---
2378	RDPGPR_MMR6 = 2363,	---	2378	RDPGPR_MMR6 = 2363,	---
2379	RECIP_D32 = 2364,	---	2379	RECIP_D32 = 2364,	---
2380	RECIP_D32_MM = 2365,	---	2380	RECIP_D32_MM = 2365,	---
2381	RECIP_D64 = 2366,	---	2381	RECIP_D64 = 2366,	---
2382	RECIP_D64_MM = 2367,	---	2382	RECIP_D64_MM = 2367,	---
2383	RECIP_S = 2368,	---	2383	RECIP_S = 2368,	---
2384	RECIP_S_MM = 2369,	---	2384	RECIP_S_MM = 2369,	---
2385	REPLV_PH = 2370,	---	2385	REPLV_PH = 2370,	---
2386	REPLV_PH_MM = 2371,	---	2386	REPLV_PH_MM = 2371,	---
2387	REPLV_QB = 2372,	---	2387	REPLV_QB = 2372,	---
2388	REPLV_QB_MM = 2373,	---	2388	REPLV_QB_MM = 2373,	---
2389	REPL_PH = 2374,	---	2389	REPL_PH = 2374,	---
2390	REPL_PH_MM = 2375,	---	2390	REPL_PH_MM = 2375,	---
2391	REPL_QB = 2376,	---	2391	REPL_QB = 2376,	---
2392	REPL_QB_MM = 2377,	---	2392	REPL_QB_MM = 2377,	---
2393	RINT_D = 2378,	---	2393	RINT_D = 2378,	---
2394	RINT_D_MMR6 = 2379,	---	2394	RINT_D_MMR6 = 2379,	---
2395	RINT_S = 2380,	---	2395	RINT_S = 2380,	---
2396	RINT_S_MMR6 = 2381,	---	2396	RINT_S_MMR6 = 2381,	---
2397	ROTR = 2382,	---	2397	ROTR = 2382,	---
2398	ROTRV = 2383,	---	2398	ROTRV = 2383,	---
2399	ROTRV_MM = 2384,	---	2399	ROTRV_MM = 2384,	---
2400	ROTR_MM = 2385,	---	2400	ROTR_MM = 2385,	---
2401	ROUND_L_D64 = 2386,	---	2401	ROUND_L_D64 = 2386,	---
2402	ROUND_L_D_MMR6 = 2387,	---	2402	ROUND_L_D_MMR6 = 2387,	---
2403	ROUND_L_S = 2388,	---	2403	ROUND_L_S = 2388,	---
2404	ROUND_L_S_MMR6 = 2389,	---	2404	ROUND_L_S_MMR6 = 2389,	---
2405	ROUND_W_D32 = 2390,	---	2405	ROUND_W_D32 = 2390,	---
2406	ROUND_W_D64 = 2391,	---	2406	ROUND_W_D64 = 2391,	---
2407	ROUND_W_D_MMR6 = 2392,	---	2407	ROUND_W_D_MMR6 = 2392,	---
2408	ROUND_W_MM = 2393,	---	2408	ROUND_W_MM = 2393,	---
2409	ROUND_W_S = 2394,	---	2409	ROUND_W_S = 2394,	---
2410	ROUND_W_S_MM = 2395,	---	2410	ROUND_W_S_MM = 2395,	---
2411	ROUND_W_S_MMR6 = 2396,	---	2411	ROUND_W_S_MMR6 = 2396,	---
2412	RSQRT_D32 = 2397,	---	2412	RSQRT_D32 = 2397,	---
2413	RSQRT_D32_MM = 2398,	---	2413	RSQRT_D32_MM = 2398,	---
2414	RSQRT_D64 = 2399,	---	2414	RSQRT_D64 = 2399,	---
2415	RSQRT_D64_MM = 2400,	---	2415	RSQRT_D64_MM = 2400,	---
2416	RSQRT_S = 2401,	---	2416	RSQRT_S = 2401,	---
2417	RSQRT_S_MM = 2402,	---	2417	RSQRT_S_MM = 2402,	---
2418	Restore16 = 2403,	---	2418	Restore16 = 2403,	---
2419	RestoreX16 = 2404,	---	2419	RestoreX16 = 2404,	---
2420	SAA = 2405,	---	2420	SAA = 2405,	---
2421	SAAD = 2406,	---	2421	SAAD = 2406,	---
2422	SAT_S_B = 2407,	---	2422	SAT_S_B = 2407,	---
2423	SAT_S_D = 2408,	---	2423	SAT_S_D = 2408,	---
2424	SAT_S_H = 2409,	---	2424	SAT_S_H = 2409,	---
2425	SAT_S_W = 2410,	---	2425	SAT_S_W = 2410,	---
2426	SAT_U_B = 2411,	---	2426	SAT_U_B = 2411,	---
2427	SAT_U_D = 2412,	---	2427	SAT_U_D = 2412,	---
2428	SAT_U_H = 2413,	---	2428	SAT_U_H = 2413,	---
2429	SAT_U_W = 2414,	---	2429	SAT_U_W = 2414,	---
2430	SB = 2415,	---	2430	SB = 2415,	---
2431	SB16_MM = 2416,	---	2431	SB16_MM = 2416,	---
2432	SB16_MMR6 = 2417,	---	2432	SB16_MMR6 = 2417,	---
2433	SB64 = 2418,	---	2433	SB64 = 2418,	---
2434	SBE = 2419,	---	2434	SBE = 2419,	---
2435	SBE_MM = 2420,	---	2435	SBE_MM = 2420,	---
2436	SB_MM = 2421,	---	2436	SB_MM = 2421,	---
2437	SB_MMR6 = 2422,	---	2437	SB_MMR6 = 2422,	---
2438	SC = 2423,	---	2438	SC = 2423,	---
2439	SC64 = 2424,	---	2439	SC64 = 2424,	---
2440	SC64_R6 = 2425,	---	2440	SC64_R6 = 2425,	---
2441	SCD = 2426,	---	2441	SCD = 2426,	---
2442	SCD_R6 = 2427,	---	2442	SCD_R6 = 2427,	---
2443	SCE = 2428,	---	2443	SCE = 2428,	---
2444	SCE_MM = 2429,	---	2444	SCE_MM = 2429,	---
2445	SC_MM = 2430,	---	2445	SC_MM = 2430,	---
2446	SC_MMR6 = 2431,	---	2446	SC_MMR6 = 2431,	---
2447	SC_R6 = 2432,	---	2447	SC_R6 = 2432,	---
2448	SD = 2433,	---	2448	SD = 2433,	---
2449	SDBBP = 2434,	---	2449	SDBBP = 2434,	---
2450	SDBBP16_MM = 2435,	---	2450	SDBBP16_MM = 2435,	---
2451	SDBBP16_MMR6 = 2436,	---	2451	SDBBP16_MMR6 = 2436,	---
2452	SDBBP_MM = 2437,	---	2452	SDBBP_MM = 2437,	---
2453	SDBBP_MMR6 = 2438,	---	2453	SDBBP_MMR6 = 2438,	---
2454	SDBBP_R6 = 2439,	---	2454	SDBBP_R6 = 2439,	---
2455	SDC1 = 2440,	---	2455	SDC1 = 2440,	---
2456	SDC164 = 2441,	---	2456	SDC164 = 2441,	---
2457	SDC1_D64_MMR6 = 2442,	---	2457	SDC1_D64_MMR6 = 2442,	---
2458	SDC1_MM_D32 = 2443,	---	2458	SDC1_MM_D32 = 2443,	---
2459	SDC1_MM_D64 = 2444,	---	2459	SDC1_MM_D64 = 2444,	---
2460	SDC2 = 2445,	---	2460	SDC2 = 2445,	---
2461	SDC2_MMR6 = 2446,	---	2461	SDC2_MMR6 = 2446,	---
2462	SDC2_R6 = 2447,	---	2462	SDC2_R6 = 2447,	---
2463	SDC3 = 2448,	---	2463	SDC3 = 2448,	---
2464	SDIV = 2449,	---	2464	SDIV = 2449,	---
2465	SDIV_MM = 2450,	---	2465	SDIV_MM = 2450,	---
2466	SDL = 2451,	---	2466	SDL = 2451,	---
2467	SDR = 2452,	---	2467	SDR = 2452,	---
2468	SDXC1 = 2453,	---	2468	SDXC1 = 2453,	---
2469	SDXC164 = 2454,	---	2469	SDXC164 = 2454,	---
2470	SEB = 2455,	---	2470	SEB = 2455,	---
2471	SEB64 = 2456,	---	2471	SEB64 = 2456,	---
2472	SEB_MM = 2457,	---	2472	SEB_MM = 2457,	---
2473	SEH = 2458,	---	2473	SEH = 2458,	---
2474	SEH64 = 2459,	---	2474	SEH64 = 2459,	---
2475	SEH_MM = 2460,	---	2475	SEH_MM = 2460,	---
2476	SELEQZ = 2461,	---	2476	SELEQZ = 2461,	---
2477	SELEQZ64 = 2462,	---	2477	SELEQZ64 = 2462,	---
2478	SELEQZ_D = 2463,	---	2478	SELEQZ_D = 2463,	---
2479	SELEQZ_D_MMR6 = 2464,	---	2479	SELEQZ_D_MMR6 = 2464,	---
2480	SELEQZ_MMR6 = 2465,	---	2480	SELEQZ_MMR6 = 2465,	---
2481	SELEQZ_S = 2466,	---	2481	SELEQZ_S = 2466,	---
2482	SELEQZ_S_MMR6 = 2467,	---	2482	SELEQZ_S_MMR6 = 2467,	---
2483	SELNEZ = 2468,	---	2483	SELNEZ = 2468,	---
2484	SELNEZ64 = 2469,	---	2484	SELNEZ64 = 2469,	---
2485	SELNEZ_D = 2470,	---	2485	SELNEZ_D = 2470,	---
2486	SELNEZ_D_MMR6 = 2471,	---	2486	SELNEZ_D_MMR6 = 2471,	---
2487	SELNEZ_MMR6 = 2472,	---	2487	SELNEZ_MMR6 = 2472,	---
2488	SELNEZ_S = 2473,	---	2488	SELNEZ_S = 2473,	---
2489	SELNEZ_S_MMR6 = 2474,	---	2489	SELNEZ_S_MMR6 = 2474,	---
2490	SEL_D = 2475,	---	2490	SEL_D = 2475,	---
2491	SEL_D_MMR6 = 2476,	---	2491	SEL_D_MMR6 = 2476,	---
2492	SEL_S = 2477,	---	2492	SEL_S = 2477,	---
2493	SEL_S_MMR6 = 2478,	---	2493	SEL_S_MMR6 = 2478,	---
2494	SEQ = 2479,	---	2494	SEQ = 2479,	---
2495	SEQi = 2480,	---	2495	SEQi = 2480,	---
2496	SH = 2481,	---	2496	SH = 2481,	---
2497	SH16_MM = 2482,	---	2497	SH16_MM = 2482,	---
2498	SH16_MMR6 = 2483,	---	2498	SH16_MMR6 = 2483,	---
2499	SH64 = 2484,	---	2499	SH64 = 2484,	---
2500	SHE = 2485,	---	2500	SHE = 2485,	---
2501	SHE_MM = 2486,	---	2501	SHE_MM = 2486,	---
2502	SHF_B = 2487,	---	2502	SHF_B = 2487,	---
2503	SHF_H = 2488,	---	2503	SHF_H = 2488,	---
2504	SHF_W = 2489,	---	2504	SHF_W = 2489,	---
2505	SHILO = 2490,	---	2505	SHILO = 2490,	---
2506	SHILOV = 2491,	---	2506	SHILOV = 2491,	---
2507	SHILOV_MM = 2492,	---	2507	SHILOV_MM = 2492,	---
2508	SHILO_MM = 2493,	---	2508	SHILO_MM = 2493,	---
2509	SHLLV_PH = 2494,	---	2509	SHLLV_PH = 2494,	---
2510	SHLLV_PH_MM = 2495,	---	2510	SHLLV_PH_MM = 2495,	---
2511	SHLLV_QB = 2496,	---	2511	SHLLV_QB = 2496,	---
2512	SHLLV_QB_MM = 2497,	---	2512	SHLLV_QB_MM = 2497,	---
2513	SHLLV_S_PH = 2498,	---	2513	SHLLV_S_PH = 2498,	---
2514	SHLLV_S_PH_MM = 2499,	---	2514	SHLLV_S_PH_MM = 2499,	---
2515	SHLLV_S_W = 2500,	---	2515	SHLLV_S_W = 2500,	---
2516	SHLLV_S_W_MM = 2501,	---	2516	SHLLV_S_W_MM = 2501,	---
2517	SHLL_PH = 2502,	---	2517	SHLL_PH = 2502,	---
2518	SHLL_PH_MM = 2503,	---	2518	SHLL_PH_MM = 2503,	---
2519	SHLL_QB = 2504,	---	2519	SHLL_QB = 2504,	---
2520	SHLL_QB_MM = 2505,	---	2520	SHLL_QB_MM = 2505,	---
2521	SHLL_S_PH = 2506,	---	2521	SHLL_S_PH = 2506,	---
2522	SHLL_S_PH_MM = 2507,	---	2522	SHLL_S_PH_MM = 2507,	---
2523	SHLL_S_W = 2508,	---	2523	SHLL_S_W = 2508,	---
2524	SHLL_S_W_MM = 2509,	---	2524	SHLL_S_W_MM = 2509,	---
2525	SHRAV_PH = 2510,	---	2525	SHRAV_PH = 2510,	---
2526	SHRAV_PH_MM = 2511,	---	2526	SHRAV_PH_MM = 2511,	---
2527	SHRAV_QB = 2512,	---	2527	SHRAV_QB = 2512,	---
2528	SHRAV_QB_MMR2 = 2513,	---	2528	SHRAV_QB_MMR2 = 2513,	---
2529	SHRAV_R_PH = 2514,	---	2529	SHRAV_R_PH = 2514,	---
2530	SHRAV_R_PH_MM = 2515,	---	2530	SHRAV_R_PH_MM = 2515,	---
2531	SHRAV_R_QB = 2516,	---	2531	SHRAV_R_QB = 2516,	---
2532	SHRAV_R_QB_MMR2 = 2517,	---	2532	SHRAV_R_QB_MMR2 = 2517,	---
2533	SHRAV_R_W = 2518,	---	2533	SHRAV_R_W = 2518,	---
2534	SHRAV_R_W_MM = 2519,	---	2534	SHRAV_R_W_MM = 2519,	---
2535	SHRA_PH = 2520,	---	2535	SHRA_PH = 2520,	---
2536	SHRA_PH_MM = 2521,	---	2536	SHRA_PH_MM = 2521,	---
2537	SHRA_QB = 2522,	---	2537	SHRA_QB = 2522,	---
2538	SHRA_QB_MMR2 = 2523,	---	2538	SHRA_QB_MMR2 = 2523,	---
2539	SHRA_R_PH = 2524,	---	2539	SHRA_R_PH = 2524,	---
2540	SHRA_R_PH_MM = 2525,	---	2540	SHRA_R_PH_MM = 2525,	---
2541	SHRA_R_QB = 2526,	---	2541	SHRA_R_QB = 2526,	---
2542	SHRA_R_QB_MMR2 = 2527,	---	2542	SHRA_R_QB_MMR2 = 2527,	---
2543	SHRA_R_W = 2528,	---	2543	SHRA_R_W = 2528,	---
2544	SHRA_R_W_MM = 2529,	---	2544	SHRA_R_W_MM = 2529,	---
2545	SHRLV_PH = 2530,	---	2545	SHRLV_PH = 2530,	---
2546	SHRLV_PH_MMR2 = 2531,	---	2546	SHRLV_PH_MMR2 = 2531,	---
2547	SHRLV_QB = 2532,	---	2547	SHRLV_QB = 2532,	---
2548	SHRLV_QB_MM = 2533,	---	2548	SHRLV_QB_MM = 2533,	---
2549	SHRL_PH = 2534,	---	2549	SHRL_PH = 2534,	---
2550	SHRL_PH_MMR2 = 2535,	---	2550	SHRL_PH_MMR2 = 2535,	---
2551	SHRL_QB = 2536,	---	2551	SHRL_QB = 2536,	---
2552	SHRL_QB_MM = 2537,	---	2552	SHRL_QB_MM = 2537,	---
2553	SH_MM = 2538,	---	2553	SH_MM = 2538,	---
2554	SH_MMR6 = 2539,	---	2554	SH_MMR6 = 2539,	---
2555	SIGRIE = 2540,	---	2555	SIGRIE = 2540,	---
2556	SIGRIE_MMR6 = 2541,	---	2556	SIGRIE_MMR6 = 2541,	---
2557	SLDI_B = 2542,	---	2557	SLDI_B = 2542,	---
2558	SLDI_D = 2543,	---	2558	SLDI_D = 2543,	---
2559	SLDI_H = 2544,	---	2559	SLDI_H = 2544,	---
2560	SLDI_W = 2545,	---	2560	SLDI_W = 2545,	---
2561	SLD_B = 2546,	---	2561	SLD_B = 2546,	---
2562	SLD_D = 2547,	---	2562	SLD_D = 2547,	---
2563	SLD_H = 2548,	---	2563	SLD_H = 2548,	---
2564	SLD_W = 2549,	---	2564	SLD_W = 2549,	---
2565	SLL = 2550,	---	2565	SLL = 2550,	---
2566	SLL16_MM = 2551,	---	2566	SLL16_MM = 2551,	---
2567	SLL16_MMR6 = 2552,	---	2567	SLL16_MMR6 = 2552,	---
2568	SLL64_32 = 2553,	---	2568	SLL64_32 = 2553,	---
2569	SLL64_64 = 2554,	---	2569	SLL64_64 = 2554,	---
2570	SLLI_B = 2555,	---	2570	SLLI_B = 2555,	---
2571	SLLI_D = 2556,	---	2571	SLLI_D = 2556,	---
2572	SLLI_H = 2557,	---	2572	SLLI_H = 2557,	---
2573	SLLI_W = 2558,	---	2573	SLLI_W = 2558,	---
2574	SLLV = 2559,	---	2574	SLLV = 2559,	---
2575	SLLV_MM = 2560,	---	2575	SLLV_MM = 2560,	---
2576	SLL_B = 2561,	---	2576	SLL_B = 2561,	---
2577	SLL_D = 2562,	---	2577	SLL_D = 2562,	---
2578	SLL_H = 2563,	---	2578	SLL_H = 2563,	---
2579	SLL_MM = 2564,	---	2579	SLL_MM = 2564,	---
2580	SLL_MMR6 = 2565,	---	2580	SLL_MMR6 = 2565,	---
2581	SLL_W = 2566,	---	2581	SLL_W = 2566,	---
2582	SLT = 2567,	---	2582	SLT = 2567,	---
2583	SLT64 = 2568,	---	2583	SLT64 = 2568,	---
2584	SLT_MM = 2569,	---	2584	SLT_MM = 2569,	---
2585	SLTi = 2570,	---	2585	SLTi = 2570,	---
2586	SLTi64 = 2571,	---	2586	SLTi64 = 2571,	---
2587	SLTi_MM = 2572,	---	2587	SLTi_MM = 2572,	---
2588	SLTiu = 2573,	---	2588	SLTiu = 2573,	---
2589	SLTiu64 = 2574,	---	2589	SLTiu64 = 2574,	---
2590	SLTiu_MM = 2575,	---	2590	SLTiu_MM = 2575,	---
2591	SLTu = 2576,	---	2591	SLTu = 2576,	---
2592	SLTu64 = 2577,	---	2592	SLTu64 = 2577,	---
2593	SLTu_MM = 2578,	---	2593	SLTu_MM = 2578,	---
2594	SNE = 2579,	---	2594	SNE = 2579,	---
2595	SNEi = 2580,	---	2595	SNEi = 2580,	---
2596	SPLATI_B = 2581,	---	2596	SPLATI_B = 2581,	---
2597	SPLATI_D = 2582,	---	2597	SPLATI_D = 2582,	---
2598	SPLATI_H = 2583,	---	2598	SPLATI_H = 2583,	---
2599	SPLATI_W = 2584,	---	2599	SPLATI_W = 2584,	---
2600	SPLAT_B = 2585,	---	2600	SPLAT_B = 2585,	---
2601	SPLAT_D = 2586,	---	2601	SPLAT_D = 2586,	---
2602	SPLAT_H = 2587,	---	2602	SPLAT_H = 2587,	---
2603	SPLAT_W = 2588,	---	2603	SPLAT_W = 2588,	---
2604	SRA = 2589,	---	2604	SRA = 2589,	---
2605	SRAI_B = 2590,	---	2605	SRAI_B = 2590,	---
2606	SRAI_D = 2591,	---	2606	SRAI_D = 2591,	---
2607	SRAI_H = 2592,	---	2607	SRAI_H = 2592,	---
2608	SRAI_W = 2593,	---	2608	SRAI_W = 2593,	---
2609	SRARI_B = 2594,	---	2609	SRARI_B = 2594,	---
2610	SRARI_D = 2595,	---	2610	SRARI_D = 2595,	---
2611	SRARI_H = 2596,	---	2611	SRARI_H = 2596,	---
2612	SRARI_W = 2597,	---	2612	SRARI_W = 2597,	---
2613	SRAR_B = 2598,	---	2613	SRAR_B = 2598,	---
2614	SRAR_D = 2599,	---	2614	SRAR_D = 2599,	---
2615	SRAR_H = 2600,	---	2615	SRAR_H = 2600,	---
2616	SRAR_W = 2601,	---	2616	SRAR_W = 2601,	---
2617	SRAV = 2602,	---	2617	SRAV = 2602,	---
2618	SRAV_MM = 2603,	---	2618	SRAV_MM = 2603,	---
2619	SRA_B = 2604,	---	2619	SRA_B = 2604,	---
2620	SRA_D = 2605,	---	2620	SRA_D = 2605,	---
2621	SRA_H = 2606,	---	2621	SRA_H = 2606,	---
2622	SRA_MM = 2607,	---	2622	SRA_MM = 2607,	---
2623	SRA_W = 2608,	---	2623	SRA_W = 2608,	---
2624	SRL = 2609,	---	2624	SRL = 2609,	---
2625	SRL16_MM = 2610,	---	2625	SRL16_MM = 2610,	---
2626	SRL16_MMR6 = 2611,	---	2626	SRL16_MMR6 = 2611,	---
2627	SRLI_B = 2612,	---	2627	SRLI_B = 2612,	---
2628	SRLI_D = 2613,	---	2628	SRLI_D = 2613,	---
2629	SRLI_H = 2614,	---	2629	SRLI_H = 2614,	---
2630	SRLI_W = 2615,	---	2630	SRLI_W = 2615,	---
2631	SRLRI_B = 2616,	---	2631	SRLRI_B = 2616,	---
2632	SRLRI_D = 2617,	---	2632	SRLRI_D = 2617,	---
2633	SRLRI_H = 2618,	---	2633	SRLRI_H = 2618,	---
2634	SRLRI_W = 2619,	---	2634	SRLRI_W = 2619,	---
2635	SRLR_B = 2620,	---	2635	SRLR_B = 2620,	---
2636	SRLR_D = 2621,	---	2636	SRLR_D = 2621,	---
2637	SRLR_H = 2622,	---	2637	SRLR_H = 2622,	---
2638	SRLR_W = 2623,	---	2638	SRLR_W = 2623,	---
2639	SRLV = 2624,	---	2639	SRLV = 2624,	---
2640	SRLV_MM = 2625,	---	2640	SRLV_MM = 2625,	---
2641	SRL_B = 2626,	---	2641	SRL_B = 2626,	---
2642	SRL_D = 2627,	---	2642	SRL_D = 2627,	---
2643	SRL_H = 2628,	---	2643	SRL_H = 2628,	---
2644	SRL_MM = 2629,	---	2644	SRL_MM = 2629,	---
2645	SRL_W = 2630,	---	2645	SRL_W = 2630,	---
2646	SSNOP = 2631,	---	2646	SSNOP = 2631,	---
2647	SSNOP_MM = 2632,	---	2647	SSNOP_MM = 2632,	---
2648	SSNOP_MMR6 = 2633,	---	2648	SSNOP_MMR6 = 2633,	---
2649	ST_B = 2634,	---	2649	ST_B = 2634,	---
2650	ST_D = 2635,	---	2650	ST_D = 2635,	---
2651	ST_H = 2636,	---	2651	ST_H = 2636,	---
2652	ST_W = 2637,	---	2652	ST_W = 2637,	---
2653	SUB = 2638,	---	2653	SUB = 2638,	---
2654	SUBQH_PH = 2639,	---	2654	SUBQH_PH = 2639,	---
2655	SUBQH_PH_MMR2 = 2640,	---	2655	SUBQH_PH_MMR2 = 2640,	---
2656	SUBQH_R_PH = 2641,	---	2656	SUBQH_R_PH = 2641,	---
2657	SUBQH_R_PH_MMR2 = 2642,	---	2657	SUBQH_R_PH_MMR2 = 2642,	---
2658	SUBQH_R_W = 2643,	---	2658	SUBQH_R_W = 2643,	---
2659	SUBQH_R_W_MMR2 = 2644,	---	2659	SUBQH_R_W_MMR2 = 2644,	---
2660	SUBQH_W = 2645,	---	2660	SUBQH_W = 2645,	---
2661	SUBQH_W_MMR2 = 2646,	---	2661	SUBQH_W_MMR2 = 2646,	---
2662	SUBQ_PH = 2647,	---	2662	SUBQ_PH = 2647,	---
2663	SUBQ_PH_MM = 2648,	---	2663	SUBQ_PH_MM = 2648,	---
2664	SUBQ_S_PH = 2649,	---	2664	SUBQ_S_PH = 2649,	---
2665	SUBQ_S_PH_MM = 2650,	---	2665	SUBQ_S_PH_MM = 2650,	---
2666	SUBQ_S_W = 2651,	---	2666	SUBQ_S_W = 2651,	---
2667	SUBQ_S_W_MM = 2652,	---	2667	SUBQ_S_W_MM = 2652,	---
2668	SUBSUS_U_B = 2653,	---	2668	SUBSUS_U_B = 2653,	---
2669	SUBSUS_U_D = 2654,	---	2669	SUBSUS_U_D = 2654,	---
2670	SUBSUS_U_H = 2655,	---	2670	SUBSUS_U_H = 2655,	---
2671	SUBSUS_U_W = 2656,	---	2671	SUBSUS_U_W = 2656,	---
2672	SUBSUU_S_B = 2657,	---	2672	SUBSUU_S_B = 2657,	---
2673	SUBSUU_S_D = 2658,	---	2673	SUBSUU_S_D = 2658,	---
2674	SUBSUU_S_H = 2659,	---	2674	SUBSUU_S_H = 2659,	---
2675	SUBSUU_S_W = 2660,	---	2675	SUBSUU_S_W = 2660,	---
2676	SUBS_S_B = 2661,	---	2676	SUBS_S_B = 2661,	---
2677	SUBS_S_D = 2662,	---	2677	SUBS_S_D = 2662,	---
2678	SUBS_S_H = 2663,	---	2678	SUBS_S_H = 2663,	---
2679	SUBS_S_W = 2664,	---	2679	SUBS_S_W = 2664,	---
2680	SUBS_U_B = 2665,	---	2680	SUBS_U_B = 2665,	---
2681	SUBS_U_D = 2666,	---	2681	SUBS_U_D = 2666,	---
2682	SUBS_U_H = 2667,	---	2682	SUBS_U_H = 2667,	---
2683	SUBS_U_W = 2668,	---	2683	SUBS_U_W = 2668,	---
2684	SUBU16_MM = 2669,	---	2684	SUBU16_MM = 2669,	---
2685	SUBU16_MMR6 = 2670,	---	2685	SUBU16_MMR6 = 2670,	---
2686	SUBUH_QB = 2671,	---	2686	SUBUH_QB = 2671,	---
2687	SUBUH_QB_MMR2 = 2672,	---	2687	SUBUH_QB_MMR2 = 2672,	---
2688	SUBUH_R_QB = 2673,	---	2688	SUBUH_R_QB = 2673,	---
2689	SUBUH_R_QB_MMR2 = 2674,	---	2689	SUBUH_R_QB_MMR2 = 2674,	---
2690	SUBU_MMR6 = 2675,	---	2690	SUBU_MMR6 = 2675,	---
2691	SUBU_PH = 2676,	---	2691	SUBU_PH = 2676,	---
2692	SUBU_PH_MMR2 = 2677,	---	2692	SUBU_PH_MMR2 = 2677,	---
2693	SUBU_QB = 2678,	---	2693	SUBU_QB = 2678,	---
2694	SUBU_QB_MM = 2679,	---	2694	SUBU_QB_MM = 2679,	---
2695	SUBU_S_PH = 2680,	---	2695	SUBU_S_PH = 2680,	---
2696	SUBU_S_PH_MMR2 = 2681,	---	2696	SUBU_S_PH_MMR2 = 2681,	---
2697	SUBU_S_QB = 2682,	---	2697	SUBU_S_QB = 2682,	---
2698	SUBU_S_QB_MM = 2683,	---	2698	SUBU_S_QB_MM = 2683,	---
2699	SUBVI_B = 2684,	---	2699	SUBVI_B = 2684,	---
2700	SUBVI_D = 2685,	---	2700	SUBVI_D = 2685,	---
2701	SUBVI_H = 2686,	---	2701	SUBVI_H = 2686,	---
2702	SUBVI_W = 2687,	---	2702	SUBVI_W = 2687,	---
2703	SUBV_B = 2688,	---	2703	SUBV_B = 2688,	---
2704	SUBV_D = 2689,	---	2704	SUBV_D = 2689,	---
2705	SUBV_H = 2690,	---	2705	SUBV_H = 2690,	---
2706	SUBV_W = 2691,	---	2706	SUBV_W = 2691,	---
2707	SUB_MM = 2692,	---	2707	SUB_MM = 2692,	---
2708	SUB_MMR6 = 2693,	---	2708	SUB_MMR6 = 2693,	---
2709	SUBu = 2694,	---	2709	SUBu = 2694,	---
2710	SUBu_MM = 2695,	---	2710	SUBu_MM = 2695,	---
2711	SUXC1 = 2696,	---	2711	SUXC1 = 2696,	---
2712	SUXC164 = 2697,	---	2712	SUXC164 = 2697,	---
2713	SUXC1_MM = 2698,	---	2713	SUXC1_MM = 2698,	---
2714	SW = 2699,	---	2714	SW = 2699,	---
2715	SW16_MM = 2700,	---	2715	SW16_MM = 2700,	---
2716	SW16_MMR6 = 2701,	---	2716	SW16_MMR6 = 2701,	---
2717	SW64 = 2702,	---	2717	SW64 = 2702,	---
2718	SWC1 = 2703,	---	2718	SWC1 = 2703,	---
2719	SWC1_MM = 2704,	---	2719	SWC1_MM = 2704,	---
2720	SWC2 = 2705,	---	2720	SWC2 = 2705,	---
2721	SWC2_MMR6 = 2706,	---	2721	SWC2_MMR6 = 2706,	---
2722	SWC2_R6 = 2707,	---	2722	SWC2_R6 = 2707,	---
2723	SWC3 = 2708,	---	2723	SWC3 = 2708,	---
2724	SWDSP = 2709,	---	2724	SWDSP = 2709,	---
2725	SWDSP_MM = 2710,	---	2725	SWDSP_MM = 2710,	---
2726	SWE = 2711,	---	2726	SWE = 2711,	---
2727	SWE_MM = 2712,	---	2727	SWE_MM = 2712,	---
2728	SWL = 2713,	---	2728	SWL = 2713,	---
2729	SWL64 = 2714,	---	2729	SWL64 = 2714,	---
2730	SWLE = 2715,	---	2730	SWLE = 2715,	---
2731	SWLE_MM = 2716,	---	2731	SWLE_MM = 2716,	---
2732	SWL_MM = 2717,	---	2732	SWL_MM = 2717,	---
2733	SWM16_MM = 2718,	---	2733	SWM16_MM = 2718,	---
2734	SWM16_MMR6 = 2719,	---	2734	SWM16_MMR6 = 2719,	---
2735	SWM32_MM = 2720,	---	2735	SWM32_MM = 2720,	---
2736	SWP_MM = 2721,	---	2736	SWP_MM = 2721,	---
2737	SWR = 2722,	---	2737	SWR = 2722,	---
2738	SWR64 = 2723,	---	2738	SWR64 = 2723,	---
2739	SWRE = 2724,	---	2739	SWRE = 2724,	---
2740	SWRE_MM = 2725,	---	2740	SWRE_MM = 2725,	---
2741	SWR_MM = 2726,	---	2741	SWR_MM = 2726,	---
2742	SWSP_MM = 2727,	---	2742	SWSP_MM = 2727,	---
2743	SWSP_MMR6 = 2728,	---	2743	SWSP_MMR6 = 2728,	---
2744	SWXC1 = 2729,	---	2744	SWXC1 = 2729,	---
2745	SWXC1_MM = 2730,	---	2745	SWXC1_MM = 2730,	---
2746	SW_MM = 2731,	---	2746	SW_MM = 2731,	---
2747	SW_MMR6 = 2732,	---	2747	SW_MMR6 = 2732,	---
2748	SYNC = 2733,	---	2748	SYNC = 2733,	---
2749	SYNCI = 2734,	---	2749	SYNCI = 2734,	---
2750	SYNCI_MM = 2735,	---	2750	SYNCI_MM = 2735,	---
2751	SYNCI_MMR6 = 2736,	---	2751	SYNCI_MMR6 = 2736,	---
2752	SYNC_MM = 2737,	---	2752	SYNC_MM = 2737,	---
2753	SYNC_MMR6 = 2738,	---	2753	SYNC_MMR6 = 2738,	---
2754	SYSCALL = 2739,	---	2754	SYSCALL = 2739,	---
2755	SYSCALL_MM = 2740,	---	2755	SYSCALL_MM = 2740,	---
2756	Save16 = 2741,	---	2756	Save16 = 2741,	---
2757	SaveX16 = 2742,	---	2757	SaveX16 = 2742,	---
2758	SbRxRyOffMemX16 = 2743,	---	2758	SbRxRyOffMemX16 = 2743,	---
2759	SebRx16 = 2744,	---	2759	SebRx16 = 2744,	---
2760	SehRx16 = 2745,	---	2760	SehRx16 = 2745,	---
2761	ShRxRyOffMemX16 = 2746,	---	2761	ShRxRyOffMemX16 = 2746,	---
2762	SllX16 = 2747,	---	2762	SllX16 = 2747,	---
2763	SllvRxRy16 = 2748,	---	2763	SllvRxRy16 = 2748,	---
2764	SltRxRy16 = 2749,	---	2764	SltRxRy16 = 2749,	---
2765	SltiRxImm16 = 2750,	---	2765	SltiRxImm16 = 2750,	---
2766	SltiRxImmX16 = 2751,	---	2766	SltiRxImmX16 = 2751,	---
2767	SltiuRxImm16 = 2752,	---	2767	SltiuRxImm16 = 2752,	---
2768	SltiuRxImmX16 = 2753,	---	2768	SltiuRxImmX16 = 2753,	---
2769	SltuRxRy16 = 2754,	---	2769	SltuRxRy16 = 2754,	---
2770	SraX16 = 2755,	---	2770	SraX16 = 2755,	---
2771	SravRxRy16 = 2756,	---	2771	SravRxRy16 = 2756,	---
2772	SrlX16 = 2757,	---	2772	SrlX16 = 2757,	---
2773	SrlvRxRy16 = 2758,	---	2773	SrlvRxRy16 = 2758,	---
2774	SubuRxRyRz16 = 2759,	---	2774	SubuRxRyRz16 = 2759,	---
2775	SwRxRyOffMemX16 = 2760,	---	2775	SwRxRyOffMemX16 = 2760,	---
2776	SwRxSpImmX16 = 2761,	---	2776	SwRxSpImmX16 = 2761,	---
2777	TEQ = 2762,	---	2777	TEQ = 2762,	---
2778	TEQI = 2763,	---	2778	TEQI = 2763,	---
2779	TEQI_MM = 2764,	---	2779	TEQI_MM = 2764,	---
2780	TEQ_MM = 2765,	---	2780	TEQ_MM = 2765,	---
2781	TGE = 2766,	---	2781	TGE = 2766,	---
2782	TGEI = 2767,	---	2782	TGEI = 2767,	---
2783	TGEIU = 2768,	---	2783	TGEIU = 2768,	---
2784	TGEIU_MM = 2769,	---	2784	TGEIU_MM = 2769,	---
2785	TGEI_MM = 2770,	---	2785	TGEI_MM = 2770,	---
2786	TGEU = 2771,	---	2786	TGEU = 2771,	---
2787	TGEU_MM = 2772,	---	2787	TGEU_MM = 2772,	---
2788	TGE_MM = 2773,	---	2788	TGE_MM = 2773,	---
2789	TLBGINV = 2774,	---	2789	TLBGINV = 2774,	---
2790	TLBGINVF = 2775,	---	2790	TLBGINVF = 2775,	---
2791	TLBGINVF_MM = 2776,	---	2791	TLBGINVF_MM = 2776,	---
2792	TLBGINV_MM = 2777,	---	2792	TLBGINV_MM = 2777,	---
2793	TLBGP = 2778,	---	2793	TLBGP = 2778,	---
2794	TLBGP_MM = 2779,	---	2794	TLBGP_MM = 2779,	---
2795	TLBGR = 2780,	---	2795	TLBGR = 2780,	---
2796	TLBGR_MM = 2781,	---	2796	TLBGR_MM = 2781,	---
2797	TLBGWI = 2782,	---	2797	TLBGWI = 2782,	---
2798	TLBGWI_MM = 2783,	---	2798	TLBGWI_MM = 2783,	---
2799	TLBGWR = 2784,	---	2799	TLBGWR = 2784,	---
2800	TLBGWR_MM = 2785,	---	2800	TLBGWR_MM = 2785,	---
2801	TLBINV = 2786,	---	2801	TLBINV = 2786,	---
2802	TLBINVF = 2787,	---	2802	TLBINVF = 2787,	---
2803	TLBINVF_MMR6 = 2788,	---	2803	TLBINVF_MMR6 = 2788,	---
2804	TLBINV_MMR6 = 2789,	---	2804	TLBINV_MMR6 = 2789,	---
2805	TLBP = 2790,	---	2805	TLBP = 2790,	---
2806	TLBP_MM = 2791,	---	2806	TLBP_MM = 2791,	---
2807	TLBR = 2792,	---	2807	TLBR = 2792,	---
2808	TLBR_MM = 2793,	---	2808	TLBR_MM = 2793,	---
2809	TLBWI = 2794,	---	2809	TLBWI = 2794,	---
2810	TLBWI_MM = 2795,	---	2810	TLBWI_MM = 2795,	---
2811	TLBWR = 2796,	---	2811	TLBWR = 2796,	---
2812	TLBWR_MM = 2797,	---	2812	TLBWR_MM = 2797,	---
2813	TLT = 2798,	---	2813	TLT = 2798,	---
2814	TLTI = 2799,	---	2814	TLTI = 2799,	---
2815	TLTIU_MM = 2800,	---	2815	TLTIU_MM = 2800,	---
2816	TLTI_MM = 2801,	---	2816	TLTI_MM = 2801,	---
2817	TLTU = 2802,	---	2817	TLTU = 2802,	---
2818	TLTU_MM = 2803,	---	2818	TLTU_MM = 2803,	---
2819	TLT_MM = 2804,	---	2819	TLT_MM = 2804,	---
2820	TNE = 2805,	---	2820	TNE = 2805,	---
2821	TNEI = 2806,	---	2821	TNEI = 2806,	---
2822	TNEI_MM = 2807,	---	2822	TNEI_MM = 2807,	---
2823	TNE_MM = 2808,	---	2823	TNE_MM = 2808,	---
2824	TRUNC_L_D64 = 2809,	---	2824	TRUNC_L_D64 = 2809,	---
2825	TRUNC_L_D_MMR6 = 2810,	---	2825	TRUNC_L_D_MMR6 = 2810,	---
2826	TRUNC_L_S = 2811,	---	2826	TRUNC_L_S = 2811,	---
2827	TRUNC_L_S_MMR6 = 2812,	---	2827	TRUNC_L_S_MMR6 = 2812,	---
2828	TRUNC_W_D32 = 2813,	---	2828	TRUNC_W_D32 = 2813,	---
2829	TRUNC_W_D64 = 2814,	---	2829	TRUNC_W_D64 = 2814,	---
2830	TRUNC_W_D_MMR6 = 2815,	---	2830	TRUNC_W_D_MMR6 = 2815,	---
2831	TRUNC_W_MM = 2816,	---	2831	TRUNC_W_MM = 2816,	---
2832	TRUNC_W_S = 2817,	---	2832	TRUNC_W_S = 2817,	---
2833	TRUNC_W_S_MM = 2818,	---	2833	TRUNC_W_S_MM = 2818,	---
2834	TRUNC_W_S_MMR6 = 2819,	---	2834	TRUNC_W_S_MMR6 = 2819,	---
2835	TTLTIU = 2820,	---	2835	TTLTIU = 2820,	---
2836	UDIV = 2821,	---	2836	UDIV = 2821,	---
2837	UDIV_MM = 2822,	---	2837	UDIV_MM = 2822,	---
2838	V3MULU = 2823,	---	2838	V3MULU = 2823,	---
2839	VMM0 = 2824,	---	2839	VMM0 = 2824,	---
2840	VMULU = 2825,	---	2840	VMULU = 2825,	---
2841	VSHF_B = 2826,	---	2841	VSHF_B = 2826,	---
2842	VSHF_D = 2827,	---	2842	VSHF_D = 2827,	---
2843	VSHF_H = 2828,	---	2843	VSHF_H = 2828,	---
2844	VSHF_W = 2829,	---	2844	VSHF_W = 2829,	---
2845	WAIT = 2830,	---	2845	WAIT = 2830,	---
2846	WAIT_MM = 2831,	---	2846	WAIT_MM = 2831,	---
2847	WAIT_MMR6 = 2832,	---	2847	WAIT_MMR6 = 2832,	---
2848	WRDSP = 2833,	---	2848	WRDSP = 2833,	---
2849	WRDSP_MM = 2834,	---	2849	WRDSP_MM = 2834,	---
2850	WRPGPR_MMR6 = 2835,	---	2850	WRPGPR_MMR6 = 2835,	---
2851	WSBH = 2836,	---	2851	WSBH = 2836,	---
2852	WSBH_MM = 2837,	---	2852	WSBH_MM = 2837,	---
2853	WSBH_MMR6 = 2838,	---	2853	WSBH_MMR6 = 2838,	---
2854	XOR = 2839,	---	2854	XOR = 2839,	---
2855	XOR16_MM = 2840,	---	2855	XOR16_MM = 2840,	---
2856	XOR16_MMR6 = 2841,	---	2856	XOR16_MMR6 = 2841,	---
2857	XOR64 = 2842,	---	2857	XOR64 = 2842,	---
2858	XORI_B = 2843,	---	2858	XORI_B = 2843,	---
2859	XORI_MMR6 = 2844,	---	2859	XORI_MMR6 = 2844,	---
2860	XOR_MM = 2845,	---	2860	XOR_MM = 2845,	---
2861	XOR_MMR6 = 2846,	---	2861	XOR_MMR6 = 2846,	---
2862	XOR_V = 2847,	---	2862	XOR_V = 2847,	---
2863	XORi = 2848,	---	2863	XORi = 2848,	---
2864	XORi64 = 2849,	---	2864	XORi64 = 2849,	---
2865	XORi_MM = 2850,	---	2865	XORi_MM = 2850,	---
2866	XorRxRxRy16 = 2851,	---	2866	XorRxRxRy16 = 2851,	---
2867	YIELD = 2852,	---	2867	YIELD = 2852,	---
2868	INSTRUCTION_LIST_END = 2853	---	2868	INSTRUCTION_LIST_END = 2853	---
2869	};	---	2869	};	---
2870		---	2870		---
2871	} // end namespace Mips	---	2871	} // end namespace Mips	---
2872	} // end namespace llvm	---	2872	} // end namespace llvm	---
2873	#endif // GET_INSTRINFO_ENUM	---	2873	#endif // GET_INSTRINFO_ENUM	---
2874		---	2874		---
2875	#ifdef GET_INSTRINFO_SCHED_ENUM	---	2875	#ifdef GET_INSTRINFO_SCHED_ENUM	---
2876	#undef GET_INSTRINFO_SCHED_ENUM	---	2876	#undef GET_INSTRINFO_SCHED_ENUM	---
2877	namespace llvm {	---	2877	namespace llvm {	---
2878		---	2878		---
2879	namespace Mips {	---	2879	namespace Mips {	---
2880	namespace Sched {	---	2880	namespace Sched {	---
2881	enum {	---	2881	enum {	---
2882	NoInstrModel = 0,	---	2882	NoInstrModel = 0,	---
2883	IIPseudo = 1,	---	2883	IIPseudo = 1,	---
2884	II_B = 2,	---	2884	II_B = 2,	---
2885	II_BCCZAL = 3,	---	2885	II_BCCZAL = 3,	---
2886	II_MTC1 = 4,	---	2886	II_MTC1 = 4,	---
2887	II_MFC1 = 5,	---	2887	II_MFC1 = 5,	---
2888	II_JALR = 6,	---	2888	II_JALR = 6,	---
2889	II_JAL = 7,	---	2889	II_JAL = 7,	---
2890	II_CVT = 8,	---	2890	II_CVT = 8,	---
2891	II_DMULT = 9,	---	2891	II_DMULT = 9,	---
2892	II_DMULTU = 10,	---	2892	II_DMULTU = 10,	---
2893	II_DDIV = 11,	---	2893	II_DDIV = 11,	---
2894	II_DDIVU = 12,	---	2894	II_DDIVU = 12,	---
2895	II_IndirectBranchPseudo = 13,	---	2895	II_IndirectBranchPseudo = 13,	---
2896	II_MADD = 14,	---	2896	II_MADD = 14,	---
2897	II_MADDU = 15,	---	2897	II_MADDU = 15,	---
2898	II_MFHI_MFLO = 16,	---	2898	II_MFHI_MFLO = 16,	---
2899	II_MSUB = 17,	---	2899	II_MSUB = 17,	---
2900	II_MSUBU = 18,	---	2900	II_MSUBU = 18,	---
2901	II_MTHI_MTLO = 19,	---	2901	II_MTHI_MTLO = 19,	---
2902	II_MULT = 20,	---	2902	II_MULT = 20,	---
2903	II_MULTU = 21,	---	2903	II_MULTU = 21,	---
2904	II_ReturnPseudo = 22,	---	2904	II_ReturnPseudo = 22,	---
2905	II_DIV = 23,	---	2905	II_DIV = 23,	---
2906	II_DIVU = 24,	---	2906	II_DIVU = 24,	---
2907	II_J = 25,	---	2907	II_J = 25,	---
2908	II_JR = 26,	---	2908	II_JR = 26,	---
2909	II_TRAP = 27,	---	2909	II_TRAP = 27,	---
2910	II_ADD = 28,	---	2910	II_ADD = 28,	---
2911	II_ADDIUPC = 29,	---	2911	II_ADDIUPC = 29,	---
2912	II_ADDIU = 30,	---	2912	II_ADDIU = 30,	---
2913	II_ADDR_PS = 31,	---	2913	II_ADDR_PS = 31,	---
2914	II_ADDU = 32,	---	2914	II_ADDU = 32,	---
2915	II_ADDI = 33,	---	2915	II_ADDI = 33,	---
2916	II_ALIGN = 34,	---	2916	II_ALIGN = 34,	---
2917	II_ALUIPC = 35,	---	2917	II_ALUIPC = 35,	---
2918	II_AND = 36,	---	2918	II_AND = 36,	---
2919	II_ANDI = 37,	---	2919	II_ANDI = 37,	---
2920	II_AUI = 38,	---	2920	II_AUI = 38,	---
2921	II_AUIPC = 39,	---	2921	II_AUIPC = 39,	---
2922	IIM16Alu = 40,	---	2922	IIM16Alu = 40,	---
2923	II_BADDU = 41,	---	2923	II_BADDU = 41,	---
2924	II_BC = 42,	---	2924	II_BC = 42,	---
2925	II_BALC = 43,	---	2925	II_BALC = 43,	---
2926	II_BBIT = 44,	---	2926	II_BBIT = 44,	---
2927	II_BC1CCZ = 45,	---	2927	II_BC1CCZ = 45,	---
2928	II_BC1F = 46,	---	2928	II_BC1F = 46,	---
2929	II_BC1FL = 47,	---	2929	II_BC1FL = 47,	---
2930	II_BC1T = 48,	---	2930	II_BC1T = 48,	---
2931	II_BC1TL = 49,	---	2931	II_BC1TL = 49,	---
2932	II_BC2CCZ = 50,	---	2932	II_BC2CCZ = 50,	---
2933	II_BCC = 51,	---	2933	II_BCC = 51,	---
2934	II_BCCC = 52,	---	2934	II_BCCC = 52,	---
2935	II_BCCZ = 53,	---	2935	II_BCCZ = 53,	---
2936	II_BCCZC = 54,	---	2936	II_BCCZC = 54,	---
2937	II_BCCZALS = 55,	---	2937	II_BCCZALS = 55,	---
2938	II_BITSWAP = 56,	---	2938	II_BITSWAP = 56,	---
2939	II_BREAK = 57,	---	2939	II_BREAK = 57,	---
2940	II_CACHE = 58,	---	2940	II_CACHE = 58,	---
2941	II_CACHEE = 59,	---	2941	II_CACHEE = 59,	---
2942	II_CEIL = 60,	---	2942	II_CEIL = 60,	---
2943	II_CFC1 = 61,	---	2943	II_CFC1 = 61,	---
2944	II_CFC2 = 62,	---	2944	II_CFC2 = 62,	---
2945	II_INS = 63,	---	2945	II_INS = 63,	---
2946	II_CLASS_D = 64,	---	2946	II_CLASS_D = 64,	---
2947	II_CLASS_S = 65,	---	2947	II_CLASS_S = 65,	---
2948	II_CLO = 66,	---	2948	II_CLO = 66,	---
2949	II_CLZ = 67,	---	2949	II_CLZ = 67,	---
2950	II_CMP_CC_D = 68,	---	2950	II_CMP_CC_D = 68,	---
2951	II_CMP_CC_S = 69,	---	2951	II_CMP_CC_S = 69,	---
2952	II_CRC32B = 70,	---	2952	II_CRC32B = 70,	---
2953	II_CRC32CB = 71,	---	2953	II_CRC32CB = 71,	---
2954	II_CRC32CD = 72,	---	2954	II_CRC32CD = 72,	---
2955	II_CRC32CH = 73,	---	2955	II_CRC32CH = 73,	---
2956	II_CRC32CW = 74,	---	2956	II_CRC32CW = 74,	---
2957	II_CRC32D = 75,	---	2957	II_CRC32D = 75,	---
2958	II_CRC32H = 76,	---	2958	II_CRC32H = 76,	---
2959	II_CRC32W = 77,	---	2959	II_CRC32W = 77,	---
2960	II_CTC1 = 78,	---	2960	II_CTC1 = 78,	---
2961	II_CTC2 = 79,	---	2961	II_CTC2 = 79,	---
2962	II_C_CC_D = 80,	---	2962	II_C_CC_D = 80,	---
2963	II_C_CC_S = 81,	---	2963	II_C_CC_S = 81,	---
2964	II_DADD = 82,	---	2964	II_DADD = 82,	---
2965	II_DADDI = 83,	---	2965	II_DADDI = 83,	---
2966	II_DADDIU = 84,	---	2966	II_DADDIU = 84,	---
2967	II_DADDU = 85,	---	2967	II_DADDU = 85,	---
2968	II_DAHI = 86,	---	2968	II_DAHI = 86,	---
2969	II_DALIGN = 87,	---	2969	II_DALIGN = 87,	---
2970	II_DATI = 88,	---	2970	II_DATI = 88,	---
2971	II_DAUI = 89,	---	2971	II_DAUI = 89,	---
2972	II_DBITSWAP = 90,	---	2972	II_DBITSWAP = 90,	---
2973	II_DCLO = 91,	---	2973	II_DCLO = 91,	---
2974	II_DCLZ = 92,	---	2974	II_DCLZ = 92,	---
2975	II_DERET = 93,	---	2975	II_DERET = 93,	---
2976	II_EXT = 94,	---	2976	II_EXT = 94,	---
2977	II_DI = 95,	---	2977	II_DI = 95,	---
2978	II_DLSA = 96,	---	2978	II_DLSA = 96,	---
2979	II_DMFC0 = 97,	---	2979	II_DMFC0 = 97,	---
2980	II_DMFC1 = 98,	---	2980	II_DMFC1 = 98,	---
2981	II_DMFC2 = 99,	---	2981	II_DMFC2 = 99,	---
2982	II_DMFGC0 = 100,	---	2982	II_DMFGC0 = 100,	---
2983	II_DMOD = 101,	---	2983	II_DMOD = 101,	---
2984	II_DMODU = 102,	---	2984	II_DMODU = 102,	---
2985	II_DMT = 103,	---	2985	II_DMT = 103,	---
2986	II_DMTC0 = 104,	---	2986	II_DMTC0 = 104,	---
2987	II_DMTC1 = 105,	---	2987	II_DMTC1 = 105,	---
2988	II_DMTC2 = 106,	---	2988	II_DMTC2 = 106,	---
2989	II_DMTGC0 = 107,	---	2989	II_DMTGC0 = 107,	---
2990	II_DMUH = 108,	---	2990	II_DMUH = 108,	---
2991	II_DMUHU = 109,	---	2991	II_DMUHU = 109,	---
2992	II_DMUL = 110,	---	2992	II_DMUL = 110,	---
2993	II_POP = 111,	---	2993	II_POP = 111,	---
2994	II_DROTR = 112,	---	2994	II_DROTR = 112,	---
2995	II_DROTR32 = 113,	---	2995	II_DROTR32 = 113,	---
2996	II_DROTRV = 114,	---	2996	II_DROTRV = 114,	---
2997	II_DSBH = 115,	---	2997	II_DSBH = 115,	---
2998	II_DSHD = 116,	---	2998	II_DSHD = 116,	---
2999	II_DSLL = 117,	---	2999	II_DSLL = 117,	---
3000	II_DSLL32 = 118,	---	3000	II_DSLL32 = 118,	---
3001	II_DSLLV = 119,	---	3001	II_DSLLV = 119,	---
3002	II_DSRA = 120,	---	3002	II_DSRA = 120,	---
3003	II_DSRA32 = 121,	---	3003	II_DSRA32 = 121,	---
3004	II_DSRAV = 122,	---	3004	II_DSRAV = 122,	---
3005	II_DSRL = 123,	---	3005	II_DSRL = 123,	---
3006	II_DSRL32 = 124,	---	3006	II_DSRL32 = 124,	---
3007	II_DSRLV = 125,	---	3007	II_DSRLV = 125,	---
3008	II_DSUB = 126,	---	3008	II_DSUB = 126,	---
3009	II_DSUBU = 127,	---	3009	II_DSUBU = 127,	---
3010	II_DVP = 128,	---	3010	II_DVP = 128,	---
3011	II_DVPE = 129,	---	3011	II_DVPE = 129,	---
3012	II_EHB = 130,	---	3012	II_EHB = 130,	---
3013	II_EI = 131,	---	3013	II_EI = 131,	---
3014	II_EMT = 132,	---	3014	II_EMT = 132,	---
3015	II_ERET = 133,	---	3015	II_ERET = 133,	---
3016	II_ERETNC = 134,	---	3016	II_ERETNC = 134,	---
3017	II_EVP = 135,	---	3017	II_EVP = 135,	---
3018	II_EVPE = 136,	---	3018	II_EVPE = 136,	---
3019	II_ABS = 137,	---	3019	II_ABS = 137,	---
3020	II_SQRT_D = 138,	---	3020	II_SQRT_D = 138,	---
3021	II_ADD_D = 139,	---	3021	II_ADD_D = 139,	---
3022	II_ADD_PS = 140,	---	3022	II_ADD_PS = 140,	---
3023	II_ADD_S = 141,	---	3023	II_ADD_S = 141,	---
3024	II_DIV_D = 142,	---	3024	II_DIV_D = 142,	---
3025	II_DIV_S = 143,	---	3025	II_DIV_S = 143,	---
3026	II_FLOOR = 144,	---	3026	II_FLOOR = 144,	---
3027	II_MOV_D = 145,	---	3027	II_MOV_D = 145,	---
3028	II_MOV_S = 146,	---	3028	II_MOV_S = 146,	---
3029	II_MUL_D = 147,	---	3029	II_MUL_D = 147,	---
3030	II_MUL_PS = 148,	---	3030	II_MUL_PS = 148,	---
3031	II_MUL_S = 149,	---	3031	II_MUL_S = 149,	---
3032	II_NEG = 150,	---	3032	II_NEG = 150,	---
3033	II_FORK = 151,	---	3033	II_FORK = 151,	---
3034	II_SQRT_S = 152,	---	3034	II_SQRT_S = 152,	---
3035	II_SUB_D = 153,	---	3035	II_SUB_D = 153,	---
3036	II_SUB_PS = 154,	---	3036	II_SUB_PS = 154,	---
3037	II_SUB_S = 155,	---	3037	II_SUB_S = 155,	---
3038	II_GINVI = 156,	---	3038	II_GINVI = 156,	---
3039	II_GINVT = 157,	---	3039	II_GINVT = 157,	---
3040	II_HYPCALL = 158,	---	3040	II_HYPCALL = 158,	---
3041	II_JALR_HB = 159,	---	3041	II_JALR_HB = 159,	---
3042	II_JALRC = 160,	---	3042	II_JALRC = 160,	---
3043	II_JALRS = 161,	---	3043	II_JALRS = 161,	---
3044	II_JALS = 162,	---	3044	II_JALS = 162,	---
3045	II_JIALC = 163,	---	3045	II_JIALC = 163,	---
3046	II_JIC = 164,	---	3046	II_JIC = 164,	---
3047	II_JRADDIUSP = 165,	---	3047	II_JRADDIUSP = 165,	---
3048	II_JRC = 166,	---	3048	II_JRC = 166,	---
3049	II_JR_HB = 167,	---	3049	II_JR_HB = 167,	---
3050	II_LB = 168,	---	3050	II_LB = 168,	---
3051	II_LBE = 169,	---	3051	II_LBE = 169,	---
3052	II_LBU = 170,	---	3052	II_LBU = 170,	---
3053	II_LBUE = 171,	---	3053	II_LBUE = 171,	---
3054	II_LD = 172,	---	3054	II_LD = 172,	---
3055	II_LDC1 = 173,	---	3055	II_LDC1 = 173,	---
3056	II_LDC2 = 174,	---	3056	II_LDC2 = 174,	---
3057	II_LDC3 = 175,	---	3057	II_LDC3 = 175,	---
3058	II_LDL = 176,	---	3058	II_LDL = 176,	---
3059	II_LDPC = 177,	---	3059	II_LDPC = 177,	---
3060	II_LDR = 178,	---	3060	II_LDR = 178,	---
3061	II_LDXC1 = 179,	---	3061	II_LDXC1 = 179,	---
3062	II_LH = 180,	---	3062	II_LH = 180,	---
3063	II_LHE = 181,	---	3063	II_LHE = 181,	---
3064	II_LHU = 182,	---	3064	II_LHU = 182,	---
3065	II_LHUE = 183,	---	3065	II_LHUE = 183,	---
3066	II_LI = 184,	---	3066	II_LI = 184,	---
3067	II_LL = 185,	---	3067	II_LL = 185,	---
3068	II_LLD = 186,	---	3068	II_LLD = 186,	---
3069	II_LLE = 187,	---	3069	II_LLE = 187,	---
3070	II_LSA = 188,	---	3070	II_LSA = 188,	---
3071	II_LUI = 189,	---	3071	II_LUI = 189,	---
3072	II_LUXC1 = 190,	---	3072	II_LUXC1 = 190,	---
3073	II_LW = 191,	---	3073	II_LW = 191,	---
3074	II_LWC1 = 192,	---	3074	II_LWC1 = 192,	---
3075	II_LWC2 = 193,	---	3075	II_LWC2 = 193,	---
3076	II_LWC3 = 194,	---	3076	II_LWC3 = 194,	---
3077	II_LWE = 195,	---	3077	II_LWE = 195,	---
3078	II_LWL = 196,	---	3078	II_LWL = 196,	---
3079	II_LWLE = 197,	---	3079	II_LWLE = 197,	---
3080	II_LWM = 198,	---	3080	II_LWM = 198,	---
3081	II_LWPC = 199,	---	3081	II_LWPC = 199,	---
3082	II_LWP = 200,	---	3082	II_LWP = 200,	---
3083	II_LWR = 201,	---	3083	II_LWR = 201,	---
3084	II_LWRE = 202,	---	3084	II_LWRE = 202,	---
3085	II_LWUPC = 203,	---	3085	II_LWUPC = 203,	---
3086	II_LWU = 204,	---	3086	II_LWU = 204,	---
3087	II_LWXC1 = 205,	---	3087	II_LWXC1 = 205,	---
3088	II_LWXS = 206,	---	3088	II_LWXS = 206,	---
3089	II_MADDF_D = 207,	---	3089	II_MADDF_D = 207,	---
3090	II_MADDF_S = 208,	---	3090	II_MADDF_S = 208,	---
3091	II_MADD_D = 209,	---	3091	II_MADD_D = 209,	---
3092	II_MADD_S = 210,	---	3092	II_MADD_S = 210,	---
3093	II_MAX_D = 211,	---	3093	II_MAX_D = 211,	---
3094	II_MAXA_D = 212,	---	3094	II_MAXA_D = 212,	---
3095	II_MAX_S = 213,	---	3095	II_MAX_S = 213,	---
3096	II_MAXA_S = 214,	---	3096	II_MAXA_S = 214,	---
3097	II_MFC0 = 215,	---	3097	II_MFC0 = 215,	---
3098	II_MFC2 = 216,	---	3098	II_MFC2 = 216,	---
3099	II_MFGC0 = 217,	---	3099	II_MFGC0 = 217,	---
3100	II_MFHC0 = 218,	---	3100	II_MFHC0 = 218,	---
3101	II_MFHC1 = 219,	---	3101	II_MFHC1 = 219,	---
3102	II_MFHGC0 = 220,	---	3102	II_MFHGC0 = 220,	---
3103	II_MFTR = 221,	---	3103	II_MFTR = 221,	---
3104	II_MIN_S = 222,	---	3104	II_MIN_S = 222,	---
3105	II_MINA_D = 223,	---	3105	II_MINA_D = 223,	---
3106	II_MIN_D = 224,	---	3106	II_MIN_D = 224,	---
3107	II_MINA_S = 225,	---	3107	II_MINA_S = 225,	---
3108	II_MOD = 226,	---	3108	II_MOD = 226,	---
3109	II_MODU = 227,	---	3109	II_MODU = 227,	---
3110	II_MOVE = 228,	---	3110	II_MOVE = 228,	---
3111	II_MOVF_D = 229,	---	3111	II_MOVF_D = 229,	---
3112	II_MOVF = 230,	---	3112	II_MOVF = 230,	---
3113	II_MOVF_S = 231,	---	3113	II_MOVF_S = 231,	---
3114	II_MOVN_D = 232,	---	3114	II_MOVN_D = 232,	---
3115	II_MOVN = 233,	---	3115	II_MOVN = 233,	---
3116	II_MOVN_S = 234,	---	3116	II_MOVN_S = 234,	---
3117	II_MOVT_D = 235,	---	3117	II_MOVT_D = 235,	---
3118	II_MOVT = 236,	---	3118	II_MOVT = 236,	---
3119	II_MOVT_S = 237,	---	3119	II_MOVT_S = 237,	---
3120	II_MOVZ_D = 238,	---	3120	II_MOVZ_D = 238,	---
3121	II_MOVZ = 239,	---	3121	II_MOVZ = 239,	---
3122	II_MOVZ_S = 240,	---	3122	II_MOVZ_S = 240,	---
3123	II_MSUBF_D = 241,	---	3123	II_MSUBF_D = 241,	---
3124	II_MSUBF_S = 242,	---	3124	II_MSUBF_S = 242,	---
3125	II_MSUB_D = 243,	---	3125	II_MSUB_D = 243,	---
3126	II_MSUB_S = 244,	---	3126	II_MSUB_S = 244,	---
3127	II_MTC0 = 245,	---	3127	II_MTC0 = 245,	---
3128	II_MTC2 = 246,	---	3128	II_MTC2 = 246,	---
3129	II_MTGC0 = 247,	---	3129	II_MTGC0 = 247,	---
3130	II_MTHC0 = 248,	---	3130	II_MTHC0 = 248,	---
3131	II_MTHC1 = 249,	---	3131	II_MTHC1 = 249,	---
3132	II_MTHGC0 = 250,	---	3132	II_MTHGC0 = 250,	---
3133	II_MTTR = 251,	---	3133	II_MTTR = 251,	---
3134	II_MUH = 252,	---	3134	II_MUH = 252,	---
3135	II_MUHU = 253,	---	3135	II_MUHU = 253,	---
3136	II_MUL = 254,	---	3136	II_MUL = 254,	---
3137	II_MULR_PS = 255,	---	3137	II_MULR_PS = 255,	---
3138	II_MULU = 256,	---	3138	II_MULU = 256,	---
3139	II_NMADD_D = 257,	---	3139	II_NMADD_D = 257,	---
3140	II_NMADD_S = 258,	---	3140	II_NMADD_S = 258,	---
3141	II_NMSUB_D = 259,	---	3141	II_NMSUB_D = 259,	---
3142	II_NMSUB_S = 260,	---	3142	II_NMSUB_S = 260,	---
3143	II_NOR = 261,	---	3143	II_NOR = 261,	---
3144	II_NOT = 262,	---	3144	II_NOT = 262,	---
3145	II_OR = 263,	---	3145	II_OR = 263,	---
3146	II_ORI = 264,	---	3146	II_ORI = 264,	---
3147	II_PAUSE = 265,	---	3147	II_PAUSE = 265,	---
3148	II_PREF = 266,	---	3148	II_PREF = 266,	---
3149	II_PREFE = 267,	---	3149	II_PREFE = 267,	---
3150	II_RDHWR = 268,	---	3150	II_RDHWR = 268,	---
3151	II_RDPGPR = 269,	---	3151	II_RDPGPR = 269,	---
3152	II_RECIP_D = 270,	---	3152	II_RECIP_D = 270,	---
3153	II_RECIP_S = 271,	---	3153	II_RECIP_S = 271,	---
3154	II_RINT_D = 272,	---	3154	II_RINT_D = 272,	---
3155	II_RINT_S = 273,	---	3155	II_RINT_S = 273,	---
3156	II_ROTR = 274,	---	3156	II_ROTR = 274,	---
3157	II_ROTRV = 275,	---	3157	II_ROTRV = 275,	---
3158	II_ROUND = 276,	---	3158	II_ROUND = 276,	---
3159	II_RSQRT_D = 277,	---	3159	II_RSQRT_D = 277,	---
3160	II_RSQRT_S = 278,	---	3160	II_RSQRT_S = 278,	---
3161	II_RESTORE = 279,	---	3161	II_RESTORE = 279,	---
3162	II_SB = 280,	---	3162	II_SB = 280,	---
3163	II_SBE = 281,	---	3163	II_SBE = 281,	---
3164	II_SC = 282,	---	3164	II_SC = 282,	---
3165	II_SCD = 283,	---	3165	II_SCD = 283,	---
3166	II_SCE = 284,	---	3166	II_SCE = 284,	---
3167	II_SD = 285,	---	3167	II_SD = 285,	---
3168	II_SDBBP = 286,	---	3168	II_SDBBP = 286,	---
3169	II_SDC1 = 287,	---	3169	II_SDC1 = 287,	---
3170	II_SDC2 = 288,	---	3170	II_SDC2 = 288,	---
3171	II_SDC3 = 289,	---	3171	II_SDC3 = 289,	---
3172	II_SDL = 290,	---	3172	II_SDL = 290,	---
3173	II_SDR = 291,	---	3173	II_SDR = 291,	---
3174	II_SDXC1 = 292,	---	3174	II_SDXC1 = 292,	---
3175	II_SEB = 293,	---	3175	II_SEB = 293,	---
3176	II_SEH = 294,	---	3176	II_SEH = 294,	---
3177	II_SELCCZ = 295,	---	3177	II_SELCCZ = 295,	---
3178	II_SELCCZ_D = 296,	---	3178	II_SELCCZ_D = 296,	---
3179	II_SELCCZ_S = 297,	---	3179	II_SELCCZ_S = 297,	---
3180	II_SEL_D = 298,	---	3180	II_SEL_D = 298,	---
3181	II_SEL_S = 299,	---	3181	II_SEL_S = 299,	---
3182	II_SEQ_SNE = 300,	---	3182	II_SEQ_SNE = 300,	---
3183	II_SEQI_SNEI = 301,	---	3183	II_SEQI_SNEI = 301,	---
3184	II_SH = 302,	---	3184	II_SH = 302,	---
3185	II_SHE = 303,	---	3185	II_SHE = 303,	---
3186	II_SIGRIE = 304,	---	3186	II_SIGRIE = 304,	---
3187	II_SLL = 305,	---	3187	II_SLL = 305,	---
3188	II_SLLV = 306,	---	3188	II_SLLV = 306,	---
3189	II_SLT_SLTU = 307,	---	3189	II_SLT_SLTU = 307,	---
3190	II_SLTI_SLTIU = 308,	---	3190	II_SLTI_SLTIU = 308,	---
3191	II_SRA = 309,	---	3191	II_SRA = 309,	---
3192	II_SRAV = 310,	---	3192	II_SRAV = 310,	---
3193	II_SRL = 311,	---	3193	II_SRL = 311,	---
3194	II_SRLV = 312,	---	3194	II_SRLV = 312,	---
3195	II_SSNOP = 313,	---	3195	II_SSNOP = 313,	---
3196	II_SUB = 314,	---	3196	II_SUB = 314,	---
3197	II_SUBU = 315,	---	3197	II_SUBU = 315,	---
3198	II_SUXC1 = 316,	---	3198	II_SUXC1 = 316,	---
3199	II_SW = 317,	---	3199	II_SW = 317,	---
3200	II_SWC1 = 318,	---	3200	II_SWC1 = 318,	---
3201	II_SWC2 = 319,	---	3201	II_SWC2 = 319,	---
3202	II_SWC3 = 320,	---	3202	II_SWC3 = 320,	---
3203	II_SWE = 321,	---	3203	II_SWE = 321,	---
3204	II_SWL = 322,	---	3204	II_SWL = 322,	---
3205	II_SWLE = 323,	---	3205	II_SWLE = 323,	---
3206	II_SWM = 324,	---	3206	II_SWM = 324,	---
3207	II_SWP = 325,	---	3207	II_SWP = 325,	---
3208	II_SWR = 326,	---	3208	II_SWR = 326,	---
3209	II_SWRE = 327,	---	3209	II_SWRE = 327,	---
3210	II_SWXC1 = 328,	---	3210	II_SWXC1 = 328,	---
3211	II_SYNC = 329,	---	3211	II_SYNC = 329,	---
3212	II_SYNCI = 330,	---	3212	II_SYNCI = 330,	---
3213	II_SYSCALL = 331,	---	3213	II_SYSCALL = 331,	---
3214	II_SAVE = 332,	---	3214	II_SAVE = 332,	---
3215	II_TEQ = 333,	---	3215	II_TEQ = 333,	---
3216	II_TEQI = 334,	---	3216	II_TEQI = 334,	---
3217	II_TGE = 335,	---	3217	II_TGE = 335,	---
3218	II_TGEI = 336,	---	3218	II_TGEI = 336,	---
3219	II_TGEIU = 337,	---	3219	II_TGEIU = 337,	---
3220	II_TGEU = 338,	---	3220	II_TGEU = 338,	---
3221	II_TLBGINV = 339,	---	3221	II_TLBGINV = 339,	---
3222	II_TLBGINVF = 340,	---	3222	II_TLBGINVF = 340,	---
3223	II_TLBGP = 341,	---	3223	II_TLBGP = 341,	---
3224	II_TLBGR = 342,	---	3224	II_TLBGR = 342,	---
3225	II_TLBGWI = 343,	---	3225	II_TLBGWI = 343,	---
3226	II_TLBGWR = 344,	---	3226	II_TLBGWR = 344,	---
3227	II_TLBINV = 345,	---	3227	II_TLBINV = 345,	---
3228	II_TLBINVF = 346,	---	3228	II_TLBINVF = 346,	---
3229	II_TLBP = 347,	---	3229	II_TLBP = 347,	---
3230	II_TLBR = 348,	---	3230	II_TLBR = 348,	---
3231	II_TLBWI = 349,	---	3231	II_TLBWI = 349,	---
3232	II_TLBWR = 350,	---	3232	II_TLBWR = 350,	---
3233	II_TLT = 351,	---	3233	II_TLT = 351,	---
3234	II_TLTI = 352,	---	3234	II_TLTI = 352,	---
3235	II_TTLTIU = 353,	---	3235	II_TTLTIU = 353,	---
3236	II_TLTU = 354,	---	3236	II_TLTU = 354,	---
3237	II_TNE = 355,	---	3237	II_TNE = 355,	---
3238	II_TNEI = 356,	---	3238	II_TNEI = 356,	---
3239	II_TRUNC = 357,	---	3239	II_TRUNC = 357,	---
3240	II_WAIT = 358,	---	3240	II_WAIT = 358,	---
3241	II_WRPGPR = 359,	---	3241	II_WRPGPR = 359,	---
3242	II_WSBH = 360,	---	3242	II_WSBH = 360,	---
3243	II_XOR = 361,	---	3243	II_XOR = 361,	---
3244	II_XORI = 362,	---	3244	II_XORI = 362,	---
3245	II_YIELD = 363,	---	3245	II_YIELD = 363,	---
3246	AND = 364,	---	3246	AND = 364,	---
3247	LUi = 365,	---	3247	LUi = 365,	---
3248	NOR = 366,	---	3248	NOR = 366,	---
3249	OR = 367,	---	3249	OR = 367,	---
3250	SLTi_SLTiu = 368,	---	3250	SLTi_SLTiu = 368,	---
3251	SUB = 369,	---	3251	SUB = 369,	---
3252	SUBu = 370,	---	3252	SUBu = 370,	---
3253	XOR = 371,	---	3253	XOR = 371,	---
3254	SSNOP = 372,	---	3254	SSNOP = 372,	---
3255	NOP = 373,	---	3255	NOP = 373,	---
3256	B = 374,	---	3256	B = 374,	---
3257	BAL = 375,	---	3257	BAL = 375,	---
3258	BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,	---	3258	BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,	---
3259	BEQ_BEQL_BNE_BNEL = 377,	---	3259	BEQ_BEQL_BNE_BNEL = 377,	---
3260	BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,	---	3260	BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,	---
3261	BREAK = 379,	---	3261	BREAK = 379,	---
3262	DERET = 380,	---	3262	DERET = 380,	---
3263	ERET = 381,	---	3263	ERET = 381,	---
3264	ERet_RetRA = 382,	---	3264	ERet_RetRA = 382,	---
3265	ERETNC = 383,	---	3265	ERETNC = 383,	---
3266	J_TAILCALL = 384,	---	3266	J_TAILCALL = 384,	---
3267	JR_TAILCALLREG_TAILCALLREGHB = 385,	---	3267	JR_TAILCALLREG_TAILCALLREGHB = 385,	---
3268	JR_HB = 386,	---	3268	JR_HB = 386,	---
3269	PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,	---	3269	PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,	---
3270	PseudoReturn = 388,	---	3270	PseudoReturn = 388,	---
3271	SDBBP = 389,	---	3271	SDBBP = 389,	---
3272	SYSCALL = 390,	---	3272	SYSCALL = 390,	---
3273	TEQ = 391,	---	3273	TEQ = 391,	---
3274	TEQI = 392,	---	3274	TEQI = 392,	---
3275	TGE = 393,	---	3275	TGE = 393,	---
3276	TGEI = 394,	---	3276	TGEI = 394,	---
3277	TGEIU = 395,	---	3277	TGEIU = 395,	---
3278	TGEU = 396,	---	3278	TGEU = 396,	---
3279	TLT = 397,	---	3279	TLT = 397,	---
3280	TLTI = 398,	---	3280	TLTI = 398,	---
3281	TLTU = 399,	---	3281	TLTU = 399,	---
3282	TNE = 400,	---	3282	TNE = 400,	---
3283	TNEI = 401,	---	3283	TNEI = 401,	---
3284	TRAP = 402,	---	3284	TRAP = 402,	---
3285	TTLTIU = 403,	---	3285	TTLTIU = 403,	---
3286	WAIT = 404,	---	3286	WAIT = 404,	---
3287	PAUSE = 405,	---	3287	PAUSE = 405,	---
3288	JAL = 406,	---	3288	JAL = 406,	---
3289	JALR_JALRHBPseudo_JALRPseudo = 407,	---	3289	JALR_JALRHBPseudo_JALRPseudo = 407,	---
3290	JALR_HB = 408,	---	3290	JALR_HB = 408,	---
3291	JALX = 409,	---	3291	JALX = 409,	---
3292	TLBINV = 410,	---	3292	TLBINV = 410,	---
3293	TLBINVF = 411,	---	3293	TLBINVF = 411,	---
3294	TLBP = 412,	---	3294	TLBP = 412,	---
3295	TLBR = 413,	---	3295	TLBR = 413,	---
3296	TLBWI = 414,	---	3296	TLBWI = 414,	---
3297	TLBWR = 415,	---	3297	TLBWR = 415,	---
3298	MFC0 = 416,	---	3298	MFC0 = 416,	---
3299	MTC0 = 417,	---	3299	MTC0 = 417,	---
3300	MFC2 = 418,	---	3300	MFC2 = 418,	---
3301	MTC2 = 419,	---	3301	MTC2 = 419,	---
3302	HYPCALL = 420,	---	3302	HYPCALL = 420,	---
3303	MFGC0 = 421,	---	3303	MFGC0 = 421,	---
3304	MFHGC0 = 422,	---	3304	MFHGC0 = 422,	---
3305	MTGC0 = 423,	---	3305	MTGC0 = 423,	---
3306	MTHGC0 = 424,	---	3306	MTHGC0 = 424,	---
3307	TLBGINV = 425,	---	3307	TLBGINV = 425,	---
3308	TLBGINVF = 426,	---	3308	TLBGINVF = 426,	---
3309	TLBGP = 427,	---	3309	TLBGP = 427,	---
3310	TLBGR = 428,	---	3310	TLBGR = 428,	---
3311	TLBGWI = 429,	---	3311	TLBGWI = 429,	---
3312	TLBGWR = 430,	---	3312	TLBGWR = 430,	---
3313	LB = 431,	---	3313	LB = 431,	---
3314	LBu = 432,	---	3314	LBu = 432,	---
3315	LH = 433,	---	3315	LH = 433,	---
3316	LHu = 434,	---	3316	LHu = 434,	---
3317	LW = 435,	---	3317	LW = 435,	---
3318	LL = 436,	---	3318	LL = 436,	---
3319	LWC2 = 437,	---	3319	LWC2 = 437,	---
3320	LWC3 = 438,	---	3320	LWC3 = 438,	---
3321	LDC2 = 439,	---	3321	LDC2 = 439,	---
3322	LDC3 = 440,	---	3322	LDC3 = 440,	---
3323	LBE = 441,	---	3323	LBE = 441,	---
3324	LBuE = 442,	---	3324	LBuE = 442,	---
3325	LHE = 443,	---	3325	LHE = 443,	---
3326	LHuE = 444,	---	3326	LHuE = 444,	---
3327	LWE = 445,	---	3327	LWE = 445,	---
3328	LLE = 446,	---	3328	LLE = 446,	---
3329	LWPC = 447,	---	3329	LWPC = 447,	---
3330	LWL = 448,	---	3330	LWL = 448,	---
3331	LWR = 449,	---	3331	LWR = 449,	---
3332	LWLE = 450,	---	3332	LWLE = 450,	---
3333	LWRE = 451,	---	3333	LWRE = 451,	---
3334	SB = 452,	---	3334	SB = 452,	---
3335	SH = 453,	---	3335	SH = 453,	---
3336	SW = 454,	---	3336	SW = 454,	---
3337	SWC2 = 455,	---	3337	SWC2 = 455,	---
3338	SWC3 = 456,	---	3338	SWC3 = 456,	---
3339	SDC2 = 457,	---	3339	SDC2 = 457,	---
3340	SDC3 = 458,	---	3340	SDC3 = 458,	---
3341	SC = 459,	---	3341	SC = 459,	---
3342	SBE = 460,	---	3342	SBE = 460,	---
3343	SHE = 461,	---	3343	SHE = 461,	---
3344	SWE = 462,	---	3344	SWE = 462,	---
3345	SCE = 463,	---	3345	SCE = 463,	---
3346	SWL = 464,	---	3346	SWL = 464,	---
3347	SWR = 465,	---	3347	SWR = 465,	---
3348	SWLE = 466,	---	3348	SWLE = 466,	---
3349	SWRE = 467,	---	3349	SWRE = 467,	---
3350	PREF = 468,	---	3350	PREF = 468,	---
3351	PREFE = 469,	---	3351	PREFE = 469,	---
3352	CACHE = 470,	---	3352	CACHE = 470,	---
3353	CACHEE = 471,	---	3353	CACHEE = 471,	---
3354	SYNC = 472,	---	3354	SYNC = 472,	---
3355	SYNCI = 473,	---	3355	SYNCI = 473,	---
3356	CLO = 474,	---	3356	CLO = 474,	---
3357	CLZ = 475,	---	3357	CLZ = 475,	---
3358	DI = 476,	---	3358	DI = 476,	---
3359	EI = 477,	---	3359	EI = 477,	---
3360	MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,	---	3360	MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,	---
3361	EHB = 479,	---	3361	EHB = 479,	---
3362	RDHWR = 480,	---	3362	RDHWR = 480,	---
3363	WSBH = 481,	---	3363	WSBH = 481,	---
3364	MOVN_I_I = 482,	---	3364	MOVN_I_I = 482,	---
3365	MOVZ_I_I = 483,	---	3365	MOVZ_I_I = 483,	---
3366	DIV_PseudoSDIV_SDIV = 484,	---	3366	DIV_PseudoSDIV_SDIV = 484,	---
3367	DIVU_PseudoUDIV_UDIV = 485,	---	3367	DIVU_PseudoUDIV_UDIV = 485,	---
3368	MUL = 486,	---	3368	MUL = 486,	---
3369	MULT_PseudoMULT = 487,	---	3369	MULT_PseudoMULT = 487,	---
3370	MULTu_PseudoMULTu = 488,	---	3370	MULTu_PseudoMULTu = 488,	---
3371	MADD_PseudoMADD = 489,	---	3371	MADD_PseudoMADD = 489,	---
3372	MADDU_PseudoMADDU = 490,	---	3372	MADDU_PseudoMADDU = 490,	---
3373	MSUB_PseudoMSUB = 491,	---	3373	MSUB_PseudoMSUB = 491,	---
3374	MSUBU_PseudoMSUBU = 492,	---	3374	MSUBU_PseudoMSUBU = 492,	---
3375	MTHI_MTLO_PseudoMTLOHI = 493,	---	3375	MTHI_MTLO_PseudoMTLOHI = 493,	---
3376	EXT = 494,	---	3376	EXT = 494,	---
3377	INS = 495,	---	3377	INS = 495,	---
3378	ADD = 496,	---	3378	ADD = 496,	---
3379	ADDi = 497,	---	3379	ADDi = 497,	---
3380	ADDiu = 498,	---	3380	ADDiu = 498,	---
3381	ANDi = 499,	---	3381	ANDi = 499,	---
3382	ORi = 500,	---	3382	ORi = 500,	---
3383	ROTR = 501,	---	3383	ROTR = 501,	---
3384	SEB = 502,	---	3384	SEB = 502,	---
3385	SEH = 503,	---	3385	SEH = 503,	---
3386	SLT_SLTu = 504,	---	3386	SLT_SLTu = 504,	---
3387	SLL = 505,	---	3387	SLL = 505,	---
3388	SRA = 506,	---	3388	SRA = 506,	---
3389	SRL = 507,	---	3389	SRL = 507,	---
3390	XORi = 508,	---	3390	XORi = 508,	---
3391	ADDu = 509,	---	3391	ADDu = 509,	---
3392	SLLV = 510,	---	3392	SLLV = 510,	---
3393	SRAV = 511,	---	3393	SRAV = 511,	---
3394	SRLV = 512,	---	3394	SRLV = 512,	---
3395	LSA = 513,	---	3395	LSA = 513,	---
3396	COPY = 514,	---	3396	COPY = 514,	---
3397	VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,	---	3397	VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,	---
3398	BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,	---	3398	BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,	---
3399	BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,	---	3399	BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,	---
3400	INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,	---	3400	INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,	---
3401	SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,	---	3401	SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,	---
3402	BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,	---	3402	BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,	---
3403	BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,	---	3403	BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,	---
3404	BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,	---	3404	BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,	---
3405	BSELI_B_BSEL_V = 523,	---	3405	BSELI_B_BSEL_V = 523,	---
3406	BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,	---	3406	BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,	---
3407	BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,	---	3407	BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,	---
3408	PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,	---	3408	PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,	---
3409	SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,	---	3409	SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,	---
3410	BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,	---	3410	BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,	---
3411	CFCMSA_CTCMSA = 529,	---	3411	CFCMSA_CTCMSA = 529,	---
3412	FABS_S_FABS_D32_FABS_D64 = 530,	---	3412	FABS_S_FABS_D32_FABS_D64 = 530,	---
3413	MOVF_D32_MOVF_D64 = 531,	---	3413	MOVF_D32_MOVF_D64 = 531,	---
3414	MOVF_S = 532,	---	3414	MOVF_S = 532,	---
3415	MOVT_D32_MOVT_D64 = 533,	---	3415	MOVT_D32_MOVT_D64 = 533,	---
3416	MOVT_S = 534,	---	3416	MOVT_S = 534,	---
3417	FMOV_D32_FMOV_D64 = 535,	---	3417	FMOV_D32_FMOV_D64 = 535,	---
3418	FMOV_S = 536,	---	3418	FMOV_S = 536,	---
3419	FNEG_S_FNEG_D32_FNEG_D64 = 537,	---	3419	FNEG_S_FNEG_D32_FNEG_D64 = 537,	---
3420	ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,	---	3420	ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,	---
3421	ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,	---	3421	ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,	---
3422	ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,	---	3422	ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,	---
3423	ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,	---	3423	ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,	---
3424	AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,	---	3424	AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,	---
3425	SHF_B_SHF_H_SHF_W = 543,	---	3425	SHF_B_SHF_H_SHF_W = 543,	---
3426	FILL_B_FILL_D_FILL_H_FILL_W = 544,	---	3426	FILL_B_FILL_D_FILL_H_FILL_W = 544,	---
3427	SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,	---	3427	SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,	---
3428	MOVE_V = 546,	---	3428	MOVE_V = 546,	---
3429	LDI_B_LDI_D_LDI_H_LDI_W = 547,	---	3429	LDI_B_LDI_D_LDI_H_LDI_W = 547,	---
3430	AND_V_NOR_V_OR_V_XOR_V = 548,	---	3430	AND_V_NOR_V_OR_V_XOR_V = 548,	---
3431	ANDI_B_NORI_B_ORI_B_XORI_B = 549,	---	3431	ANDI_B_NORI_B_ORI_B_XORI_B = 549,	---
3432	AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,	---	3432	AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,	---
3433	FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,	---	3433	FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,	---
3434	INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,	---	3434	INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,	---
3435	FEXP2_D_FEXP2_W = 553,	---	3435	FEXP2_D_FEXP2_W = 553,	---
3436	CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,	---	3436	CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,	---
3437	CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,	---	3437	CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,	---
3438	CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,	---	3438	CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,	---
3439	CMP_UN_D = 557,	---	3439	CMP_UN_D = 557,	---
3440	CMP_UN_S = 558,	---	3440	CMP_UN_S = 558,	---
3441	CMP_UEQ_D = 559,	---	3441	CMP_UEQ_D = 559,	---
3442	CMP_UEQ_S = 560,	---	3442	CMP_UEQ_S = 560,	---
3443	CMP_EQ_D = 561,	---	3443	CMP_EQ_D = 561,	---
3444	CMP_EQ_S = 562,	---	3444	CMP_EQ_S = 562,	---
3445	CMP_LT_D = 563,	---	3445	CMP_LT_D = 563,	---
3446	CMP_LT_S = 564,	---	3446	CMP_LT_S = 564,	---
3447	CMP_ULT_D = 565,	---	3447	CMP_ULT_D = 565,	---
3448	CMP_ULT_S = 566,	---	3448	CMP_ULT_S = 566,	---
3449	CMP_LE_D = 567,	---	3449	CMP_LE_D = 567,	---
3450	CMP_LE_S = 568,	---	3450	CMP_LE_S = 568,	---
3451	CMP_ULE_D = 569,	---	3451	CMP_ULE_D = 569,	---
3452	CMP_ULE_S = 570,	---	3452	CMP_ULE_S = 570,	---
3453	FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,	---	3453	FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,	---
3454	FSUEQ_D_FSUEQ_W = 572,	---	3454	FSUEQ_D_FSUEQ_W = 572,	---
3455	FSULE_D_FSULE_W = 573,	---	3455	FSULE_D_FSULE_W = 573,	---
3456	FSULT_D_FSULT_W = 574,	---	3456	FSULT_D_FSULT_W = 574,	---
3457	FSUNE_D_FSUNE_W = 575,	---	3457	FSUNE_D_FSUNE_W = 575,	---
3458	FSUN_D_FSUN_W = 576,	---	3458	FSUN_D_FSUN_W = 576,	---
3459	FCAF_D_FCAF_W = 577,	---	3459	FCAF_D_FCAF_W = 577,	---
3460	FCEQ_D_FCEQ_W = 578,	---	3460	FCEQ_D_FCEQ_W = 578,	---
3461	FCLE_D_FCLE_W = 579,	---	3461	FCLE_D_FCLE_W = 579,	---
3462	FCLT_D_FCLT_W = 580,	---	3462	FCLT_D_FCLT_W = 580,	---
3463	FCNE_D_FCNE_W = 581,	---	3463	FCNE_D_FCNE_W = 581,	---
3464	FCOR_D_FCOR_W = 582,	---	3464	FCOR_D_FCOR_W = 582,	---
3465	FCUEQ_D_FCUEQ_W = 583,	---	3465	FCUEQ_D_FCUEQ_W = 583,	---
3466	FCULE_D_FCULE_W = 584,	---	3466	FCULE_D_FCULE_W = 584,	---
3467	FCULT_D_FCULT_W = 585,	---	3467	FCULT_D_FCULT_W = 585,	---
3468	FCUNE_D_FCUNE_W = 586,	---	3468	FCUNE_D_FCUNE_W = 586,	---
3469	FCUN_D_FCUN_W = 587,	---	3469	FCUN_D_FCUN_W = 587,	---
3470	FABS_D_FABS_W = 588,	---	3470	FABS_D_FABS_W = 588,	---
3471	FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,	---	3471	FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,	---
3472	FFQL_D_FFQL_W = 590,	---	3472	FFQL_D_FFQL_W = 590,	---
3473	FFQR_D_FFQR_W = 591,	---	3473	FFQR_D_FFQR_W = 591,	---
3474	FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,	---	3474	FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,	---
3475	FRINT_D_FRINT_W = 593,	---	3475	FRINT_D_FRINT_W = 593,	---
3476	FTQ_H_FTQ_W = 594,	---	3476	FTQ_H_FTQ_W = 594,	---
3477	FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,	---	3477	FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,	---
3478	FEXDO_H_FEXDO_W = 596,	---	3478	FEXDO_H_FEXDO_W = 596,	---
3479	FEXUPL_D_FEXUPL_W = 597,	---	3479	FEXUPL_D_FEXUPL_W = 597,	---
3480	FEXUPR_D_FEXUPR_W = 598,	---	3480	FEXUPR_D_FEXUPR_W = 598,	---
3481	FCLASS_D_FCLASS_W = 599,	---	3481	FCLASS_D_FCLASS_W = 599,	---
3482	FMAX_A_D_FMAX_A_W = 600,	---	3482	FMAX_A_D_FMAX_A_W = 600,	---
3483	FMAX_D_FMAX_W = 601,	---	3483	FMAX_D_FMAX_W = 601,	---
3484	FMIN_A_D_FMIN_A_W = 602,	---	3484	FMIN_A_D_FMIN_A_W = 602,	---
3485	FMIN_D_FMIN_W = 603,	---	3485	FMIN_D_FMIN_W = 603,	---
3486	FLOG2_D_FLOG2_W = 604,	---	3486	FLOG2_D_FLOG2_W = 604,	---
3487	ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,	---	3487	ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,	---
3488	ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,	---	3488	ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,	---
3489	INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,	---	3489	INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,	---
3490	SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,	---	3490	SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,	---
3491	SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,	---	3491	SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,	---
3492	SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,	---	3492	SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,	---
3493	SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,	---	3493	SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,	---
3494	SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,	---	3494	SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,	---
3495	MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,	---	3495	MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,	---
3496	DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,	---	3496	DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,	---
3497	HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,	---	3497	HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,	---
3498	HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,	---	3498	HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,	---
3499	MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,	---	3499	MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,	---
3500	MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,	---	3500	MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,	---
3501	MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,	---	3501	MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,	---
3502	MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,	---	3502	MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,	---
3503	SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,	---	3503	SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,	---
3504	SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,	---	3504	SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,	---
3505	SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,	---	3505	SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,	---
3506	SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,	---	3506	SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,	---
3507	SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,	---	3507	SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,	---
3508	PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,	---	3508	PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,	---
3509	NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,	---	3509	NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,	---
3510	FADD_D32_FADD_D64 = 628,	---	3510	FADD_D32_FADD_D64 = 628,	---
3511	FADD_PS64 = 629,	---	3511	FADD_PS64 = 629,	---
3512	FADD_S = 630,	---	3512	FADD_S = 630,	---
3513	FMUL_D32_FMUL_D64 = 631,	---	3513	FMUL_D32_FMUL_D64 = 631,	---
3514	FMUL_PS64 = 632,	---	3514	FMUL_PS64 = 632,	---
3515	FMUL_S = 633,	---	3515	FMUL_S = 633,	---
3516	FSUB_D32_FSUB_D64 = 634,	---	3516	FSUB_D32_FSUB_D64 = 634,	---
3517	FSUB_PS64 = 635,	---	3517	FSUB_PS64 = 635,	---
3518	FSUB_S = 636,	---	3518	FSUB_S = 636,	---
3519	TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,	---	3519	TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,	---
3520	CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,	---	3520	CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,	---
3521	CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,	---	3521	CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,	---
3522	C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,	---	3522	C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,	---
3523	C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,	---	3523	C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,	---
3524	FCMP_D32_FCMP_D64 = 642,	---	3524	FCMP_D32_FCMP_D64 = 642,	---
3525	FCMP_S32 = 643,	---	3525	FCMP_S32 = 643,	---
3526	PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,	---	3526	PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,	---
3527	PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,	---	3527	PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,	---
3528	FDIV_S = 646,	---	3528	FDIV_S = 646,	---
3529	FDIV_D32_FDIV_D64 = 647,	---	3529	FDIV_D32_FDIV_D64 = 647,	---
3530	FSQRT_S = 648,	---	3530	FSQRT_S = 648,	---
3531	FSQRT_D32_FSQRT_D64 = 649,	---	3531	FSQRT_D32_FSQRT_D64 = 649,	---
3532	FRCP_D_FRCP_W = 650,	---	3532	FRCP_D_FRCP_W = 650,	---
3533	FRSQRT_D_FRSQRT_W = 651,	---	3533	FRSQRT_D_FRSQRT_W = 651,	---
3534	RECIP_D32_RECIP_D64 = 652,	---	3534	RECIP_D32_RECIP_D64 = 652,	---
3535	RSQRT_D32_RSQRT_D64 = 653,	---	3535	RSQRT_D32_RSQRT_D64 = 653,	---
3536	RECIP_S = 654,	---	3536	RECIP_S = 654,	---
3537	RSQRT_S = 655,	---	3537	RSQRT_S = 655,	---
3538	FMADD_D_FMADD_W = 656,	---	3538	FMADD_D_FMADD_W = 656,	---
3539	FMSUB_D_FMSUB_W = 657,	---	3539	FMSUB_D_FMSUB_W = 657,	---
3540	FDIV_W = 658,	---	3540	FDIV_W = 658,	---
3541	FDIV_D = 659,	---	3541	FDIV_D = 659,	---
3542	FSQRT_W = 660,	---	3542	FSQRT_W = 660,	---
3543	FSQRT_D = 661,	---	3543	FSQRT_D = 661,	---
3544	FMUL_D_FMUL_W = 662,	---	3544	FMUL_D_FMUL_W = 662,	---
3545	FADD_D_FADD_W = 663,	---	3545	FADD_D_FADD_W = 663,	---
3546	FSUB_D_FSUB_W = 664,	---	3546	FSUB_D_FSUB_W = 664,	---
3547	DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,	---	3547	DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,	---
3548	DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,	---	3548	DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,	---
3549	DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,	---	3549	DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,	---
3550	MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,	---	3550	MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,	---
3551	MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,	---	3551	MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,	---
3552	MULV_B_MULV_D_MULV_H_MULV_W = 670,	---	3552	MULV_B_MULV_D_MULV_H_MULV_W = 670,	---
3553	MADDR_Q_H_MADDR_Q_W = 671,	---	3553	MADDR_Q_H_MADDR_Q_W = 671,	---
3554	MADD_Q_H_MADD_Q_W = 672,	---	3554	MADD_Q_H_MADD_Q_W = 672,	---
3555	MSUBR_Q_H_MSUBR_Q_W = 673,	---	3555	MSUBR_Q_H_MSUBR_Q_W = 673,	---
3556	MSUB_Q_H_MSUB_Q_W = 674,	---	3556	MSUB_Q_H_MSUB_Q_W = 674,	---
3557	MULR_Q_H_MULR_Q_W = 675,	---	3557	MULR_Q_H_MULR_Q_W = 675,	---
3558	MUL_Q_H_MUL_Q_W = 676,	---	3558	MUL_Q_H_MUL_Q_W = 676,	---
3559	MADD_D32_MADD_D64 = 677,	---	3559	MADD_D32_MADD_D64 = 677,	---
3560	MADD_S = 678,	---	3560	MADD_S = 678,	---
3561	MSUB_D32_MSUB_D64 = 679,	---	3561	MSUB_D32_MSUB_D64 = 679,	---
3562	MSUB_S = 680,	---	3562	MSUB_S = 680,	---
3563	NMADD_D32_NMADD_D64 = 681,	---	3563	NMADD_D32_NMADD_D64 = 681,	---
3564	NMADD_S = 682,	---	3564	NMADD_S = 682,	---
3565	NMSUB_D32_NMSUB_D64 = 683,	---	3565	NMSUB_D32_NMSUB_D64 = 683,	---
3566	NMSUB_S = 684,	---	3566	NMSUB_S = 684,	---
3567	CTC1 = 685,	---	3567	CTC1 = 685,	---
3568	MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,	---	3568	MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,	---
3569	MTHC1_D32_MTHC1_D64 = 687,	---	3569	MTHC1_D32_MTHC1_D64 = 687,	---
3570	COPY_U_B_COPY_U_H_COPY_U_W = 688,	---	3570	COPY_U_B_COPY_U_H_COPY_U_W = 688,	---
3571	COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,	---	3571	COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,	---
3572	BC1F = 690,	---	3572	BC1F = 690,	---
3573	BC1FL = 691,	---	3573	BC1FL = 691,	---
3574	BC1T = 692,	---	3574	BC1T = 692,	---
3575	BC1TL = 693,	---	3575	BC1TL = 693,	---
3576	CFC1 = 694,	---	3576	CFC1 = 694,	---
3577	MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,	---	3577	MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,	---
3578	MFHC1_D32_MFHC1_D64 = 696,	---	3578	MFHC1_D32_MFHC1_D64 = 696,	---
3579	MOVF_I = 697,	---	3579	MOVF_I = 697,	---
3580	MOVT_I = 698,	---	3580	MOVT_I = 698,	---
3581	SDC1_SDC164 = 699,	---	3581	SDC1_SDC164 = 699,	---
3582	SDXC1_SDXC164 = 700,	---	3582	SDXC1_SDXC164 = 700,	---
3583	SWC1 = 701,	---	3583	SWC1 = 701,	---
3584	SWXC1 = 702,	---	3584	SWXC1 = 702,	---
3585	SUXC1_SUXC164 = 703,	---	3585	SUXC1_SUXC164 = 703,	---
3586	ST_B_ST_D_ST_H_ST_W = 704,	---	3586	ST_B_ST_D_ST_H_ST_W = 704,	---
3587	ST_F16 = 705,	---	3587	ST_F16 = 705,	---
3588	MOVN_I_D32_MOVN_I_D64 = 706,	---	3588	MOVN_I_D32_MOVN_I_D64 = 706,	---
3589	MOVN_I_S = 707,	---	3589	MOVN_I_S = 707,	---
3590	MOVZ_I_D32_MOVZ_I_D64 = 708,	---	3590	MOVZ_I_D32_MOVZ_I_D64 = 708,	---
3591	MOVZ_I_S = 709,	---	3591	MOVZ_I_S = 709,	---
3592	LDC1_LDC164 = 710,	---	3592	LDC1_LDC164 = 710,	---
3593	LDXC1_LDXC164 = 711,	---	3593	LDXC1_LDXC164 = 711,	---
3594	LWC1 = 712,	---	3594	LWC1 = 712,	---
3595	LWXC1 = 713,	---	3595	LWXC1 = 713,	---
3596	LUXC1_LUXC164 = 714,	---	3596	LUXC1_LUXC164 = 714,	---
3597	LD_B_LD_D_LD_H_LD_W = 715,	---	3597	LD_B_LD_D_LD_H_LD_W = 715,	---
3598	LD_F16 = 716,	---	3598	LD_F16 = 716,	---
3599	CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,	---	3599	CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,	---
3600	FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,	---	3600	FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,	---
3601	ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,	---	3601	ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,	---
3602	ROTRV = 720,	---	3602	ROTRV = 720,	---
3603	ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,	---	3603	ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,	---
3604	ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,	---	3604	ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,	---
3605	ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,	---	3605	ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,	---
3606	LEA_ADDiu = 724,	---	3606	LEA_ADDiu = 724,	---
3607	ADDIUPC = 725,	---	3607	ADDIUPC = 725,	---
3608	ALIGN = 726,	---	3608	ALIGN = 726,	---
3609	ALUIPC = 727,	---	3609	ALUIPC = 727,	---
3610	AUI = 728,	---	3610	AUI = 728,	---
3611	AUIPC = 729,	---	3611	AUIPC = 729,	---
3612	BITSWAP = 730,	---	3612	BITSWAP = 730,	---
3613	CLO_R6 = 731,	---	3613	CLO_R6 = 731,	---
3614	CLZ_R6 = 732,	---	3614	CLZ_R6 = 732,	---
3615	LSA_R6 = 733,	---	3615	LSA_R6 = 733,	---
3616	SELEQZ_SELNEZ = 734,	---	3616	SELEQZ_SELNEZ = 734,	---
3617	AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,	---	3617	AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,	---
3618	SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,	---	3618	SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,	---
3619	Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,	---	3619	Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,	---
3620	ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,	---	3620	ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,	---
3621	ADDU16_MM_ADDu_MM = 739,	---	3621	ADDU16_MM_ADDu_MM = 739,	---
3622	ADD_MM = 740,	---	3622	ADD_MM = 740,	---
3623	ADDi_MM = 741,	---	3623	ADDi_MM = 741,	---
3624	AND16_MM_ANDI16_MM_AND_MM = 742,	---	3624	AND16_MM_ANDI16_MM_AND_MM = 742,	---
3625	ANDi_MM = 743,	---	3625	ANDi_MM = 743,	---
3626	CLO_MM = 744,	---	3626	CLO_MM = 744,	---
3627	CLZ_MM = 745,	---	3627	CLZ_MM = 745,	---
3628	EXT_MM = 746,	---	3628	EXT_MM = 746,	---
3629	INS_MM = 747,	---	3629	INS_MM = 747,	---
3630	LI16_MM = 748,	---	3630	LI16_MM = 748,	---
3631	LUi_MM = 749,	---	3631	LUi_MM = 749,	---
3632	MOVE16_MM = 750,	---	3632	MOVE16_MM = 750,	---
3633	MOVEP_MM = 751,	---	3633	MOVEP_MM = 751,	---
3634	NOR_MM = 752,	---	3634	NOR_MM = 752,	---
3635	NOT16_MM = 753,	---	3635	NOT16_MM = 753,	---
3636	OR16_MM_OR_MM = 754,	---	3636	OR16_MM_OR_MM = 754,	---
3637	ORi_MM = 755,	---	3637	ORi_MM = 755,	---
3638	ROTRV_MM = 756,	---	3638	ROTRV_MM = 756,	---
3639	ROTR_MM = 757,	---	3639	ROTR_MM = 757,	---
3640	SEB_MM = 758,	---	3640	SEB_MM = 758,	---
3641	SEH_MM = 759,	---	3641	SEH_MM = 759,	---
3642	SLL16_MM_SLL_MM = 760,	---	3642	SLL16_MM_SLL_MM = 760,	---
3643	SLLV_MM = 761,	---	3643	SLLV_MM = 761,	---
3644	SLT_MM_SLTu_MM = 762,	---	3644	SLT_MM_SLTu_MM = 762,	---
3645	SLTi_MM_SLTiu_MM = 763,	---	3645	SLTi_MM_SLTiu_MM = 763,	---
3646	SRAV_MM = 764,	---	3646	SRAV_MM = 764,	---
3647	SRA_MM = 765,	---	3647	SRA_MM = 765,	---
3648	SRL16_MM_SRL_MM = 766,	---	3648	SRL16_MM_SRL_MM = 766,	---
3649	SRLV_MM = 767,	---	3649	SRLV_MM = 767,	---
3650	SSNOP_MM = 768,	---	3650	SSNOP_MM = 768,	---
3651	SUBU16_MM_SUBu_MM = 769,	---	3651	SUBU16_MM_SUBu_MM = 769,	---
3652	SUB_MM = 770,	---	3652	SUB_MM = 770,	---
3653	WSBH_MM = 771,	---	3653	WSBH_MM = 771,	---
3654	XOR16_MM_XOR_MM = 772,	---	3654	XOR16_MM_XOR_MM = 772,	---
3655	XORi_MM = 773,	---	3655	XORi_MM = 773,	---
3656	ADDIUPC_MMR6 = 774,	---	3656	ADDIUPC_MMR6 = 774,	---
3657	ADDIU_MMR6 = 775,	---	3657	ADDIU_MMR6 = 775,	---
3658	ADDU16_MMR6_ADDU_MMR6 = 776,	---	3658	ADDU16_MMR6_ADDU_MMR6 = 776,	---
3659	ADD_MMR6 = 777,	---	3659	ADD_MMR6 = 777,	---
3660	ALIGN_MMR6 = 778,	---	3660	ALIGN_MMR6 = 778,	---
3661	ALUIPC_MMR6 = 779,	---	3661	ALUIPC_MMR6 = 779,	---
3662	AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,	---	3662	AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,	---
3663	ANDI_MMR6 = 781,	---	3663	ANDI_MMR6 = 781,	---
3664	AUIPC_MMR6 = 782,	---	3664	AUIPC_MMR6 = 782,	---
3665	AUI_MMR6 = 783,	---	3665	AUI_MMR6 = 783,	---
3666	BITSWAP_MMR6 = 784,	---	3666	BITSWAP_MMR6 = 784,	---
3667	CLO_MMR6 = 785,	---	3667	CLO_MMR6 = 785,	---
3668	CLZ_MMR6 = 786,	---	3668	CLZ_MMR6 = 786,	---
3669	EXT_MMR6 = 787,	---	3669	EXT_MMR6 = 787,	---
3670	INS_MMR6 = 788,	---	3670	INS_MMR6 = 788,	---
3671	LI16_MMR6 = 789,	---	3671	LI16_MMR6 = 789,	---
3672	LSA_MMR6 = 790,	---	3672	LSA_MMR6 = 790,	---
3673	LUI_MMR6 = 791,	---	3673	LUI_MMR6 = 791,	---
3674	MOVE16_MMR6 = 792,	---	3674	MOVE16_MMR6 = 792,	---
3675	NOR_MMR6 = 793,	---	3675	NOR_MMR6 = 793,	---
3676	NOT16_MMR6 = 794,	---	3676	NOT16_MMR6 = 794,	---
3677	OR16_MMR6_OR_MMR6 = 795,	---	3677	OR16_MMR6_OR_MMR6 = 795,	---
3678	ORI_MMR6 = 796,	---	3678	ORI_MMR6 = 796,	---
3679	SELEQZ_MMR6_SELNEZ_MMR6 = 797,	---	3679	SELEQZ_MMR6_SELNEZ_MMR6 = 797,	---
3680	SLL16_MMR6_SLL_MMR6 = 798,	---	3680	SLL16_MMR6_SLL_MMR6 = 798,	---
3681	SRL16_MMR6 = 799,	---	3681	SRL16_MMR6 = 799,	---
3682	SSNOP_MMR6 = 800,	---	3682	SSNOP_MMR6 = 800,	---
3683	SUBU16_MMR6_SUBU_MMR6 = 801,	---	3683	SUBU16_MMR6_SUBU_MMR6 = 801,	---
3684	SUB_MMR6 = 802,	---	3684	SUB_MMR6 = 802,	---
3685	WSBH_MMR6 = 803,	---	3685	WSBH_MMR6 = 803,	---
3686	XOR16_MMR6_XOR_MMR6 = 804,	---	3686	XOR16_MMR6_XOR_MMR6 = 804,	---
3687	XORI_MMR6 = 805,	---	3687	XORI_MMR6 = 805,	---
3688	AND64_ANDi64 = 806,	---	3688	AND64_ANDi64 = 806,	---
3689	DEXT64_32 = 807,	---	3689	DEXT64_32 = 807,	---
3690	DSLL64_32 = 808,	---	3690	DSLL64_32 = 808,	---
3691	ORi64 = 809,	---	3691	ORi64 = 809,	---
3692	SEB64 = 810,	---	3692	SEB64 = 810,	---
3693	SEH64 = 811,	---	3693	SEH64 = 811,	---
3694	SLL64_32_SLL64_64 = 812,	---	3694	SLL64_32_SLL64_64 = 812,	---
3695	SLT64_SLTu64 = 813,	---	3695	SLT64_SLTu64 = 813,	---
3696	SLTi64_SLTiu64 = 814,	---	3696	SLTi64_SLTiu64 = 814,	---
3697	XOR64_XORi64 = 815,	---	3697	XOR64_XORi64 = 815,	---
3698	DADD = 816,	---	3698	DADD = 816,	---
3699	DADDi = 817,	---	3699	DADDi = 817,	---
3700	DADDiu = 818,	---	3700	DADDiu = 818,	---
3701	DADDu = 819,	---	3701	DADDu = 819,	---
3702	DCLO = 820,	---	3702	DCLO = 820,	---
3703	DCLZ = 821,	---	3703	DCLZ = 821,	---
3704	DEXT_DEXTM_DEXTU = 822,	---	3704	DEXT_DEXTM_DEXTU = 822,	---
3705	DINS_DINSM_DINSU = 823,	---	3705	DINS_DINSM_DINSU = 823,	---
3706	DROTR = 824,	---	3706	DROTR = 824,	---
3707	DROTR32 = 825,	---	3707	DROTR32 = 825,	---
3708	DROTRV = 826,	---	3708	DROTRV = 826,	---
3709	DSBH = 827,	---	3709	DSBH = 827,	---
3710	DSHD = 828,	---	3710	DSHD = 828,	---
3711	DSLL = 829,	---	3711	DSLL = 829,	---
3712	DSLL32 = 830,	---	3712	DSLL32 = 830,	---
3713	DSLLV = 831,	---	3713	DSLLV = 831,	---
3714	DSRA = 832,	---	3714	DSRA = 832,	---
3715	DSRA32 = 833,	---	3715	DSRA32 = 833,	---
3716	DSRAV = 834,	---	3716	DSRAV = 834,	---
3717	DSRL = 835,	---	3717	DSRL = 835,	---
3718	DSRL32 = 836,	---	3718	DSRL32 = 836,	---
3719	DSRLV = 837,	---	3719	DSRLV = 837,	---
3720	DSUB = 838,	---	3720	DSUB = 838,	---
3721	DSUBu = 839,	---	3721	DSUBu = 839,	---
3722	LEA_ADDiu64 = 840,	---	3722	LEA_ADDiu64 = 840,	---
3723	LUi64 = 841,	---	3723	LUi64 = 841,	---
3724	NOR64 = 842,	---	3724	NOR64 = 842,	---
3725	OR64 = 843,	---	3725	OR64 = 843,	---
3726	DALIGN = 844,	---	3726	DALIGN = 844,	---
3727	DAHI = 845,	---	3727	DAHI = 845,	---
3728	DATI = 846,	---	3728	DATI = 846,	---
3729	DAUI = 847,	---	3729	DAUI = 847,	---
3730	DCLO_R6 = 848,	---	3730	DCLO_R6 = 848,	---
3731	DCLZ_R6 = 849,	---	3731	DCLZ_R6 = 849,	---
3732	DBITSWAP = 850,	---	3732	DBITSWAP = 850,	---
3733	DLSA_DLSA_R6 = 851,	---	3733	DLSA_DLSA_R6 = 851,	---
3734	SELEQZ64_SELNEZ64 = 852,	---	3734	SELEQZ64_SELNEZ64 = 852,	---
3735	MADD = 853,	---	3735	MADD = 853,	---
3736	MADDU = 854,	---	3736	MADDU = 854,	---
3737	MSUB = 855,	---	3737	MSUB = 855,	---
3738	MSUBU = 856,	---	3738	MSUBU = 856,	---
3739	PseudoMADD_MM = 857,	---	3739	PseudoMADD_MM = 857,	---
3740	PseudoMADDU_MM = 858,	---	3740	PseudoMADDU_MM = 858,	---
3741	PseudoMSUB_MM = 859,	---	3741	PseudoMSUB_MM = 859,	---
3742	PseudoMSUBU_MM = 860,	---	3742	PseudoMSUBU_MM = 860,	---
3743	PseudoMULT_MM = 861,	---	3743	PseudoMULT_MM = 861,	---
3744	PseudoMULTu_MM = 862,	---	3744	PseudoMULTu_MM = 862,	---
3745	PseudoMULT = 863,	---	3745	PseudoMULT = 863,	---
3746	PseudoMULTu = 864,	---	3746	PseudoMULTu = 864,	---
3747	PseudoSDIV_SDIV = 865,	---	3747	PseudoSDIV_SDIV = 865,	---
3748	PseudoUDIV_UDIV = 866,	---	3748	PseudoUDIV_UDIV = 866,	---
3749	PseudoMFHI_MM_PseudoMFLO_MM = 867,	---	3749	PseudoMFHI_MM_PseudoMFLO_MM = 867,	---
3750	PseudoMTLOHI_MM = 868,	---	3750	PseudoMTLOHI_MM = 868,	---
3751	MUH = 869,	---	3751	MUH = 869,	---
3752	MUHU = 870,	---	3752	MUHU = 870,	---
3753	MULU = 871,	---	3753	MULU = 871,	---
3754	MUL_R6 = 872,	---	3754	MUL_R6 = 872,	---
3755	MOD = 873,	---	3755	MOD = 873,	---
3756	MODU = 874,	---	3756	MODU = 874,	---
3757	MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,	---	3757	MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,	---
3758	DivRxRy16 = 876,	---	3758	DivRxRy16 = 876,	---
3759	DivuRxRy16 = 877,	---	3759	DivuRxRy16 = 877,	---
3760	MULT_MM = 878,	---	3760	MULT_MM = 878,	---
3761	MULTu_MM = 879,	---	3761	MULTu_MM = 879,	---
3762	MADD_MM = 880,	---	3762	MADD_MM = 880,	---
3763	MADDU_MM = 881,	---	3763	MADDU_MM = 881,	---
3764	MSUB_MM = 882,	---	3764	MSUB_MM = 882,	---
3765	MSUBU_MM = 883,	---	3765	MSUBU_MM = 883,	---
3766	MUL_MM = 884,	---	3766	MUL_MM = 884,	---
3767	SDIV_MM_SDIV_MM_Pseudo = 885,	---	3767	SDIV_MM_SDIV_MM_Pseudo = 885,	---
3768	UDIV_MM_UDIV_MM_Pseudo = 886,	---	3768	UDIV_MM_UDIV_MM_Pseudo = 886,	---
3769	MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,	---	3769	MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,	---
3770	MOVF_I_MM = 888,	---	3770	MOVF_I_MM = 888,	---
3771	MOVT_I_MM = 889,	---	3771	MOVT_I_MM = 889,	---
3772	MTHI_MM_MTLO_MM = 890,	---	3772	MTHI_MM_MTLO_MM = 890,	---
3773	RDHWR_MM = 891,	---	3773	RDHWR_MM = 891,	---
3774	MUHU_MMR6 = 892,	---	3774	MUHU_MMR6 = 892,	---
3775	MUH_MMR6 = 893,	---	3775	MUH_MMR6 = 893,	---
3776	MULU_MMR6 = 894,	---	3776	MULU_MMR6 = 894,	---
3777	MUL_MMR6 = 895,	---	3777	MUL_MMR6 = 895,	---
3778	MODU_MMR6 = 896,	---	3778	MODU_MMR6 = 896,	---
3779	MOD_MMR6 = 897,	---	3779	MOD_MMR6 = 897,	---
3780	DIVU_MMR6 = 898,	---	3780	DIVU_MMR6 = 898,	---
3781	DIV_MMR6 = 899,	---	3781	DIV_MMR6 = 899,	---
3782	RDHWR_MMR6 = 900,	---	3782	RDHWR_MMR6 = 900,	---
3783	DMULU = 901,	---	3783	DMULU = 901,	---
3784	DMULT_PseudoDMULT = 902,	---	3784	DMULT_PseudoDMULT = 902,	---
3785	DMULTu_PseudoDMULTu = 903,	---	3785	DMULTu_PseudoDMULTu = 903,	---
3786	DSDIV_PseudoDSDIV = 904,	---	3786	DSDIV_PseudoDSDIV = 904,	---
3787	DUDIV_PseudoDUDIV = 905,	---	3787	DUDIV_PseudoDUDIV = 905,	---
3788	MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,	---	3788	MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,	---
3789	PseudoMTLOHI64 = 907,	---	3789	PseudoMTLOHI64 = 907,	---
3790	MTHI64_MTLO64 = 908,	---	3790	MTHI64_MTLO64 = 908,	---
3791	RDHWR64 = 909,	---	3791	RDHWR64 = 909,	---
3792	MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,	---	3792	MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,	---
3793	MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,	---	3793	MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,	---
3794	DMUH = 912,	---	3794	DMUH = 912,	---
3795	DMUHU = 913,	---	3795	DMUHU = 913,	---
3796	DMUL_R6 = 914,	---	3796	DMUL_R6 = 914,	---
3797	DDIV = 915,	---	3797	DDIV = 915,	---
3798	DMOD = 916,	---	3798	DMOD = 916,	---
3799	DDIVU = 917,	---	3799	DDIVU = 917,	---
3800	DMODU = 918,	---	3800	DMODU = 918,	---
3801	BAL_BR_BLTZAL = 919,	---	3801	BAL_BR_BLTZAL = 919,	---
3802	BEQ_BNE = 920,	---	3802	BEQ_BNE = 920,	---
3803	BGTZ_BGEZ_BLEZ_BLTZ = 921,	---	3803	BGTZ_BGEZ_BLEZ_BLTZ = 921,	---
3804	J = 922,	---	3804	J = 922,	---
3805	JR = 923,	---	3805	JR = 923,	---
3806	ERet = 924,	---	3806	ERet = 924,	---
3807	BGEZAL = 925,	---	3807	BGEZAL = 925,	---
3808	BALC = 926,	---	3808	BALC = 926,	---
3809	BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927,	---	3809	BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927,	---
3810	JIALC = 928,	---	3810	JIALC = 928,	---
3811	BC = 929,	---	3811	BC = 929,	---
3812	BC2EQZ_BC2NEZ = 930,	---	3812	BC2EQZ_BC2NEZ = 930,	---
3813	BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931,	---	3813	BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931,	---
3814	BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932,	---	3814	BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932,	---
3815	JIC = 933,	---	3815	JIC = 933,	---
3816	JR_HB_R6 = 934,	---	3816	JR_HB_R6 = 934,	---
3817	SIGRIE = 935,	---	3817	SIGRIE = 935,	---
3818	PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936,	---	3818	PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936,	---
3819	TAILCALLR6REG_TAILCALLHBR6REG = 937,	---	3819	TAILCALLR6REG_TAILCALLHBR6REG = 937,	---
3820	SDBBP_R6 = 938,	---	3820	SDBBP_R6 = 938,	---
3821	Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939,	---	3821	Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939,	---
3822	BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940,	---	3822	BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940,	---
3823	Jal16_JalB16 = 941,	---	3823	Jal16_JalB16 = 941,	---
3824	JumpLinkReg16 = 942,	---	3824	JumpLinkReg16 = 942,	---
3825	Break16 = 943,	---	3825	Break16 = 943,	---
3826	SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944,	---	3826	SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944,	---
3827	B16_MM_B_MM = 945,	---	3827	B16_MM_B_MM = 945,	---
3828	BAL_BR_MM = 946,	---	3828	BAL_BR_MM = 946,	---
3829	BC1F_MM = 947,	---	3829	BC1F_MM = 947,	---
3830	BC1T_MM = 948,	---	3830	BC1T_MM = 948,	---
3831	BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949,	---	3831	BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949,	---
3832	BEQZC_MM_BNEZC_MM = 950,	---	3832	BEQZC_MM_BNEZC_MM = 950,	---
3833	BEQ_MM_BNE_MM = 951,	---	3833	BEQ_MM_BNE_MM = 951,	---
3834	DERET_MM = 952,	---	3834	DERET_MM = 952,	---
3835	ERET_MM = 953,	---	3835	ERET_MM = 953,	---
3836	JR16_MM_JR_MM = 954,	---	3836	JR16_MM_JR_MM = 954,	---
3837	J_MM = 955,	---	3837	J_MM = 955,	---
3838	B_MM_Pseudo = 956,	---	3838	B_MM_Pseudo = 956,	---
3839	BGEZALS_MM_BLTZALS_MM = 957,	---	3839	BGEZALS_MM_BLTZALS_MM = 957,	---
3840	BGEZAL_MM_BLTZAL_MM = 958,	---	3840	BGEZAL_MM_BLTZAL_MM = 958,	---
3841	JALR16_MM_JALR_MM = 959,	---	3841	JALR16_MM_JALR_MM = 959,	---
3842	JALRS16_MM_JALRS_MM = 960,	---	3842	JALRS16_MM_JALRS_MM = 960,	---
3843	JALS_MM = 961,	---	3843	JALS_MM = 961,	---
3844	JALX_MM_JAL_MM = 962,	---	3844	JALX_MM_JAL_MM = 962,	---
3845	TAILCALLREG_MM = 963,	---	3845	TAILCALLREG_MM = 963,	---
3846	TAILCALL_MM = 964,	---	3846	TAILCALL_MM = 964,	---
3847	PseudoIndirectBranch_MM = 965,	---	3847	PseudoIndirectBranch_MM = 965,	---
3848	BREAK16_MM_BREAK_MM = 966,	---	3848	BREAK16_MM_BREAK_MM = 966,	---
3849	SDBBP16_MM_SDBBP_MM = 967,	---	3849	SDBBP16_MM_SDBBP_MM = 967,	---
3850	SYSCALL_MM = 968,	---	3850	SYSCALL_MM = 968,	---
3851	TEQI_MM = 969,	---	3851	TEQI_MM = 969,	---
3852	TEQ_MM = 970,	---	3852	TEQ_MM = 970,	---
3853	TGEIU_MM = 971,	---	3853	TGEIU_MM = 971,	---
3854	TGEI_MM = 972,	---	3854	TGEI_MM = 972,	---
3855	TGEU_MM = 973,	---	3855	TGEU_MM = 973,	---
3856	TGE_MM = 974,	---	3856	TGE_MM = 974,	---
3857	TLTIU_MM = 975,	---	3857	TLTIU_MM = 975,	---
3858	TLTI_MM = 976,	---	3858	TLTI_MM = 976,	---
3859	TLTU_MM = 977,	---	3859	TLTU_MM = 977,	---
3860	TLT_MM = 978,	---	3860	TLT_MM = 978,	---
3861	TNEI_MM = 979,	---	3861	TNEI_MM = 979,	---
3862	TNE_MM = 980,	---	3862	TNE_MM = 980,	---
3863	TRAP_MM = 981,	---	3863	TRAP_MM = 981,	---
3864	BC16_MMR6_BC_MMR6 = 982,	---	3864	BC16_MMR6_BC_MMR6 = 982,	---
3865	BC1EQZC_MMR6_BC1NEZC_MMR6 = 983,	---	3865	BC1EQZC_MMR6_BC1NEZC_MMR6 = 983,	---
3866	BC2EQZC_MMR6_BC2NEZC_MMR6 = 984,	---	3866	BC2EQZC_MMR6_BC2NEZC_MMR6 = 984,	---
3867	BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985,	---	3867	BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985,	---
3868	BEQZC16_MMR6_BNEZC16_MMR6 = 986,	---	3868	BEQZC16_MMR6_BNEZC16_MMR6 = 986,	---
3869	BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987,	---	3869	BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987,	---
3870	DERET_MMR6 = 988,	---	3870	DERET_MMR6 = 988,	---
3871	ERETNC_MMR6 = 989,	---	3871	ERETNC_MMR6 = 989,	---
3872	JAL_MMR6 = 990,	---	3872	JAL_MMR6 = 990,	---
3873	ERET_MMR6 = 991,	---	3873	ERET_MMR6 = 991,	---
3874	JIC_MMR6 = 992,	---	3874	JIC_MMR6 = 992,	---
3875	JRADDIUSP_JRCADDIUSP_MMR6 = 993,	---	3875	JRADDIUSP_JRCADDIUSP_MMR6 = 993,	---
3876	JRC16_MM = 994,	---	3876	JRC16_MM = 994,	---
3877	JRC16_MMR6 = 995,	---	3877	JRC16_MMR6 = 995,	---
3878	SIGRIE_MMR6 = 996,	---	3878	SIGRIE_MMR6 = 996,	---
3879	B_MMR6_Pseudo = 997,	---	3879	B_MMR6_Pseudo = 997,	---
3880	PseudoIndirectBranch_MMR6 = 998,	---	3880	PseudoIndirectBranch_MMR6 = 998,	---
3881	BALC_MMR6 = 999,	---	3881	BALC_MMR6 = 999,	---
3882	BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000,	---	3882	BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000,	---
3883	JALRC16_MMR6 = 1001,	---	3883	JALRC16_MMR6 = 1001,	---
3884	JALRC_HB_MMR6 = 1002,	---	3884	JALRC_HB_MMR6 = 1002,	---
3885	JALRC_MMR6 = 1003,	---	3885	JALRC_MMR6 = 1003,	---
3886	JIALC_MMR6 = 1004,	---	3886	JIALC_MMR6 = 1004,	---
3887	TAILCALLREG_MMR6 = 1005,	---	3887	TAILCALLREG_MMR6 = 1005,	---
3888	TAILCALL_MMR6 = 1006,	---	3888	TAILCALL_MMR6 = 1006,	---
3889	BREAK16_MMR6_BREAK_MMR6 = 1007,	---	3889	BREAK16_MMR6_BREAK_MMR6 = 1007,	---
3890	SDBBP_MMR6_SDBBP16_MMR6 = 1008,	---	3890	SDBBP_MMR6_SDBBP16_MMR6 = 1008,	---
3891	BEQ64_BNE64 = 1009,	---	3891	BEQ64_BNE64 = 1009,	---
3892	BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010,	---	3892	BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010,	---
3893	JR64 = 1011,	---	3893	JR64 = 1011,	---
3894	JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012,	---	3894	JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012,	---
3895	JALR_HB64 = 1013,	---	3895	JALR_HB64 = 1013,	---
3896	JR_HB64 = 1014,	---	3896	JR_HB64 = 1014,	---
3897	TAILCALLREG64_TAILCALLREGHB64 = 1015,	---	3897	TAILCALLREG64_TAILCALLREGHB64 = 1015,	---
3898	PseudoReturn64 = 1016,	---	3898	PseudoReturn64 = 1016,	---
3899	BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017,	---	3899	BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017,	---
3900	BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018,	---	3900	BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018,	---
3901	JIC64 = 1019,	---	3901	JIC64 = 1019,	---
3902	PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020,	---	3902	PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020,	---
3903	JIALC64 = 1021,	---	3903	JIALC64 = 1021,	---
3904	JR_HB64_R6 = 1022,	---	3904	JR_HB64_R6 = 1022,	---
3905	TAILCALL64R6REG_TAILCALLHB64R6REG = 1023,	---	3905	TAILCALL64R6REG_TAILCALLHB64R6REG = 1023,	---
3906	PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024,	---	3906	PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024,	---
3907	EVP = 1025,	---	3907	EVP = 1025,	---
3908	DVP = 1026,	---	3908	DVP = 1026,	---
3909	TLBP_MM = 1027,	---	3909	TLBP_MM = 1027,	---
3910	TLBR_MM = 1028,	---	3910	TLBR_MM = 1028,	---
3911	TLBWI_MM = 1029,	---	3911	TLBWI_MM = 1029,	---
3912	TLBWR_MM = 1030,	---	3912	TLBWR_MM = 1030,	---
3913	DI_MM = 1031,	---	3913	DI_MM = 1031,	---
3914	EI_MM = 1032,	---	3914	EI_MM = 1032,	---
3915	EHB_MM = 1033,	---	3915	EHB_MM = 1033,	---
3916	PAUSE_MM = 1034,	---	3916	PAUSE_MM = 1034,	---
3917	WAIT_MM = 1035,	---	3917	WAIT_MM = 1035,	---
3918	RDPGPR_MMR6 = 1036,	---	3918	RDPGPR_MMR6 = 1036,	---
3919	WRPGPR_MMR6 = 1037,	---	3919	WRPGPR_MMR6 = 1037,	---
3920	TLBINV_MMR6 = 1038,	---	3920	TLBINV_MMR6 = 1038,	---
3921	TLBINVF_MMR6 = 1039,	---	3921	TLBINVF_MMR6 = 1039,	---
3922	MFHC0_MMR6 = 1040,	---	3922	MFHC0_MMR6 = 1040,	---
3923	MFC0_MMR6 = 1041,	---	3923	MFC0_MMR6 = 1041,	---
3924	MFHC2_MMR6_MFC2_MMR6 = 1042,	---	3924	MFHC2_MMR6_MFC2_MMR6 = 1042,	---
3925	MTHC0_MMR6 = 1043,	---	3925	MTHC0_MMR6 = 1043,	---
3926	MTC0_MMR6 = 1044,	---	3926	MTC0_MMR6 = 1044,	---
3927	MTHC2_MMR6_MTC2_MMR6 = 1045,	---	3927	MTHC2_MMR6_MTC2_MMR6 = 1045,	---
3928	EVP_MMR6 = 1046,	---	3928	EVP_MMR6 = 1046,	---
3929	DVP_MMR6 = 1047,	---	3929	DVP_MMR6 = 1047,	---
3930	DI_MMR6 = 1048,	---	3930	DI_MMR6 = 1048,	---
3931	EI_MMR6 = 1049,	---	3931	EI_MMR6 = 1049,	---
3932	EHB_MMR6 = 1050,	---	3932	EHB_MMR6 = 1050,	---
3933	PAUSE_MMR6 = 1051,	---	3933	PAUSE_MMR6 = 1051,	---
3934	WAIT_MMR6 = 1052,	---	3934	WAIT_MMR6 = 1052,	---
3935	DMFC0 = 1053,	---	3935	DMFC0 = 1053,	---
3936	DMTC0 = 1054,	---	3936	DMTC0 = 1054,	---
3937	DMFC2 = 1055,	---	3937	DMFC2 = 1055,	---
3938	DMTC2 = 1056,	---	3938	DMTC2 = 1056,	---
3939	CFC2_MM = 1057,	---	3939	CFC2_MM = 1057,	---
3940	CTC2_MM = 1058,	---	3940	CTC2_MM = 1058,	---
3941	DMT = 1059,	---	3941	DMT = 1059,	---
3942	DVPE = 1060,	---	3942	DVPE = 1060,	---
3943	EMT = 1061,	---	3943	EMT = 1061,	---
3944	EVPE = 1062,	---	3944	EVPE = 1062,	---
3945	MFTR = 1063,	---	3945	MFTR = 1063,	---
3946	MTTR = 1064,	---	3946	MTTR = 1064,	---
3947	YIELD = 1065,	---	3947	YIELD = 1065,	---
3948	FORK = 1066,	---	3948	FORK = 1066,	---
3949	DMFGC0 = 1067,	---	3949	DMFGC0 = 1067,	---
3950	DMTGC0 = 1068,	---	3950	DMTGC0 = 1068,	---
3951	HYPCALL_MM = 1069,	---	3951	HYPCALL_MM = 1069,	---
3952	TLBGINVF_MM = 1070,	---	3952	TLBGINVF_MM = 1070,	---
3953	TLBGINV_MM = 1071,	---	3953	TLBGINV_MM = 1071,	---
3954	TLBGP_MM = 1072,	---	3954	TLBGP_MM = 1072,	---
3955	TLBGR_MM = 1073,	---	3955	TLBGR_MM = 1073,	---
3956	TLBGWI_MM = 1074,	---	3956	TLBGWI_MM = 1074,	---
3957	TLBGWR_MM = 1075,	---	3957	TLBGWR_MM = 1075,	---
3958	MFGC0_MM = 1076,	---	3958	MFGC0_MM = 1076,	---
3959	MFHGC0_MM = 1077,	---	3959	MFHGC0_MM = 1077,	---
3960	MTGC0_MM = 1078,	---	3960	MTGC0_MM = 1078,	---
3961	MTHGC0_MM = 1079,	---	3961	MTHGC0_MM = 1079,	---
3962	SC_MMR6 = 1080,	---	3962	SC_MMR6 = 1080,	---
3963	LDC2_R6 = 1081,	---	3963	LDC2_R6 = 1081,	---
3964	LL_R6 = 1082,	---	3964	LL_R6 = 1082,	---
3965	LWC2_R6 = 1083,	---	3965	LWC2_R6 = 1083,	---
3966	SWC2_R6 = 1084,	---	3966	SWC2_R6 = 1084,	---
3967	SDC2_R6 = 1085,	---	3967	SDC2_R6 = 1085,	---
3968	SC_R6 = 1086,	---	3968	SC_R6 = 1086,	---
3969	PREF_R6 = 1087,	---	3969	PREF_R6 = 1087,	---
3970	CACHE_R6 = 1088,	---	3970	CACHE_R6 = 1088,	---
3971	GINVI = 1089,	---	3971	GINVI = 1089,	---
3972	GINVT = 1090,	---	3972	GINVT = 1090,	---
3973	LBE_MM = 1091,	---	3973	LBE_MM = 1091,	---
3974	LBuE_MM = 1092,	---	3974	LBuE_MM = 1092,	---
3975	LHE_MM = 1093,	---	3975	LHE_MM = 1093,	---
3976	LHuE_MM = 1094,	---	3976	LHuE_MM = 1094,	---
3977	LWE_MM = 1095,	---	3977	LWE_MM = 1095,	---
3978	LWLE_MM = 1096,	---	3978	LWLE_MM = 1096,	---
3979	LWRE_MM = 1097,	---	3979	LWRE_MM = 1097,	---
3980	LLE_MM = 1098,	---	3980	LLE_MM = 1098,	---
3981	SBE_MM = 1099,	---	3981	SBE_MM = 1099,	---
3982	SB_MM = 1100,	---	3982	SB_MM = 1100,	---
3983	SHE_MM = 1101,	---	3983	SHE_MM = 1101,	---
3984	SWE_MM = 1102,	---	3984	SWE_MM = 1102,	---
3985	SWLE_MM = 1103,	---	3985	SWLE_MM = 1103,	---
3986	SWRE_MM = 1104,	---	3986	SWRE_MM = 1104,	---
3987	SCE_MM = 1105,	---	3987	SCE_MM = 1105,	---
3988	PREFE_MM = 1106,	---	3988	PREFE_MM = 1106,	---
3989	CACHEE_MM = 1107,	---	3989	CACHEE_MM = 1107,	---
3990	Restore16_RestoreX16 = 1108,	---	3990	Restore16_RestoreX16 = 1108,	---
3991	LbRxRyOffMemX16 = 1109,	---	3991	LbRxRyOffMemX16 = 1109,	---
3992	LbuRxRyOffMemX16 = 1110,	---	3992	LbuRxRyOffMemX16 = 1110,	---
3993	LhRxRyOffMemX16 = 1111,	---	3993	LhRxRyOffMemX16 = 1111,	---
3994	LhuRxRyOffMemX16 = 1112,	---	3994	LhuRxRyOffMemX16 = 1112,	---
3995	LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113,	---	3995	LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113,	---
3996	Save16_SaveX16 = 1114,	---	3996	Save16_SaveX16 = 1114,	---
3997	SbRxRyOffMemX16 = 1115,	---	3997	SbRxRyOffMemX16 = 1115,	---
3998	ShRxRyOffMemX16 = 1116,	---	3998	ShRxRyOffMemX16 = 1116,	---
3999	SwRxRyOffMemX16_SwRxSpImmX16 = 1117,	---	3999	SwRxRyOffMemX16_SwRxSpImmX16 = 1117,	---
4000	LBU16_MM_LBu_MM = 1118,	---	4000	LBU16_MM_LBu_MM = 1118,	---
4001	LB_MM = 1119,	---	4001	LB_MM = 1119,	---
4002	LHU16_MM_LHu_MM = 1120,	---	4002	LHU16_MM_LHu_MM = 1120,	---
4003	LH_MM = 1121,	---	4003	LH_MM = 1121,	---
4004	LL_MM = 1122,	---	4004	LL_MM = 1122,	---
4005	LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123,	---	4005	LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123,	---
4006	LWL_MM = 1124,	---	4006	LWL_MM = 1124,	---
4007	LWM16_MM_LWM32_MM = 1125,	---	4007	LWM16_MM_LWM32_MM = 1125,	---
4008	LWP_MM = 1126,	---	4008	LWP_MM = 1126,	---
4009	LWR_MM = 1127,	---	4009	LWR_MM = 1127,	---
4010	LWU_MM = 1128,	---	4010	LWU_MM = 1128,	---
4011	LWXS_MM = 1129,	---	4011	LWXS_MM = 1129,	---
4012	SB16_MM = 1130,	---	4012	SB16_MM = 1130,	---
4013	SC_MM = 1131,	---	4013	SC_MM = 1131,	---
4014	SH16_MM_SH_MM = 1132,	---	4014	SH16_MM_SH_MM = 1132,	---
4015	SW16_MM_SWSP_MM_SW_MM = 1133,	---	4015	SW16_MM_SWSP_MM_SW_MM = 1133,	---
4016	SWL_MM = 1134,	---	4016	SWL_MM = 1134,	---
4017	SWM16_MM_SWM32_MM = 1135,	---	4017	SWM16_MM_SWM32_MM = 1135,	---
4018	SWM_MM = 1136,	---	4018	SWM_MM = 1136,	---
4019	SWP_MM = 1137,	---	4019	SWP_MM = 1137,	---
4020	SWR_MM = 1138,	---	4020	SWR_MM = 1138,	---
4021	PREF_MM_PREFX_MM = 1139,	---	4021	PREF_MM_PREFX_MM = 1139,	---
4022	CACHE_MM = 1140,	---	4022	CACHE_MM = 1140,	---
4023	SYNC_MM = 1141,	---	4023	SYNC_MM = 1141,	---
4024	SYNCI_MM = 1142,	---	4024	SYNCI_MM = 1142,	---
4025	GINVI_MMR6 = 1143,	---	4025	GINVI_MMR6 = 1143,	---
4026	GINVT_MMR6 = 1144,	---	4026	GINVT_MMR6 = 1144,	---
4027	LBU_MMR6 = 1145,	---	4027	LBU_MMR6 = 1145,	---
4028	LB_MMR6 = 1146,	---	4028	LB_MMR6 = 1146,	---
4029	LDC2_MMR6 = 1147,	---	4029	LDC2_MMR6 = 1147,	---
4030	LL_MMR6 = 1148,	---	4030	LL_MMR6 = 1148,	---
4031	LWM16_MMR6 = 1149,	---	4031	LWM16_MMR6 = 1149,	---
4032	LWC2_MMR6 = 1150,	---	4032	LWC2_MMR6 = 1150,	---
4033	LWPC_MMR6 = 1151,	---	4033	LWPC_MMR6 = 1151,	---
4034	LW_MMR6 = 1152,	---	4034	LW_MMR6 = 1152,	---
4035	SB16_MMR6_SB_MMR6 = 1153,	---	4035	SB16_MMR6_SB_MMR6 = 1153,	---
4036	SDC2_MMR6 = 1154,	---	4036	SDC2_MMR6 = 1154,	---
4037	SH16_MMR6_SH_MMR6 = 1155,	---	4037	SH16_MMR6_SH_MMR6 = 1155,	---
4038	SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156,	---	4038	SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156,	---
4039	SWC2_MMR6 = 1157,	---	4039	SWC2_MMR6 = 1157,	---
4040	SWM16_MMR6 = 1158,	---	4040	SWM16_MMR6 = 1158,	---
4041	SYNC_MMR6 = 1159,	---	4041	SYNC_MMR6 = 1159,	---
4042	SYNCI_MMR6 = 1160,	---	4042	SYNCI_MMR6 = 1160,	---
4043	PREF_MMR6 = 1161,	---	4043	PREF_MMR6 = 1161,	---
4044	CACHE_MMR6 = 1162,	---	4044	CACHE_MMR6 = 1162,	---
4045	LD = 1163,	---	4045	LD = 1163,	---
4046	LL64_LLD = 1164,	---	4046	LL64_LLD = 1164,	---
4047	LWu = 1165,	---	4047	LWu = 1165,	---
4048	LB64 = 1166,	---	4048	LB64 = 1166,	---
4049	LBu64 = 1167,	---	4049	LBu64 = 1167,	---
4050	LH64 = 1168,	---	4050	LH64 = 1168,	---
4051	LHu64 = 1169,	---	4051	LHu64 = 1169,	---
4052	LW64 = 1170,	---	4052	LW64 = 1170,	---
4053	LWL64 = 1171,	---	4053	LWL64 = 1171,	---
4054	LWR64 = 1172,	---	4054	LWR64 = 1172,	---
4055	LDL = 1173,	---	4055	LDL = 1173,	---
4056	LDR = 1174,	---	4056	LDR = 1174,	---
4057	SD = 1175,	---	4057	SD = 1175,	---
4058	SC64_SCD = 1176,	---	4058	SC64_SCD = 1176,	---
4059	SB64 = 1177,	---	4059	SB64 = 1177,	---
4060	SH64 = 1178,	---	4060	SH64 = 1178,	---
4061	SW64 = 1179,	---	4061	SW64 = 1179,	---
4062	SWL64 = 1180,	---	4062	SWL64 = 1180,	---
4063	SWR64 = 1181,	---	4063	SWR64 = 1181,	---
4064	SDL = 1182,	---	4064	SDL = 1182,	---
4065	SDR = 1183,	---	4065	SDR = 1183,	---
4066	LWUPC = 1184,	---	4066	LWUPC = 1184,	---
4067	LDPC = 1185,	---	4067	LDPC = 1185,	---
4068	LLD_R6 = 1186,	---	4068	LLD_R6 = 1186,	---
4069	LL64_R6 = 1187,	---	4069	LL64_R6 = 1187,	---
4070	SC64_R6 = 1188,	---	4070	SC64_R6 = 1188,	---
4071	SCD_R6 = 1189,	---	4071	SCD_R6 = 1189,	---
4072	CRC32B = 1190,	---	4072	CRC32B = 1190,	---
4073	CRC32H = 1191,	---	4073	CRC32H = 1191,	---
4074	CRC32W = 1192,	---	4074	CRC32W = 1192,	---
4075	CRC32CB = 1193,	---	4075	CRC32CB = 1193,	---
4076	CRC32CH = 1194,	---	4076	CRC32CH = 1194,	---
4077	CRC32CW = 1195,	---	4077	CRC32CW = 1195,	---
4078	CRC32D = 1196,	---	4078	CRC32D = 1196,	---
4079	CRC32CD = 1197,	---	4079	CRC32CD = 1197,	---
4080	BADDu = 1198,	---	4080	BADDu = 1198,	---
4081	BBIT0_BBIT032_BBIT1_BBIT132 = 1199,	---	4081	BBIT0_BBIT032_BBIT1_BBIT132 = 1199,	---
4082	CINS_CINS32_CINS64_32_CINS_i32 = 1200,	---	4082	CINS_CINS32_CINS64_32_CINS_i32 = 1200,	---
4083	DMFC2_OCTEON = 1201,	---	4083	DMFC2_OCTEON = 1201,	---
4084	DMTC2_OCTEON = 1202,	---	4084	DMTC2_OCTEON = 1202,	---
4085	DPOP_POP = 1203,	---	4085	DPOP_POP = 1203,	---
4086	EXTS_EXTS32 = 1204,	---	4086	EXTS_EXTS32 = 1204,	---
4087	MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205,	---	4087	MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205,	---
4088	SEQ_SNE = 1206,	---	4088	SEQ_SNE = 1206,	---
4089	SEQi_SNEi = 1207,	---	4089	SEQi_SNEi = 1207,	---
4090	V3MULU_VMM0_VMULU = 1208,	---	4090	V3MULU_VMM0_VMULU = 1208,	---
4091	DMUL = 1209,	---	4091	DMUL = 1209,	---
4092	SAA_SAAD = 1210,	---	4092	SAA_SAAD = 1210,	---
4093	ADDR_PS64 = 1211,	---	4093	ADDR_PS64 = 1211,	---
4094	CVT_PS_PW64_CVT_PW_PS64 = 1212,	---	4094	CVT_PS_PW64_CVT_PW_PS64 = 1212,	---
4095	MULR_PS64 = 1213,	---	4095	MULR_PS64 = 1213,	---
4096	PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214,	---	4096	PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214,	---
4097	MOVT_I64 = 1215,	---	4097	MOVT_I64 = 1215,	---
4098	MOVF_I64 = 1216,	---	4098	MOVF_I64 = 1216,	---
4099	MOVZ_I64_S = 1217,	---	4099	MOVZ_I64_S = 1217,	---
4100	MOVN_I64_D64 = 1218,	---	4100	MOVN_I64_D64 = 1218,	---
4101	MOVN_I64_S = 1219,	---	4101	MOVN_I64_S = 1219,	---
4102	MOVZ_I64_D64 = 1220,	---	4102	MOVZ_I64_D64 = 1220,	---
4103	SELEQZ_S_SELNEZ_S = 1221,	---	4103	SELEQZ_S_SELNEZ_S = 1221,	---
4104	SELEQZ_D_SELNEZ_D = 1222,	---	4104	SELEQZ_D_SELNEZ_D = 1222,	---
4105	MAX_S_MAXA_S = 1223,	---	4105	MAX_S_MAXA_S = 1223,	---
4106	MAX_D_MAXA_D = 1224,	---	4106	MAX_D_MAXA_D = 1224,	---
4107	MIN_S_MINA_D = 1225,	---	4107	MIN_S_MINA_D = 1225,	---
4108	MIN_D_MINA_S = 1226,	---	4108	MIN_D_MINA_S = 1226,	---
4109	CLASS_S = 1227,	---	4109	CLASS_S = 1227,	---
4110	CLASS_D = 1228,	---	4110	CLASS_D = 1228,	---
4111	RINT_S = 1229,	---	4111	RINT_S = 1229,	---
4112	RINT_D = 1230,	---	4112	RINT_D = 1230,	---
4113	BC1EQZ_BC1NEZ = 1231,	---	4113	BC1EQZ_BC1NEZ = 1231,	---
4114	SEL_D = 1232,	---	4114	SEL_D = 1232,	---
4115	SEL_S = 1233,	---	4115	SEL_S = 1233,	---
4116	MADDF_S = 1234,	---	4116	MADDF_S = 1234,	---
4117	MSUBF_S = 1235,	---	4117	MSUBF_S = 1235,	---
4118	MADDF_D = 1236,	---	4118	MADDF_D = 1236,	---
4119	MSUBF_D = 1237,	---	4119	MSUBF_D = 1237,	---
4120	MOVF_D32_MM = 1238,	---	4120	MOVF_D32_MM = 1238,	---
4121	MOVF_S_MM = 1239,	---	4121	MOVF_S_MM = 1239,	---
4122	MOVN_I_D32_MM = 1240,	---	4122	MOVN_I_D32_MM = 1240,	---
4123	MOVN_I_S_MM = 1241,	---	4123	MOVN_I_S_MM = 1241,	---
4124	MOVT_D32_MM = 1242,	---	4124	MOVT_D32_MM = 1242,	---
4125	MOVT_S_MM = 1243,	---	4125	MOVT_S_MM = 1243,	---
4126	MOVZ_I_D32_MM = 1244,	---	4126	MOVZ_I_D32_MM = 1244,	---
4127	MOVZ_I_S_MM = 1245,	---	4127	MOVZ_I_S_MM = 1245,	---
4128	CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246,	---	4128	CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246,	---
4129	CEIL_W_MM_CEIL_W_S_MM = 1247,	---	4129	CEIL_W_MM_CEIL_W_S_MM = 1247,	---
4130	FLOOR_W_MM_FLOOR_W_S_MM = 1248,	---	4130	FLOOR_W_MM_FLOOR_W_S_MM = 1248,	---
4131	NMADD_S_MM = 1249,	---	4131	NMADD_S_MM = 1249,	---
4132	NMADD_D32_MM = 1250,	---	4132	NMADD_D32_MM = 1250,	---
4133	NMSUB_S_MM = 1251,	---	4133	NMSUB_S_MM = 1251,	---
4134	NMSUB_D32_MM = 1252,	---	4134	NMSUB_D32_MM = 1252,	---
4135	MADD_S_MM = 1253,	---	4135	MADD_S_MM = 1253,	---
4136	MADD_D32_MM = 1254,	---	4136	MADD_D32_MM = 1254,	---
4137	ROUND_W_MM_ROUND_W_S_MM = 1255,	---	4137	ROUND_W_MM_ROUND_W_S_MM = 1255,	---
4138	TRUNC_W_MM_TRUNC_W_S_MM = 1256,	---	4138	TRUNC_W_MM_TRUNC_W_S_MM = 1256,	---
4139	C_F_D32_MM_C_F_D64_MM = 1257,	---	4139	C_F_D32_MM_C_F_D64_MM = 1257,	---
4140	C_F_S_MM = 1258,	---	4140	C_F_S_MM = 1258,	---
4141	C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259,	---	4141	C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259,	---
4142	C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260,	---	4142	C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260,	---
4143	C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261,	---	4143	C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261,	---
4144	C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262,	---	4144	C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262,	---
4145	C_NGLE_D32_MM_C_NGLE_D64_MM = 1263,	---	4145	C_NGLE_D32_MM_C_NGLE_D64_MM = 1263,	---
4146	C_NGLE_S_MM = 1264,	---	4146	C_NGLE_S_MM = 1264,	---
4147	FCMP_S32_MM = 1265,	---	4147	FCMP_S32_MM = 1265,	---
4148	FCMP_D32_MM = 1266,	---	4148	FCMP_D32_MM = 1266,	---
4149	MFC1_MM = 1267,	---	4149	MFC1_MM = 1267,	---
4150	MFHC1_D32_MM_MFHC1_D64_MM = 1268,	---	4150	MFHC1_D32_MM_MFHC1_D64_MM = 1268,	---
4151	MTC1_MM_MTC1_D64_MM = 1269,	---	4151	MTC1_MM_MTC1_D64_MM = 1269,	---
4152	MTHC1_D32_MM_MTHC1_D64_MM = 1270,	---	4152	MTHC1_D32_MM_MTHC1_D64_MM = 1270,	---
4153	FABS_D32_MM_FABS_D64_MM = 1271,	---	4153	FABS_D32_MM_FABS_D64_MM = 1271,	---
4154	FABS_S_MM = 1272,	---	4154	FABS_S_MM = 1272,	---
4155	FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273,	---	4155	FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273,	---
4156	FADD_D32_MM_FADD_D64_MM = 1274,	---	4156	FADD_D32_MM_FADD_D64_MM = 1274,	---
4157	FADD_S_MM = 1275,	---	4157	FADD_S_MM = 1275,	---
4158	FMOV_D32_MM_FMOV_D64_MM = 1276,	---	4158	FMOV_D32_MM_FMOV_D64_MM = 1276,	---
4159	FMOV_S_MM = 1277,	---	4159	FMOV_S_MM = 1277,	---
4160	FMUL_D32_MM_FMUL_D64_MM = 1278,	---	4160	FMUL_D32_MM_FMUL_D64_MM = 1278,	---
4161	FMUL_S_MM = 1279,	---	4161	FMUL_S_MM = 1279,	---
4162	FSUB_D32_MM_FSUB_D64_MM = 1280,	---	4162	FSUB_D32_MM_FSUB_D64_MM = 1280,	---
4163	FSUB_S_MM = 1281,	---	4163	FSUB_S_MM = 1281,	---
4164	MSUB_S_MM = 1282,	---	4164	MSUB_S_MM = 1282,	---
4165	MSUB_D32_MM = 1283,	---	4165	MSUB_D32_MM = 1283,	---
4166	FDIV_S_MM = 1284,	---	4166	FDIV_S_MM = 1284,	---
4167	FDIV_D32_MM_FDIV_D64_MM = 1285,	---	4167	FDIV_D32_MM_FDIV_D64_MM = 1285,	---
4168	FSQRT_S_MM = 1286,	---	4168	FSQRT_S_MM = 1286,	---
4169	FSQRT_D32_MM_FSQRT_D64_MM = 1287,	---	4169	FSQRT_D32_MM_FSQRT_D64_MM = 1287,	---
4170	RECIP_S_MM_RSQRT_S_MM = 1288,	---	4170	RECIP_S_MM_RSQRT_S_MM = 1288,	---
4171	RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289,	---	4171	RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289,	---
4172	SDC1_MM_D32_SDC1_MM_D64 = 1290,	---	4172	SDC1_MM_D32_SDC1_MM_D64 = 1290,	---
4173	SWC1_MM = 1291,	---	4173	SWC1_MM = 1291,	---
4174	SUXC1_MM = 1292,	---	4174	SUXC1_MM = 1292,	---
4175	SWXC1_MM = 1293,	---	4175	SWXC1_MM = 1293,	---
4176	CFC1_MM = 1294,	---	4176	CFC1_MM = 1294,	---
4177	CTC1_MM = 1295,	---	4177	CTC1_MM = 1295,	---
4178	LDC1_MM_D32_LDC1_MM_D64 = 1296,	---	4178	LDC1_MM_D32_LDC1_MM_D64 = 1296,	---
4179	LUXC1_MM = 1297,	---	4179	LUXC1_MM = 1297,	---
4180	LWC1_MM = 1298,	---	4180	LWC1_MM = 1298,	---
4181	LWXC1_MM = 1299,	---	4181	LWXC1_MM = 1299,	---
4182	FNEG_S_MMR6 = 1300,	---	4182	FNEG_S_MMR6 = 1300,	---
4183	CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301,	---	4183	CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301,	---
4184	CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302,	---	4184	CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302,	---
4185	CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303,	---	4185	CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303,	---
4186	CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304,	---	4186	CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304,	---
4187	CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305,	---	4187	CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305,	---
4188	CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306,	---	4188	CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306,	---
4189	CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307,	---	4189	CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307,	---
4190	TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308,	---	4190	TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308,	---
4191	ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309,	---	4191	ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309,	---
4192	FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310,	---	4192	FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310,	---
4193	CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311,	---	4193	CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311,	---
4194	MFC1_MMR6 = 1312,	---	4194	MFC1_MMR6 = 1312,	---
4195	MTC1_MMR6 = 1313,	---	4195	MTC1_MMR6 = 1313,	---
4196	CLASS_S_MMR6_CLASS_D_MMR6 = 1314,	---	4196	CLASS_S_MMR6_CLASS_D_MMR6 = 1314,	---
4197	FADD_S_MMR6 = 1315,	---	4197	FADD_S_MMR6 = 1315,	---
4198	MAX_D_MMR6 = 1316,	---	4198	MAX_D_MMR6 = 1316,	---
4199	MAX_S_MMR6 = 1317,	---	4199	MAX_S_MMR6 = 1317,	---
4200	MIN_D_MMR6 = 1318,	---	4200	MIN_D_MMR6 = 1318,	---
4201	MIN_S_MMR6 = 1319,	---	4201	MIN_S_MMR6 = 1319,	---
4202	MAXA_D_MMR6 = 1320,	---	4202	MAXA_D_MMR6 = 1320,	---
4203	MAXA_S_MMR6 = 1321,	---	4203	MAXA_S_MMR6 = 1321,	---
4204	MINA_D_MMR6 = 1322,	---	4204	MINA_D_MMR6 = 1322,	---
4205	MINA_S_MMR6 = 1323,	---	4205	MINA_S_MMR6 = 1323,	---
4206	SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324,	---	4206	SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324,	---
4207	SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325,	---	4207	SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325,	---
4208	SEL_D_MMR6 = 1326,	---	4208	SEL_D_MMR6 = 1326,	---
4209	SEL_S_MMR6 = 1327,	---	4209	SEL_S_MMR6 = 1327,	---
4210	RINT_S_MMR6_RINT_D_MMR6 = 1328,	---	4210	RINT_S_MMR6_RINT_D_MMR6 = 1328,	---
4211	MADDF_D_MMR6 = 1329,	---	4211	MADDF_D_MMR6 = 1329,	---
4212	MADDF_S_MMR6 = 1330,	---	4212	MADDF_S_MMR6 = 1330,	---
4213	MSUBF_D_MMR6 = 1331,	---	4213	MSUBF_D_MMR6 = 1331,	---
4214	MSUBF_S_MMR6 = 1332,	---	4214	MSUBF_S_MMR6 = 1332,	---
4215	FMOV_S_MMR6 = 1333,	---	4215	FMOV_S_MMR6 = 1333,	---
4216	FMUL_S_MMR6 = 1334,	---	4216	FMUL_S_MMR6 = 1334,	---
4217	FSUB_S_MMR6 = 1335,	---	4217	FSUB_S_MMR6 = 1335,	---
4218	FMOV_D_MMR6 = 1336,	---	4218	FMOV_D_MMR6 = 1336,	---
4219	FDIV_S_MMR6 = 1337,	---	4219	FDIV_S_MMR6 = 1337,	---
4220	SDC1_D64_MMR6 = 1338,	---	4220	SDC1_D64_MMR6 = 1338,	---
4221	LDC1_D64_MMR6 = 1339,	---	4221	LDC1_D64_MMR6 = 1339,	---
4222	DMFC1 = 1340,	---	4222	DMFC1 = 1340,	---
4223	DMTC1 = 1341,	---	4223	DMTC1 = 1341,	---
4224	SWDSP = 1342,	---	4224	SWDSP = 1342,	---
4225	LWDSP = 1343,	---	4225	LWDSP = 1343,	---
4226	PseudoMTLOHI_DSP = 1344,	---	4226	PseudoMTLOHI_DSP = 1344,	---
4227	EXTRV_RS_W = 1345,	---	4227	EXTRV_RS_W = 1345,	---
4228	EXTRV_R_W = 1346,	---	4228	EXTRV_R_W = 1346,	---
4229	EXTRV_S_H = 1347,	---	4229	EXTRV_S_H = 1347,	---
4230	EXTRV_W = 1348,	---	4230	EXTRV_W = 1348,	---
4231	EXTR_RS_W = 1349,	---	4231	EXTR_RS_W = 1349,	---
4232	EXTR_R_W = 1350,	---	4232	EXTR_R_W = 1350,	---
4233	EXTR_S_H = 1351,	---	4233	EXTR_S_H = 1351,	---
4234	EXTR_W = 1352,	---	4234	EXTR_W = 1352,	---
4235	INSV = 1353,	---	4235	INSV = 1353,	---
4236	MTHLIP = 1354,	---	4236	MTHLIP = 1354,	---
4237	MTHI_DSP = 1355,	---	4237	MTHI_DSP = 1355,	---
4238	MTLO_DSP = 1356,	---	4238	MTLO_DSP = 1356,	---
4239	ABSQ_S_PH = 1357,	---	4239	ABSQ_S_PH = 1357,	---
4240	ABSQ_S_W = 1358,	---	4240	ABSQ_S_W = 1358,	---
4241	ADDQ_PH = 1359,	---	4241	ADDQ_PH = 1359,	---
4242	ADDQ_S_PH = 1360,	---	4242	ADDQ_S_PH = 1360,	---
4243	ADDQ_S_W = 1361,	---	4243	ADDQ_S_W = 1361,	---
4244	ADDSC = 1362,	---	4244	ADDSC = 1362,	---
4245	ADDU_QB = 1363,	---	4245	ADDU_QB = 1363,	---
4246	ADDU_S_QB = 1364,	---	4246	ADDU_S_QB = 1364,	---
4247	ADDWC = 1365,	---	4247	ADDWC = 1365,	---
4248	BITREV = 1366,	---	4248	BITREV = 1366,	---
4249	BPOSGE32 = 1367,	---	4249	BPOSGE32 = 1367,	---
4250	CMPGU_EQ_QB = 1368,	---	4250	CMPGU_EQ_QB = 1368,	---
4251	CMPGU_LE_QB = 1369,	---	4251	CMPGU_LE_QB = 1369,	---
4252	CMPGU_LT_QB = 1370,	---	4252	CMPGU_LT_QB = 1370,	---
4253	CMPU_EQ_QB = 1371,	---	4253	CMPU_EQ_QB = 1371,	---
4254	CMPU_LE_QB = 1372,	---	4254	CMPU_LE_QB = 1372,	---
4255	CMPU_LT_QB = 1373,	---	4255	CMPU_LT_QB = 1373,	---
4256	CMP_EQ_PH = 1374,	---	4256	CMP_EQ_PH = 1374,	---
4257	CMP_LE_PH = 1375,	---	4257	CMP_LE_PH = 1375,	---
4258	CMP_LT_PH = 1376,	---	4258	CMP_LT_PH = 1376,	---
4259	DPAQ_SA_L_W = 1377,	---	4259	DPAQ_SA_L_W = 1377,	---
4260	DPAQ_S_W_PH = 1378,	---	4260	DPAQ_S_W_PH = 1378,	---
4261	DPAU_H_QBL = 1379,	---	4261	DPAU_H_QBL = 1379,	---
4262	DPAU_H_QBR = 1380,	---	4262	DPAU_H_QBR = 1380,	---
4263	DPSQ_SA_L_W = 1381,	---	4263	DPSQ_SA_L_W = 1381,	---
4264	DPSQ_S_W_PH = 1382,	---	4264	DPSQ_S_W_PH = 1382,	---
4265	DPSU_H_QBL = 1383,	---	4265	DPSU_H_QBL = 1383,	---
4266	DPSU_H_QBR = 1384,	---	4266	DPSU_H_QBR = 1384,	---
4267	EXTPDPV = 1385,	---	4267	EXTPDPV = 1385,	---
4268	EXTPDP = 1386,	---	4268	EXTPDP = 1386,	---
4269	EXTPV = 1387,	---	4269	EXTPV = 1387,	---
4270	EXTP = 1388,	---	4270	EXTP = 1388,	---
4271	LBUX = 1389,	---	4271	LBUX = 1389,	---
4272	LHX = 1390,	---	4272	LHX = 1390,	---
4273	LWX = 1391,	---	4273	LWX = 1391,	---
4274	MADDU_DSP = 1392,	---	4274	MADDU_DSP = 1392,	---
4275	MADD_DSP = 1393,	---	4275	MADD_DSP = 1393,	---
4276	MAQ_SA_W_PHL = 1394,	---	4276	MAQ_SA_W_PHL = 1394,	---
4277	MAQ_SA_W_PHR = 1395,	---	4277	MAQ_SA_W_PHR = 1395,	---
4278	MAQ_S_W_PHL = 1396,	---	4278	MAQ_S_W_PHL = 1396,	---
4279	MAQ_S_W_PHR = 1397,	---	4279	MAQ_S_W_PHR = 1397,	---
4280	MFHI_DSP = 1398,	---	4280	MFHI_DSP = 1398,	---
4281	MFLO_DSP = 1399,	---	4281	MFLO_DSP = 1399,	---
4282	MODSUB = 1400,	---	4282	MODSUB = 1400,	---
4283	MSUBU_DSP = 1401,	---	4283	MSUBU_DSP = 1401,	---
4284	MSUB_DSP = 1402,	---	4284	MSUB_DSP = 1402,	---
4285	MULEQ_S_W_PHL = 1403,	---	4285	MULEQ_S_W_PHL = 1403,	---
4286	MULEQ_S_W_PHR = 1404,	---	4286	MULEQ_S_W_PHR = 1404,	---
4287	MULEU_S_PH_QBL = 1405,	---	4287	MULEU_S_PH_QBL = 1405,	---
4288	MULEU_S_PH_QBR = 1406,	---	4288	MULEU_S_PH_QBR = 1406,	---
4289	MULQ_RS_PH = 1407,	---	4289	MULQ_RS_PH = 1407,	---
4290	MULSAQ_S_W_PH = 1408,	---	4290	MULSAQ_S_W_PH = 1408,	---
4291	MULTU_DSP = 1409,	---	4291	MULTU_DSP = 1409,	---
4292	MULT_DSP = 1410,	---	4292	MULT_DSP = 1410,	---
4293	PACKRL_PH = 1411,	---	4293	PACKRL_PH = 1411,	---
4294	PICK_PH = 1412,	---	4294	PICK_PH = 1412,	---
4295	PICK_QB = 1413,	---	4295	PICK_QB = 1413,	---
4296	PRECEQU_PH_QBLA = 1414,	---	4296	PRECEQU_PH_QBLA = 1414,	---
4297	PRECEQU_PH_QBL = 1415,	---	4297	PRECEQU_PH_QBL = 1415,	---
4298	PRECEQU_PH_QBRA = 1416,	---	4298	PRECEQU_PH_QBRA = 1416,	---
4299	PRECEQU_PH_QBR = 1417,	---	4299	PRECEQU_PH_QBR = 1417,	---
4300	PRECEQ_W_PHL = 1418,	---	4300	PRECEQ_W_PHL = 1418,	---
4301	PRECEQ_W_PHR = 1419,	---	4301	PRECEQ_W_PHR = 1419,	---
4302	PRECEU_PH_QBLA = 1420,	---	4302	PRECEU_PH_QBLA = 1420,	---
4303	PRECEU_PH_QBL = 1421,	---	4303	PRECEU_PH_QBL = 1421,	---
4304	PRECEU_PH_QBRA = 1422,	---	4304	PRECEU_PH_QBRA = 1422,	---
4305	PRECEU_PH_QBR = 1423,	---	4305	PRECEU_PH_QBR = 1423,	---
4306	PRECRQU_S_QB_PH = 1424,	---	4306	PRECRQU_S_QB_PH = 1424,	---
4307	PRECRQ_PH_W = 1425,	---	4307	PRECRQ_PH_W = 1425,	---
4308	PRECRQ_QB_PH = 1426,	---	4308	PRECRQ_QB_PH = 1426,	---
4309	PRECRQ_RS_PH_W = 1427,	---	4309	PRECRQ_RS_PH_W = 1427,	---
4310	RADDU_W_QB = 1428,	---	4310	RADDU_W_QB = 1428,	---
4311	RDDSP = 1429,	---	4311	RDDSP = 1429,	---
4312	REPLV_PH = 1430,	---	4312	REPLV_PH = 1430,	---
4313	REPLV_QB = 1431,	---	4313	REPLV_QB = 1431,	---
4314	REPL_PH = 1432,	---	4314	REPL_PH = 1432,	---
4315	REPL_QB = 1433,	---	4315	REPL_QB = 1433,	---
4316	SHILOV = 1434,	---	4316	SHILOV = 1434,	---
4317	SHILO = 1435,	---	4317	SHILO = 1435,	---
4318	SHLLV_PH = 1436,	---	4318	SHLLV_PH = 1436,	---
4319	SHLLV_QB = 1437,	---	4319	SHLLV_QB = 1437,	---
4320	SHLLV_S_PH = 1438,	---	4320	SHLLV_S_PH = 1438,	---
4321	SHLLV_S_W = 1439,	---	4321	SHLLV_S_W = 1439,	---
4322	SHLL_PH = 1440,	---	4322	SHLL_PH = 1440,	---
4323	SHLL_QB = 1441,	---	4323	SHLL_QB = 1441,	---
4324	SHLL_S_PH = 1442,	---	4324	SHLL_S_PH = 1442,	---
4325	SHLL_S_W = 1443,	---	4325	SHLL_S_W = 1443,	---
4326	SHRAV_PH = 1444,	---	4326	SHRAV_PH = 1444,	---
4327	SHRAV_R_PH = 1445,	---	4327	SHRAV_R_PH = 1445,	---
4328	SHRAV_R_W = 1446,	---	4328	SHRAV_R_W = 1446,	---
4329	SHRA_PH = 1447,	---	4329	SHRA_PH = 1447,	---
4330	SHRA_R_PH = 1448,	---	4330	SHRA_R_PH = 1448,	---
4331	SHRA_R_W = 1449,	---	4331	SHRA_R_W = 1449,	---
4332	SHRLV_QB = 1450,	---	4332	SHRLV_QB = 1450,	---
4333	SHRL_QB = 1451,	---	4333	SHRL_QB = 1451,	---
4334	SUBQ_PH = 1452,	---	4334	SUBQ_PH = 1452,	---
4335	SUBQ_S_PH = 1453,	---	4335	SUBQ_S_PH = 1453,	---
4336	SUBQ_S_W = 1454,	---	4336	SUBQ_S_W = 1454,	---
4337	SUBU_QB = 1455,	---	4337	SUBU_QB = 1455,	---
4338	SUBU_S_QB = 1456,	---	4338	SUBU_S_QB = 1456,	---
4339	WRDSP = 1457,	---	4339	WRDSP = 1457,	---
4340	PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458,	---	4340	PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458,	---
4341	PseudoPICK_PH_PseudoPICK_QB = 1459,	---	4341	PseudoPICK_PH_PseudoPICK_QB = 1459,	---
4342	ABSQ_S_QB = 1460,	---	4342	ABSQ_S_QB = 1460,	---
4343	ADDQH_PH = 1461,	---	4343	ADDQH_PH = 1461,	---
4344	ADDQH_R_PH = 1462,	---	4344	ADDQH_R_PH = 1462,	---
4345	ADDQH_R_W = 1463,	---	4345	ADDQH_R_W = 1463,	---
4346	ADDQH_W = 1464,	---	4346	ADDQH_W = 1464,	---
4347	ADDUH_QB = 1465,	---	4347	ADDUH_QB = 1465,	---
4348	ADDUH_R_QB = 1466,	---	4348	ADDUH_R_QB = 1466,	---
4349	ADDU_PH = 1467,	---	4349	ADDU_PH = 1467,	---
4350	ADDU_S_PH = 1468,	---	4350	ADDU_S_PH = 1468,	---
4351	APPEND = 1469,	---	4351	APPEND = 1469,	---
4352	BALIGN = 1470,	---	4352	BALIGN = 1470,	---
4353	CMPGDU_EQ_QB = 1471,	---	4353	CMPGDU_EQ_QB = 1471,	---
4354	CMPGDU_LE_QB = 1472,	---	4354	CMPGDU_LE_QB = 1472,	---
4355	CMPGDU_LT_QB = 1473,	---	4355	CMPGDU_LT_QB = 1473,	---
4356	DPA_W_PH = 1474,	---	4356	DPA_W_PH = 1474,	---
4357	DPAQX_SA_W_PH = 1475,	---	4357	DPAQX_SA_W_PH = 1475,	---
4358	DPAQX_S_W_PH = 1476,	---	4358	DPAQX_S_W_PH = 1476,	---
4359	DPAX_W_PH = 1477,	---	4359	DPAX_W_PH = 1477,	---
4360	DPS_W_PH = 1478,	---	4360	DPS_W_PH = 1478,	---
4361	DPSQX_S_W_PH = 1479,	---	4361	DPSQX_S_W_PH = 1479,	---
4362	DPSQX_SA_W_PH = 1480,	---	4362	DPSQX_SA_W_PH = 1480,	---
4363	DPSX_W_PH = 1481,	---	4363	DPSX_W_PH = 1481,	---
4364	MUL_PH = 1482,	---	4364	MUL_PH = 1482,	---
4365	MUL_S_PH = 1483,	---	4365	MUL_S_PH = 1483,	---
4366	MULQ_RS_W = 1484,	---	4366	MULQ_RS_W = 1484,	---
4367	MULQ_S_PH = 1485,	---	4367	MULQ_S_PH = 1485,	---
4368	MULQ_S_W = 1486,	---	4368	MULQ_S_W = 1486,	---
4369	MULSA_W_PH = 1487,	---	4369	MULSA_W_PH = 1487,	---
4370	PRECR_QB_PH = 1488,	---	4370	PRECR_QB_PH = 1488,	---
4371	PRECR_SRA_PH_W = 1489,	---	4371	PRECR_SRA_PH_W = 1489,	---
4372	PRECR_SRA_R_PH_W = 1490,	---	4372	PRECR_SRA_R_PH_W = 1490,	---
4373	PREPEND = 1491,	---	4373	PREPEND = 1491,	---
4374	SHRA_QB = 1492,	---	4374	SHRA_QB = 1492,	---
4375	SHRA_R_QB = 1493,	---	4375	SHRA_R_QB = 1493,	---
4376	SHRAV_QB = 1494,	---	4376	SHRAV_QB = 1494,	---
4377	SHRAV_R_QB = 1495,	---	4377	SHRAV_R_QB = 1495,	---
4378	SHRL_PH = 1496,	---	4378	SHRL_PH = 1496,	---
4379	SHRLV_PH = 1497,	---	4379	SHRLV_PH = 1497,	---
4380	SUBQH_PH = 1498,	---	4380	SUBQH_PH = 1498,	---
4381	SUBQH_R_PH = 1499,	---	4381	SUBQH_R_PH = 1499,	---
4382	SUBQH_W = 1500,	---	4382	SUBQH_W = 1500,	---
4383	SUBQH_R_W = 1501,	---	4383	SUBQH_R_W = 1501,	---
4384	SUBU_PH = 1502,	---	4384	SUBU_PH = 1502,	---
4385	SUBU_S_PH = 1503,	---	4385	SUBU_S_PH = 1503,	---
4386	SUBUH_QB = 1504,	---	4386	SUBUH_QB = 1504,	---
4387	SUBUH_R_QB = 1505,	---	4387	SUBUH_R_QB = 1505,	---
4388	LWDSP_MM = 1506,	---	4388	LWDSP_MM = 1506,	---
4389	SWDSP_MM = 1507,	---	4389	SWDSP_MM = 1507,	---
4390	ABSQ_S_PH_MM = 1508,	---	4390	ABSQ_S_PH_MM = 1508,	---
4391	ABSQ_S_W_MM = 1509,	---	4391	ABSQ_S_W_MM = 1509,	---
4392	ADDQ_PH_MM = 1510,	---	4392	ADDQ_PH_MM = 1510,	---
4393	ADDQ_S_PH_MM = 1511,	---	4393	ADDQ_S_PH_MM = 1511,	---
4394	ADDQ_S_W_MM = 1512,	---	4394	ADDQ_S_W_MM = 1512,	---
4395	ADDSC_MM = 1513,	---	4395	ADDSC_MM = 1513,	---
4396	ADDU_QB_MM = 1514,	---	4396	ADDU_QB_MM = 1514,	---
4397	ADDU_S_QB_MM = 1515,	---	4397	ADDU_S_QB_MM = 1515,	---
4398	ADDWC_MM = 1516,	---	4398	ADDWC_MM = 1516,	---
4399	BITREV_MM = 1517,	---	4399	BITREV_MM = 1517,	---
4400	BPOSGE32_MM = 1518,	---	4400	BPOSGE32_MM = 1518,	---
4401	CMPGU_EQ_QB_MM = 1519,	---	4401	CMPGU_EQ_QB_MM = 1519,	---
4402	CMPGU_LE_QB_MM = 1520,	---	4402	CMPGU_LE_QB_MM = 1520,	---
4403	CMPGU_LT_QB_MM = 1521,	---	4403	CMPGU_LT_QB_MM = 1521,	---
4404	CMPU_EQ_QB_MM = 1522,	---	4404	CMPU_EQ_QB_MM = 1522,	---
4405	CMPU_LE_QB_MM = 1523,	---	4405	CMPU_LE_QB_MM = 1523,	---
4406	CMPU_LT_QB_MM = 1524,	---	4406	CMPU_LT_QB_MM = 1524,	---
4407	CMP_EQ_PH_MM = 1525,	---	4407	CMP_EQ_PH_MM = 1525,	---
4408	CMP_LE_PH_MM = 1526,	---	4408	CMP_LE_PH_MM = 1526,	---
4409	CMP_LT_PH_MM = 1527,	---	4409	CMP_LT_PH_MM = 1527,	---
4410	DPAQ_SA_L_W_MM = 1528,	---	4410	DPAQ_SA_L_W_MM = 1528,	---
4411	DPAQ_S_W_PH_MM = 1529,	---	4411	DPAQ_S_W_PH_MM = 1529,	---
4412	DPAU_H_QBL_MM = 1530,	---	4412	DPAU_H_QBL_MM = 1530,	---
4413	DPAU_H_QBR_MM = 1531,	---	4413	DPAU_H_QBR_MM = 1531,	---
4414	DPSQ_SA_L_W_MM = 1532,	---	4414	DPSQ_SA_L_W_MM = 1532,	---
4415	DPSQ_S_W_PH_MM = 1533,	---	4415	DPSQ_S_W_PH_MM = 1533,	---
4416	DPSU_H_QBL_MM = 1534,	---	4416	DPSU_H_QBL_MM = 1534,	---
4417	DPSU_H_QBR_MM = 1535,	---	4417	DPSU_H_QBR_MM = 1535,	---
4418	EXTPDPV_MM = 1536,	---	4418	EXTPDPV_MM = 1536,	---
4419	EXTPDP_MM = 1537,	---	4419	EXTPDP_MM = 1537,	---
4420	EXTPV_MM = 1538,	---	4420	EXTPV_MM = 1538,	---
4421	EXTP_MM = 1539,	---	4421	EXTP_MM = 1539,	---
4422	EXTRV_RS_W_MM = 1540,	---	4422	EXTRV_RS_W_MM = 1540,	---
4423	EXTRV_R_W_MM = 1541,	---	4423	EXTRV_R_W_MM = 1541,	---
4424	EXTRV_S_H_MM = 1542,	---	4424	EXTRV_S_H_MM = 1542,	---
4425	EXTRV_W_MM = 1543,	---	4425	EXTRV_W_MM = 1543,	---
4426	EXTR_RS_W_MM = 1544,	---	4426	EXTR_RS_W_MM = 1544,	---
4427	EXTR_R_W_MM = 1545,	---	4427	EXTR_R_W_MM = 1545,	---
4428	EXTR_S_H_MM = 1546,	---	4428	EXTR_S_H_MM = 1546,	---
4429	EXTR_W_MM = 1547,	---	4429	EXTR_W_MM = 1547,	---
4430	INSV_MM = 1548,	---	4430	INSV_MM = 1548,	---
4431	LBUX_MM = 1549,	---	4431	LBUX_MM = 1549,	---
4432	LHX_MM = 1550,	---	4432	LHX_MM = 1550,	---
4433	LWX_MM = 1551,	---	4433	LWX_MM = 1551,	---
4434	MADDU_DSP_MM = 1552,	---	4434	MADDU_DSP_MM = 1552,	---
4435	MADD_DSP_MM = 1553,	---	4435	MADD_DSP_MM = 1553,	---
4436	MAQ_SA_W_PHL_MM = 1554,	---	4436	MAQ_SA_W_PHL_MM = 1554,	---
4437	MAQ_SA_W_PHR_MM = 1555,	---	4437	MAQ_SA_W_PHR_MM = 1555,	---
4438	MAQ_S_W_PHL_MM = 1556,	---	4438	MAQ_S_W_PHL_MM = 1556,	---
4439	MAQ_S_W_PHR_MM = 1557,	---	4439	MAQ_S_W_PHR_MM = 1557,	---
4440	MFHI_DSP_MM = 1558,	---	4440	MFHI_DSP_MM = 1558,	---
4441	MFLO_DSP_MM = 1559,	---	4441	MFLO_DSP_MM = 1559,	---
4442	MODSUB_MM = 1560,	---	4442	MODSUB_MM = 1560,	---
4443	MOVEP_MMR6 = 1561,	---	4443	MOVEP_MMR6 = 1561,	---
4444	MOVN_I_MM = 1562,	---	4444	MOVN_I_MM = 1562,	---
4445	MOVZ_I_MM = 1563,	---	4445	MOVZ_I_MM = 1563,	---
4446	MSUBU_DSP_MM = 1564,	---	4446	MSUBU_DSP_MM = 1564,	---
4447	MSUB_DSP_MM = 1565,	---	4447	MSUB_DSP_MM = 1565,	---
4448	MTHI_DSP_MM = 1566,	---	4448	MTHI_DSP_MM = 1566,	---
4449	MTHLIP_MM = 1567,	---	4449	MTHLIP_MM = 1567,	---
4450	MTLO_DSP_MM = 1568,	---	4450	MTLO_DSP_MM = 1568,	---
4451	MULEQ_S_W_PHL_MM = 1569,	---	4451	MULEQ_S_W_PHL_MM = 1569,	---
4452	MULEQ_S_W_PHR_MM = 1570,	---	4452	MULEQ_S_W_PHR_MM = 1570,	---
4453	MULEU_S_PH_QBL_MM = 1571,	---	4453	MULEU_S_PH_QBL_MM = 1571,	---
4454	MULEU_S_PH_QBR_MM = 1572,	---	4454	MULEU_S_PH_QBR_MM = 1572,	---
4455	MULQ_RS_PH_MM = 1573,	---	4455	MULQ_RS_PH_MM = 1573,	---
4456	MULSAQ_S_W_PH_MM = 1574,	---	4456	MULSAQ_S_W_PH_MM = 1574,	---
4457	MULTU_DSP_MM = 1575,	---	4457	MULTU_DSP_MM = 1575,	---
4458	MULT_DSP_MM = 1576,	---	4458	MULT_DSP_MM = 1576,	---
4459	PACKRL_PH_MM = 1577,	---	4459	PACKRL_PH_MM = 1577,	---
4460	PICK_PH_MM = 1578,	---	4460	PICK_PH_MM = 1578,	---
4461	PICK_QB_MM = 1579,	---	4461	PICK_QB_MM = 1579,	---
4462	PRECEQU_PH_QBLA_MM = 1580,	---	4462	PRECEQU_PH_QBLA_MM = 1580,	---
4463	PRECEQU_PH_QBL_MM = 1581,	---	4463	PRECEQU_PH_QBL_MM = 1581,	---
4464	PRECEQU_PH_QBRA_MM = 1582,	---	4464	PRECEQU_PH_QBRA_MM = 1582,	---
4465	PRECEQU_PH_QBR_MM = 1583,	---	4465	PRECEQU_PH_QBR_MM = 1583,	---
4466	PRECEQ_W_PHL_MM = 1584,	---	4466	PRECEQ_W_PHL_MM = 1584,	---
4467	PRECEQ_W_PHR_MM = 1585,	---	4467	PRECEQ_W_PHR_MM = 1585,	---
4468	PRECEU_PH_QBLA_MM = 1586,	---	4468	PRECEU_PH_QBLA_MM = 1586,	---
4469	PRECEU_PH_QBL_MM = 1587,	---	4469	PRECEU_PH_QBL_MM = 1587,	---
4470	PRECEU_PH_QBRA_MM = 1588,	---	4470	PRECEU_PH_QBRA_MM = 1588,	---
4471	PRECEU_PH_QBR_MM = 1589,	---	4471	PRECEU_PH_QBR_MM = 1589,	---
4472	PRECRQU_S_QB_PH_MM = 1590,	---	4472	PRECRQU_S_QB_PH_MM = 1590,	---
4473	PRECRQ_PH_W_MM = 1591,	---	4473	PRECRQ_PH_W_MM = 1591,	---
4474	PRECRQ_QB_PH_MM = 1592,	---	4474	PRECRQ_QB_PH_MM = 1592,	---
4475	PRECRQ_RS_PH_W_MM = 1593,	---	4475	PRECRQ_RS_PH_W_MM = 1593,	---
4476	RADDU_W_QB_MM = 1594,	---	4476	RADDU_W_QB_MM = 1594,	---
4477	RDDSP_MM = 1595,	---	4477	RDDSP_MM = 1595,	---
4478	REPLV_PH_MM = 1596,	---	4478	REPLV_PH_MM = 1596,	---
4479	REPLV_QB_MM = 1597,	---	4479	REPLV_QB_MM = 1597,	---
4480	REPL_PH_MM = 1598,	---	4480	REPL_PH_MM = 1598,	---
4481	REPL_QB_MM = 1599,	---	4481	REPL_QB_MM = 1599,	---
4482	SHILOV_MM = 1600,	---	4482	SHILOV_MM = 1600,	---
4483	SHILO_MM = 1601,	---	4483	SHILO_MM = 1601,	---
4484	SHLLV_PH_MM = 1602,	---	4484	SHLLV_PH_MM = 1602,	---
4485	SHLLV_QB_MM = 1603,	---	4485	SHLLV_QB_MM = 1603,	---
4486	SHLLV_S_PH_MM = 1604,	---	4486	SHLLV_S_PH_MM = 1604,	---
4487	SHLLV_S_W_MM = 1605,	---	4487	SHLLV_S_W_MM = 1605,	---
4488	SHLL_PH_MM = 1606,	---	4488	SHLL_PH_MM = 1606,	---
4489	SHLL_QB_MM = 1607,	---	4489	SHLL_QB_MM = 1607,	---
4490	SHLL_S_PH_MM = 1608,	---	4490	SHLL_S_PH_MM = 1608,	---
4491	SHLL_S_W_MM = 1609,	---	4491	SHLL_S_W_MM = 1609,	---
4492	SHRAV_PH_MM = 1610,	---	4492	SHRAV_PH_MM = 1610,	---
4493	SHRAV_R_PH_MM = 1611,	---	4493	SHRAV_R_PH_MM = 1611,	---
4494	SHRAV_R_W_MM = 1612,	---	4494	SHRAV_R_W_MM = 1612,	---
4495	SHRA_PH_MM = 1613,	---	4495	SHRA_PH_MM = 1613,	---
4496	SHRA_R_PH_MM = 1614,	---	4496	SHRA_R_PH_MM = 1614,	---
4497	SHRA_R_W_MM = 1615,	---	4497	SHRA_R_W_MM = 1615,	---
4498	SHRLV_QB_MM = 1616,	---	4498	SHRLV_QB_MM = 1616,	---
4499	SHRL_QB_MM = 1617,	---	4499	SHRL_QB_MM = 1617,	---
4500	SUBQ_PH_MM = 1618,	---	4500	SUBQ_PH_MM = 1618,	---
4501	SUBQ_S_PH_MM = 1619,	---	4501	SUBQ_S_PH_MM = 1619,	---
4502	SUBQ_S_W_MM = 1620,	---	4502	SUBQ_S_W_MM = 1620,	---
4503	SUBU_QB_MM = 1621,	---	4503	SUBU_QB_MM = 1621,	---
4504	SUBU_S_QB_MM = 1622,	---	4504	SUBU_S_QB_MM = 1622,	---
4505	WRDSP_MM = 1623,	---	4505	WRDSP_MM = 1623,	---
4506	ABSQ_S_QB_MMR2 = 1624,	---	4506	ABSQ_S_QB_MMR2 = 1624,	---
4507	ADDQH_PH_MMR2 = 1625,	---	4507	ADDQH_PH_MMR2 = 1625,	---
4508	ADDQH_R_PH_MMR2 = 1626,	---	4508	ADDQH_R_PH_MMR2 = 1626,	---
4509	ADDQH_R_W_MMR2 = 1627,	---	4509	ADDQH_R_W_MMR2 = 1627,	---
4510	ADDQH_W_MMR2 = 1628,	---	4510	ADDQH_W_MMR2 = 1628,	---
4511	ADDUH_QB_MMR2 = 1629,	---	4511	ADDUH_QB_MMR2 = 1629,	---
4512	ADDUH_R_QB_MMR2 = 1630,	---	4512	ADDUH_R_QB_MMR2 = 1630,	---
4513	ADDU_PH_MMR2 = 1631,	---	4513	ADDU_PH_MMR2 = 1631,	---
4514	ADDU_S_PH_MMR2 = 1632,	---	4514	ADDU_S_PH_MMR2 = 1632,	---
4515	APPEND_MMR2 = 1633,	---	4515	APPEND_MMR2 = 1633,	---
4516	BALIGN_MMR2 = 1634,	---	4516	BALIGN_MMR2 = 1634,	---
4517	CMPGDU_EQ_QB_MMR2 = 1635,	---	4517	CMPGDU_EQ_QB_MMR2 = 1635,	---
4518	CMPGDU_LE_QB_MMR2 = 1636,	---	4518	CMPGDU_LE_QB_MMR2 = 1636,	---
4519	CMPGDU_LT_QB_MMR2 = 1637,	---	4519	CMPGDU_LT_QB_MMR2 = 1637,	---
4520	DPA_W_PH_MMR2 = 1638,	---	4520	DPA_W_PH_MMR2 = 1638,	---
4521	DPAQX_SA_W_PH_MMR2 = 1639,	---	4521	DPAQX_SA_W_PH_MMR2 = 1639,	---
4522	DPAQX_S_W_PH_MMR2 = 1640,	---	4522	DPAQX_S_W_PH_MMR2 = 1640,	---
4523	DPAX_W_PH_MMR2 = 1641,	---	4523	DPAX_W_PH_MMR2 = 1641,	---
4524	DPS_W_PH_MMR2 = 1642,	---	4524	DPS_W_PH_MMR2 = 1642,	---
4525	DPSQX_S_W_PH_MMR2 = 1643,	---	4525	DPSQX_S_W_PH_MMR2 = 1643,	---
4526	DPSQX_SA_W_PH_MMR2 = 1644,	---	4526	DPSQX_SA_W_PH_MMR2 = 1644,	---
4527	DPSX_W_PH_MMR2 = 1645,	---	4527	DPSX_W_PH_MMR2 = 1645,	---
4528	MUL_PH_MMR2 = 1646,	---	4528	MUL_PH_MMR2 = 1646,	---
4529	MUL_S_PH_MMR2 = 1647,	---	4529	MUL_S_PH_MMR2 = 1647,	---
4530	MULQ_RS_W_MMR2 = 1648,	---	4530	MULQ_RS_W_MMR2 = 1648,	---
4531	MULQ_S_PH_MMR2 = 1649,	---	4531	MULQ_S_PH_MMR2 = 1649,	---
4532	MULQ_S_W_MMR2 = 1650,	---	4532	MULQ_S_W_MMR2 = 1650,	---
4533	MULSA_W_PH_MMR2 = 1651,	---	4533	MULSA_W_PH_MMR2 = 1651,	---
4534	PRECR_QB_PH_MMR2 = 1652,	---	4534	PRECR_QB_PH_MMR2 = 1652,	---
4535	PRECR_SRA_PH_W_MMR2 = 1653,	---	4535	PRECR_SRA_PH_W_MMR2 = 1653,	---
4536	PRECR_SRA_R_PH_W_MMR2 = 1654,	---	4536	PRECR_SRA_R_PH_W_MMR2 = 1654,	---
4537	PREPEND_MMR2 = 1655,	---	4537	PREPEND_MMR2 = 1655,	---
4538	SHRA_QB_MMR2 = 1656,	---	4538	SHRA_QB_MMR2 = 1656,	---
4539	SHRA_R_QB_MMR2 = 1657,	---	4539	SHRA_R_QB_MMR2 = 1657,	---
4540	SHRAV_QB_MMR2 = 1658,	---	4540	SHRAV_QB_MMR2 = 1658,	---
4541	SHRAV_R_QB_MMR2 = 1659,	---	4541	SHRAV_R_QB_MMR2 = 1659,	---
4542	SHRL_PH_MMR2 = 1660,	---	4542	SHRL_PH_MMR2 = 1660,	---
4543	SHRLV_PH_MMR2 = 1661,	---	4543	SHRLV_PH_MMR2 = 1661,	---
4544	SUBQH_PH_MMR2 = 1662,	---	4544	SUBQH_PH_MMR2 = 1662,	---
4545	SUBQH_R_PH_MMR2 = 1663,	---	4545	SUBQH_R_PH_MMR2 = 1663,	---
4546	SUBQH_W_MMR2 = 1664,	---	4546	SUBQH_W_MMR2 = 1664,	---
4547	SUBQH_R_W_MMR2 = 1665,	---	4547	SUBQH_R_W_MMR2 = 1665,	---
4548	SUBU_PH_MMR2 = 1666,	---	4548	SUBU_PH_MMR2 = 1666,	---
4549	SUBU_S_PH_MMR2 = 1667,	---	4549	SUBU_S_PH_MMR2 = 1667,	---
4550	SUBUH_QB_MMR2 = 1668,	---	4550	SUBUH_QB_MMR2 = 1668,	---
4551	SUBUH_R_QB_MMR2 = 1669,	---	4551	SUBUH_R_QB_MMR2 = 1669,	---
4552	BPOSGE32C_MMR3 = 1670,	---	4552	BPOSGE32C_MMR3 = 1670,	---
4553	CMP_F_D = 1671,	---	4553	CMP_F_D = 1671,	---
4554	CMP_F_S = 1672,	---	4554	CMP_F_S = 1672,	---
4555	CMP_SAF_D = 1673,	---	4555	CMP_SAF_D = 1673,	---
4556	CMP_SAF_S = 1674,	---	4556	CMP_SAF_S = 1674,	---
4557	CMP_SEQ_D = 1675,	---	4557	CMP_SEQ_D = 1675,	---
4558	CMP_SEQ_S = 1676,	---	4558	CMP_SEQ_S = 1676,	---
4559	CMP_SLE_D = 1677,	---	4559	CMP_SLE_D = 1677,	---
4560	CMP_SLE_S = 1678,	---	4560	CMP_SLE_S = 1678,	---
4561	CMP_SLT_D = 1679,	---	4561	CMP_SLT_D = 1679,	---
4562	CMP_SLT_S = 1680,	---	4562	CMP_SLT_S = 1680,	---
4563	CMP_SUEQ_D = 1681,	---	4563	CMP_SUEQ_D = 1681,	---
4564	CMP_SUEQ_S = 1682,	---	4564	CMP_SUEQ_S = 1682,	---
4565	CMP_SULE_D = 1683,	---	4565	CMP_SULE_D = 1683,	---
4566	CMP_SULE_S = 1684,	---	4566	CMP_SULE_S = 1684,	---
4567	CMP_SULT_D = 1685,	---	4567	CMP_SULT_D = 1685,	---
4568	CMP_SULT_S = 1686,	---	4568	CMP_SULT_S = 1686,	---
4569	CMP_SUN_D = 1687,	---	4569	CMP_SUN_D = 1687,	---
4570	CMP_SUN_S = 1688,	---	4570	CMP_SUN_S = 1688,	---
4571	SCHED_LIST_END = 1689	---	4571	SCHED_LIST_END = 1689	---
4572	};	---	4572	};	---
4573	} // end namespace Sched	---	4573	} // end namespace Sched	---
4574	} // end namespace Mips	---	4574	} // end namespace Mips	---
4575	} // end namespace llvm	---	4575	} // end namespace llvm	---
4576	#endif // GET_INSTRINFO_SCHED_ENUM	---	4576	#endif // GET_INSTRINFO_SCHED_ENUM	---
4577		---	4577		---
4578	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	---	4578	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	---
4579	namespace llvm {	---	4579	namespace llvm {	---
4580		---	4580		---
4581	struct MipsInstrTable {	---	4581	struct MipsInstrTable {	---
4582	MCInstrDesc Insts[2853];	---	4582	MCInstrDesc Insts[2853];	---
4583	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");	---	4583	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");	---
4584	MCOperandInfo OperandInfo[1126];	---	4584	MCOperandInfo OperandInfo[1126];	---
4585	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");	---	4585	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");	---
4586	MCPhysReg ImplicitOps[67];	---	4586	MCPhysReg ImplicitOps[67];	---
4587	};	---	4587	};	---
4588		---	4588		---
4589	} // end namespace llvm	---	4589	} // end namespace llvm	---
4590	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	---	4590	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)	---
4591		---	4591		---
4592	#ifdef GET_INSTRINFO_MC_DESC	---	4592	#ifdef GET_INSTRINFO_MC_DESC	---
4593	#undef GET_INSTRINFO_MC_DESC	---	4593	#undef GET_INSTRINFO_MC_DESC	---
4594	namespace llvm {	---	4594	namespace llvm {	---
4595		---	4595		---
4596	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);	---	4596	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);	---
4597	static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));	---	4597	static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));	---
4598		---	4598		---
4599	extern const MipsInstrTable MipsDescs = {	---	4599	extern const MipsInstrTable MipsDescs = {	---
4600	{	---	4600	{	---
4601	{ 2852, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	4601	{ 2852, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
4602	{ 2851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---	4602	{ 2851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---
4603	{ 2850, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4603	{ 2850, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4604	{ 2849, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	4604	{ 2849, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
4605	{ 2848, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4605	{ 2848, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4606	{ 2847, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2847 = XOR_V	---	4606	{ 2847, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2847 = XOR_V	---
4607	{ 2846, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4607	{ 2846, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4608	{ 2845, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4608	{ 2845, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4609	{ 2844, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4609	{ 2844, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4610	{ 2843, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2843 = XORI_B	---	4610	{ 2843, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2843 = XORI_B	---
4611	{ 2842, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	4611	{ 2842, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
4612	{ 2841, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	4612	{ 2841, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
4613	{ 2840, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	4613	{ 2840, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
4614	{ 2839, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4614	{ 2839, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4615	{ 2838, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2838 = WSBH_MMR6	---	4615	{ 2838, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2838 = WSBH_MMR6	---
4616	{ 2837, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2837 = WSBH_MM	---	4616	{ 2837, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2837 = WSBH_MM	---
4617	{ 2836, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2836 = WSBH	---	4617	{ 2836, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2836 = WSBH	---
4618	{ 2835, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2835 = WRPGPR_MMR6	---	4618	{ 2835, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #2835 = WRPGPR_MMR6	---
4619	{ 2834, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4619	{ 2834, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4620	{ 2833, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4620	{ 2833, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4621	{ 2832, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4621	{ 2832, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4622	{ 2831, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4622	{ 2831, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4623	{ 2830, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4623	{ 2830, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4624	{ 2829, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2829 = VSHF_W	---	4624	{ 2829, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2829 = VSHF_W	---
4625	{ 2828, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2828 = VSHF_H	---	4625	{ 2828, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2828 = VSHF_H	---
4626	{ 2827, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2827 = VSHF_D	---	4626	{ 2827, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2827 = VSHF_D	---
4627	{ 2826, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2826 = VSHF_B	---	4627	{ 2826, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2826 = VSHF_B	---
4628	{ 2825, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 219, 0\|(1ULL<	---	4628	{ 2825, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 219, 0\|(1ULL<	---
4629	{ 2824, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 219, 0\|(1ULL<	---	4629	{ 2824, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 219, 0\|(1ULL<	---
4630	{ 2823, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 219, 0\|(1ULL<	---	4630	{ 2823, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 219, 0\|(1ULL<	---
4631	{ 2822, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	4631	{ 2822, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
4632	{ 2821, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	4632	{ 2821, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
4633	{ 2820, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4633	{ 2820, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4634	{ 2819, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2819 = TRUNC_W_S_MMR6	---	4634	{ 2819, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2819 = TRUNC_W_S_MMR6	---
4635	{ 2818, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2818 = TRUNC_W_S_MM	---	4635	{ 2818, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2818 = TRUNC_W_S_MM	---
4636	{ 2817, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2817 = TRUNC_W_S	---	4636	{ 2817, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2817 = TRUNC_W_S	---
4637	{ 2816, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2816 = TRUNC_W_MM	---	4637	{ 2816, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2816 = TRUNC_W_MM	---
4638	{ 2815, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2815 = TRUNC_W_D_MMR6	---	4638	{ 2815, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2815 = TRUNC_W_D_MMR6	---
4639	{ 2814, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2814 = TRUNC_W_D64	---	4639	{ 2814, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2814 = TRUNC_W_D64	---
4640	{ 2813, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2813 = TRUNC_W_D32	---	4640	{ 2813, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2813 = TRUNC_W_D32	---
4641	{ 2812, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2812 = TRUNC_L_S_MMR6	---	4641	{ 2812, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2812 = TRUNC_L_S_MMR6	---
4642	{ 2811, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2811 = TRUNC_L_S	---	4642	{ 2811, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2811 = TRUNC_L_S	---
4643	{ 2810, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2810 = TRUNC_L_D_MMR6	---	4643	{ 2810, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2810 = TRUNC_L_D_MMR6	---
4644	{ 2809, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2809 = TRUNC_L_D64	---	4644	{ 2809, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2809 = TRUNC_L_D64	---
4645	{ 2808, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4645	{ 2808, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4646	{ 2807, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4646	{ 2807, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4647	{ 2806, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4647	{ 2806, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4648	{ 2805, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4648	{ 2805, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4649	{ 2804, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4649	{ 2804, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4650	{ 2803, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4650	{ 2803, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4651	{ 2802, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4651	{ 2802, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4652	{ 2801, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4652	{ 2801, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4653	{ 2800, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4653	{ 2800, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4654	{ 2799, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4654	{ 2799, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4655	{ 2798, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4655	{ 2798, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4656	{ 2797, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4656	{ 2797, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4657	{ 2796, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4657	{ 2796, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4658	{ 2795, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4658	{ 2795, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4659	{ 2794, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4659	{ 2794, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4660	{ 2793, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4660	{ 2793, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4661	{ 2792, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4661	{ 2792, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4662	{ 2791, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4662	{ 2791, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4663	{ 2790, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4663	{ 2790, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4664	{ 2789, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4664	{ 2789, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4665	{ 2788, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4665	{ 2788, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4666	{ 2787, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4666	{ 2787, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4667	{ 2786, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4667	{ 2786, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4668	{ 2785, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4668	{ 2785, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4669	{ 2784, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4669	{ 2784, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4670	{ 2783, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4670	{ 2783, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4671	{ 2782, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4671	{ 2782, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4672	{ 2781, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4672	{ 2781, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4673	{ 2780, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4673	{ 2780, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4674	{ 2779, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4674	{ 2779, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4675	{ 2778, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4675	{ 2778, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4676	{ 2777, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4676	{ 2777, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4677	{ 2776, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4677	{ 2776, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4678	{ 2775, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4678	{ 2775, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4679	{ 2774, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4679	{ 2774, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4680	{ 2773, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4680	{ 2773, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4681	{ 2772, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4681	{ 2772, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4682	{ 2771, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4682	{ 2771, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4683	{ 2770, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4683	{ 2770, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4684	{ 2769, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4684	{ 2769, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4685	{ 2768, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4685	{ 2768, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4686	{ 2767, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4686	{ 2767, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4687	{ 2766, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4687	{ 2766, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4688	{ 2765, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4688	{ 2765, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4689	{ 2764, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4689	{ 2764, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4690	{ 2763, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	4690	{ 2763, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
4691	{ 2762, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4691	{ 2762, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4692	{ 2761, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	---	4692	{ 2761, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	---
4693	{ 2760, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	4693	{ 2760, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
4694	{ 2759, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---	4694	{ 2759, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---
4695	{ 2758, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2758 = SrlvRxRy16	---	4695	{ 2758, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2758 = SrlvRxRy16	---
4696	{ 2757, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2757 = SrlX16	---	4696	{ 2757, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2757 = SrlX16	---
4697	{ 2756, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2756 = SravRxRy16	---	4697	{ 2756, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2756 = SravRxRy16	---
4698	{ 2755, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2755 = SraX16	---	4698	{ 2755, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2755 = SraX16	---
4699	{ 2754, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---	4699	{ 2754, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---
4700	{ 2753, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	4700	{ 2753, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
4701	{ 2752, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	4701	{ 2752, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
4702	{ 2751, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	4702	{ 2751, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
4703	{ 2750, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	4703	{ 2750, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
4704	{ 2749, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---	4704	{ 2749, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---
4705	{ 2748, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2748 = SllvRxRy16	---	4705	{ 2748, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0, 0x0ULL }, // Inst #2748 = SllvRxRy16	---
4706	{ 2747, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2747 = SllX16	---	4706	{ 2747, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 516, 0, 0x0ULL }, // Inst #2747 = SllX16	---
4707	{ 2746, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	4707	{ 2746, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
4708	{ 2745, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2745 = SehRx16	---	4708	{ 2745, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2745 = SehRx16	---
4709	{ 2744, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2744 = SebRx16	---	4709	{ 2744, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1124, 0, 0x0ULL }, // Inst #2744 = SebRx16	---
4710	{ 2743, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	4710	{ 2743, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
4711	{ 2742, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4711	{ 2742, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4712	{ 2741, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4712	{ 2741, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4713	{ 2740, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4713	{ 2740, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4714	{ 2739, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4714	{ 2739, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4715	{ 2738, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4715	{ 2738, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4716	{ 2737, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4716	{ 2737, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4717	{ 2736, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---	4717	{ 2736, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---
4718	{ 2735, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---	4718	{ 2735, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---
4719	{ 2734, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---	4719	{ 2734, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1122, 0\|(1ULL<	---
4720	{ 2733, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4720	{ 2733, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4721	{ 2732, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4721	{ 2732, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4722	{ 2731, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4722	{ 2731, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4723	{ 2730, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---	4723	{ 2730, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---
4724	{ 2729, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---	4724	{ 2729, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---
4725	{ 2728, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---	4725	{ 2728, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---
4726	{ 2727, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---	4726	{ 2727, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---
4727	{ 2726, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4727	{ 2726, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4728	{ 2725, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4728	{ 2725, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4729	{ 2724, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4729	{ 2724, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4730	{ 2723, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	4730	{ 2723, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
4731	{ 2722, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4731	{ 2722, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4732	{ 2721, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	---	4732	{ 2721, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	---
4733	{ 2720, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---	4733	{ 2720, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---
4734	{ 2719, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---	4734	{ 2719, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---
4735	{ 2718, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---	4735	{ 2718, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---
4736	{ 2717, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4736	{ 2717, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4737	{ 2716, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4737	{ 2716, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4738	{ 2715, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4738	{ 2715, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4739	{ 2714, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	4739	{ 2714, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
4740	{ 2713, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4740	{ 2713, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4741	{ 2712, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4741	{ 2712, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4742	{ 2711, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4742	{ 2711, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4743	{ 2710, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---	4743	{ 2710, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---
4744	{ 2709, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---	4744	{ 2709, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---
4745	{ 2708, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---	4745	{ 2708, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---
4746	{ 2707, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	4746	{ 2707, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
4747	{ 2706, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---	4747	{ 2706, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---
4748	{ 2705, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	4748	{ 2705, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
4749	{ 2704, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---	4749	{ 2704, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---
4750	{ 2703, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---	4750	{ 2703, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---
4751	{ 2702, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	4751	{ 2702, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
4752	{ 2701, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	4752	{ 2701, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
4753	{ 2700, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	4753	{ 2700, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
4754	{ 2699, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4754	{ 2699, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4755	{ 2698, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	4755	{ 2698, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
4756	{ 2697, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	4756	{ 2697, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
4757	{ 2696, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---	4757	{ 2696, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---
4758	{ 2695, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4758	{ 2695, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4759	{ 2694, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4759	{ 2694, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4760	{ 2693, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4760	{ 2693, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4761	{ 2692, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4761	{ 2692, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4762	{ 2691, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2691 = SUBV_W	---	4762	{ 2691, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2691 = SUBV_W	---
4763	{ 2690, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2690 = SUBV_H	---	4763	{ 2690, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2690 = SUBV_H	---
4764	{ 2689, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2689 = SUBV_D	---	4764	{ 2689, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2689 = SUBV_D	---
4765	{ 2688, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2688 = SUBV_B	---	4765	{ 2688, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2688 = SUBV_B	---
4766	{ 2687, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2687 = SUBVI_W	---	4766	{ 2687, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2687 = SUBVI_W	---
4767	{ 2686, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2686 = SUBVI_H	---	4767	{ 2686, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2686 = SUBVI_H	---
4768	{ 2685, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2685 = SUBVI_D	---	4768	{ 2685, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2685 = SUBVI_D	---
4769	{ 2684, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2684 = SUBVI_B	---	4769	{ 2684, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2684 = SUBVI_B	---
4770	{ 2683, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2683 = SUBU_S_QB_MM	---	4770	{ 2683, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2683 = SUBU_S_QB_MM	---
4771	{ 2682, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2682 = SUBU_S_QB	---	4771	{ 2682, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2682 = SUBU_S_QB	---
4772	{ 2681, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4772	{ 2681, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4773	{ 2680, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4773	{ 2680, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4774	{ 2679, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4774	{ 2679, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4775	{ 2678, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2678 = SUBU_QB	---	4775	{ 2678, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2678 = SUBU_QB	---
4776	{ 2677, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4776	{ 2677, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4777	{ 2676, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4777	{ 2676, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4778	{ 2675, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4778	{ 2675, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4779	{ 2674, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2674 = SUBUH_R_QB_MMR2	---	4779	{ 2674, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2674 = SUBUH_R_QB_MMR2	---
4780	{ 2673, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2673 = SUBUH_R_QB	---	4780	{ 2673, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2673 = SUBUH_R_QB	---
4781	{ 2672, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2672 = SUBUH_QB_MMR2	---	4781	{ 2672, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2672 = SUBUH_QB_MMR2	---
4782	{ 2671, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2671 = SUBUH_QB	---	4782	{ 2671, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2671 = SUBUH_QB	---
4783	{ 2670, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2670 = SUBU16_MMR6	---	4783	{ 2670, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2670 = SUBU16_MMR6	---
4784	{ 2669, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2669 = SUBU16_MM	---	4784	{ 2669, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #2669 = SUBU16_MM	---
4785	{ 2668, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2668 = SUBS_U_W	---	4785	{ 2668, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2668 = SUBS_U_W	---
4786	{ 2667, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2667 = SUBS_U_H	---	4786	{ 2667, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2667 = SUBS_U_H	---
4787	{ 2666, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2666 = SUBS_U_D	---	4787	{ 2666, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2666 = SUBS_U_D	---
4788	{ 2665, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2665 = SUBS_U_B	---	4788	{ 2665, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2665 = SUBS_U_B	---
4789	{ 2664, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2664 = SUBS_S_W	---	4789	{ 2664, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2664 = SUBS_S_W	---
4790	{ 2663, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2663 = SUBS_S_H	---	4790	{ 2663, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2663 = SUBS_S_H	---
4791	{ 2662, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2662 = SUBS_S_D	---	4791	{ 2662, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2662 = SUBS_S_D	---
4792	{ 2661, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2661 = SUBS_S_B	---	4792	{ 2661, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2661 = SUBS_S_B	---
4793	{ 2660, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2660 = SUBSUU_S_W	---	4793	{ 2660, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2660 = SUBSUU_S_W	---
4794	{ 2659, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2659 = SUBSUU_S_H	---	4794	{ 2659, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2659 = SUBSUU_S_H	---
4795	{ 2658, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2658 = SUBSUU_S_D	---	4795	{ 2658, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2658 = SUBSUU_S_D	---
4796	{ 2657, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2657 = SUBSUU_S_B	---	4796	{ 2657, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2657 = SUBSUU_S_B	---
4797	{ 2656, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2656 = SUBSUS_U_W	---	4797	{ 2656, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2656 = SUBSUS_U_W	---
4798	{ 2655, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2655 = SUBSUS_U_H	---	4798	{ 2655, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2655 = SUBSUS_U_H	---
4799	{ 2654, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2654 = SUBSUS_U_D	---	4799	{ 2654, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2654 = SUBSUS_U_D	---
4800	{ 2653, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2653 = SUBSUS_U_B	---	4800	{ 2653, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2653 = SUBSUS_U_B	---
4801	{ 2652, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---	4801	{ 2652, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---
4802	{ 2651, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---	4802	{ 2651, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---
4803	{ 2650, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2650 = SUBQ_S_PH_MM	---	4803	{ 2650, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2650 = SUBQ_S_PH_MM	---
4804	{ 2649, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2649 = SUBQ_S_PH	---	4804	{ 2649, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2649 = SUBQ_S_PH	---
4805	{ 2648, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	4805	{ 2648, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
4806	{ 2647, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2647 = SUBQ_PH	---	4806	{ 2647, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 529, 0, 0x6ULL }, // Inst #2647 = SUBQ_PH	---
4807	{ 2646, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2646 = SUBQH_W_MMR2	---	4807	{ 2646, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2646 = SUBQH_W_MMR2	---
4808	{ 2645, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2645 = SUBQH_W	---	4808	{ 2645, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2645 = SUBQH_W	---
4809	{ 2644, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2644 = SUBQH_R_W_MMR2	---	4809	{ 2644, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2644 = SUBQH_R_W_MMR2	---
4810	{ 2643, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2643 = SUBQH_R_W	---	4810	{ 2643, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2643 = SUBQH_R_W	---
4811	{ 2642, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2642 = SUBQH_R_PH_MMR2	---	4811	{ 2642, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2642 = SUBQH_R_PH_MMR2	---
4812	{ 2641, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2641 = SUBQH_R_PH	---	4812	{ 2641, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2641 = SUBQH_R_PH	---
4813	{ 2640, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2640 = SUBQH_PH_MMR2	---	4813	{ 2640, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2640 = SUBQH_PH_MMR2	---
4814	{ 2639, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2639 = SUBQH_PH	---	4814	{ 2639, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2639 = SUBQH_PH	---
4815	{ 2638, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	4815	{ 2638, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
4816	{ 2637, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	---	4816	{ 2637, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	---
4817	{ 2636, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	---	4817	{ 2636, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	---
4818	{ 2635, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	---	4818	{ 2635, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	---
4819	{ 2634, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	---	4819	{ 2634, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	---
4820	{ 2633, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4820	{ 2633, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4821	{ 2632, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4821	{ 2632, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4822	{ 2631, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	4822	{ 2631, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
4823	{ 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2630 = SRL_W	---	4823	{ 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2630 = SRL_W	---
4824	{ 2629, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2629 = SRL_MM	---	4824	{ 2629, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2629 = SRL_MM	---
4825	{ 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2628 = SRL_H	---	4825	{ 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2628 = SRL_H	---
4826	{ 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2627 = SRL_D	---	4826	{ 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2627 = SRL_D	---
4827	{ 2626, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2626 = SRL_B	---	4827	{ 2626, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2626 = SRL_B	---
4828	{ 2625, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2625 = SRLV_MM	---	4828	{ 2625, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2625 = SRLV_MM	---
4829	{ 2624, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2624 = SRLV	---	4829	{ 2624, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2624 = SRLV	---
4830	{ 2623, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2623 = SRLR_W	---	4830	{ 2623, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2623 = SRLR_W	---
4831	{ 2622, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2622 = SRLR_H	---	4831	{ 2622, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2622 = SRLR_H	---
4832	{ 2621, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2621 = SRLR_D	---	4832	{ 2621, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2621 = SRLR_D	---
4833	{ 2620, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2620 = SRLR_B	---	4833	{ 2620, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2620 = SRLR_B	---
4834	{ 2619, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2619 = SRLRI_W	---	4834	{ 2619, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2619 = SRLRI_W	---
4835	{ 2618, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2618 = SRLRI_H	---	4835	{ 2618, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2618 = SRLRI_H	---
4836	{ 2617, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2617 = SRLRI_D	---	4836	{ 2617, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2617 = SRLRI_D	---
4837	{ 2616, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2616 = SRLRI_B	---	4837	{ 2616, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2616 = SRLRI_B	---
4838	{ 2615, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2615 = SRLI_W	---	4838	{ 2615, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2615 = SRLI_W	---
4839	{ 2614, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2614 = SRLI_H	---	4839	{ 2614, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2614 = SRLI_H	---
4840	{ 2613, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2613 = SRLI_D	---	4840	{ 2613, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2613 = SRLI_D	---
4841	{ 2612, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2612 = SRLI_B	---	4841	{ 2612, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2612 = SRLI_B	---
4842	{ 2611, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---	4842	{ 2611, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---
4843	{ 2610, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2610 = SRL16_MM	---	4843	{ 2610, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2610 = SRL16_MM	---
4844	{ 2609, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2609 = SRL	---	4844	{ 2609, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2609 = SRL	---
4845	{ 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2608 = SRA_W	---	4845	{ 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2608 = SRA_W	---
4846	{ 2607, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2607 = SRA_MM	---	4846	{ 2607, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2607 = SRA_MM	---
4847	{ 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2606 = SRA_H	---	4847	{ 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2606 = SRA_H	---
4848	{ 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2605 = SRA_D	---	4848	{ 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2605 = SRA_D	---
4849	{ 2604, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2604 = SRA_B	---	4849	{ 2604, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2604 = SRA_B	---
4850	{ 2603, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2603 = SRAV_MM	---	4850	{ 2603, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2603 = SRAV_MM	---
4851	{ 2602, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2602 = SRAV	---	4851	{ 2602, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2602 = SRAV	---
4852	{ 2601, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2601 = SRAR_W	---	4852	{ 2601, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2601 = SRAR_W	---
4853	{ 2600, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2600 = SRAR_H	---	4853	{ 2600, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2600 = SRAR_H	---
4854	{ 2599, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2599 = SRAR_D	---	4854	{ 2599, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2599 = SRAR_D	---
4855	{ 2598, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2598 = SRAR_B	---	4855	{ 2598, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2598 = SRAR_B	---
4856	{ 2597, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2597 = SRARI_W	---	4856	{ 2597, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2597 = SRARI_W	---
4857	{ 2596, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2596 = SRARI_H	---	4857	{ 2596, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2596 = SRARI_H	---
4858	{ 2595, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2595 = SRARI_D	---	4858	{ 2595, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2595 = SRARI_D	---
4859	{ 2594, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2594 = SRARI_B	---	4859	{ 2594, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2594 = SRARI_B	---
4860	{ 2593, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2593 = SRAI_W	---	4860	{ 2593, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2593 = SRAI_W	---
4861	{ 2592, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2592 = SRAI_H	---	4861	{ 2592, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2592 = SRAI_H	---
4862	{ 2591, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2591 = SRAI_D	---	4862	{ 2591, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2591 = SRAI_D	---
4863	{ 2590, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2590 = SRAI_B	---	4863	{ 2590, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2590 = SRAI_B	---
4864	{ 2589, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2589 = SRA	---	4864	{ 2589, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2589 = SRA	---
4865	{ 2588, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1119, 0, 0x6ULL }, // Inst #2588 = SPLAT_W	---	4865	{ 2588, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1119, 0, 0x6ULL }, // Inst #2588 = SPLAT_W	---
4866	{ 2587, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2587 = SPLAT_H	---	4866	{ 2587, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2587 = SPLAT_H	---
4867	{ 2586, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1113, 0, 0x6ULL }, // Inst #2586 = SPLAT_D	---	4867	{ 2586, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1113, 0, 0x6ULL }, // Inst #2586 = SPLAT_D	---
4868	{ 2585, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1110, 0, 0x6ULL }, // Inst #2585 = SPLAT_B	---	4868	{ 2585, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1110, 0, 0x6ULL }, // Inst #2585 = SPLAT_B	---
4869	{ 2584, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2584 = SPLATI_W	---	4869	{ 2584, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2584 = SPLATI_W	---
4870	{ 2583, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2583 = SPLATI_H	---	4870	{ 2583, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2583 = SPLATI_H	---
4871	{ 2582, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2582 = SPLATI_D	---	4871	{ 2582, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2582 = SPLATI_D	---
4872	{ 2581, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2581 = SPLATI_B	---	4872	{ 2581, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2581 = SPLATI_B	---
4873	{ 2580, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2580 = SNEi	---	4873	{ 2580, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2580 = SNEi	---
4874	{ 2579, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2579 = SNE	---	4874	{ 2579, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2579 = SNE	---
4875	{ 2578, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2578 = SLTu_MM	---	4875	{ 2578, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2578 = SLTu_MM	---
4876	{ 2577, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2577 = SLTu64	---	4876	{ 2577, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2577 = SLTu64	---
4877	{ 2576, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2576 = SLTu	---	4877	{ 2576, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2576 = SLTu	---
4878	{ 2575, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2575 = SLTiu_MM	---	4878	{ 2575, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2575 = SLTiu_MM	---
4879	{ 2574, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2574 = SLTiu64	---	4879	{ 2574, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2574 = SLTiu64	---
4880	{ 2573, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2573 = SLTiu	---	4880	{ 2573, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2573 = SLTiu	---
4881	{ 2572, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2572 = SLTi_MM	---	4881	{ 2572, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2572 = SLTi_MM	---
4882	{ 2571, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2571 = SLTi64	---	4882	{ 2571, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1107, 0, 0x2ULL }, // Inst #2571 = SLTi64	---
4883	{ 2570, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2570 = SLTi	---	4883	{ 2570, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 225, 0, 0x2ULL }, // Inst #2570 = SLTi	---
4884	{ 2569, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2569 = SLT_MM	---	4884	{ 2569, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2569 = SLT_MM	---
4885	{ 2568, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2568 = SLT64	---	4885	{ 2568, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x1ULL }, // Inst #2568 = SLT64	---
4886	{ 2567, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2567 = SLT	---	4886	{ 2567, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2567 = SLT	---
4887	{ 2566, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2566 = SLL_W	---	4887	{ 2566, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2566 = SLL_W	---
4888	{ 2565, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4888	{ 2565, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4889	{ 2564, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2564 = SLL_MM	---	4889	{ 2564, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2564 = SLL_MM	---
4890	{ 2563, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2563 = SLL_H	---	4890	{ 2563, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2563 = SLL_H	---
4891	{ 2562, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2562 = SLL_D	---	4891	{ 2562, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2562 = SLL_D	---
4892	{ 2561, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2561 = SLL_B	---	4892	{ 2561, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2561 = SLL_B	---
4893	{ 2560, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2560 = SLLV_MM	---	4893	{ 2560, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2560 = SLLV_MM	---
4894	{ 2559, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2559 = SLLV	---	4894	{ 2559, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2559 = SLLV	---
4895	{ 2558, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2558 = SLLI_W	---	4895	{ 2558, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2558 = SLLI_W	---
4896	{ 2557, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2557 = SLLI_H	---	4896	{ 2557, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2557 = SLLI_H	---
4897	{ 2556, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2556 = SLLI_D	---	4897	{ 2556, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2556 = SLLI_D	---
4898	{ 2555, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2555 = SLLI_B	---	4898	{ 2555, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2555 = SLLI_B	---
4899	{ 2554, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---	4899	{ 2554, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---
4900	{ 2553, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	---	4900	{ 2553, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	---
4901	{ 2552, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---	4901	{ 2552, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---
4902	{ 2551, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2551 = SLL16_MM	---	4902	{ 2551, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #2551 = SLL16_MM	---
4903	{ 2550, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2550 = SLL	---	4903	{ 2550, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2550 = SLL	---
4904	{ 2549, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2549 = SLD_W	---	4904	{ 2549, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2549 = SLD_W	---
4905	{ 2548, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2548 = SLD_H	---	4905	{ 2548, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2548 = SLD_H	---
4906	{ 2547, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2547 = SLD_D	---	4906	{ 2547, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2547 = SLD_D	---
4907	{ 2546, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1088, 0, 0x6ULL }, // Inst #2546 = SLD_B	---	4907	{ 2546, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1088, 0, 0x6ULL }, // Inst #2546 = SLD_B	---
4908	{ 2545, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2545 = SLDI_W	---	4908	{ 2545, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2545 = SLDI_W	---
4909	{ 2544, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2544 = SLDI_H	---	4909	{ 2544, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2544 = SLDI_H	---
4910	{ 2543, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2543 = SLDI_D	---	4910	{ 2543, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2543 = SLDI_D	---
4911	{ 2542, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #2542 = SLDI_B	---	4911	{ 2542, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #2542 = SLDI_B	---
4912	{ 2541, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4912	{ 2541, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4913	{ 2540, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	4913	{ 2540, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
4914	{ 2539, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4914	{ 2539, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4915	{ 2538, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4915	{ 2538, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4916	{ 2537, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4916	{ 2537, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4917	{ 2536, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4917	{ 2536, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4918	{ 2535, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4918	{ 2535, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4919	{ 2534, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4919	{ 2534, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4920	{ 2533, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2533 = SHRLV_QB_MM	---	4920	{ 2533, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2533 = SHRLV_QB_MM	---
4921	{ 2532, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2532 = SHRLV_QB	---	4921	{ 2532, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2532 = SHRLV_QB	---
4922	{ 2531, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2531 = SHRLV_PH_MMR2	---	4922	{ 2531, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2531 = SHRLV_PH_MMR2	---
4923	{ 2530, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2530 = SHRLV_PH	---	4923	{ 2530, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2530 = SHRLV_PH	---
4924	{ 2529, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4924	{ 2529, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4925	{ 2528, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	4925	{ 2528, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
4926	{ 2527, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4926	{ 2527, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4927	{ 2526, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4927	{ 2526, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4928	{ 2525, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4928	{ 2525, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4929	{ 2524, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4929	{ 2524, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4930	{ 2523, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4930	{ 2523, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4931	{ 2522, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4931	{ 2522, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4932	{ 2521, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4932	{ 2521, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4933	{ 2520, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---	4933	{ 2520, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1085, 0\|(1ULL<	---
4934	{ 2519, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2519 = SHRAV_R_W_MM	---	4934	{ 2519, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2519 = SHRAV_R_W_MM	---
4935	{ 2518, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2518 = SHRAV_R_W	---	4935	{ 2518, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2518 = SHRAV_R_W	---
4936	{ 2517, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2517 = SHRAV_R_QB_MMR2	---	4936	{ 2517, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2517 = SHRAV_R_QB_MMR2	---
4937	{ 2516, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2516 = SHRAV_R_QB	---	4937	{ 2516, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2516 = SHRAV_R_QB	---
4938	{ 2515, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2515 = SHRAV_R_PH_MM	---	4938	{ 2515, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2515 = SHRAV_R_PH_MM	---
4939	{ 2514, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2514 = SHRAV_R_PH	---	4939	{ 2514, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2514 = SHRAV_R_PH	---
4940	{ 2513, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2513 = SHRAV_QB_MMR2	---	4940	{ 2513, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2513 = SHRAV_QB_MMR2	---
4941	{ 2512, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2512 = SHRAV_QB	---	4941	{ 2512, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2512 = SHRAV_QB	---
4942	{ 2511, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2511 = SHRAV_PH_MM	---	4942	{ 2511, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2511 = SHRAV_PH_MM	---
4943	{ 2510, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2510 = SHRAV_PH	---	4943	{ 2510, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1082, 0, 0x6ULL }, // Inst #2510 = SHRAV_PH	---
4944	{ 2509, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	---	4944	{ 2509, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	---
4945	{ 2508, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	---	4945	{ 2508, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 225, 0\|(1ULL<	---
4946	{ 2507, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4946	{ 2507, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4947	{ 2506, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4947	{ 2506, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4948	{ 2505, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4948	{ 2505, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4949	{ 2504, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4949	{ 2504, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4950	{ 2503, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4950	{ 2503, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4951	{ 2502, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---	4951	{ 2502, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1085, 0\|(1ULL<	---
4952	{ 2501, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	---	4952	{ 2501, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	---
4953	{ 2500, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	---	4953	{ 2500, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 222, 0\|(1ULL<	---
4954	{ 2499, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4954	{ 2499, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4955	{ 2498, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4955	{ 2498, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4956	{ 2497, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4956	{ 2497, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4957	{ 2496, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4957	{ 2496, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4958	{ 2495, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4958	{ 2495, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4959	{ 2494, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---	4959	{ 2494, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1082, 0\|(1ULL<	---
4960	{ 2493, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SHILO_MM	---	4960	{ 2493, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SHILO_MM	---
4961	{ 2492, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2492 = SHILOV_MM	---	4961	{ 2492, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2492 = SHILOV_MM	---
4962	{ 2491, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2491 = SHILOV	---	4962	{ 2491, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1021, 0, 0x6ULL }, // Inst #2491 = SHILOV	---
4963	{ 2490, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2490 = SHILO	---	4963	{ 2490, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2490 = SHILO	---
4964	{ 2489, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2489 = SHF_W	---	4964	{ 2489, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2489 = SHF_W	---
4965	{ 2488, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2488 = SHF_H	---	4965	{ 2488, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2488 = SHF_H	---
4966	{ 2487, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2487 = SHF_B	---	4966	{ 2487, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2487 = SHF_B	---
4967	{ 2486, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4967	{ 2486, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4968	{ 2485, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4968	{ 2485, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4969	{ 2484, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	4969	{ 2484, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
4970	{ 2483, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	4970	{ 2483, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
4971	{ 2482, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	4971	{ 2482, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
4972	{ 2481, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	4972	{ 2481, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
4973	{ 2480, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2480 = SEQi	---	4973	{ 2480, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 216, 0, 0x2ULL }, // Inst #2480 = SEQi	---
4974	{ 2479, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2479 = SEQ	---	4974	{ 2479, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 219, 0, 0x1ULL }, // Inst #2479 = SEQ	---
4975	{ 2478, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2478 = SEL_S_MMR6	---	4975	{ 2478, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2478 = SEL_S_MMR6	---
4976	{ 2477, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2477 = SEL_S	---	4976	{ 2477, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1075, 0, 0x6ULL }, // Inst #2477 = SEL_S	---
4977	{ 2476, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2476 = SEL_D_MMR6	---	4977	{ 2476, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2476 = SEL_D_MMR6	---
4978	{ 2475, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2475 = SEL_D	---	4978	{ 2475, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 916, 0, 0x6ULL }, // Inst #2475 = SEL_D	---
4979	{ 2474, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	4979	{ 2474, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
4980	{ 2473, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	4980	{ 2473, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
4981	{ 2472, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2472 = SELNEZ_MMR6	---	4981	{ 2472, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2472 = SELNEZ_MMR6	---
4982	{ 2471, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	4982	{ 2471, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
4983	{ 2470, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	4983	{ 2470, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
4984	{ 2469, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2469 = SELNEZ64	---	4984	{ 2469, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2469 = SELNEZ64	---
4985	{ 2468, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2468 = SELNEZ	---	4985	{ 2468, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2468 = SELNEZ	---
4986	{ 2467, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	4986	{ 2467, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
4987	{ 2466, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	4987	{ 2466, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
4988	{ 2465, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2465 = SELEQZ_MMR6	---	4988	{ 2465, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2465 = SELEQZ_MMR6	---
4989	{ 2464, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	4989	{ 2464, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
4990	{ 2463, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	4990	{ 2463, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
4991	{ 2462, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2462 = SELEQZ64	---	4991	{ 2462, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #2462 = SELEQZ64	---
4992	{ 2461, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2461 = SELEQZ	---	4992	{ 2461, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2461 = SELEQZ	---
4993	{ 2460, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2460 = SEH_MM	---	4993	{ 2460, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2460 = SEH_MM	---
4994	{ 2459, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2459 = SEH64	---	4994	{ 2459, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2459 = SEH64	---
4995	{ 2458, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2458 = SEH	---	4995	{ 2458, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2458 = SEH	---
4996	{ 2457, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2457 = SEB_MM	---	4996	{ 2457, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2457 = SEB_MM	---
4997	{ 2456, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2456 = SEB64	---	4997	{ 2456, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #2456 = SEB64	---
4998	{ 2455, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2455 = SEB	---	4998	{ 2455, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2455 = SEB	---
4999	{ 2454, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	4999	{ 2454, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
5000	{ 2453, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---	5000	{ 2453, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---
5001	{ 2452, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5001	{ 2452, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5002	{ 2451, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5002	{ 2451, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5003	{ 2450, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5003	{ 2450, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5004	{ 2449, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5004	{ 2449, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5005	{ 2448, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---	5005	{ 2448, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---
5006	{ 2447, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5006	{ 2447, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5007	{ 2446, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---	5007	{ 2446, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---
5008	{ 2445, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5008	{ 2445, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5009	{ 2444, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5009	{ 2444, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5010	{ 2443, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---	5010	{ 2443, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---
5011	{ 2442, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5011	{ 2442, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5012	{ 2441, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5012	{ 2441, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5013	{ 2440, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---	5013	{ 2440, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---
5014	{ 2439, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5014	{ 2439, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5015	{ 2438, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5015	{ 2438, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5016	{ 2437, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5016	{ 2437, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5017	{ 2436, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5017	{ 2436, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5018	{ 2435, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5018	{ 2435, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5019	{ 2434, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5019	{ 2434, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5020	{ 2433, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5020	{ 2433, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5021	{ 2432, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	---	5021	{ 2432, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	---
5022	{ 2431, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5022	{ 2431, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5023	{ 2430, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5023	{ 2430, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5024	{ 2429, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5024	{ 2429, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5025	{ 2428, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5025	{ 2428, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5026	{ 2427, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1071, 0\|(1ULL<	---	5026	{ 2427, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1071, 0\|(1ULL<	---
5027	{ 2426, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1067, 0\|(1ULL<	---	5027	{ 2426, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1067, 0\|(1ULL<	---
5028	{ 2425, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	---	5028	{ 2425, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1063, 0\|(1ULL<	---
5029	{ 2424, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5029	{ 2424, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5030	{ 2423, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---	5030	{ 2423, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1059, 0\|(1ULL<	---
5031	{ 2422, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5031	{ 2422, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5032	{ 2421, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5032	{ 2421, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5033	{ 2420, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5033	{ 2420, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5034	{ 2419, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5034	{ 2419, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5035	{ 2418, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5035	{ 2418, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5036	{ 2417, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	5036	{ 2417, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
5037	{ 2416, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---	5037	{ 2416, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1056, 0\|(1ULL<	---
5038	{ 2415, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5038	{ 2415, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5039	{ 2414, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2414 = SAT_U_W	---	5039	{ 2414, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2414 = SAT_U_W	---
5040	{ 2413, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2413 = SAT_U_H	---	5040	{ 2413, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2413 = SAT_U_H	---
5041	{ 2412, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2412 = SAT_U_D	---	5041	{ 2412, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2412 = SAT_U_D	---
5042	{ 2411, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2411 = SAT_U_B	---	5042	{ 2411, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2411 = SAT_U_B	---
5043	{ 2410, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2410 = SAT_S_W	---	5043	{ 2410, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2410 = SAT_S_W	---
5044	{ 2409, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2409 = SAT_S_H	---	5044	{ 2409, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2409 = SAT_S_H	---
5045	{ 2408, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2408 = SAT_S_D	---	5045	{ 2408, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2408 = SAT_S_D	---
5046	{ 2407, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2407 = SAT_S_B	---	5046	{ 2407, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2407 = SAT_S_B	---
5047	{ 2406, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---	5047	{ 2406, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---
5048	{ 2405, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---	5048	{ 2405, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---
5049	{ 2404, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5049	{ 2404, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5050	{ 2403, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5050	{ 2403, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5051	{ 2402, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2402 = RSQRT_S_MM	---	5051	{ 2402, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2402 = RSQRT_S_MM	---
5052	{ 2401, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2401 = RSQRT_S	---	5052	{ 2401, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2401 = RSQRT_S	---
5053	{ 2400, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2400 = RSQRT_D64_MM	---	5053	{ 2400, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2400 = RSQRT_D64_MM	---
5054	{ 2399, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2399 = RSQRT_D64	---	5054	{ 2399, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2399 = RSQRT_D64	---
5055	{ 2398, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2398 = RSQRT_D32_MM	---	5055	{ 2398, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2398 = RSQRT_D32_MM	---
5056	{ 2397, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2397 = RSQRT_D32	---	5056	{ 2397, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2397 = RSQRT_D32	---
5057	{ 2396, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2396 = ROUND_W_S_MMR6	---	5057	{ 2396, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2396 = ROUND_W_S_MMR6	---
5058	{ 2395, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2395 = ROUND_W_S_MM	---	5058	{ 2395, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2395 = ROUND_W_S_MM	---
5059	{ 2394, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2394 = ROUND_W_S	---	5059	{ 2394, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2394 = ROUND_W_S	---
5060	{ 2393, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2393 = ROUND_W_MM	---	5060	{ 2393, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2393 = ROUND_W_MM	---
5061	{ 2392, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2392 = ROUND_W_D_MMR6	---	5061	{ 2392, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2392 = ROUND_W_D_MMR6	---
5062	{ 2391, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2391 = ROUND_W_D64	---	5062	{ 2391, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2391 = ROUND_W_D64	---
5063	{ 2390, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2390 = ROUND_W_D32	---	5063	{ 2390, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2390 = ROUND_W_D32	---
5064	{ 2389, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2389 = ROUND_L_S_MMR6	---	5064	{ 2389, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2389 = ROUND_L_S_MMR6	---
5065	{ 2388, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2388 = ROUND_L_S	---	5065	{ 2388, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #2388 = ROUND_L_S	---
5066	{ 2387, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2387 = ROUND_L_D_MMR6	---	5066	{ 2387, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2387 = ROUND_L_D_MMR6	---
5067	{ 2386, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2386 = ROUND_L_D64	---	5067	{ 2386, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2386 = ROUND_L_D64	---
5068	{ 2385, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2385 = ROTR_MM	---	5068	{ 2385, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2385 = ROTR_MM	---
5069	{ 2384, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2384 = ROTRV_MM	---	5069	{ 2384, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2384 = ROTRV_MM	---
5070	{ 2383, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2383 = ROTRV	---	5070	{ 2383, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 222, 0, 0x1ULL }, // Inst #2383 = ROTRV	---
5071	{ 2382, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2382 = ROTR	---	5071	{ 2382, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 225, 0, 0x1ULL }, // Inst #2382 = ROTR	---
5072	{ 2381, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	5072	{ 2381, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
5073	{ 2380, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	5073	{ 2380, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
5074	{ 2379, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---	5074	{ 2379, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---
5075	{ 2378, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---	5075	{ 2378, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---
5076	{ 2377, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2377 = REPL_QB_MM	---	5076	{ 2377, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2377 = REPL_QB_MM	---
5077	{ 2376, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2376 = REPL_QB	---	5077	{ 2376, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2376 = REPL_QB	---
5078	{ 2375, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2375 = REPL_PH_MM	---	5078	{ 2375, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2375 = REPL_PH_MM	---
5079	{ 2374, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2374 = REPL_PH	---	5079	{ 2374, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1054, 0, 0x6ULL }, // Inst #2374 = REPL_PH	---
5080	{ 2373, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = REPLV_QB_MM	---	5080	{ 2373, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = REPLV_QB_MM	---
5081	{ 2372, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = REPLV_QB	---	5081	{ 2372, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = REPLV_QB	---
5082	{ 2371, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2371 = REPLV_PH_MM	---	5082	{ 2371, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2371 = REPLV_PH_MM	---
5083	{ 2370, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2370 = REPLV_PH	---	5083	{ 2370, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2370 = REPLV_PH	---
5084	{ 2369, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2369 = RECIP_S_MM	---	5084	{ 2369, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2369 = RECIP_S_MM	---
5085	{ 2368, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2368 = RECIP_S	---	5085	{ 2368, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2368 = RECIP_S	---
5086	{ 2367, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2367 = RECIP_D64_MM	---	5086	{ 2367, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2367 = RECIP_D64_MM	---
5087	{ 2366, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2366 = RECIP_D64	---	5087	{ 2366, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #2366 = RECIP_D64	---
5088	{ 2365, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2365 = RECIP_D32_MM	---	5088	{ 2365, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2365 = RECIP_D32_MM	---
5089	{ 2364, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2364 = RECIP_D32	---	5089	{ 2364, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #2364 = RECIP_D32	---
5090	{ 2363, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	5090	{ 2363, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
5091	{ 2362, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---	5091	{ 2362, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---
5092	{ 2361, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---	5092	{ 2361, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---
5093	{ 2360, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1049, 0\|(1ULL<	---	5093	{ 2360, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1049, 0\|(1ULL<	---
5094	{ 2359, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---	5094	{ 2359, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1046, 0\|(1ULL<	---
5095	{ 2358, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5095	{ 2358, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5096	{ 2357, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5096	{ 2357, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5097	{ 2356, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2356 = RADDU_W_QB_MM	---	5097	{ 2356, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2356 = RADDU_W_QB_MM	---
5098	{ 2355, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2355 = RADDU_W_QB	---	5098	{ 2355, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2355 = RADDU_W_QB	---
5099	{ 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5099	{ 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5100	{ 2353, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5100	{ 2353, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5101	{ 2352, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2352 = PREPEND_MMR2	---	5101	{ 2352, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2352 = PREPEND_MMR2	---
5102	{ 2351, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2351 = PREPEND	---	5102	{ 2351, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2351 = PREPEND	---
5103	{ 2350, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5103	{ 2350, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5104	{ 2349, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5104	{ 2349, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5105	{ 2348, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5105	{ 2348, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5106	{ 2347, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1043, 0\|(1ULL<	---	5106	{ 2347, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1043, 0\|(1ULL<	---
5107	{ 2346, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5107	{ 2346, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5108	{ 2345, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5108	{ 2345, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5109	{ 2344, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	5109	{ 2344, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
5110	{ 2343, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2343 = PRECR_SRA_R_PH_W_MMR2	---	5110	{ 2343, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2343 = PRECR_SRA_R_PH_W_MMR2	---
5111	{ 2342, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2342 = PRECR_SRA_R_PH_W	---	5111	{ 2342, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2342 = PRECR_SRA_R_PH_W	---
5112	{ 2341, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2341 = PRECR_SRA_PH_W_MMR2	---	5112	{ 2341, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2341 = PRECR_SRA_PH_W_MMR2	---
5113	{ 2340, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2340 = PRECR_SRA_PH_W	---	5113	{ 2340, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1039, 0, 0x6ULL }, // Inst #2340 = PRECR_SRA_PH_W	---
5114	{ 2339, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	5114	{ 2339, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
5115	{ 2338, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	5115	{ 2338, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
5116	{ 2337, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	---	5116	{ 2337, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	---
5117	{ 2336, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	---	5117	{ 2336, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1036, 0\|(1ULL<	---
5118	{ 2335, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2335 = PRECRQ_QB_PH_MM	---	5118	{ 2335, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2335 = PRECRQ_QB_PH_MM	---
5119	{ 2334, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2334 = PRECRQ_QB_PH	---	5119	{ 2334, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2334 = PRECRQ_QB_PH	---
5120	{ 2333, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2333 = PRECRQ_PH_W_MM	---	5120	{ 2333, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2333 = PRECRQ_PH_W_MM	---
5121	{ 2332, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2332 = PRECRQ_PH_W	---	5121	{ 2332, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x6ULL }, // Inst #2332 = PRECRQ_PH_W	---
5122	{ 2331, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	---	5122	{ 2331, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	---
5123	{ 2330, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	---	5123	{ 2330, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 529, 0\|(1ULL<	---
5124	{ 2329, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2329 = PRECEU_PH_QBR_MM	---	5124	{ 2329, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2329 = PRECEU_PH_QBR_MM	---
5125	{ 2328, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2328 = PRECEU_PH_QBRA_MM	---	5125	{ 2328, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2328 = PRECEU_PH_QBRA_MM	---
5126	{ 2327, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2327 = PRECEU_PH_QBRA	---	5126	{ 2327, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2327 = PRECEU_PH_QBRA	---
5127	{ 2326, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2326 = PRECEU_PH_QBR	---	5127	{ 2326, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2326 = PRECEU_PH_QBR	---
5128	{ 2325, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2325 = PRECEU_PH_QBL_MM	---	5128	{ 2325, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2325 = PRECEU_PH_QBL_MM	---
5129	{ 2324, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2324 = PRECEU_PH_QBLA_MM	---	5129	{ 2324, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2324 = PRECEU_PH_QBLA_MM	---
5130	{ 2323, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2323 = PRECEU_PH_QBLA	---	5130	{ 2323, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2323 = PRECEU_PH_QBLA	---
5131	{ 2322, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2322 = PRECEU_PH_QBL	---	5131	{ 2322, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2322 = PRECEU_PH_QBL	---
5132	{ 2321, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2321 = PRECEQ_W_PHR_MM	---	5132	{ 2321, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2321 = PRECEQ_W_PHR_MM	---
5133	{ 2320, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2320 = PRECEQ_W_PHR	---	5133	{ 2320, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2320 = PRECEQ_W_PHR	---
5134	{ 2319, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2319 = PRECEQ_W_PHL_MM	---	5134	{ 2319, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2319 = PRECEQ_W_PHL_MM	---
5135	{ 2318, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2318 = PRECEQ_W_PHL	---	5135	{ 2318, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2318 = PRECEQ_W_PHL	---
5136	{ 2317, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2317 = PRECEQU_PH_QBR_MM	---	5136	{ 2317, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2317 = PRECEQU_PH_QBR_MM	---
5137	{ 2316, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2316 = PRECEQU_PH_QBRA_MM	---	5137	{ 2316, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2316 = PRECEQU_PH_QBRA_MM	---
5138	{ 2315, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2315 = PRECEQU_PH_QBRA	---	5138	{ 2315, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2315 = PRECEQU_PH_QBRA	---
5139	{ 2314, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2314 = PRECEQU_PH_QBR	---	5139	{ 2314, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2314 = PRECEQU_PH_QBR	---
5140	{ 2313, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2313 = PRECEQU_PH_QBL_MM	---	5140	{ 2313, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2313 = PRECEQU_PH_QBL_MM	---
5141	{ 2312, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2312 = PRECEQU_PH_QBLA_MM	---	5141	{ 2312, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2312 = PRECEQU_PH_QBLA_MM	---
5142	{ 2311, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2311 = PRECEQU_PH_QBLA	---	5142	{ 2311, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2311 = PRECEQU_PH_QBLA	---
5143	{ 2310, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2310 = PRECEQU_PH_QBL	---	5143	{ 2310, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 519, 0, 0x6ULL }, // Inst #2310 = PRECEQU_PH_QBL	---
5144	{ 2309, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2309 = POP	---	5144	{ 2309, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #2309 = POP	---
5145	{ 2308, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5145	{ 2308, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5146	{ 2307, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5146	{ 2307, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5147	{ 2306, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---	5147	{ 2306, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---
5148	{ 2305, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---	5148	{ 2305, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---
5149	{ 2304, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---	5149	{ 2304, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---
5150	{ 2303, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---	5150	{ 2303, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 529, 0\|(1ULL<	---
5151	{ 2302, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2302 = PCNT_W	---	5151	{ 2302, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2302 = PCNT_W	---
5152	{ 2301, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2301 = PCNT_H	---	5152	{ 2301, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2301 = PCNT_H	---
5153	{ 2300, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2300 = PCNT_D	---	5153	{ 2300, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2300 = PCNT_D	---
5154	{ 2299, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2299 = PCNT_B	---	5154	{ 2299, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2299 = PCNT_B	---
5155	{ 2298, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2298 = PCKOD_W	---	5155	{ 2298, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2298 = PCKOD_W	---
5156	{ 2297, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2297 = PCKOD_H	---	5156	{ 2297, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2297 = PCKOD_H	---
5157	{ 2296, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2296 = PCKOD_D	---	5157	{ 2296, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2296 = PCKOD_D	---
5158	{ 2295, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2295 = PCKOD_B	---	5158	{ 2295, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2295 = PCKOD_B	---
5159	{ 2294, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2294 = PCKEV_W	---	5159	{ 2294, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2294 = PCKEV_W	---
5160	{ 2293, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2293 = PCKEV_H	---	5160	{ 2293, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2293 = PCKEV_H	---
5161	{ 2292, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2292 = PCKEV_D	---	5161	{ 2292, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2292 = PCKEV_D	---
5162	{ 2291, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2291 = PCKEV_B	---	5162	{ 2291, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2291 = PCKEV_B	---
5163	{ 2290, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5163	{ 2290, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5164	{ 2289, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5164	{ 2289, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5165	{ 2288, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5165	{ 2288, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5166	{ 2287, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2287 = PACKRL_PH_MM	---	5166	{ 2287, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2287 = PACKRL_PH_MM	---
5167	{ 2286, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2286 = PACKRL_PH	---	5167	{ 2286, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 529, 0, 0x6ULL }, // Inst #2286 = PACKRL_PH	---
5168	{ 2285, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---	5168	{ 2285, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---
5169	{ 2284, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	5169	{ 2284, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
5170	{ 2283, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	5170	{ 2283, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
5171	{ 2282, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	5171	{ 2282, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
5172	{ 2281, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2281 = OR_V	---	5172	{ 2281, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2281 = OR_V	---
5173	{ 2280, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5173	{ 2280, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5174	{ 2279, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5174	{ 2279, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5175	{ 2278, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	5175	{ 2278, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
5176	{ 2277, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2277 = ORI_B	---	5176	{ 2277, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2277 = ORI_B	---
5177	{ 2276, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	5177	{ 2276, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
5178	{ 2275, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	5178	{ 2275, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
5179	{ 2274, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	5179	{ 2274, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
5180	{ 2273, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5180	{ 2273, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5181	{ 2272, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2272 = NotRxRy16	---	5181	{ 2272, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2272 = NotRxRy16	---
5182	{ 2271, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2271 = NegRxRy16	---	5182	{ 2271, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 390, 0, 0x0ULL }, // Inst #2271 = NegRxRy16	---
5183	{ 2270, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2270 = NOT16_MMR6	---	5183	{ 2270, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2270 = NOT16_MMR6	---
5184	{ 2269, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2269 = NOT16_MM	---	5184	{ 2269, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1032, 0, 0x0ULL }, // Inst #2269 = NOT16_MM	---
5185	{ 2268, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2268 = NOR_V	---	5185	{ 2268, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2268 = NOR_V	---
5186	{ 2267, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5186	{ 2267, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5187	{ 2266, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5187	{ 2266, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5188	{ 2265, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2265 = NORI_B	---	5188	{ 2265, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2265 = NORI_B	---
5189	{ 2264, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	5189	{ 2264, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
5190	{ 2263, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5190	{ 2263, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5191	{ 2262, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2262 = NMSUB_S_MM	---	5191	{ 2262, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2262 = NMSUB_S_MM	---
5192	{ 2261, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2261 = NMSUB_S	---	5192	{ 2261, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2261 = NMSUB_S	---
5193	{ 2260, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2260 = NMSUB_D64	---	5193	{ 2260, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2260 = NMSUB_D64	---
5194	{ 2259, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2259 = NMSUB_D32_MM	---	5194	{ 2259, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2259 = NMSUB_D32_MM	---
5195	{ 2258, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2258 = NMSUB_D32	---	5195	{ 2258, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2258 = NMSUB_D32	---
5196	{ 2257, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2257 = NMADD_S_MM	---	5196	{ 2257, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2257 = NMADD_S_MM	---
5197	{ 2256, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2256 = NMADD_S	---	5197	{ 2256, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2256 = NMADD_S	---
5198	{ 2255, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2255 = NMADD_D64	---	5198	{ 2255, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2255 = NMADD_D64	---
5199	{ 2254, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2254 = NMADD_D32_MM	---	5199	{ 2254, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2254 = NMADD_D32_MM	---
5200	{ 2253, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2253 = NMADD_D32	---	5200	{ 2253, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2253 = NMADD_D32	---
5201	{ 2252, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2252 = NLZC_W	---	5201	{ 2252, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2252 = NLZC_W	---
5202	{ 2251, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2251 = NLZC_H	---	5202	{ 2251, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2251 = NLZC_H	---
5203	{ 2250, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2250 = NLZC_D	---	5203	{ 2250, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2250 = NLZC_D	---
5204	{ 2249, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2249 = NLZC_B	---	5204	{ 2249, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2249 = NLZC_B	---
5205	{ 2248, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2248 = NLOC_W	---	5205	{ 2248, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #2248 = NLOC_W	---
5206	{ 2247, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2247 = NLOC_H	---	5206	{ 2247, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1030, 0, 0x6ULL }, // Inst #2247 = NLOC_H	---
5207	{ 2246, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2246 = NLOC_D	---	5207	{ 2246, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #2246 = NLOC_D	---
5208	{ 2245, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2245 = NLOC_B	---	5208	{ 2245, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 952, 0, 0x6ULL }, // Inst #2245 = NLOC_B	---
5209	{ 2244, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1028, 0\|(1ULL<	---	5209	{ 2244, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1028, 0\|(1ULL<	---
5210	{ 2243, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1026, 0\|(1ULL<	---	5210	{ 2243, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1026, 0\|(1ULL<	---
5211	{ 2242, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 829, 0, 0x0ULL }, // Inst #2242 = Mflo16	---	5211	{ 2242, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 829, 0, 0x0ULL }, // Inst #2242 = Mflo16	---
5212	{ 2241, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 829, 0\|(1ULL<	---	5212	{ 2241, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 829, 0\|(1ULL<	---
5213	{ 2240, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5213	{ 2240, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5214	{ 2239, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5214	{ 2239, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5215	{ 2238, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2238 = MUL_R6	---	5215	{ 2238, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2238 = MUL_R6	---
5216	{ 2237, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2237 = MUL_Q_W	---	5216	{ 2237, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2237 = MUL_Q_W	---
5217	{ 2236, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2236 = MUL_Q_H	---	5217	{ 2236, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2236 = MUL_Q_H	---
5218	{ 2235, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5218	{ 2235, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5219	{ 2234, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5219	{ 2234, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5220	{ 2233, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5220	{ 2233, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5221	{ 2232, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	---	5221	{ 2232, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	---
5222	{ 2231, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2231 = MULV_W	---	5222	{ 2231, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2231 = MULV_W	---
5223	{ 2230, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2230 = MULV_H	---	5223	{ 2230, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2230 = MULV_H	---
5224	{ 2229, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2229 = MULV_D	---	5224	{ 2229, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2229 = MULV_D	---
5225	{ 2228, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2228 = MULV_B	---	5225	{ 2228, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2228 = MULV_B	---
5226	{ 2227, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5226	{ 2227, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5227	{ 2226, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5227	{ 2226, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5228	{ 2225, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5228	{ 2225, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5229	{ 2224, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5229	{ 2224, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5230	{ 2223, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5230	{ 2223, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5231	{ 2222, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---	5231	{ 2222, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---
5232	{ 2221, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---	5232	{ 2221, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---
5233	{ 2220, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---	5233	{ 2220, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---
5234	{ 2219, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---	5234	{ 2219, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---
5235	{ 2218, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---	5235	{ 2218, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 136, 0\|(1ULL<	---
5236	{ 2217, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2217 = MULSA_W_PH_MMR2	---	5236	{ 2217, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2217 = MULSA_W_PH_MMR2	---
5237	{ 2216, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2216 = MULSA_W_PH	---	5237	{ 2216, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2216 = MULSA_W_PH	---
5238	{ 2215, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5238	{ 2215, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5239	{ 2214, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5239	{ 2214, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5240	{ 2213, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2213 = MULR_Q_W	---	5240	{ 2213, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2213 = MULR_Q_W	---
5241	{ 2212, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2212 = MULR_Q_H	---	5241	{ 2212, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2212 = MULR_Q_H	---
5242	{ 2211, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5242	{ 2211, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5243	{ 2210, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---	5243	{ 2210, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---
5244	{ 2209, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---	5244	{ 2209, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---
5245	{ 2208, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5245	{ 2208, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5246	{ 2207, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5246	{ 2207, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5247	{ 2206, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---	5247	{ 2206, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---
5248	{ 2205, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---	5248	{ 2205, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 222, 0\|(1ULL<	---
5249	{ 2204, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5249	{ 2204, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5250	{ 2203, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5250	{ 2203, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5251	{ 2202, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5251	{ 2202, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5252	{ 2201, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5252	{ 2201, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5253	{ 2200, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5253	{ 2200, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5254	{ 2199, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---	5254	{ 2199, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 529, 0\|(1ULL<	---
5255	{ 2198, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---	5255	{ 2198, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---
5256	{ 2197, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---	5256	{ 2197, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---
5257	{ 2196, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---	5257	{ 2196, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---
5258	{ 2195, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---	5258	{ 2195, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 647, 0\|(1ULL<	---
5259	{ 2194, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	---	5259	{ 2194, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 222, 0\|(1ULL<	---
5260	{ 2193, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5260	{ 2193, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5261	{ 2192, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5261	{ 2192, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5262	{ 2191, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2191 = MUHU	---	5262	{ 2191, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2191 = MUHU	---
5263	{ 2190, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2190 = MUH	---	5263	{ 2190, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2190 = MUH	---
5264	{ 2189, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	---	5264	{ 2189, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	---
5265	{ 2188, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 302, 0\|(1ULL<	---	5265	{ 2188, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 302, 0\|(1ULL<	---
5266	{ 2187, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 302, 0\|(1ULL<	---	5266	{ 2187, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 302, 0\|(1ULL<	---
5267	{ 2186, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 302, 0\|(1ULL<	---	5267	{ 2186, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 302, 0\|(1ULL<	---
5268	{ 2185, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 302, 0\|(1ULL<	---	5268	{ 2185, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 302, 0\|(1ULL<	---
5269	{ 2184, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 302, 0\|(1ULL<	---	5269	{ 2184, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 302, 0\|(1ULL<	---
5270	{ 2183, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 302, 0\|(1ULL<	---	5270	{ 2183, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 302, 0\|(1ULL<	---
5271	{ 2182, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	---	5271	{ 2182, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	---
5272	{ 2181, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	---	5272	{ 2181, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	---
5273	{ 2180, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	---	5273	{ 2180, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1024, 0\|(1ULL<	---
5274	{ 2179, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 302, 0\|(1ULL<	---	5274	{ 2179, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 302, 0\|(1ULL<	---
5275	{ 2178, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	---	5275	{ 2178, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 181, 0\|(1ULL<	---
5276	{ 2177, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	---	5276	{ 2177, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	---
5277	{ 2176, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	---	5277	{ 2176, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1021, 0\|(1ULL<	---
5278	{ 2175, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	---	5278	{ 2175, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	---
5279	{ 2174, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	---	5279	{ 2174, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	---
5280	{ 2173, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	---	5280	{ 2173, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1019, 0\|(1ULL<	---
5281	{ 2172, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 302, 0\|(1ULL<	---	5281	{ 2172, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 302, 0\|(1ULL<	---
5282	{ 2171, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	---	5282	{ 2171, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 181, 0\|(1ULL<	---
5283	{ 2170, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5283	{ 2170, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5284	{ 2169, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5284	{ 2169, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5285	{ 2168, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---	5285	{ 2168, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---
5286	{ 2167, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	---	5286	{ 2167, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	---
5287	{ 2166, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	---	5287	{ 2166, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1016, 0\|(1ULL<	---
5288	{ 2165, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	---	5288	{ 2165, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	---
5289	{ 2164, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	---	5289	{ 2164, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1013, 0\|(1ULL<	---
5290	{ 2163, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5290	{ 2163, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5291	{ 2162, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5291	{ 2162, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5292	{ 2161, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5292	{ 2161, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5293	{ 2160, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---	5293	{ 2160, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---
5294	{ 2159, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1010, 0\|(1ULL<	---	5294	{ 2159, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1010, 0\|(1ULL<	---
5295	{ 2158, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	5295	{ 2158, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
5296	{ 2157, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	5296	{ 2157, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
5297	{ 2156, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---	5297	{ 2156, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---
5298	{ 2155, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---	5298	{ 2155, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---
5299	{ 2154, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	5299	{ 2154, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
5300	{ 2153, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5300	{ 2153, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5301	{ 2152, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	5301	{ 2152, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
5302	{ 2151, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	---	5302	{ 2151, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	---
5303	{ 2150, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2150 = MSUB_S	---	5303	{ 2150, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2150 = MSUB_S	---
5304	{ 2149, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2149 = MSUB_Q_W	---	5304	{ 2149, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2149 = MSUB_Q_W	---
5305	{ 2148, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUB_Q_H	---	5305	{ 2148, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUB_Q_H	---
5306	{ 2147, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5306	{ 2147, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5307	{ 2146, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2146 = MSUB_DSP_MM	---	5307	{ 2146, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2146 = MSUB_DSP_MM	---
5308	{ 2145, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2145 = MSUB_DSP	---	5308	{ 2145, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2145 = MSUB_DSP	---
5309	{ 2144, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2144 = MSUB_D64	---	5309	{ 2144, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2144 = MSUB_D64	---
5310	{ 2143, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	---	5310	{ 2143, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	---
5311	{ 2142, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2142 = MSUB_D32	---	5311	{ 2142, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #2142 = MSUB_D32	---
5312	{ 2141, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2141 = MSUBV_W	---	5312	{ 2141, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2141 = MSUBV_W	---
5313	{ 2140, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2140 = MSUBV_H	---	5313	{ 2140, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2140 = MSUBV_H	---
5314	{ 2139, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2139 = MSUBV_D	---	5314	{ 2139, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #2139 = MSUBV_D	---
5315	{ 2138, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2138 = MSUBV_B	---	5315	{ 2138, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2138 = MSUBV_B	---
5316	{ 2137, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5316	{ 2137, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5317	{ 2136, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2136 = MSUBU_DSP_MM	---	5317	{ 2136, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2136 = MSUBU_DSP_MM	---
5318	{ 2135, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2135 = MSUBU_DSP	---	5318	{ 2135, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #2135 = MSUBU_DSP	---
5319	{ 2134, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5319	{ 2134, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5320	{ 2133, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2133 = MSUBR_Q_W	---	5320	{ 2133, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2133 = MSUBR_Q_W	---
5321	{ 2132, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2132 = MSUBR_Q_H	---	5321	{ 2132, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2132 = MSUBR_Q_H	---
5322	{ 2131, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---	5322	{ 2131, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---
5323	{ 2130, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---	5323	{ 2130, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---
5324	{ 2129, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---	5324	{ 2129, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---
5325	{ 2128, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---	5325	{ 2128, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---
5326	{ 2127, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5326	{ 2127, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5327	{ 2126, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2126 = MOVZ_I_S_MM	---	5327	{ 2126, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2126 = MOVZ_I_S_MM	---
5328	{ 2125, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2125 = MOVZ_I_S	---	5328	{ 2125, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2125 = MOVZ_I_S	---
5329	{ 2124, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2124 = MOVZ_I_MM	---	5329	{ 2124, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2124 = MOVZ_I_MM	---
5330	{ 2123, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2123 = MOVZ_I_I64	---	5330	{ 2123, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2123 = MOVZ_I_I64	---
5331	{ 2122, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2122 = MOVZ_I_I	---	5331	{ 2122, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2122 = MOVZ_I_I	---
5332	{ 2121, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2121 = MOVZ_I_D64	---	5332	{ 2121, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2121 = MOVZ_I_D64	---
5333	{ 2120, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2120 = MOVZ_I_D32_MM	---	5333	{ 2120, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2120 = MOVZ_I_D32_MM	---
5334	{ 2119, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2119 = MOVZ_I_D32	---	5334	{ 2119, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2119 = MOVZ_I_D32	---
5335	{ 2118, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2118 = MOVZ_I64_S	---	5335	{ 2118, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2118 = MOVZ_I64_S	---
5336	{ 2117, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2117 = MOVZ_I64_I64	---	5336	{ 2117, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2117 = MOVZ_I64_I64	---
5337	{ 2116, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2116 = MOVZ_I64_I	---	5337	{ 2116, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2116 = MOVZ_I64_I	---
5338	{ 2115, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2115 = MOVZ_I64_D64	---	5338	{ 2115, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2115 = MOVZ_I64_D64	---
5339	{ 2114, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2114 = MOVT_S_MM	---	5339	{ 2114, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2114 = MOVT_S_MM	---
5340	{ 2113, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2113 = MOVT_S	---	5340	{ 2113, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2113 = MOVT_S	---
5341	{ 2112, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2112 = MOVT_I_MM	---	5341	{ 2112, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2112 = MOVT_I_MM	---
5342	{ 2111, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2111 = MOVT_I64	---	5342	{ 2111, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2111 = MOVT_I64	---
5343	{ 2110, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2110 = MOVT_I	---	5343	{ 2110, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2110 = MOVT_I	---
5344	{ 2109, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2109 = MOVT_D64	---	5344	{ 2109, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2109 = MOVT_D64	---
5345	{ 2108, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2108 = MOVT_D32_MM	---	5345	{ 2108, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2108 = MOVT_D32_MM	---
5346	{ 2107, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2107 = MOVT_D32	---	5346	{ 2107, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2107 = MOVT_D32	---
5347	{ 2106, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2106 = MOVN_I_S_MM	---	5347	{ 2106, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2106 = MOVN_I_S_MM	---
5348	{ 2105, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2105 = MOVN_I_S	---	5348	{ 2105, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2105 = MOVN_I_S	---
5349	{ 2104, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2104 = MOVN_I_MM	---	5349	{ 2104, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2104 = MOVN_I_MM	---
5350	{ 2103, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2103 = MOVN_I_I64	---	5350	{ 2103, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2103 = MOVN_I_I64	---
5351	{ 2102, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2102 = MOVN_I_I	---	5351	{ 2102, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2102 = MOVN_I_I	---
5352	{ 2101, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2101 = MOVN_I_D64	---	5352	{ 2101, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2101 = MOVN_I_D64	---
5353	{ 2100, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2100 = MOVN_I_D32_MM	---	5353	{ 2100, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2100 = MOVN_I_D32_MM	---
5354	{ 2099, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2099 = MOVN_I_D32	---	5354	{ 2099, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2099 = MOVN_I_D32	---
5355	{ 2098, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2098 = MOVN_I64_S	---	5355	{ 2098, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2098 = MOVN_I64_S	---
5356	{ 2097, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2097 = MOVN_I64_I64	---	5356	{ 2097, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2097 = MOVN_I64_I64	---
5357	{ 2096, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2096 = MOVN_I64_I	---	5357	{ 2096, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2096 = MOVN_I64_I	---
5358	{ 2095, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2095 = MOVN_I64_D64	---	5358	{ 2095, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2095 = MOVN_I64_D64	---
5359	{ 2094, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2094 = MOVF_S_MM	---	5359	{ 2094, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2094 = MOVF_S_MM	---
5360	{ 2093, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2093 = MOVF_S	---	5360	{ 2093, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2093 = MOVF_S	---
5361	{ 2092, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2092 = MOVF_I_MM	---	5361	{ 2092, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2092 = MOVF_I_MM	---
5362	{ 2091, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2091 = MOVF_I64	---	5362	{ 2091, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2091 = MOVF_I64	---
5363	{ 2090, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2090 = MOVF_I	---	5363	{ 2090, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2090 = MOVF_I	---
5364	{ 2089, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2089 = MOVF_D64	---	5364	{ 2089, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2089 = MOVF_D64	---
5365	{ 2088, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2088 = MOVF_D32_MM	---	5365	{ 2088, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2088 = MOVF_D32_MM	---
5366	{ 2087, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2087 = MOVF_D32	---	5366	{ 2087, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 954, 0, 0x4ULL }, // Inst #2087 = MOVF_D32	---
5367	{ 2086, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 952, 0\|(1ULL<	---	5367	{ 2086, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 952, 0\|(1ULL<	---
5368	{ 2085, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	---	5368	{ 2085, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	---
5369	{ 2084, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	---	5369	{ 2084, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 948, 0\|(1ULL<	---
5370	{ 2083, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	5370	{ 2083, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
5371	{ 2082, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	5371	{ 2082, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
5372	{ 2081, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2081 = MOD_U_W	---	5372	{ 2081, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2081 = MOD_U_W	---
5373	{ 2080, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2080 = MOD_U_H	---	5373	{ 2080, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2080 = MOD_U_H	---
5374	{ 2079, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2079 = MOD_U_D	---	5374	{ 2079, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2079 = MOD_U_D	---
5375	{ 2078, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2078 = MOD_U_B	---	5375	{ 2078, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2078 = MOD_U_B	---
5376	{ 2077, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2077 = MOD_S_W	---	5376	{ 2077, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2077 = MOD_S_W	---
5377	{ 2076, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2076 = MOD_S_H	---	5377	{ 2076, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2076 = MOD_S_H	---
5378	{ 2075, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2075 = MOD_S_D	---	5378	{ 2075, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2075 = MOD_S_D	---
5379	{ 2074, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2074 = MOD_S_B	---	5379	{ 2074, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2074 = MOD_S_B	---
5380	{ 2073, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5380	{ 2073, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5381	{ 2072, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5381	{ 2072, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5382	{ 2071, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5382	{ 2071, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5383	{ 2070, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2070 = MODSUB_MM	---	5383	{ 2070, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2070 = MODSUB_MM	---
5384	{ 2069, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2069 = MODSUB	---	5384	{ 2069, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 222, 0, 0x6ULL }, // Inst #2069 = MODSUB	---
5385	{ 2068, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5385	{ 2068, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5386	{ 2067, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2067 = MIN_U_W	---	5386	{ 2067, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2067 = MIN_U_W	---
5387	{ 2066, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2066 = MIN_U_H	---	5387	{ 2066, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2066 = MIN_U_H	---
5388	{ 2065, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2065 = MIN_U_D	---	5388	{ 2065, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2065 = MIN_U_D	---
5389	{ 2064, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2064 = MIN_U_B	---	5389	{ 2064, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2064 = MIN_U_B	---
5390	{ 2063, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2063 = MIN_S_W	---	5390	{ 2063, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2063 = MIN_S_W	---
5391	{ 2062, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5391	{ 2062, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5392	{ 2061, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2061 = MIN_S_H	---	5392	{ 2061, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2061 = MIN_S_H	---
5393	{ 2060, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2060 = MIN_S_D	---	5393	{ 2060, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2060 = MIN_S_D	---
5394	{ 2059, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2059 = MIN_S_B	---	5394	{ 2059, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2059 = MIN_S_B	---
5395	{ 2058, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5395	{ 2058, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5396	{ 2057, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5396	{ 2057, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5397	{ 2056, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5397	{ 2056, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5398	{ 2055, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2055 = MIN_A_W	---	5398	{ 2055, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2055 = MIN_A_W	---
5399	{ 2054, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2054 = MIN_A_H	---	5399	{ 2054, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2054 = MIN_A_H	---
5400	{ 2053, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2053 = MIN_A_D	---	5400	{ 2053, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2053 = MIN_A_D	---
5401	{ 2052, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2052 = MIN_A_B	---	5401	{ 2052, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2052 = MIN_A_B	---
5402	{ 2051, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2051 = MINI_U_W	---	5402	{ 2051, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2051 = MINI_U_W	---
5403	{ 2050, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2050 = MINI_U_H	---	5403	{ 2050, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2050 = MINI_U_H	---
5404	{ 2049, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2049 = MINI_U_D	---	5404	{ 2049, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2049 = MINI_U_D	---
5405	{ 2048, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2048 = MINI_U_B	---	5405	{ 2048, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2048 = MINI_U_B	---
5406	{ 2047, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2047 = MINI_S_W	---	5406	{ 2047, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #2047 = MINI_S_W	---
5407	{ 2046, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2046 = MINI_S_H	---	5407	{ 2046, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #2046 = MINI_S_H	---
5408	{ 2045, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2045 = MINI_S_D	---	5408	{ 2045, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #2045 = MINI_S_D	---
5409	{ 2044, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2044 = MINI_S_B	---	5409	{ 2044, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #2044 = MINI_S_B	---
5410	{ 2043, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5410	{ 2043, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5411	{ 2042, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5411	{ 2042, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5412	{ 2041, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5412	{ 2041, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5413	{ 2040, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5413	{ 2040, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5414	{ 2039, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	---	5414	{ 2039, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 943, 0\|(1ULL<	---
5415	{ 2038, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5415	{ 2038, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5416	{ 2037, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2037 = MFLO_DSP_MM	---	5416	{ 2037, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2037 = MFLO_DSP_MM	---
5417	{ 2036, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---	5417	{ 2036, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---
5418	{ 2035, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	---	5418	{ 2035, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	---
5419	{ 2034, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5419	{ 2034, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5420	{ 2033, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5420	{ 2033, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5421	{ 2032, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5421	{ 2032, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5422	{ 2031, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2031 = MFHI_DSP_MM	---	5422	{ 2031, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 366, 0, 0x6ULL }, // Inst #2031 = MFHI_DSP_MM	---
5423	{ 2030, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---	5423	{ 2030, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---
5424	{ 2029, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	---	5424	{ 2029, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 302, 0\|(1ULL<	---
5425	{ 2028, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5425	{ 2028, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5426	{ 2027, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---	5426	{ 2027, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 181, 0\|(1ULL<	---
5427	{ 2026, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5427	{ 2026, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5428	{ 2025, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5428	{ 2025, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5429	{ 2024, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---	5429	{ 2024, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---
5430	{ 2023, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---	5430	{ 2023, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---
5431	{ 2022, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---	5431	{ 2022, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---
5432	{ 2021, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	---	5432	{ 2021, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	---
5433	{ 2020, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	---	5433	{ 2020, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 941, 0\|(1ULL<	---
5434	{ 2019, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5434	{ 2019, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5435	{ 2018, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5435	{ 2018, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5436	{ 2017, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5436	{ 2017, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5437	{ 2016, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---	5437	{ 2016, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---
5438	{ 2015, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 938, 0\|(1ULL<	---	5438	{ 2015, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 938, 0\|(1ULL<	---
5439	{ 2014, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---	5439	{ 2014, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---
5440	{ 2013, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---	5440	{ 2013, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---
5441	{ 2012, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---	5441	{ 2012, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 936, 0\|(1ULL<	---
5442	{ 2011, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---	5442	{ 2011, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---
5443	{ 2010, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5443	{ 2010, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5444	{ 2009, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	5444	{ 2009, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
5445	{ 2008, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2008 = MAX_U_W	---	5445	{ 2008, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2008 = MAX_U_W	---
5446	{ 2007, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2007 = MAX_U_H	---	5446	{ 2007, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2007 = MAX_U_H	---
5447	{ 2006, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2006 = MAX_U_D	---	5447	{ 2006, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2006 = MAX_U_D	---
5448	{ 2005, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2005 = MAX_U_B	---	5448	{ 2005, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2005 = MAX_U_B	---
5449	{ 2004, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2004 = MAX_S_W	---	5449	{ 2004, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #2004 = MAX_S_W	---
5450	{ 2003, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5450	{ 2003, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5451	{ 2002, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2002 = MAX_S_H	---	5451	{ 2002, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #2002 = MAX_S_H	---
5452	{ 2001, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2001 = MAX_S_D	---	5452	{ 2001, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #2001 = MAX_S_D	---
5453	{ 2000, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2000 = MAX_S_B	---	5453	{ 2000, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2000 = MAX_S_B	---
5454	{ 1999, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5454	{ 1999, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5455	{ 1998, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5455	{ 1998, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5456	{ 1997, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5456	{ 1997, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5457	{ 1996, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1996 = MAX_A_W	---	5457	{ 1996, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1996 = MAX_A_W	---
5458	{ 1995, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1995 = MAX_A_H	---	5458	{ 1995, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1995 = MAX_A_H	---
5459	{ 1994, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1994 = MAX_A_D	---	5459	{ 1994, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1994 = MAX_A_D	---
5460	{ 1993, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1993 = MAX_A_B	---	5460	{ 1993, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1993 = MAX_A_B	---
5461	{ 1992, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1992 = MAXI_U_W	---	5461	{ 1992, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1992 = MAXI_U_W	---
5462	{ 1991, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1991 = MAXI_U_H	---	5462	{ 1991, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1991 = MAXI_U_H	---
5463	{ 1990, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1990 = MAXI_U_D	---	5463	{ 1990, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1990 = MAXI_U_D	---
5464	{ 1989, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1989 = MAXI_U_B	---	5464	{ 1989, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1989 = MAXI_U_B	---
5465	{ 1988, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1988 = MAXI_S_W	---	5465	{ 1988, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1988 = MAXI_S_W	---
5466	{ 1987, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1987 = MAXI_S_H	---	5466	{ 1987, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1987 = MAXI_S_H	---
5467	{ 1986, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1986 = MAXI_S_D	---	5467	{ 1986, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1986 = MAXI_S_D	---
5468	{ 1985, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1985 = MAXI_S_B	---	5468	{ 1985, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1985 = MAXI_S_B	---
5469	{ 1984, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5469	{ 1984, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5470	{ 1983, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5470	{ 1983, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5471	{ 1982, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5471	{ 1982, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5472	{ 1981, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5472	{ 1981, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5473	{ 1980, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5473	{ 1980, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5474	{ 1979, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5474	{ 1979, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5475	{ 1978, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5475	{ 1978, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5476	{ 1977, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5476	{ 1977, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5477	{ 1976, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5477	{ 1976, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5478	{ 1975, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5478	{ 1975, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5479	{ 1974, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5479	{ 1974, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5480	{ 1973, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5480	{ 1973, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5481	{ 1972, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	---	5481	{ 1972, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 932, 0\|(1ULL<	---
5482	{ 1971, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1971 = MADD_S	---	5482	{ 1971, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1971 = MADD_S	---
5483	{ 1970, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1970 = MADD_Q_W	---	5483	{ 1970, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1970 = MADD_Q_W	---
5484	{ 1969, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADD_Q_H	---	5484	{ 1969, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADD_Q_H	---
5485	{ 1968, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5485	{ 1968, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5486	{ 1967, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1967 = MADD_DSP_MM	---	5486	{ 1967, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1967 = MADD_DSP_MM	---
5487	{ 1966, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1966 = MADD_DSP	---	5487	{ 1966, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1966 = MADD_DSP	---
5488	{ 1965, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1965 = MADD_D64	---	5488	{ 1965, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1965 = MADD_D64	---
5489	{ 1964, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	---	5489	{ 1964, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 924, 0\|(1ULL<	---
5490	{ 1963, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #1963 = MADD_D32	---	5490	{ 1963, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 924, 0, 0x4ULL }, // Inst #1963 = MADD_D32	---
5491	{ 1962, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1962 = MADDV_W	---	5491	{ 1962, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1962 = MADDV_W	---
5492	{ 1961, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1961 = MADDV_H	---	5492	{ 1961, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1961 = MADDV_H	---
5493	{ 1960, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1960 = MADDV_D	---	5493	{ 1960, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1960 = MADDV_D	---
5494	{ 1959, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1959 = MADDV_B	---	5494	{ 1959, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1959 = MADDV_B	---
5495	{ 1958, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5495	{ 1958, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5496	{ 1957, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1957 = MADDU_DSP_MM	---	5496	{ 1957, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1957 = MADDU_DSP_MM	---
5497	{ 1956, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1956 = MADDU_DSP	---	5497	{ 1956, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1956 = MADDU_DSP	---
5498	{ 1955, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5498	{ 1955, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5499	{ 1954, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1954 = MADDR_Q_W	---	5499	{ 1954, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1954 = MADDR_Q_W	---
5500	{ 1953, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1953 = MADDR_Q_H	---	5500	{ 1953, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1953 = MADDR_Q_H	---
5501	{ 1952, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---	5501	{ 1952, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---
5502	{ 1951, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---	5502	{ 1951, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 920, 0\|(1ULL<	---
5503	{ 1950, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---	5503	{ 1950, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---
5504	{ 1949, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---	5504	{ 1949, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 916, 0\|(1ULL<	---
5505	{ 1948, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---	5505	{ 1948, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 136, 0\|(1ULL<	---
5506	{ 1947, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	---	5506	{ 1947, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 569, 0\|(1ULL<	---
5507	{ 1946, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	5507	{ 1946, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
5508	{ 1945, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	---	5508	{ 1945, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	---
5509	{ 1944, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	---	5509	{ 1944, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 913, 0\|(1ULL<	---
5510	{ 1943, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0, 0x0ULL }, // Inst #1943 = LiRxImmX16	---	5510	{ 1943, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0, 0x0ULL }, // Inst #1943 = LiRxImmX16	---
5511	{ 1942, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---	5511	{ 1942, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---
5512	{ 1941, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---	5512	{ 1941, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---
5513	{ 1940, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	5513	{ 1940, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
5514	{ 1939, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	5514	{ 1939, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
5515	{ 1938, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	5515	{ 1938, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
5516	{ 1937, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---	5516	{ 1937, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 910, 0\|(1ULL<	---
5517	{ 1936, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5517	{ 1936, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5518	{ 1935, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5518	{ 1935, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5519	{ 1934, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5519	{ 1934, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5520	{ 1933, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5520	{ 1933, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5521	{ 1932, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5521	{ 1932, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5522	{ 1931, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---	5522	{ 1931, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---
5523	{ 1930, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---	5523	{ 1930, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 907, 0\|(1ULL<	---
5524	{ 1929, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5524	{ 1929, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5525	{ 1928, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5525	{ 1928, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5526	{ 1927, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5526	{ 1927, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5527	{ 1926, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---	5527	{ 1926, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 904, 0\|(1ULL<	---
5528	{ 1925, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5528	{ 1925, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5529	{ 1924, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5529	{ 1924, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5530	{ 1923, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5530	{ 1923, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5531	{ 1922, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---	5531	{ 1922, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---
5532	{ 1921, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5532	{ 1921, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5533	{ 1920, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	---	5533	{ 1920, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 900, 0\|(1ULL<	---
5534	{ 1919, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5534	{ 1919, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5535	{ 1918, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5535	{ 1918, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5536	{ 1917, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---	5536	{ 1917, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---
5537	{ 1916, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---	5537	{ 1916, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---
5538	{ 1915, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---	5538	{ 1915, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 897, 0\|(1ULL<	---
5539	{ 1914, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5539	{ 1914, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5540	{ 1913, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5540	{ 1913, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5541	{ 1912, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5541	{ 1912, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5542	{ 1911, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---	5542	{ 1911, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---
5543	{ 1910, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---	5543	{ 1910, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 893, 0\|(1ULL<	---
5544	{ 1909, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 890, 0\|(1ULL<	---	5544	{ 1909, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 890, 0\|(1ULL<	---
5545	{ 1908, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5545	{ 1908, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5546	{ 1907, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5546	{ 1907, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5547	{ 1906, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---	5547	{ 1906, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---
5548	{ 1905, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---	5548	{ 1905, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 887, 0\|(1ULL<	---
5549	{ 1904, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---	5549	{ 1904, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---
5550	{ 1903, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5550	{ 1903, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5551	{ 1902, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---	5551	{ 1902, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---
5552	{ 1901, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5552	{ 1901, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5553	{ 1900, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---	5553	{ 1900, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---
5554	{ 1899, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---	5554	{ 1899, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 884, 0\|(1ULL<	---
5555	{ 1898, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5555	{ 1898, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5556	{ 1897, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---	5556	{ 1897, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---
5557	{ 1896, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5557	{ 1896, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5558	{ 1895, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5558	{ 1895, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5559	{ 1894, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	5559	{ 1894, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
5560	{ 1893, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5560	{ 1893, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5561	{ 1892, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	5561	{ 1892, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
5562	{ 1891, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	5562	{ 1891, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
5563	{ 1890, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---	5563	{ 1890, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---
5564	{ 1889, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5564	{ 1889, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5565	{ 1888, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---	5565	{ 1888, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---
5566	{ 1887, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---	5566	{ 1887, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---
5567	{ 1886, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 553, 0, 0x6ULL }, // Inst #1886 = LSA	---	5567	{ 1886, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 553, 0, 0x6ULL }, // Inst #1886 = LSA	---
5568	{ 1885, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	---	5568	{ 1885, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	---
5569	{ 1884, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5569	{ 1884, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5570	{ 1883, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5570	{ 1883, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5571	{ 1882, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5571	{ 1882, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5572	{ 1881, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5572	{ 1881, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5573	{ 1880, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 881, 0\|(1ULL<	---	5573	{ 1880, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 881, 0\|(1ULL<	---
5574	{ 1879, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5574	{ 1879, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5575	{ 1878, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	---	5575	{ 1878, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 878, 0\|(1ULL<	---
5576	{ 1877, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5576	{ 1877, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5577	{ 1876, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5577	{ 1876, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5578	{ 1875, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---	5578	{ 1875, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---
5579	{ 1874, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---	5579	{ 1874, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---
5580	{ 1873, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5580	{ 1873, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5581	{ 1872, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5581	{ 1872, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5582	{ 1871, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5582	{ 1871, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5583	{ 1870, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5583	{ 1870, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5584	{ 1869, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5584	{ 1869, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5585	{ 1868, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5585	{ 1868, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5586	{ 1867, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5586	{ 1867, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5587	{ 1866, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5587	{ 1866, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5588	{ 1865, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---	5588	{ 1865, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---
5589	{ 1864, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5589	{ 1864, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5590	{ 1863, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5590	{ 1863, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5591	{ 1862, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5591	{ 1862, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5592	{ 1861, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5592	{ 1861, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5593	{ 1860, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1860 = LEA_ADDiu_MM	---	5593	{ 1860, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1860 = LEA_ADDiu_MM	---
5594	{ 1859, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 352, 0, 0x2ULL }, // Inst #1859 = LEA_ADDiu64	---	5594	{ 1859, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 352, 0, 0x2ULL }, // Inst #1859 = LEA_ADDiu64	---
5595	{ 1858, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1858 = LEA_ADDiu	---	5595	{ 1858, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 303, 0, 0x2ULL }, // Inst #1858 = LEA_ADDiu	---
5596	{ 1857, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	---	5596	{ 1857, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 875, 0\|(1ULL<	---
5597	{ 1856, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	---	5597	{ 1856, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 872, 0\|(1ULL<	---
5598	{ 1855, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	---	5598	{ 1855, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 869, 0\|(1ULL<	---
5599	{ 1854, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	---	5599	{ 1854, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 866, 0\|(1ULL<	---
5600	{ 1853, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---	5600	{ 1853, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 863, 0\|(1ULL<	---
5601	{ 1852, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---	5601	{ 1852, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 860, 0\|(1ULL<	---
5602	{ 1851, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---	5602	{ 1851, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---
5603	{ 1850, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	5603	{ 1850, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
5604	{ 1849, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---	5604	{ 1849, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 856, 0\|(1ULL<	---
5605	{ 1848, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0\|(1ULL<	---	5605	{ 1848, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0\|(1ULL<	---
5606	{ 1847, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0\|(1ULL<	---	5606	{ 1847, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0\|(1ULL<	---
5607	{ 1846, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 850, 0\|(1ULL<	---	5607	{ 1846, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 850, 0\|(1ULL<	---
5608	{ 1845, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 848, 0\|(1ULL<	---	5608	{ 1845, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 848, 0\|(1ULL<	---
5609	{ 1844, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---	5609	{ 1844, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 845, 0\|(1ULL<	---
5610	{ 1843, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5610	{ 1843, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5611	{ 1842, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---	5611	{ 1842, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 842, 0\|(1ULL<	---
5612	{ 1841, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---	5612	{ 1841, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 839, 0\|(1ULL<	---
5613	{ 1840, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5613	{ 1840, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5614	{ 1839, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---	5614	{ 1839, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---
5615	{ 1838, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5615	{ 1838, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5616	{ 1837, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---	5616	{ 1837, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 836, 0\|(1ULL<	---
5617	{ 1836, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---	5617	{ 1836, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---
5618	{ 1835, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5618	{ 1835, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5619	{ 1834, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5619	{ 1834, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5620	{ 1833, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5620	{ 1833, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5621	{ 1832, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5621	{ 1832, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5622	{ 1831, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5622	{ 1831, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5623	{ 1830, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5623	{ 1830, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5624	{ 1829, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5624	{ 1829, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5625	{ 1828, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5625	{ 1828, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5626	{ 1827, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5626	{ 1827, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5627	{ 1826, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5627	{ 1826, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5628	{ 1825, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---	5628	{ 1825, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 833, 0\|(1ULL<	---
5629	{ 1824, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---	5629	{ 1824, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 830, 0\|(1ULL<	---
5630	{ 1823, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5630	{ 1823, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5631	{ 1822, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5631	{ 1822, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5632	{ 1821, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	5632	{ 1821, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
5633	{ 1820, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	5633	{ 1820, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
5634	{ 1819, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 829, 0\|(1ULL<	---	5634	{ 1819, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 829, 0\|(1ULL<	---
5635	{ 1818, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 829, 0\|(1ULL<	---	5635	{ 1818, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 829, 0\|(1ULL<	---
5636	{ 1817, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5636	{ 1817, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5637	{ 1816, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5637	{ 1816, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5638	{ 1815, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5638	{ 1815, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5639	{ 1814, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5639	{ 1814, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5640	{ 1813, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---	5640	{ 1813, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---
5641	{ 1812, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5641	{ 1812, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5642	{ 1811, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5642	{ 1811, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5643	{ 1810, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	5643	{ 1810, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
5644	{ 1809, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	5644	{ 1809, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
5645	{ 1808, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5645	{ 1808, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5646	{ 1807, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5646	{ 1807, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5647	{ 1806, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5647	{ 1806, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5648	{ 1805, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5648	{ 1805, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5649	{ 1804, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5649	{ 1804, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5650	{ 1803, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	5650	{ 1803, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
5651	{ 1802, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5651	{ 1802, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5652	{ 1801, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5652	{ 1801, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5653	{ 1800, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	---	5653	{ 1800, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	---
5654	{ 1799, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 350, 0\|(1ULL<	---	5654	{ 1799, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 350, 0\|(1ULL<	---
5655	{ 1798, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	---	5655	{ 1798, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 355, 0\|(1ULL<	---
5656	{ 1797, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	---	5656	{ 1797, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	---
5657	{ 1796, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 350, 0\|(1ULL<	---	5657	{ 1796, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 350, 0\|(1ULL<	---
5658	{ 1795, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	---	5658	{ 1795, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 355, 0\|(1ULL<	---
5659	{ 1794, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5659	{ 1794, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5660	{ 1793, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5660	{ 1793, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5661	{ 1792, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5661	{ 1792, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5662	{ 1791, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5662	{ 1791, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5663	{ 1790, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---	5663	{ 1790, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---
5664	{ 1789, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---	5664	{ 1789, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---
5665	{ 1788, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	5665	{ 1788, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
5666	{ 1787, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---	5666	{ 1787, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---
5667	{ 1786, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---	5667	{ 1786, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---
5668	{ 1785, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---	5668	{ 1785, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---
5669	{ 1784, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	5669	{ 1784, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
5670	{ 1783, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---	5670	{ 1783, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---
5671	{ 1782, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 373, 0\|(1ULL<	---	5671	{ 1782, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 373, 0\|(1ULL<	---
5672	{ 1781, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---	5672	{ 1781, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---
5673	{ 1780, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---	5673	{ 1780, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 136, 0\|(1ULL<	---
5674	{ 1779, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	5674	{ 1779, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
5675	{ 1778, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---	5675	{ 1778, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---
5676	{ 1777, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 785, 0, 0x1ULL }, // Inst #1777 = INS_MMR6	---	5676	{ 1777, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 785, 0, 0x1ULL }, // Inst #1777 = INS_MMR6	---
5677	{ 1776, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	---	5677	{ 1776, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	---
5678	{ 1775, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	---	5678	{ 1775, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	---
5679	{ 1774, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 824, 0, 0x6ULL }, // Inst #1774 = INSVE_W	---	5679	{ 1774, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 824, 0, 0x6ULL }, // Inst #1774 = INSVE_W	---
5680	{ 1773, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 819, 0, 0x6ULL }, // Inst #1773 = INSVE_H	---	5680	{ 1773, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 819, 0, 0x6ULL }, // Inst #1773 = INSVE_H	---
5681	{ 1772, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1772 = INSVE_D	---	5681	{ 1772, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1772 = INSVE_D	---
5682	{ 1771, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 809, 0, 0x6ULL }, // Inst #1771 = INSVE_B	---	5682	{ 1771, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 809, 0, 0x6ULL }, // Inst #1771 = INSVE_B	---
5683	{ 1770, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	---	5683	{ 1770, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 806, 0\|(1ULL<	---
5684	{ 1769, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1769 = INSERT_W	---	5684	{ 1769, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1769 = INSERT_W	---
5685	{ 1768, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1768 = INSERT_H	---	5685	{ 1768, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1768 = INSERT_H	---
5686	{ 1767, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1767 = INSERT_D	---	5686	{ 1767, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1767 = INSERT_D	---
5687	{ 1766, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 790, 0, 0x6ULL }, // Inst #1766 = INSERT_B	---	5687	{ 1766, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 790, 0, 0x6ULL }, // Inst #1766 = INSERT_B	---
5688	{ 1765, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	---	5688	{ 1765, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 785, 0\|(1ULL<	---
5689	{ 1764, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1764 = ILVR_W	---	5689	{ 1764, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1764 = ILVR_W	---
5690	{ 1763, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1763 = ILVR_H	---	5690	{ 1763, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1763 = ILVR_H	---
5691	{ 1762, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1762 = ILVR_D	---	5691	{ 1762, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1762 = ILVR_D	---
5692	{ 1761, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1761 = ILVR_B	---	5692	{ 1761, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1761 = ILVR_B	---
5693	{ 1760, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1760 = ILVOD_W	---	5693	{ 1760, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1760 = ILVOD_W	---
5694	{ 1759, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1759 = ILVOD_H	---	5694	{ 1759, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1759 = ILVOD_H	---
5695	{ 1758, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1758 = ILVOD_D	---	5695	{ 1758, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1758 = ILVOD_D	---
5696	{ 1757, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1757 = ILVOD_B	---	5696	{ 1757, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1757 = ILVOD_B	---
5697	{ 1756, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1756 = ILVL_W	---	5697	{ 1756, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1756 = ILVL_W	---
5698	{ 1755, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1755 = ILVL_H	---	5698	{ 1755, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1755 = ILVL_H	---
5699	{ 1754, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1754 = ILVL_D	---	5699	{ 1754, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1754 = ILVL_D	---
5700	{ 1753, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1753 = ILVL_B	---	5700	{ 1753, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1753 = ILVL_B	---
5701	{ 1752, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1752 = ILVEV_W	---	5701	{ 1752, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1752 = ILVEV_W	---
5702	{ 1751, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1751 = ILVEV_H	---	5702	{ 1751, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1751 = ILVEV_H	---
5703	{ 1750, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1750 = ILVEV_D	---	5703	{ 1750, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1750 = ILVEV_D	---
5704	{ 1749, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1749 = ILVEV_B	---	5704	{ 1749, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1749 = ILVEV_B	---
5705	{ 1748, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5705	{ 1748, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5706	{ 1747, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	5706	{ 1747, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
5707	{ 1746, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1746 = HSUB_U_W	---	5707	{ 1746, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1746 = HSUB_U_W	---
5708	{ 1745, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1745 = HSUB_U_H	---	5708	{ 1745, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1745 = HSUB_U_H	---
5709	{ 1744, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1744 = HSUB_U_D	---	5709	{ 1744, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1744 = HSUB_U_D	---
5710	{ 1743, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1743 = HSUB_S_W	---	5710	{ 1743, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1743 = HSUB_S_W	---
5711	{ 1742, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1742 = HSUB_S_H	---	5711	{ 1742, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1742 = HSUB_S_H	---
5712	{ 1741, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1741 = HSUB_S_D	---	5712	{ 1741, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1741 = HSUB_S_D	---
5713	{ 1740, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1740 = HADD_U_W	---	5713	{ 1740, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1740 = HADD_U_W	---
5714	{ 1739, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1739 = HADD_U_H	---	5714	{ 1739, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1739 = HADD_U_H	---
5715	{ 1738, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1738 = HADD_U_D	---	5715	{ 1738, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1738 = HADD_U_D	---
5716	{ 1737, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1737 = HADD_S_W	---	5716	{ 1737, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 720, 0, 0x6ULL }, // Inst #1737 = HADD_S_W	---
5717	{ 1736, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1736 = HADD_S_H	---	5717	{ 1736, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 717, 0, 0x6ULL }, // Inst #1736 = HADD_S_H	---
5718	{ 1735, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1735 = HADD_S_D	---	5718	{ 1735, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 714, 0, 0x6ULL }, // Inst #1735 = HADD_S_D	---
5719	{ 1734, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5719	{ 1734, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5720	{ 1733, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	5720	{ 1733, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
5721	{ 1732, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5721	{ 1732, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5722	{ 1731, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5722	{ 1731, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5723	{ 1730, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1730 = FTRUNC_U_W	---	5723	{ 1730, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1730 = FTRUNC_U_W	---
5724	{ 1729, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1729 = FTRUNC_U_D	---	5724	{ 1729, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1729 = FTRUNC_U_D	---
5725	{ 1728, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1728 = FTRUNC_S_W	---	5725	{ 1728, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1728 = FTRUNC_S_W	---
5726	{ 1727, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1727 = FTRUNC_S_D	---	5726	{ 1727, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1727 = FTRUNC_S_D	---
5727	{ 1726, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1726 = FTQ_W	---	5727	{ 1726, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1726 = FTQ_W	---
5728	{ 1725, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1725 = FTQ_H	---	5728	{ 1725, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1725 = FTQ_H	---
5729	{ 1724, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1724 = FTINT_U_W	---	5729	{ 1724, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1724 = FTINT_U_W	---
5730	{ 1723, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1723 = FTINT_U_D	---	5730	{ 1723, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1723 = FTINT_U_D	---
5731	{ 1722, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1722 = FTINT_S_W	---	5731	{ 1722, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1722 = FTINT_S_W	---
5732	{ 1721, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1721 = FTINT_S_D	---	5732	{ 1721, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1721 = FTINT_S_D	---
5733	{ 1720, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1720 = FSUN_W	---	5733	{ 1720, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1720 = FSUN_W	---
5734	{ 1719, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1719 = FSUN_D	---	5734	{ 1719, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1719 = FSUN_D	---
5735	{ 1718, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1718 = FSUNE_W	---	5735	{ 1718, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1718 = FSUNE_W	---
5736	{ 1717, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1717 = FSUNE_D	---	5736	{ 1717, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1717 = FSUNE_D	---
5737	{ 1716, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1716 = FSULT_W	---	5737	{ 1716, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1716 = FSULT_W	---
5738	{ 1715, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1715 = FSULT_D	---	5738	{ 1715, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1715 = FSULT_D	---
5739	{ 1714, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1714 = FSULE_W	---	5739	{ 1714, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1714 = FSULE_W	---
5740	{ 1713, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1713 = FSULE_D	---	5740	{ 1713, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1713 = FSULE_D	---
5741	{ 1712, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1712 = FSUEQ_W	---	5741	{ 1712, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1712 = FSUEQ_W	---
5742	{ 1711, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1711 = FSUEQ_D	---	5742	{ 1711, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1711 = FSUEQ_D	---
5743	{ 1710, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1710 = FSUB_W	---	5743	{ 1710, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1710 = FSUB_W	---
5744	{ 1709, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1709 = FSUB_S_MMR6	---	5744	{ 1709, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1709 = FSUB_S_MMR6	---
5745	{ 1708, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1708 = FSUB_S_MM	---	5745	{ 1708, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1708 = FSUB_S_MM	---
5746	{ 1707, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1707 = FSUB_S	---	5746	{ 1707, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1707 = FSUB_S	---
5747	{ 1706, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5747	{ 1706, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5748	{ 1705, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1705 = FSUB_D64_MM	---	5748	{ 1705, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1705 = FSUB_D64_MM	---
5749	{ 1704, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1704 = FSUB_D64	---	5749	{ 1704, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1704 = FSUB_D64	---
5750	{ 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1703 = FSUB_D32_MM	---	5750	{ 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1703 = FSUB_D32_MM	---
5751	{ 1702, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1702 = FSUB_D32	---	5751	{ 1702, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1702 = FSUB_D32	---
5752	{ 1701, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1701 = FSUB_D	---	5752	{ 1701, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1701 = FSUB_D	---
5753	{ 1700, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1700 = FSQRT_W	---	5753	{ 1700, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1700 = FSQRT_W	---
5754	{ 1699, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1699 = FSQRT_S_MM	---	5754	{ 1699, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1699 = FSQRT_S_MM	---
5755	{ 1698, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1698 = FSQRT_S	---	5755	{ 1698, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1698 = FSQRT_S	---
5756	{ 1697, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1697 = FSQRT_D64_MM	---	5756	{ 1697, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1697 = FSQRT_D64_MM	---
5757	{ 1696, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1696 = FSQRT_D64	---	5757	{ 1696, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1696 = FSQRT_D64	---
5758	{ 1695, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1695 = FSQRT_D32_MM	---	5758	{ 1695, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1695 = FSQRT_D32_MM	---
5759	{ 1694, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1694 = FSQRT_D32	---	5759	{ 1694, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1694 = FSQRT_D32	---
5760	{ 1693, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1693 = FSQRT_D	---	5760	{ 1693, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1693 = FSQRT_D	---
5761	{ 1692, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1692 = FSOR_W	---	5761	{ 1692, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1692 = FSOR_W	---
5762	{ 1691, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1691 = FSOR_D	---	5762	{ 1691, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1691 = FSOR_D	---
5763	{ 1690, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1690 = FSNE_W	---	5763	{ 1690, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1690 = FSNE_W	---
5764	{ 1689, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1689 = FSNE_D	---	5764	{ 1689, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1689 = FSNE_D	---
5765	{ 1688, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1688 = FSLT_W	---	5765	{ 1688, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1688 = FSLT_W	---
5766	{ 1687, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1687 = FSLT_D	---	5766	{ 1687, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1687 = FSLT_D	---
5767	{ 1686, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1686 = FSLE_W	---	5767	{ 1686, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1686 = FSLE_W	---
5768	{ 1685, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1685 = FSLE_D	---	5768	{ 1685, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1685 = FSLE_D	---
5769	{ 1684, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1684 = FSEQ_W	---	5769	{ 1684, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1684 = FSEQ_W	---
5770	{ 1683, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1683 = FSEQ_D	---	5770	{ 1683, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1683 = FSEQ_D	---
5771	{ 1682, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1682 = FSAF_W	---	5771	{ 1682, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1682 = FSAF_W	---
5772	{ 1681, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1681 = FSAF_D	---	5772	{ 1681, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1681 = FSAF_D	---
5773	{ 1680, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1680 = FRSQRT_W	---	5773	{ 1680, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1680 = FRSQRT_W	---
5774	{ 1679, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1679 = FRSQRT_D	---	5774	{ 1679, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1679 = FRSQRT_D	---
5775	{ 1678, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1678 = FRINT_W	---	5775	{ 1678, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1678 = FRINT_W	---
5776	{ 1677, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1677 = FRINT_D	---	5776	{ 1677, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1677 = FRINT_D	---
5777	{ 1676, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1676 = FRCP_W	---	5777	{ 1676, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1676 = FRCP_W	---
5778	{ 1675, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1675 = FRCP_D	---	5778	{ 1675, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1675 = FRCP_D	---
5779	{ 1674, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	5779	{ 1674, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
5780	{ 1673, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1673 = FNEG_S_MMR6	---	5780	{ 1673, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1673 = FNEG_S_MMR6	---
5781	{ 1672, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1672 = FNEG_S_MM	---	5781	{ 1672, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1672 = FNEG_S_MM	---
5782	{ 1671, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1671 = FNEG_S	---	5782	{ 1671, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1671 = FNEG_S	---
5783	{ 1670, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1670 = FNEG_D64_MM	---	5783	{ 1670, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1670 = FNEG_D64_MM	---
5784	{ 1669, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1669 = FNEG_D64	---	5784	{ 1669, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1669 = FNEG_D64	---
5785	{ 1668, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1668 = FNEG_D32_MM	---	5785	{ 1668, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1668 = FNEG_D32_MM	---
5786	{ 1667, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1667 = FNEG_D32	---	5786	{ 1667, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1667 = FNEG_D32	---
5787	{ 1666, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1666 = FMUL_W	---	5787	{ 1666, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1666 = FMUL_W	---
5788	{ 1665, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5788	{ 1665, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5789	{ 1664, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5789	{ 1664, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5790	{ 1663, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5790	{ 1663, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5791	{ 1662, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5791	{ 1662, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5792	{ 1661, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5792	{ 1661, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5793	{ 1660, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5793	{ 1660, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5794	{ 1659, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---	5794	{ 1659, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---
5795	{ 1658, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---	5795	{ 1658, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---
5796	{ 1657, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1657 = FMUL_D	---	5796	{ 1657, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1657 = FMUL_D	---
5797	{ 1656, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1656 = FMSUB_W	---	5797	{ 1656, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1656 = FMSUB_W	---
5798	{ 1655, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1655 = FMSUB_D	---	5798	{ 1655, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1655 = FMSUB_D	---
5799	{ 1654, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1654 = FMOV_S_MMR6	---	5799	{ 1654, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1654 = FMOV_S_MMR6	---
5800	{ 1653, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	5800	{ 1653, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
5801	{ 1652, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	5801	{ 1652, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
5802	{ 1651, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1651 = FMOV_D_MMR6	---	5802	{ 1651, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1651 = FMOV_D_MMR6	---
5803	{ 1650, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1650 = FMOV_D64_MM	---	5803	{ 1650, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1650 = FMOV_D64_MM	---
5804	{ 1649, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---	5804	{ 1649, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---
5805	{ 1648, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1648 = FMOV_D32_MM	---	5805	{ 1648, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1648 = FMOV_D32_MM	---
5806	{ 1647, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 750, 0\|(1ULL<	---	5806	{ 1647, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 750, 0\|(1ULL<	---
5807	{ 1646, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1646 = FMIN_W	---	5807	{ 1646, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1646 = FMIN_W	---
5808	{ 1645, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1645 = FMIN_D	---	5808	{ 1645, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1645 = FMIN_D	---
5809	{ 1644, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1644 = FMIN_A_W	---	5809	{ 1644, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1644 = FMIN_A_W	---
5810	{ 1643, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1643 = FMIN_A_D	---	5810	{ 1643, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1643 = FMIN_A_D	---
5811	{ 1642, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1642 = FMAX_W	---	5811	{ 1642, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1642 = FMAX_W	---
5812	{ 1641, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1641 = FMAX_D	---	5812	{ 1641, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1641 = FMAX_D	---
5813	{ 1640, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1640 = FMAX_A_W	---	5813	{ 1640, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1640 = FMAX_A_W	---
5814	{ 1639, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1639 = FMAX_A_D	---	5814	{ 1639, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1639 = FMAX_A_D	---
5815	{ 1638, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1638 = FMADD_W	---	5815	{ 1638, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1638 = FMADD_W	---
5816	{ 1637, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1637 = FMADD_D	---	5816	{ 1637, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #1637 = FMADD_D	---
5817	{ 1636, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1636 = FLOOR_W_S_MMR6	---	5817	{ 1636, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1636 = FLOOR_W_S_MMR6	---
5818	{ 1635, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1635 = FLOOR_W_S_MM	---	5818	{ 1635, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1635 = FLOOR_W_S_MM	---
5819	{ 1634, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1634 = FLOOR_W_S	---	5819	{ 1634, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1634 = FLOOR_W_S	---
5820	{ 1633, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1633 = FLOOR_W_MM	---	5820	{ 1633, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1633 = FLOOR_W_MM	---
5821	{ 1632, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1632 = FLOOR_W_D_MMR6	---	5821	{ 1632, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1632 = FLOOR_W_D_MMR6	---
5822	{ 1631, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1631 = FLOOR_W_D64	---	5822	{ 1631, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1631 = FLOOR_W_D64	---
5823	{ 1630, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1630 = FLOOR_W_D32	---	5823	{ 1630, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1630 = FLOOR_W_D32	---
5824	{ 1629, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1629 = FLOOR_L_S_MMR6	---	5824	{ 1629, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1629 = FLOOR_L_S_MMR6	---
5825	{ 1628, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1628 = FLOOR_L_S	---	5825	{ 1628, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1628 = FLOOR_L_S	---
5826	{ 1627, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1627 = FLOOR_L_D_MMR6	---	5826	{ 1627, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1627 = FLOOR_L_D_MMR6	---
5827	{ 1626, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1626 = FLOOR_L_D64	---	5827	{ 1626, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1626 = FLOOR_L_D64	---
5828	{ 1625, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1625 = FLOG2_W	---	5828	{ 1625, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1625 = FLOG2_W	---
5829	{ 1624, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1624 = FLOG2_D	---	5829	{ 1624, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1624 = FLOG2_D	---
5830	{ 1623, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1623 = FILL_W	---	5830	{ 1623, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1623 = FILL_W	---
5831	{ 1622, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1622 = FILL_H	---	5831	{ 1622, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1622 = FILL_H	---
5832	{ 1621, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1621 = FILL_D	---	5832	{ 1621, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1621 = FILL_D	---
5833	{ 1620, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1620 = FILL_B	---	5833	{ 1620, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1620 = FILL_B	---
5834	{ 1619, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1619 = FFQR_W	---	5834	{ 1619, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1619 = FFQR_W	---
5835	{ 1618, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1618 = FFQR_D	---	5835	{ 1618, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1618 = FFQR_D	---
5836	{ 1617, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1617 = FFQL_W	---	5836	{ 1617, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1617 = FFQL_W	---
5837	{ 1616, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1616 = FFQL_D	---	5837	{ 1616, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1616 = FFQL_D	---
5838	{ 1615, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1615 = FFINT_U_W	---	5838	{ 1615, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1615 = FFINT_U_W	---
5839	{ 1614, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1614 = FFINT_U_D	---	5839	{ 1614, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1614 = FFINT_U_D	---
5840	{ 1613, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1613 = FFINT_S_W	---	5840	{ 1613, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1613 = FFINT_S_W	---
5841	{ 1612, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1612 = FFINT_S_D	---	5841	{ 1612, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1612 = FFINT_S_D	---
5842	{ 1611, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1611 = FEXUPR_W	---	5842	{ 1611, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1611 = FEXUPR_W	---
5843	{ 1610, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1610 = FEXUPR_D	---	5843	{ 1610, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1610 = FEXUPR_D	---
5844	{ 1609, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1609 = FEXUPL_W	---	5844	{ 1609, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 775, 0, 0x6ULL }, // Inst #1609 = FEXUPL_W	---
5845	{ 1608, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1608 = FEXUPL_D	---	5845	{ 1608, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 773, 0, 0x6ULL }, // Inst #1608 = FEXUPL_D	---
5846	{ 1607, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1607 = FEXP2_W	---	5846	{ 1607, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1607 = FEXP2_W	---
5847	{ 1606, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1606 = FEXP2_D	---	5847	{ 1606, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1606 = FEXP2_D	---
5848	{ 1605, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1605 = FEXDO_W	---	5848	{ 1605, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 770, 0, 0x6ULL }, // Inst #1605 = FEXDO_W	---
5849	{ 1604, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1604 = FEXDO_H	---	5849	{ 1604, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 767, 0, 0x6ULL }, // Inst #1604 = FEXDO_H	---
5850	{ 1603, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1603 = FDIV_W	---	5850	{ 1603, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1603 = FDIV_W	---
5851	{ 1602, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1602 = FDIV_S_MMR6	---	5851	{ 1602, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 755, 0, 0x6ULL }, // Inst #1602 = FDIV_S_MMR6	---
5852	{ 1601, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1601 = FDIV_S_MM	---	5852	{ 1601, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1601 = FDIV_S_MM	---
5853	{ 1600, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1600 = FDIV_S	---	5853	{ 1600, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 755, 0, 0x4ULL }, // Inst #1600 = FDIV_S	---
5854	{ 1599, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1599 = FDIV_D64_MM	---	5854	{ 1599, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1599 = FDIV_D64_MM	---
5855	{ 1598, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1598 = FDIV_D64	---	5855	{ 1598, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 532, 0, 0x4ULL }, // Inst #1598 = FDIV_D64	---
5856	{ 1597, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1597 = FDIV_D32_MM	---	5856	{ 1597, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1597 = FDIV_D32_MM	---
5857	{ 1596, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1596 = FDIV_D32	---	5857	{ 1596, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 752, 0, 0x4ULL }, // Inst #1596 = FDIV_D32	---
5858	{ 1595, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1595 = FDIV_D	---	5858	{ 1595, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1595 = FDIV_D	---
5859	{ 1594, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5859	{ 1594, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5860	{ 1593, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5860	{ 1593, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5861	{ 1592, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5861	{ 1592, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5862	{ 1591, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5862	{ 1591, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5863	{ 1590, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5863	{ 1590, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5864	{ 1589, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5864	{ 1589, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5865	{ 1588, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5865	{ 1588, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5866	{ 1587, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5866	{ 1587, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5867	{ 1586, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5867	{ 1586, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5868	{ 1585, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5868	{ 1585, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5869	{ 1584, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5869	{ 1584, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5870	{ 1583, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5870	{ 1583, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5871	{ 1582, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5871	{ 1582, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5872	{ 1581, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5872	{ 1581, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5873	{ 1580, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1580 = FCMP_S32_MM	---	5873	{ 1580, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1580 = FCMP_S32_MM	---
5874	{ 1579, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1579 = FCMP_S32	---	5874	{ 1579, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 764, 0, 0x44ULL }, // Inst #1579 = FCMP_S32	---
5875	{ 1578, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 761, 0, 0x44ULL }, // Inst #1578 = FCMP_D64	---	5875	{ 1578, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 761, 0, 0x44ULL }, // Inst #1578 = FCMP_D64	---
5876	{ 1577, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1577 = FCMP_D32_MM	---	5876	{ 1577, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1577 = FCMP_D32_MM	---
5877	{ 1576, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1576 = FCMP_D32	---	5877	{ 1576, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 758, 0, 0x44ULL }, // Inst #1576 = FCMP_D32	---
5878	{ 1575, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1575 = FCLT_W	---	5878	{ 1575, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1575 = FCLT_W	---
5879	{ 1574, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1574 = FCLT_D	---	5879	{ 1574, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1574 = FCLT_D	---
5880	{ 1573, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1573 = FCLE_W	---	5880	{ 1573, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1573 = FCLE_W	---
5881	{ 1572, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1572 = FCLE_D	---	5881	{ 1572, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1572 = FCLE_D	---
5882	{ 1571, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1571 = FCLASS_W	---	5882	{ 1571, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 236, 0, 0x6ULL }, // Inst #1571 = FCLASS_W	---
5883	{ 1570, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1570 = FCLASS_D	---	5883	{ 1570, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 234, 0, 0x6ULL }, // Inst #1570 = FCLASS_D	---
5884	{ 1569, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5884	{ 1569, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5885	{ 1568, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5885	{ 1568, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5886	{ 1567, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5886	{ 1567, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5887	{ 1566, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5887	{ 1566, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5888	{ 1565, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	5888	{ 1565, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
5889	{ 1564, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5889	{ 1564, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5890	{ 1563, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5890	{ 1563, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5891	{ 1562, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---	5891	{ 1562, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 755, 0\|(1ULL<	---
5892	{ 1561, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5892	{ 1561, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5893	{ 1560, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5893	{ 1560, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5894	{ 1559, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	5894	{ 1559, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
5895	{ 1558, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---	5895	{ 1558, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---
5896	{ 1557, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---	5896	{ 1557, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 752, 0\|(1ULL<	---
5897	{ 1556, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	5897	{ 1556, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
5898	{ 1555, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1555 = FABS_S_MM	---	5898	{ 1555, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1555 = FABS_S_MM	---
5899	{ 1554, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1554 = FABS_S	---	5899	{ 1554, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1554 = FABS_S	---
5900	{ 1553, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1553 = FABS_D64_MM	---	5900	{ 1553, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1553 = FABS_D64_MM	---
5901	{ 1552, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1552 = FABS_D64	---	5901	{ 1552, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1552 = FABS_D64	---
5902	{ 1551, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1551 = FABS_D32_MM	---	5902	{ 1551, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1551 = FABS_D32_MM	---
5903	{ 1550, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1550 = FABS_D32	---	5903	{ 1550, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 750, 0, 0x4ULL }, // Inst #1550 = FABS_D32	---
5904	{ 1549, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1549 = EXT_MMR6	---	5904	{ 1549, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1549 = EXT_MMR6	---
5905	{ 1548, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1548 = EXT_MM	---	5905	{ 1548, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1548 = EXT_MM	---
5906	{ 1547, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	---	5906	{ 1547, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	---
5907	{ 1546, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	---	5907	{ 1546, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 635, 0\|(1ULL<	---
5908	{ 1545, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5908	{ 1545, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5909	{ 1544, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5909	{ 1544, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5910	{ 1543, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5910	{ 1543, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5911	{ 1542, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5911	{ 1542, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5912	{ 1541, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5912	{ 1541, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5913	{ 1540, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5913	{ 1540, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5914	{ 1539, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5914	{ 1539, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5915	{ 1538, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---	5915	{ 1538, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 744, 0\|(1ULL<	---
5916	{ 1537, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5916	{ 1537, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5917	{ 1536, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5917	{ 1536, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5918	{ 1535, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5918	{ 1535, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5919	{ 1534, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5919	{ 1534, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5920	{ 1533, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5920	{ 1533, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5921	{ 1532, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5921	{ 1532, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5922	{ 1531, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5922	{ 1531, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5923	{ 1530, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---	5923	{ 1530, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 747, 0\|(1ULL<	---
5924	{ 1529, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	---	5924	{ 1529, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	---
5925	{ 1528, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	---	5925	{ 1528, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	---
5926	{ 1527, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	---	5926	{ 1527, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 747, 0\|(1ULL<	---
5927	{ 1526, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	---	5927	{ 1526, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	---
5928	{ 1525, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	---	5928	{ 1525, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	---
5929	{ 1524, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	---	5929	{ 1524, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 747, 0\|(1ULL<	---
5930	{ 1523, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	---	5930	{ 1523, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 744, 0\|(1ULL<	---
5931	{ 1522, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	---	5931	{ 1522, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 744, 0\|(1ULL<	---
5932	{ 1521, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1521 = EXT	---	5932	{ 1521, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1521 = EXT	---
5933	{ 1520, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5933	{ 1520, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5934	{ 1519, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5934	{ 1519, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5935	{ 1518, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5935	{ 1518, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5936	{ 1517, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5936	{ 1517, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5937	{ 1516, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5937	{ 1516, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5938	{ 1515, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5938	{ 1515, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5939	{ 1514, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5939	{ 1514, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5940	{ 1513, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5940	{ 1513, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5941	{ 1512, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5941	{ 1512, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5942	{ 1511, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5942	{ 1511, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5943	{ 1510, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5943	{ 1510, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5944	{ 1509, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5944	{ 1509, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5945	{ 1508, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5945	{ 1508, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5946	{ 1507, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5946	{ 1507, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5947	{ 1506, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	5947	{ 1506, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
5948	{ 1505, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1505 = DivuRxRy16	---	5948	{ 1505, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1505 = DivuRxRy16	---
5949	{ 1504, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1504 = DivRxRy16	---	5949	{ 1504, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 390, 0, 0x0ULL }, // Inst #1504 = DivRxRy16	---
5950	{ 1503, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5950	{ 1503, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5951	{ 1502, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5951	{ 1502, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5952	{ 1501, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	5952	{ 1501, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
5953	{ 1500, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---	5953	{ 1500, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---
5954	{ 1499, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	5954	{ 1499, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
5955	{ 1498, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	5955	{ 1498, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
5956	{ 1497, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1497 = DSRLV	---	5956	{ 1497, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1497 = DSRLV	---
5957	{ 1496, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	5957	{ 1496, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
5958	{ 1495, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1495 = DSRL	---	5958	{ 1495, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1495 = DSRL	---
5959	{ 1494, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1494 = DSRAV	---	5959	{ 1494, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1494 = DSRAV	---
5960	{ 1493, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	5960	{ 1493, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
5961	{ 1492, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1492 = DSRA	---	5961	{ 1492, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1492 = DSRA	---
5962	{ 1491, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1491 = DSLLV	---	5962	{ 1491, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1491 = DSLLV	---
5963	{ 1490, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	---	5963	{ 1490, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 742, 0\|(1ULL<	---
5964	{ 1489, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	5964	{ 1489, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
5965	{ 1488, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1488 = DSLL	---	5965	{ 1488, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1488 = DSLL	---
5966	{ 1487, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1487 = DSHD	---	5966	{ 1487, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1487 = DSHD	---
5967	{ 1486, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---	5967	{ 1486, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---
5968	{ 1485, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1485 = DSBH	---	5968	{ 1485, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1485 = DSBH	---
5969	{ 1484, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1484 = DROTRV	---	5969	{ 1484, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 739, 0, 0x1ULL }, // Inst #1484 = DROTRV	---
5970	{ 1483, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	5970	{ 1483, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
5971	{ 1482, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1482 = DROTR	---	5971	{ 1482, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 216, 0, 0x1ULL }, // Inst #1482 = DROTR	---
5972	{ 1481, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1481 = DPS_W_PH_MMR2	---	5972	{ 1481, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1481 = DPS_W_PH_MMR2	---
5973	{ 1480, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1480 = DPS_W_PH	---	5973	{ 1480, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1480 = DPS_W_PH	---
5974	{ 1479, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1479 = DPSX_W_PH_MMR2	---	5974	{ 1479, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1479 = DPSX_W_PH_MMR2	---
5975	{ 1478, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1478 = DPSX_W_PH	---	5975	{ 1478, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1478 = DPSX_W_PH	---
5976	{ 1477, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1477 = DPSU_H_QBR_MM	---	5976	{ 1477, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1477 = DPSU_H_QBR_MM	---
5977	{ 1476, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1476 = DPSU_H_QBR	---	5977	{ 1476, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1476 = DPSU_H_QBR	---
5978	{ 1475, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1475 = DPSU_H_QBL_MM	---	5978	{ 1475, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1475 = DPSU_H_QBL_MM	---
5979	{ 1474, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1474 = DPSU_H_QBL	---	5979	{ 1474, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1474 = DPSU_H_QBL	---
5980	{ 1473, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1473 = DPSUB_U_W	---	5980	{ 1473, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1473 = DPSUB_U_W	---
5981	{ 1472, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1472 = DPSUB_U_H	---	5981	{ 1472, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1472 = DPSUB_U_H	---
5982	{ 1471, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1471 = DPSUB_U_D	---	5982	{ 1471, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1471 = DPSUB_U_D	---
5983	{ 1470, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1470 = DPSUB_S_W	---	5983	{ 1470, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1470 = DPSUB_S_W	---
5984	{ 1469, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1469 = DPSUB_S_H	---	5984	{ 1469, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1469 = DPSUB_S_H	---
5985	{ 1468, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1468 = DPSUB_S_D	---	5985	{ 1468, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 723, 0, 0x6ULL }, // Inst #1468 = DPSUB_S_D	---
5986	{ 1467, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5986	{ 1467, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5987	{ 1466, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5987	{ 1466, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5988	{ 1465, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5988	{ 1465, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5989	{ 1464, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5989	{ 1464, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5990	{ 1463, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5990	{ 1463, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5991	{ 1462, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5991	{ 1462, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5992	{ 1461, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5992	{ 1461, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5993	{ 1460, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	5993	{ 1460, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
5994	{ 1459, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1459 = DPOP	---	5994	{ 1459, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1459 = DPOP	---
5995	{ 1458, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1458 = DPA_W_PH_MMR2	---	5995	{ 1458, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1458 = DPA_W_PH_MMR2	---
5996	{ 1457, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1457 = DPA_W_PH	---	5996	{ 1457, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1457 = DPA_W_PH	---
5997	{ 1456, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1456 = DPAX_W_PH_MMR2	---	5997	{ 1456, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1456 = DPAX_W_PH_MMR2	---
5998	{ 1455, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1455 = DPAX_W_PH	---	5998	{ 1455, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1455 = DPAX_W_PH	---
5999	{ 1454, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1454 = DPAU_H_QBR_MM	---	5999	{ 1454, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1454 = DPAU_H_QBR_MM	---
6000	{ 1453, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1453 = DPAU_H_QBR	---	6000	{ 1453, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1453 = DPAU_H_QBR	---
6001	{ 1452, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1452 = DPAU_H_QBL_MM	---	6001	{ 1452, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1452 = DPAU_H_QBL_MM	---
6002	{ 1451, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1451 = DPAU_H_QBL	---	6002	{ 1451, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1451 = DPAU_H_QBL	---
6003	{ 1450, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6003	{ 1450, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6004	{ 1449, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6004	{ 1449, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6005	{ 1448, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6005	{ 1448, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6006	{ 1447, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6006	{ 1447, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6007	{ 1446, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6007	{ 1446, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6008	{ 1445, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6008	{ 1445, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6009	{ 1444, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6009	{ 1444, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6010	{ 1443, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---	6010	{ 1443, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 735, 0\|(1ULL<	---
6011	{ 1442, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	---	6011	{ 1442, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	---
6012	{ 1441, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	---	6012	{ 1441, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	---
6013	{ 1440, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	---	6013	{ 1440, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	---
6014	{ 1439, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	---	6014	{ 1439, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0\|(1ULL<	---
6015	{ 1438, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	---	6015	{ 1438, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0\|(1ULL<	---
6016	{ 1437, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	---	6016	{ 1437, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 723, 0\|(1ULL<	---
6017	{ 1436, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	---	6017	{ 1436, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	---
6018	{ 1435, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	---	6018	{ 1435, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	---
6019	{ 1434, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	---	6019	{ 1434, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	---
6020	{ 1433, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	---	6020	{ 1433, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 720, 0\|(1ULL<	---
6021	{ 1432, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	---	6021	{ 1432, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 717, 0\|(1ULL<	---
6022	{ 1431, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	---	6022	{ 1431, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 714, 0\|(1ULL<	---
6023	{ 1430, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1430 = DMUL_R6	---	6023	{ 1430, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1430 = DMUL_R6	---
6024	{ 1429, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6024	{ 1429, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6025	{ 1428, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---	6025	{ 1428, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---
6026	{ 1427, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---	6026	{ 1427, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 373, 0\|(1ULL<	---
6027	{ 1426, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 219, 0\|(1ULL<	---	6027	{ 1426, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 219, 0\|(1ULL<	---
6028	{ 1425, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1425 = DMUHU	---	6028	{ 1425, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1425 = DMUHU	---
6029	{ 1424, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1424 = DMUH	---	6029	{ 1424, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 219, 0, 0x6ULL }, // Inst #1424 = DMUH	---
6030	{ 1423, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	---	6030	{ 1423, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	---
6031	{ 1422, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	6031	{ 1422, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
6032	{ 1421, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 711, 0\|(1ULL<	---	6032	{ 1421, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 711, 0\|(1ULL<	---
6033	{ 1420, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---	6033	{ 1420, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---
6034	{ 1419, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	---	6034	{ 1419, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 708, 0\|(1ULL<	---
6035	{ 1418, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6035	{ 1418, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6036	{ 1417, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6036	{ 1417, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6037	{ 1416, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6037	{ 1416, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6038	{ 1415, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	---	6038	{ 1415, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	---
6039	{ 1414, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	6039	{ 1414, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
6040	{ 1413, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 705, 0\|(1ULL<	---	6040	{ 1413, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 705, 0\|(1ULL<	---
6041	{ 1412, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 703, 0\|(1ULL<	---	6041	{ 1412, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 703, 0\|(1ULL<	---
6042	{ 1411, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	---	6042	{ 1411, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 700, 0\|(1ULL<	---
6043	{ 1410, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	---	6043	{ 1410, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	---
6044	{ 1409, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0, 0x6ULL }, // Inst #1409 = DLSA	---	6044	{ 1409, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 691, 0, 0x6ULL }, // Inst #1409 = DLSA	---
6045	{ 1408, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6045	{ 1408, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6046	{ 1407, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6046	{ 1407, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6047	{ 1406, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1406 = DIV_U_W	---	6047	{ 1406, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1406 = DIV_U_W	---
6048	{ 1405, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1405 = DIV_U_H	---	6048	{ 1405, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1405 = DIV_U_H	---
6049	{ 1404, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1404 = DIV_U_D	---	6049	{ 1404, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1404 = DIV_U_D	---
6050	{ 1403, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1403 = DIV_U_B	---	6050	{ 1403, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1403 = DIV_U_B	---
6051	{ 1402, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1402 = DIV_S_W	---	6051	{ 1402, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1402 = DIV_S_W	---
6052	{ 1401, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1401 = DIV_S_H	---	6052	{ 1401, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1401 = DIV_S_H	---
6053	{ 1400, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1400 = DIV_S_D	---	6053	{ 1400, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1400 = DIV_S_D	---
6054	{ 1399, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1399 = DIV_S_B	---	6054	{ 1399, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1399 = DIV_S_B	---
6055	{ 1398, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6055	{ 1398, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6056	{ 1397, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6056	{ 1397, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6057	{ 1396, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6057	{ 1396, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6058	{ 1395, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6058	{ 1395, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6059	{ 1394, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---	6059	{ 1394, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---
6060	{ 1393, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---	6060	{ 1393, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---
6061	{ 1392, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---	6061	{ 1392, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 695, 0\|(1ULL<	---
6062	{ 1391, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6062	{ 1391, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6063	{ 1390, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1390 = DEXTU	---	6063	{ 1390, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1390 = DEXTU	---
6064	{ 1389, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1389 = DEXTM	---	6064	{ 1389, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1389 = DEXTM	---
6065	{ 1388, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1388 = DEXT64_32	---	6065	{ 1388, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1388 = DEXT64_32	---
6066	{ 1387, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1387 = DEXT	---	6066	{ 1387, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1387 = DEXT	---
6067	{ 1386, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6067	{ 1386, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6068	{ 1385, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6068	{ 1385, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6069	{ 1384, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6069	{ 1384, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6070	{ 1383, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6070	{ 1383, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6071	{ 1382, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6071	{ 1382, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6072	{ 1381, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1381 = DCLZ_R6	---	6072	{ 1381, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1381 = DCLZ_R6	---
6073	{ 1380, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1380 = DCLZ	---	6073	{ 1380, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1380 = DCLZ	---
6074	{ 1379, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1379 = DCLO_R6	---	6074	{ 1379, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 373, 0, 0x6ULL }, // Inst #1379 = DCLO_R6	---
6075	{ 1378, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1378 = DCLO	---	6075	{ 1378, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 373, 0, 0x1ULL }, // Inst #1378 = DCLO	---
6076	{ 1377, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---	6076	{ 1377, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 373, 0\|(1ULL<	---
6077	{ 1376, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6077	{ 1376, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6078	{ 1375, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	---	6078	{ 1375, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	---
6079	{ 1374, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	---	6079	{ 1374, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 691, 0\|(1ULL<	---
6080	{ 1373, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	---	6080	{ 1373, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 688, 0\|(1ULL<	---
6081	{ 1372, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6081	{ 1372, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6082	{ 1371, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6082	{ 1371, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6083	{ 1370, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6083	{ 1370, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6084	{ 1369, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6084	{ 1369, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6085	{ 1368, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	6085	{ 1368, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
6086	{ 1367, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---	6086	{ 1367, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 564, 0\|(1ULL<	---
6087	{ 1366, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---	6087	{ 1366, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 390, 0\|(1ULL<	---
6088	{ 1365, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6088	{ 1365, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6089	{ 1364, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6089	{ 1364, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6090	{ 1363, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6090	{ 1363, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6091	{ 1362, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6091	{ 1362, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6092	{ 1361, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6092	{ 1361, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6093	{ 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6093	{ 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6094	{ 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6094	{ 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6095	{ 1358, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6095	{ 1358, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6096	{ 1357, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6096	{ 1357, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6097	{ 1356, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6097	{ 1356, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6098	{ 1355, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6098	{ 1355, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6099	{ 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6099	{ 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6100	{ 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6100	{ 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6101	{ 1352, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6101	{ 1352, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6102	{ 1351, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6102	{ 1351, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6103	{ 1350, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6103	{ 1350, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6104	{ 1349, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6104	{ 1349, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6105	{ 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6105	{ 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6106	{ 1347, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6106	{ 1347, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6107	{ 1346, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6107	{ 1346, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6108	{ 1345, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6108	{ 1345, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6109	{ 1344, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6109	{ 1344, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6110	{ 1343, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6110	{ 1343, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6111	{ 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6111	{ 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6112	{ 1341, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6112	{ 1341, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6113	{ 1340, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6113	{ 1340, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6114	{ 1339, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6114	{ 1339, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6115	{ 1338, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6115	{ 1338, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6116	{ 1337, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6116	{ 1337, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6117	{ 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6117	{ 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6118	{ 1335, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6118	{ 1335, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6119	{ 1334, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6119	{ 1334, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6120	{ 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6120	{ 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6121	{ 1332, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6121	{ 1332, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6122	{ 1331, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6122	{ 1331, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6123	{ 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6123	{ 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6124	{ 1329, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6124	{ 1329, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6125	{ 1328, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6125	{ 1328, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6126	{ 1327, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6126	{ 1327, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6127	{ 1326, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6127	{ 1326, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6128	{ 1325, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6128	{ 1325, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6129	{ 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6129	{ 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6130	{ 1323, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6130	{ 1323, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6131	{ 1322, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6131	{ 1322, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6132	{ 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6132	{ 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6133	{ 1320, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6133	{ 1320, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6134	{ 1319, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6134	{ 1319, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6135	{ 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6135	{ 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6136	{ 1317, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6136	{ 1317, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6137	{ 1316, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6137	{ 1316, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6138	{ 1315, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6138	{ 1315, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6139	{ 1314, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6139	{ 1314, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6140	{ 1313, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6140	{ 1313, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6141	{ 1312, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6141	{ 1312, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6142	{ 1311, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6142	{ 1311, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6143	{ 1310, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6143	{ 1310, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6144	{ 1309, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6144	{ 1309, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6145	{ 1308, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6145	{ 1308, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6146	{ 1307, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6146	{ 1307, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6147	{ 1306, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6147	{ 1306, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6148	{ 1305, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6148	{ 1305, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6149	{ 1304, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6149	{ 1304, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6150	{ 1303, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6150	{ 1303, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6151	{ 1302, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6151	{ 1302, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6152	{ 1301, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6152	{ 1301, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6153	{ 1300, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6153	{ 1300, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6154	{ 1299, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6154	{ 1299, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6155	{ 1298, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6155	{ 1298, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6156	{ 1297, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6156	{ 1297, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6157	{ 1296, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6157	{ 1296, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6158	{ 1295, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6158	{ 1295, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6159	{ 1294, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6159	{ 1294, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6160	{ 1293, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6160	{ 1293, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6161	{ 1292, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6161	{ 1292, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6162	{ 1291, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6162	{ 1291, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6163	{ 1290, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6163	{ 1290, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6164	{ 1289, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6164	{ 1289, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6165	{ 1288, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6165	{ 1288, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6166	{ 1287, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6166	{ 1287, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6167	{ 1286, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6167	{ 1286, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6168	{ 1285, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6168	{ 1285, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6169	{ 1284, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6169	{ 1284, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6170	{ 1283, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6170	{ 1283, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6171	{ 1282, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6171	{ 1282, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6172	{ 1281, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6172	{ 1281, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6173	{ 1280, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6173	{ 1280, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6174	{ 1279, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6174	{ 1279, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6175	{ 1278, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6175	{ 1278, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6176	{ 1277, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6176	{ 1277, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6177	{ 1276, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6177	{ 1276, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6178	{ 1275, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6178	{ 1275, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6179	{ 1274, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---	6179	{ 1274, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 685, 0\|(1ULL<	---
6180	{ 1273, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6180	{ 1273, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6181	{ 1272, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---	6181	{ 1272, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 682, 0\|(1ULL<	---
6182	{ 1271, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6182	{ 1271, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6183	{ 1270, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---	6183	{ 1270, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 679, 0\|(1ULL<	---
6184	{ 1269, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1269 = CVT_W_S_MMR6	---	6184	{ 1269, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1269 = CVT_W_S_MMR6	---
6185	{ 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_W_S_MM	---	6185	{ 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_W_S_MM	---
6186	{ 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_W_S	---	6186	{ 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_W_S	---
6187	{ 1266, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1266 = CVT_W_D64_MM	---	6187	{ 1266, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1266 = CVT_W_D64_MM	---
6188	{ 1265, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1265 = CVT_W_D64	---	6188	{ 1265, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1265 = CVT_W_D64	---
6189	{ 1264, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_W_D32_MM	---	6189	{ 1264, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_W_D32_MM	---
6190	{ 1263, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1263 = CVT_W_D32	---	6190	{ 1263, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1263 = CVT_W_D32	---
6191	{ 1262, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1262 = CVT_S_W_MMR6	---	6191	{ 1262, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1262 = CVT_S_W_MMR6	---
6192	{ 1261, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1261 = CVT_S_W_MM	---	6192	{ 1261, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1261 = CVT_S_W_MM	---
6193	{ 1260, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1260 = CVT_S_W	---	6193	{ 1260, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1260 = CVT_S_W	---
6194	{ 1259, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1259 = CVT_S_PU64	---	6194	{ 1259, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1259 = CVT_S_PU64	---
6195	{ 1258, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1258 = CVT_S_PL64	---	6195	{ 1258, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1258 = CVT_S_PL64	---
6196	{ 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1257 = CVT_S_L_MMR6	---	6196	{ 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1257 = CVT_S_L_MMR6	---
6197	{ 1256, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_S_L	---	6197	{ 1256, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_S_L	---
6198	{ 1255, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_S_D64_MM	---	6198	{ 1255, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_S_D64_MM	---
6199	{ 1254, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_S_D64	---	6199	{ 1254, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_S_D64	---
6200	{ 1253, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1253 = CVT_S_D32_MM	---	6200	{ 1253, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1253 = CVT_S_D32_MM	---
6201	{ 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_S_D32	---	6201	{ 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_S_D32	---
6202	{ 1251, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1251 = CVT_PW_PS64	---	6202	{ 1251, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1251 = CVT_PW_PS64	---
6203	{ 1250, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 676, 0\|(1ULL<	---	6203	{ 1250, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 676, 0\|(1ULL<	---
6204	{ 1249, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1249 = CVT_PS_PW64	---	6204	{ 1249, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1249 = CVT_PS_PW64	---
6205	{ 1248, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1248 = CVT_L_S_MMR6	---	6205	{ 1248, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1248 = CVT_L_S_MMR6	---
6206	{ 1247, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1247 = CVT_L_S_MM	---	6206	{ 1247, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1247 = CVT_L_S_MM	---
6207	{ 1246, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1246 = CVT_L_S	---	6207	{ 1246, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1246 = CVT_L_S	---
6208	{ 1245, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1245 = CVT_L_D_MMR6	---	6208	{ 1245, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1245 = CVT_L_D_MMR6	---
6209	{ 1244, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1244 = CVT_L_D64_MM	---	6209	{ 1244, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1244 = CVT_L_D64_MM	---
6210	{ 1243, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1243 = CVT_L_D64	---	6210	{ 1243, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1243 = CVT_L_D64	---
6211	{ 1242, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1242 = CVT_D_L_MMR6	---	6211	{ 1242, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1242 = CVT_D_L_MMR6	---
6212	{ 1241, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1241 = CVT_D64_W_MM	---	6212	{ 1241, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1241 = CVT_D64_W_MM	---
6213	{ 1240, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1240 = CVT_D64_W	---	6213	{ 1240, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1240 = CVT_D64_W	---
6214	{ 1239, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1239 = CVT_D64_S_MM	---	6214	{ 1239, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1239 = CVT_D64_S_MM	---
6215	{ 1238, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1238 = CVT_D64_S	---	6215	{ 1238, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1238 = CVT_D64_S	---
6216	{ 1237, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1237 = CVT_D64_L	---	6216	{ 1237, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1237 = CVT_D64_L	---
6217	{ 1236, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1236 = CVT_D32_W_MM	---	6217	{ 1236, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1236 = CVT_D32_W_MM	---
6218	{ 1235, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1235 = CVT_D32_W	---	6218	{ 1235, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1235 = CVT_D32_W	---
6219	{ 1234, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1234 = CVT_D32_S_MM	---	6219	{ 1234, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1234 = CVT_D32_S_MM	---
6220	{ 1233, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1233 = CVT_D32_S	---	6220	{ 1233, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 674, 0, 0x4ULL }, // Inst #1233 = CVT_D32_S	---
6221	{ 1232, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 672, 0\|(1ULL<	---	6221	{ 1232, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 672, 0\|(1ULL<	---
6222	{ 1231, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---	6222	{ 1231, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 670, 0\|(1ULL<	---
6223	{ 1230, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	---	6223	{ 1230, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	---
6224	{ 1229, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	---	6224	{ 1229, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 668, 0\|(1ULL<	---
6225	{ 1228, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6225	{ 1228, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6226	{ 1227, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6226	{ 1227, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6227	{ 1226, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6227	{ 1226, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6228	{ 1225, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6228	{ 1225, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6229	{ 1224, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6229	{ 1224, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6230	{ 1223, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6230	{ 1223, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6231	{ 1222, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6231	{ 1222, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6232	{ 1221, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6232	{ 1221, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6233	{ 1220, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1220 = COPY_U_W	---	6233	{ 1220, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1220 = COPY_U_W	---
6234	{ 1219, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1219 = COPY_U_H	---	6234	{ 1219, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1219 = COPY_U_H	---
6235	{ 1218, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1218 = COPY_U_B	---	6235	{ 1218, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1218 = COPY_U_B	---
6236	{ 1217, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1217 = COPY_S_W	---	6236	{ 1217, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 665, 0, 0x6ULL }, // Inst #1217 = COPY_S_W	---
6237	{ 1216, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1216 = COPY_S_H	---	6237	{ 1216, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 662, 0, 0x6ULL }, // Inst #1216 = COPY_S_H	---
6238	{ 1215, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 659, 0, 0x6ULL }, // Inst #1215 = COPY_S_D	---	6238	{ 1215, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 659, 0, 0x6ULL }, // Inst #1215 = COPY_S_D	---
6239	{ 1214, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1214 = COPY_S_B	---	6239	{ 1214, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 656, 0, 0x6ULL }, // Inst #1214 = COPY_S_B	---
6240	{ 1213, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1213 = CMP_UN_S_MMR6	---	6240	{ 1213, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1213 = CMP_UN_S_MMR6	---
6241	{ 1212, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1212 = CMP_UN_S	---	6241	{ 1212, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1212 = CMP_UN_S	---
6242	{ 1211, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1211 = CMP_UN_D_MMR6	---	6242	{ 1211, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1211 = CMP_UN_D_MMR6	---
6243	{ 1210, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1210 = CMP_UN_D	---	6243	{ 1210, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1210 = CMP_UN_D	---
6244	{ 1209, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1209 = CMP_ULT_S_MMR6	---	6244	{ 1209, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1209 = CMP_ULT_S_MMR6	---
6245	{ 1208, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1208 = CMP_ULT_S	---	6245	{ 1208, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1208 = CMP_ULT_S	---
6246	{ 1207, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1207 = CMP_ULT_D_MMR6	---	6246	{ 1207, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1207 = CMP_ULT_D_MMR6	---
6247	{ 1206, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1206 = CMP_ULT_D	---	6247	{ 1206, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1206 = CMP_ULT_D	---
6248	{ 1205, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1205 = CMP_ULE_S_MMR6	---	6248	{ 1205, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1205 = CMP_ULE_S_MMR6	---
6249	{ 1204, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1204 = CMP_ULE_S	---	6249	{ 1204, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1204 = CMP_ULE_S	---
6250	{ 1203, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1203 = CMP_ULE_D_MMR6	---	6250	{ 1203, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1203 = CMP_ULE_D_MMR6	---
6251	{ 1202, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1202 = CMP_ULE_D	---	6251	{ 1202, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1202 = CMP_ULE_D	---
6252	{ 1201, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1201 = CMP_UEQ_S_MMR6	---	6252	{ 1201, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1201 = CMP_UEQ_S_MMR6	---
6253	{ 1200, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1200 = CMP_UEQ_S	---	6253	{ 1200, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1200 = CMP_UEQ_S	---
6254	{ 1199, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1199 = CMP_UEQ_D_MMR6	---	6254	{ 1199, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1199 = CMP_UEQ_D_MMR6	---
6255	{ 1198, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1198 = CMP_UEQ_D	---	6255	{ 1198, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1198 = CMP_UEQ_D	---
6256	{ 1197, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6256	{ 1197, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6257	{ 1196, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6257	{ 1196, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6258	{ 1195, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6258	{ 1195, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6259	{ 1194, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6259	{ 1194, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6260	{ 1193, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6260	{ 1193, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6261	{ 1192, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6261	{ 1192, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6262	{ 1191, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6262	{ 1191, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6263	{ 1190, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6263	{ 1190, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6264	{ 1189, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6264	{ 1189, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6265	{ 1188, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6265	{ 1188, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6266	{ 1187, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6266	{ 1187, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6267	{ 1186, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6267	{ 1186, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6268	{ 1185, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6268	{ 1185, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6269	{ 1184, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6269	{ 1184, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6270	{ 1183, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6270	{ 1183, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6271	{ 1182, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6271	{ 1182, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6272	{ 1181, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6272	{ 1181, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6273	{ 1180, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6273	{ 1180, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6274	{ 1179, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6274	{ 1179, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6275	{ 1178, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6275	{ 1178, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6276	{ 1177, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6276	{ 1177, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6277	{ 1176, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6277	{ 1176, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6278	{ 1175, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6278	{ 1175, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6279	{ 1174, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6279	{ 1174, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6280	{ 1173, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6280	{ 1173, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6281	{ 1172, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6281	{ 1172, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6282	{ 1171, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6282	{ 1171, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6283	{ 1170, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6283	{ 1170, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6284	{ 1169, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6284	{ 1169, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6285	{ 1168, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6285	{ 1168, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6286	{ 1167, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6286	{ 1167, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6287	{ 1166, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6287	{ 1166, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6288	{ 1165, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1165 = CMP_LT_S_MMR6	---	6288	{ 1165, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1165 = CMP_LT_S_MMR6	---
6289	{ 1164, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1164 = CMP_LT_S	---	6289	{ 1164, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1164 = CMP_LT_S	---
6290	{ 1163, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6290	{ 1163, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6291	{ 1162, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6291	{ 1162, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6292	{ 1161, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1161 = CMP_LT_D_MMR6	---	6292	{ 1161, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1161 = CMP_LT_D_MMR6	---
6293	{ 1160, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1160 = CMP_LT_D	---	6293	{ 1160, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1160 = CMP_LT_D	---
6294	{ 1159, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1159 = CMP_LE_S_MMR6	---	6294	{ 1159, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1159 = CMP_LE_S_MMR6	---
6295	{ 1158, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1158 = CMP_LE_S	---	6295	{ 1158, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1158 = CMP_LE_S	---
6296	{ 1157, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6296	{ 1157, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6297	{ 1156, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6297	{ 1156, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6298	{ 1155, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1155 = CMP_LE_D_MMR6	---	6298	{ 1155, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1155 = CMP_LE_D_MMR6	---
6299	{ 1154, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1154 = CMP_LE_D	---	6299	{ 1154, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1154 = CMP_LE_D	---
6300	{ 1153, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6300	{ 1153, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6301	{ 1152, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6301	{ 1152, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6302	{ 1151, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1151 = CMP_EQ_S_MMR6	---	6302	{ 1151, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1151 = CMP_EQ_S_MMR6	---
6303	{ 1150, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1150 = CMP_EQ_S	---	6303	{ 1150, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 653, 0, 0x16ULL }, // Inst #1150 = CMP_EQ_S	---
6304	{ 1149, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6304	{ 1149, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6305	{ 1148, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6305	{ 1148, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6306	{ 1147, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1147 = CMP_EQ_D_MMR6	---	6306	{ 1147, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1147 = CMP_EQ_D_MMR6	---
6307	{ 1146, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1146 = CMP_EQ_D	---	6307	{ 1146, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 650, 0, 0x16ULL }, // Inst #1146 = CMP_EQ_D	---
6308	{ 1145, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---	6308	{ 1145, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 653, 0\|(1ULL<	---
6309	{ 1144, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---	6309	{ 1144, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 650, 0\|(1ULL<	---
6310	{ 1143, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6310	{ 1143, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6311	{ 1142, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6311	{ 1142, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6312	{ 1141, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6312	{ 1141, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6313	{ 1140, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6313	{ 1140, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6314	{ 1139, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6314	{ 1139, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6315	{ 1138, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---	6315	{ 1138, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 519, 0\|(1ULL<	---
6316	{ 1137, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6316	{ 1137, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6317	{ 1136, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6317	{ 1136, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6318	{ 1135, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6318	{ 1135, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6319	{ 1134, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6319	{ 1134, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6320	{ 1133, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6320	{ 1133, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6321	{ 1132, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---	6321	{ 1132, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 647, 0\|(1ULL<	---
6322	{ 1131, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6322	{ 1131, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6323	{ 1130, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6323	{ 1130, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6324	{ 1129, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6324	{ 1129, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6325	{ 1128, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6325	{ 1128, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6326	{ 1127, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6326	{ 1127, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6327	{ 1126, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---	6327	{ 1126, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 647, 0\|(1ULL<	---
6328	{ 1125, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1125 = CLZ_R6	---	6328	{ 1125, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1125 = CLZ_R6	---
6329	{ 1124, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6329	{ 1124, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6330	{ 1123, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1123 = CLZ_MM	---	6330	{ 1123, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1123 = CLZ_MM	---
6331	{ 1122, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1122 = CLZ	---	6331	{ 1122, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1122 = CLZ	---
6332	{ 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1121 = CLT_U_W	---	6332	{ 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1121 = CLT_U_W	---
6333	{ 1120, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1120 = CLT_U_H	---	6333	{ 1120, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1120 = CLT_U_H	---
6334	{ 1119, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1119 = CLT_U_D	---	6334	{ 1119, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1119 = CLT_U_D	---
6335	{ 1118, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1118 = CLT_U_B	---	6335	{ 1118, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1118 = CLT_U_B	---
6336	{ 1117, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1117 = CLT_S_W	---	6336	{ 1117, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1117 = CLT_S_W	---
6337	{ 1116, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1116 = CLT_S_H	---	6337	{ 1116, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1116 = CLT_S_H	---
6338	{ 1115, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1115 = CLT_S_D	---	6338	{ 1115, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1115 = CLT_S_D	---
6339	{ 1114, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1114 = CLT_S_B	---	6339	{ 1114, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1114 = CLT_S_B	---
6340	{ 1113, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1113 = CLTI_U_W	---	6340	{ 1113, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1113 = CLTI_U_W	---
6341	{ 1112, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1112 = CLTI_U_H	---	6341	{ 1112, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1112 = CLTI_U_H	---
6342	{ 1111, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1111 = CLTI_U_D	---	6342	{ 1111, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1111 = CLTI_U_D	---
6343	{ 1110, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1110 = CLTI_U_B	---	6343	{ 1110, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1110 = CLTI_U_B	---
6344	{ 1109, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1109 = CLTI_S_W	---	6344	{ 1109, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1109 = CLTI_S_W	---
6345	{ 1108, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1108 = CLTI_S_H	---	6345	{ 1108, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1108 = CLTI_S_H	---
6346	{ 1107, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1107 = CLTI_S_D	---	6346	{ 1107, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1107 = CLTI_S_D	---
6347	{ 1106, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1106 = CLTI_S_B	---	6347	{ 1106, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1106 = CLTI_S_B	---
6348	{ 1105, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1105 = CLO_R6	---	6348	{ 1105, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #1105 = CLO_R6	---
6349	{ 1104, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6349	{ 1104, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6350	{ 1103, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1103 = CLO_MM	---	6350	{ 1103, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1103 = CLO_MM	---
6351	{ 1102, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1102 = CLO	---	6351	{ 1102, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 136, 0, 0x1ULL }, // Inst #1102 = CLO	---
6352	{ 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1101 = CLE_U_W	---	6352	{ 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1101 = CLE_U_W	---
6353	{ 1100, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1100 = CLE_U_H	---	6353	{ 1100, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1100 = CLE_U_H	---
6354	{ 1099, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1099 = CLE_U_D	---	6354	{ 1099, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1099 = CLE_U_D	---
6355	{ 1098, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1098 = CLE_U_B	---	6355	{ 1098, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1098 = CLE_U_B	---
6356	{ 1097, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1097 = CLE_S_W	---	6356	{ 1097, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1097 = CLE_S_W	---
6357	{ 1096, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1096 = CLE_S_H	---	6357	{ 1096, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1096 = CLE_S_H	---
6358	{ 1095, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1095 = CLE_S_D	---	6358	{ 1095, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1095 = CLE_S_D	---
6359	{ 1094, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1094 = CLE_S_B	---	6359	{ 1094, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1094 = CLE_S_B	---
6360	{ 1093, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1093 = CLEI_U_W	---	6360	{ 1093, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1093 = CLEI_U_W	---
6361	{ 1092, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1092 = CLEI_U_H	---	6361	{ 1092, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1092 = CLEI_U_H	---
6362	{ 1091, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1091 = CLEI_U_D	---	6362	{ 1091, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1091 = CLEI_U_D	---
6363	{ 1090, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1090 = CLEI_U_B	---	6363	{ 1090, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1090 = CLEI_U_B	---
6364	{ 1089, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1089 = CLEI_S_W	---	6364	{ 1089, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1089 = CLEI_S_W	---
6365	{ 1088, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1088 = CLEI_S_H	---	6365	{ 1088, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1088 = CLEI_S_H	---
6366	{ 1087, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1087 = CLEI_S_D	---	6366	{ 1087, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1087 = CLEI_S_D	---
6367	{ 1086, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1086 = CLEI_S_B	---	6367	{ 1086, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1086 = CLEI_S_B	---
6368	{ 1085, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	6368	{ 1085, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
6369	{ 1084, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---	6369	{ 1084, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 627, 0\|(1ULL<	---
6370	{ 1083, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---	6370	{ 1083, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---
6371	{ 1082, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---	6371	{ 1082, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 619, 0\|(1ULL<	---
6372	{ 1081, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1081 = CINS_i32	---	6372	{ 1081, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1081 = CINS_i32	---
6373	{ 1080, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1080 = CINS64_32	---	6373	{ 1080, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1080 = CINS64_32	---
6374	{ 1079, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1079 = CINS32	---	6374	{ 1079, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1079 = CINS32	---
6375	{ 1078, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1078 = CINS	---	6375	{ 1078, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 635, 0, 0x1ULL }, // Inst #1078 = CINS	---
6376	{ 1077, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 633, 0\|(1ULL<	---	6376	{ 1077, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 633, 0\|(1ULL<	---
6377	{ 1076, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---	6377	{ 1076, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 631, 0\|(1ULL<	---
6378	{ 1075, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	---	6378	{ 1075, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	---
6379	{ 1074, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	---	6379	{ 1074, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 629, 0\|(1ULL<	---
6380	{ 1073, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6380	{ 1073, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6381	{ 1072, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6381	{ 1072, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6382	{ 1071, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6382	{ 1071, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6383	{ 1070, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6383	{ 1070, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6384	{ 1069, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1069 = CEQI_W	---	6384	{ 1069, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1069 = CEQI_W	---
6385	{ 1068, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1068 = CEQI_H	---	6385	{ 1068, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1068 = CEQI_H	---
6386	{ 1067, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1067 = CEQI_D	---	6386	{ 1067, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1067 = CEQI_D	---
6387	{ 1066, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1066 = CEQI_B	---	6387	{ 1066, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1066 = CEQI_B	---
6388	{ 1065, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1065 = CEIL_W_S_MMR6	---	6388	{ 1065, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1065 = CEIL_W_S_MMR6	---
6389	{ 1064, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1064 = CEIL_W_S_MM	---	6389	{ 1064, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1064 = CEIL_W_S_MM	---
6390	{ 1063, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1063 = CEIL_W_S	---	6390	{ 1063, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1063 = CEIL_W_S	---
6391	{ 1062, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1062 = CEIL_W_MM	---	6391	{ 1062, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1062 = CEIL_W_MM	---
6392	{ 1061, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1061 = CEIL_W_D_MMR6	---	6392	{ 1061, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1061 = CEIL_W_D_MMR6	---
6393	{ 1060, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1060 = CEIL_W_D64	---	6393	{ 1060, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1060 = CEIL_W_D64	---
6394	{ 1059, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1059 = CEIL_W_D32	---	6394	{ 1059, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1059 = CEIL_W_D32	---
6395	{ 1058, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1058 = CEIL_L_S_MMR6	---	6395	{ 1058, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1058 = CEIL_L_S_MMR6	---
6396	{ 1057, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1057 = CEIL_L_S	---	6396	{ 1057, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 621, 0, 0x4ULL }, // Inst #1057 = CEIL_L_S	---
6397	{ 1056, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1056 = CEIL_L_D_MMR6	---	6397	{ 1056, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1056 = CEIL_L_D_MMR6	---
6398	{ 1055, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1055 = CEIL_L_D64	---	6398	{ 1055, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 619, 0, 0x4ULL }, // Inst #1055 = CEIL_L_D64	---
6399	{ 1054, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6399	{ 1054, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6400	{ 1053, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6400	{ 1053, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6401	{ 1052, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6401	{ 1052, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6402	{ 1051, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6402	{ 1051, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6403	{ 1050, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6403	{ 1050, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6404	{ 1049, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---	6404	{ 1049, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 616, 0\|(1ULL<	---
6405	{ 1048, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---	6405	{ 1048, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---
6406	{ 1047, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---	6406	{ 1047, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---
6407	{ 1046, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---	6407	{ 1046, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---
6408	{ 1045, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---	6408	{ 1045, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0\|(1ULL<	---
6409	{ 1044, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6409	{ 1044, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6410	{ 1043, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---	6410	{ 1043, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---
6411	{ 1042, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---	6411	{ 1042, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---
6412	{ 1041, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6412	{ 1041, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6413	{ 1040, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6413	{ 1040, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6414	{ 1039, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---	6414	{ 1039, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---
6415	{ 1038, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---	6415	{ 1038, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 614, 0\|(1ULL<	---
6416	{ 1037, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	---	6416	{ 1037, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	---
6417	{ 1036, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---	6417	{ 1036, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---
6418	{ 1035, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	---	6418	{ 1035, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	---
6419	{ 1034, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	---	6419	{ 1034, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	---
6420	{ 1033, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---	6420	{ 1033, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---
6421	{ 1032, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1032 = BSET_W	---	6421	{ 1032, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #1032 = BSET_W	---
6422	{ 1031, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1031 = BSET_H	---	6422	{ 1031, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #1031 = BSET_H	---
6423	{ 1030, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1030 = BSET_D	---	6423	{ 1030, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #1030 = BSET_D	---
6424	{ 1029, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1029 = BSET_B	---	6424	{ 1029, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #1029 = BSET_B	---
6425	{ 1028, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1028 = BSETI_W	---	6425	{ 1028, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #1028 = BSETI_W	---
6426	{ 1027, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1027 = BSETI_H	---	6426	{ 1027, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #1027 = BSETI_H	---
6427	{ 1026, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1026 = BSETI_D	---	6427	{ 1026, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #1026 = BSETI_D	---
6428	{ 1025, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1025 = BSETI_B	---	6428	{ 1025, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #1025 = BSETI_B	---
6429	{ 1024, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1024 = BSEL_V	---	6429	{ 1024, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1024 = BSEL_V	---
6430	{ 1023, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #1023 = BSELI_B	---	6430	{ 1023, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #1023 = BSELI_B	---
6431	{ 1022, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---	6431	{ 1022, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---
6432	{ 1021, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---	6432	{ 1021, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---
6433	{ 1020, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	6433	{ 1020, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
6434	{ 1019, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	6434	{ 1019, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
6435	{ 1018, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---	6435	{ 1018, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---
6436	{ 1017, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6436	{ 1017, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6437	{ 1016, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6437	{ 1016, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6438	{ 1015, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6438	{ 1015, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6439	{ 1014, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6439	{ 1014, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6440	{ 1013, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6440	{ 1013, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6441	{ 1012, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	---	6441	{ 1012, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0\|(1ULL<	---
6442	{ 1011, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---	6442	{ 1011, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---
6443	{ 1010, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	---	6443	{ 1010, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0\|(1ULL<	---
6444	{ 1009, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	---	6444	{ 1009, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 608, 0\|(1ULL<	---
6445	{ 1008, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---	6445	{ 1008, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 606, 0\|(1ULL<	---
6446	{ 1007, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6446	{ 1007, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6447	{ 1006, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6447	{ 1006, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6448	{ 1005, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6448	{ 1005, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6449	{ 1004, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6449	{ 1004, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6450	{ 1003, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6450	{ 1003, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6451	{ 1002, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6451	{ 1002, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6452	{ 1001, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---	6452	{ 1001, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---
6453	{ 1000, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6453	{ 1000, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6454	{ 999, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6454	{ 999, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6455	{ 998, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6455	{ 998, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6456	{ 997, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---	6456	{ 997, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---
6457	{ 996, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6457	{ 996, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6458	{ 995, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #995 = BNEG_W	---	6458	{ 995, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #995 = BNEG_W	---
6459	{ 994, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #994 = BNEG_H	---	6459	{ 994, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #994 = BNEG_H	---
6460	{ 993, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #993 = BNEG_D	---	6460	{ 993, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #993 = BNEG_D	---
6461	{ 992, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #992 = BNEG_B	---	6461	{ 992, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #992 = BNEG_B	---
6462	{ 991, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #991 = BNEGI_W	---	6462	{ 991, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #991 = BNEGI_W	---
6463	{ 990, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #990 = BNEGI_H	---	6463	{ 990, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #990 = BNEGI_H	---
6464	{ 989, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #989 = BNEGI_D	---	6464	{ 989, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #989 = BNEGI_D	---
6465	{ 988, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #988 = BNEGI_B	---	6465	{ 988, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #988 = BNEGI_B	---
6466	{ 987, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6466	{ 987, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6467	{ 986, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6467	{ 986, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6468	{ 985, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6468	{ 985, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6469	{ 984, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6469	{ 984, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6470	{ 983, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6470	{ 983, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6471	{ 982, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #982 = BMZ_V	---	6471	{ 982, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #982 = BMZ_V	---
6472	{ 981, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #981 = BMZI_B	---	6472	{ 981, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #981 = BMZI_B	---
6473	{ 980, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #980 = BMNZ_V	---	6473	{ 980, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #980 = BMNZ_V	---
6474	{ 979, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #979 = BMNZI_B	---	6474	{ 979, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #979 = BMNZI_B	---
6475	{ 978, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6475	{ 978, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6476	{ 977, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6476	{ 977, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6477	{ 976, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6477	{ 976, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6478	{ 975, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6478	{ 975, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6479	{ 974, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6479	{ 974, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6480	{ 973, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6480	{ 973, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6481	{ 972, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6481	{ 972, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6482	{ 971, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6482	{ 971, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6483	{ 970, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6483	{ 970, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6484	{ 969, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6484	{ 969, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6485	{ 968, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6485	{ 968, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6486	{ 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6486	{ 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6487	{ 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6487	{ 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6488	{ 965, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6488	{ 965, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6489	{ 964, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6489	{ 964, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6490	{ 963, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6490	{ 963, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6491	{ 962, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6491	{ 962, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6492	{ 961, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6492	{ 961, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6493	{ 960, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6493	{ 960, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6494	{ 959, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6494	{ 959, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6495	{ 958, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6495	{ 958, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6496	{ 957, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6496	{ 957, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6497	{ 956, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6497	{ 956, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6498	{ 955, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6498	{ 955, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6499	{ 954, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6499	{ 954, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6500	{ 953, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6500	{ 953, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6501	{ 952, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6501	{ 952, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6502	{ 951, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6502	{ 951, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6503	{ 950, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6503	{ 950, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6504	{ 949, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6504	{ 949, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6505	{ 948, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #948 = BITREV_MM	---	6505	{ 948, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #948 = BITREV_MM	---
6506	{ 947, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #947 = BITREV	---	6506	{ 947, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 136, 0, 0x6ULL }, // Inst #947 = BITREV	---
6507	{ 946, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #946 = BINSR_W	---	6507	{ 946, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #946 = BINSR_W	---
6508	{ 945, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #945 = BINSR_H	---	6508	{ 945, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #945 = BINSR_H	---
6509	{ 944, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #944 = BINSR_D	---	6509	{ 944, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #944 = BINSR_D	---
6510	{ 943, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #943 = BINSR_B	---	6510	{ 943, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #943 = BINSR_B	---
6511	{ 942, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #942 = BINSRI_W	---	6511	{ 942, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #942 = BINSRI_W	---
6512	{ 941, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #941 = BINSRI_H	---	6512	{ 941, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #941 = BINSRI_H	---
6513	{ 940, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #940 = BINSRI_D	---	6513	{ 940, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #940 = BINSRI_D	---
6514	{ 939, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #939 = BINSRI_B	---	6514	{ 939, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #939 = BINSRI_B	---
6515	{ 938, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #938 = BINSL_W	---	6515	{ 938, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #938 = BINSL_W	---
6516	{ 937, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #937 = BINSL_H	---	6516	{ 937, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #937 = BINSL_H	---
6517	{ 936, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #936 = BINSL_D	---	6517	{ 936, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 182, 0, 0x6ULL }, // Inst #936 = BINSL_D	---
6518	{ 935, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #935 = BINSL_B	---	6518	{ 935, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #935 = BINSL_B	---
6519	{ 934, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #934 = BINSLI_W	---	6519	{ 934, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #934 = BINSLI_W	---
6520	{ 933, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #933 = BINSLI_H	---	6520	{ 933, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #933 = BINSLI_H	---
6521	{ 932, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #932 = BINSLI_D	---	6521	{ 932, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #932 = BINSLI_D	---
6522	{ 931, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #931 = BINSLI_B	---	6522	{ 931, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 586, 0, 0x6ULL }, // Inst #931 = BINSLI_B	---
6523	{ 930, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6523	{ 930, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6524	{ 929, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6524	{ 929, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6525	{ 928, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6525	{ 928, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6526	{ 927, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6526	{ 927, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6527	{ 926, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6527	{ 926, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6528	{ 925, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6528	{ 925, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6529	{ 924, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6529	{ 924, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6530	{ 923, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6530	{ 923, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6531	{ 922, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6531	{ 922, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6532	{ 921, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6532	{ 921, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6533	{ 920, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6533	{ 920, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6534	{ 919, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6534	{ 919, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6535	{ 918, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6535	{ 918, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6536	{ 917, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6536	{ 917, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6537	{ 916, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6537	{ 916, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6538	{ 915, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6538	{ 915, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6539	{ 914, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6539	{ 914, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6540	{ 913, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6540	{ 913, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6541	{ 912, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6541	{ 912, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6542	{ 911, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6542	{ 911, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6543	{ 910, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6543	{ 910, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6544	{ 909, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6544	{ 909, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6545	{ 908, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6545	{ 908, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6546	{ 907, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6546	{ 907, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6547	{ 906, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6547	{ 906, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6548	{ 905, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6548	{ 905, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6549	{ 904, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6549	{ 904, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6550	{ 903, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6550	{ 903, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6551	{ 902, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6551	{ 902, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6552	{ 901, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6552	{ 901, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6553	{ 900, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6553	{ 900, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6554	{ 899, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---	6554	{ 899, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 343, 0\|(1ULL<	---
6555	{ 898, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---	6555	{ 898, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---
6556	{ 897, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---	6556	{ 897, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 341, 0\|(1ULL<	---
6557	{ 896, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6557	{ 896, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6558	{ 895, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---	6558	{ 895, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 341, 0\|(1ULL<	---
6559	{ 894, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---	6559	{ 894, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 584, 0\|(1ULL<	---
6560	{ 893, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6560	{ 893, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6561	{ 892, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6561	{ 892, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6562	{ 891, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6562	{ 891, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6563	{ 890, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6563	{ 890, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6564	{ 889, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---	6564	{ 889, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 335, 0\|(1ULL<	---
6565	{ 888, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---	6565	{ 888, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 178, 0\|(1ULL<	---
6566	{ 887, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6566	{ 887, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6567	{ 886, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #886 = BCLR_W	---	6567	{ 886, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #886 = BCLR_W	---
6568	{ 885, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #885 = BCLR_H	---	6568	{ 885, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #885 = BCLR_H	---
6569	{ 884, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #884 = BCLR_D	---	6569	{ 884, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #884 = BCLR_D	---
6570	{ 883, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #883 = BCLR_B	---	6570	{ 883, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #883 = BCLR_B	---
6571	{ 882, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #882 = BCLRI_W	---	6571	{ 882, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #882 = BCLRI_W	---
6572	{ 881, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #881 = BCLRI_H	---	6572	{ 881, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #881 = BCLRI_H	---
6573	{ 880, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #880 = BCLRI_D	---	6573	{ 880, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #880 = BCLRI_D	---
6574	{ 879, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #879 = BCLRI_B	---	6574	{ 879, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #879 = BCLRI_B	---
6575	{ 878, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	---	6575	{ 878, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	---
6576	{ 877, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	---	6576	{ 877, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	---
6577	{ 876, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	---	6577	{ 876, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 582, 0\|(1ULL<	---
6578	{ 875, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	---	6578	{ 875, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 582, 0\|(1ULL<	---
6579	{ 874, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6579	{ 874, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6580	{ 873, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6580	{ 873, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6581	{ 872, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6581	{ 872, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6582	{ 871, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	---	6582	{ 871, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	---
6583	{ 870, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	---	6583	{ 870, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	---
6584	{ 869, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6584	{ 869, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6585	{ 868, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6585	{ 868, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6586	{ 867, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---	6586	{ 867, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 580, 0\|(1ULL<	---
6587	{ 866, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	---	6587	{ 866, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 578, 0\|(1ULL<	---
6588	{ 865, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	---	6588	{ 865, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 578, 0\|(1ULL<	---
6589	{ 864, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---	6589	{ 864, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---
6590	{ 863, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	6590	{ 863, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
6591	{ 862, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---	6591	{ 862, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---
6592	{ 861, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---	6592	{ 861, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---
6593	{ 860, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---	6593	{ 860, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---
6594	{ 859, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---	6594	{ 859, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 575, 0\|(1ULL<	---
6595	{ 858, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #858 = BALIGN_MMR2	---	6595	{ 858, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #858 = BALIGN_MMR2	---
6596	{ 857, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #857 = BALIGN	---	6596	{ 857, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #857 = BALIGN	---
6597	{ 856, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---	6597	{ 856, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---
6598	{ 855, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---	6598	{ 855, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---
6599	{ 854, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---	6599	{ 854, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---
6600	{ 853, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6600	{ 853, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6601	{ 852, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---	6601	{ 852, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---
6602	{ 851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---	6602	{ 851, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 572, 0\|(1ULL<	---
6603	{ 850, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---	6603	{ 850, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---
6604	{ 849, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	6604	{ 849, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
6605	{ 848, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	6605	{ 848, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
6606	{ 847, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 569, 0, 0x0ULL }, // Inst #847 = AddiuRxRyOffMemX16	---	6606	{ 847, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 569, 0, 0x0ULL }, // Inst #847 = AddiuRxRyOffMemX16	---
6607	{ 846, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	---	6607	{ 846, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	---
6608	{ 845, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	---	6608	{ 845, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 566, 0\|(1ULL<	---
6609	{ 844, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---	6609	{ 844, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---
6610	{ 843, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---	6610	{ 843, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 564, 0\|(1ULL<	---
6611	{ 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6611	{ 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6612	{ 841, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6612	{ 841, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6613	{ 840, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6613	{ 840, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6614	{ 839, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6614	{ 839, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6615	{ 838, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6615	{ 838, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6616	{ 837, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6616	{ 837, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6617	{ 836, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6617	{ 836, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6618	{ 835, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6618	{ 835, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6619	{ 834, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6619	{ 834, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6620	{ 833, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6620	{ 833, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6621	{ 832, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6621	{ 832, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6622	{ 831, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6622	{ 831, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6623	{ 830, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6623	{ 830, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6624	{ 829, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6624	{ 829, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6625	{ 828, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6625	{ 828, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6626	{ 827, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6626	{ 827, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6627	{ 826, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6627	{ 826, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6628	{ 825, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6628	{ 825, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6629	{ 824, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6629	{ 824, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6630	{ 823, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6630	{ 823, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6631	{ 822, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #822 = ASUB_U_W	---	6631	{ 822, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #822 = ASUB_U_W	---
6632	{ 821, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #821 = ASUB_U_H	---	6632	{ 821, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #821 = ASUB_U_H	---
6633	{ 820, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #820 = ASUB_U_D	---	6633	{ 820, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #820 = ASUB_U_D	---
6634	{ 819, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #819 = ASUB_U_B	---	6634	{ 819, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #819 = ASUB_U_B	---
6635	{ 818, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #818 = ASUB_S_W	---	6635	{ 818, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 144, 0, 0x6ULL }, // Inst #818 = ASUB_S_W	---
6636	{ 817, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #817 = ASUB_S_H	---	6636	{ 817, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 141, 0, 0x6ULL }, // Inst #817 = ASUB_S_H	---
6637	{ 816, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #816 = ASUB_S_D	---	6637	{ 816, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 138, 0, 0x6ULL }, // Inst #816 = ASUB_S_D	---
6638	{ 815, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #815 = ASUB_S_B	---	6638	{ 815, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #815 = ASUB_S_B	---
6639	{ 814, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #814 = APPEND_MMR2	---	6639	{ 814, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #814 = APPEND_MMR2	---
6640	{ 813, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = APPEND	---	6640	{ 813, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = APPEND	---
6641	{ 812, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6641	{ 812, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6642	{ 811, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6642	{ 811, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6643	{ 810, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6643	{ 810, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6644	{ 809, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #809 = AND_V	---	6644	{ 809, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #809 = AND_V	---
6645	{ 808, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6645	{ 808, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6646	{ 807, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6646	{ 807, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6647	{ 806, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6647	{ 806, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6648	{ 805, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #805 = ANDI_B	---	6648	{ 805, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #805 = ANDI_B	---
6649	{ 804, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #804 = ANDI16_MMR6	---	6649	{ 804, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #804 = ANDI16_MMR6	---
6650	{ 803, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #803 = ANDI16_MM	---	6650	{ 803, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #803 = ANDI16_MM	---
6651	{ 802, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	6651	{ 802, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
6652	{ 801, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	6652	{ 801, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
6653	{ 800, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---	6653	{ 800, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 557, 0\|(1ULL<	---
6654	{ 799, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6654	{ 799, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6655	{ 798, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6655	{ 798, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6656	{ 797, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6656	{ 797, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6657	{ 796, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---	6657	{ 796, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---
6658	{ 795, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---	6658	{ 795, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 553, 0\|(1ULL<	---
6659	{ 794, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6659	{ 794, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6660	{ 793, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6660	{ 793, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6661	{ 792, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6661	{ 792, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6662	{ 791, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6662	{ 791, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6663	{ 790, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6663	{ 790, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6664	{ 789, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6664	{ 789, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6665	{ 788, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6665	{ 788, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6666	{ 787, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6666	{ 787, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6667	{ 786, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6667	{ 786, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6668	{ 785, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6668	{ 785, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6669	{ 784, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6669	{ 784, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6670	{ 783, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6670	{ 783, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6671	{ 782, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	---	6671	{ 782, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	---
6672	{ 781, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	---	6672	{ 781, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 222, 0\|(1ULL<	---
6673	{ 780, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6673	{ 780, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6674	{ 779, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6674	{ 779, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6675	{ 778, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6675	{ 778, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6676	{ 777, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6676	{ 777, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6677	{ 776, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #776 = ADDVI_W	---	6677	{ 776, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 550, 0, 0x6ULL }, // Inst #776 = ADDVI_W	---
6678	{ 775, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #775 = ADDVI_H	---	6678	{ 775, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 547, 0, 0x6ULL }, // Inst #775 = ADDVI_H	---
6679	{ 774, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #774 = ADDVI_D	---	6679	{ 774, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 544, 0, 0x6ULL }, // Inst #774 = ADDVI_D	---
6680	{ 773, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #773 = ADDVI_B	---	6680	{ 773, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 541, 0, 0x6ULL }, // Inst #773 = ADDVI_B	---
6681	{ 772, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6681	{ 772, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6682	{ 771, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6682	{ 771, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6683	{ 770, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6683	{ 770, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6684	{ 769, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6684	{ 769, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6685	{ 768, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6685	{ 768, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6686	{ 767, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6686	{ 767, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6687	{ 766, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6687	{ 766, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6688	{ 765, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6688	{ 765, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6689	{ 764, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6689	{ 764, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6690	{ 763, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6690	{ 763, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6691	{ 762, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6691	{ 762, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6692	{ 761, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6692	{ 761, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6693	{ 760, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6693	{ 760, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6694	{ 759, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	---	6694	{ 759, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	---
6695	{ 758, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	---	6695	{ 758, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 538, 0\|(1ULL<	---
6696	{ 757, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6696	{ 757, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6697	{ 756, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6697	{ 756, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6698	{ 755, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6698	{ 755, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6699	{ 754, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6699	{ 754, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6700	{ 753, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6700	{ 753, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6701	{ 752, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6701	{ 752, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6702	{ 751, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6702	{ 751, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6703	{ 750, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6703	{ 750, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6704	{ 749, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6704	{ 749, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6705	{ 748, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6705	{ 748, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6706	{ 747, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6706	{ 747, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6707	{ 746, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---	6707	{ 746, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 535, 0\|(1ULL<	---
6708	{ 745, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	---	6708	{ 745, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	---
6709	{ 744, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	---	6709	{ 744, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 222, 0\|(1ULL<	---
6710	{ 743, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---	6710	{ 743, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 532, 0\|(1ULL<	---
6711	{ 742, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---	6711	{ 742, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---
6712	{ 741, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---	6712	{ 741, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 222, 0\|(1ULL<	---
6713	{ 740, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6713	{ 740, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6714	{ 739, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6714	{ 739, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6715	{ 738, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6715	{ 738, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6716	{ 737, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---	6716	{ 737, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 529, 0\|(1ULL<	---
6717	{ 736, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6717	{ 736, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6718	{ 735, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6718	{ 735, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6719	{ 734, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6719	{ 734, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6720	{ 733, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6720	{ 733, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6721	{ 732, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6721	{ 732, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6722	{ 731, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6722	{ 731, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6723	{ 730, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6723	{ 730, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6724	{ 729, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---	6724	{ 729, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 529, 0\|(1ULL<	---
6725	{ 728, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6725	{ 728, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6726	{ 727, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	6726	{ 727, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
6727	{ 726, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #726 = ADDIUS5_MM	---	6727	{ 726, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #726 = ADDIUS5_MM	---
6728	{ 725, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---	6728	{ 725, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 523, 0\|(1ULL<	---
6729	{ 724, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---	6729	{ 724, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---
6730	{ 723, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6730	{ 723, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6731	{ 722, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---	6731	{ 722, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 521, 0\|(1ULL<	---
6732	{ 721, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6732	{ 721, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6733	{ 720, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6733	{ 720, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6734	{ 719, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	---	6734	{ 719, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	---
6735	{ 718, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	---	6735	{ 718, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 136, 0\|(1ULL<	---
6736	{ 717, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---	6736	{ 717, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---
6737	{ 716, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---	6737	{ 716, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---
6738	{ 715, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---	6738	{ 715, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---
6739	{ 714, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---	6739	{ 714, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 519, 0\|(1ULL<	---
6740	{ 713, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6740	{ 713, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6741	{ 712, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6741	{ 712, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6742	{ 711, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6742	{ 711, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6743	{ 710, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6743	{ 710, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6744	{ 709, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6744	{ 709, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6745	{ 708, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6745	{ 708, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6746	{ 707, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6746	{ 707, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6747	{ 706, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6747	{ 706, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6748	{ 705, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6748	{ 705, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6749	{ 704, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6749	{ 704, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6750	{ 703, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6750	{ 703, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6751	{ 702, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6751	{ 702, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6752	{ 701, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6752	{ 701, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6753	{ 700, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6753	{ 700, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6754	{ 699, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6754	{ 699, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6755	{ 698, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---	6755	{ 698, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---
6756	{ 697, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---	6756	{ 697, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---
6757	{ 696, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6757	{ 696, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6758	{ 695, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6758	{ 695, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6759	{ 694, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---	6759	{ 694, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---
6760	{ 693, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6760	{ 693, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6761	{ 692, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---	6761	{ 692, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---
6762	{ 691, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6762	{ 691, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6763	{ 690, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6763	{ 690, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6764	{ 689, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---	6764	{ 689, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 181, 0\|(1ULL<	---
6765	{ 688, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---	6765	{ 688, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---
6766	{ 687, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---	6766	{ 687, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 302, 0\|(1ULL<	---
6767	{ 686, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---	6767	{ 686, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0\|(1ULL<	---
6768	{ 685, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 392, 0\|(1ULL<	---	6768	{ 685, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 392, 0\|(1ULL<	---
6769	{ 684, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---	6769	{ 684, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---
6770	{ 683, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	---	6770	{ 683, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	---
6771	{ 682, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	---	6771	{ 682, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 516, 0\|(1ULL<	---
6772	{ 681, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---	6772	{ 681, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 392, 0\|(1ULL<	---
6773	{ 680, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6773	{ 680, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6774	{ 679, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6774	{ 679, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6775	{ 678, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6775	{ 678, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6776	{ 677, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6776	{ 677, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6777	{ 676, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6777	{ 676, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6778	{ 675, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6778	{ 675, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6779	{ 674, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6779	{ 674, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6780	{ 673, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6780	{ 673, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6781	{ 672, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6781	{ 672, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6782	{ 671, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6782	{ 671, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6783	{ 670, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---	6783	{ 670, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 511, 0\|(1ULL<	---
6784	{ 669, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---	6784	{ 669, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0\|(1ULL<	---
6785	{ 668, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	---	6785	{ 668, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	---
6786	{ 667, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	---	6786	{ 667, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 502, 0\|(1ULL<	---
6787	{ 666, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	6787	{ 666, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
6788	{ 665, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	6788	{ 665, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
6789	{ 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	---	6789	{ 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	---
6790	{ 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---	6790	{ 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---
6791	{ 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	---	6791	{ 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	---
6792	{ 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	---	6792	{ 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	---
6793	{ 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---	6793	{ 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---
6794	{ 659, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---	6794	{ 659, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---
6795	{ 658, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	---	6795	{ 658, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	---
6796	{ 657, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	---	6796	{ 657, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	---
6797	{ 656, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	---	6797	{ 656, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	---
6798	{ 655, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	---	6798	{ 655, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	---
6799	{ 654, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	---	6799	{ 654, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	---
6800	{ 653, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	---	6800	{ 653, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	---
6801	{ 652, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	---	6801	{ 652, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	---
6802	{ 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6802	{ 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6803	{ 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6803	{ 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6804	{ 649, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	---	6804	{ 649, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0\|(1ULL<	---
6805	{ 648, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---	6805	{ 648, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---
6806	{ 647, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	---	6806	{ 647, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0\|(1ULL<	---
6807	{ 646, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	---	6807	{ 646, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 496, 0\|(1ULL<	---
6808	{ 645, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---	6808	{ 645, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 494, 0\|(1ULL<	---
6809	{ 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6809	{ 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6810	{ 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6810	{ 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6811	{ 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6811	{ 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6812	{ 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6812	{ 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6813	{ 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6813	{ 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6814	{ 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6814	{ 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6815	{ 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6815	{ 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6816	{ 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6816	{ 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6817	{ 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6817	{ 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6818	{ 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6818	{ 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6819	{ 634, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6819	{ 634, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6820	{ 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6820	{ 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6821	{ 632, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6821	{ 632, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6822	{ 631, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6822	{ 631, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6823	{ 630, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6823	{ 630, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6824	{ 629, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6824	{ 629, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6825	{ 628, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6825	{ 628, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6826	{ 627, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6826	{ 627, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6827	{ 626, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6827	{ 626, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6828	{ 625, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6828	{ 625, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6829	{ 624, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6829	{ 624, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6830	{ 623, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6830	{ 623, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6831	{ 622, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0\|(1ULL<	---	6831	{ 622, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0\|(1ULL<	---
6832	{ 621, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6832	{ 621, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6833	{ 620, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6833	{ 620, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6834	{ 619, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6834	{ 619, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6835	{ 618, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---	6835	{ 618, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 488, 0\|(1ULL<	---
6836	{ 617, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6836	{ 617, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6837	{ 616, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6837	{ 616, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6838	{ 615, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6838	{ 615, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6839	{ 614, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6839	{ 614, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6840	{ 613, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6840	{ 613, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6841	{ 612, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6841	{ 612, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6842	{ 611, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6842	{ 611, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6843	{ 610, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 485, 0\|(1ULL<	---	6843	{ 610, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 485, 0\|(1ULL<	---
6844	{ 609, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 482, 0\|(1ULL<	---	6844	{ 609, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 482, 0\|(1ULL<	---
6845	{ 608, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 479, 0\|(1ULL<	---	6845	{ 608, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 479, 0\|(1ULL<	---
6846	{ 607, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0\|(1ULL<	---	6846	{ 607, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0\|(1ULL<	---
6847	{ 606, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0\|(1ULL<	---	6847	{ 606, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0\|(1ULL<	---
6848	{ 605, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0\|(1ULL<	---	6848	{ 605, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0\|(1ULL<	---
6849	{ 604, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0\|(1ULL<	---	6849	{ 604, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0\|(1ULL<	---
6850	{ 603, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0\|(1ULL<	---	6850	{ 603, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0\|(1ULL<	---
6851	{ 602, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	---	6851	{ 602, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	---
6852	{ 601, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	---	6852	{ 601, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	---
6853	{ 600, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	---	6853	{ 600, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	---
6854	{ 599, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	---	6854	{ 599, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	---
6855	{ 598, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	---	6855	{ 598, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	---
6856	{ 597, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	---	6856	{ 597, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0\|(1ULL<	---
6857	{ 596, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	---	6857	{ 596, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0\|(1ULL<	---
6858	{ 595, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	---	6858	{ 595, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0\|(1ULL<	---
6859	{ 594, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	---	6859	{ 594, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0\|(1ULL<	---
6860	{ 593, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	---	6860	{ 593, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 439, 0\|(1ULL<	---
6861	{ 592, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6861	{ 592, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6862	{ 591, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	6862	{ 591, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
6863	{ 590, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6863	{ 590, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6864	{ 589, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	---	6864	{ 589, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	---
6865	{ 588, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	---	6865	{ 588, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 435, 0\|(1ULL<	---
6866	{ 587, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6866	{ 587, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6867	{ 586, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6867	{ 586, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6868	{ 585, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6868	{ 585, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6869	{ 584, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6869	{ 584, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6870	{ 583, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6870	{ 583, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6871	{ 582, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---	6871	{ 582, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 432, 0\|(1ULL<	---
6872	{ 581, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---	6872	{ 581, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---
6873	{ 580, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---	6873	{ 580, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 429, 0\|(1ULL<	---
6874	{ 579, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6874	{ 579, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6875	{ 578, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6875	{ 578, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6876	{ 577, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6876	{ 577, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6877	{ 576, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6877	{ 576, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6878	{ 575, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---	6878	{ 575, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---
6879	{ 574, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	---	6879	{ 574, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	---
6880	{ 573, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---	6880	{ 573, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---
6881	{ 572, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---	6881	{ 572, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---
6882	{ 571, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	---	6882	{ 571, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 427, 0\|(1ULL<	---
6883	{ 570, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---	6883	{ 570, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 425, 0\|(1ULL<	---
6884	{ 569, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6884	{ 569, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6885	{ 568, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6885	{ 568, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6886	{ 567, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6886	{ 567, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6887	{ 566, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---	6887	{ 566, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 421, 0\|(1ULL<	---
6888	{ 565, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6888	{ 565, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6889	{ 564, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	6889	{ 564, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
6890	{ 563, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	6890	{ 563, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
6891	{ 562, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6891	{ 562, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6892	{ 561, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6892	{ 561, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6893	{ 560, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6893	{ 560, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6894	{ 559, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6894	{ 559, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6895	{ 558, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	6895	{ 558, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
6896	{ 557, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---	6896	{ 557, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 302, 0\|(1ULL<	---
6897	{ 556, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6897	{ 556, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6898	{ 555, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 414, 0\|(1ULL<	---	6898	{ 555, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 414, 0\|(1ULL<	---
6899	{ 554, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 407, 0\|(1ULL<	---	6899	{ 554, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 407, 0\|(1ULL<	---
6900	{ 553, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---	6900	{ 553, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---
6901	{ 552, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---	6901	{ 552, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---
6902	{ 551, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---	6902	{ 551, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---
6903	{ 550, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---	6903	{ 550, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 404, 0\|(1ULL<	---
6904	{ 549, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	6904	{ 549, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
6905	{ 548, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---	6905	{ 548, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---
6906	{ 547, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---	6906	{ 547, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0\|(1ULL<	---
6907	{ 546, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---	6907	{ 546, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 400, 0\|(1ULL<	---
6908	{ 545, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 398, 0\|(1ULL<	---	6908	{ 545, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 398, 0\|(1ULL<	---
6909	{ 544, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6909	{ 544, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6910	{ 543, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6910	{ 543, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6911	{ 542, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6911	{ 542, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6912	{ 541, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6912	{ 541, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6913	{ 540, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6913	{ 540, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6914	{ 539, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---	6914	{ 539, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 395, 0\|(1ULL<	---
6915	{ 538, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6915	{ 538, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6916	{ 537, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6916	{ 537, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6917	{ 536, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6917	{ 536, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6918	{ 535, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	6918	{ 535, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
6919	{ 534, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	6919	{ 534, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
6920	{ 533, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	6920	{ 533, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
6921	{ 532, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	6921	{ 532, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
6922	{ 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6922	{ 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6923	{ 530, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	6923	{ 530, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
6924	{ 529, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	---	6924	{ 529, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	---
6925	{ 528, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	---	6925	{ 528, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	---
6926	{ 527, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	---	6926	{ 527, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 392, 0\|(1ULL<	---
6927	{ 526, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	---	6927	{ 526, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 390, 0\|(1ULL<	---
6928	{ 525, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6928	{ 525, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6929	{ 524, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	6929	{ 524, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
6930	{ 523, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6930	{ 523, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6931	{ 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---	6931	{ 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---
6932	{ 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---	6932	{ 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---
6933	{ 520, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	6933	{ 520, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
6934	{ 519, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6934	{ 519, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6935	{ 518, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6935	{ 518, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6936	{ 517, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---	6936	{ 517, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 388, 0\|(1ULL<	---
6937	{ 516, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---	6937	{ 516, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0\|(1ULL<	---
6938	{ 515, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---	6938	{ 515, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0\|(1ULL<	---
6939	{ 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0\|(1ULL<	---	6939	{ 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0\|(1ULL<	---
6940	{ 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0\|(1ULL<	---	6940	{ 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0\|(1ULL<	---
6941	{ 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0\|(1ULL<	---	6941	{ 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0\|(1ULL<	---
6942	{ 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0\|(1ULL<	---	6942	{ 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0\|(1ULL<	---
6943	{ 510, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 373, 0\|(1ULL<	---	6943	{ 510, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 373, 0\|(1ULL<	---
6944	{ 509, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 136, 0\|(1ULL<	---	6944	{ 509, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 136, 0\|(1ULL<	---
6945	{ 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---	6945	{ 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---
6946	{ 507, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---	6946	{ 507, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---
6947	{ 506, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---	6947	{ 506, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---
6948	{ 505, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	6948	{ 505, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
6949	{ 504, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6949	{ 504, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6950	{ 503, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---	6950	{ 503, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0\|(1ULL<	---
6951	{ 502, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---	6951	{ 502, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0\|(1ULL<	---
6952	{ 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---	6952	{ 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0\|(1ULL<	---
6953	{ 500, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 363, 0\|(1ULL<	---	6953	{ 500, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 363, 0\|(1ULL<	---
6954	{ 499, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6954	{ 499, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6955	{ 498, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0\|(1ULL<	---	6955	{ 498, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0\|(1ULL<	---
6956	{ 497, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6956	{ 497, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6957	{ 496, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0\|(1ULL<	---	6957	{ 496, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0\|(1ULL<	---
6958	{ 495, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0\|(1ULL<	---	6958	{ 495, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0\|(1ULL<	---
6959	{ 494, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	6959	{ 494, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
6960	{ 493, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---	6960	{ 493, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 355, 0\|(1ULL<	---
6961	{ 492, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---	6961	{ 492, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0\|(1ULL<	---
6962	{ 491, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6962	{ 491, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6963	{ 490, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---	6963	{ 490, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 350, 0\|(1ULL<	---
6964	{ 489, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 348, 0\|(1ULL<	---	6964	{ 489, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 348, 0\|(1ULL<	---
6965	{ 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---	6965	{ 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0\|(1ULL<	---
6966	{ 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0\|(1ULL<	---	6966	{ 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0\|(1ULL<	---
6967	{ 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 341, 0\|(1ULL<	---	6967	{ 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 341, 0\|(1ULL<	---
6968	{ 485, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 338, 0\|(1ULL<	---	6968	{ 485, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 338, 0\|(1ULL<	---
6969	{ 484, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0\|(1ULL<	---	6969	{ 484, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0\|(1ULL<	---
6970	{ 483, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0\|(1ULL<	---	6970	{ 483, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0\|(1ULL<	---
6971	{ 482, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	6971	{ 482, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
6972	{ 481, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 327, 0\|(1ULL<	---	6972	{ 481, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 327, 0\|(1ULL<	---
6973	{ 480, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	---	6973	{ 480, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 324, 0\|(1ULL<	---
6974	{ 479, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	---	6974	{ 479, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 321, 0\|(1ULL<	---
6975	{ 478, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	---	6975	{ 478, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 318, 0\|(1ULL<	---
6976	{ 477, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	---	6976	{ 477, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 315, 0\|(1ULL<	---
6977	{ 476, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	---	6977	{ 476, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 312, 0\|(1ULL<	---
6978	{ 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	---	6978	{ 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 309, 0\|(1ULL<	---
6979	{ 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	---	6979	{ 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0\|(1ULL<	---
6980	{ 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---	6980	{ 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 303, 0\|(1ULL<	---
6981	{ 472, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	6981	{ 472, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
6982	{ 471, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---	6982	{ 471, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 181, 0\|(1ULL<	---
6983	{ 470, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---	6983	{ 470, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0\|(1ULL<	---
6984	{ 469, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---	6984	{ 469, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---
6985	{ 468, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---	6985	{ 468, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 181, 0\|(1ULL<	---
6986	{ 467, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	---	6986	{ 467, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	---
6987	{ 466, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	---	6987	{ 466, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 302, 0\|(1ULL<	---
6988	{ 465, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0\|(1ULL<	---	6988	{ 465, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0\|(1ULL<	---
6989	{ 464, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0\|(1ULL<	---	6989	{ 464, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0\|(1ULL<	---
6990	{ 463, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0\|(1ULL<	---	6990	{ 463, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0\|(1ULL<	---
6991	{ 462, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0\|(1ULL<	---	6991	{ 462, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0\|(1ULL<	---
6992	{ 461, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0\|(1ULL<	---	6992	{ 461, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0\|(1ULL<	---
6993	{ 460, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 278, 0\|(1ULL<	---	6993	{ 460, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 278, 0\|(1ULL<	---
6994	{ 459, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 274, 0\|(1ULL<	---	6994	{ 459, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 274, 0\|(1ULL<	---
6995	{ 458, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0\|(1ULL<	---	6995	{ 458, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0\|(1ULL<	---
6996	{ 457, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0\|(1ULL<	---	6996	{ 457, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0\|(1ULL<	---
6997	{ 456, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 262, 0\|(1ULL<	---	6997	{ 456, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 262, 0\|(1ULL<	---
6998	{ 455, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0\|(1ULL<	---	6998	{ 455, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0\|(1ULL<	---
6999	{ 454, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0\|(1ULL<	---	6999	{ 454, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0\|(1ULL<	---
7000	{ 453, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0\|(1ULL<	---	7000	{ 453, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0\|(1ULL<	---
7001	{ 452, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 246, 0\|(1ULL<	---	7001	{ 452, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 246, 0\|(1ULL<	---
7002	{ 451, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 242, 0\|(1ULL<	---	7002	{ 451, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 242, 0\|(1ULL<	---
7003	{ 450, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 240, 0\|(1ULL<	---	7003	{ 450, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 240, 0\|(1ULL<	---
7004	{ 449, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 238, 0\|(1ULL<	---	7004	{ 449, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 238, 0\|(1ULL<	---
7005	{ 448, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	---	7005	{ 448, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	---
7006	{ 447, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	---	7006	{ 447, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	---
7007	{ 446, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	---	7007	{ 446, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 236, 0\|(1ULL<	---
7008	{ 445, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	---	7008	{ 445, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 234, 0\|(1ULL<	---
7009	{ 444, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 231, 0\|(1ULL<	---	7009	{ 444, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 231, 0\|(1ULL<	---
7010	{ 443, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 228, 0\|(1ULL<	---	7010	{ 443, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 228, 0\|(1ULL<	---
7011	{ 442, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7011	{ 442, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7012	{ 441, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7012	{ 441, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7013	{ 440, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	7013	{ 440, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
7014	{ 439, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7014	{ 439, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7015	{ 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	7015	{ 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
7016	{ 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7016	{ 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7017	{ 436, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	7017	{ 436, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
7018	{ 435, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7018	{ 435, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7019	{ 434, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	7019	{ 434, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
7020	{ 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	7020	{ 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
7021	{ 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	7021	{ 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
7022	{ 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---	7022	{ 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 225, 0\|(1ULL<	---
7023	{ 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---	7023	{ 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0\|(1ULL<	---
7024	{ 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7024	{ 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7025	{ 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7025	{ 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7026	{ 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---	7026	{ 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 219, 0\|(1ULL<	---
7027	{ 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---	7027	{ 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 216, 0\|(1ULL<	---
7028	{ 425, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7028	{ 425, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7029	{ 424, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 214, 0\|(1ULL<	---	7029	{ 424, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 214, 0\|(1ULL<	---
7030	{ 423, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 211, 0\|(1ULL<	---	7030	{ 423, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 211, 0\|(1ULL<	---
7031	{ 422, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 208, 0\|(1ULL<	---	7031	{ 422, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 208, 0\|(1ULL<	---
7032	{ 421, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---	7032	{ 421, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---
7033	{ 420, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 206, 0\|(1ULL<	---	7033	{ 420, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 206, 0\|(1ULL<	---
7034	{ 419, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 203, 0\|(1ULL<	---	7034	{ 419, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 203, 0\|(1ULL<	---
7035	{ 418, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 200, 0\|(1ULL<	---	7035	{ 418, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 200, 0\|(1ULL<	---
7036	{ 417, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7036	{ 417, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7037	{ 416, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7037	{ 416, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7038	{ 415, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7038	{ 415, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7039	{ 414, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7039	{ 414, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7040	{ 413, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7040	{ 413, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7041	{ 412, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7041	{ 412, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7042	{ 411, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7042	{ 411, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7043	{ 410, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7043	{ 410, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7044	{ 409, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7044	{ 409, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7045	{ 408, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7045	{ 408, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7046	{ 407, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---	7046	{ 407, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 197, 0\|(1ULL<	---
7047	{ 406, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---	7047	{ 406, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 194, 0\|(1ULL<	---
7048	{ 405, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7048	{ 405, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7049	{ 404, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7049	{ 404, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7050	{ 403, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	7050	{ 403, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
7051	{ 402, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---	7051	{ 402, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 174, 0\|(1ULL<	---
7052	{ 401, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---	7052	{ 401, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---
7053	{ 400, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	---	7053	{ 400, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	---
7054	{ 399, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0\|(1ULL<	---	7054	{ 399, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0\|(1ULL<	---
7055	{ 398, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	---	7055	{ 398, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0\|(1ULL<	---
7056	{ 397, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	---	7056	{ 397, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	---
7057	{ 396, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	---	7057	{ 396, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 182, 0\|(1ULL<	---
7058	{ 395, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 181, 0\|(1ULL<	---	7058	{ 395, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 181, 0\|(1ULL<	---
7059	{ 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7059	{ 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7060	{ 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7060	{ 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7061	{ 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7061	{ 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7062	{ 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7062	{ 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7063	{ 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7063	{ 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7064	{ 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7064	{ 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7065	{ 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7065	{ 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7066	{ 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7066	{ 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7067	{ 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7067	{ 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7068	{ 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7068	{ 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7069	{ 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7069	{ 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7070	{ 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7070	{ 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7071	{ 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7071	{ 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7072	{ 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7072	{ 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7073	{ 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7073	{ 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7074	{ 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7074	{ 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7075	{ 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7075	{ 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7076	{ 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7076	{ 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7077	{ 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7077	{ 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7078	{ 375, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7078	{ 375, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7079	{ 374, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7079	{ 374, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7080	{ 373, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7080	{ 373, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7081	{ 372, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7081	{ 372, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7082	{ 371, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7082	{ 371, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7083	{ 370, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7083	{ 370, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7084	{ 369, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7084	{ 369, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7085	{ 368, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7085	{ 368, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7086	{ 367, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7086	{ 367, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7087	{ 366, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7087	{ 366, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7088	{ 365, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7088	{ 365, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7089	{ 364, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7089	{ 364, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7090	{ 363, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7090	{ 363, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7091	{ 362, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---	7091	{ 362, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0\|(1ULL<	---
7092	{ 361, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---	7092	{ 361, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0\|(1ULL<	---
7093	{ 360, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---	7093	{ 360, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---
7094	{ 359, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---	7094	{ 359, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 174, 0\|(1ULL<	---
7095	{ 358, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---	7095	{ 358, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 174, 0\|(1ULL<	---
7096	{ 357, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7096	{ 357, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7097	{ 356, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7097	{ 356, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7098	{ 355, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7098	{ 355, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7099	{ 354, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7099	{ 354, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7100	{ 353, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7100	{ 353, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7101	{ 352, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7101	{ 352, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7102	{ 351, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7102	{ 351, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7103	{ 350, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7103	{ 350, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7104	{ 349, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7104	{ 349, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7105	{ 348, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7105	{ 348, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7106	{ 347, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7106	{ 347, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7107	{ 346, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7107	{ 346, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7108	{ 345, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7108	{ 345, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7109	{ 344, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7109	{ 344, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7110	{ 343, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7110	{ 343, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7111	{ 342, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7111	{ 342, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7112	{ 341, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7112	{ 341, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7113	{ 340, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7113	{ 340, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7114	{ 339, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7114	{ 339, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7115	{ 338, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7115	{ 338, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7116	{ 337, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7116	{ 337, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7117	{ 336, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7117	{ 336, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7118	{ 335, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7118	{ 335, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7119	{ 334, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7119	{ 334, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7120	{ 333, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7120	{ 333, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7121	{ 332, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7121	{ 332, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7122	{ 331, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7122	{ 331, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7123	{ 330, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7123	{ 330, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7124	{ 329, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7124	{ 329, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7125	{ 328, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7125	{ 328, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7126	{ 327, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7126	{ 327, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7127	{ 326, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7127	{ 326, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7128	{ 325, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7128	{ 325, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7129	{ 324, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7129	{ 324, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7130	{ 323, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7130	{ 323, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7131	{ 322, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7131	{ 322, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7132	{ 321, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7132	{ 321, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7133	{ 320, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7133	{ 320, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7134	{ 319, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7134	{ 319, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7135	{ 318, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7135	{ 318, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7136	{ 317, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7136	{ 317, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7137	{ 316, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7137	{ 316, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7138	{ 315, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7138	{ 315, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7139	{ 314, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7139	{ 314, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7140	{ 313, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7140	{ 313, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7141	{ 312, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7141	{ 312, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7142	{ 311, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7142	{ 311, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7143	{ 310, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7143	{ 310, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7144	{ 309, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7144	{ 309, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7145	{ 308, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7145	{ 308, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7146	{ 307, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7146	{ 307, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7147	{ 306, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7147	{ 306, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7148	{ 305, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7148	{ 305, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7149	{ 304, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7149	{ 304, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7150	{ 303, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7150	{ 303, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7151	{ 302, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7151	{ 302, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7152	{ 301, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7152	{ 301, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7153	{ 300, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7153	{ 300, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7154	{ 299, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7154	{ 299, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7155	{ 298, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7155	{ 298, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7156	{ 297, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7156	{ 297, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7157	{ 296, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7157	{ 296, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7158	{ 295, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7158	{ 295, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7159	{ 294, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7159	{ 294, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7160	{ 293, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7160	{ 293, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7161	{ 292, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7161	{ 292, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7162	{ 291, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7162	{ 291, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7163	{ 290, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7163	{ 290, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7164	{ 289, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7164	{ 289, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7165	{ 288, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7165	{ 288, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7166	{ 287, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7166	{ 287, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7167	{ 286, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7167	{ 286, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7168	{ 285, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7168	{ 285, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7169	{ 284, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7169	{ 284, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7170	{ 283, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7170	{ 283, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7171	{ 282, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7171	{ 282, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7172	{ 281, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7172	{ 281, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7173	{ 280, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7173	{ 280, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7174	{ 279, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7174	{ 279, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7175	{ 278, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7175	{ 278, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7176	{ 277, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7176	{ 277, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7177	{ 276, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7177	{ 276, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7178	{ 275, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7178	{ 275, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7179	{ 274, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---	7179	{ 274, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 171, 0\|(1ULL<	---
7180	{ 273, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7180	{ 273, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7181	{ 272, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7181	{ 272, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7182	{ 271, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---	7182	{ 271, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 165, 0\|(1ULL<	---
7183	{ 270, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---	7183	{ 270, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0\|(1ULL<	---
7184	{ 269, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	---	7184	{ 269, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	---
7185	{ 268, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---	7185	{ 268, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---
7186	{ 267, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	---	7186	{ 267, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	---
7187	{ 266, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	---	7187	{ 266, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 158, 0\|(1ULL<	---
7188	{ 265, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---	7188	{ 265, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---
7189	{ 264, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---	7189	{ 264, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---
7190	{ 263, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	---	7190	{ 263, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0\|(1ULL<	---
7191	{ 262, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---	7191	{ 262, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 147, 0\|(1ULL<	---
7192	{ 261, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---	7192	{ 261, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 144, 0\|(1ULL<	---
7193	{ 260, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---	7193	{ 260, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 141, 0\|(1ULL<	---
7194	{ 259, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---	7194	{ 259, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 138, 0\|(1ULL<	---
7195	{ 258, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	---	7195	{ 258, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	---
7196	{ 257, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	---	7196	{ 257, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0\|(1ULL<	---
7197	{ 256, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---	7197	{ 256, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 136, 0\|(1ULL<	---
7198	{ 255, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	---	7198	{ 255, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	---
7199	{ 254, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	---	7199	{ 254, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0\|(1ULL<	---
7200	{ 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7200	{ 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7201	{ 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7201	{ 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7202	{ 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7202	{ 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7203	{ 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7203	{ 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7204	{ 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7204	{ 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7205	{ 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7205	{ 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7206	{ 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7206	{ 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7207	{ 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7207	{ 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7208	{ 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7208	{ 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7209	{ 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7209	{ 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7210	{ 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7210	{ 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7211	{ 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7211	{ 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7212	{ 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7212	{ 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7213	{ 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---	7213	{ 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---
7214	{ 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---	7214	{ 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---
7215	{ 238, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	---	7215	{ 238, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	---
7216	{ 237, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---	7216	{ 237, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---
7217	{ 236, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---	7217	{ 236, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---
7218	{ 235, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---	7218	{ 235, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---
7219	{ 234, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---	7219	{ 234, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 128, 0\|(1ULL<	---
7220	{ 233, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0\|(1ULL<	---	7220	{ 233, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0\|(1ULL<	---
7221	{ 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7221	{ 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7222	{ 231, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7222	{ 231, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7223	{ 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7223	{ 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7224	{ 229, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---	7224	{ 229, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---
7225	{ 228, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7225	{ 228, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7226	{ 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7226	{ 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7227	{ 226, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7227	{ 226, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7228	{ 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7228	{ 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7229	{ 224, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7229	{ 224, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7230	{ 223, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	---	7230	{ 223, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	---
7231	{ 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7231	{ 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7232	{ 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7232	{ 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7233	{ 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7233	{ 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7234	{ 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7234	{ 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7235	{ 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7235	{ 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7236	{ 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7236	{ 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7237	{ 216, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7237	{ 216, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7238	{ 215, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7238	{ 215, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7239	{ 214, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7239	{ 214, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7240	{ 213, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7240	{ 213, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7241	{ 212, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7241	{ 212, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7242	{ 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7242	{ 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7243	{ 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7243	{ 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7244	{ 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7244	{ 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7245	{ 208, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7245	{ 208, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7246	{ 207, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7246	{ 207, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7247	{ 206, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7247	{ 206, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7248	{ 205, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 122, 0\|(1ULL<	---	7248	{ 205, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 122, 0\|(1ULL<	---
7249	{ 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---	7249	{ 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0\|(1ULL<	---
7250	{ 203, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0\|(1ULL<	---	7250	{ 203, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0\|(1ULL<	---
7251	{ 202, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0\|(1ULL<	---	7251	{ 202, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0\|(1ULL<	---
7252	{ 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7252	{ 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7253	{ 200, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7253	{ 200, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7254	{ 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7254	{ 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7255	{ 198, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7255	{ 198, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7256	{ 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7256	{ 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7257	{ 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7257	{ 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7258	{ 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7258	{ 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7259	{ 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7259	{ 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7260	{ 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7260	{ 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7261	{ 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7261	{ 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7262	{ 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7262	{ 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7263	{ 190, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7263	{ 190, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7264	{ 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7264	{ 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7265	{ 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7265	{ 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7266	{ 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7266	{ 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7267	{ 186, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7267	{ 186, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7268	{ 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7268	{ 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7269	{ 184, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	---	7269	{ 184, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	---
7270	{ 183, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7270	{ 183, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7271	{ 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7271	{ 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7272	{ 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7272	{ 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7273	{ 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7273	{ 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7274	{ 179, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7274	{ 179, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7275	{ 178, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7275	{ 178, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7276	{ 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7276	{ 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7277	{ 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7277	{ 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7278	{ 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7278	{ 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7279	{ 174, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7279	{ 174, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7280	{ 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7280	{ 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7281	{ 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7281	{ 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7282	{ 171, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7282	{ 171, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7283	{ 170, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7283	{ 170, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7284	{ 169, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7284	{ 169, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7285	{ 168, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7285	{ 168, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7286	{ 167, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7286	{ 167, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7287	{ 166, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7287	{ 166, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7288	{ 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7288	{ 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7289	{ 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7289	{ 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7290	{ 163, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---	7290	{ 163, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---
7291	{ 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---	7291	{ 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---
7292	{ 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7292	{ 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7293	{ 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7293	{ 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7294	{ 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7294	{ 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7295	{ 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7295	{ 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7296	{ 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7296	{ 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7297	{ 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7297	{ 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7298	{ 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7298	{ 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7299	{ 154, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7299	{ 154, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7300	{ 153, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7300	{ 153, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7301	{ 152, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7301	{ 152, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7302	{ 151, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---	7302	{ 151, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0\|(1ULL<	---
7303	{ 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7303	{ 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7304	{ 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7304	{ 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7305	{ 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7305	{ 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7306	{ 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7306	{ 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7307	{ 146, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7307	{ 146, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7308	{ 145, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7308	{ 145, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7309	{ 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7309	{ 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7310	{ 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7310	{ 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7311	{ 142, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7311	{ 142, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7312	{ 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7312	{ 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7313	{ 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---	7313	{ 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---
7314	{ 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7314	{ 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7315	{ 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---	7315	{ 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---
7316	{ 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7316	{ 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7317	{ 136, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---	7317	{ 136, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---
7318	{ 135, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7318	{ 135, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7319	{ 134, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---	7319	{ 134, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0\|(1ULL<	---
7320	{ 133, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7320	{ 133, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7321	{ 132, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7321	{ 132, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7322	{ 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	---	7322	{ 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	---
7323	{ 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	---	7323	{ 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0\|(1ULL<	---
7324	{ 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7324	{ 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7325	{ 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7325	{ 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7326	{ 127, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	---	7326	{ 127, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	---
7327	{ 126, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	---	7327	{ 126, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 95, 0\|(1ULL<	---
7328	{ 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7328	{ 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7329	{ 124, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7329	{ 124, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7330	{ 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---	7330	{ 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 92, 0\|(1ULL<	---
7331	{ 122, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7331	{ 122, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7332	{ 121, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---	7332	{ 121, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---
7333	{ 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7333	{ 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7334	{ 119, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	---	7334	{ 119, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0\|(1ULL<	---
7335	{ 118, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---	7335	{ 118, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---
7336	{ 117, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7336	{ 117, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7337	{ 116, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7337	{ 116, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7338	{ 115, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7338	{ 115, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7339	{ 114, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7339	{ 114, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7340	{ 113, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7340	{ 113, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7341	{ 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7341	{ 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7342	{ 111, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7342	{ 111, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7343	{ 110, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---	7343	{ 110, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---
7344	{ 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7344	{ 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7345	{ 108, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	---	7345	{ 108, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	---
7346	{ 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7346	{ 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7347	{ 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7347	{ 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7348	{ 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7348	{ 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7349	{ 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7349	{ 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7350	{ 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7350	{ 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7351	{ 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7351	{ 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7352	{ 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7352	{ 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7353	{ 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7353	{ 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7354	{ 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7354	{ 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7355	{ 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7355	{ 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7356	{ 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7356	{ 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7357	{ 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7357	{ 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7358	{ 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7358	{ 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7359	{ 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7359	{ 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7360	{ 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7360	{ 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7361	{ 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7361	{ 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7362	{ 91, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---	7362	{ 91, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0\|(1ULL<	---
7363	{ 90, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---	7363	{ 90, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0\|(1ULL<	---
7364	{ 89, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0\|(1ULL<	---	7364	{ 89, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0\|(1ULL<	---
7365	{ 88, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0\|(1ULL<	---	7365	{ 88, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0\|(1ULL<	---
7366	{ 87, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7366	{ 87, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7367	{ 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---	7367	{ 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---
7368	{ 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---	7368	{ 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---
7369	{ 84, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---	7369	{ 84, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0\|(1ULL<	---
7370	{ 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7370	{ 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7371	{ 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7371	{ 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7372	{ 81, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7372	{ 81, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7373	{ 80, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---	7373	{ 80, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---
7374	{ 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7374	{ 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7375	{ 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7375	{ 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7376	{ 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7376	{ 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7377	{ 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7377	{ 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7378	{ 75, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	---	7378	{ 75, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0\|(1ULL<	---
7379	{ 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7379	{ 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7380	{ 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---	7380	{ 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0\|(1ULL<	---
7381	{ 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7381	{ 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7382	{ 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7382	{ 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7383	{ 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7383	{ 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7384	{ 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7384	{ 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7385	{ 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7385	{ 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7386	{ 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7386	{ 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7387	{ 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7387	{ 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7388	{ 65, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0\|(1ULL<	---	7388	{ 65, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0\|(1ULL<	---
7389	{ 64, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---	7389	{ 64, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0\|(1ULL<	---
7390	{ 63, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	---	7390	{ 63, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0\|(1ULL<	---
7391	{ 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7391	{ 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7392	{ 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7392	{ 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7393	{ 60, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---	7393	{ 60, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0\|(1ULL<	---
7394	{ 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---	7394	{ 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---
7395	{ 58, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---	7395	{ 58, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0\|(1ULL<	---
7396	{ 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7396	{ 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7397	{ 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7397	{ 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7398	{ 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7398	{ 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7399	{ 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---	7399	{ 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---
7400	{ 53, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---	7400	{ 53, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0\|(1ULL<	---
7401	{ 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7401	{ 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7402	{ 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7402	{ 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7403	{ 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7403	{ 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7404	{ 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7404	{ 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7405	{ 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7405	{ 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7406	{ 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7406	{ 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7407	{ 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---	7407	{ 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0\|(1ULL<	---
7408	{ 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---	7408	{ 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---
7409	{ 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---	7409	{ 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---
7410	{ 43, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---	7410	{ 43, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0\|(1ULL<	---
7411	{ 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7411	{ 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7412	{ 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7412	{ 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7413	{ 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0\|(1ULL<	---	7413	{ 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0\|(1ULL<	---
7414	{ 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0\|(1ULL<	---	7414	{ 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0\|(1ULL<	---
7415	{ 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7415	{ 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7416	{ 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7416	{ 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7417	{ 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7417	{ 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7418	{ 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7418	{ 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7419	{ 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7419	{ 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7420	{ 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7420	{ 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7421	{ 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0\|(1ULL<	---	7421	{ 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0\|(1ULL<	---
7422	{ 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7422	{ 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7423	{ 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0\|(1ULL<	---	7423	{ 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0\|(1ULL<	---
7424	{ 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7424	{ 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7425	{ 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0\|(1ULL<	---	7425	{ 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0\|(1ULL<	---
7426	{ 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0\|(1ULL<	---	7426	{ 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0\|(1ULL<	---
7427	{ 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7427	{ 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7428	{ 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	---	7428	{ 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0\|(1ULL<	---
7429	{ 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0\|(1ULL<	---	7429	{ 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0\|(1ULL<	---
7430	{ 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0\|(1ULL<	---	7430	{ 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0\|(1ULL<	---
7431	{ 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7431	{ 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7432	{ 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7432	{ 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7433	{ 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7433	{ 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7434	{ 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---	7434	{ 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---
7435	{ 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---	7435	{ 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0\|(1ULL<	---
7436	{ 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7436	{ 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7437	{ 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7437	{ 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7438	{ 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7438	{ 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7439	{ 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7439	{ 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7440	{ 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7440	{ 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7441	{ 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---	7441	{ 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---
7442	{ 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0\|(1ULL<	---	7442	{ 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0\|(1ULL<	---
7443	{ 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7443	{ 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7444	{ 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0\|(1ULL<	---	7444	{ 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0\|(1ULL<	---
7445	{ 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---	7445	{ 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0\|(1ULL<	---
7446	{ 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7446	{ 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7447	{ 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7447	{ 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7448	{ 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7448	{ 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7449	{ 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7449	{ 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7450	{ 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7450	{ 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7451	{ 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7451	{ 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7452	{ 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---	7452	{ 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0\|(1ULL<	---
7453	{ 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---	7453	{ 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0\|(1ULL<	---
7454	}, {	---	7454	}, {	---
7455	/* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7455	/* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7456	/* 1 */	---	7456	/* 1 */	---
7457	/* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7457	/* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7458	/* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7458	/* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7459	/* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7459	/* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7460	/* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7460	/* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7461	/* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7461	/* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7462	/* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7462	/* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7463	/* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },	---	7463	/* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },	---
7464	/* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7464	/* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7465	/* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7465	/* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7466	/* 29 */ { 0, 0\|(1<	---	7466	/* 29 */ { 0, 0\|(1<	---
7467	/* 30 */ { 0, 0\|(1<	---	7467	/* 30 */ { 0, 0\|(1<	---
7468	/* 33 */ { 0, 0\|(1<	---	7468	/* 33 */ { 0, 0\|(1<	---
7469	/* 35 */ { 0, 0\|(1<	---	7469	/* 35 */ { 0, 0\|(1<	---
7470	/* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	---	7470	/* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	---
7471	/* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---	7471	/* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---
7472	/* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7472	/* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7473	/* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7473	/* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7474	/* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7474	/* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7475	/* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7475	/* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7476	/* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---	7476	/* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---
7477	/* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7477	/* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7478	/* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---	7478	/* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---
7479	/* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7479	/* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7480	/* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7480	/* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7481	/* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7481	/* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7482	/* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7482	/* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7483	/* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7483	/* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7484	/* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7484	/* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7485	/* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7485	/* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7486	/* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7486	/* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7487	/* 92 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7487	/* 92 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7488	/* 95 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7488	/* 95 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7489	/* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7489	/* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7490	/* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7490	/* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7491	/* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---	7491	/* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---
7492	/* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7492	/* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7493	/* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	---	7493	/* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	---
7494	/* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	---	7494	/* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },	---
7495	/* 122 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7495	/* 122 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7496	/* 126 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---	7496	/* 126 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },	---
7497	/* 128 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---	7497	/* 128 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },	---
7498	/* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---	7498	/* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },	---
7499	/* 136 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7499	/* 136 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7500	/* 138 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7500	/* 138 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7501	/* 141 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7501	/* 141 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7502	/* 144 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7502	/* 144 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7503	/* 147 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7503	/* 147 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7504	/* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7504	/* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7505	/* 158 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7505	/* 158 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7506	/* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7506	/* 162 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7507	/* 165 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7507	/* 165 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7508	/* 171 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7508	/* 171 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7509	/* 174 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7509	/* 174 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7510	/* 175 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7510	/* 175 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7511	/* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7511	/* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7512	/* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7512	/* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7513	/* 182 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7513	/* 182 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7514	/* 186 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7514	/* 186 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7515	/* 190 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7515	/* 190 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7516	/* 194 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7516	/* 194 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7517	/* 197 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7517	/* 197 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7518	/* 200 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7518	/* 200 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7519	/* 203 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7519	/* 203 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7520	/* 206 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7520	/* 206 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7521	/* 208 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7521	/* 208 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7522	/* 211 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7522	/* 211 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7523	/* 214 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7523	/* 214 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7524	/* 216 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7524	/* 216 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7525	/* 219 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7525	/* 219 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7526	/* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7526	/* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7527	/* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7527	/* 225 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7528	/* 228 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7528	/* 228 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7529	/* 231 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7529	/* 231 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7530	/* 234 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7530	/* 234 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7531	/* 236 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7531	/* 236 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7532	/* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7532	/* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7533	/* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7533	/* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7534	/* 242 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7534	/* 242 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7535	/* 246 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7535	/* 246 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7536	/* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7536	/* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7537	/* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7537	/* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7538	/* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7538	/* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7539	/* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7539	/* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7540	/* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7540	/* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7541	/* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7541	/* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7542	/* 274 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7542	/* 274 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7543	/* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7543	/* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7544	/* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7544	/* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7545	/* 286 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7545	/* 286 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7546	/* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7546	/* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7547	/* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7547	/* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7548	/* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7548	/* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7549	/* 302 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7549	/* 302 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7550	/* 303 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7550	/* 303 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7551	/* 306 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7551	/* 306 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7552	/* 309 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7552	/* 309 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7553	/* 312 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7553	/* 312 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7554	/* 315 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7554	/* 315 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7555	/* 318 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7555	/* 318 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7556	/* 321 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7556	/* 321 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7557	/* 324 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7557	/* 324 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7558	/* 327 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7558	/* 327 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7559	/* 331 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7559	/* 331 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7560	/* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7560	/* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7561	/* 338 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7561	/* 338 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7562	/* 341 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7562	/* 341 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7563	/* 343 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7563	/* 343 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7564	/* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	---	7564	/* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0\|(1<	---
7565	/* 348 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7565	/* 348 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7566	/* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7566	/* 350 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7567	/* 352 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7567	/* 352 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7568	/* 355 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7568	/* 355 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7569	/* 357 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7569	/* 357 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7570	/* 359 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7570	/* 359 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7571	/* 361 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7571	/* 361 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7572	/* 363 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7572	/* 363 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7573	/* 366 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7573	/* 366 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7574	/* 368 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7574	/* 368 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7575	/* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7575	/* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7576	/* 373 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7576	/* 373 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7577	/* 375 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7577	/* 375 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7578	/* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7578	/* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7579	/* 379 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7579	/* 379 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7580	/* 381 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7580	/* 381 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7581	/* 383 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7581	/* 383 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7582	/* 385 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7582	/* 385 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7583	/* 388 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7583	/* 388 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7584	/* 390 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7584	/* 390 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7585	/* 392 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7585	/* 392 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7586	/* 395 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7586	/* 395 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7587	/* 398 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7587	/* 398 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7588	/* 400 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7588	/* 400 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7589	/* 402 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7589	/* 402 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7590	/* 404 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7590	/* 404 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7591	/* 407 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7591	/* 407 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7592	/* 414 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7592	/* 414 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7593	/* 421 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7593	/* 421 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7594	/* 425 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7594	/* 425 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7595	/* 427 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7595	/* 427 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7596	/* 429 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7596	/* 429 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7597	/* 432 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7597	/* 432 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7598	/* 435 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7598	/* 435 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7599	/* 439 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7599	/* 439 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7600	/* 443 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7600	/* 443 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7601	/* 447 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7601	/* 447 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7602	/* 451 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7602	/* 451 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7603	/* 455 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7603	/* 455 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7604	/* 459 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7604	/* 459 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7605	/* 463 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7605	/* 463 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7606	/* 467 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7606	/* 467 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7607	/* 471 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7607	/* 471 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7608	/* 475 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7608	/* 475 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7609	/* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7609	/* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7610	/* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7610	/* 482 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7611	/* 485 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7611	/* 485 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7612	/* 488 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7612	/* 488 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7613	/* 491 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7613	/* 491 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7614	/* 494 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7614	/* 494 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7615	/* 496 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7615	/* 496 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7616	/* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7616	/* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7617	/* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7617	/* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7618	/* 502 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7618	/* 502 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7619	/* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7619	/* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7620	/* 511 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7620	/* 511 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7621	/* 516 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7621	/* 516 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7622	/* 519 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7622	/* 519 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7623	/* 521 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7623	/* 521 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7624	/* 523 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7624	/* 523 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7625	/* 526 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7625	/* 526 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7626	/* 529 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7626	/* 529 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7627	/* 532 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7627	/* 532 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7628	/* 535 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7628	/* 535 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7629	/* 538 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7629	/* 538 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7630	/* 541 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7630	/* 541 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7631	/* 544 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7631	/* 544 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7632	/* 547 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7632	/* 547 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7633	/* 550 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7633	/* 550 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7634	/* 553 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7634	/* 553 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7635	/* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7635	/* 557 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7636	/* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7636	/* 560 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7637	/* 564 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7637	/* 564 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7638	/* 566 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7638	/* 566 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7639	/* 569 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7639	/* 569 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7640	/* 572 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7640	/* 572 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7641	/* 575 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7641	/* 575 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7642	/* 578 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7642	/* 578 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7643	/* 580 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7643	/* 580 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7644	/* 582 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7644	/* 582 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7645	/* 584 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7645	/* 584 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7646	/* 586 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7646	/* 586 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7647	/* 590 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7647	/* 590 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7648	/* 594 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7648	/* 594 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7649	/* 598 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7649	/* 598 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7650	/* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7650	/* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7651	/* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7651	/* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7652	/* 608 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7652	/* 608 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7653	/* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7653	/* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7654	/* 612 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7654	/* 612 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7655	/* 614 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---	7655	/* 614 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },	---
7656	/* 616 */ { 0, 0\|(1<	---	7656	/* 616 */ { 0, 0\|(1<	---
7657	/* 619 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7657	/* 619 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7658	/* 621 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7658	/* 621 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7659	/* 623 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7659	/* 623 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7660	/* 625 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7660	/* 625 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7661	/* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7661	/* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7662	/* 629 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7662	/* 629 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7663	/* 631 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7663	/* 631 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7664	/* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7664	/* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7665	/* 635 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7665	/* 635 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7666	/* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7666	/* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7667	/* 643 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7667	/* 643 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7668	/* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7668	/* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7669	/* 650 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7669	/* 650 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7670	/* 653 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7670	/* 653 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7671	/* 656 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7671	/* 656 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7672	/* 659 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7672	/* 659 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7673	/* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7673	/* 662 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7674	/* 665 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7674	/* 665 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7675	/* 668 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7675	/* 668 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7676	/* 670 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7676	/* 670 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7677	/* 672 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7677	/* 672 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7678	/* 674 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7678	/* 674 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7679	/* 676 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7679	/* 676 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7680	/* 679 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7680	/* 679 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7681	/* 682 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7681	/* 682 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7682	/* 685 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7682	/* 685 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7683	/* 688 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7683	/* 688 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7684	/* 691 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7684	/* 691 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7685	/* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7685	/* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7686	/* 700 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7686	/* 700 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7687	/* 703 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7687	/* 703 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7688	/* 705 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7688	/* 705 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7689	/* 708 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7689	/* 708 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7690	/* 711 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7690	/* 711 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7691	/* 714 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7691	/* 714 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7692	/* 717 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7692	/* 717 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7693	/* 720 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7693	/* 720 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7694	/* 723 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7694	/* 723 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7695	/* 727 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7695	/* 727 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7696	/* 731 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7696	/* 731 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7697	/* 735 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7697	/* 735 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7698	/* 739 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7698	/* 739 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7699	/* 742 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7699	/* 742 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7700	/* 744 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7700	/* 744 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7701	/* 747 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7701	/* 747 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7702	/* 750 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7702	/* 750 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7703	/* 752 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7703	/* 752 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7704	/* 755 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7704	/* 755 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7705	/* 758 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7705	/* 758 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7706	/* 761 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7706	/* 761 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7707	/* 764 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7707	/* 764 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7708	/* 767 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7708	/* 767 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7709	/* 770 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7709	/* 770 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7710	/* 773 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7710	/* 773 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7711	/* 775 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7711	/* 775 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7712	/* 777 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7712	/* 777 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7713	/* 779 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7713	/* 779 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7714	/* 781 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7714	/* 781 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7715	/* 783 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7715	/* 783 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7716	/* 785 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7716	/* 785 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7717	/* 790 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7717	/* 790 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7718	/* 794 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7718	/* 794 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7719	/* 798 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7719	/* 798 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7720	/* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7720	/* 802 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7721	/* 806 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7721	/* 806 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7722	/* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7722	/* 809 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7723	/* 814 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7723	/* 814 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7724	/* 819 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7724	/* 819 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7725	/* 824 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7725	/* 824 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7726	/* 829 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7726	/* 829 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7727	/* 830 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	---	7727	/* 830 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	---
7728	/* 833 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7728	/* 833 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7729	/* 836 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7729	/* 836 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7730	/* 839 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7730	/* 839 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7731	/* 842 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },	---	7731	/* 842 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },	---
7732	/* 845 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7732	/* 845 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7733	/* 848 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7733	/* 848 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7734	/* 850 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7734	/* 850 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7735	/* 852 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7735	/* 852 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7736	/* 854 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7736	/* 854 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7737	/* 856 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7737	/* 856 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7738	/* 860 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7738	/* 860 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7739	/* 863 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7739	/* 863 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7740	/* 866 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7740	/* 866 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7741	/* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7741	/* 869 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7742	/* 872 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7742	/* 872 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7743	/* 875 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7743	/* 875 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7744	/* 878 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7744	/* 878 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7745	/* 881 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7745	/* 881 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7746	/* 884 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7746	/* 884 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7747	/* 887 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7747	/* 887 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7748	/* 890 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0\|(1<	---	7748	/* 890 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0\|(1<	---
7749	/* 893 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7749	/* 893 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7750	/* 897 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0\|(1<	---	7750	/* 897 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0\|(1<	---
7751	/* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7751	/* 900 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7752	/* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0\|(1<	---	7752	/* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0\|(1<	---
7753	/* 907 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---	7753	/* 907 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0\|(1<	---
7754	/* 910 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7754	/* 910 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7755	/* 913 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---	7755	/* 913 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },	---
7756	/* 916 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7756	/* 916 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7757	/* 920 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7757	/* 920 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7758	/* 924 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7758	/* 924 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7759	/* 928 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7759	/* 928 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7760	/* 932 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7760	/* 932 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7761	/* 936 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7761	/* 936 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7762	/* 938 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7762	/* 938 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7763	/* 941 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7763	/* 941 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7764	/* 943 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7764	/* 943 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7765	/* 948 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7765	/* 948 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7766	/* 952 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7766	/* 952 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7767	/* 954 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7767	/* 954 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7768	/* 958 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7768	/* 958 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7769	/* 962 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7769	/* 962 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7770	/* 966 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7770	/* 966 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7771	/* 970 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7771	/* 970 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7772	/* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7772	/* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7773	/* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7773	/* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7774	/* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7774	/* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7775	/* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7775	/* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7776	/* 990 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7776	/* 990 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7777	/* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7777	/* 994 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7778	/* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7778	/* 998 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7779	/* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7779	/* 1002 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7780	/* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7780	/* 1006 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7781	/* 1010 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7781	/* 1010 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7782	/* 1013 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7782	/* 1013 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7783	/* 1016 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7783	/* 1016 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7784	/* 1019 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7784	/* 1019 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7785	/* 1021 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7785	/* 1021 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7786	/* 1024 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7786	/* 1024 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7787	/* 1026 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7787	/* 1026 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7788	/* 1028 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7788	/* 1028 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7789	/* 1030 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7789	/* 1030 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7790	/* 1032 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7790	/* 1032 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7791	/* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7791	/* 1034 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7792	/* 1036 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7792	/* 1036 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7793	/* 1039 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7793	/* 1039 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7794	/* 1043 */ { 0, 0\|(1<	---	7794	/* 1043 */ { 0, 0\|(1<	---
7795	/* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7795	/* 1046 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7796	/* 1049 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7796	/* 1049 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7797	/* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7797	/* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7798	/* 1054 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7798	/* 1054 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7799	/* 1056 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	---	7799	/* 1056 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0\|(1<	---
7800	/* 1059 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---	7800	/* 1059 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---
7801	/* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---	7801	/* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---
7802	/* 1067 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---	7802	/* 1067 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---
7803	/* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---	7803	/* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0\|(1<	---
7804	/* 1075 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7804	/* 1075 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7805	/* 1079 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7805	/* 1079 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7806	/* 1082 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7806	/* 1082 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7807	/* 1085 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7807	/* 1085 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7808	/* 1088 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7808	/* 1088 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7809	/* 1092 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7809	/* 1092 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7810	/* 1096 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7810	/* 1096 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7811	/* 1100 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7811	/* 1100 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7812	/* 1104 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7812	/* 1104 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7813	/* 1107 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---	7813	/* 1107 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },	---
7814	/* 1110 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7814	/* 1110 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7815	/* 1113 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7815	/* 1113 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7816	/* 1116 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7816	/* 1116 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7817	/* 1119 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---	7817	/* 1119 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },	---
7818	/* 1122 */ { 0, 0\|(1<	---	7818	/* 1122 */ { 0, 0\|(1<	---
7819	/* 1124 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---	7819	/* 1124 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },	---
7820	}, {	---	7820	}, {	---
7821	/* 0 */	---	7821	/* 0 */	---
7822	/* 0 */ Mips::SP, Mips::SP,	---	7822	/* 0 */ Mips::SP, Mips::SP,	---
7823	/* 2 */ Mips::AT,	---	7823	/* 2 */ Mips::AT,	---
7824	/* 3 */ Mips::RA,	---	7824	/* 3 */ Mips::RA,	---
7825	/* 4 */ Mips::DSPPos,	---	7825	/* 4 */ Mips::DSPPos,	---
7826	/* 5 */ Mips::V0, Mips::V1,	---	7826	/* 5 */ Mips::V0, Mips::V1,	---
7827	/* 7 */ Mips::HI0, Mips::LO0,	---	7827	/* 7 */ Mips::HI0, Mips::LO0,	---
7828	/* 9 */ Mips::T8,	---	7828	/* 9 */ Mips::T8,	---
7829	/* 10 */ Mips::DSPOutFlag20,	---	7829	/* 10 */ Mips::DSPOutFlag20,	---
7830	/* 11 */ Mips::DSPCarry,	---	7830	/* 11 */ Mips::DSPCarry,	---
7831	/* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,	---	7831	/* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,	---
7832	/* 14 */ Mips::DSPCCond,	---	7832	/* 14 */ Mips::DSPCCond,	---
7833	/* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,	---	7833	/* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,	---
7834	/* 20 */ Mips::HI0_64, Mips::LO0_64,	---	7834	/* 20 */ Mips::HI0_64, Mips::LO0_64,	---
7835	/* 22 */ Mips::DSPOutFlag16_19,	---	7835	/* 22 */ Mips::DSPOutFlag16_19,	---
7836	/* 23 */ Mips::DSPPos, Mips::DSPEFI,	---	7836	/* 23 */ Mips::DSPPos, Mips::DSPEFI,	---
7837	/* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,	---	7837	/* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,	---
7838	/* 28 */ Mips::DSPOutFlag23,	---	7838	/* 28 */ Mips::DSPOutFlag23,	---
7839	/* 29 */ Mips::FCC0,	---	7839	/* 29 */ Mips::FCC0,	---
7840	/* 30 */ Mips::DSPPos, Mips::DSPSCount,	---	7840	/* 30 */ Mips::DSPPos, Mips::DSPSCount,	---
7841	/* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,	---	7841	/* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,	---
7842	/* 36 */ Mips::AC0,	---	7842	/* 36 */ Mips::AC0,	---
7843	/* 37 */ Mips::AC0_64,	---	7843	/* 37 */ Mips::AC0_64,	---
7844	/* 38 */ Mips::HI0,	---	7844	/* 38 */ Mips::HI0,	---
7845	/* 39 */ Mips::HI0_64,	---	7845	/* 39 */ Mips::HI0_64,	---
7846	/* 40 */ Mips::LO0,	---	7846	/* 40 */ Mips::LO0,	---
7847	/* 41 */ Mips::LO0_64,	---	7847	/* 41 */ Mips::LO0_64,	---
7848	/* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,	---	7848	/* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,	---
7849	/* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,	---	7849	/* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,	---
7850	/* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	---	7850	/* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	---
7851	/* 54 */ Mips::P0,	---	7851	/* 54 */ Mips::P0,	---
7852	/* 55 */ Mips::P1,	---	7852	/* 55 */ Mips::P1,	---
7853	/* 56 */ Mips::P2,	---	7853	/* 56 */ Mips::P2,	---
7854	/* 57 */ Mips::DSPOutFlag21,	---	7854	/* 57 */ Mips::DSPOutFlag21,	---
7855	/* 58 */ Mips::DSPOutFlag22,	---	7855	/* 58 */ Mips::DSPOutFlag22,	---
7856	/* 59 */ Mips::P0, Mips::P1, Mips::P2,	---	7856	/* 59 */ Mips::P0, Mips::P1, Mips::P2,	---
7857	/* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	---	7857	/* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,	---
7858	}	---	7858	}	---
7859	};	---	7859	};	---
7860		---	7860		---
7861		---	7861		---
7862	#ifdef __GNUC__	---	7862	#ifdef __GNUC__	---
7863	#pragma GCC diagnostic push	---	7863	#pragma GCC diagnostic push	---
7864	#pragma GCC diagnostic ignored "-Woverlength-strings"	---	7864	#pragma GCC diagnostic ignored "-Woverlength-strings"	---
7865	#endif	---	7865	#endif	---
7866	extern const char MipsInstrNameData[] = {	---	7866	extern const char MipsInstrNameData[] = {	---
7867	/* 0 */ "G_FLOG10\0"	---	7867	/* 0 */ "G_FLOG10\0"	---
7868	/* 9 */ "DMFC0\0"	---	7868	/* 9 */ "DMFC0\0"	---
7869	/* 15 */ "DMFGC0\0"	---	7869	/* 15 */ "DMFGC0\0"	---
7870	/* 22 */ "MFHGC0\0"	---	7870	/* 22 */ "MFHGC0\0"	---
7871	/* 29 */ "MTHGC0\0"	---	7871	/* 29 */ "MTHGC0\0"	---
7872	/* 36 */ "DMTGC0\0"	---	7872	/* 36 */ "DMTGC0\0"	---
7873	/* 43 */ "MFTC0\0"	---	7873	/* 43 */ "MFTC0\0"	---
7874	/* 49 */ "DMTC0\0"	---	7874	/* 49 */ "DMTC0\0"	---
7875	/* 55 */ "MTTC0\0"	---	7875	/* 55 */ "MTTC0\0"	---
7876	/* 61 */ "VMM0\0"	---	7876	/* 61 */ "VMM0\0"	---
7877	/* 66 */ "MTM0\0"	---	7877	/* 66 */ "MTM0\0"	---
7878	/* 71 */ "MTP0\0"	---	7878	/* 71 */ "MTP0\0"	---
7879	/* 76 */ "BBIT0\0"	---	7879	/* 76 */ "BBIT0\0"	---
7880	/* 82 */ "LDC1\0"	---	7880	/* 82 */ "LDC1\0"	---
7881	/* 87 */ "SDC1\0"	---	7881	/* 87 */ "SDC1\0"	---
7882	/* 92 */ "CFC1\0"	---	7882	/* 92 */ "CFC1\0"	---
7883	/* 97 */ "DMFC1\0"	---	7883	/* 97 */ "DMFC1\0"	---
7884	/* 103 */ "MFTHC1\0"	---	7884	/* 103 */ "MFTHC1\0"	---
7885	/* 110 */ "MTTHC1\0"	---	7885	/* 110 */ "MTTHC1\0"	---
7886	/* 117 */ "CTC1\0"	---	7886	/* 117 */ "CTC1\0"	---
7887	/* 122 */ "CFTC1\0"	---	7887	/* 122 */ "CFTC1\0"	---
7888	/* 128 */ "MFTC1\0"	---	7888	/* 128 */ "MFTC1\0"	---
7889	/* 134 */ "DMTC1\0"	---	7889	/* 134 */ "DMTC1\0"	---
7890	/* 140 */ "CTTC1\0"	---	7890	/* 140 */ "CTTC1\0"	---
7891	/* 146 */ "MTTC1\0"	---	7891	/* 146 */ "MTTC1\0"	---
7892	/* 152 */ "LWC1\0"	---	7892	/* 152 */ "LWC1\0"	---
7893	/* 157 */ "SWC1\0"	---	7893	/* 157 */ "SWC1\0"	---
7894	/* 162 */ "LDXC1\0"	---	7894	/* 162 */ "LDXC1\0"	---
7895	/* 168 */ "SDXC1\0"	---	7895	/* 168 */ "SDXC1\0"	---
7896	/* 174 */ "LUXC1\0"	---	7896	/* 174 */ "LUXC1\0"	---
7897	/* 180 */ "SUXC1\0"	---	7897	/* 180 */ "SUXC1\0"	---
7898	/* 186 */ "LWXC1\0"	---	7898	/* 186 */ "LWXC1\0"	---
7899	/* 192 */ "SWXC1\0"	---	7899	/* 192 */ "SWXC1\0"	---
7900	/* 198 */ "MTM1\0"	---	7900	/* 198 */ "MTM1\0"	---
7901	/* 203 */ "SDC1_M1\0"	---	7901	/* 203 */ "SDC1_M1\0"	---
7902	/* 211 */ "MTP1\0"	---	7902	/* 211 */ "MTP1\0"	---
7903	/* 216 */ "BBIT1\0"	---	7903	/* 216 */ "BBIT1\0"	---
7904	/* 222 */ "BBIT032\0"	---	7904	/* 222 */ "BBIT032\0"	---
7905	/* 230 */ "BBIT132\0"	---	7905	/* 230 */ "BBIT132\0"	---
7906	/* 238 */ "DSRA32\0"	---	7906	/* 238 */ "DSRA32\0"	---
7907	/* 245 */ "MFHC1_D32\0"	---	7907	/* 245 */ "MFHC1_D32\0"	---
7908	/* 255 */ "MTHC1_D32\0"	---	7908	/* 255 */ "MTHC1_D32\0"	---
7909	/* 265 */ "FSUB_D32\0"	---	7909	/* 265 */ "FSUB_D32\0"	---
7910	/* 274 */ "NMSUB_D32\0"	---	7910	/* 274 */ "NMSUB_D32\0"	---
7911	/* 284 */ "FADD_D32\0"	---	7911	/* 284 */ "FADD_D32\0"	---
7912	/* 293 */ "NMADD_D32\0"	---	7912	/* 293 */ "NMADD_D32\0"	---
7913	/* 303 */ "C_NGE_D32\0"	---	7913	/* 303 */ "C_NGE_D32\0"	---
7914	/* 313 */ "C_NGLE_D32\0"	---	7914	/* 313 */ "C_NGLE_D32\0"	---
7915	/* 324 */ "C_OLE_D32\0"	---	7915	/* 324 */ "C_OLE_D32\0"	---
7916	/* 334 */ "C_ULE_D32\0"	---	7916	/* 334 */ "C_ULE_D32\0"	---
7917	/* 344 */ "C_LE_D32\0"	---	7917	/* 344 */ "C_LE_D32\0"	---
7918	/* 353 */ "C_SF_D32\0"	---	7918	/* 353 */ "C_SF_D32\0"	---
7919	/* 362 */ "MOVF_D32\0"	---	7919	/* 362 */ "MOVF_D32\0"	---
7920	/* 371 */ "C_F_D32\0"	---	7920	/* 371 */ "C_F_D32\0"	---
7921	/* 379 */ "PseudoSELECTFP_F_D32\0"	---	7921	/* 379 */ "PseudoSELECTFP_F_D32\0"	---
7922	/* 400 */ "FNEG_D32\0"	---	7922	/* 400 */ "FNEG_D32\0"	---
7923	/* 409 */ "MOVN_I_D32\0"	---	7923	/* 409 */ "MOVN_I_D32\0"	---
7924	/* 420 */ "MOVZ_I_D32\0"	---	7924	/* 420 */ "MOVZ_I_D32\0"	---
7925	/* 431 */ "C_NGL_D32\0"	---	7925	/* 431 */ "C_NGL_D32\0"	---
7926	/* 441 */ "FMUL_D32\0"	---	7926	/* 441 */ "FMUL_D32\0"	---
7927	/* 450 */ "LDC1_MM_D32\0"	---	7927	/* 450 */ "LDC1_MM_D32\0"	---
7928	/* 462 */ "SDC1_MM_D32\0"	---	7928	/* 462 */ "SDC1_MM_D32\0"	---
7929	/* 474 */ "C_UN_D32\0"	---	7929	/* 474 */ "C_UN_D32\0"	---
7930	/* 483 */ "RECIP_D32\0"	---	7930	/* 483 */ "RECIP_D32\0"	---
7931	/* 493 */ "FCMP_D32\0"	---	7931	/* 493 */ "FCMP_D32\0"	---
7932	/* 502 */ "C_SEQ_D32\0"	---	7932	/* 502 */ "C_SEQ_D32\0"	---
7933	/* 512 */ "C_UEQ_D32\0"	---	7933	/* 512 */ "C_UEQ_D32\0"	---
7934	/* 522 */ "C_EQ_D32\0"	---	7934	/* 522 */ "C_EQ_D32\0"	---
7935	/* 531 */ "FABS_D32\0"	---	7935	/* 531 */ "FABS_D32\0"	---
7936	/* 540 */ "CVT_S_D32\0"	---	7936	/* 540 */ "CVT_S_D32\0"	---
7937	/* 550 */ "PseudoSELECT_D32\0"	---	7937	/* 550 */ "PseudoSELECT_D32\0"	---
7938	/* 567 */ "C_NGT_D32\0"	---	7938	/* 567 */ "C_NGT_D32\0"	---
7939	/* 577 */ "C_OLT_D32\0"	---	7939	/* 577 */ "C_OLT_D32\0"	---
7940	/* 587 */ "C_ULT_D32\0"	---	7940	/* 587 */ "C_ULT_D32\0"	---
7941	/* 597 */ "C_LT_D32\0"	---	7941	/* 597 */ "C_LT_D32\0"	---
7942	/* 606 */ "FSQRT_D32\0"	---	7942	/* 606 */ "FSQRT_D32\0"	---
7943	/* 616 */ "RSQRT_D32\0"	---	7943	/* 616 */ "RSQRT_D32\0"	---
7944	/* 626 */ "MOVT_D32\0"	---	7944	/* 626 */ "MOVT_D32\0"	---
7945	/* 635 */ "PseudoSELECTFP_T_D32\0"	---	7945	/* 635 */ "PseudoSELECTFP_T_D32\0"	---
7946	/* 656 */ "FDIV_D32\0"	---	7946	/* 656 */ "FDIV_D32\0"	---
7947	/* 665 */ "FMOV_D32\0"	---	7947	/* 665 */ "FMOV_D32\0"	---
7948	/* 674 */ "PseudoTRUNC_W_D32\0"	---	7948	/* 674 */ "PseudoTRUNC_W_D32\0"	---
7949	/* 692 */ "ROUND_W_D32\0"	---	7949	/* 692 */ "ROUND_W_D32\0"	---
7950	/* 704 */ "CEIL_W_D32\0"	---	7950	/* 704 */ "CEIL_W_D32\0"	---
7951	/* 715 */ "FLOOR_W_D32\0"	---	7951	/* 715 */ "FLOOR_W_D32\0"	---
7952	/* 727 */ "CVT_W_D32\0"	---	7952	/* 727 */ "CVT_W_D32\0"	---
7953	/* 737 */ "BPOSGE32\0"	---	7953	/* 737 */ "BPOSGE32\0"	---
7954	/* 746 */ "ATOMIC_LOAD_SUB_I32\0"	---	7954	/* 746 */ "ATOMIC_LOAD_SUB_I32\0"	---
7955	/* 766 */ "ATOMIC_LOAD_ADD_I32\0"	---	7955	/* 766 */ "ATOMIC_LOAD_ADD_I32\0"	---
7956	/* 786 */ "ATOMIC_LOAD_NAND_I32\0"	---	7956	/* 786 */ "ATOMIC_LOAD_NAND_I32\0"	---
7957	/* 807 */ "ATOMIC_LOAD_AND_I32\0"	---	7957	/* 807 */ "ATOMIC_LOAD_AND_I32\0"	---
7958	/* 827 */ "ATOMIC_LOAD_UMIN_I32\0"	---	7958	/* 827 */ "ATOMIC_LOAD_UMIN_I32\0"	---
7959	/* 848 */ "ATOMIC_LOAD_MIN_I32\0"	---	7959	/* 848 */ "ATOMIC_LOAD_MIN_I32\0"	---
7960	/* 868 */ "ATOMIC_SWAP_I32\0"	---	7960	/* 868 */ "ATOMIC_SWAP_I32\0"	---
7961	/* 884 */ "ATOMIC_CMP_SWAP_I32\0"	---	7961	/* 884 */ "ATOMIC_CMP_SWAP_I32\0"	---
7962	/* 904 */ "ATOMIC_LOAD_XOR_I32\0"	---	7962	/* 904 */ "ATOMIC_LOAD_XOR_I32\0"	---
7963	/* 924 */ "ATOMIC_LOAD_OR_I32\0"	---	7963	/* 924 */ "ATOMIC_LOAD_OR_I32\0"	---
7964	/* 943 */ "ATOMIC_LOAD_UMAX_I32\0"	---	7964	/* 943 */ "ATOMIC_LOAD_UMAX_I32\0"	---
7965	/* 964 */ "ATOMIC_LOAD_MAX_I32\0"	---	7965	/* 964 */ "ATOMIC_LOAD_MAX_I32\0"	---
7966	/* 984 */ "DSLL32\0"	---	7966	/* 984 */ "DSLL32\0"	---
7967	/* 991 */ "DSRL32\0"	---	7967	/* 991 */ "DSRL32\0"	---
7968	/* 998 */ "DROTR32\0"	---	7968	/* 998 */ "DROTR32\0"	---
7969	/* 1006 */ "CINS32\0"	---	7969	/* 1006 */ "CINS32\0"	---
7970	/* 1013 */ "EXTS32\0"	---	7970	/* 1013 */ "EXTS32\0"	---
7971	/* 1020 */ "FCMP_S32\0"	---	7971	/* 1020 */ "FCMP_S32\0"	---
7972	/* 1029 */ "DSLL64_32\0"	---	7972	/* 1029 */ "DSLL64_32\0"	---
7973	/* 1039 */ "CINS64_32\0"	---	7973	/* 1039 */ "CINS64_32\0"	---
7974	/* 1049 */ "DEXT64_32\0"	---	7974	/* 1049 */ "DEXT64_32\0"	---
7975	/* 1059 */ "LoadImmDoubleFGR_32\0"	---	7975	/* 1059 */ "LoadImmDoubleFGR_32\0"	---
7976	/* 1079 */ "LoadAddrReg32\0"	---	7976	/* 1079 */ "LoadAddrReg32\0"	---
7977	/* 1093 */ "CINS_i32\0"	---	7977	/* 1093 */ "CINS_i32\0"	---
7978	/* 1102 */ "LoadImm32\0"	---	7978	/* 1102 */ "LoadImm32\0"	---
7979	/* 1112 */ "LoadAddrImm32\0"	---	7979	/* 1112 */ "LoadAddrImm32\0"	---
7980	/* 1126 */ "MIPSeh_return32\0"	---	7980	/* 1126 */ "MIPSeh_return32\0"	---
7981	/* 1142 */ "LwConstant32\0"	---	7981	/* 1142 */ "LwConstant32\0"	---
7982	/* 1155 */ "LDC2\0"	---	7982	/* 1155 */ "LDC2\0"	---
7983	/* 1160 */ "SDC2\0"	---	7983	/* 1160 */ "SDC2\0"	---
7984	/* 1165 */ "DMFC2\0"	---	7984	/* 1165 */ "DMFC2\0"	---
7985	/* 1171 */ "DMTC2\0"	---	7985	/* 1171 */ "DMTC2\0"	---
7986	/* 1177 */ "LWC2\0"	---	7986	/* 1177 */ "LWC2\0"	---
7987	/* 1182 */ "SWC2\0"	---	7987	/* 1182 */ "SWC2\0"	---
7988	/* 1187 */ "G_FLOG2\0"	---	7988	/* 1187 */ "G_FLOG2\0"	---
7989	/* 1195 */ "MTM2\0"	---	7989	/* 1195 */ "MTM2\0"	---
7990	/* 1200 */ "MTP2\0"	---	7990	/* 1200 */ "MTP2\0"	---
7991	/* 1205 */ "G_FEXP2\0"	---	7991	/* 1205 */ "G_FEXP2\0"	---
7992	/* 1213 */ "SHRA_QB_MMR2\0"	---	7992	/* 1213 */ "SHRA_QB_MMR2\0"	---
7993	/* 1226 */ "CMPGDU_LE_QB_MMR2\0"	---	7993	/* 1226 */ "CMPGDU_LE_QB_MMR2\0"	---
7994	/* 1244 */ "SUBUH_QB_MMR2\0"	---	7994	/* 1244 */ "SUBUH_QB_MMR2\0"	---
7995	/* 1258 */ "ADDUH_QB_MMR2\0"	---	7995	/* 1258 */ "ADDUH_QB_MMR2\0"	---
7996	/* 1272 */ "CMPGDU_EQ_QB_MMR2\0"	---	7996	/* 1272 */ "CMPGDU_EQ_QB_MMR2\0"	---
7997	/* 1290 */ "SHRA_R_QB_MMR2\0"	---	7997	/* 1290 */ "SHRA_R_QB_MMR2\0"	---
7998	/* 1305 */ "SUBUH_R_QB_MMR2\0"	---	7998	/* 1305 */ "SUBUH_R_QB_MMR2\0"	---
7999	/* 1321 */ "ADDUH_R_QB_MMR2\0"	---	7999	/* 1321 */ "ADDUH_R_QB_MMR2\0"	---
8000	/* 1337 */ "SHRAV_R_QB_MMR2\0"	---	8000	/* 1337 */ "SHRAV_R_QB_MMR2\0"	---
8001	/* 1353 */ "ABSQ_S_QB_MMR2\0"	---	8001	/* 1353 */ "ABSQ_S_QB_MMR2\0"	---
8002	/* 1368 */ "CMPGDU_LT_QB_MMR2\0"	---	8002	/* 1368 */ "CMPGDU_LT_QB_MMR2\0"	---
8003	/* 1386 */ "SHRAV_QB_MMR2\0"	---	8003	/* 1386 */ "SHRAV_QB_MMR2\0"	---
8004	/* 1400 */ "PREPEND_MMR2\0"	---	8004	/* 1400 */ "PREPEND_MMR2\0"	---
8005	/* 1413 */ "APPEND_MMR2\0"	---	8005	/* 1413 */ "APPEND_MMR2\0"	---
8006	/* 1425 */ "PRECR_QB_PH_MMR2\0"	---	8006	/* 1425 */ "PRECR_QB_PH_MMR2\0"	---
8007	/* 1442 */ "SUBQH_PH_MMR2\0"	---	8007	/* 1442 */ "SUBQH_PH_MMR2\0"	---
8008	/* 1456 */ "ADDQH_PH_MMR2\0"	---	8008	/* 1456 */ "ADDQH_PH_MMR2\0"	---
8009	/* 1470 */ "SHRL_PH_MMR2\0"	---	8009	/* 1470 */ "SHRL_PH_MMR2\0"	---
8010	/* 1483 */ "MUL_PH_MMR2\0"	---	8010	/* 1483 */ "MUL_PH_MMR2\0"	---
8011	/* 1495 */ "SUBQH_R_PH_MMR2\0"	---	8011	/* 1495 */ "SUBQH_R_PH_MMR2\0"	---
8012	/* 1511 */ "ADDQH_R_PH_MMR2\0"	---	8012	/* 1511 */ "ADDQH_R_PH_MMR2\0"	---
8013	/* 1527 */ "MUL_S_PH_MMR2\0"	---	8013	/* 1527 */ "MUL_S_PH_MMR2\0"	---
8014	/* 1541 */ "MULQ_S_PH_MMR2\0"	---	8014	/* 1541 */ "MULQ_S_PH_MMR2\0"	---
8015	/* 1556 */ "SUBU_S_PH_MMR2\0"	---	8015	/* 1556 */ "SUBU_S_PH_MMR2\0"	---
8016	/* 1571 */ "ADDU_S_PH_MMR2\0"	---	8016	/* 1571 */ "ADDU_S_PH_MMR2\0"	---
8017	/* 1586 */ "SUBU_PH_MMR2\0"	---	8017	/* 1586 */ "SUBU_PH_MMR2\0"	---
8018	/* 1599 */ "ADDU_PH_MMR2\0"	---	8018	/* 1599 */ "ADDU_PH_MMR2\0"	---
8019	/* 1612 */ "SHRLV_PH_MMR2\0"	---	8019	/* 1612 */ "SHRLV_PH_MMR2\0"	---
8020	/* 1626 */ "DPA_W_PH_MMR2\0"	---	8020	/* 1626 */ "DPA_W_PH_MMR2\0"	---
8021	/* 1640 */ "MULSA_W_PH_MMR2\0"	---	8021	/* 1640 */ "MULSA_W_PH_MMR2\0"	---
8022	/* 1656 */ "DPAQX_SA_W_PH_MMR2\0"	---	8022	/* 1656 */ "DPAQX_SA_W_PH_MMR2\0"	---
8023	/* 1675 */ "DPSQX_SA_W_PH_MMR2\0"	---	8023	/* 1675 */ "DPSQX_SA_W_PH_MMR2\0"	---
8024	/* 1694 */ "DPS_W_PH_MMR2\0"	---	8024	/* 1694 */ "DPS_W_PH_MMR2\0"	---
8025	/* 1708 */ "DPAQX_S_W_PH_MMR2\0"	---	8025	/* 1708 */ "DPAQX_S_W_PH_MMR2\0"	---
8026	/* 1726 */ "DPSQX_S_W_PH_MMR2\0"	---	8026	/* 1726 */ "DPSQX_S_W_PH_MMR2\0"	---
8027	/* 1744 */ "DPAX_W_PH_MMR2\0"	---	8027	/* 1744 */ "DPAX_W_PH_MMR2\0"	---
8028	/* 1759 */ "DPSX_W_PH_MMR2\0"	---	8028	/* 1759 */ "DPSX_W_PH_MMR2\0"	---
8029	/* 1774 */ "BALIGN_MMR2\0"	---	8029	/* 1774 */ "BALIGN_MMR2\0"	---
8030	/* 1786 */ "PRECR_SRA_PH_W_MMR2\0"	---	8030	/* 1786 */ "PRECR_SRA_PH_W_MMR2\0"	---
8031	/* 1806 */ "PRECR_SRA_R_PH_W_MMR2\0"	---	8031	/* 1806 */ "PRECR_SRA_R_PH_W_MMR2\0"	---
8032	/* 1828 */ "SUBQH_W_MMR2\0"	---	8032	/* 1828 */ "SUBQH_W_MMR2\0"	---
8033	/* 1841 */ "ADDQH_W_MMR2\0"	---	8033	/* 1841 */ "ADDQH_W_MMR2\0"	---
8034	/* 1854 */ "SUBQH_R_W_MMR2\0"	---	8034	/* 1854 */ "SUBQH_R_W_MMR2\0"	---
8035	/* 1869 */ "ADDQH_R_W_MMR2\0"	---	8035	/* 1869 */ "ADDQH_R_W_MMR2\0"	---
8036	/* 1884 */ "MULQ_RS_W_MMR2\0"	---	8036	/* 1884 */ "MULQ_RS_W_MMR2\0"	---
8037	/* 1899 */ "MULQ_S_W_MMR2\0"	---	8037	/* 1899 */ "MULQ_S_W_MMR2\0"	---
8038	/* 1913 */ "LDC3\0"	---	8038	/* 1913 */ "LDC3\0"	---
8039	/* 1918 */ "SDC3\0"	---	8039	/* 1918 */ "SDC3\0"	---
8040	/* 1923 */ "LWC3\0"	---	8040	/* 1923 */ "LWC3\0"	---
8041	/* 1928 */ "SWC3\0"	---	8041	/* 1928 */ "SWC3\0"	---
8042	/* 1933 */ "BPOSGE32C_MMR3\0"	---	8042	/* 1933 */ "BPOSGE32C_MMR3\0"	---
8043	/* 1948 */ "LDC164\0"	---	8043	/* 1948 */ "LDC164\0"	---
8044	/* 1955 */ "SDC164\0"	---	8044	/* 1955 */ "SDC164\0"	---
8045	/* 1962 */ "LDXC164\0"	---	8045	/* 1962 */ "LDXC164\0"	---
8046	/* 1970 */ "SDXC164\0"	---	8046	/* 1970 */ "SDXC164\0"	---
8047	/* 1978 */ "LUXC164\0"	---	8047	/* 1978 */ "LUXC164\0"	---
8048	/* 1986 */ "SUXC164\0"	---	8048	/* 1986 */ "SUXC164\0"	---
8049	/* 1994 */ "SEB64\0"	---	8049	/* 1994 */ "SEB64\0"	---
8050	/* 2000 */ "TAILCALLREGHB64\0"	---	8050	/* 2000 */ "TAILCALLREGHB64\0"	---
8051	/* 2016 */ "JR_HB64\0"	---	8051	/* 2016 */ "JR_HB64\0"	---
8052	/* 2024 */ "JALR_HB64\0"	---	8052	/* 2024 */ "JALR_HB64\0"	---
8053	/* 2034 */ "LB64\0"	---	8053	/* 2034 */ "LB64\0"	---
8054	/* 2039 */ "SB64\0"	---	8054	/* 2039 */ "SB64\0"	---
8055	/* 2044 */ "LOAD_ACC64\0"	---	8055	/* 2044 */ "LOAD_ACC64\0"	---
8056	/* 2055 */ "STORE_ACC64\0"	---	8056	/* 2055 */ "STORE_ACC64\0"	---
8057	/* 2067 */ "BGEC64\0"	---	8057	/* 2067 */ "BGEC64\0"	---
8058	/* 2074 */ "BNEC64\0"	---	8058	/* 2074 */ "BNEC64\0"	---
8059	/* 2081 */ "JIC64\0"	---	8059	/* 2081 */ "JIC64\0"	---
8060	/* 2087 */ "JIALC64\0"	---	8060	/* 2087 */ "JIALC64\0"	---
8061	/* 2095 */ "BEQC64\0"	---	8061	/* 2095 */ "BEQC64\0"	---
8062	/* 2102 */ "SC64\0"	---	8062	/* 2102 */ "SC64\0"	---
8063	/* 2107 */ "BLTC64\0"	---	8063	/* 2107 */ "BLTC64\0"	---
8064	/* 2114 */ "BGEUC64\0"	---	8064	/* 2114 */ "BGEUC64\0"	---
8065	/* 2122 */ "BLTUC64\0"	---	8065	/* 2122 */ "BLTUC64\0"	---
8066	/* 2130 */ "BGEZC64\0"	---	8066	/* 2130 */ "BGEZC64\0"	---
8067	/* 2138 */ "BLEZC64\0"	---	8067	/* 2138 */ "BLEZC64\0"	---
8068	/* 2146 */ "BNEZC64\0"	---	8068	/* 2146 */ "BNEZC64\0"	---
8069	/* 2154 */ "BEQZC64\0"	---	8069	/* 2154 */ "BEQZC64\0"	---
8070	/* 2162 */ "BGTZC64\0"	---	8070	/* 2162 */ "BGTZC64\0"	---
8071	/* 2170 */ "BLTZC64\0"	---	8071	/* 2170 */ "BLTZC64\0"	---
8072	/* 2178 */ "AND64\0"	---	8072	/* 2178 */ "AND64\0"	---
8073	/* 2184 */ "MFC1_D64\0"	---	8073	/* 2184 */ "MFC1_D64\0"	---
8074	/* 2193 */ "MFHC1_D64\0"	---	8074	/* 2193 */ "MFHC1_D64\0"	---
8075	/* 2203 */ "MTHC1_D64\0"	---	8075	/* 2203 */ "MTHC1_D64\0"	---
8076	/* 2213 */ "MTC1_D64\0"	---	8076	/* 2213 */ "MTC1_D64\0"	---
8077	/* 2222 */ "MOVN_I64_D64\0"	---	8077	/* 2222 */ "MOVN_I64_D64\0"	---
8078	/* 2235 */ "MOVZ_I64_D64\0"	---	8078	/* 2235 */ "MOVZ_I64_D64\0"	---
8079	/* 2248 */ "FSUB_D64\0"	---	8079	/* 2248 */ "FSUB_D64\0"	---
8080	/* 2257 */ "NMSUB_D64\0"	---	8080	/* 2257 */ "NMSUB_D64\0"	---
8081	/* 2267 */ "FADD_D64\0"	---	8081	/* 2267 */ "FADD_D64\0"	---
8082	/* 2276 */ "NMADD_D64\0"	---	8082	/* 2276 */ "NMADD_D64\0"	---
8083	/* 2286 */ "C_NGE_D64\0"	---	8083	/* 2286 */ "C_NGE_D64\0"	---
8084	/* 2296 */ "C_NGLE_D64\0"	---	8084	/* 2296 */ "C_NGLE_D64\0"	---
8085	/* 2307 */ "C_OLE_D64\0"	---	8085	/* 2307 */ "C_OLE_D64\0"	---
8086	/* 2317 */ "C_ULE_D64\0"	---	8086	/* 2317 */ "C_ULE_D64\0"	---
8087	/* 2327 */ "C_LE_D64\0"	---	8087	/* 2327 */ "C_LE_D64\0"	---
8088	/* 2336 */ "C_SF_D64\0"	---	8088	/* 2336 */ "C_SF_D64\0"	---
8089	/* 2345 */ "MOVF_D64\0"	---	8089	/* 2345 */ "MOVF_D64\0"	---
8090	/* 2354 */ "C_F_D64\0"	---	8090	/* 2354 */ "C_F_D64\0"	---
8091	/* 2362 */ "PseudoSELECTFP_F_D64\0"	---	8091	/* 2362 */ "PseudoSELECTFP_F_D64\0"	---
8092	/* 2383 */ "FNEG_D64\0"	---	8092	/* 2383 */ "FNEG_D64\0"	---
8093	/* 2392 */ "MOVN_I_D64\0"	---	8093	/* 2392 */ "MOVN_I_D64\0"	---
8094	/* 2403 */ "MOVZ_I_D64\0"	---	8094	/* 2403 */ "MOVZ_I_D64\0"	---
8095	/* 2414 */ "C_NGL_D64\0"	---	8095	/* 2414 */ "C_NGL_D64\0"	---
8096	/* 2424 */ "FMUL_D64\0"	---	8096	/* 2424 */ "FMUL_D64\0"	---
8097	/* 2433 */ "TRUNC_L_D64\0"	---	8097	/* 2433 */ "TRUNC_L_D64\0"	---
8098	/* 2445 */ "ROUND_L_D64\0"	---	8098	/* 2445 */ "ROUND_L_D64\0"	---
8099	/* 2457 */ "CEIL_L_D64\0"	---	8099	/* 2457 */ "CEIL_L_D64\0"	---
8100	/* 2468 */ "FLOOR_L_D64\0"	---	8100	/* 2468 */ "FLOOR_L_D64\0"	---
8101	/* 2480 */ "CVT_L_D64\0"	---	8101	/* 2480 */ "CVT_L_D64\0"	---
8102	/* 2490 */ "LDC1_MM_D64\0"	---	8102	/* 2490 */ "LDC1_MM_D64\0"	---
8103	/* 2502 */ "SDC1_MM_D64\0"	---	8103	/* 2502 */ "SDC1_MM_D64\0"	---
8104	/* 2514 */ "C_UN_D64\0"	---	8104	/* 2514 */ "C_UN_D64\0"	---
8105	/* 2523 */ "RECIP_D64\0"	---	8105	/* 2523 */ "RECIP_D64\0"	---
8106	/* 2533 */ "FCMP_D64\0"	---	8106	/* 2533 */ "FCMP_D64\0"	---
8107	/* 2542 */ "C_SEQ_D64\0"	---	8107	/* 2542 */ "C_SEQ_D64\0"	---
8108	/* 2552 */ "C_UEQ_D64\0"	---	8108	/* 2552 */ "C_UEQ_D64\0"	---
8109	/* 2562 */ "C_EQ_D64\0"	---	8109	/* 2562 */ "C_EQ_D64\0"	---
8110	/* 2571 */ "FABS_D64\0"	---	8110	/* 2571 */ "FABS_D64\0"	---
8111	/* 2580 */ "CVT_S_D64\0"	---	8111	/* 2580 */ "CVT_S_D64\0"	---
8112	/* 2590 */ "PseudoSELECT_D64\0"	---	8112	/* 2590 */ "PseudoSELECT_D64\0"	---
8113	/* 2607 */ "C_NGT_D64\0"	---	8113	/* 2607 */ "C_NGT_D64\0"	---
8114	/* 2617 */ "C_OLT_D64\0"	---	8114	/* 2617 */ "C_OLT_D64\0"	---
8115	/* 2627 */ "C_ULT_D64\0"	---	8115	/* 2627 */ "C_ULT_D64\0"	---
8116	/* 2637 */ "C_LT_D64\0"	---	8116	/* 2637 */ "C_LT_D64\0"	---
8117	/* 2646 */ "FSQRT_D64\0"	---	8117	/* 2646 */ "FSQRT_D64\0"	---
8118	/* 2656 */ "RSQRT_D64\0"	---	8118	/* 2656 */ "RSQRT_D64\0"	---
8119	/* 2666 */ "MOVT_D64\0"	---	8119	/* 2666 */ "MOVT_D64\0"	---
8120	/* 2675 */ "PseudoSELECTFP_T_D64\0"	---	8120	/* 2675 */ "PseudoSELECTFP_T_D64\0"	---
8121	/* 2696 */ "FDIV_D64\0"	---	8121	/* 2696 */ "FDIV_D64\0"	---
8122	/* 2705 */ "FMOV_D64\0"	---	8122	/* 2705 */ "FMOV_D64\0"	---
8123	/* 2714 */ "TRUNC_W_D64\0"	---	8123	/* 2714 */ "TRUNC_W_D64\0"	---
8124	/* 2726 */ "ROUND_W_D64\0"	---	8124	/* 2726 */ "ROUND_W_D64\0"	---
8125	/* 2738 */ "CEIL_W_D64\0"	---	8125	/* 2738 */ "CEIL_W_D64\0"	---
8126	/* 2749 */ "FLOOR_W_D64\0"	---	8126	/* 2749 */ "FLOOR_W_D64\0"	---
8127	/* 2761 */ "CVT_W_D64\0"	---	8127	/* 2761 */ "CVT_W_D64\0"	---
8128	/* 2771 */ "BNE64\0"	---	8128	/* 2771 */ "BNE64\0"	---
8129	/* 2777 */ "BuildPairF64\0"	---	8129	/* 2777 */ "BuildPairF64\0"	---
8130	/* 2790 */ "ExtractElementF64\0"	---	8130	/* 2790 */ "ExtractElementF64\0"	---
8131	/* 2808 */ "TAILCALLREG64\0"	---	8131	/* 2808 */ "TAILCALLREG64\0"	---
8132	/* 2822 */ "SEH64\0"	---	8132	/* 2822 */ "SEH64\0"	---
8133	/* 2828 */ "LH64\0"	---	8133	/* 2828 */ "LH64\0"	---
8134	/* 2833 */ "SH64\0"	---	8134	/* 2833 */ "SH64\0"	---
8135	/* 2838 */ "PseudoMFHI64\0"	---	8135	/* 2838 */ "PseudoMFHI64\0"	---
8136	/* 2851 */ "PseudoMTLOHI64\0"	---	8136	/* 2851 */ "PseudoMTLOHI64\0"	---
8137	/* 2866 */ "MTHI64\0"	---	8137	/* 2866 */ "MTHI64\0"	---
8138	/* 2873 */ "MOVN_I64_I64\0"	---	8138	/* 2873 */ "MOVN_I64_I64\0"	---
8139	/* 2886 */ "MOVZ_I64_I64\0"	---	8139	/* 2886 */ "MOVZ_I64_I64\0"	---
8140	/* 2899 */ "ATOMIC_LOAD_SUB_I64\0"	---	8140	/* 2899 */ "ATOMIC_LOAD_SUB_I64\0"	---
8141	/* 2919 */ "ATOMIC_LOAD_ADD_I64\0"	---	8141	/* 2919 */ "ATOMIC_LOAD_ADD_I64\0"	---
8142	/* 2939 */ "ATOMIC_LOAD_NAND_I64\0"	---	8142	/* 2939 */ "ATOMIC_LOAD_NAND_I64\0"	---
8143	/* 2960 */ "ATOMIC_LOAD_AND_I64\0"	---	8143	/* 2960 */ "ATOMIC_LOAD_AND_I64\0"	---
8144	/* 2980 */ "MOVF_I64\0"	---	8144	/* 2980 */ "MOVF_I64\0"	---
8145	/* 2989 */ "PseudoSELECTFP_F_I64\0"	---	8145	/* 2989 */ "PseudoSELECTFP_F_I64\0"	---
8146	/* 3010 */ "MOVN_I_I64\0"	---	8146	/* 3010 */ "MOVN_I_I64\0"	---
8147	/* 3021 */ "MOVZ_I_I64\0"	---	8147	/* 3021 */ "MOVZ_I_I64\0"	---
8148	/* 3032 */ "ATOMIC_LOAD_UMIN_I64\0"	---	8148	/* 3032 */ "ATOMIC_LOAD_UMIN_I64\0"	---
8149	/* 3053 */ "ATOMIC_LOAD_MIN_I64\0"	---	8149	/* 3053 */ "ATOMIC_LOAD_MIN_I64\0"	---
8150	/* 3073 */ "ATOMIC_SWAP_I64\0"	---	8150	/* 3073 */ "ATOMIC_SWAP_I64\0"	---
8151	/* 3089 */ "ATOMIC_CMP_SWAP_I64\0"	---	8151	/* 3089 */ "ATOMIC_CMP_SWAP_I64\0"	---
8152	/* 3109 */ "ATOMIC_LOAD_XOR_I64\0"	---	8152	/* 3109 */ "ATOMIC_LOAD_XOR_I64\0"	---
8153	/* 3129 */ "ATOMIC_LOAD_OR_I64\0"	---	8153	/* 3129 */ "ATOMIC_LOAD_OR_I64\0"	---
8154	/* 3148 */ "PseudoD_SELECT_I64\0"	---	8154	/* 3148 */ "PseudoD_SELECT_I64\0"	---
8155	/* 3167 */ "PseudoSELECT_I64\0"	---	8155	/* 3167 */ "PseudoSELECT_I64\0"	---
8156	/* 3184 */ "MOVT_I64\0"	---	8156	/* 3184 */ "MOVT_I64\0"	---
8157	/* 3193 */ "PseudoSELECTFP_T_I64\0"	---	8157	/* 3193 */ "PseudoSELECTFP_T_I64\0"	---
8158	/* 3214 */ "ATOMIC_LOAD_UMAX_I64\0"	---	8158	/* 3214 */ "ATOMIC_LOAD_UMAX_I64\0"	---
8159	/* 3235 */ "ATOMIC_LOAD_MAX_I64\0"	---	8159	/* 3235 */ "ATOMIC_LOAD_MAX_I64\0"	---
8160	/* 3255 */ "LL64\0"	---	8160	/* 3255 */ "LL64\0"	---
8161	/* 3260 */ "CVT_S_PL64\0"	---	8161	/* 3260 */ "CVT_S_PL64\0"	---
8162	/* 3271 */ "LWL64\0"	---	8162	/* 3271 */ "LWL64\0"	---
8163	/* 3277 */ "SWL64\0"	---	8163	/* 3277 */ "SWL64\0"	---
8164	/* 3283 */ "PseudoMFLO64\0"	---	8164	/* 3283 */ "PseudoMFLO64\0"	---
8165	/* 3296 */ "MTLO64\0"	---	8165	/* 3296 */ "MTLO64\0"	---
8166	/* 3303 */ "BEQ64\0"	---	8166	/* 3303 */ "BEQ64\0"	---
8167	/* 3309 */ "JR64\0"	---	8167	/* 3309 */ "JR64\0"	---
8168	/* 3314 */ "JALR64\0"	---	8168	/* 3314 */ "JALR64\0"	---
8169	/* 3321 */ "NOR64\0"	---	8169	/* 3321 */ "NOR64\0"	---
8170	/* 3327 */ "XOR64\0"	---	8170	/* 3327 */ "XOR64\0"	---
8171	/* 3333 */ "RDHWR64\0"	---	8171	/* 3333 */ "RDHWR64\0"	---
8172	/* 3341 */ "LWR64\0"	---	8172	/* 3341 */ "LWR64\0"	---
8173	/* 3347 */ "SWR64\0"	---	8173	/* 3347 */ "SWR64\0"	---
8174	/* 3353 */ "FSUB_PS64\0"	---	8174	/* 3353 */ "FSUB_PS64\0"	---
8175	/* 3363 */ "FADD_PS64\0"	---	8175	/* 3363 */ "FADD_PS64\0"	---
8176	/* 3373 */ "PLL_PS64\0"	---	8176	/* 3373 */ "PLL_PS64\0"	---
8177	/* 3382 */ "FMUL_PS64\0"	---	8177	/* 3382 */ "FMUL_PS64\0"	---
8178	/* 3392 */ "PUL_PS64\0"	---	8178	/* 3392 */ "PUL_PS64\0"	---
8179	/* 3401 */ "ADDR_PS64\0"	---	8179	/* 3401 */ "ADDR_PS64\0"	---
8180	/* 3411 */ "MULR_PS64\0"	---	8180	/* 3411 */ "MULR_PS64\0"	---
8181	/* 3421 */ "PLU_PS64\0"	---	8181	/* 3421 */ "PLU_PS64\0"	---
8182	/* 3430 */ "PUU_PS64\0"	---	8182	/* 3430 */ "PUU_PS64\0"	---
8183	/* 3439 */ "CVT_PW_PS64\0"	---	8183	/* 3439 */ "CVT_PW_PS64\0"	---
8184	/* 3451 */ "CVT_PS_S64\0"	---	8184	/* 3451 */ "CVT_PS_S64\0"	---
8185	/* 3462 */ "SLT64\0"	---	8185	/* 3462 */ "SLT64\0"	---
8186	/* 3468 */ "CVT_S_PU64\0"	---	8186	/* 3468 */ "CVT_S_PU64\0"	---
8187	/* 3479 */ "LW64\0"	---	8187	/* 3479 */ "LW64\0"	---
8188	/* 3484 */ "CVT_PS_PW64\0"	---	8188	/* 3484 */ "CVT_PS_PW64\0"	---
8189	/* 3496 */ "SW64\0"	---	8189	/* 3496 */ "SW64\0"	---
8190	/* 3501 */ "BGEZ64\0"	---	8190	/* 3501 */ "BGEZ64\0"	---
8191	/* 3508 */ "BLEZ64\0"	---	8191	/* 3508 */ "BLEZ64\0"	---
8192	/* 3515 */ "SELNEZ64\0"	---	8192	/* 3515 */ "SELNEZ64\0"	---
8193	/* 3524 */ "SELEQZ64\0"	---	8193	/* 3524 */ "SELEQZ64\0"	---
8194	/* 3533 */ "BGTZ64\0"	---	8194	/* 3533 */ "BGTZ64\0"	---
8195	/* 3540 */ "BLTZ64\0"	---	8195	/* 3540 */ "BLTZ64\0"	---
8196	/* 3547 */ "BuildPairF64_64\0"	---	8196	/* 3547 */ "BuildPairF64_64\0"	---
8197	/* 3563 */ "ExtractElementF64_64\0"	---	8197	/* 3563 */ "ExtractElementF64_64\0"	---
8198	/* 3584 */ "SLL64_64\0"	---	8198	/* 3584 */ "SLL64_64\0"	---
8199	/* 3593 */ "LONG_BRANCH_LUi2Op_64\0"	---	8199	/* 3593 */ "LONG_BRANCH_LUi2Op_64\0"	---
8200	/* 3615 */ "LoadAddrReg64\0"	---	8200	/* 3615 */ "LoadAddrReg64\0"	---
8201	/* 3629 */ "PseudoIndirectHazardBranch64\0"	---	8201	/* 3629 */ "PseudoIndirectHazardBranch64\0"	---
8202	/* 3658 */ "PseudoIndirectBranch64\0"	---	8202	/* 3658 */ "PseudoIndirectBranch64\0"	---
8203	/* 3681 */ "ANDi64\0"	---	8203	/* 3681 */ "ANDi64\0"	---
8204	/* 3688 */ "XORi64\0"	---	8204	/* 3688 */ "XORi64\0"	---
8205	/* 3695 */ "SLTi64\0"	---	8205	/* 3695 */ "SLTi64\0"	---
8206	/* 3702 */ "LUi64\0"	---	8206	/* 3702 */ "LUi64\0"	---
8207	/* 3708 */ "SGEImm64\0"	---	8207	/* 3708 */ "SGEImm64\0"	---
8208	/* 3717 */ "SLEImm64\0"	---	8208	/* 3717 */ "SLEImm64\0"	---
8209	/* 3726 */ "NORImm64\0"	---	8209	/* 3726 */ "NORImm64\0"	---
8210	/* 3735 */ "SGTImm64\0"	---	8210	/* 3735 */ "SGTImm64\0"	---
8211	/* 3744 */ "SLTImm64\0"	---	8211	/* 3744 */ "SLTImm64\0"	---
8212	/* 3753 */ "SGEUImm64\0"	---	8212	/* 3753 */ "SGEUImm64\0"	---
8213	/* 3763 */ "SLEUImm64\0"	---	8213	/* 3763 */ "SLEUImm64\0"	---
8214	/* 3773 */ "SGTUImm64\0"	---	8214	/* 3773 */ "SGTUImm64\0"	---
8215	/* 3783 */ "SLTUImm64\0"	---	8215	/* 3783 */ "SLTUImm64\0"	---
8216	/* 3793 */ "LoadImm64\0"	---	8216	/* 3793 */ "LoadImm64\0"	---
8217	/* 3803 */ "LoadAddrImm64\0"	---	8217	/* 3803 */ "LoadAddrImm64\0"	---
8218	/* 3817 */ "PseudoReturn64\0"	---	8218	/* 3817 */ "PseudoReturn64\0"	---
8219	/* 3832 */ "MIPSeh_return64\0"	---	8219	/* 3832 */ "MIPSeh_return64\0"	---
8220	/* 3848 */ "LBu64\0"	---	8220	/* 3848 */ "LBu64\0"	---
8221	/* 3854 */ "LHu64\0"	---	8221	/* 3854 */ "LHu64\0"	---
8222	/* 3860 */ "SLTu64\0"	---	8222	/* 3860 */ "SLTu64\0"	---
8223	/* 3867 */ "LEA_ADDiu64\0"	---	8223	/* 3867 */ "LEA_ADDiu64\0"	---
8224	/* 3879 */ "SLTiu64\0"	---	8224	/* 3879 */ "SLTiu64\0"	---
8225	/* 3887 */ "MoveR3216\0"	---	8225	/* 3887 */ "MoveR3216\0"	---
8226	/* 3897 */ "RetRA16\0"	---	8226	/* 3897 */ "RetRA16\0"	---
8227	/* 3905 */ "JalB16\0"	---	8227	/* 3905 */ "JalB16\0"	---
8228	/* 3912 */ "LD_F16\0"	---	8228	/* 3912 */ "LD_F16\0"	---
8229	/* 3919 */ "ST_F16\0"	---	8229	/* 3919 */ "ST_F16\0"	---
8230	/* 3926 */ "ATOMIC_LOAD_SUB_I16\0"	---	8230	/* 3926 */ "ATOMIC_LOAD_SUB_I16\0"	---
8231	/* 3946 */ "ATOMIC_LOAD_ADD_I16\0"	---	8231	/* 3946 */ "ATOMIC_LOAD_ADD_I16\0"	---
8232	/* 3966 */ "ATOMIC_LOAD_NAND_I16\0"	---	8232	/* 3966 */ "ATOMIC_LOAD_NAND_I16\0"	---
8233	/* 3987 */ "ATOMIC_LOAD_AND_I16\0"	---	8233	/* 3987 */ "ATOMIC_LOAD_AND_I16\0"	---
8234	/* 4007 */ "ATOMIC_LOAD_UMIN_I16\0"	---	8234	/* 4007 */ "ATOMIC_LOAD_UMIN_I16\0"	---
8235	/* 4028 */ "ATOMIC_LOAD_MIN_I16\0"	---	8235	/* 4028 */ "ATOMIC_LOAD_MIN_I16\0"	---
8236	/* 4048 */ "ATOMIC_SWAP_I16\0"	---	8236	/* 4048 */ "ATOMIC_SWAP_I16\0"	---
8237	/* 4064 */ "ATOMIC_CMP_SWAP_I16\0"	---	8237	/* 4064 */ "ATOMIC_CMP_SWAP_I16\0"	---
8238	/* 4084 */ "ATOMIC_LOAD_XOR_I16\0"	---	8238	/* 4084 */ "ATOMIC_LOAD_XOR_I16\0"	---
8239	/* 4104 */ "ATOMIC_LOAD_OR_I16\0"	---	8239	/* 4104 */ "ATOMIC_LOAD_OR_I16\0"	---
8240	/* 4123 */ "ATOMIC_LOAD_UMAX_I16\0"	---	8240	/* 4123 */ "ATOMIC_LOAD_UMAX_I16\0"	---
8241	/* 4144 */ "ATOMIC_LOAD_MAX_I16\0"	---	8241	/* 4144 */ "ATOMIC_LOAD_MAX_I16\0"	---
8242	/* 4164 */ "Move32R16\0"	---	8242	/* 4164 */ "Move32R16\0"	---
8243	/* 4174 */ "SraX16\0"	---	8243	/* 4174 */ "SraX16\0"	---
8244	/* 4181 */ "RestoreX16\0"	---	8244	/* 4181 */ "RestoreX16\0"	---
8245	/* 4192 */ "SaveX16\0"	---	8245	/* 4192 */ "SaveX16\0"	---
8246	/* 4200 */ "BtnezT8CmpiX16\0"	---	8246	/* 4200 */ "BtnezT8CmpiX16\0"	---
8247	/* 4215 */ "BteqzT8CmpiX16\0"	---	8247	/* 4215 */ "BteqzT8CmpiX16\0"	---
8248	/* 4230 */ "BtnezT8SltiX16\0"	---	8248	/* 4230 */ "BtnezT8SltiX16\0"	---
8249	/* 4245 */ "BteqzT8SltiX16\0"	---	8249	/* 4245 */ "BteqzT8SltiX16\0"	---
8250	/* 4260 */ "SllX16\0"	---	8250	/* 4260 */ "SllX16\0"	---
8251	/* 4267 */ "SrlX16\0"	---	8251	/* 4267 */ "SrlX16\0"	---
8252	/* 4274 */ "LbRxRyOffMemX16\0"	---	8252	/* 4274 */ "LbRxRyOffMemX16\0"	---
8253	/* 4290 */ "SbRxRyOffMemX16\0"	---	8253	/* 4290 */ "SbRxRyOffMemX16\0"	---
8254	/* 4306 */ "LhRxRyOffMemX16\0"	---	8254	/* 4306 */ "LhRxRyOffMemX16\0"	---
8255	/* 4322 */ "ShRxRyOffMemX16\0"	---	8255	/* 4322 */ "ShRxRyOffMemX16\0"	---
8256	/* 4338 */ "LbuRxRyOffMemX16\0"	---	8256	/* 4338 */ "LbuRxRyOffMemX16\0"	---
8257	/* 4355 */ "LhuRxRyOffMemX16\0"	---	8257	/* 4355 */ "LhuRxRyOffMemX16\0"	---
8258	/* 4372 */ "AddiuRxRyOffMemX16\0"	---	8258	/* 4372 */ "AddiuRxRyOffMemX16\0"	---
8259	/* 4391 */ "LwRxRyOffMemX16\0"	---	8259	/* 4391 */ "LwRxRyOffMemX16\0"	---
8260	/* 4407 */ "SwRxRyOffMemX16\0"	---	8260	/* 4407 */ "SwRxRyOffMemX16\0"	---
8261	/* 4423 */ "AddiuRxPcImmX16\0"	---	8261	/* 4423 */ "AddiuRxPcImmX16\0"	---
8262	/* 4439 */ "AddiuSpImmX16\0"	---	8262	/* 4439 */ "AddiuSpImmX16\0"	---
8263	/* 4453 */ "LwRxSpImmX16\0"	---	8263	/* 4453 */ "LwRxSpImmX16\0"	---
8264	/* 4466 */ "SwRxSpImmX16\0"	---	8264	/* 4466 */ "SwRxSpImmX16\0"	---
8265	/* 4479 */ "SltiCCRxImmX16\0"	---	8265	/* 4479 */ "SltiCCRxImmX16\0"	---
8266	/* 4494 */ "SltiuCCRxImmX16\0"	---	8266	/* 4494 */ "SltiuCCRxImmX16\0"	---
8267	/* 4510 */ "LiRxImmX16\0"	---	8267	/* 4510 */ "LiRxImmX16\0"	---
8268	/* 4521 */ "CmpiRxImmX16\0"	---	8268	/* 4521 */ "CmpiRxImmX16\0"	---
8269	/* 4534 */ "SltiRxImmX16\0"	---	8269	/* 4534 */ "SltiRxImmX16\0"	---
8270	/* 4547 */ "AddiuRxImmX16\0"	---	8270	/* 4547 */ "AddiuRxImmX16\0"	---
8271	/* 4561 */ "SltiuRxImmX16\0"	---	8271	/* 4561 */ "SltiuRxImmX16\0"	---
8272	/* 4575 */ "AddiuRxRxImmX16\0"	---	8272	/* 4575 */ "AddiuRxRxImmX16\0"	---
8273	/* 4591 */ "BnezRxImmX16\0"	---	8273	/* 4591 */ "BnezRxImmX16\0"	---
8274	/* 4604 */ "BeqzRxImmX16\0"	---	8274	/* 4604 */ "BeqzRxImmX16\0"	---
8275	/* 4617 */ "BimmX16\0"	---	8275	/* 4617 */ "BimmX16\0"	---
8276	/* 4625 */ "LiRxImmAlignX16\0"	---	8276	/* 4625 */ "LiRxImmAlignX16\0"	---
8277	/* 4641 */ "LwRxPcTcpX16\0"	---	8277	/* 4641 */ "LwRxPcTcpX16\0"	---
8278	/* 4654 */ "BtnezT8CmpX16\0"	---	8278	/* 4654 */ "BtnezT8CmpX16\0"	---
8279	/* 4668 */ "BteqzT8CmpX16\0"	---	8279	/* 4668 */ "BteqzT8CmpX16\0"	---
8280	/* 4682 */ "BtnezT8SltX16\0"	---	8280	/* 4682 */ "BtnezT8SltX16\0"	---
8281	/* 4696 */ "BteqzT8SltX16\0"	---	8281	/* 4696 */ "BteqzT8SltX16\0"	---
8282	/* 4710 */ "BtnezT8SltiuX16\0"	---	8282	/* 4710 */ "BtnezT8SltiuX16\0"	---
8283	/* 4726 */ "BteqzT8SltiuX16\0"	---	8283	/* 4726 */ "BteqzT8SltiuX16\0"	---
8284	/* 4742 */ "BtnezT8SltuX16\0"	---	8284	/* 4742 */ "BtnezT8SltuX16\0"	---
8285	/* 4757 */ "BteqzT8SltuX16\0"	---	8285	/* 4757 */ "BteqzT8SltuX16\0"	---
8286	/* 4772 */ "BtnezX16\0"	---	8286	/* 4772 */ "BtnezX16\0"	---
8287	/* 4781 */ "BteqzX16\0"	---	8287	/* 4781 */ "BteqzX16\0"	---
8288	/* 4790 */ "JrcRa16\0"	---	8288	/* 4790 */ "JrcRa16\0"	---
8289	/* 4798 */ "JrRa16\0"	---	8289	/* 4798 */ "JrRa16\0"	---
8290	/* 4805 */ "Restore16\0"	---	8290	/* 4805 */ "Restore16\0"	---
8291	/* 4815 */ "GotPrologue16\0"	---	8291	/* 4815 */ "GotPrologue16\0"	---
8292	/* 4829 */ "Save16\0"	---	8292	/* 4829 */ "Save16\0"	---
8293	/* 4836 */ "JumpLinkReg16\0"	---	8293	/* 4836 */ "JumpLinkReg16\0"	---
8294	/* 4850 */ "Mfhi16\0"	---	8294	/* 4850 */ "Mfhi16\0"	---
8295	/* 4857 */ "Break16\0"	---	8295	/* 4857 */ "Break16\0"	---
8296	/* 4865 */ "Jal16\0"	---	8296	/* 4865 */ "Jal16\0"	---
8297	/* 4871 */ "AddiuSpImm16\0"	---	8297	/* 4871 */ "AddiuSpImm16\0"	---
8298	/* 4884 */ "LiRxImm16\0"	---	8298	/* 4884 */ "LiRxImm16\0"	---
8299	/* 4894 */ "CmpiRxImm16\0"	---	8299	/* 4894 */ "CmpiRxImm16\0"	---
8300	/* 4906 */ "SltiRxImm16\0"	---	8300	/* 4906 */ "SltiRxImm16\0"	---
8301	/* 4918 */ "SltiuRxImm16\0"	---	8301	/* 4918 */ "SltiuRxImm16\0"	---
8302	/* 4931 */ "AddiuRxRxImm16\0"	---	8302	/* 4931 */ "AddiuRxRxImm16\0"	---
8303	/* 4946 */ "BnezRxImm16\0"	---	8303	/* 4946 */ "BnezRxImm16\0"	---
8304	/* 4958 */ "BeqzRxImm16\0"	---	8304	/* 4958 */ "BeqzRxImm16\0"	---
8305	/* 4970 */ "Bimm16\0"	---	8305	/* 4970 */ "Bimm16\0"	---
8306	/* 4977 */ "Mflo16\0"	---	8306	/* 4977 */ "Mflo16\0"	---
8307	/* 4984 */ "LwRxPcTcp16\0"	---	8307	/* 4984 */ "LwRxPcTcp16\0"	---
8308	/* 4996 */ "SebRx16\0"	---	8308	/* 4996 */ "SebRx16\0"	---
8309	/* 5004 */ "JrcRx16\0"	---	8309	/* 5004 */ "JrcRx16\0"	---
8310	/* 5012 */ "SehRx16\0"	---	8310	/* 5012 */ "SehRx16\0"	---
8311	/* 5020 */ "SltCCRxRy16\0"	---	8311	/* 5020 */ "SltCCRxRy16\0"	---
8312	/* 5032 */ "SltuCCRxRy16\0"	---	8312	/* 5032 */ "SltuCCRxRy16\0"	---
8313	/* 5045 */ "NegRxRy16\0"	---	8313	/* 5045 */ "NegRxRy16\0"	---
8314	/* 5055 */ "CmpRxRy16\0"	---	8314	/* 5055 */ "CmpRxRy16\0"	---
8315	/* 5065 */ "SltRxRy16\0"	---	8315	/* 5065 */ "SltRxRy16\0"	---
8316	/* 5075 */ "MultRxRy16\0"	---	8316	/* 5075 */ "MultRxRy16\0"	---
8317	/* 5086 */ "NotRxRy16\0"	---	8317	/* 5086 */ "NotRxRy16\0"	---
8318	/* 5096 */ "SltuRxRy16\0"	---	8318	/* 5096 */ "SltuRxRy16\0"	---
8319	/* 5107 */ "MultuRxRy16\0"	---	8319	/* 5107 */ "MultuRxRy16\0"	---
8320	/* 5119 */ "DivuRxRy16\0"	---	8320	/* 5119 */ "DivuRxRy16\0"	---
8321	/* 5130 */ "SravRxRy16\0"	---	8321	/* 5130 */ "SravRxRy16\0"	---
8322	/* 5141 */ "DivRxRy16\0"	---	8322	/* 5141 */ "DivRxRy16\0"	---
8323	/* 5151 */ "SllvRxRy16\0"	---	8323	/* 5151 */ "SllvRxRy16\0"	---
8324	/* 5162 */ "SrlvRxRy16\0"	---	8324	/* 5162 */ "SrlvRxRy16\0"	---
8325	/* 5173 */ "AndRxRxRy16\0"	---	8325	/* 5173 */ "AndRxRxRy16\0"	---
8326	/* 5185 */ "OrRxRxRy16\0"	---	8326	/* 5185 */ "OrRxRxRy16\0"	---
8327	/* 5196 */ "XorRxRxRy16\0"	---	8327	/* 5196 */ "XorRxRxRy16\0"	---
8328	/* 5208 */ "MultRxRyRz16\0"	---	8328	/* 5208 */ "MultRxRyRz16\0"	---
8329	/* 5221 */ "SubuRxRyRz16\0"	---	8329	/* 5221 */ "SubuRxRyRz16\0"	---
8330	/* 5234 */ "AdduRxRyRz16\0"	---	8330	/* 5234 */ "AdduRxRyRz16\0"	---
8331	/* 5247 */ "SltuRxRyRz16\0"	---	8331	/* 5247 */ "SltuRxRyRz16\0"	---
8332	/* 5260 */ "MultuRxRyRz16\0"	---	8332	/* 5260 */ "MultuRxRyRz16\0"	---
8333	/* 5274 */ "Btnez16\0"	---	8333	/* 5274 */ "Btnez16\0"	---
8334	/* 5282 */ "Bteqz16\0"	---	8334	/* 5282 */ "Bteqz16\0"	---
8335	/* 5290 */ "PseudoIndrectHazardBranch64R6\0"	---	8335	/* 5290 */ "PseudoIndrectHazardBranch64R6\0"	---
8336	/* 5320 */ "PseudoIndirectBranch64R6\0"	---	8336	/* 5320 */ "PseudoIndirectBranch64R6\0"	---
8337	/* 5345 */ "MFC0_MMR6\0"	---	8337	/* 5345 */ "MFC0_MMR6\0"	---
8338	/* 5355 */ "MFHC0_MMR6\0"	---	8338	/* 5355 */ "MFHC0_MMR6\0"	---
8339	/* 5366 */ "MTHC0_MMR6\0"	---	8339	/* 5366 */ "MTHC0_MMR6\0"	---
8340	/* 5377 */ "MTC0_MMR6\0"	---	8340	/* 5377 */ "MTC0_MMR6\0"	---
8341	/* 5387 */ "MFC1_MMR6\0"	---	8341	/* 5387 */ "MFC1_MMR6\0"	---
8342	/* 5397 */ "MTC1_MMR6\0"	---	8342	/* 5397 */ "MTC1_MMR6\0"	---
8343	/* 5407 */ "LDC2_MMR6\0"	---	8343	/* 5407 */ "LDC2_MMR6\0"	---
8344	/* 5417 */ "SDC2_MMR6\0"	---	8344	/* 5417 */ "SDC2_MMR6\0"	---
8345	/* 5427 */ "MFC2_MMR6\0"	---	8345	/* 5427 */ "MFC2_MMR6\0"	---
8346	/* 5437 */ "MFHC2_MMR6\0"	---	8346	/* 5437 */ "MFHC2_MMR6\0"	---
8347	/* 5448 */ "MTHC2_MMR6\0"	---	8347	/* 5448 */ "MTHC2_MMR6\0"	---
8348	/* 5459 */ "MTC2_MMR6\0"	---	8348	/* 5459 */ "MTC2_MMR6\0"	---
8349	/* 5469 */ "LWC2_MMR6\0"	---	8349	/* 5469 */ "LWC2_MMR6\0"	---
8350	/* 5479 */ "SWC2_MMR6\0"	---	8350	/* 5479 */ "SWC2_MMR6\0"	---
8351	/* 5489 */ "LDC1_D64_MMR6\0"	---	8351	/* 5489 */ "LDC1_D64_MMR6\0"	---
8352	/* 5503 */ "SDC1_D64_MMR6\0"	---	8352	/* 5503 */ "SDC1_D64_MMR6\0"	---
8353	/* 5517 */ "SB16_MMR6\0"	---	8353	/* 5517 */ "SB16_MMR6\0"	---
8354	/* 5527 */ "BC16_MMR6\0"	---	8354	/* 5527 */ "BC16_MMR6\0"	---
8355	/* 5537 */ "JRC16_MMR6\0"	---	8355	/* 5537 */ "JRC16_MMR6\0"	---
8356	/* 5548 */ "JALRC16_MMR6\0"	---	8356	/* 5548 */ "JALRC16_MMR6\0"	---
8357	/* 5561 */ "BNEZC16_MMR6\0"	---	8357	/* 5561 */ "BNEZC16_MMR6\0"	---
8358	/* 5574 */ "BEQZC16_MMR6\0"	---	8358	/* 5574 */ "BEQZC16_MMR6\0"	---
8359	/* 5587 */ "AND16_MMR6\0"	---	8359	/* 5587 */ "AND16_MMR6\0"	---
8360	/* 5598 */ "MOVE16_MMR6\0"	---	8360	/* 5598 */ "MOVE16_MMR6\0"	---
8361	/* 5610 */ "SH16_MMR6\0"	---	8361	/* 5610 */ "SH16_MMR6\0"	---
8362	/* 5620 */ "ANDI16_MMR6\0"	---	8362	/* 5620 */ "ANDI16_MMR6\0"	---
8363	/* 5632 */ "LI16_MMR6\0"	---	8363	/* 5632 */ "LI16_MMR6\0"	---
8364	/* 5642 */ "BREAK16_MMR6\0"	---	8364	/* 5642 */ "BREAK16_MMR6\0"	---
8365	/* 5655 */ "SLL16_MMR6\0"	---	8365	/* 5655 */ "SLL16_MMR6\0"	---
8366	/* 5666 */ "SRL16_MMR6\0"	---	8366	/* 5666 */ "SRL16_MMR6\0"	---
8367	/* 5677 */ "LWM16_MMR6\0"	---	8367	/* 5677 */ "LWM16_MMR6\0"	---
8368	/* 5688 */ "SWM16_MMR6\0"	---	8368	/* 5688 */ "SWM16_MMR6\0"	---
8369	/* 5699 */ "SDBBP16_MMR6\0"	---	8369	/* 5699 */ "SDBBP16_MMR6\0"	---
8370	/* 5712 */ "XOR16_MMR6\0"	---	8370	/* 5712 */ "XOR16_MMR6\0"	---
8371	/* 5723 */ "NOT16_MMR6\0"	---	8371	/* 5723 */ "NOT16_MMR6\0"	---
8372	/* 5734 */ "SUBU16_MMR6\0"	---	8372	/* 5734 */ "SUBU16_MMR6\0"	---
8373	/* 5746 */ "ADDU16_MMR6\0"	---	8373	/* 5746 */ "ADDU16_MMR6\0"	---
8374	/* 5758 */ "SW16_MMR6\0"	---	8374	/* 5758 */ "SW16_MMR6\0"	---
8375	/* 5768 */ "LSA_MMR6\0"	---	8375	/* 5768 */ "LSA_MMR6\0"	---
8376	/* 5777 */ "EHB_MMR6\0"	---	8376	/* 5777 */ "EHB_MMR6\0"	---
8377	/* 5786 */ "JALRC_HB_MMR6\0"	---	8377	/* 5786 */ "JALRC_HB_MMR6\0"	---
8378	/* 5800 */ "LB_MMR6\0"	---	8378	/* 5800 */ "LB_MMR6\0"	---
8379	/* 5808 */ "SB_MMR6\0"	---	8379	/* 5808 */ "SB_MMR6\0"	---
8380	/* 5816 */ "SUB_MMR6\0"	---	8380	/* 5816 */ "SUB_MMR6\0"	---
8381	/* 5825 */ "BC_MMR6\0"	---	8381	/* 5825 */ "BC_MMR6\0"	---
8382	/* 5833 */ "BGEC_MMR6\0"	---	8382	/* 5833 */ "BGEC_MMR6\0"	---
8383	/* 5843 */ "BNEC_MMR6\0"	---	8383	/* 5843 */ "BNEC_MMR6\0"	---
8384	/* 5853 */ "JIC_MMR6\0"	---	8384	/* 5853 */ "JIC_MMR6\0"	---
8385	/* 5862 */ "BALC_MMR6\0"	---	8385	/* 5862 */ "BALC_MMR6\0"	---
8386	/* 5872 */ "JIALC_MMR6\0"	---	8386	/* 5872 */ "JIALC_MMR6\0"	---
8387	/* 5883 */ "BGEZALC_MMR6\0"	---	8387	/* 5883 */ "BGEZALC_MMR6\0"	---
8388	/* 5896 */ "BLEZALC_MMR6\0"	---	8388	/* 5896 */ "BLEZALC_MMR6\0"	---
8389	/* 5909 */ "BNEZALC_MMR6\0"	---	8389	/* 5909 */ "BNEZALC_MMR6\0"	---
8390	/* 5922 */ "BEQZALC_MMR6\0"	---	8390	/* 5922 */ "BEQZALC_MMR6\0"	---
8391	/* 5935 */ "BGTZALC_MMR6\0"	---	8391	/* 5935 */ "BGTZALC_MMR6\0"	---
8392	/* 5948 */ "BLTZALC_MMR6\0"	---	8392	/* 5948 */ "BLTZALC_MMR6\0"	---
8393	/* 5961 */ "ERETNC_MMR6\0"	---	8393	/* 5961 */ "ERETNC_MMR6\0"	---
8394	/* 5973 */ "SYNC_MMR6\0"	---	8394	/* 5973 */ "SYNC_MMR6\0"	---
8395	/* 5983 */ "AUIPC_MMR6\0"	---	8395	/* 5983 */ "AUIPC_MMR6\0"	---
8396	/* 5994 */ "ALUIPC_MMR6\0"	---	8396	/* 5994 */ "ALUIPC_MMR6\0"	---
8397	/* 6006 */ "ADDIUPC_MMR6\0"	---	8397	/* 6006 */ "ADDIUPC_MMR6\0"	---
8398	/* 6019 */ "LWPC_MMR6\0"	---	8398	/* 6019 */ "LWPC_MMR6\0"	---
8399	/* 6029 */ "BEQC_MMR6\0"	---	8399	/* 6029 */ "BEQC_MMR6\0"	---
8400	/* 6039 */ "JALRC_MMR6\0"	---	8400	/* 6039 */ "JALRC_MMR6\0"	---
8401	/* 6050 */ "SC_MMR6\0"	---	8401	/* 6050 */ "SC_MMR6\0"	---
8402	/* 6058 */ "BLTC_MMR6\0"	---	8402	/* 6058 */ "BLTC_MMR6\0"	---
8403	/* 6068 */ "BGEUC_MMR6\0"	---	8403	/* 6068 */ "BGEUC_MMR6\0"	---
8404	/* 6079 */ "BLTUC_MMR6\0"	---	8404	/* 6079 */ "BLTUC_MMR6\0"	---
8405	/* 6090 */ "BNVC_MMR6\0"	---	8405	/* 6090 */ "BNVC_MMR6\0"	---
8406	/* 6100 */ "BOVC_MMR6\0"	---	8406	/* 6100 */ "BOVC_MMR6\0"	---
8407	/* 6110 */ "BGEZC_MMR6\0"	---	8407	/* 6110 */ "BGEZC_MMR6\0"	---
8408	/* 6121 */ "BLEZC_MMR6\0"	---	8408	/* 6121 */ "BLEZC_MMR6\0"	---
8409	/* 6132 */ "BC1NEZC_MMR6\0"	---	8409	/* 6132 */ "BC1NEZC_MMR6\0"	---
8410	/* 6145 */ "BC2NEZC_MMR6\0"	---	8410	/* 6145 */ "BC2NEZC_MMR6\0"	---
8411	/* 6158 */ "BNEZC_MMR6\0"	---	8411	/* 6158 */ "BNEZC_MMR6\0"	---
8412	/* 6169 */ "BC1EQZC_MMR6\0"	---	8412	/* 6169 */ "BC1EQZC_MMR6\0"	---
8413	/* 6182 */ "BC2EQZC_MMR6\0"	---	8413	/* 6182 */ "BC2EQZC_MMR6\0"	---
8414	/* 6195 */ "BEQZC_MMR6\0"	---	8414	/* 6195 */ "BEQZC_MMR6\0"	---
8415	/* 6206 */ "BGTZC_MMR6\0"	---	8415	/* 6206 */ "BGTZC_MMR6\0"	---
8416	/* 6217 */ "BLTZC_MMR6\0"	---	8416	/* 6217 */ "BLTZC_MMR6\0"	---
8417	/* 6228 */ "ADD_MMR6\0"	---	8417	/* 6228 */ "ADD_MMR6\0"	---
8418	/* 6237 */ "AND_MMR6\0"	---	8418	/* 6237 */ "AND_MMR6\0"	---
8419	/* 6246 */ "MOD_MMR6\0"	---	8419	/* 6246 */ "MOD_MMR6\0"	---
8420	/* 6255 */ "MINA_D_MMR6\0"	---	8420	/* 6255 */ "MINA_D_MMR6\0"	---
8421	/* 6267 */ "MAXA_D_MMR6\0"	---	8421	/* 6267 */ "MAXA_D_MMR6\0"	---
8422	/* 6279 */ "CMP_SLE_D_MMR6\0"	---	8422	/* 6279 */ "CMP_SLE_D_MMR6\0"	---
8423	/* 6294 */ "CMP_SULE_D_MMR6\0"	---	8423	/* 6294 */ "CMP_SULE_D_MMR6\0"	---
8424	/* 6310 */ "CMP_ULE_D_MMR6\0"	---	8424	/* 6310 */ "CMP_ULE_D_MMR6\0"	---
8425	/* 6325 */ "CMP_LE_D_MMR6\0"	---	8425	/* 6325 */ "CMP_LE_D_MMR6\0"	---
8426	/* 6339 */ "CMP_SAF_D_MMR6\0"	---	8426	/* 6339 */ "CMP_SAF_D_MMR6\0"	---
8427	/* 6354 */ "CMP_AF_D_MMR6\0"	---	8427	/* 6354 */ "CMP_AF_D_MMR6\0"	---
8428	/* 6368 */ "MSUBF_D_MMR6\0"	---	8428	/* 6368 */ "MSUBF_D_MMR6\0"	---
8429	/* 6381 */ "MADDF_D_MMR6\0"	---	8429	/* 6381 */ "MADDF_D_MMR6\0"	---
8430	/* 6394 */ "SEL_D_MMR6\0"	---	8430	/* 6394 */ "SEL_D_MMR6\0"	---
8431	/* 6405 */ "TRUNC_L_D_MMR6\0"	---	8431	/* 6405 */ "TRUNC_L_D_MMR6\0"	---
8432	/* 6420 */ "ROUND_L_D_MMR6\0"	---	8432	/* 6420 */ "ROUND_L_D_MMR6\0"	---
8433	/* 6435 */ "CEIL_L_D_MMR6\0"	---	8433	/* 6435 */ "CEIL_L_D_MMR6\0"	---
8434	/* 6449 */ "FLOOR_L_D_MMR6\0"	---	8434	/* 6449 */ "FLOOR_L_D_MMR6\0"	---
8435	/* 6464 */ "CVT_L_D_MMR6\0"	---	8435	/* 6464 */ "CVT_L_D_MMR6\0"	---
8436	/* 6477 */ "MIN_D_MMR6\0"	---	8436	/* 6477 */ "MIN_D_MMR6\0"	---
8437	/* 6488 */ "CMP_SUN_D_MMR6\0"	---	8437	/* 6488 */ "CMP_SUN_D_MMR6\0"	---
8438	/* 6503 */ "CMP_UN_D_MMR6\0"	---	8438	/* 6503 */ "CMP_UN_D_MMR6\0"	---
8439	/* 6517 */ "CMP_SEQ_D_MMR6\0"	---	8439	/* 6517 */ "CMP_SEQ_D_MMR6\0"	---
8440	/* 6532 */ "CMP_SUEQ_D_MMR6\0"	---	8440	/* 6532 */ "CMP_SUEQ_D_MMR6\0"	---
8441	/* 6548 */ "CMP_UEQ_D_MMR6\0"	---	8441	/* 6548 */ "CMP_UEQ_D_MMR6\0"	---
8442	/* 6563 */ "CMP_EQ_D_MMR6\0"	---	8442	/* 6563 */ "CMP_EQ_D_MMR6\0"	---
8443	/* 6577 */ "CLASS_D_MMR6\0"	---	8443	/* 6577 */ "CLASS_D_MMR6\0"	---
8444	/* 6590 */ "CMP_SLT_D_MMR6\0"	---	8444	/* 6590 */ "CMP_SLT_D_MMR6\0"	---
8445	/* 6605 */ "CMP_SULT_D_MMR6\0"	---	8445	/* 6605 */ "CMP_SULT_D_MMR6\0"	---
8446	/* 6621 */ "CMP_ULT_D_MMR6\0"	---	8446	/* 6621 */ "CMP_ULT_D_MMR6\0"	---
8447	/* 6636 */ "CMP_LT_D_MMR6\0"	---	8447	/* 6636 */ "CMP_LT_D_MMR6\0"	---
8448	/* 6650 */ "RINT_D_MMR6\0"	---	8448	/* 6650 */ "RINT_D_MMR6\0"	---
8449	/* 6662 */ "FMOV_D_MMR6\0"	---	8449	/* 6662 */ "FMOV_D_MMR6\0"	---
8450	/* 6674 */ "TRUNC_W_D_MMR6\0"	---	8450	/* 6674 */ "TRUNC_W_D_MMR6\0"	---
8451	/* 6689 */ "ROUND_W_D_MMR6\0"	---	8451	/* 6689 */ "ROUND_W_D_MMR6\0"	---
8452	/* 6704 */ "CEIL_W_D_MMR6\0"	---	8452	/* 6704 */ "CEIL_W_D_MMR6\0"	---
8453	/* 6718 */ "FLOOR_W_D_MMR6\0"	---	8453	/* 6718 */ "FLOOR_W_D_MMR6\0"	---
8454	/* 6733 */ "MAX_D_MMR6\0"	---	8454	/* 6733 */ "MAX_D_MMR6\0"	---
8455	/* 6744 */ "SELNEZ_D_MMR6\0"	---	8455	/* 6744 */ "SELNEZ_D_MMR6\0"	---
8456	/* 6758 */ "SELEQZ_D_MMR6\0"	---	8456	/* 6758 */ "SELEQZ_D_MMR6\0"	---
8457	/* 6772 */ "CACHE_MMR6\0"	---	8457	/* 6772 */ "CACHE_MMR6\0"	---
8458	/* 6783 */ "SIGRIE_MMR6\0"	---	8458	/* 6783 */ "SIGRIE_MMR6\0"	---
8459	/* 6795 */ "PAUSE_MMR6\0"	---	8459	/* 6795 */ "PAUSE_MMR6\0"	---
8460	/* 6806 */ "PREF_MMR6\0"	---	8460	/* 6806 */ "PREF_MMR6\0"	---
8461	/* 6816 */ "TLBINVF_MMR6\0"	---	8461	/* 6816 */ "TLBINVF_MMR6\0"	---
8462	/* 6829 */ "TAILCALLREG_MMR6\0"	---	8462	/* 6829 */ "TAILCALLREG_MMR6\0"	---
8463	/* 6846 */ "WSBH_MMR6\0"	---	8463	/* 6846 */ "WSBH_MMR6\0"	---
8464	/* 6856 */ "SH_MMR6\0"	---	8464	/* 6856 */ "SH_MMR6\0"	---
8465	/* 6864 */ "MUH_MMR6\0"	---	8465	/* 6864 */ "MUH_MMR6\0"	---
8466	/* 6873 */ "SYNCI_MMR6\0"	---	8466	/* 6873 */ "SYNCI_MMR6\0"	---
8467	/* 6884 */ "ANDI_MMR6\0"	---	8467	/* 6884 */ "ANDI_MMR6\0"	---
8468	/* 6894 */ "EI_MMR6\0"	---	8468	/* 6894 */ "EI_MMR6\0"	---
8469	/* 6902 */ "XORI_MMR6\0"	---	8469	/* 6902 */ "XORI_MMR6\0"	---
8470	/* 6912 */ "AUI_MMR6\0"	---	8470	/* 6912 */ "AUI_MMR6\0"	---
8471	/* 6921 */ "LUI_MMR6\0"	---	8471	/* 6921 */ "LUI_MMR6\0"	---
8472	/* 6930 */ "GINVI_MMR6\0"	---	8472	/* 6930 */ "GINVI_MMR6\0"	---
8473	/* 6941 */ "BREAK_MMR6\0"	---	8473	/* 6941 */ "BREAK_MMR6\0"	---
8474	/* 6952 */ "JAL_MMR6\0"	---	8474	/* 6952 */ "JAL_MMR6\0"	---
8475	/* 6961 */ "TAILCALL_MMR6\0"	---	8475	/* 6961 */ "TAILCALL_MMR6\0"	---
8476	/* 6975 */ "SLL_MMR6\0"	---	8476	/* 6975 */ "SLL_MMR6\0"	---
8477	/* 6984 */ "MUL_MMR6\0"	---	8477	/* 6984 */ "MUL_MMR6\0"	---
8478	/* 6993 */ "CVT_D_L_MMR6\0"	---	8478	/* 6993 */ "CVT_D_L_MMR6\0"	---
8479	/* 7006 */ "CVT_S_L_MMR6\0"	---	8479	/* 7006 */ "CVT_S_L_MMR6\0"	---
8480	/* 7019 */ "ALIGN_MMR6\0"	---	8480	/* 7019 */ "ALIGN_MMR6\0"	---
8481	/* 7030 */ "CLO_MMR6\0"	---	8481	/* 7030 */ "CLO_MMR6\0"	---
8482	/* 7039 */ "BITSWAP_MMR6\0"	---	8482	/* 7039 */ "BITSWAP_MMR6\0"	---
8483	/* 7052 */ "SDBBP_MMR6\0"	---	8483	/* 7052 */ "SDBBP_MMR6\0"	---
8484	/* 7063 */ "MOVEP_MMR6\0"	---	8484	/* 7063 */ "MOVEP_MMR6\0"	---
8485	/* 7074 */ "SSNOP_MMR6\0"	---	8485	/* 7074 */ "SSNOP_MMR6\0"	---
8486	/* 7085 */ "JRCADDIUSP_MMR6\0"	---	8486	/* 7085 */ "JRCADDIUSP_MMR6\0"	---
8487	/* 7101 */ "SWSP_MMR6\0"	---	8487	/* 7101 */ "SWSP_MMR6\0"	---
8488	/* 7111 */ "DVP_MMR6\0"	---	8488	/* 7111 */ "DVP_MMR6\0"	---
8489	/* 7120 */ "EVP_MMR6\0"	---	8489	/* 7120 */ "EVP_MMR6\0"	---
8490	/* 7129 */ "NOR_MMR6\0"	---	8490	/* 7129 */ "NOR_MMR6\0"	---
8491	/* 7138 */ "XOR_MMR6\0"	---	8491	/* 7138 */ "XOR_MMR6\0"	---
8492	/* 7147 */ "RDPGPR_MMR6\0"	---	8492	/* 7147 */ "RDPGPR_MMR6\0"	---
8493	/* 7159 */ "WRPGPR_MMR6\0"	---	8493	/* 7159 */ "WRPGPR_MMR6\0"	---
8494	/* 7171 */ "RDHWR_MMR6\0"	---	8494	/* 7171 */ "RDHWR_MMR6\0"	---
8495	/* 7182 */ "INS_MMR6\0"	---	8495	/* 7182 */ "INS_MMR6\0"	---
8496	/* 7191 */ "MINA_S_MMR6\0"	---	8496	/* 7191 */ "MINA_S_MMR6\0"	---
8497	/* 7203 */ "MAXA_S_MMR6\0"	---	8497	/* 7203 */ "MAXA_S_MMR6\0"	---
8498	/* 7215 */ "FSUB_S_MMR6\0"	---	8498	/* 7215 */ "FSUB_S_MMR6\0"	---
8499	/* 7227 */ "FADD_S_MMR6\0"	---	8499	/* 7227 */ "FADD_S_MMR6\0"	---
8500	/* 7239 */ "CMP_SLE_S_MMR6\0"	---	8500	/* 7239 */ "CMP_SLE_S_MMR6\0"	---
8501	/* 7254 */ "CMP_SULE_S_MMR6\0"	---	8501	/* 7254 */ "CMP_SULE_S_MMR6\0"	---
8502	/* 7270 */ "CMP_ULE_S_MMR6\0"	---	8502	/* 7270 */ "CMP_ULE_S_MMR6\0"	---
8503	/* 7285 */ "CMP_LE_S_MMR6\0"	---	8503	/* 7285 */ "CMP_LE_S_MMR6\0"	---
8504	/* 7299 */ "CMP_SAF_S_MMR6\0"	---	8504	/* 7299 */ "CMP_SAF_S_MMR6\0"	---
8505	/* 7314 */ "CMP_AF_S_MMR6\0"	---	8505	/* 7314 */ "CMP_AF_S_MMR6\0"	---
8506	/* 7328 */ "MSUBF_S_MMR6\0"	---	8506	/* 7328 */ "MSUBF_S_MMR6\0"	---
8507	/* 7341 */ "MADDF_S_MMR6\0"	---	8507	/* 7341 */ "MADDF_S_MMR6\0"	---
8508	/* 7354 */ "FNEG_S_MMR6\0"	---	8508	/* 7354 */ "FNEG_S_MMR6\0"	---
8509	/* 7366 */ "SEL_S_MMR6\0"	---	8509	/* 7366 */ "SEL_S_MMR6\0"	---
8510	/* 7377 */ "FMUL_S_MMR6\0"	---	8510	/* 7377 */ "FMUL_S_MMR6\0"	---
8511	/* 7389 */ "TRUNC_L_S_MMR6\0"	---	8511	/* 7389 */ "TRUNC_L_S_MMR6\0"	---
8512	/* 7404 */ "ROUND_L_S_MMR6\0"	---	8512	/* 7404 */ "ROUND_L_S_MMR6\0"	---
8513	/* 7419 */ "CEIL_L_S_MMR6\0"	---	8513	/* 7419 */ "CEIL_L_S_MMR6\0"	---
8514	/* 7433 */ "FLOOR_L_S_MMR6\0"	---	8514	/* 7433 */ "FLOOR_L_S_MMR6\0"	---
8515	/* 7448 */ "CVT_L_S_MMR6\0"	---	8515	/* 7448 */ "CVT_L_S_MMR6\0"	---
8516	/* 7461 */ "MIN_S_MMR6\0"	---	8516	/* 7461 */ "MIN_S_MMR6\0"	---
8517	/* 7472 */ "CMP_SUN_S_MMR6\0"	---	8517	/* 7472 */ "CMP_SUN_S_MMR6\0"	---
8518	/* 7487 */ "CMP_UN_S_MMR6\0"	---	8518	/* 7487 */ "CMP_UN_S_MMR6\0"	---
8519	/* 7501 */ "CMP_SEQ_S_MMR6\0"	---	8519	/* 7501 */ "CMP_SEQ_S_MMR6\0"	---
8520	/* 7516 */ "CMP_SUEQ_S_MMR6\0"	---	8520	/* 7516 */ "CMP_SUEQ_S_MMR6\0"	---
8521	/* 7532 */ "CMP_UEQ_S_MMR6\0"	---	8521	/* 7532 */ "CMP_UEQ_S_MMR6\0"	---
8522	/* 7547 */ "CMP_EQ_S_MMR6\0"	---	8522	/* 7547 */ "CMP_EQ_S_MMR6\0"	---
8523	/* 7561 */ "CLASS_S_MMR6\0"	---	8523	/* 7561 */ "CLASS_S_MMR6\0"	---
8524	/* 7574 */ "CMP_SLT_S_MMR6\0"	---	8524	/* 7574 */ "CMP_SLT_S_MMR6\0"	---
8525	/* 7589 */ "CMP_SULT_S_MMR6\0"	---	8525	/* 7589 */ "CMP_SULT_S_MMR6\0"	---
8526	/* 7605 */ "CMP_ULT_S_MMR6\0"	---	8526	/* 7605 */ "CMP_ULT_S_MMR6\0"	---
8527	/* 7620 */ "CMP_LT_S_MMR6\0"	---	8527	/* 7620 */ "CMP_LT_S_MMR6\0"	---
8528	/* 7634 */ "RINT_S_MMR6\0"	---	8528	/* 7634 */ "RINT_S_MMR6\0"	---
8529	/* 7646 */ "FDIV_S_MMR6\0"	---	8529	/* 7646 */ "FDIV_S_MMR6\0"	---
8530	/* 7658 */ "FMOV_S_MMR6\0"	---	8530	/* 7658 */ "FMOV_S_MMR6\0"	---
8531	/* 7670 */ "TRUNC_W_S_MMR6\0"	---	8531	/* 7670 */ "TRUNC_W_S_MMR6\0"	---
8532	/* 7685 */ "ROUND_W_S_MMR6\0"	---	8532	/* 7685 */ "ROUND_W_S_MMR6\0"	---
8533	/* 7700 */ "CEIL_W_S_MMR6\0"	---	8533	/* 7700 */ "CEIL_W_S_MMR6\0"	---
8534	/* 7714 */ "FLOOR_W_S_MMR6\0"	---	8534	/* 7714 */ "FLOOR_W_S_MMR6\0"	---
8535	/* 7729 */ "CVT_W_S_MMR6\0"	---	8535	/* 7729 */ "CVT_W_S_MMR6\0"	---
8536	/* 7742 */ "MAX_S_MMR6\0"	---	8536	/* 7742 */ "MAX_S_MMR6\0"	---
8537	/* 7753 */ "SELNEZ_S_MMR6\0"	---	8537	/* 7753 */ "SELNEZ_S_MMR6\0"	---
8538	/* 7767 */ "SELEQZ_S_MMR6\0"	---	8538	/* 7767 */ "SELEQZ_S_MMR6\0"	---
8539	/* 7781 */ "DERET_MMR6\0"	---	8539	/* 7781 */ "DERET_MMR6\0"	---
8540	/* 7792 */ "WAIT_MMR6\0"	---	8540	/* 7792 */ "WAIT_MMR6\0"	---
8541	/* 7802 */ "GINVT_MMR6\0"	---	8541	/* 7802 */ "GINVT_MMR6\0"	---
8542	/* 7813 */ "EXT_MMR6\0"	---	8542	/* 7813 */ "EXT_MMR6\0"	---
8543	/* 7822 */ "LBU_MMR6\0"	---	8543	/* 7822 */ "LBU_MMR6\0"	---
8544	/* 7831 */ "SUBU_MMR6\0"	---	8544	/* 7831 */ "SUBU_MMR6\0"	---
8545	/* 7841 */ "ADDU_MMR6\0"	---	8545	/* 7841 */ "ADDU_MMR6\0"	---
8546	/* 7851 */ "MODU_MMR6\0"	---	8546	/* 7851 */ "MODU_MMR6\0"	---
8547	/* 7861 */ "MUHU_MMR6\0"	---	8547	/* 7861 */ "MUHU_MMR6\0"	---
8548	/* 7871 */ "ADDIU_MMR6\0"	---	8548	/* 7871 */ "ADDIU_MMR6\0"	---
8549	/* 7882 */ "MULU_MMR6\0"	---	8549	/* 7882 */ "MULU_MMR6\0"	---
8550	/* 7892 */ "DIVU_MMR6\0"	---	8550	/* 7892 */ "DIVU_MMR6\0"	---
8551	/* 7902 */ "DIV_MMR6\0"	---	8551	/* 7902 */ "DIV_MMR6\0"	---
8552	/* 7911 */ "TLBINV_MMR6\0"	---	8552	/* 7911 */ "TLBINV_MMR6\0"	---
8553	/* 7923 */ "LW_MMR6\0"	---	8553	/* 7923 */ "LW_MMR6\0"	---
8554	/* 7931 */ "SW_MMR6\0"	---	8554	/* 7931 */ "SW_MMR6\0"	---
8555	/* 7939 */ "CVT_S_W_MMR6\0"	---	8555	/* 7939 */ "CVT_S_W_MMR6\0"	---
8556	/* 7952 */ "SELNEZ_MMR6\0"	---	8556	/* 7952 */ "SELNEZ_MMR6\0"	---
8557	/* 7964 */ "CLZ_MMR6\0"	---	8557	/* 7964 */ "CLZ_MMR6\0"	---
8558	/* 7973 */ "SELEQZ_MMR6\0"	---	8558	/* 7973 */ "SELEQZ_MMR6\0"	---
8559	/* 7985 */ "PseudoIndirectBranch_MMR6\0"	---	8559	/* 7985 */ "PseudoIndirectBranch_MMR6\0"	---
8560	/* 8011 */ "LDC2_R6\0"	---	8560	/* 8011 */ "LDC2_R6\0"	---
8561	/* 8019 */ "SDC2_R6\0"	---	8561	/* 8019 */ "SDC2_R6\0"	---
8562	/* 8027 */ "LWC2_R6\0"	---	8562	/* 8027 */ "LWC2_R6\0"	---
8563	/* 8035 */ "SWC2_R6\0"	---	8563	/* 8035 */ "SWC2_R6\0"	---
8564	/* 8043 */ "JR_HB64_R6\0"	---	8564	/* 8043 */ "JR_HB64_R6\0"	---
8565	/* 8054 */ "SC64_R6\0"	---	8565	/* 8054 */ "SC64_R6\0"	---
8566	/* 8062 */ "LL64_R6\0"	---	8566	/* 8062 */ "LL64_R6\0"	---
8567	/* 8070 */ "DLSA_R6\0"	---	8567	/* 8070 */ "DLSA_R6\0"	---
8568	/* 8078 */ "JR_HB_R6\0"	---	8568	/* 8078 */ "JR_HB_R6\0"	---
8569	/* 8087 */ "SC_R6\0"	---	8569	/* 8087 */ "SC_R6\0"	---
8570	/* 8093 */ "SCD_R6\0"	---	8570	/* 8093 */ "SCD_R6\0"	---
8571	/* 8100 */ "LLD_R6\0"	---	8571	/* 8100 */ "LLD_R6\0"	---
8572	/* 8107 */ "CACHE_R6\0"	---	8572	/* 8107 */ "CACHE_R6\0"	---
8573	/* 8116 */ "PREF_R6\0"	---	8573	/* 8116 */ "PREF_R6\0"	---
8574	/* 8124 */ "LL_R6\0"	---	8574	/* 8124 */ "LL_R6\0"	---
8575	/* 8130 */ "DMUL_R6\0"	---	8575	/* 8130 */ "DMUL_R6\0"	---
8576	/* 8138 */ "DCLO_R6\0"	---	8576	/* 8138 */ "DCLO_R6\0"	---
8577	/* 8146 */ "SDBBP_R6\0"	---	8577	/* 8146 */ "SDBBP_R6\0"	---
8578	/* 8155 */ "DCLZ_R6\0"	---	8578	/* 8155 */ "DCLZ_R6\0"	---
8579	/* 8163 */ "PseudoIndrectHazardBranchR6\0"	---	8579	/* 8163 */ "PseudoIndrectHazardBranchR6\0"	---
8580	/* 8191 */ "PseudoIndirectBranchR6\0"	---	8580	/* 8191 */ "PseudoIndirectBranchR6\0"	---
8581	/* 8214 */ "LOAD_ACC128\0"	---	8581	/* 8214 */ "LOAD_ACC128\0"	---
8582	/* 8226 */ "STORE_ACC128\0"	---	8582	/* 8226 */ "STORE_ACC128\0"	---
8583	/* 8239 */ "ATOMIC_LOAD_SUB_I8\0"	---	8583	/* 8239 */ "ATOMIC_LOAD_SUB_I8\0"	---
8584	/* 8258 */ "ATOMIC_LOAD_ADD_I8\0"	---	8584	/* 8258 */ "ATOMIC_LOAD_ADD_I8\0"	---
8585	/* 8277 */ "ATOMIC_LOAD_NAND_I8\0"	---	8585	/* 8277 */ "ATOMIC_LOAD_NAND_I8\0"	---
8586	/* 8297 */ "ATOMIC_LOAD_AND_I8\0"	---	8586	/* 8297 */ "ATOMIC_LOAD_AND_I8\0"	---
8587	/* 8316 */ "ATOMIC_LOAD_UMIN_I8\0"	---	8587	/* 8316 */ "ATOMIC_LOAD_UMIN_I8\0"	---
8588	/* 8336 */ "ATOMIC_LOAD_MIN_I8\0"	---	8588	/* 8336 */ "ATOMIC_LOAD_MIN_I8\0"	---
8589	/* 8355 */ "ATOMIC_SWAP_I8\0"	---	8589	/* 8355 */ "ATOMIC_SWAP_I8\0"	---
8590	/* 8370 */ "ATOMIC_CMP_SWAP_I8\0"	---	8590	/* 8370 */ "ATOMIC_CMP_SWAP_I8\0"	---
8591	/* 8389 */ "ATOMIC_LOAD_XOR_I8\0"	---	8591	/* 8389 */ "ATOMIC_LOAD_XOR_I8\0"	---
8592	/* 8408 */ "ATOMIC_LOAD_OR_I8\0"	---	8592	/* 8408 */ "ATOMIC_LOAD_OR_I8\0"	---
8593	/* 8426 */ "ATOMIC_LOAD_UMAX_I8\0"	---	8593	/* 8426 */ "ATOMIC_LOAD_UMAX_I8\0"	---
8594	/* 8446 */ "ATOMIC_LOAD_MAX_I8\0"	---	8594	/* 8446 */ "ATOMIC_LOAD_MAX_I8\0"	---
8595	/* 8465 */ "SAA\0"	---	8595	/* 8465 */ "SAA\0"	---
8596	/* 8469 */ "PRECEU_PH_QBLA\0"	---	8596	/* 8469 */ "PRECEU_PH_QBLA\0"	---
8597	/* 8484 */ "PRECEQU_PH_QBLA\0"	---	8597	/* 8484 */ "PRECEQU_PH_QBLA\0"	---
8598	/* 8500 */ "G_FMA\0"	---	8598	/* 8500 */ "G_FMA\0"	---
8599	/* 8506 */ "G_STRICT_FMA\0"	---	8599	/* 8506 */ "G_STRICT_FMA\0"	---
8600	/* 8519 */ "PRECEU_PH_QBRA\0"	---	8600	/* 8519 */ "PRECEU_PH_QBRA\0"	---
8601	/* 8534 */ "PRECEQU_PH_QBRA\0"	---	8601	/* 8534 */ "PRECEQU_PH_QBRA\0"	---
8602	/* 8550 */ "DSRA\0"	---	8602	/* 8550 */ "DSRA\0"	---
8603	/* 8555 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"	---	8603	/* 8555 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"	---
8604	/* 8582 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"	---	8604	/* 8582 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"	---
8605	/* 8609 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"	---	8605	/* 8609 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"	---
8606	/* 8637 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"	---	8606	/* 8637 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"	---
8607	/* 8664 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"	---	8607	/* 8664 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"	---
8608	/* 8692 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"	---	8608	/* 8692 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"	---
8609	/* 8719 */ "ATOMIC_SWAP_I32_POSTRA\0"	---	8609	/* 8719 */ "ATOMIC_SWAP_I32_POSTRA\0"	---
8610	/* 8742 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"	---	8610	/* 8742 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"	---
8611	/* 8769 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"	---	8611	/* 8769 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"	---
8612	/* 8796 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"	---	8612	/* 8796 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"	---
8613	/* 8822 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"	---	8613	/* 8822 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"	---
8614	/* 8850 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"	---	8614	/* 8850 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"	---
8615	/* 8877 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"	---	8615	/* 8877 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"	---
8616	/* 8904 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"	---	8616	/* 8904 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"	---
8617	/* 8931 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"	---	8617	/* 8931 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"	---
8618	/* 8959 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"	---	8618	/* 8959 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"	---
8619	/* 8986 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"	---	8619	/* 8986 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"	---
8620	/* 9014 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"	---	8620	/* 9014 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"	---
8621	/* 9041 */ "ATOMIC_SWAP_I64_POSTRA\0"	---	8621	/* 9041 */ "ATOMIC_SWAP_I64_POSTRA\0"	---
8622	/* 9064 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"	---	8622	/* 9064 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"	---
8623	/* 9091 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"	---	8623	/* 9091 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"	---
8624	/* 9118 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"	---	8624	/* 9118 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"	---
8625	/* 9144 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"	---	8625	/* 9144 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"	---
8626	/* 9172 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"	---	8626	/* 9172 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"	---
8627	/* 9199 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"	---	8627	/* 9199 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"	---
8628	/* 9226 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"	---	8628	/* 9226 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"	---
8629	/* 9253 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"	---	8629	/* 9253 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"	---
8630	/* 9281 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"	---	8630	/* 9281 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"	---
8631	/* 9308 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"	---	8631	/* 9308 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"	---
8632	/* 9336 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"	---	8632	/* 9336 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"	---
8633	/* 9363 */ "ATOMIC_SWAP_I16_POSTRA\0"	---	8633	/* 9363 */ "ATOMIC_SWAP_I16_POSTRA\0"	---
8634	/* 9386 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"	---	8634	/* 9386 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"	---
8635	/* 9413 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"	---	8635	/* 9413 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"	---
8636	/* 9440 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"	---	8636	/* 9440 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"	---
8637	/* 9466 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"	---	8637	/* 9466 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"	---
8638	/* 9494 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"	---	8638	/* 9494 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"	---
8639	/* 9521 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"	---	8639	/* 9521 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"	---
8640	/* 9547 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"	---	8640	/* 9547 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"	---
8641	/* 9573 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"	---	8641	/* 9573 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"	---
8642	/* 9600 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"	---	8642	/* 9600 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"	---
8643	/* 9626 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"	---	8643	/* 9626 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"	---
8644	/* 9653 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"	---	8644	/* 9653 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"	---
8645	/* 9679 */ "ATOMIC_SWAP_I8_POSTRA\0"	---	8645	/* 9679 */ "ATOMIC_SWAP_I8_POSTRA\0"	---
8646	/* 9701 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"	---	8646	/* 9701 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"	---
8647	/* 9727 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"	---	8647	/* 9727 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"	---
8648	/* 9753 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"	---	8648	/* 9753 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"	---
8649	/* 9778 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"	---	8649	/* 9778 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"	---
8650	/* 9805 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"	---	8650	/* 9805 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"	---
8651	/* 9831 */ "RetRA\0"	---	8651	/* 9831 */ "RetRA\0"	---
8652	/* 9837 */ "DLSA\0"	---	8652	/* 9837 */ "DLSA\0"	---
8653	/* 9842 */ "CFCMSA\0"	---	8653	/* 9842 */ "CFCMSA\0"	---
8654	/* 9849 */ "CTCMSA\0"	---	8654	/* 9849 */ "CTCMSA\0"	---
8655	/* 9856 */ "CRC32B\0"	---	8655	/* 9856 */ "CRC32B\0"	---
8656	/* 9863 */ "CRC32CB\0"	---	8656	/* 9863 */ "CRC32CB\0"	---
8657	/* 9871 */ "SEB\0"	---	8657	/* 9871 */ "SEB\0"	---
8658	/* 9875 */ "EHB\0"	---	8658	/* 9875 */ "EHB\0"	---
8659	/* 9879 */ "TAILCALLREGHB\0"	---	8659	/* 9879 */ "TAILCALLREGHB\0"	---
8660	/* 9893 */ "JR_HB\0"	---	8660	/* 9893 */ "JR_HB\0"	---
8661	/* 9899 */ "JALR_HB\0"	---	8661	/* 9899 */ "JALR_HB\0"	---
8662	/* 9907 */ "LB\0"	---	8662	/* 9907 */ "LB\0"	---
8663	/* 9910 */ "SHRA_QB\0"	---	8663	/* 9910 */ "SHRA_QB\0"	---
8664	/* 9918 */ "CMPGDU_LE_QB\0"	---	8664	/* 9918 */ "CMPGDU_LE_QB\0"	---
8665	/* 9931 */ "CMPGU_LE_QB\0"	---	8665	/* 9931 */ "CMPGU_LE_QB\0"	---
8666	/* 9943 */ "PseudoCMPU_LE_QB\0"	---	8666	/* 9943 */ "PseudoCMPU_LE_QB\0"	---
8667	/* 9960 */ "SUBUH_QB\0"	---	8667	/* 9960 */ "SUBUH_QB\0"	---
8668	/* 9969 */ "ADDUH_QB\0"	---	8668	/* 9969 */ "ADDUH_QB\0"	---
8669	/* 9978 */ "PseudoPICK_QB\0"	---	8669	/* 9978 */ "PseudoPICK_QB\0"	---
8670	/* 9992 */ "SHLL_QB\0"	---	8670	/* 9992 */ "SHLL_QB\0"	---
8671	/* 10000 */ "REPL_QB\0"	---	8671	/* 10000 */ "REPL_QB\0"	---
8672	/* 10008 */ "SHRL_QB\0"	---	8672	/* 10008 */ "SHRL_QB\0"	---
8673	/* 10016 */ "CMPGDU_EQ_QB\0"	---	8673	/* 10016 */ "CMPGDU_EQ_QB\0"	---
8674	/* 10029 */ "CMPGU_EQ_QB\0"	---	8674	/* 10029 */ "CMPGU_EQ_QB\0"	---
8675	/* 10041 */ "PseudoCMPU_EQ_QB\0"	---	8675	/* 10041 */ "PseudoCMPU_EQ_QB\0"	---
8676	/* 10058 */ "SHRA_R_QB\0"	---	8676	/* 10058 */ "SHRA_R_QB\0"	---
8677	/* 10068 */ "SUBUH_R_QB\0"	---	8677	/* 10068 */ "SUBUH_R_QB\0"	---
8678	/* 10079 */ "ADDUH_R_QB\0"	---	8678	/* 10079 */ "ADDUH_R_QB\0"	---
8679	/* 10090 */ "SHRAV_R_QB\0"	---	8679	/* 10090 */ "SHRAV_R_QB\0"	---
8680	/* 10101 */ "ABSQ_S_QB\0"	---	8680	/* 10101 */ "ABSQ_S_QB\0"	---
8681	/* 10111 */ "SUBU_S_QB\0"	---	8681	/* 10111 */ "SUBU_S_QB\0"	---
8682	/* 10121 */ "ADDU_S_QB\0"	---	8682	/* 10121 */ "ADDU_S_QB\0"	---
8683	/* 10131 */ "CMPGDU_LT_QB\0"	---	8683	/* 10131 */ "CMPGDU_LT_QB\0"	---
8684	/* 10144 */ "CMPGU_LT_QB\0"	---	8684	/* 10144 */ "CMPGU_LT_QB\0"	---
8685	/* 10156 */ "PseudoCMPU_LT_QB\0"	---	8685	/* 10156 */ "PseudoCMPU_LT_QB\0"	---
8686	/* 10173 */ "SUBU_QB\0"	---	8686	/* 10173 */ "SUBU_QB\0"	---
8687	/* 10181 */ "ADDU_QB\0"	---	8687	/* 10181 */ "ADDU_QB\0"	---
8688	/* 10189 */ "SHRAV_QB\0"	---	8688	/* 10189 */ "SHRAV_QB\0"	---
8689	/* 10198 */ "SHLLV_QB\0"	---	8689	/* 10198 */ "SHLLV_QB\0"	---
8690	/* 10207 */ "REPLV_QB\0"	---	8690	/* 10207 */ "REPLV_QB\0"	---
8691	/* 10216 */ "SHRLV_QB\0"	---	8691	/* 10216 */ "SHRLV_QB\0"	---
8692	/* 10225 */ "RADDU_W_QB\0"	---	8692	/* 10225 */ "RADDU_W_QB\0"	---
8693	/* 10236 */ "SB\0"	---	8693	/* 10236 */ "SB\0"	---
8694	/* 10239 */ "MODSUB\0"	---	8694	/* 10239 */ "MODSUB\0"	---
8695	/* 10246 */ "G_FSUB\0"	---	8695	/* 10246 */ "G_FSUB\0"	---
8696	/* 10253 */ "G_STRICT_FSUB\0"	---	8696	/* 10253 */ "G_STRICT_FSUB\0"	---
8697	/* 10267 */ "G_ATOMICRMW_FSUB\0"	---	8697	/* 10267 */ "G_ATOMICRMW_FSUB\0"	---
8698	/* 10284 */ "PseudoMSUB\0"	---	8698	/* 10284 */ "PseudoMSUB\0"	---
8699	/* 10295 */ "G_SUB\0"	---	8699	/* 10295 */ "G_SUB\0"	---
8700	/* 10301 */ "G_ATOMICRMW_SUB\0"	---	8700	/* 10301 */ "G_ATOMICRMW_SUB\0"	---
8701	/* 10317 */ "SRA_B\0"	---	8701	/* 10317 */ "SRA_B\0"	---
8702	/* 10323 */ "ADD_A_B\0"	---	8702	/* 10323 */ "ADD_A_B\0"	---
8703	/* 10331 */ "MIN_A_B\0"	---	8703	/* 10331 */ "MIN_A_B\0"	---
8704	/* 10339 */ "ADDS_A_B\0"	---	8704	/* 10339 */ "ADDS_A_B\0"	---
8705	/* 10348 */ "MAX_A_B\0"	---	8705	/* 10348 */ "MAX_A_B\0"	---
8706	/* 10356 */ "NLOC_B\0"	---	8706	/* 10356 */ "NLOC_B\0"	---
8707	/* 10363 */ "NLZC_B\0"	---	8707	/* 10363 */ "NLZC_B\0"	---
8708	/* 10370 */ "SLD_B\0"	---	8708	/* 10370 */ "SLD_B\0"	---
8709	/* 10376 */ "PCKOD_B\0"	---	8709	/* 10376 */ "PCKOD_B\0"	---
8710	/* 10384 */ "ILVOD_B\0"	---	8710	/* 10384 */ "ILVOD_B\0"	---
8711	/* 10392 */ "INSVE_B\0"	---	8711	/* 10392 */ "INSVE_B\0"	---
8712	/* 10400 */ "VSHF_B\0"	---	8712	/* 10400 */ "VSHF_B\0"	---
8713	/* 10407 */ "BNEG_B\0"	---	8713	/* 10407 */ "BNEG_B\0"	---
8714	/* 10414 */ "SRAI_B\0"	---	8714	/* 10414 */ "SRAI_B\0"	---
8715	/* 10421 */ "SLDI_B\0"	---	8715	/* 10421 */ "SLDI_B\0"	---
8716	/* 10428 */ "ANDI_B\0"	---	8716	/* 10428 */ "ANDI_B\0"	---
8717	/* 10435 */ "BNEGI_B\0"	---	8717	/* 10435 */ "BNEGI_B\0"	---
8718	/* 10443 */ "BSELI_B\0"	---	8718	/* 10443 */ "BSELI_B\0"	---
8719	/* 10451 */ "SLLI_B\0"	---	8719	/* 10451 */ "SLLI_B\0"	---
8720	/* 10458 */ "SRLI_B\0"	---	8720	/* 10458 */ "SRLI_B\0"	---
8721	/* 10465 */ "BINSLI_B\0"	---	8721	/* 10465 */ "BINSLI_B\0"	---
8722	/* 10474 */ "CEQI_B\0"	---	8722	/* 10474 */ "CEQI_B\0"	---
8723	/* 10481 */ "SRARI_B\0"	---	8723	/* 10481 */ "SRARI_B\0"	---
8724	/* 10489 */ "BCLRI_B\0"	---	8724	/* 10489 */ "BCLRI_B\0"	---
8725	/* 10497 */ "SRLRI_B\0"	---	8725	/* 10497 */ "SRLRI_B\0"	---
8726	/* 10505 */ "NORI_B\0"	---	8726	/* 10505 */ "NORI_B\0"	---
8727	/* 10512 */ "XORI_B\0"	---	8727	/* 10512 */ "XORI_B\0"	---
8728	/* 10519 */ "BINSRI_B\0"	---	8728	/* 10519 */ "BINSRI_B\0"	---
8729	/* 10528 */ "SPLATI_B\0"	---	8729	/* 10528 */ "SPLATI_B\0"	---
8730	/* 10537 */ "BSETI_B\0"	---	8730	/* 10537 */ "BSETI_B\0"	---
8731	/* 10545 */ "SUBVI_B\0"	---	8731	/* 10545 */ "SUBVI_B\0"	---
8732	/* 10553 */ "ADDVI_B\0"	---	8732	/* 10553 */ "ADDVI_B\0"	---
8733	/* 10561 */ "BMZI_B\0"	---	8733	/* 10561 */ "BMZI_B\0"	---
8734	/* 10568 */ "BMNZI_B\0"	---	8734	/* 10568 */ "BMNZI_B\0"	---
8735	/* 10576 */ "FILL_B\0"	---	8735	/* 10576 */ "FILL_B\0"	---
8736	/* 10583 */ "SLL_B\0"	---	8736	/* 10583 */ "SLL_B\0"	---
8737	/* 10589 */ "SRL_B\0"	---	8737	/* 10589 */ "SRL_B\0"	---
8738	/* 10595 */ "BINSL_B\0"	---	8738	/* 10595 */ "BINSL_B\0"	---
8739	/* 10603 */ "ILVL_B\0"	---	8739	/* 10603 */ "ILVL_B\0"	---
8740	/* 10610 */ "CEQ_B\0"	---	8740	/* 10610 */ "CEQ_B\0"	---
8741	/* 10616 */ "SRAR_B\0"	---	8741	/* 10616 */ "SRAR_B\0"	---
8742	/* 10623 */ "BCLR_B\0"	---	8742	/* 10623 */ "BCLR_B\0"	---
8743	/* 10630 */ "SRLR_B\0"	---	8743	/* 10630 */ "SRLR_B\0"	---
8744	/* 10637 */ "BINSR_B\0"	---	8744	/* 10637 */ "BINSR_B\0"	---
8745	/* 10645 */ "ILVR_B\0"	---	8745	/* 10645 */ "ILVR_B\0"	---
8746	/* 10652 */ "ASUB_S_B\0"	---	8746	/* 10652 */ "ASUB_S_B\0"	---
8747	/* 10661 */ "MOD_S_B\0"	---	8747	/* 10661 */ "MOD_S_B\0"	---
8748	/* 10669 */ "CLE_S_B\0"	---	8748	/* 10669 */ "CLE_S_B\0"	---
8749	/* 10677 */ "AVE_S_B\0"	---	8749	/* 10677 */ "AVE_S_B\0"	---
8750	/* 10685 */ "CLEI_S_B\0"	---	8750	/* 10685 */ "CLEI_S_B\0"	---
8751	/* 10694 */ "MINI_S_B\0"	---	8751	/* 10694 */ "MINI_S_B\0"	---
8752	/* 10703 */ "CLTI_S_B\0"	---	8752	/* 10703 */ "CLTI_S_B\0"	---
8753	/* 10712 */ "MAXI_S_B\0"	---	8753	/* 10712 */ "MAXI_S_B\0"	---
8754	/* 10721 */ "MIN_S_B\0"	---	8754	/* 10721 */ "MIN_S_B\0"	---
8755	/* 10729 */ "AVER_S_B\0"	---	8755	/* 10729 */ "AVER_S_B\0"	---
8756	/* 10738 */ "SUBS_S_B\0"	---	8756	/* 10738 */ "SUBS_S_B\0"	---
8757	/* 10747 */ "ADDS_S_B\0"	---	8757	/* 10747 */ "ADDS_S_B\0"	---
8758	/* 10756 */ "SAT_S_B\0"	---	8758	/* 10756 */ "SAT_S_B\0"	---
8759	/* 10764 */ "CLT_S_B\0"	---	8759	/* 10764 */ "CLT_S_B\0"	---
8760	/* 10772 */ "SUBSUU_S_B\0"	---	8760	/* 10772 */ "SUBSUU_S_B\0"	---
8761	/* 10783 */ "DIV_S_B\0"	---	8761	/* 10783 */ "DIV_S_B\0"	---
8762	/* 10791 */ "MAX_S_B\0"	---	8762	/* 10791 */ "MAX_S_B\0"	---
8763	/* 10799 */ "COPY_S_B\0"	---	8763	/* 10799 */ "COPY_S_B\0"	---
8764	/* 10808 */ "SPLAT_B\0"	---	8764	/* 10808 */ "SPLAT_B\0"	---
8765	/* 10816 */ "BSET_B\0"	---	8765	/* 10816 */ "BSET_B\0"	---
8766	/* 10823 */ "PCNT_B\0"	---	8766	/* 10823 */ "PCNT_B\0"	---
8767	/* 10830 */ "INSERT_B\0"	---	8767	/* 10830 */ "INSERT_B\0"	---
8768	/* 10839 */ "ST_B\0"	---	8768	/* 10839 */ "ST_B\0"	---
8769	/* 10844 */ "ASUB_U_B\0"	---	8769	/* 10844 */ "ASUB_U_B\0"	---
8770	/* 10853 */ "MOD_U_B\0"	---	8770	/* 10853 */ "MOD_U_B\0"	---
8771	/* 10861 */ "CLE_U_B\0"	---	8771	/* 10861 */ "CLE_U_B\0"	---
8772	/* 10869 */ "AVE_U_B\0"	---	8772	/* 10869 */ "AVE_U_B\0"	---
8773	/* 10877 */ "CLEI_U_B\0"	---	8773	/* 10877 */ "CLEI_U_B\0"	---
8774	/* 10886 */ "MINI_U_B\0"	---	8774	/* 10886 */ "MINI_U_B\0"	---
8775	/* 10895 */ "CLTI_U_B\0"	---	8775	/* 10895 */ "CLTI_U_B\0"	---
8776	/* 10904 */ "MAXI_U_B\0"	---	8776	/* 10904 */ "MAXI_U_B\0"	---
8777	/* 10913 */ "MIN_U_B\0"	---	8777	/* 10913 */ "MIN_U_B\0"	---
8778	/* 10921 */ "AVER_U_B\0"	---	8778	/* 10921 */ "AVER_U_B\0"	---
8779	/* 10930 */ "SUBS_U_B\0"	---	8779	/* 10930 */ "SUBS_U_B\0"	---
8780	/* 10939 */ "ADDS_U_B\0"	---	8780	/* 10939 */ "ADDS_U_B\0"	---
8781	/* 10948 */ "SUBSUS_U_B\0"	---	8781	/* 10948 */ "SUBSUS_U_B\0"	---
8782	/* 10959 */ "SAT_U_B\0"	---	8782	/* 10959 */ "SAT_U_B\0"	---
8783	/* 10967 */ "CLT_U_B\0"	---	8783	/* 10967 */ "CLT_U_B\0"	---
8784	/* 10975 */ "DIV_U_B\0"	---	8784	/* 10975 */ "DIV_U_B\0"	---
8785	/* 10983 */ "MAX_U_B\0"	---	8785	/* 10983 */ "MAX_U_B\0"	---
8786	/* 10991 */ "COPY_U_B\0"	---	8786	/* 10991 */ "COPY_U_B\0"	---
8787	/* 11000 */ "MSUBV_B\0"	---	8787	/* 11000 */ "MSUBV_B\0"	---
8788	/* 11008 */ "MADDV_B\0"	---	8788	/* 11008 */ "MADDV_B\0"	---
8789	/* 11016 */ "PCKEV_B\0"	---	8789	/* 11016 */ "PCKEV_B\0"	---
8790	/* 11024 */ "ILVEV_B\0"	---	8790	/* 11024 */ "ILVEV_B\0"	---
8791	/* 11032 */ "MULV_B\0"	---	8791	/* 11032 */ "MULV_B\0"	---
8792	/* 11039 */ "BZ_B\0"	---	8792	/* 11039 */ "BZ_B\0"	---
8793	/* 11044 */ "BNZ_B\0"	---	8793	/* 11044 */ "BNZ_B\0"	---
8794	/* 11050 */ "BC\0"	---	8794	/* 11050 */ "BC\0"	---
8795	/* 11053 */ "BGEC\0"	---	8795	/* 11053 */ "BGEC\0"	---
8796	/* 11058 */ "BNEC\0"	---	8796	/* 11058 */ "BNEC\0"	---
8797	/* 11063 */ "JIC\0"	---	8797	/* 11063 */ "JIC\0"	---
8798	/* 11067 */ "G_INTRINSIC\0"	---	8798	/* 11067 */ "G_INTRINSIC\0"	---
8799	/* 11079 */ "BALC\0"	---	8799	/* 11079 */ "BALC\0"	---
8800	/* 11084 */ "JIALC\0"	---	8800	/* 11084 */ "JIALC\0"	---
8801	/* 11090 */ "BGEZALC\0"	---	8801	/* 11090 */ "BGEZALC\0"	---
8802	/* 11098 */ "BLEZALC\0"	---	8802	/* 11098 */ "BLEZALC\0"	---
8803	/* 11106 */ "BNEZALC\0"	---	8803	/* 11106 */ "BNEZALC\0"	---
8804	/* 11114 */ "BEQZALC\0"	---	8804	/* 11114 */ "BEQZALC\0"	---
8805	/* 11122 */ "BGTZALC\0"	---	8805	/* 11122 */ "BGTZALC\0"	---
8806	/* 11130 */ "BLTZALC\0"	---	8806	/* 11130 */ "BLTZALC\0"	---
8807	/* 11138 */ "ERETNC\0"	---	8807	/* 11138 */ "ERETNC\0"	---
8808	/* 11145 */ "G_FPTRUNC\0"	---	8808	/* 11145 */ "G_FPTRUNC\0"	---
8809	/* 11155 */ "G_INTRINSIC_TRUNC\0"	---	8809	/* 11155 */ "G_INTRINSIC_TRUNC\0"	---
8810	/* 11173 */ "G_TRUNC\0"	---	8810	/* 11173 */ "G_TRUNC\0"	---
8811	/* 11181 */ "G_BUILD_VECTOR_TRUNC\0"	---	8811	/* 11181 */ "G_BUILD_VECTOR_TRUNC\0"	---
8812	/* 11202 */ "SYNC\0"	---	8812	/* 11202 */ "SYNC\0"	---
8813	/* 11207 */ "G_DYN_STACKALLOC\0"	---	8813	/* 11207 */ "G_DYN_STACKALLOC\0"	---
8814	/* 11224 */ "LDPC\0"	---	8814	/* 11224 */ "LDPC\0"	---
8815	/* 11229 */ "AUIPC\0"	---	8815	/* 11229 */ "AUIPC\0"	---
8816	/* 11235 */ "ALUIPC\0"	---	8816	/* 11235 */ "ALUIPC\0"	---
8817	/* 11242 */ "ADDIUPC\0"	---	8817	/* 11242 */ "ADDIUPC\0"	---
8818	/* 11250 */ "LWUPC\0"	---	8818	/* 11250 */ "LWUPC\0"	---
8819	/* 11256 */ "LWPC\0"	---	8819	/* 11256 */ "LWPC\0"	---
8820	/* 11261 */ "BEQC\0"	---	8820	/* 11261 */ "BEQC\0"	---
8821	/* 11266 */ "ADDSC\0"	---	8821	/* 11266 */ "ADDSC\0"	---
8822	/* 11272 */ "BLTC\0"	---	8822	/* 11272 */ "BLTC\0"	---
8823	/* 11277 */ "BGEUC\0"	---	8823	/* 11277 */ "BGEUC\0"	---
8824	/* 11283 */ "BLTUC\0"	---	8824	/* 11283 */ "BLTUC\0"	---
8825	/* 11289 */ "BNVC\0"	---	8825	/* 11289 */ "BNVC\0"	---
8826	/* 11294 */ "BOVC\0"	---	8826	/* 11294 */ "BOVC\0"	---
8827	/* 11299 */ "ADDWC\0"	---	8827	/* 11299 */ "ADDWC\0"	---
8828	/* 11305 */ "BGEZC\0"	---	8828	/* 11305 */ "BGEZC\0"	---
8829	/* 11311 */ "BLEZC\0"	---	8829	/* 11311 */ "BLEZC\0"	---
8830	/* 11317 */ "BNEZC\0"	---	8830	/* 11317 */ "BNEZC\0"	---
8831	/* 11323 */ "BEQZC\0"	---	8831	/* 11323 */ "BEQZC\0"	---
8832	/* 11329 */ "BGTZC\0"	---	8832	/* 11329 */ "BGTZC\0"	---
8833	/* 11335 */ "BLTZC\0"	---	8833	/* 11335 */ "BLTZC\0"	---
8834	/* 11341 */ "CRC32D\0"	---	8834	/* 11341 */ "CRC32D\0"	---
8835	/* 11348 */ "SAAD\0"	---	8835	/* 11348 */ "SAAD\0"	---
8836	/* 11353 */ "G_FMAD\0"	---	8836	/* 11353 */ "G_FMAD\0"	---
8837	/* 11360 */ "G_INDEXED_SEXTLOAD\0"	---	8837	/* 11360 */ "G_INDEXED_SEXTLOAD\0"	---
8838	/* 11379 */ "G_SEXTLOAD\0"	---	8838	/* 11379 */ "G_SEXTLOAD\0"	---
8839	/* 11390 */ "G_INDEXED_ZEXTLOAD\0"	---	8839	/* 11390 */ "G_INDEXED_ZEXTLOAD\0"	---
8840	/* 11409 */ "G_ZEXTLOAD\0"	---	8840	/* 11409 */ "G_ZEXTLOAD\0"	---
8841	/* 11420 */ "G_INDEXED_LOAD\0"	---	8841	/* 11420 */ "G_INDEXED_LOAD\0"	---
8842	/* 11435 */ "G_LOAD\0"	---	8842	/* 11435 */ "G_LOAD\0"	---
8843	/* 11442 */ "CRC32CD\0"	---	8843	/* 11442 */ "CRC32CD\0"	---
8844	/* 11450 */ "SCD\0"	---	8844	/* 11450 */ "SCD\0"	---
8845	/* 11454 */ "DADD\0"	---	8845	/* 11454 */ "DADD\0"	---
8846	/* 11459 */ "G_VECREDUCE_FADD\0"	---	8846	/* 11459 */ "G_VECREDUCE_FADD\0"	---
8847	/* 11476 */ "G_FADD\0"	---	8847	/* 11476 */ "G_FADD\0"	---
8848	/* 11483 */ "G_VECREDUCE_SEQ_FADD\0"	---	8848	/* 11483 */ "G_VECREDUCE_SEQ_FADD\0"	---
8849	/* 11504 */ "G_STRICT_FADD\0"	---	8849	/* 11504 */ "G_STRICT_FADD\0"	---
8850	/* 11518 */ "G_ATOMICRMW_FADD\0"	---	8850	/* 11518 */ "G_ATOMICRMW_FADD\0"	---
8851	/* 11535 */ "PseudoMADD\0"	---	8851	/* 11535 */ "PseudoMADD\0"	---
8852	/* 11546 */ "G_VECREDUCE_ADD\0"	---	8852	/* 11546 */ "G_VECREDUCE_ADD\0"	---
8853	/* 11562 */ "G_ADD\0"	---	8853	/* 11562 */ "G_ADD\0"	---
8854	/* 11568 */ "G_PTR_ADD\0"	---	8854	/* 11568 */ "G_PTR_ADD\0"	---
8855	/* 11578 */ "G_ATOMICRMW_ADD\0"	---	8855	/* 11578 */ "G_ATOMICRMW_ADD\0"	---
8856	/* 11594 */ "DSHD\0"	---	8856	/* 11594 */ "DSHD\0"	---
8857	/* 11599 */ "YIELD\0"	---	8857	/* 11599 */ "YIELD\0"	---
8858	/* 11605 */ "LLD\0"	---	8858	/* 11605 */ "LLD\0"	---
8859	/* 11609 */ "G_ATOMICRMW_NAND\0"	---	8859	/* 11609 */ "G_ATOMICRMW_NAND\0"	---
8860	/* 11626 */ "G_VECREDUCE_AND\0"	---	8860	/* 11626 */ "G_VECREDUCE_AND\0"	---
8861	/* 11642 */ "G_AND\0"	---	8861	/* 11642 */ "G_AND\0"	---
8862	/* 11648 */ "G_ATOMICRMW_AND\0"	---	8862	/* 11648 */ "G_ATOMICRMW_AND\0"	---
8863	/* 11664 */ "PREPEND\0"	---	8863	/* 11664 */ "PREPEND\0"	---
8864	/* 11672 */ "APPEND\0"	---	8864	/* 11672 */ "APPEND\0"	---
8865	/* 11679 */ "LIFETIME_END\0"	---	8865	/* 11679 */ "LIFETIME_END\0"	---
8866	/* 11692 */ "G_BRCOND\0"	---	8866	/* 11692 */ "G_BRCOND\0"	---
8867	/* 11701 */ "G_LLROUND\0"	---	8867	/* 11701 */ "G_LLROUND\0"	---
8868	/* 11711 */ "G_LROUND\0"	---	8868	/* 11711 */ "G_LROUND\0"	---
8869	/* 11720 */ "G_INTRINSIC_ROUND\0"	---	8869	/* 11720 */ "G_INTRINSIC_ROUND\0"	---
8870	/* 11738 */ "G_INTRINSIC_FPTRUNC_ROUND\0"	---	8870	/* 11738 */ "G_INTRINSIC_FPTRUNC_ROUND\0"	---
8871	/* 11764 */ "DMOD\0"	---	8871	/* 11764 */ "DMOD\0"	---
8872	/* 11769 */ "LOAD_STACK_GUARD\0"	---	8872	/* 11769 */ "LOAD_STACK_GUARD\0"	---
8873	/* 11786 */ "SD\0"	---	8873	/* 11786 */ "SD\0"	---
8874	/* 11789 */ "FLOG2_D\0"	---	8874	/* 11789 */ "FLOG2_D\0"	---
8875	/* 11797 */ "FEXP2_D\0"	---	8875	/* 11797 */ "FEXP2_D\0"	---
8876	/* 11805 */ "MINA_D\0"	---	8876	/* 11805 */ "MINA_D\0"	---
8877	/* 11812 */ "SRA_D\0"	---	8877	/* 11812 */ "SRA_D\0"	---
8878	/* 11818 */ "MAXA_D\0"	---	8878	/* 11818 */ "MAXA_D\0"	---
8879	/* 11825 */ "ADD_A_D\0"	---	8879	/* 11825 */ "ADD_A_D\0"	---
8880	/* 11833 */ "FMIN_A_D\0"	---	8880	/* 11833 */ "FMIN_A_D\0"	---
8881	/* 11842 */ "ADDS_A_D\0"	---	8881	/* 11842 */ "ADDS_A_D\0"	---
8882	/* 11851 */ "FMAX_A_D\0"	---	8882	/* 11851 */ "FMAX_A_D\0"	---
8883	/* 11860 */ "FSUB_D\0"	---	8883	/* 11860 */ "FSUB_D\0"	---
8884	/* 11867 */ "FMSUB_D\0"	---	8884	/* 11867 */ "FMSUB_D\0"	---
8885	/* 11875 */ "NLOC_D\0"	---	8885	/* 11875 */ "NLOC_D\0"	---
8886	/* 11882 */ "NLZC_D\0"	---	8886	/* 11882 */ "NLZC_D\0"	---
8887	/* 11889 */ "FADD_D\0"	---	8887	/* 11889 */ "FADD_D\0"	---
8888	/* 11896 */ "FMADD_D\0"	---	8888	/* 11896 */ "FMADD_D\0"	---
8889	/* 11904 */ "SLD_D\0"	---	8889	/* 11904 */ "SLD_D\0"	---
8890	/* 11910 */ "PCKOD_D\0"	---	8890	/* 11910 */ "PCKOD_D\0"	---
8891	/* 11918 */ "ILVOD_D\0"	---	8891	/* 11918 */ "ILVOD_D\0"	---
8892	/* 11926 */ "FCLE_D\0"	---	8892	/* 11926 */ "FCLE_D\0"	---
8893	/* 11933 */ "FSLE_D\0"	---	8893	/* 11933 */ "FSLE_D\0"	---
8894	/* 11940 */ "CMP_SLE_D\0"	---	8894	/* 11940 */ "CMP_SLE_D\0"	---
8895	/* 11950 */ "FCULE_D\0"	---	8895	/* 11950 */ "FCULE_D\0"	---
8896	/* 11958 */ "FSULE_D\0"	---	8896	/* 11958 */ "FSULE_D\0"	---
8897	/* 11966 */ "CMP_SULE_D\0"	---	8897	/* 11966 */ "CMP_SULE_D\0"	---
8898	/* 11977 */ "CMP_ULE_D\0"	---	8898	/* 11977 */ "CMP_ULE_D\0"	---
8899	/* 11987 */ "CMP_LE_D\0"	---	8899	/* 11987 */ "CMP_LE_D\0"	---
8900	/* 11996 */ "FCNE_D\0"	---	8900	/* 11996 */ "FCNE_D\0"	---
8901	/* 12003 */ "FSNE_D\0"	---	8901	/* 12003 */ "FSNE_D\0"	---
8902	/* 12010 */ "FCUNE_D\0"	---	8902	/* 12010 */ "FCUNE_D\0"	---
8903	/* 12018 */ "FSUNE_D\0"	---	8903	/* 12018 */ "FSUNE_D\0"	---
8904	/* 12026 */ "INSVE_D\0"	---	8904	/* 12026 */ "INSVE_D\0"	---
8905	/* 12034 */ "FCAF_D\0"	---	8905	/* 12034 */ "FCAF_D\0"	---
8906	/* 12041 */ "FSAF_D\0"	---	8906	/* 12041 */ "FSAF_D\0"	---
8907	/* 12048 */ "CMP_SAF_D\0"	---	8907	/* 12048 */ "CMP_SAF_D\0"	---
8908	/* 12058 */ "MSUBF_D\0"	---	8908	/* 12058 */ "MSUBF_D\0"	---
8909	/* 12066 */ "MADDF_D\0"	---	8909	/* 12066 */ "MADDF_D\0"	---
8910	/* 12074 */ "VSHF_D\0"	---	8910	/* 12074 */ "VSHF_D\0"	---
8911	/* 12081 */ "CMP_F_D\0"	---	8911	/* 12081 */ "CMP_F_D\0"	---
8912	/* 12089 */ "BNEG_D\0"	---	8912	/* 12089 */ "BNEG_D\0"	---
8913	/* 12096 */ "SRAI_D\0"	---	8913	/* 12096 */ "SRAI_D\0"	---
8914	/* 12103 */ "SLDI_D\0"	---	8914	/* 12103 */ "SLDI_D\0"	---
8915	/* 12110 */ "BNEGI_D\0"	---	8915	/* 12110 */ "BNEGI_D\0"	---
8916	/* 12118 */ "SLLI_D\0"	---	8916	/* 12118 */ "SLLI_D\0"	---
8917	/* 12125 */ "SRLI_D\0"	---	8917	/* 12125 */ "SRLI_D\0"	---
8918	/* 12132 */ "BINSLI_D\0"	---	8918	/* 12132 */ "BINSLI_D\0"	---
8919	/* 12141 */ "CEQI_D\0"	---	8919	/* 12141 */ "CEQI_D\0"	---
8920	/* 12148 */ "SRARI_D\0"	---	8920	/* 12148 */ "SRARI_D\0"	---
8921	/* 12156 */ "BCLRI_D\0"	---	8921	/* 12156 */ "BCLRI_D\0"	---
8922	/* 12164 */ "SRLRI_D\0"	---	8922	/* 12164 */ "SRLRI_D\0"	---
8923	/* 12172 */ "BINSRI_D\0"	---	8923	/* 12172 */ "BINSRI_D\0"	---
8924	/* 12181 */ "SPLATI_D\0"	---	8924	/* 12181 */ "SPLATI_D\0"	---
8925	/* 12190 */ "BSETI_D\0"	---	8925	/* 12190 */ "BSETI_D\0"	---
8926	/* 12198 */ "SUBVI_D\0"	---	8926	/* 12198 */ "SUBVI_D\0"	---
8927	/* 12206 */ "ADDVI_D\0"	---	8927	/* 12206 */ "ADDVI_D\0"	---
8928	/* 12214 */ "SEL_D\0"	---	8928	/* 12214 */ "SEL_D\0"	---
8929	/* 12220 */ "FILL_D\0"	---	8929	/* 12220 */ "FILL_D\0"	---
8930	/* 12227 */ "SLL_D\0"	---	8930	/* 12227 */ "SLL_D\0"	---
8931	/* 12233 */ "FEXUPL_D\0"	---	8931	/* 12233 */ "FEXUPL_D\0"	---
8932	/* 12242 */ "FFQL_D\0"	---	8932	/* 12242 */ "FFQL_D\0"	---
8933	/* 12249 */ "SRL_D\0"	---	8933	/* 12249 */ "SRL_D\0"	---
8934	/* 12255 */ "BINSL_D\0"	---	8934	/* 12255 */ "BINSL_D\0"	---
8935	/* 12263 */ "FMUL_D\0"	---	8935	/* 12263 */ "FMUL_D\0"	---
8936	/* 12270 */ "ILVL_D\0"	---	8936	/* 12270 */ "ILVL_D\0"	---
8937	/* 12277 */ "FMIN_D\0"	---	8937	/* 12277 */ "FMIN_D\0"	---
8938	/* 12284 */ "FCUN_D\0"	---	8938	/* 12284 */ "FCUN_D\0"	---
8939	/* 12291 */ "FSUN_D\0"	---	8939	/* 12291 */ "FSUN_D\0"	---
8940	/* 12298 */ "CMP_SUN_D\0"	---	8940	/* 12298 */ "CMP_SUN_D\0"	---
8941	/* 12308 */ "CMP_UN_D\0"	---	8941	/* 12308 */ "CMP_UN_D\0"	---
8942	/* 12317 */ "FRCP_D\0"	---	8942	/* 12317 */ "FRCP_D\0"	---
8943	/* 12324 */ "FCEQ_D\0"	---	8943	/* 12324 */ "FCEQ_D\0"	---
8944	/* 12331 */ "FSEQ_D\0"	---	8944	/* 12331 */ "FSEQ_D\0"	---
8945	/* 12338 */ "CMP_SEQ_D\0"	---	8945	/* 12338 */ "CMP_SEQ_D\0"	---
8946	/* 12348 */ "FCUEQ_D\0"	---	8946	/* 12348 */ "FCUEQ_D\0"	---
8947	/* 12356 */ "FSUEQ_D\0"	---	8947	/* 12356 */ "FSUEQ_D\0"	---
8948	/* 12364 */ "CMP_SUEQ_D\0"	---	8948	/* 12364 */ "CMP_SUEQ_D\0"	---
8949	/* 12375 */ "CMP_UEQ_D\0"	---	8949	/* 12375 */ "CMP_UEQ_D\0"	---
8950	/* 12385 */ "CMP_EQ_D\0"	---	8950	/* 12385 */ "CMP_EQ_D\0"	---
8951	/* 12394 */ "SRAR_D\0"	---	8951	/* 12394 */ "SRAR_D\0"	---
8952	/* 12401 */ "LDR_D\0"	---	8952	/* 12401 */ "LDR_D\0"	---
8953	/* 12407 */ "BCLR_D\0"	---	8953	/* 12407 */ "BCLR_D\0"	---
8954	/* 12414 */ "SRLR_D\0"	---	8954	/* 12414 */ "SRLR_D\0"	---
8955	/* 12421 */ "FCOR_D\0"	---	8955	/* 12421 */ "FCOR_D\0"	---
8956	/* 12428 */ "FSOR_D\0"	---	8956	/* 12428 */ "FSOR_D\0"	---
8957	/* 12435 */ "FEXUPR_D\0"	---	8957	/* 12435 */ "FEXUPR_D\0"	---
8958	/* 12444 */ "FFQR_D\0"	---	8958	/* 12444 */ "FFQR_D\0"	---
8959	/* 12451 */ "BINSR_D\0"	---	8959	/* 12451 */ "BINSR_D\0"	---
8960	/* 12459 */ "STR_D\0"	---	8960	/* 12459 */ "STR_D\0"	---
8961	/* 12465 */ "ILVR_D\0"	---	8961	/* 12465 */ "ILVR_D\0"	---
8962	/* 12472 */ "FABS_D\0"	---	8962	/* 12472 */ "FABS_D\0"	---
8963	/* 12479 */ "FCLASS_D\0"	---	8963	/* 12479 */ "FCLASS_D\0"	---
8964	/* 12488 */ "ASUB_S_D\0"	---	8964	/* 12488 */ "ASUB_S_D\0"	---
8965	/* 12497 */ "HSUB_S_D\0"	---	8965	/* 12497 */ "HSUB_S_D\0"	---
8966	/* 12506 */ "DPSUB_S_D\0"	---	8966	/* 12506 */ "DPSUB_S_D\0"	---
8967	/* 12516 */ "FTRUNC_S_D\0"	---	8967	/* 12516 */ "FTRUNC_S_D\0"	---
8968	/* 12527 */ "HADD_S_D\0"	---	8968	/* 12527 */ "HADD_S_D\0"	---
8969	/* 12536 */ "DPADD_S_D\0"	---	8969	/* 12536 */ "DPADD_S_D\0"	---
8970	/* 12546 */ "MOD_S_D\0"	---	8970	/* 12546 */ "MOD_S_D\0"	---
8971	/* 12554 */ "CLE_S_D\0"	---	8971	/* 12554 */ "CLE_S_D\0"	---
8972	/* 12562 */ "AVE_S_D\0"	---	8972	/* 12562 */ "AVE_S_D\0"	---
8973	/* 12570 */ "CLEI_S_D\0"	---	8973	/* 12570 */ "CLEI_S_D\0"	---
8974	/* 12579 */ "MINI_S_D\0"	---	8974	/* 12579 */ "MINI_S_D\0"	---
8975	/* 12588 */ "CLTI_S_D\0"	---	8975	/* 12588 */ "CLTI_S_D\0"	---
8976	/* 12597 */ "MAXI_S_D\0"	---	8976	/* 12597 */ "MAXI_S_D\0"	---
8977	/* 12606 */ "MIN_S_D\0"	---	8977	/* 12606 */ "MIN_S_D\0"	---
8978	/* 12614 */ "DOTP_S_D\0"	---	8978	/* 12614 */ "DOTP_S_D\0"	---
8979	/* 12623 */ "AVER_S_D\0"	---	8979	/* 12623 */ "AVER_S_D\0"	---
8980	/* 12632 */ "SUBS_S_D\0"	---	8980	/* 12632 */ "SUBS_S_D\0"	---
8981	/* 12641 */ "ADDS_S_D\0"	---	8981	/* 12641 */ "ADDS_S_D\0"	---
8982	/* 12650 */ "SAT_S_D\0"	---	8982	/* 12650 */ "SAT_S_D\0"	---
8983	/* 12658 */ "CLT_S_D\0"	---	8983	/* 12658 */ "CLT_S_D\0"	---
8984	/* 12666 */ "FFINT_S_D\0"	---	8984	/* 12666 */ "FFINT_S_D\0"	---
8985	/* 12676 */ "FTINT_S_D\0"	---	8985	/* 12676 */ "FTINT_S_D\0"	---
8986	/* 12686 */ "SUBSUU_S_D\0"	---	8986	/* 12686 */ "SUBSUU_S_D\0"	---
8987	/* 12697 */ "DIV_S_D\0"	---	8987	/* 12697 */ "DIV_S_D\0"	---
8988	/* 12705 */ "MAX_S_D\0"	---	8988	/* 12705 */ "MAX_S_D\0"	---
8989	/* 12713 */ "COPY_S_D\0"	---	8989	/* 12713 */ "COPY_S_D\0"	---
8990	/* 12722 */ "SPLAT_D\0"	---	8990	/* 12722 */ "SPLAT_D\0"	---
8991	/* 12730 */ "BSET_D\0"	---	8991	/* 12730 */ "BSET_D\0"	---
8992	/* 12737 */ "FCLT_D\0"	---	8992	/* 12737 */ "FCLT_D\0"	---
8993	/* 12744 */ "FSLT_D\0"	---	8993	/* 12744 */ "FSLT_D\0"	---
8994	/* 12751 */ "CMP_SLT_D\0"	---	8994	/* 12751 */ "CMP_SLT_D\0"	---
8995	/* 12761 */ "FCULT_D\0"	---	8995	/* 12761 */ "FCULT_D\0"	---
8996	/* 12769 */ "FSULT_D\0"	---	8996	/* 12769 */ "FSULT_D\0"	---
8997	/* 12777 */ "CMP_SULT_D\0"	---	8997	/* 12777 */ "CMP_SULT_D\0"	---
8998	/* 12788 */ "CMP_ULT_D\0"	---	8998	/* 12788 */ "CMP_ULT_D\0"	---
8999	/* 12798 */ "CMP_LT_D\0"	---	8999	/* 12798 */ "CMP_LT_D\0"	---
9000	/* 12807 */ "PCNT_D\0"	---	9000	/* 12807 */ "PCNT_D\0"	---
9001	/* 12814 */ "FRINT_D\0"	---	9001	/* 12814 */ "FRINT_D\0"	---
9002	/* 12822 */ "INSERT_D\0"	---	9002	/* 12822 */ "INSERT_D\0"	---
9003	/* 12831 */ "FSQRT_D\0"	---	9003	/* 12831 */ "FSQRT_D\0"	---
9004	/* 12839 */ "FRSQRT_D\0"	---	9004	/* 12839 */ "FRSQRT_D\0"	---
9005	/* 12848 */ "ST_D\0"	---	9005	/* 12848 */ "ST_D\0"	---
9006	/* 12853 */ "ASUB_U_D\0"	---	9006	/* 12853 */ "ASUB_U_D\0"	---
9007	/* 12862 */ "HSUB_U_D\0"	---	9007	/* 12862 */ "HSUB_U_D\0"	---
9008	/* 12871 */ "DPSUB_U_D\0"	---	9008	/* 12871 */ "DPSUB_U_D\0"	---
9009	/* 12881 */ "FTRUNC_U_D\0"	---	9009	/* 12881 */ "FTRUNC_U_D\0"	---
9010	/* 12892 */ "HADD_U_D\0"	---	9010	/* 12892 */ "HADD_U_D\0"	---
9011	/* 12901 */ "DPADD_U_D\0"	---	9011	/* 12901 */ "DPADD_U_D\0"	---
9012	/* 12911 */ "MOD_U_D\0"	---	9012	/* 12911 */ "MOD_U_D\0"	---
9013	/* 12919 */ "CLE_U_D\0"	---	9013	/* 12919 */ "CLE_U_D\0"	---
9014	/* 12927 */ "AVE_U_D\0"	---	9014	/* 12927 */ "AVE_U_D\0"	---
9015	/* 12935 */ "CLEI_U_D\0"	---	9015	/* 12935 */ "CLEI_U_D\0"	---
9016	/* 12944 */ "MINI_U_D\0"	---	9016	/* 12944 */ "MINI_U_D\0"	---
9017	/* 12953 */ "CLTI_U_D\0"	---	9017	/* 12953 */ "CLTI_U_D\0"	---
9018	/* 12962 */ "MAXI_U_D\0"	---	9018	/* 12962 */ "MAXI_U_D\0"	---
9019	/* 12971 */ "MIN_U_D\0"	---	9019	/* 12971 */ "MIN_U_D\0"	---
9020	/* 12979 */ "DOTP_U_D\0"	---	9020	/* 12979 */ "DOTP_U_D\0"	---
9021	/* 12988 */ "AVER_U_D\0"	---	9021	/* 12988 */ "AVER_U_D\0"	---
9022	/* 12997 */ "SUBS_U_D\0"	---	9022	/* 12997 */ "SUBS_U_D\0"	---
9023	/* 13006 */ "ADDS_U_D\0"	---	9023	/* 13006 */ "ADDS_U_D\0"	---
9024	/* 13015 */ "SUBSUS_U_D\0"	---	9024	/* 13015 */ "SUBSUS_U_D\0"	---
9025	/* 13026 */ "SAT_U_D\0"	---	9025	/* 13026 */ "SAT_U_D\0"	---
9026	/* 13034 */ "CLT_U_D\0"	---	9026	/* 13034 */ "CLT_U_D\0"	---
9027	/* 13042 */ "FFINT_U_D\0"	---	9027	/* 13042 */ "FFINT_U_D\0"	---
9028	/* 13052 */ "FTINT_U_D\0"	---	9028	/* 13052 */ "FTINT_U_D\0"	---
9029	/* 13062 */ "DIV_U_D\0"	---	9029	/* 13062 */ "DIV_U_D\0"	---
9030	/* 13070 */ "MAX_U_D\0"	---	9030	/* 13070 */ "MAX_U_D\0"	---
9031	/* 13078 */ "MSUBV_D\0"	---	9031	/* 13078 */ "MSUBV_D\0"	---
9032	/* 13086 */ "MADDV_D\0"	---	9032	/* 13086 */ "MADDV_D\0"	---
9033	/* 13094 */ "PCKEV_D\0"	---	9033	/* 13094 */ "PCKEV_D\0"	---
9034	/* 13102 */ "ILVEV_D\0"	---	9034	/* 13102 */ "ILVEV_D\0"	---
9035	/* 13110 */ "FDIV_D\0"	---	9035	/* 13110 */ "FDIV_D\0"	---
9036	/* 13117 */ "MULV_D\0"	---	9036	/* 13117 */ "MULV_D\0"	---
9037	/* 13124 */ "PseudoTRUNC_W_D\0"	---	9037	/* 13124 */ "PseudoTRUNC_W_D\0"	---
9038	/* 13140 */ "FMAX_D\0"	---	9038	/* 13140 */ "FMAX_D\0"	---
9039	/* 13147 */ "BZ_D\0"	---	9039	/* 13147 */ "BZ_D\0"	---
9040	/* 13152 */ "SELNEZ_D\0"	---	9040	/* 13152 */ "SELNEZ_D\0"	---
9041	/* 13161 */ "BNZ_D\0"	---	9041	/* 13161 */ "BNZ_D\0"	---
9042	/* 13167 */ "SELEQZ_D\0"	---	9042	/* 13167 */ "SELEQZ_D\0"	---
9043	/* 13176 */ "LBE\0"	---	9043	/* 13176 */ "LBE\0"	---
9044	/* 13180 */ "PSEUDO_PROBE\0"	---	9044	/* 13180 */ "PSEUDO_PROBE\0"	---
9045	/* 13193 */ "SBE\0"	---	9045	/* 13193 */ "SBE\0"	---
9046	/* 13197 */ "G_SSUBE\0"	---	9046	/* 13197 */ "G_SSUBE\0"	---
9047	/* 13205 */ "G_USUBE\0"	---	9047	/* 13205 */ "G_USUBE\0"	---
9048	/* 13213 */ "G_FENCE\0"	---	9048	/* 13213 */ "G_FENCE\0"	---
9049	/* 13221 */ "ARITH_FENCE\0"	---	9049	/* 13221 */ "ARITH_FENCE\0"	---
9050	/* 13233 */ "REG_SEQUENCE\0"	---	9050	/* 13233 */ "REG_SEQUENCE\0"	---
9051	/* 13246 */ "SCE\0"	---	9051	/* 13246 */ "SCE\0"	---
9052	/* 13250 */ "G_SADDE\0"	---	9052	/* 13250 */ "G_SADDE\0"	---
9053	/* 13258 */ "G_UADDE\0"	---	9053	/* 13258 */ "G_UADDE\0"	---
9054	/* 13266 */ "G_FMINNUM_IEEE\0"	---	9054	/* 13266 */ "G_FMINNUM_IEEE\0"	---
9055	/* 13281 */ "G_FMAXNUM_IEEE\0"	---	9055	/* 13281 */ "G_FMAXNUM_IEEE\0"	---
9056	/* 13296 */ "CACHEE\0"	---	9056	/* 13296 */ "CACHEE\0"	---
9057	/* 13303 */ "PREFE\0"	---	9057	/* 13303 */ "PREFE\0"	---
9058	/* 13309 */ "BGE\0"	---	9058	/* 13309 */ "BGE\0"	---
9059	/* 13313 */ "SGE\0"	---	9059	/* 13313 */ "SGE\0"	---
9060	/* 13317 */ "TGE\0"	---	9060	/* 13317 */ "TGE\0"	---
9061	/* 13321 */ "CACHE\0"	---	9061	/* 13321 */ "CACHE\0"	---
9062	/* 13327 */ "LHE\0"	---	9062	/* 13327 */ "LHE\0"	---
9063	/* 13331 */ "SHE\0"	---	9063	/* 13331 */ "SHE\0"	---
9064	/* 13335 */ "SIGRIE\0"	---	9064	/* 13335 */ "SIGRIE\0"	---
9065	/* 13342 */ "G_JUMP_TABLE\0"	---	9065	/* 13342 */ "G_JUMP_TABLE\0"	---
9066	/* 13355 */ "BUNDLE\0"	---	9066	/* 13355 */ "BUNDLE\0"	---
9067	/* 13362 */ "LLE\0"	---	9067	/* 13362 */ "LLE\0"	---
9068	/* 13366 */ "SLE\0"	---	9068	/* 13366 */ "SLE\0"	---
9069	/* 13370 */ "LWLE\0"	---	9069	/* 13370 */ "LWLE\0"	---
9070	/* 13375 */ "SWLE\0"	---	9070	/* 13375 */ "SWLE\0"	---
9071	/* 13380 */ "BNE\0"	---	9071	/* 13380 */ "BNE\0"	---
9072	/* 13384 */ "G_MEMCPY_INLINE\0"	---	9072	/* 13384 */ "G_MEMCPY_INLINE\0"	---
9073	/* 13400 */ "SNE\0"	---	9073	/* 13400 */ "SNE\0"	---
9074	/* 13404 */ "TNE\0"	---	9074	/* 13404 */ "TNE\0"	---
9075	/* 13408 */ "LOCAL_ESCAPE\0"	---	9075	/* 13408 */ "LOCAL_ESCAPE\0"	---
9076	/* 13421 */ "DVPE\0"	---	9076	/* 13421 */ "DVPE\0"	---
9077	/* 13426 */ "EVPE\0"	---	9077	/* 13426 */ "EVPE\0"	---
9078	/* 13431 */ "G_INDEXED_STORE\0"	---	9078	/* 13431 */ "G_INDEXED_STORE\0"	---
9079	/* 13447 */ "G_STORE\0"	---	9079	/* 13447 */ "G_STORE\0"	---
9080	/* 13455 */ "LWRE\0"	---	9080	/* 13455 */ "LWRE\0"	---
9081	/* 13460 */ "SWRE\0"	---	9081	/* 13460 */ "SWRE\0"	---
9082	/* 13465 */ "G_BITREVERSE\0"	---	9082	/* 13465 */ "G_BITREVERSE\0"	---
9083	/* 13478 */ "PAUSE\0"	---	9083	/* 13478 */ "PAUSE\0"	---
9084	/* 13484 */ "DBG_VALUE\0"	---	9084	/* 13484 */ "DBG_VALUE\0"	---
9085	/* 13494 */ "G_GLOBAL_VALUE\0"	---	9085	/* 13494 */ "G_GLOBAL_VALUE\0"	---
9086	/* 13509 */ "G_MEMMOVE\0"	---	9086	/* 13509 */ "G_MEMMOVE\0"	---
9087	/* 13519 */ "LWE\0"	---	9087	/* 13519 */ "LWE\0"	---
9088	/* 13523 */ "SWE\0"	---	9088	/* 13523 */ "SWE\0"	---
9089	/* 13527 */ "G_FREEZE\0"	---	9089	/* 13527 */ "G_FREEZE\0"	---
9090	/* 13536 */ "G_FCANONICALIZE\0"	---	9090	/* 13536 */ "G_FCANONICALIZE\0"	---
9091	/* 13552 */ "LBuE\0"	---	9091	/* 13552 */ "LBuE\0"	---
9092	/* 13557 */ "LHuE\0"	---	9092	/* 13557 */ "LHuE\0"	---
9093	/* 13562 */ "BC1F\0"	---	9093	/* 13562 */ "BC1F\0"	---
9094	/* 13567 */ "G_CTLZ_ZERO_UNDEF\0"	---	9094	/* 13567 */ "G_CTLZ_ZERO_UNDEF\0"	---
9095	/* 13585 */ "G_CTTZ_ZERO_UNDEF\0"	---	9095	/* 13585 */ "G_CTTZ_ZERO_UNDEF\0"	---
9096	/* 13603 */ "G_IMPLICIT_DEF\0"	---	9096	/* 13603 */ "G_IMPLICIT_DEF\0"	---
9097	/* 13618 */ "PREF\0"	---	9097	/* 13618 */ "PREF\0"	---
9098	/* 13623 */ "DBG_INSTR_REF\0"	---	9098	/* 13623 */ "DBG_INSTR_REF\0"	---
9099	/* 13637 */ "TLBINVF\0"	---	9099	/* 13637 */ "TLBINVF\0"	---
9100	/* 13645 */ "TLBGINVF\0"	---	9100	/* 13645 */ "TLBGINVF\0"	---
9101	/* 13654 */ "G_FNEG\0"	---	9101	/* 13654 */ "G_FNEG\0"	---
9102	/* 13661 */ "TAILCALLHB64R6REG\0"	---	9102	/* 13661 */ "TAILCALLHB64R6REG\0"	---
9103	/* 13679 */ "TAILCALL64R6REG\0"	---	9103	/* 13679 */ "TAILCALL64R6REG\0"	---
9104	/* 13695 */ "TAILCALLHBR6REG\0"	---	9104	/* 13695 */ "TAILCALLHBR6REG\0"	---
9105	/* 13711 */ "TAILCALLR6REG\0"	---	9105	/* 13711 */ "TAILCALLR6REG\0"	---
9106	/* 13725 */ "EXTRACT_SUBREG\0"	---	9106	/* 13725 */ "EXTRACT_SUBREG\0"	---
9107	/* 13740 */ "INSERT_SUBREG\0"	---	9107	/* 13740 */ "INSERT_SUBREG\0"	---
9108	/* 13754 */ "TAILCALLREG\0"	---	9108	/* 13754 */ "TAILCALLREG\0"	---
9109	/* 13766 */ "G_SEXT_INREG\0"	---	9109	/* 13766 */ "G_SEXT_INREG\0"	---
9110	/* 13779 */ "SUBREG_TO_REG\0"	---	9110	/* 13779 */ "SUBREG_TO_REG\0"	---
9111	/* 13793 */ "G_ATOMIC_CMPXCHG\0"	---	9111	/* 13793 */ "G_ATOMIC_CMPXCHG\0"	---
9112	/* 13810 */ "G_ATOMICRMW_XCHG\0"	---	9112	/* 13810 */ "G_ATOMICRMW_XCHG\0"	---
9113	/* 13827 */ "G_FLOG\0"	---	9113	/* 13827 */ "G_FLOG\0"	---
9114	/* 13834 */ "G_VAARG\0"	---	9114	/* 13834 */ "G_VAARG\0"	---
9115	/* 13842 */ "PREALLOCATED_ARG\0"	---	9115	/* 13842 */ "PREALLOCATED_ARG\0"	---
9116	/* 13859 */ "CRC32H\0"	---	9116	/* 13859 */ "CRC32H\0"	---
9117	/* 13866 */ "DSBH\0"	---	9117	/* 13866 */ "DSBH\0"	---
9118	/* 13871 */ "WSBH\0"	---	9118	/* 13871 */ "WSBH\0"	---
9119	/* 13876 */ "CRC32CH\0"	---	9119	/* 13876 */ "CRC32CH\0"	---
9120	/* 13884 */ "SEH\0"	---	9120	/* 13884 */ "SEH\0"	---
9121	/* 13888 */ "G_SMULH\0"	---	9121	/* 13888 */ "G_SMULH\0"	---
9122	/* 13896 */ "G_UMULH\0"	---	9122	/* 13896 */ "G_UMULH\0"	---
9123	/* 13904 */ "SHRA_PH\0"	---	9123	/* 13904 */ "SHRA_PH\0"	---
9124	/* 13912 */ "PRECRQ_QB_PH\0"	---	9124	/* 13912 */ "PRECRQ_QB_PH\0"	---
9125	/* 13925 */ "PRECR_QB_PH\0"	---	9125	/* 13925 */ "PRECR_QB_PH\0"	---
9126	/* 13937 */ "PRECRQU_S_QB_PH\0"	---	9126	/* 13937 */ "PRECRQU_S_QB_PH\0"	---
9127	/* 13953 */ "PseudoCMP_LE_PH\0"	---	9127	/* 13953 */ "PseudoCMP_LE_PH\0"	---
9128	/* 13969 */ "SUBQH_PH\0"	---	9128	/* 13969 */ "SUBQH_PH\0"	---
9129	/* 13978 */ "ADDQH_PH\0"	---	9129	/* 13978 */ "ADDQH_PH\0"	---
9130	/* 13987 */ "PseudoPICK_PH\0"	---	9130	/* 13987 */ "PseudoPICK_PH\0"	---
9131	/* 14001 */ "SHLL_PH\0"	---	9131	/* 14001 */ "SHLL_PH\0"	---
9132	/* 14009 */ "REPL_PH\0"	---	9132	/* 14009 */ "REPL_PH\0"	---
9133	/* 14017 */ "SHRL_PH\0"	---	9133	/* 14017 */ "SHRL_PH\0"	---
9134	/* 14025 */ "PACKRL_PH\0"	---	9134	/* 14025 */ "PACKRL_PH\0"	---
9135	/* 14035 */ "MUL_PH\0"	---	9135	/* 14035 */ "MUL_PH\0"	---
9136	/* 14042 */ "SUBQ_PH\0"	---	9136	/* 14042 */ "SUBQ_PH\0"	---
9137	/* 14050 */ "ADDQ_PH\0"	---	9137	/* 14050 */ "ADDQ_PH\0"	---
9138	/* 14058 */ "PseudoCMP_EQ_PH\0"	---	9138	/* 14058 */ "PseudoCMP_EQ_PH\0"	---
9139	/* 14074 */ "SHRA_R_PH\0"	---	9139	/* 14074 */ "SHRA_R_PH\0"	---
9140	/* 14084 */ "SUBQH_R_PH\0"	---	9140	/* 14084 */ "SUBQH_R_PH\0"	---
9141	/* 14095 */ "ADDQH_R_PH\0"	---	9141	/* 14095 */ "ADDQH_R_PH\0"	---
9142	/* 14106 */ "SHRAV_R_PH\0"	---	9142	/* 14106 */ "SHRAV_R_PH\0"	---
9143	/* 14117 */ "MULQ_RS_PH\0"	---	9143	/* 14117 */ "MULQ_RS_PH\0"	---
9144	/* 14128 */ "SHLL_S_PH\0"	---	9144	/* 14128 */ "SHLL_S_PH\0"	---
9145	/* 14138 */ "MUL_S_PH\0"	---	9145	/* 14138 */ "MUL_S_PH\0"	---
9146	/* 14147 */ "SUBQ_S_PH\0"	---	9146	/* 14147 */ "SUBQ_S_PH\0"	---
9147	/* 14157 */ "ADDQ_S_PH\0"	---	9147	/* 14157 */ "ADDQ_S_PH\0"	---
9148	/* 14167 */ "MULQ_S_PH\0"	---	9148	/* 14167 */ "MULQ_S_PH\0"	---
9149	/* 14177 */ "ABSQ_S_PH\0"	---	9149	/* 14177 */ "ABSQ_S_PH\0"	---
9150	/* 14187 */ "SUBU_S_PH\0"	---	9150	/* 14187 */ "SUBU_S_PH\0"	---
9151	/* 14197 */ "ADDU_S_PH\0"	---	9151	/* 14197 */ "ADDU_S_PH\0"	---
9152	/* 14207 */ "SHLLV_S_PH\0"	---	9152	/* 14207 */ "SHLLV_S_PH\0"	---
9153	/* 14218 */ "PseudoCMP_LT_PH\0"	---	9153	/* 14218 */ "PseudoCMP_LT_PH\0"	---
9154	/* 14234 */ "SUBU_PH\0"	---	9154	/* 14234 */ "SUBU_PH\0"	---
9155	/* 14242 */ "ADDU_PH\0"	---	9155	/* 14242 */ "ADDU_PH\0"	---
9156	/* 14250 */ "SHRAV_PH\0"	---	9156	/* 14250 */ "SHRAV_PH\0"	---
9157	/* 14259 */ "SHLLV_PH\0"	---	9157	/* 14259 */ "SHLLV_PH\0"	---
9158	/* 14268 */ "REPLV_PH\0"	---	9158	/* 14268 */ "REPLV_PH\0"	---
9159	/* 14277 */ "SHRLV_PH\0"	---	9159	/* 14277 */ "SHRLV_PH\0"	---
9160	/* 14286 */ "DPA_W_PH\0"	---	9160	/* 14286 */ "DPA_W_PH\0"	---
9161	/* 14295 */ "MULSA_W_PH\0"	---	9161	/* 14295 */ "MULSA_W_PH\0"	---
9162	/* 14306 */ "DPAQX_SA_W_PH\0"	---	9162	/* 14306 */ "DPAQX_SA_W_PH\0"	---
9163	/* 14320 */ "DPSQX_SA_W_PH\0"	---	9163	/* 14320 */ "DPSQX_SA_W_PH\0"	---
9164	/* 14334 */ "DPS_W_PH\0"	---	9164	/* 14334 */ "DPS_W_PH\0"	---
9165	/* 14343 */ "DPAQ_S_W_PH\0"	---	9165	/* 14343 */ "DPAQ_S_W_PH\0"	---
9166	/* 14355 */ "MULSAQ_S_W_PH\0"	---	9166	/* 14355 */ "MULSAQ_S_W_PH\0"	---
9167	/* 14369 */ "DPSQ_S_W_PH\0"	---	9167	/* 14369 */ "DPSQ_S_W_PH\0"	---
9168	/* 14381 */ "DPAQX_S_W_PH\0"	---	9168	/* 14381 */ "DPAQX_S_W_PH\0"	---
9169	/* 14394 */ "DPSQX_S_W_PH\0"	---	9169	/* 14394 */ "DPSQX_S_W_PH\0"	---
9170	/* 14407 */ "DPAX_W_PH\0"	---	9170	/* 14407 */ "DPAX_W_PH\0"	---
9171	/* 14417 */ "DPSX_W_PH\0"	---	9171	/* 14417 */ "DPSX_W_PH\0"	---
9172	/* 14427 */ "SH\0"	---	9172	/* 14427 */ "SH\0"	---
9173	/* 14430 */ "DMUH\0"	---	9173	/* 14430 */ "DMUH\0"	---
9174	/* 14435 */ "SRA_H\0"	---	9174	/* 14435 */ "SRA_H\0"	---
9175	/* 14441 */ "ADD_A_H\0"	---	9175	/* 14441 */ "ADD_A_H\0"	---
9176	/* 14449 */ "MIN_A_H\0"	---	9176	/* 14449 */ "MIN_A_H\0"	---
9177	/* 14457 */ "ADDS_A_H\0"	---	9177	/* 14457 */ "ADDS_A_H\0"	---
9178	/* 14466 */ "MAX_A_H\0"	---	9178	/* 14466 */ "MAX_A_H\0"	---
9179	/* 14474 */ "NLOC_H\0"	---	9179	/* 14474 */ "NLOC_H\0"	---
9180	/* 14481 */ "NLZC_H\0"	---	9180	/* 14481 */ "NLZC_H\0"	---
9181	/* 14488 */ "SLD_H\0"	---	9181	/* 14488 */ "SLD_H\0"	---
9182	/* 14494 */ "PCKOD_H\0"	---	9182	/* 14494 */ "PCKOD_H\0"	---
9183	/* 14502 */ "ILVOD_H\0"	---	9183	/* 14502 */ "ILVOD_H\0"	---
9184	/* 14510 */ "INSVE_H\0"	---	9184	/* 14510 */ "INSVE_H\0"	---
9185	/* 14518 */ "VSHF_H\0"	---	9185	/* 14518 */ "VSHF_H\0"	---
9186	/* 14525 */ "BNEG_H\0"	---	9186	/* 14525 */ "BNEG_H\0"	---
9187	/* 14532 */ "SRAI_H\0"	---	9187	/* 14532 */ "SRAI_H\0"	---
9188	/* 14539 */ "SLDI_H\0"	---	9188	/* 14539 */ "SLDI_H\0"	---
9189	/* 14546 */ "BNEGI_H\0"	---	9189	/* 14546 */ "BNEGI_H\0"	---
9190	/* 14554 */ "SLLI_H\0"	---	9190	/* 14554 */ "SLLI_H\0"	---
9191	/* 14561 */ "SRLI_H\0"	---	9191	/* 14561 */ "SRLI_H\0"	---
9192	/* 14568 */ "BINSLI_H\0"	---	9192	/* 14568 */ "BINSLI_H\0"	---
9193	/* 14577 */ "CEQI_H\0"	---	9193	/* 14577 */ "CEQI_H\0"	---
9194	/* 14584 */ "SRARI_H\0"	---	9194	/* 14584 */ "SRARI_H\0"	---
9195	/* 14592 */ "BCLRI_H\0"	---	9195	/* 14592 */ "BCLRI_H\0"	---
9196	/* 14600 */ "SRLRI_H\0"	---	9196	/* 14600 */ "SRLRI_H\0"	---
9197	/* 14608 */ "BINSRI_H\0"	---	9197	/* 14608 */ "BINSRI_H\0"	---
9198	/* 14617 */ "SPLATI_H\0"	---	9198	/* 14617 */ "SPLATI_H\0"	---
9199	/* 14626 */ "BSETI_H\0"	---	9199	/* 14626 */ "BSETI_H\0"	---
9200	/* 14634 */ "SUBVI_H\0"	---	9200	/* 14634 */ "SUBVI_H\0"	---
9201	/* 14642 */ "ADDVI_H\0"	---	9201	/* 14642 */ "ADDVI_H\0"	---
9202	/* 14650 */ "FILL_H\0"	---	9202	/* 14650 */ "FILL_H\0"	---
9203	/* 14657 */ "SLL_H\0"	---	9203	/* 14657 */ "SLL_H\0"	---
9204	/* 14663 */ "SRL_H\0"	---	9204	/* 14663 */ "SRL_H\0"	---
9205	/* 14669 */ "BINSL_H\0"	---	9205	/* 14669 */ "BINSL_H\0"	---
9206	/* 14677 */ "ILVL_H\0"	---	9206	/* 14677 */ "ILVL_H\0"	---
9207	/* 14684 */ "FEXDO_H\0"	---	9207	/* 14684 */ "FEXDO_H\0"	---
9208	/* 14692 */ "CEQ_H\0"	---	9208	/* 14692 */ "CEQ_H\0"	---
9209	/* 14698 */ "FTQ_H\0"	---	9209	/* 14698 */ "FTQ_H\0"	---
9210	/* 14704 */ "MSUB_Q_H\0"	---	9210	/* 14704 */ "MSUB_Q_H\0"	---
9211	/* 14713 */ "MADD_Q_H\0"	---	9211	/* 14713 */ "MADD_Q_H\0"	---
9212	/* 14722 */ "MUL_Q_H\0"	---	9212	/* 14722 */ "MUL_Q_H\0"	---
9213	/* 14730 */ "MSUBR_Q_H\0"	---	9213	/* 14730 */ "MSUBR_Q_H\0"	---
9214	/* 14740 */ "MADDR_Q_H\0"	---	9214	/* 14740 */ "MADDR_Q_H\0"	---
9215	/* 14750 */ "MULR_Q_H\0"	---	9215	/* 14750 */ "MULR_Q_H\0"	---
9216	/* 14759 */ "SRAR_H\0"	---	9216	/* 14759 */ "SRAR_H\0"	---
9217	/* 14766 */ "BCLR_H\0"	---	9217	/* 14766 */ "BCLR_H\0"	---
9218	/* 14773 */ "SRLR_H\0"	---	9218	/* 14773 */ "SRLR_H\0"	---
9219	/* 14780 */ "BINSR_H\0"	---	9219	/* 14780 */ "BINSR_H\0"	---
9220	/* 14788 */ "ILVR_H\0"	---	9220	/* 14788 */ "ILVR_H\0"	---
9221	/* 14795 */ "ASUB_S_H\0"	---	9221	/* 14795 */ "ASUB_S_H\0"	---
9222	/* 14804 */ "HSUB_S_H\0"	---	9222	/* 14804 */ "HSUB_S_H\0"	---
9223	/* 14813 */ "DPSUB_S_H\0"	---	9223	/* 14813 */ "DPSUB_S_H\0"	---
9224	/* 14823 */ "HADD_S_H\0"	---	9224	/* 14823 */ "HADD_S_H\0"	---
9225	/* 14832 */ "DPADD_S_H\0"	---	9225	/* 14832 */ "DPADD_S_H\0"	---
9226	/* 14842 */ "MOD_S_H\0"	---	9226	/* 14842 */ "MOD_S_H\0"	---
9227	/* 14850 */ "CLE_S_H\0"	---	9227	/* 14850 */ "CLE_S_H\0"	---
9228	/* 14858 */ "AVE_S_H\0"	---	9228	/* 14858 */ "AVE_S_H\0"	---
9229	/* 14866 */ "CLEI_S_H\0"	---	9229	/* 14866 */ "CLEI_S_H\0"	---
9230	/* 14875 */ "MINI_S_H\0"	---	9230	/* 14875 */ "MINI_S_H\0"	---
9231	/* 14884 */ "CLTI_S_H\0"	---	9231	/* 14884 */ "CLTI_S_H\0"	---
9232	/* 14893 */ "MAXI_S_H\0"	---	9232	/* 14893 */ "MAXI_S_H\0"	---
9233	/* 14902 */ "MIN_S_H\0"	---	9233	/* 14902 */ "MIN_S_H\0"	---
9234	/* 14910 */ "DOTP_S_H\0"	---	9234	/* 14910 */ "DOTP_S_H\0"	---
9235	/* 14919 */ "AVER_S_H\0"	---	9235	/* 14919 */ "AVER_S_H\0"	---
9236	/* 14928 */ "EXTR_S_H\0"	---	9236	/* 14928 */ "EXTR_S_H\0"	---
9237	/* 14937 */ "SUBS_S_H\0"	---	9237	/* 14937 */ "SUBS_S_H\0"	---
9238	/* 14946 */ "ADDS_S_H\0"	---	9238	/* 14946 */ "ADDS_S_H\0"	---
9239	/* 14955 */ "SAT_S_H\0"	---	9239	/* 14955 */ "SAT_S_H\0"	---
9240	/* 14963 */ "CLT_S_H\0"	---	9240	/* 14963 */ "CLT_S_H\0"	---
9241	/* 14971 */ "SUBSUU_S_H\0"	---	9241	/* 14971 */ "SUBSUU_S_H\0"	---
9242	/* 14982 */ "DIV_S_H\0"	---	9242	/* 14982 */ "DIV_S_H\0"	---
9243	/* 14990 */ "EXTRV_S_H\0"	---	9243	/* 14990 */ "EXTRV_S_H\0"	---
9244	/* 15000 */ "MAX_S_H\0"	---	9244	/* 15000 */ "MAX_S_H\0"	---
9245	/* 15008 */ "COPY_S_H\0"	---	9245	/* 15008 */ "COPY_S_H\0"	---
9246	/* 15017 */ "SPLAT_H\0"	---	9246	/* 15017 */ "SPLAT_H\0"	---
9247	/* 15025 */ "BSET_H\0"	---	9247	/* 15025 */ "BSET_H\0"	---
9248	/* 15032 */ "PCNT_H\0"	---	9248	/* 15032 */ "PCNT_H\0"	---
9249	/* 15039 */ "INSERT_H\0"	---	9249	/* 15039 */ "INSERT_H\0"	---
9250	/* 15048 */ "ST_H\0"	---	9250	/* 15048 */ "ST_H\0"	---
9251	/* 15053 */ "ASUB_U_H\0"	---	9251	/* 15053 */ "ASUB_U_H\0"	---
9252	/* 15062 */ "HSUB_U_H\0"	---	9252	/* 15062 */ "HSUB_U_H\0"	---
9253	/* 15071 */ "DPSUB_U_H\0"	---	9253	/* 15071 */ "DPSUB_U_H\0"	---
9254	/* 15081 */ "HADD_U_H\0"	---	9254	/* 15081 */ "HADD_U_H\0"	---
9255	/* 15090 */ "DPADD_U_H\0"	---	9255	/* 15090 */ "DPADD_U_H\0"	---
9256	/* 15100 */ "MOD_U_H\0"	---	9256	/* 15100 */ "MOD_U_H\0"	---
9257	/* 15108 */ "CLE_U_H\0"	---	9257	/* 15108 */ "CLE_U_H\0"	---
9258	/* 15116 */ "AVE_U_H\0"	---	9258	/* 15116 */ "AVE_U_H\0"	---
9259	/* 15124 */ "CLEI_U_H\0"	---	9259	/* 15124 */ "CLEI_U_H\0"	---
9260	/* 15133 */ "MINI_U_H\0"	---	9260	/* 15133 */ "MINI_U_H\0"	---
9261	/* 15142 */ "CLTI_U_H\0"	---	9261	/* 15142 */ "CLTI_U_H\0"	---
9262	/* 15151 */ "MAXI_U_H\0"	---	9262	/* 15151 */ "MAXI_U_H\0"	---
9263	/* 15160 */ "MIN_U_H\0"	---	9263	/* 15160 */ "MIN_U_H\0"	---
9264	/* 15168 */ "DOTP_U_H\0"	---	9264	/* 15168 */ "DOTP_U_H\0"	---
9265	/* 15177 */ "AVER_U_H\0"	---	9265	/* 15177 */ "AVER_U_H\0"	---
9266	/* 15186 */ "SUBS_U_H\0"	---	9266	/* 15186 */ "SUBS_U_H\0"	---
9267	/* 15195 */ "ADDS_U_H\0"	---	9267	/* 15195 */ "ADDS_U_H\0"	---
9268	/* 15204 */ "SUBSUS_U_H\0"	---	9268	/* 15204 */ "SUBSUS_U_H\0"	---
9269	/* 15215 */ "SAT_U_H\0"	---	9269	/* 15215 */ "SAT_U_H\0"	---
9270	/* 15223 */ "CLT_U_H\0"	---	9270	/* 15223 */ "CLT_U_H\0"	---
9271	/* 15231 */ "DIV_U_H\0"	---	9271	/* 15231 */ "DIV_U_H\0"	---
9272	/* 15239 */ "MAX_U_H\0"	---	9272	/* 15239 */ "MAX_U_H\0"	---
9273	/* 15247 */ "COPY_U_H\0"	---	9273	/* 15247 */ "COPY_U_H\0"	---
9274	/* 15256 */ "MSUBV_H\0"	---	9274	/* 15256 */ "MSUBV_H\0"	---
9275	/* 15264 */ "MADDV_H\0"	---	9275	/* 15264 */ "MADDV_H\0"	---
9276	/* 15272 */ "PCKEV_H\0"	---	9276	/* 15272 */ "PCKEV_H\0"	---
9277	/* 15280 */ "ILVEV_H\0"	---	9277	/* 15280 */ "ILVEV_H\0"	---
9278	/* 15288 */ "MULV_H\0"	---	9278	/* 15288 */ "MULV_H\0"	---
9279	/* 15295 */ "BZ_H\0"	---	9279	/* 15295 */ "BZ_H\0"	---
9280	/* 15300 */ "BNZ_H\0"	---	9280	/* 15300 */ "BNZ_H\0"	---
9281	/* 15306 */ "SYNCI\0"	---	9281	/* 15306 */ "SYNCI\0"	---
9282	/* 15312 */ "DI\0"	---	9282	/* 15312 */ "DI\0"	---
9283	/* 15315 */ "TGEI\0"	---	9283	/* 15315 */ "TGEI\0"	---
9284	/* 15320 */ "TNEI\0"	---	9284	/* 15320 */ "TNEI\0"	---
9285	/* 15325 */ "DAHI\0"	---	9285	/* 15325 */ "DAHI\0"	---
9286	/* 15330 */ "PseudoMFHI\0"	---	9286	/* 15330 */ "PseudoMFHI\0"	---
9287	/* 15341 */ "PseudoMTLOHI\0"	---	9287	/* 15341 */ "PseudoMTLOHI\0"	---
9288	/* 15354 */ "DBG_PHI\0"	---	9288	/* 15354 */ "DBG_PHI\0"	---
9289	/* 15362 */ "MFTHI\0"	---	9289	/* 15362 */ "MFTHI\0"	---
9290	/* 15368 */ "MTHI\0"	---	9290	/* 15368 */ "MTHI\0"	---
9291	/* 15373 */ "MTTHI\0"	---	9291	/* 15373 */ "MTTHI\0"	---
9292	/* 15379 */ "TEQI\0"	---	9292	/* 15379 */ "TEQI\0"	---
9293	/* 15384 */ "G_FPTOSI\0"	---	9293	/* 15384 */ "G_FPTOSI\0"	---
9294	/* 15393 */ "DATI\0"	---	9294	/* 15393 */ "DATI\0"	---
9295	/* 15398 */ "TLTI\0"	---	9295	/* 15398 */ "TLTI\0"	---
9296	/* 15403 */ "DAUI\0"	---	9296	/* 15403 */ "DAUI\0"	---
9297	/* 15408 */ "G_FPTOUI\0"	---	9297	/* 15408 */ "G_FPTOUI\0"	---
9298	/* 15417 */ "GINVI\0"	---	9298	/* 15417 */ "GINVI\0"	---
9299	/* 15423 */ "TLBWI\0"	---	9299	/* 15423 */ "TLBWI\0"	---
9300	/* 15429 */ "TLBGWI\0"	---	9300	/* 15429 */ "TLBGWI\0"	---
9301	/* 15436 */ "G_FPOWI\0"	---	9301	/* 15436 */ "G_FPOWI\0"	---
9302	/* 15444 */ "MOVN_I64_I\0"	---	9302	/* 15444 */ "MOVN_I64_I\0"	---
9303	/* 15455 */ "MOVZ_I64_I\0"	---	9303	/* 15455 */ "MOVZ_I64_I\0"	---
9304	/* 15466 */ "MOVF_I\0"	---	9304	/* 15466 */ "MOVF_I\0"	---
9305	/* 15473 */ "PseudoSELECTFP_F_I\0"	---	9305	/* 15473 */ "PseudoSELECTFP_F_I\0"	---
9306	/* 15492 */ "MOVN_I_I\0"	---	9306	/* 15492 */ "MOVN_I_I\0"	---
9307	/* 15501 */ "MOVZ_I_I\0"	---	9307	/* 15501 */ "MOVZ_I_I\0"	---
9308	/* 15510 */ "PseudoD_SELECT_I\0"	---	9308	/* 15510 */ "PseudoD_SELECT_I\0"	---
9309	/* 15527 */ "PseudoSELECT_I\0"	---	9309	/* 15527 */ "PseudoSELECT_I\0"	---
9310	/* 15542 */ "MOVT_I\0"	---	9310	/* 15542 */ "MOVT_I\0"	---
9311	/* 15549 */ "PseudoSELECTFP_T_I\0"	---	9311	/* 15549 */ "PseudoSELECTFP_T_I\0"	---
9312	/* 15568 */ "J\0"	---	9312	/* 15568 */ "J\0"	---
9313	/* 15570 */ "BREAK\0"	---	9313	/* 15570 */ "BREAK\0"	---
9314	/* 15576 */ "FORK\0"	---	9314	/* 15576 */ "FORK\0"	---
9315	/* 15581 */ "G_PTRMASK\0"	---	9315	/* 15581 */ "G_PTRMASK\0"	---
9316	/* 15591 */ "BAL\0"	---	9316	/* 15591 */ "BAL\0"	---
9317	/* 15595 */ "JAL\0"	---	9317	/* 15595 */ "JAL\0"	---
9318	/* 15599 */ "BGEZAL\0"	---	9318	/* 15599 */ "BGEZAL\0"	---
9319	/* 15606 */ "BLTZAL\0"	---	9319	/* 15606 */ "BLTZAL\0"	---
9320	/* 15613 */ "MULEU_S_PH_QBL\0"	---	9320	/* 15613 */ "MULEU_S_PH_QBL\0"	---
9321	/* 15628 */ "PRECEU_PH_QBL\0"	---	9321	/* 15628 */ "PRECEU_PH_QBL\0"	---
9322	/* 15642 */ "PRECEQU_PH_QBL\0"	---	9322	/* 15642 */ "PRECEQU_PH_QBL\0"	---
9323	/* 15657 */ "DPAU_H_QBL\0"	---	9323	/* 15657 */ "DPAU_H_QBL\0"	---
9324	/* 15668 */ "DPSU_H_QBL\0"	---	9324	/* 15668 */ "DPSU_H_QBL\0"	---
9325	/* 15679 */ "LDL\0"	---	9325	/* 15679 */ "LDL\0"	---
9326	/* 15683 */ "SDL\0"	---	9326	/* 15683 */ "SDL\0"	---
9327	/* 15687 */ "GC_LABEL\0"	---	9327	/* 15687 */ "GC_LABEL\0"	---
9328	/* 15696 */ "DBG_LABEL\0"	---	9328	/* 15696 */ "DBG_LABEL\0"	---
9329	/* 15706 */ "EH_LABEL\0"	---	9329	/* 15706 */ "EH_LABEL\0"	---
9330	/* 15715 */ "ANNOTATION_LABEL\0"	---	9330	/* 15715 */ "ANNOTATION_LABEL\0"	---
9331	/* 15732 */ "BGEL\0"	---	9331	/* 15732 */ "BGEL\0"	---
9332	/* 15737 */ "BLEL\0"	---	9332	/* 15737 */ "BLEL\0"	---
9333	/* 15742 */ "BNEL\0"	---	9333	/* 15742 */ "BNEL\0"	---
9334	/* 15747 */ "ICALL_BRANCH_FUNNEL\0"	---	9334	/* 15747 */ "ICALL_BRANCH_FUNNEL\0"	---
9335	/* 15767 */ "BC1FL\0"	---	9335	/* 15767 */ "BC1FL\0"	---
9336	/* 15773 */ "MAQ_SA_W_PHL\0"	---	9336	/* 15773 */ "MAQ_SA_W_PHL\0"	---
9337	/* 15786 */ "PRECEQ_W_PHL\0"	---	9337	/* 15786 */ "PRECEQ_W_PHL\0"	---
9338	/* 15799 */ "MAQ_S_W_PHL\0"	---	9338	/* 15799 */ "MAQ_S_W_PHL\0"	---
9339	/* 15811 */ "MULEQ_S_W_PHL\0"	---	9339	/* 15811 */ "MULEQ_S_W_PHL\0"	---
9340	/* 15825 */ "G_FSHL\0"	---	9340	/* 15825 */ "G_FSHL\0"	---
9341	/* 15832 */ "G_SHL\0"	---	9341	/* 15832 */ "G_SHL\0"	---
9342	/* 15838 */ "G_FCEIL\0"	---	9342	/* 15838 */ "G_FCEIL\0"	---
9343	/* 15846 */ "TAILCALL\0"	---	9343	/* 15846 */ "TAILCALL\0"	---
9344	/* 15855 */ "HYPCALL\0"	---	9344	/* 15855 */ "HYPCALL\0"	---
9345	/* 15863 */ "SYSCALL\0"	---	9345	/* 15863 */ "SYSCALL\0"	---
9346	/* 15871 */ "PATCHABLE_TAIL_CALL\0"	---	9346	/* 15871 */ "PATCHABLE_TAIL_CALL\0"	---
9347	/* 15891 */ "PATCHABLE_TYPED_EVENT_CALL\0"	---	9347	/* 15891 */ "PATCHABLE_TYPED_EVENT_CALL\0"	---
9348	/* 15918 */ "PATCHABLE_EVENT_CALL\0"	---	9348	/* 15918 */ "PATCHABLE_EVENT_CALL\0"	---
9349	/* 15939 */ "FENTRY_CALL\0"	---	9349	/* 15939 */ "FENTRY_CALL\0"	---
9350	/* 15951 */ "BGEZALL\0"	---	9350	/* 15951 */ "BGEZALL\0"	---
9351	/* 15959 */ "BLTZALL\0"	---	9351	/* 15959 */ "BLTZALL\0"	---
9352	/* 15967 */ "KILL\0"	---	9352	/* 15967 */ "KILL\0"	---
9353	/* 15972 */ "DSLL\0"	---	9353	/* 15972 */ "DSLL\0"	---
9354	/* 15977 */ "G_CONSTANT_POOL\0"	---	9354	/* 15977 */ "G_CONSTANT_POOL\0"	---
9355	/* 15993 */ "DROL\0"	---	9355	/* 15993 */ "DROL\0"	---
9356	/* 15998 */ "BEQL\0"	---	9356	/* 15998 */ "BEQL\0"	---
9357	/* 16003 */ "DSRL\0"	---	9357	/* 16003 */ "DSRL\0"	---
9358	/* 16008 */ "BC1TL\0"	---	9358	/* 16008 */ "BC1TL\0"	---
9359	/* 16014 */ "BGTL\0"	---	9359	/* 16014 */ "BGTL\0"	---
9360	/* 16019 */ "BLTL\0"	---	9360	/* 16019 */ "BLTL\0"	---
9361	/* 16024 */ "G_ROTL\0"	---	9361	/* 16024 */ "G_ROTL\0"	---
9362	/* 16031 */ "BGEUL\0"	---	9362	/* 16031 */ "BGEUL\0"	---
9363	/* 16037 */ "BLEUL\0"	---	9363	/* 16037 */ "BLEUL\0"	---
9364	/* 16043 */ "DMUL\0"	---	9364	/* 16043 */ "DMUL\0"	---
9365	/* 16048 */ "G_VECREDUCE_FMUL\0"	---	9365	/* 16048 */ "G_VECREDUCE_FMUL\0"	---
9366	/* 16065 */ "G_FMUL\0"	---	9366	/* 16065 */ "G_FMUL\0"	---
9367	/* 16072 */ "G_VECREDUCE_SEQ_FMUL\0"	---	9367	/* 16072 */ "G_VECREDUCE_SEQ_FMUL\0"	---
9368	/* 16093 */ "G_STRICT_FMUL\0"	---	9368	/* 16093 */ "G_STRICT_FMUL\0"	---
9369	/* 16107 */ "G_VECREDUCE_MUL\0"	---	9369	/* 16107 */ "G_VECREDUCE_MUL\0"	---
9370	/* 16123 */ "G_MUL\0"	---	9370	/* 16123 */ "G_MUL\0"	---
9371	/* 16129 */ "BGTUL\0"	---	9371	/* 16129 */ "BGTUL\0"	---
9372	/* 16135 */ "BLTUL\0"	---	9372	/* 16135 */ "BLTUL\0"	---
9373	/* 16141 */ "LWL\0"	---	9373	/* 16141 */ "LWL\0"	---
9374	/* 16145 */ "SWL\0"	---	9374	/* 16145 */ "SWL\0"	---
9375	/* 16149 */ "BGEZL\0"	---	9375	/* 16149 */ "BGEZL\0"	---
9376	/* 16155 */ "BLEZL\0"	---	9376	/* 16155 */ "BLEZL\0"	---
9377	/* 16161 */ "BGTZL\0"	---	9377	/* 16161 */ "BGTZL\0"	---
9378	/* 16167 */ "BLTZL\0"	---	9378	/* 16167 */ "BLTZL\0"	---
9379	/* 16173 */ "PseudoCVT_D64_L\0"	---	9379	/* 16173 */ "PseudoCVT_D64_L\0"	---
9380	/* 16189 */ "PseudoCVT_S_L\0"	---	9380	/* 16189 */ "PseudoCVT_S_L\0"	---
9381	/* 16203 */ "G_FREM\0"	---	9381	/* 16203 */ "G_FREM\0"	---
9382	/* 16210 */ "G_STRICT_FREM\0"	---	9382	/* 16210 */ "G_STRICT_FREM\0"	---
9383	/* 16224 */ "G_SREM\0"	---	9383	/* 16224 */ "G_SREM\0"	---
9384	/* 16231 */ "G_UREM\0"	---	9384	/* 16231 */ "G_UREM\0"	---
9385	/* 16238 */ "G_SDIVREM\0"	---	9385	/* 16238 */ "G_SDIVREM\0"	---
9386	/* 16248 */ "G_UDIVREM\0"	---	9386	/* 16248 */ "G_UDIVREM\0"	---
9387	/* 16258 */ "MFGC0_MM\0"	---	9387	/* 16258 */ "MFGC0_MM\0"	---
9388	/* 16267 */ "MFHGC0_MM\0"	---	9388	/* 16267 */ "MFHGC0_MM\0"	---
9389	/* 16277 */ "MTHGC0_MM\0"	---	9389	/* 16277 */ "MTHGC0_MM\0"	---
9390	/* 16287 */ "MTGC0_MM\0"	---	9390	/* 16287 */ "MTGC0_MM\0"	---
9391	/* 16296 */ "CFC1_MM\0"	---	9391	/* 16296 */ "CFC1_MM\0"	---
9392	/* 16304 */ "MFC1_MM\0"	---	9392	/* 16304 */ "MFC1_MM\0"	---
9393	/* 16312 */ "CTC1_MM\0"	---	9393	/* 16312 */ "CTC1_MM\0"	---
9394	/* 16320 */ "MTC1_MM\0"	---	9394	/* 16320 */ "MTC1_MM\0"	---
9395	/* 16328 */ "LWC1_MM\0"	---	9395	/* 16328 */ "LWC1_MM\0"	---
9396	/* 16336 */ "SWC1_MM\0"	---	9396	/* 16336 */ "SWC1_MM\0"	---
9397	/* 16344 */ "LUXC1_MM\0"	---	9397	/* 16344 */ "LUXC1_MM\0"	---
9398	/* 16353 */ "SUXC1_MM\0"	---	9398	/* 16353 */ "SUXC1_MM\0"	---
9399	/* 16362 */ "LWXC1_MM\0"	---	9399	/* 16362 */ "LWXC1_MM\0"	---
9400	/* 16371 */ "SWXC1_MM\0"	---	9400	/* 16371 */ "SWXC1_MM\0"	---
9401	/* 16380 */ "MFHC1_D32_MM\0"	---	9401	/* 16380 */ "MFHC1_D32_MM\0"	---
9402	/* 16393 */ "MTHC1_D32_MM\0"	---	9402	/* 16393 */ "MTHC1_D32_MM\0"	---
9403	/* 16406 */ "FSUB_D32_MM\0"	---	9403	/* 16406 */ "FSUB_D32_MM\0"	---
9404	/* 16418 */ "NMSUB_D32_MM\0"	---	9404	/* 16418 */ "NMSUB_D32_MM\0"	---
9405	/* 16431 */ "FADD_D32_MM\0"	---	9405	/* 16431 */ "FADD_D32_MM\0"	---
9406	/* 16443 */ "NMADD_D32_MM\0"	---	9406	/* 16443 */ "NMADD_D32_MM\0"	---
9407	/* 16456 */ "C_NGE_D32_MM\0"	---	9407	/* 16456 */ "C_NGE_D32_MM\0"	---
9408	/* 16469 */ "C_NGLE_D32_MM\0"	---	9408	/* 16469 */ "C_NGLE_D32_MM\0"	---
9409	/* 16483 */ "C_OLE_D32_MM\0"	---	9409	/* 16483 */ "C_OLE_D32_MM\0"	---
9410	/* 16496 */ "C_ULE_D32_MM\0"	---	9410	/* 16496 */ "C_ULE_D32_MM\0"	---
9411	/* 16509 */ "C_LE_D32_MM\0"	---	9411	/* 16509 */ "C_LE_D32_MM\0"	---
9412	/* 16521 */ "C_SF_D32_MM\0"	---	9412	/* 16521 */ "C_SF_D32_MM\0"	---
9413	/* 16533 */ "MOVF_D32_MM\0"	---	9413	/* 16533 */ "MOVF_D32_MM\0"	---
9414	/* 16545 */ "C_F_D32_MM\0"	---	9414	/* 16545 */ "C_F_D32_MM\0"	---
9415	/* 16556 */ "FNEG_D32_MM\0"	---	9415	/* 16556 */ "FNEG_D32_MM\0"	---
9416	/* 16568 */ "MOVN_I_D32_MM\0"	---	9416	/* 16568 */ "MOVN_I_D32_MM\0"	---
9417	/* 16582 */ "MOVZ_I_D32_MM\0"	---	9417	/* 16582 */ "MOVZ_I_D32_MM\0"	---
9418	/* 16596 */ "C_NGL_D32_MM\0"	---	9418	/* 16596 */ "C_NGL_D32_MM\0"	---
9419	/* 16609 */ "FMUL_D32_MM\0"	---	9419	/* 16609 */ "FMUL_D32_MM\0"	---
9420	/* 16621 */ "C_UN_D32_MM\0"	---	9420	/* 16621 */ "C_UN_D32_MM\0"	---
9421	/* 16633 */ "RECIP_D32_MM\0"	---	9421	/* 16633 */ "RECIP_D32_MM\0"	---
9422	/* 16646 */ "FCMP_D32_MM\0"	---	9422	/* 16646 */ "FCMP_D32_MM\0"	---
9423	/* 16658 */ "C_SEQ_D32_MM\0"	---	9423	/* 16658 */ "C_SEQ_D32_MM\0"	---
9424	/* 16671 */ "C_UEQ_D32_MM\0"	---	9424	/* 16671 */ "C_UEQ_D32_MM\0"	---
9425	/* 16684 */ "C_EQ_D32_MM\0"	---	9425	/* 16684 */ "C_EQ_D32_MM\0"	---
9426	/* 16696 */ "FABS_D32_MM\0"	---	9426	/* 16696 */ "FABS_D32_MM\0"	---
9427	/* 16708 */ "CVT_S_D32_MM\0"	---	9427	/* 16708 */ "CVT_S_D32_MM\0"	---
9428	/* 16721 */ "C_NGT_D32_MM\0"	---	9428	/* 16721 */ "C_NGT_D32_MM\0"	---
9429	/* 16734 */ "C_OLT_D32_MM\0"	---	9429	/* 16734 */ "C_OLT_D32_MM\0"	---
9430	/* 16747 */ "C_ULT_D32_MM\0"	---	9430	/* 16747 */ "C_ULT_D32_MM\0"	---
9431	/* 16760 */ "C_LT_D32_MM\0"	---	9431	/* 16760 */ "C_LT_D32_MM\0"	---
9432	/* 16772 */ "FSQRT_D32_MM\0"	---	9432	/* 16772 */ "FSQRT_D32_MM\0"	---
9433	/* 16785 */ "RSQRT_D32_MM\0"	---	9433	/* 16785 */ "RSQRT_D32_MM\0"	---
9434	/* 16798 */ "MOVT_D32_MM\0"	---	9434	/* 16798 */ "MOVT_D32_MM\0"	---
9435	/* 16810 */ "FDIV_D32_MM\0"	---	9435	/* 16810 */ "FDIV_D32_MM\0"	---
9436	/* 16822 */ "FMOV_D32_MM\0"	---	9436	/* 16822 */ "FMOV_D32_MM\0"	---
9437	/* 16834 */ "CVT_W_D32_MM\0"	---	9437	/* 16834 */ "CVT_W_D32_MM\0"	---
9438	/* 16847 */ "BPOSGE32_MM\0"	---	9438	/* 16847 */ "BPOSGE32_MM\0"	---
9439	/* 16859 */ "LWM32_MM\0"	---	9439	/* 16859 */ "LWM32_MM\0"	---
9440	/* 16868 */ "SWM32_MM\0"	---	9440	/* 16868 */ "SWM32_MM\0"	---
9441	/* 16877 */ "FCMP_S32_MM\0"	---	9441	/* 16877 */ "FCMP_S32_MM\0"	---
9442	/* 16889 */ "CFC2_MM\0"	---	9442	/* 16889 */ "CFC2_MM\0"	---
9443	/* 16897 */ "CTC2_MM\0"	---	9443	/* 16897 */ "CTC2_MM\0"	---
9444	/* 16905 */ "ADDIUR2_MM\0"	---	9444	/* 16905 */ "ADDIUR2_MM\0"	---
9445	/* 16916 */ "MFHC1_D64_MM\0"	---	9445	/* 16916 */ "MFHC1_D64_MM\0"	---
9446	/* 16929 */ "MTHC1_D64_MM\0"	---	9446	/* 16929 */ "MTHC1_D64_MM\0"	---
9447	/* 16942 */ "MTC1_D64_MM\0"	---	9447	/* 16942 */ "MTC1_D64_MM\0"	---
9448	/* 16954 */ "FSUB_D64_MM\0"	---	9448	/* 16954 */ "FSUB_D64_MM\0"	---
9449	/* 16966 */ "FADD_D64_MM\0"	---	9449	/* 16966 */ "FADD_D64_MM\0"	---
9450	/* 16978 */ "C_NGE_D64_MM\0"	---	9450	/* 16978 */ "C_NGE_D64_MM\0"	---
9451	/* 16991 */ "C_NGLE_D64_MM\0"	---	9451	/* 16991 */ "C_NGLE_D64_MM\0"	---
9452	/* 17005 */ "C_OLE_D64_MM\0"	---	9452	/* 17005 */ "C_OLE_D64_MM\0"	---
9453	/* 17018 */ "C_ULE_D64_MM\0"	---	9453	/* 17018 */ "C_ULE_D64_MM\0"	---
9454	/* 17031 */ "C_LE_D64_MM\0"	---	9454	/* 17031 */ "C_LE_D64_MM\0"	---
9455	/* 17043 */ "C_SF_D64_MM\0"	---	9455	/* 17043 */ "C_SF_D64_MM\0"	---
9456	/* 17055 */ "C_F_D64_MM\0"	---	9456	/* 17055 */ "C_F_D64_MM\0"	---
9457	/* 17066 */ "FNEG_D64_MM\0"	---	9457	/* 17066 */ "FNEG_D64_MM\0"	---
9458	/* 17078 */ "C_NGL_D64_MM\0"	---	9458	/* 17078 */ "C_NGL_D64_MM\0"	---
9459	/* 17091 */ "FMUL_D64_MM\0"	---	9459	/* 17091 */ "FMUL_D64_MM\0"	---
9460	/* 17103 */ "CVT_L_D64_MM\0"	---	9460	/* 17103 */ "CVT_L_D64_MM\0"	---
9461	/* 17116 */ "C_UN_D64_MM\0"	---	9461	/* 17116 */ "C_UN_D64_MM\0"	---
9462	/* 17128 */ "RECIP_D64_MM\0"	---	9462	/* 17128 */ "RECIP_D64_MM\0"	---
9463	/* 17141 */ "C_SEQ_D64_MM\0"	---	9463	/* 17141 */ "C_SEQ_D64_MM\0"	---
9464	/* 17154 */ "C_UEQ_D64_MM\0"	---	9464	/* 17154 */ "C_UEQ_D64_MM\0"	---
9465	/* 17167 */ "C_EQ_D64_MM\0"	---	9465	/* 17167 */ "C_EQ_D64_MM\0"	---
9466	/* 17179 */ "FABS_D64_MM\0"	---	9466	/* 17179 */ "FABS_D64_MM\0"	---
9467	/* 17191 */ "CVT_S_D64_MM\0"	---	9467	/* 17191 */ "CVT_S_D64_MM\0"	---
9468	/* 17204 */ "C_NGT_D64_MM\0"	---	9468	/* 17204 */ "C_NGT_D64_MM\0"	---
9469	/* 17217 */ "C_OLT_D64_MM\0"	---	9469	/* 17217 */ "C_OLT_D64_MM\0"	---
9470	/* 17230 */ "C_ULT_D64_MM\0"	---	9470	/* 17230 */ "C_ULT_D64_MM\0"	---
9471	/* 17243 */ "C_LT_D64_MM\0"	---	9471	/* 17243 */ "C_LT_D64_MM\0"	---
9472	/* 17255 */ "FSQRT_D64_MM\0"	---	9472	/* 17255 */ "FSQRT_D64_MM\0"	---
9473	/* 17268 */ "RSQRT_D64_MM\0"	---	9473	/* 17268 */ "RSQRT_D64_MM\0"	---
9474	/* 17281 */ "FDIV_D64_MM\0"	---	9474	/* 17281 */ "FDIV_D64_MM\0"	---
9475	/* 17293 */ "FMOV_D64_MM\0"	---	9475	/* 17293 */ "FMOV_D64_MM\0"	---
9476	/* 17305 */ "CVT_W_D64_MM\0"	---	9476	/* 17305 */ "CVT_W_D64_MM\0"	---
9477	/* 17318 */ "ADDIUS5_MM\0"	---	9477	/* 17318 */ "ADDIUS5_MM\0"	---
9478	/* 17329 */ "SB16_MM\0"	---	9478	/* 17329 */ "SB16_MM\0"	---
9479	/* 17337 */ "JRC16_MM\0"	---	9479	/* 17337 */ "JRC16_MM\0"	---
9480	/* 17346 */ "AND16_MM\0"	---	9480	/* 17346 */ "AND16_MM\0"	---
9481	/* 17355 */ "MOVE16_MM\0"	---	9481	/* 17355 */ "MOVE16_MM\0"	---
9482	/* 17365 */ "SH16_MM\0"	---	9482	/* 17365 */ "SH16_MM\0"	---
9483	/* 17373 */ "ANDI16_MM\0"	---	9483	/* 17373 */ "ANDI16_MM\0"	---
9484	/* 17383 */ "MFHI16_MM\0"	---	9484	/* 17383 */ "MFHI16_MM\0"	---
9485	/* 17393 */ "LI16_MM\0"	---	9485	/* 17393 */ "LI16_MM\0"	---
9486	/* 17401 */ "BREAK16_MM\0"	---	9486	/* 17401 */ "BREAK16_MM\0"	---
9487	/* 17412 */ "SLL16_MM\0"	---	9487	/* 17412 */ "SLL16_MM\0"	---
9488	/* 17421 */ "SRL16_MM\0"	---	9488	/* 17421 */ "SRL16_MM\0"	---
9489	/* 17430 */ "LWM16_MM\0"	---	9489	/* 17430 */ "LWM16_MM\0"	---
9490	/* 17439 */ "SWM16_MM\0"	---	9490	/* 17439 */ "SWM16_MM\0"	---
9491	/* 17448 */ "MFLO16_MM\0"	---	9491	/* 17448 */ "MFLO16_MM\0"	---
9492	/* 17458 */ "SDBBP16_MM\0"	---	9492	/* 17458 */ "SDBBP16_MM\0"	---
9493	/* 17469 */ "JR16_MM\0"	---	9493	/* 17469 */ "JR16_MM\0"	---
9494	/* 17477 */ "JALR16_MM\0"	---	9494	/* 17477 */ "JALR16_MM\0"	---
9495	/* 17487 */ "XOR16_MM\0"	---	9495	/* 17487 */ "XOR16_MM\0"	---
9496	/* 17496 */ "JALRS16_MM\0"	---	9496	/* 17496 */ "JALRS16_MM\0"	---
9497	/* 17507 */ "NOT16_MM\0"	---	9497	/* 17507 */ "NOT16_MM\0"	---
9498	/* 17516 */ "LBU16_MM\0"	---	9498	/* 17516 */ "LBU16_MM\0"	---
9499	/* 17525 */ "SUBU16_MM\0"	---	9499	/* 17525 */ "SUBU16_MM\0"	---
9500	/* 17535 */ "ADDU16_MM\0"	---	9500	/* 17535 */ "ADDU16_MM\0"	---
9501	/* 17545 */ "LHU16_MM\0"	---	9501	/* 17545 */ "LHU16_MM\0"	---
9502	/* 17554 */ "LW16_MM\0"	---	9502	/* 17554 */ "LW16_MM\0"	---
9503	/* 17562 */ "SW16_MM\0"	---	9503	/* 17562 */ "SW16_MM\0"	---
9504	/* 17570 */ "BNEZ16_MM\0"	---	9504	/* 17570 */ "BNEZ16_MM\0"	---
9505	/* 17580 */ "BEQZ16_MM\0"	---	9505	/* 17580 */ "BEQZ16_MM\0"	---
9506	/* 17590 */ "PRECEU_PH_QBLA_MM\0"	---	9506	/* 17590 */ "PRECEU_PH_QBLA_MM\0"	---
9507	/* 17608 */ "PRECEQU_PH_QBLA_MM\0"	---	9507	/* 17608 */ "PRECEQU_PH_QBLA_MM\0"	---
9508	/* 17627 */ "PRECEU_PH_QBRA_MM\0"	---	9508	/* 17627 */ "PRECEU_PH_QBRA_MM\0"	---
9509	/* 17645 */ "PRECEQU_PH_QBRA_MM\0"	---	9509	/* 17645 */ "PRECEQU_PH_QBRA_MM\0"	---
9510	/* 17664 */ "SRA_MM\0"	---	9510	/* 17664 */ "SRA_MM\0"	---
9511	/* 17671 */ "SEB_MM\0"	---	9511	/* 17671 */ "SEB_MM\0"	---
9512	/* 17678 */ "EHB_MM\0"	---	9512	/* 17678 */ "EHB_MM\0"	---
9513	/* 17685 */ "LB_MM\0"	---	9513	/* 17685 */ "LB_MM\0"	---
9514	/* 17691 */ "CMPGU_LE_QB_MM\0"	---	9514	/* 17691 */ "CMPGU_LE_QB_MM\0"	---
9515	/* 17706 */ "CMPU_LE_QB_MM\0"	---	9515	/* 17706 */ "CMPU_LE_QB_MM\0"	---
9516	/* 17720 */ "PICK_QB_MM\0"	---	9516	/* 17720 */ "PICK_QB_MM\0"	---
9517	/* 17731 */ "SHLL_QB_MM\0"	---	9517	/* 17731 */ "SHLL_QB_MM\0"	---
9518	/* 17742 */ "REPL_QB_MM\0"	---	9518	/* 17742 */ "REPL_QB_MM\0"	---
9519	/* 17753 */ "SHRL_QB_MM\0"	---	9519	/* 17753 */ "SHRL_QB_MM\0"	---
9520	/* 17764 */ "CMPGU_EQ_QB_MM\0"	---	9520	/* 17764 */ "CMPGU_EQ_QB_MM\0"	---
9521	/* 17779 */ "CMPU_EQ_QB_MM\0"	---	9521	/* 17779 */ "CMPU_EQ_QB_MM\0"	---
9522	/* 17793 */ "SUBU_S_QB_MM\0"	---	9522	/* 17793 */ "SUBU_S_QB_MM\0"	---
9523	/* 17806 */ "ADDU_S_QB_MM\0"	---	9523	/* 17806 */ "ADDU_S_QB_MM\0"	---
9524	/* 17819 */ "CMPGU_LT_QB_MM\0"	---	9524	/* 17819 */ "CMPGU_LT_QB_MM\0"	---
9525	/* 17834 */ "CMPU_LT_QB_MM\0"	---	9525	/* 17834 */ "CMPU_LT_QB_MM\0"	---
9526	/* 17848 */ "SUBU_QB_MM\0"	---	9526	/* 17848 */ "SUBU_QB_MM\0"	---
9527	/* 17859 */ "ADDU_QB_MM\0"	---	9527	/* 17859 */ "ADDU_QB_MM\0"	---
9528	/* 17870 */ "SHLLV_QB_MM\0"	---	9528	/* 17870 */ "SHLLV_QB_MM\0"	---
9529	/* 17882 */ "REPLV_QB_MM\0"	---	9529	/* 17882 */ "REPLV_QB_MM\0"	---
9530	/* 17894 */ "SHRLV_QB_MM\0"	---	9530	/* 17894 */ "SHRLV_QB_MM\0"	---
9531	/* 17906 */ "RADDU_W_QB_MM\0"	---	9531	/* 17906 */ "RADDU_W_QB_MM\0"	---
9532	/* 17920 */ "SB_MM\0"	---	9532	/* 17920 */ "SB_MM\0"	---
9533	/* 17926 */ "MODSUB_MM\0"	---	9533	/* 17926 */ "MODSUB_MM\0"	---
9534	/* 17936 */ "PseudoMSUB_MM\0"	---	9534	/* 17936 */ "PseudoMSUB_MM\0"	---
9535	/* 17950 */ "SYNC_MM\0"	---	9535	/* 17950 */ "SYNC_MM\0"	---
9536	/* 17958 */ "ADDIUPC_MM\0"	---	9536	/* 17958 */ "ADDIUPC_MM\0"	---
9537	/* 17969 */ "ADDSC_MM\0"	---	9537	/* 17969 */ "ADDSC_MM\0"	---
9538	/* 17978 */ "ADDWC_MM\0"	---	9538	/* 17978 */ "ADDWC_MM\0"	---
9539	/* 17987 */ "BNEZC_MM\0"	---	9539	/* 17987 */ "BNEZC_MM\0"	---
9540	/* 17996 */ "BEQZC_MM\0"	---	9540	/* 17996 */ "BEQZC_MM\0"	---
9541	/* 18005 */ "PseudoMADD_MM\0"	---	9541	/* 18005 */ "PseudoMADD_MM\0"	---
9542	/* 18019 */ "AND_MM\0"	---	9542	/* 18019 */ "AND_MM\0"	---
9543	/* 18026 */ "LBE_MM\0"	---	9543	/* 18026 */ "LBE_MM\0"	---
9544	/* 18033 */ "SBE_MM\0"	---	9544	/* 18033 */ "SBE_MM\0"	---
9545	/* 18040 */ "SCE_MM\0"	---	9545	/* 18040 */ "SCE_MM\0"	---
9546	/* 18047 */ "CACHEE_MM\0"	---	9546	/* 18047 */ "CACHEE_MM\0"	---
9547	/* 18057 */ "PREFE_MM\0"	---	9547	/* 18057 */ "PREFE_MM\0"	---
9548	/* 18066 */ "TGE_MM\0"	---	9548	/* 18066 */ "TGE_MM\0"	---
9549	/* 18073 */ "CACHE_MM\0"	---	9549	/* 18073 */ "CACHE_MM\0"	---
9550	/* 18082 */ "LHE_MM\0"	---	9550	/* 18082 */ "LHE_MM\0"	---
9551	/* 18089 */ "SHE_MM\0"	---	9551	/* 18089 */ "SHE_MM\0"	---
9552	/* 18096 */ "LLE_MM\0"	---	9552	/* 18096 */ "LLE_MM\0"	---
9553	/* 18103 */ "LWLE_MM\0"	---	9553	/* 18103 */ "LWLE_MM\0"	---
9554	/* 18111 */ "SWLE_MM\0"	---	9554	/* 18111 */ "SWLE_MM\0"	---
9555	/* 18119 */ "BNE_MM\0"	---	9555	/* 18119 */ "BNE_MM\0"	---
9556	/* 18126 */ "TNE_MM\0"	---	9556	/* 18126 */ "TNE_MM\0"	---
9557	/* 18133 */ "LWRE_MM\0"	---	9557	/* 18133 */ "LWRE_MM\0"	---
9558	/* 18141 */ "SWRE_MM\0"	---	9558	/* 18141 */ "SWRE_MM\0"	---
9559	/* 18149 */ "PAUSE_MM\0"	---	9559	/* 18149 */ "PAUSE_MM\0"	---
9560	/* 18158 */ "LWE_MM\0"	---	9560	/* 18158 */ "LWE_MM\0"	---
9561	/* 18165 */ "SWE_MM\0"	---	9561	/* 18165 */ "SWE_MM\0"	---
9562	/* 18172 */ "LBuE_MM\0"	---	9562	/* 18172 */ "LBuE_MM\0"	---
9563	/* 18180 */ "LHuE_MM\0"	---	9563	/* 18180 */ "LHuE_MM\0"	---
9564	/* 18188 */ "BC1F_MM\0"	---	9564	/* 18188 */ "BC1F_MM\0"	---
9565	/* 18196 */ "PREF_MM\0"	---	9565	/* 18196 */ "PREF_MM\0"	---
9566	/* 18204 */ "TLBGINVF_MM\0"	---	9566	/* 18204 */ "TLBGINVF_MM\0"	---
9567	/* 18216 */ "TAILCALLREG_MM\0"	---	9567	/* 18216 */ "TAILCALLREG_MM\0"	---
9568	/* 18231 */ "WSBH_MM\0"	---	9568	/* 18231 */ "WSBH_MM\0"	---
9569	/* 18239 */ "SEH_MM\0"	---	9569	/* 18239 */ "SEH_MM\0"	---
9570	/* 18246 */ "LH_MM\0"	---	9570	/* 18246 */ "LH_MM\0"	---
9571	/* 18252 */ "SHRA_PH_MM\0"	---	9571	/* 18252 */ "SHRA_PH_MM\0"	---
9572	/* 18263 */ "PRECRQ_QB_PH_MM\0"	---	9572	/* 18263 */ "PRECRQ_QB_PH_MM\0"	---
9573	/* 18279 */ "PRECRQU_S_QB_PH_MM\0"	---	9573	/* 18279 */ "PRECRQU_S_QB_PH_MM\0"	---
9574	/* 18298 */ "CMP_LE_PH_MM\0"	---	9574	/* 18298 */ "CMP_LE_PH_MM\0"	---
9575	/* 18311 */ "PICK_PH_MM\0"	---	9575	/* 18311 */ "PICK_PH_MM\0"	---
9576	/* 18322 */ "SHLL_PH_MM\0"	---	9576	/* 18322 */ "SHLL_PH_MM\0"	---
9577	/* 18333 */ "REPL_PH_MM\0"	---	9577	/* 18333 */ "REPL_PH_MM\0"	---
9578	/* 18344 */ "PACKRL_PH_MM\0"	---	9578	/* 18344 */ "PACKRL_PH_MM\0"	---
9579	/* 18357 */ "SUBQ_PH_MM\0"	---	9579	/* 18357 */ "SUBQ_PH_MM\0"	---
9580	/* 18368 */ "ADDQ_PH_MM\0"	---	9580	/* 18368 */ "ADDQ_PH_MM\0"	---
9581	/* 18379 */ "CMP_EQ_PH_MM\0"	---	9581	/* 18379 */ "CMP_EQ_PH_MM\0"	---
9582	/* 18392 */ "SHRA_R_PH_MM\0"	---	9582	/* 18392 */ "SHRA_R_PH_MM\0"	---
9583	/* 18405 */ "SHRAV_R_PH_MM\0"	---	9583	/* 18405 */ "SHRAV_R_PH_MM\0"	---
9584	/* 18419 */ "MULQ_RS_PH_MM\0"	---	9584	/* 18419 */ "MULQ_RS_PH_MM\0"	---
9585	/* 18433 */ "SHLL_S_PH_MM\0"	---	9585	/* 18433 */ "SHLL_S_PH_MM\0"	---
9586	/* 18446 */ "SUBQ_S_PH_MM\0"	---	9586	/* 18446 */ "SUBQ_S_PH_MM\0"	---
9587	/* 18459 */ "ADDQ_S_PH_MM\0"	---	9587	/* 18459 */ "ADDQ_S_PH_MM\0"	---
9588	/* 18472 */ "ABSQ_S_PH_MM\0"	---	9588	/* 18472 */ "ABSQ_S_PH_MM\0"	---
9589	/* 18485 */ "SHLLV_S_PH_MM\0"	---	9589	/* 18485 */ "SHLLV_S_PH_MM\0"	---
9590	/* 18499 */ "CMP_LT_PH_MM\0"	---	9590	/* 18499 */ "CMP_LT_PH_MM\0"	---
9591	/* 18512 */ "SHRAV_PH_MM\0"	---	9591	/* 18512 */ "SHRAV_PH_MM\0"	---
9592	/* 18524 */ "SHLLV_PH_MM\0"	---	9592	/* 18524 */ "SHLLV_PH_MM\0"	---
9593	/* 18536 */ "REPLV_PH_MM\0"	---	9593	/* 18536 */ "REPLV_PH_MM\0"	---
9594	/* 18548 */ "DPAQ_S_W_PH_MM\0"	---	9594	/* 18548 */ "DPAQ_S_W_PH_MM\0"	---
9595	/* 18563 */ "MULSAQ_S_W_PH_MM\0"	---	9595	/* 18563 */ "MULSAQ_S_W_PH_MM\0"	---
9596	/* 18580 */ "DPSQ_S_W_PH_MM\0"	---	9596	/* 18580 */ "DPSQ_S_W_PH_MM\0"	---
9597	/* 18595 */ "SH_MM\0"	---	9597	/* 18595 */ "SH_MM\0"	---
9598	/* 18601 */ "EXTR_S_H_MM\0"	---	9598	/* 18601 */ "EXTR_S_H_MM\0"	---
9599	/* 18613 */ "EXTRV_S_H_MM\0"	---	9599	/* 18613 */ "EXTRV_S_H_MM\0"	---
9600	/* 18626 */ "SYNCI_MM\0"	---	9600	/* 18626 */ "SYNCI_MM\0"	---
9601	/* 18635 */ "DI_MM\0"	---	9601	/* 18635 */ "DI_MM\0"	---
9602	/* 18641 */ "TGEI_MM\0"	---	9602	/* 18641 */ "TGEI_MM\0"	---
9603	/* 18649 */ "TNEI_MM\0"	---	9603	/* 18649 */ "TNEI_MM\0"	---
9604	/* 18657 */ "PseudoMFHI_MM\0"	---	9604	/* 18657 */ "PseudoMFHI_MM\0"	---
9605	/* 18671 */ "PseudoMTLOHI_MM\0"	---	9605	/* 18671 */ "PseudoMTLOHI_MM\0"	---
9606	/* 18687 */ "MTHI_MM\0"	---	9606	/* 18687 */ "MTHI_MM\0"	---
9607	/* 18695 */ "TEQI_MM\0"	---	9607	/* 18695 */ "TEQI_MM\0"	---
9608	/* 18703 */ "TLTI_MM\0"	---	9608	/* 18703 */ "TLTI_MM\0"	---
9609	/* 18711 */ "TLBWI_MM\0"	---	9609	/* 18711 */ "TLBWI_MM\0"	---
9610	/* 18720 */ "TLBGWI_MM\0"	---	9610	/* 18720 */ "TLBGWI_MM\0"	---
9611	/* 18730 */ "MOVF_I_MM\0"	---	9611	/* 18730 */ "MOVF_I_MM\0"	---
9612	/* 18740 */ "MOVN_I_MM\0"	---	9612	/* 18740 */ "MOVN_I_MM\0"	---
9613	/* 18750 */ "MOVT_I_MM\0"	---	9613	/* 18750 */ "MOVT_I_MM\0"	---
9614	/* 18760 */ "MOVZ_I_MM\0"	---	9614	/* 18760 */ "MOVZ_I_MM\0"	---
9615	/* 18770 */ "J_MM\0"	---	9615	/* 18770 */ "J_MM\0"	---
9616	/* 18775 */ "BREAK_MM\0"	---	9616	/* 18775 */ "BREAK_MM\0"	---
9617	/* 18784 */ "JAL_MM\0"	---	9617	/* 18784 */ "JAL_MM\0"	---
9618	/* 18791 */ "BGEZAL_MM\0"	---	9618	/* 18791 */ "BGEZAL_MM\0"	---
9619	/* 18801 */ "BLTZAL_MM\0"	---	9619	/* 18801 */ "BLTZAL_MM\0"	---
9620	/* 18811 */ "MULEU_S_PH_QBL_MM\0"	---	9620	/* 18811 */ "MULEU_S_PH_QBL_MM\0"	---
9621	/* 18829 */ "PRECEU_PH_QBL_MM\0"	---	9621	/* 18829 */ "PRECEU_PH_QBL_MM\0"	---
9622	/* 18846 */ "PRECEQU_PH_QBL_MM\0"	---	9622	/* 18846 */ "PRECEQU_PH_QBL_MM\0"	---
9623	/* 18864 */ "DPAU_H_QBL_MM\0"	---	9623	/* 18864 */ "DPAU_H_QBL_MM\0"	---
9624	/* 18878 */ "DPSU_H_QBL_MM\0"	---	9624	/* 18878 */ "DPSU_H_QBL_MM\0"	---
9625	/* 18892 */ "MAQ_SA_W_PHL_MM\0"	---	9625	/* 18892 */ "MAQ_SA_W_PHL_MM\0"	---
9626	/* 18908 */ "PRECEQ_W_PHL_MM\0"	---	9626	/* 18908 */ "PRECEQ_W_PHL_MM\0"	---
9627	/* 18924 */ "MAQ_S_W_PHL_MM\0"	---	9627	/* 18924 */ "MAQ_S_W_PHL_MM\0"	---
9628	/* 18939 */ "MULEQ_S_W_PHL_MM\0"	---	9628	/* 18939 */ "MULEQ_S_W_PHL_MM\0"	---
9629	/* 18956 */ "TAILCALL_MM\0"	---	9629	/* 18956 */ "TAILCALL_MM\0"	---
9630	/* 18968 */ "HYPCALL_MM\0"	---	9630	/* 18968 */ "HYPCALL_MM\0"	---
9631	/* 18979 */ "SYSCALL_MM\0"	---	9631	/* 18979 */ "SYSCALL_MM\0"	---
9632	/* 18990 */ "SLL_MM\0"	---	9632	/* 18990 */ "SLL_MM\0"	---
9633	/* 18997 */ "SRL_MM\0"	---	9633	/* 18997 */ "SRL_MM\0"	---
9634	/* 19004 */ "MUL_MM\0"	---	9634	/* 19004 */ "MUL_MM\0"	---
9635	/* 19011 */ "LWL_MM\0"	---	9635	/* 19011 */ "LWL_MM\0"	---
9636	/* 19018 */ "SWL_MM\0"	---	9636	/* 19018 */ "SWL_MM\0"	---
9637	/* 19025 */ "LWM_MM\0"	---	9637	/* 19025 */ "LWM_MM\0"	---
9638	/* 19032 */ "SWM_MM\0"	---	9638	/* 19032 */ "SWM_MM\0"	---
9639	/* 19039 */ "CLO_MM\0"	---	9639	/* 19039 */ "CLO_MM\0"	---
9640	/* 19046 */ "PseudoMFLO_MM\0"	---	9640	/* 19046 */ "PseudoMFLO_MM\0"	---
9641	/* 19060 */ "SHILO_MM\0"	---	9641	/* 19060 */ "SHILO_MM\0"	---
9642	/* 19069 */ "MTLO_MM\0"	---	9642	/* 19069 */ "MTLO_MM\0"	---
9643	/* 19077 */ "TRAP_MM\0"	---	9643	/* 19077 */ "TRAP_MM\0"	---
9644	/* 19085 */ "SDBBP_MM\0"	---	9644	/* 19085 */ "SDBBP_MM\0"	---
9645	/* 19094 */ "TLBP_MM\0"	---	9645	/* 19094 */ "TLBP_MM\0"	---
9646	/* 19102 */ "EXTPDP_MM\0"	---	9646	/* 19102 */ "EXTPDP_MM\0"	---
9647	/* 19112 */ "MOVEP_MM\0"	---	9647	/* 19112 */ "MOVEP_MM\0"	---
9648	/* 19121 */ "TLBGP_MM\0"	---	9648	/* 19121 */ "TLBGP_MM\0"	---
9649	/* 19130 */ "LWGP_MM\0"	---	9649	/* 19130 */ "LWGP_MM\0"	---
9650	/* 19138 */ "MTHLIP_MM\0"	---	9650	/* 19138 */ "MTHLIP_MM\0"	---
9651	/* 19148 */ "SSNOP_MM\0"	---	9651	/* 19148 */ "SSNOP_MM\0"	---
9652	/* 19157 */ "ADDIUR1SP_MM\0"	---	9652	/* 19157 */ "ADDIUR1SP_MM\0"	---
9653	/* 19170 */ "RDDSP_MM\0"	---	9653	/* 19170 */ "RDDSP_MM\0"	---
9654	/* 19179 */ "WRDSP_MM\0"	---	9654	/* 19179 */ "WRDSP_MM\0"	---
9655	/* 19188 */ "LWDSP_MM\0"	---	9655	/* 19188 */ "LWDSP_MM\0"	---
9656	/* 19197 */ "SWDSP_MM\0"	---	9656	/* 19197 */ "SWDSP_MM\0"	---
9657	/* 19206 */ "MSUB_DSP_MM\0"	---	9657	/* 19206 */ "MSUB_DSP_MM\0"	---
9658	/* 19218 */ "MADD_DSP_MM\0"	---	9658	/* 19218 */ "MADD_DSP_MM\0"	---
9659	/* 19230 */ "MFHI_DSP_MM\0"	---	9659	/* 19230 */ "MFHI_DSP_MM\0"	---
9660	/* 19242 */ "MTHI_DSP_MM\0"	---	9660	/* 19242 */ "MTHI_DSP_MM\0"	---
9661	/* 19254 */ "MFLO_DSP_MM\0"	---	9661	/* 19254 */ "MFLO_DSP_MM\0"	---
9662	/* 19266 */ "MTLO_DSP_MM\0"	---	9662	/* 19266 */ "MTLO_DSP_MM\0"	---
9663	/* 19278 */ "MULT_DSP_MM\0"	---	9663	/* 19278 */ "MULT_DSP_MM\0"	---
9664	/* 19290 */ "MSUBU_DSP_MM\0"	---	9664	/* 19290 */ "MSUBU_DSP_MM\0"	---
9665	/* 19303 */ "MADDU_DSP_MM\0"	---	9665	/* 19303 */ "MADDU_DSP_MM\0"	---
9666	/* 19316 */ "MULTU_DSP_MM\0"	---	9666	/* 19316 */ "MULTU_DSP_MM\0"	---
9667	/* 19329 */ "ADDIUSP_MM\0"	---	9667	/* 19329 */ "ADDIUSP_MM\0"	---
9668	/* 19340 */ "LWSP_MM\0"	---	9668	/* 19340 */ "LWSP_MM\0"	---
9669	/* 19348 */ "SWSP_MM\0"	---	9669	/* 19348 */ "SWSP_MM\0"	---
9670	/* 19356 */ "EXTP_MM\0"	---	9670	/* 19356 */ "EXTP_MM\0"	---
9671	/* 19364 */ "LWP_MM\0"	---	9671	/* 19364 */ "LWP_MM\0"	---
9672	/* 19371 */ "SWP_MM\0"	---	9672	/* 19371 */ "SWP_MM\0"	---
9673	/* 19378 */ "BEQ_MM\0"	---	9673	/* 19378 */ "BEQ_MM\0"	---
9674	/* 19385 */ "TEQ_MM\0"	---	9674	/* 19385 */ "TEQ_MM\0"	---
9675	/* 19392 */ "TLBR_MM\0"	---	9675	/* 19392 */ "TLBR_MM\0"	---
9676	/* 19400 */ "MULEU_S_PH_QBR_MM\0"	---	9676	/* 19400 */ "MULEU_S_PH_QBR_MM\0"	---
9677	/* 19418 */ "PRECEU_PH_QBR_MM\0"	---	9677	/* 19418 */ "PRECEU_PH_QBR_MM\0"	---
9678	/* 19435 */ "PRECEQU_PH_QBR_MM\0"	---	9678	/* 19435 */ "PRECEQU_PH_QBR_MM\0"	---
9679	/* 19453 */ "DPAU_H_QBR_MM\0"	---	9679	/* 19453 */ "DPAU_H_QBR_MM\0"	---
9680	/* 19467 */ "DPSU_H_QBR_MM\0"	---	9680	/* 19467 */ "DPSU_H_QBR_MM\0"	---
9681	/* 19481 */ "BAL_BR_MM\0"	---	9681	/* 19481 */ "BAL_BR_MM\0"	---
9682	/* 19491 */ "TLBGR_MM\0"	---	9682	/* 19491 */ "TLBGR_MM\0"	---
9683	/* 19500 */ "MAQ_SA_W_PHR_MM\0"	---	9683	/* 19500 */ "MAQ_SA_W_PHR_MM\0"	---
9684	/* 19516 */ "PRECEQ_W_PHR_MM\0"	---	9684	/* 19516 */ "PRECEQ_W_PHR_MM\0"	---
9685	/* 19532 */ "MAQ_S_W_PHR_MM\0"	---	9685	/* 19532 */ "MAQ_S_W_PHR_MM\0"	---
9686	/* 19547 */ "MULEQ_S_W_PHR_MM\0"	---	9686	/* 19547 */ "MULEQ_S_W_PHR_MM\0"	---
9687	/* 19564 */ "JR_MM\0"	---	9687	/* 19564 */ "JR_MM\0"	---
9688	/* 19570 */ "JALR_MM\0"	---	9688	/* 19570 */ "JALR_MM\0"	---
9689	/* 19578 */ "NOR_MM\0"	---	9689	/* 19578 */ "NOR_MM\0"	---
9690	/* 19585 */ "XOR_MM\0"	---	9690	/* 19585 */ "XOR_MM\0"	---
9691	/* 19592 */ "ROTR_MM\0"	---	9691	/* 19592 */ "ROTR_MM\0"	---
9692	/* 19600 */ "TLBWR_MM\0"	---	9692	/* 19600 */ "TLBWR_MM\0"	---
9693	/* 19609 */ "TLBGWR_MM\0"	---	9693	/* 19609 */ "TLBGWR_MM\0"	---
9694	/* 19619 */ "RDHWR_MM\0"	---	9694	/* 19619 */ "RDHWR_MM\0"	---
9695	/* 19628 */ "LWR_MM\0"	---	9695	/* 19628 */ "LWR_MM\0"	---
9696	/* 19635 */ "SWR_MM\0"	---	9696	/* 19635 */ "SWR_MM\0"	---
9697	/* 19642 */ "JALS_MM\0"	---	9697	/* 19642 */ "JALS_MM\0"	---
9698	/* 19650 */ "BGEZALS_MM\0"	---	9698	/* 19650 */ "BGEZALS_MM\0"	---
9699	/* 19661 */ "BLTZALS_MM\0"	---	9699	/* 19661 */ "BLTZALS_MM\0"	---
9700	/* 19672 */ "INS_MM\0"	---	9700	/* 19672 */ "INS_MM\0"	---
9701	/* 19679 */ "JALRS_MM\0"	---	9701	/* 19679 */ "JALRS_MM\0"	---
9702	/* 19688 */ "LWXS_MM\0"	---	9702	/* 19688 */ "LWXS_MM\0"	---
9703	/* 19696 */ "CVT_D32_S_MM\0"	---	9703	/* 19696 */ "CVT_D32_S_MM\0"	---
9704	/* 19709 */ "CVT_D64_S_MM\0"	---	9704	/* 19709 */ "CVT_D64_S_MM\0"	---
9705	/* 19722 */ "FSUB_S_MM\0"	---	9705	/* 19722 */ "FSUB_S_MM\0"	---
9706	/* 19732 */ "NMSUB_S_MM\0"	---	9706	/* 19732 */ "NMSUB_S_MM\0"	---
9707	/* 19743 */ "FADD_S_MM\0"	---	9707	/* 19743 */ "FADD_S_MM\0"	---
9708	/* 19753 */ "NMADD_S_MM\0"	---	9708	/* 19753 */ "NMADD_S_MM\0"	---
9709	/* 19764 */ "C_NGE_S_MM\0"	---	9709	/* 19764 */ "C_NGE_S_MM\0"	---
9710	/* 19775 */ "C_NGLE_S_MM\0"	---	9710	/* 19775 */ "C_NGLE_S_MM\0"	---
9711	/* 19787 */ "C_OLE_S_MM\0"	---	9711	/* 19787 */ "C_OLE_S_MM\0"	---
9712	/* 19798 */ "C_ULE_S_MM\0"	---	9712	/* 19798 */ "C_ULE_S_MM\0"	---
9713	/* 19809 */ "C_LE_S_MM\0"	---	9713	/* 19809 */ "C_LE_S_MM\0"	---
9714	/* 19819 */ "C_SF_S_MM\0"	---	9714	/* 19819 */ "C_SF_S_MM\0"	---
9715	/* 19829 */ "MOVF_S_MM\0"	---	9715	/* 19829 */ "MOVF_S_MM\0"	---
9716	/* 19839 */ "C_F_S_MM\0"	---	9716	/* 19839 */ "C_F_S_MM\0"	---
9717	/* 19848 */ "FNEG_S_MM\0"	---	9717	/* 19848 */ "FNEG_S_MM\0"	---
9718	/* 19858 */ "MOVN_I_S_MM\0"	---	9718	/* 19858 */ "MOVN_I_S_MM\0"	---
9719	/* 19870 */ "MOVZ_I_S_MM\0"	---	9719	/* 19870 */ "MOVZ_I_S_MM\0"	---
9720	/* 19882 */ "C_NGL_S_MM\0"	---	9720	/* 19882 */ "C_NGL_S_MM\0"	---
9721	/* 19893 */ "FMUL_S_MM\0"	---	9721	/* 19893 */ "FMUL_S_MM\0"	---
9722	/* 19903 */ "CVT_L_S_MM\0"	---	9722	/* 19903 */ "CVT_L_S_MM\0"	---
9723	/* 19914 */ "C_UN_S_MM\0"	---	9723	/* 19914 */ "C_UN_S_MM\0"	---
9724	/* 19924 */ "RECIP_S_MM\0"	---	9724	/* 19924 */ "RECIP_S_MM\0"	---
9725	/* 19935 */ "C_SEQ_S_MM\0"	---	9725	/* 19935 */ "C_SEQ_S_MM\0"	---
9726	/* 19946 */ "C_UEQ_S_MM\0"	---	9726	/* 19946 */ "C_UEQ_S_MM\0"	---
9727	/* 19957 */ "C_EQ_S_MM\0"	---	9727	/* 19957 */ "C_EQ_S_MM\0"	---
9728	/* 19967 */ "FABS_S_MM\0"	---	9728	/* 19967 */ "FABS_S_MM\0"	---
9729	/* 19977 */ "C_NGT_S_MM\0"	---	9729	/* 19977 */ "C_NGT_S_MM\0"	---
9730	/* 19988 */ "C_OLT_S_MM\0"	---	9730	/* 19988 */ "C_OLT_S_MM\0"	---
9731	/* 19999 */ "C_ULT_S_MM\0"	---	9731	/* 19999 */ "C_ULT_S_MM\0"	---
9732	/* 20010 */ "C_LT_S_MM\0"	---	9732	/* 20010 */ "C_LT_S_MM\0"	---
9733	/* 20020 */ "FSQRT_S_MM\0"	---	9733	/* 20020 */ "FSQRT_S_MM\0"	---
9734	/* 20031 */ "RSQRT_S_MM\0"	---	9734	/* 20031 */ "RSQRT_S_MM\0"	---
9735	/* 20042 */ "MOVT_S_MM\0"	---	9735	/* 20042 */ "MOVT_S_MM\0"	---
9736	/* 20052 */ "FDIV_S_MM\0"	---	9736	/* 20052 */ "FDIV_S_MM\0"	---
9737	/* 20062 */ "FMOV_S_MM\0"	---	9737	/* 20062 */ "FMOV_S_MM\0"	---
9738	/* 20072 */ "TRUNC_W_S_MM\0"	---	9738	/* 20072 */ "TRUNC_W_S_MM\0"	---
9739	/* 20085 */ "ROUND_W_S_MM\0"	---	9739	/* 20085 */ "ROUND_W_S_MM\0"	---
9740	/* 20098 */ "CEIL_W_S_MM\0"	---	9740	/* 20098 */ "CEIL_W_S_MM\0"	---
9741	/* 20110 */ "FLOOR_W_S_MM\0"	---	9741	/* 20110 */ "FLOOR_W_S_MM\0"	---
9742	/* 20123 */ "CVT_W_S_MM\0"	---	9742	/* 20123 */ "CVT_W_S_MM\0"	---
9743	/* 20134 */ "BC1T_MM\0"	---	9743	/* 20134 */ "BC1T_MM\0"	---
9744	/* 20142 */ "DERET_MM\0"	---	9744	/* 20142 */ "DERET_MM\0"	---
9745	/* 20151 */ "WAIT_MM\0"	---	9745	/* 20151 */ "WAIT_MM\0"	---
9746	/* 20159 */ "SLT_MM\0"	---	9746	/* 20159 */ "SLT_MM\0"	---
9747	/* 20166 */ "TLT_MM\0"	---	9747	/* 20166 */ "TLT_MM\0"	---
9748	/* 20173 */ "PseudoMULT_MM\0"	---	9748	/* 20173 */ "PseudoMULT_MM\0"	---
9749	/* 20187 */ "EXT_MM\0"	---	9749	/* 20187 */ "EXT_MM\0"	---
9750	/* 20194 */ "PseudoMSUBU_MM\0"	---	9750	/* 20194 */ "PseudoMSUBU_MM\0"	---
9751	/* 20209 */ "PseudoMADDU_MM\0"	---	9751	/* 20209 */ "PseudoMADDU_MM\0"	---
9752	/* 20224 */ "TGEU_MM\0"	---	9752	/* 20224 */ "TGEU_MM\0"	---
9753	/* 20232 */ "TGEIU_MM\0"	---	9753	/* 20232 */ "TGEIU_MM\0"	---
9754	/* 20241 */ "TLTIU_MM\0"	---	9754	/* 20241 */ "TLTIU_MM\0"	---
9755	/* 20250 */ "TLTU_MM\0"	---	9755	/* 20250 */ "TLTU_MM\0"	---
9756	/* 20258 */ "LWU_MM\0"	---	9756	/* 20258 */ "LWU_MM\0"	---
9757	/* 20265 */ "SRAV_MM\0"	---	9757	/* 20265 */ "SRAV_MM\0"	---
9758	/* 20273 */ "BITREV_MM\0"	---	9758	/* 20273 */ "BITREV_MM\0"	---
9759	/* 20283 */ "SDIV_MM\0"	---	9759	/* 20283 */ "SDIV_MM\0"	---
9760	/* 20291 */ "UDIV_MM\0"	---	9760	/* 20291 */ "UDIV_MM\0"	---
9761	/* 20299 */ "SLLV_MM\0"	---	9761	/* 20299 */ "SLLV_MM\0"	---
9762	/* 20307 */ "SRLV_MM\0"	---	9762	/* 20307 */ "SRLV_MM\0"	---
9763	/* 20315 */ "TLBGINV_MM\0"	---	9763	/* 20315 */ "TLBGINV_MM\0"	---
9764	/* 20326 */ "SHILOV_MM\0"	---	9764	/* 20326 */ "SHILOV_MM\0"	---
9765	/* 20336 */ "EXTPDPV_MM\0"	---	9765	/* 20336 */ "EXTPDPV_MM\0"	---
9766	/* 20347 */ "EXTPV_MM\0"	---	9766	/* 20347 */ "EXTPV_MM\0"	---
9767	/* 20356 */ "ROTRV_MM\0"	---	9767	/* 20356 */ "ROTRV_MM\0"	---
9768	/* 20365 */ "INSV_MM\0"	---	9768	/* 20365 */ "INSV_MM\0"	---
9769	/* 20373 */ "LW_MM\0"	---	9769	/* 20373 */ "LW_MM\0"	---
9770	/* 20379 */ "SW_MM\0"	---	9770	/* 20379 */ "SW_MM\0"	---
9771	/* 20385 */ "CVT_D32_W_MM\0"	---	9771	/* 20385 */ "CVT_D32_W_MM\0"	---
9772	/* 20398 */ "CVT_D64_W_MM\0"	---	9772	/* 20398 */ "CVT_D64_W_MM\0"	---
9773	/* 20411 */ "TRUNC_W_MM\0"	---	9773	/* 20411 */ "TRUNC_W_MM\0"	---
9774	/* 20422 */ "ROUND_W_MM\0"	---	9774	/* 20422 */ "ROUND_W_MM\0"	---
9775	/* 20433 */ "PRECRQ_PH_W_MM\0"	---	9775	/* 20433 */ "PRECRQ_PH_W_MM\0"	---
9776	/* 20448 */ "PRECRQ_RS_PH_W_MM\0"	---	9776	/* 20448 */ "PRECRQ_RS_PH_W_MM\0"	---
9777	/* 20466 */ "CEIL_W_MM\0"	---	9777	/* 20466 */ "CEIL_W_MM\0"	---
9778	/* 20476 */ "DPAQ_SA_L_W_MM\0"	---	9778	/* 20476 */ "DPAQ_SA_L_W_MM\0"	---
9779	/* 20491 */ "DPSQ_SA_L_W_MM\0"	---	9779	/* 20491 */ "DPSQ_SA_L_W_MM\0"	---
9780	/* 20506 */ "FLOOR_W_MM\0"	---	9780	/* 20506 */ "FLOOR_W_MM\0"	---
9781	/* 20517 */ "EXTR_W_MM\0"	---	9781	/* 20517 */ "EXTR_W_MM\0"	---
9782	/* 20527 */ "SHRA_R_W_MM\0"	---	9782	/* 20527 */ "SHRA_R_W_MM\0"	---
9783	/* 20539 */ "EXTR_R_W_MM\0"	---	9783	/* 20539 */ "EXTR_R_W_MM\0"	---
9784	/* 20551 */ "SHRAV_R_W_MM\0"	---	9784	/* 20551 */ "SHRAV_R_W_MM\0"	---
9785	/* 20564 */ "EXTRV_R_W_MM\0"	---	9785	/* 20564 */ "EXTRV_R_W_MM\0"	---
9786	/* 20577 */ "EXTR_RS_W_MM\0"	---	9786	/* 20577 */ "EXTR_RS_W_MM\0"	---
9787	/* 20590 */ "EXTRV_RS_W_MM\0"	---	9787	/* 20590 */ "EXTRV_RS_W_MM\0"	---
9788	/* 20604 */ "SHLL_S_W_MM\0"	---	9788	/* 20604 */ "SHLL_S_W_MM\0"	---
9789	/* 20616 */ "SUBQ_S_W_MM\0"	---	9789	/* 20616 */ "SUBQ_S_W_MM\0"	---
9790	/* 20628 */ "ADDQ_S_W_MM\0"	---	9790	/* 20628 */ "ADDQ_S_W_MM\0"	---
9791	/* 20640 */ "ABSQ_S_W_MM\0"	---	9791	/* 20640 */ "ABSQ_S_W_MM\0"	---
9792	/* 20652 */ "CVT_S_W_MM\0"	---	9792	/* 20652 */ "CVT_S_W_MM\0"	---
9793	/* 20663 */ "SHLLV_S_W_MM\0"	---	9793	/* 20663 */ "SHLLV_S_W_MM\0"	---
9794	/* 20676 */ "EXTRV_W_MM\0"	---	9794	/* 20676 */ "EXTRV_W_MM\0"	---
9795	/* 20687 */ "PREFX_MM\0"	---	9795	/* 20687 */ "PREFX_MM\0"	---
9796	/* 20696 */ "LHX_MM\0"	---	9796	/* 20696 */ "LHX_MM\0"	---
9797	/* 20703 */ "JALX_MM\0"	---	9797	/* 20703 */ "JALX_MM\0"	---
9798	/* 20711 */ "LBUX_MM\0"	---	9798	/* 20711 */ "LBUX_MM\0"	---
9799	/* 20719 */ "LWX_MM\0"	---	9799	/* 20719 */ "LWX_MM\0"	---
9800	/* 20726 */ "BGEZ_MM\0"	---	9800	/* 20726 */ "BGEZ_MM\0"	---
9801	/* 20734 */ "BLEZ_MM\0"	---	9801	/* 20734 */ "BLEZ_MM\0"	---
9802	/* 20742 */ "CLZ_MM\0"	---	9802	/* 20742 */ "CLZ_MM\0"	---
9803	/* 20749 */ "BGTZ_MM\0"	---	9803	/* 20749 */ "BGTZ_MM\0"	---
9804	/* 20757 */ "BLTZ_MM\0"	---	9804	/* 20757 */ "BLTZ_MM\0"	---
9805	/* 20765 */ "PseudoIndirectBranch_MM\0"	---	9805	/* 20765 */ "PseudoIndirectBranch_MM\0"	---
9806	/* 20789 */ "ADDi_MM\0"	---	9806	/* 20789 */ "ADDi_MM\0"	---
9807	/* 20797 */ "ANDi_MM\0"	---	9807	/* 20797 */ "ANDi_MM\0"	---
9808	/* 20805 */ "XORi_MM\0"	---	9808	/* 20805 */ "XORi_MM\0"	---
9809	/* 20813 */ "SLTi_MM\0"	---	9809	/* 20813 */ "SLTi_MM\0"	---
9810	/* 20821 */ "LUi_MM\0"	---	9810	/* 20821 */ "LUi_MM\0"	---
9811	/* 20828 */ "LBu_MM\0"	---	9811	/* 20828 */ "LBu_MM\0"	---
9812	/* 20835 */ "SUBu_MM\0"	---	9812	/* 20835 */ "SUBu_MM\0"	---
9813	/* 20843 */ "ADDu_MM\0"	---	9813	/* 20843 */ "ADDu_MM\0"	---
9814	/* 20851 */ "LHu_MM\0"	---	9814	/* 20851 */ "LHu_MM\0"	---
9815	/* 20858 */ "SLTu_MM\0"	---	9815	/* 20858 */ "SLTu_MM\0"	---
9816	/* 20866 */ "PseudoMULTu_MM\0"	---	9816	/* 20866 */ "PseudoMULTu_MM\0"	---
9817	/* 20881 */ "LEA_ADDiu_MM\0"	---	9817	/* 20881 */ "LEA_ADDiu_MM\0"	---
9818	/* 20894 */ "SLTiu_MM\0"	---	9818	/* 20894 */ "SLTiu_MM\0"	---
9819	/* 20903 */ "INLINEASM\0"	---	9819	/* 20903 */ "INLINEASM\0"	---
9820	/* 20913 */ "DINSM\0"	---	9820	/* 20913 */ "DINSM\0"	---
9821	/* 20919 */ "DEXTM\0"	---	9821	/* 20919 */ "DEXTM\0"	---
9822	/* 20925 */ "G_FMINIMUM\0"	---	9822	/* 20925 */ "G_FMINIMUM\0"	---
9823	/* 20936 */ "G_FMAXIMUM\0"	---	9823	/* 20936 */ "G_FMAXIMUM\0"	---
9824	/* 20947 */ "G_FMINNUM\0"	---	9824	/* 20947 */ "G_FMINNUM\0"	---
9825	/* 20957 */ "G_FMAXNUM\0"	---	9825	/* 20957 */ "G_FMAXNUM\0"	---
9826	/* 20967 */ "G_INTRINSIC_ROUNDEVEN\0"	---	9826	/* 20967 */ "G_INTRINSIC_ROUNDEVEN\0"	---
9827	/* 20989 */ "BALIGN\0"	---	9827	/* 20989 */ "BALIGN\0"	---
9828	/* 20996 */ "DALIGN\0"	---	9828	/* 20996 */ "DALIGN\0"	---
9829	/* 21003 */ "G_ASSERT_ALIGN\0"	---	9829	/* 21003 */ "G_ASSERT_ALIGN\0"	---
9830	/* 21018 */ "G_FCOPYSIGN\0"	---	9830	/* 21018 */ "G_FCOPYSIGN\0"	---
9831	/* 21030 */ "G_VECREDUCE_FMIN\0"	---	9831	/* 21030 */ "G_VECREDUCE_FMIN\0"	---
9832	/* 21047 */ "G_ATOMICRMW_FMIN\0"	---	9832	/* 21047 */ "G_ATOMICRMW_FMIN\0"	---
9833	/* 21064 */ "G_VECREDUCE_SMIN\0"	---	9833	/* 21064 */ "G_VECREDUCE_SMIN\0"	---
9834	/* 21081 */ "G_SMIN\0"	---	9834	/* 21081 */ "G_SMIN\0"	---
9835	/* 21088 */ "G_VECREDUCE_UMIN\0"	---	9835	/* 21088 */ "G_VECREDUCE_UMIN\0"	---
9836	/* 21105 */ "G_UMIN\0"	---	9836	/* 21105 */ "G_UMIN\0"	---
9837	/* 21112 */ "G_ATOMICRMW_UMIN\0"	---	9837	/* 21112 */ "G_ATOMICRMW_UMIN\0"	---
9838	/* 21129 */ "G_ATOMICRMW_MIN\0"	---	9838	/* 21129 */ "G_ATOMICRMW_MIN\0"	---
9839	/* 21145 */ "G_FSIN\0"	---	9839	/* 21145 */ "G_FSIN\0"	---
9840	/* 21152 */ "DMFC2_OCTEON\0"	---	9840	/* 21152 */ "DMFC2_OCTEON\0"	---
9841	/* 21165 */ "DMTC2_OCTEON\0"	---	9841	/* 21165 */ "DMTC2_OCTEON\0"	---
9842	/* 21178 */ "CFI_INSTRUCTION\0"	---	9842	/* 21178 */ "CFI_INSTRUCTION\0"	---
9843	/* 21194 */ "ADJCALLSTACKDOWN\0"	---	9843	/* 21194 */ "ADJCALLSTACKDOWN\0"	---
9844	/* 21211 */ "G_SSUBO\0"	---	9844	/* 21211 */ "G_SSUBO\0"	---
9845	/* 21219 */ "G_USUBO\0"	---	9845	/* 21219 */ "G_USUBO\0"	---
9846	/* 21227 */ "G_SADDO\0"	---	9846	/* 21227 */ "G_SADDO\0"	---
9847	/* 21235 */ "G_UADDO\0"	---	9847	/* 21235 */ "G_UADDO\0"	---
9848	/* 21243 */ "FEXP2_D_1_PSEUDO\0"	---	9848	/* 21243 */ "FEXP2_D_1_PSEUDO\0"	---
9849	/* 21260 */ "FEXP2_W_1_PSEUDO\0"	---	9849	/* 21260 */ "FEXP2_W_1_PSEUDO\0"	---
9850	/* 21277 */ "BPOSGE32_PSEUDO\0"	---	9850	/* 21277 */ "BPOSGE32_PSEUDO\0"	---
9851	/* 21293 */ "INSERT_B_VIDX64_PSEUDO\0"	---	9851	/* 21293 */ "INSERT_B_VIDX64_PSEUDO\0"	---
9852	/* 21316 */ "INSERT_FD_VIDX64_PSEUDO\0"	---	9852	/* 21316 */ "INSERT_FD_VIDX64_PSEUDO\0"	---
9853	/* 21340 */ "INSERT_D_VIDX64_PSEUDO\0"	---	9853	/* 21340 */ "INSERT_D_VIDX64_PSEUDO\0"	---
9854	/* 21363 */ "INSERT_H_VIDX64_PSEUDO\0"	---	9854	/* 21363 */ "INSERT_H_VIDX64_PSEUDO\0"	---
9855	/* 21386 */ "INSERT_FW_VIDX64_PSEUDO\0"	---	9855	/* 21386 */ "INSERT_FW_VIDX64_PSEUDO\0"	---
9856	/* 21410 */ "INSERT_W_VIDX64_PSEUDO\0"	---	9856	/* 21410 */ "INSERT_W_VIDX64_PSEUDO\0"	---
9857	/* 21433 */ "SNZ_B_PSEUDO\0"	---	9857	/* 21433 */ "SNZ_B_PSEUDO\0"	---
9858	/* 21446 */ "SZ_B_PSEUDO\0"	---	9858	/* 21446 */ "SZ_B_PSEUDO\0"	---
9859	/* 21458 */ "BSEL_FD_PSEUDO\0"	---	9859	/* 21458 */ "BSEL_FD_PSEUDO\0"	---
9860	/* 21473 */ "FILL_FD_PSEUDO\0"	---	9860	/* 21473 */ "FILL_FD_PSEUDO\0"	---
9861	/* 21488 */ "INSERT_FD_PSEUDO\0"	---	9861	/* 21488 */ "INSERT_FD_PSEUDO\0"	---
9862	/* 21505 */ "COPY_FD_PSEUDO\0"	---	9862	/* 21505 */ "COPY_FD_PSEUDO\0"	---
9863	/* 21520 */ "MSA_FP_EXTEND_D_PSEUDO\0"	---	9863	/* 21520 */ "MSA_FP_EXTEND_D_PSEUDO\0"	---
9864	/* 21543 */ "MSA_FP_ROUND_D_PSEUDO\0"	---	9864	/* 21543 */ "MSA_FP_ROUND_D_PSEUDO\0"	---
9865	/* 21565 */ "BSEL_D_PSEUDO\0"	---	9865	/* 21565 */ "BSEL_D_PSEUDO\0"	---
9866	/* 21579 */ "AND_V_D_PSEUDO\0"	---	9866	/* 21579 */ "AND_V_D_PSEUDO\0"	---
9867	/* 21594 */ "NOR_V_D_PSEUDO\0"	---	9867	/* 21594 */ "NOR_V_D_PSEUDO\0"	---
9868	/* 21609 */ "XOR_V_D_PSEUDO\0"	---	9868	/* 21609 */ "XOR_V_D_PSEUDO\0"	---
9869	/* 21624 */ "SNZ_D_PSEUDO\0"	---	9869	/* 21624 */ "SNZ_D_PSEUDO\0"	---
9870	/* 21637 */ "SZ_D_PSEUDO\0"	---	9870	/* 21637 */ "SZ_D_PSEUDO\0"	---
9871	/* 21649 */ "BSEL_H_PSEUDO\0"	---	9871	/* 21649 */ "BSEL_H_PSEUDO\0"	---
9872	/* 21663 */ "AND_V_H_PSEUDO\0"	---	9872	/* 21663 */ "AND_V_H_PSEUDO\0"	---
9873	/* 21678 */ "NOR_V_H_PSEUDO\0"	---	9873	/* 21678 */ "NOR_V_H_PSEUDO\0"	---
9874	/* 21693 */ "XOR_V_H_PSEUDO\0"	---	9874	/* 21693 */ "XOR_V_H_PSEUDO\0"	---
9875	/* 21708 */ "SNZ_H_PSEUDO\0"	---	9875	/* 21708 */ "SNZ_H_PSEUDO\0"	---
9876	/* 21721 */ "SZ_H_PSEUDO\0"	---	9876	/* 21721 */ "SZ_H_PSEUDO\0"	---
9877	/* 21733 */ "SNZ_V_PSEUDO\0"	---	9877	/* 21733 */ "SNZ_V_PSEUDO\0"	---
9878	/* 21746 */ "SZ_V_PSEUDO\0"	---	9878	/* 21746 */ "SZ_V_PSEUDO\0"	---
9879	/* 21758 */ "BSEL_FW_PSEUDO\0"	---	9879	/* 21758 */ "BSEL_FW_PSEUDO\0"	---
9880	/* 21773 */ "FILL_FW_PSEUDO\0"	---	9880	/* 21773 */ "FILL_FW_PSEUDO\0"	---
9881	/* 21788 */ "INSERT_FW_PSEUDO\0"	---	9881	/* 21788 */ "INSERT_FW_PSEUDO\0"	---
9882	/* 21805 */ "COPY_FW_PSEUDO\0"	---	9882	/* 21805 */ "COPY_FW_PSEUDO\0"	---
9883	/* 21820 */ "MSA_FP_EXTEND_W_PSEUDO\0"	---	9883	/* 21820 */ "MSA_FP_EXTEND_W_PSEUDO\0"	---
9884	/* 21843 */ "MSA_FP_ROUND_W_PSEUDO\0"	---	9884	/* 21843 */ "MSA_FP_ROUND_W_PSEUDO\0"	---
9885	/* 21865 */ "BSEL_W_PSEUDO\0"	---	9885	/* 21865 */ "BSEL_W_PSEUDO\0"	---
9886	/* 21879 */ "AND_V_W_PSEUDO\0"	---	9886	/* 21879 */ "AND_V_W_PSEUDO\0"	---
9887	/* 21894 */ "NOR_V_W_PSEUDO\0"	---	9887	/* 21894 */ "NOR_V_W_PSEUDO\0"	---
9888	/* 21909 */ "XOR_V_W_PSEUDO\0"	---	9888	/* 21909 */ "XOR_V_W_PSEUDO\0"	---
9889	/* 21924 */ "SNZ_W_PSEUDO\0"	---	9889	/* 21924 */ "SNZ_W_PSEUDO\0"	---
9890	/* 21937 */ "SZ_W_PSEUDO\0"	---	9890	/* 21937 */ "SZ_W_PSEUDO\0"	---
9891	/* 21949 */ "INSERT_B_VIDX_PSEUDO\0"	---	9891	/* 21949 */ "INSERT_B_VIDX_PSEUDO\0"	---
9892	/* 21970 */ "INSERT_FD_VIDX_PSEUDO\0"	---	9892	/* 21970 */ "INSERT_FD_VIDX_PSEUDO\0"	---
9893	/* 21992 */ "INSERT_D_VIDX_PSEUDO\0"	---	9893	/* 21992 */ "INSERT_D_VIDX_PSEUDO\0"	---
9894	/* 22013 */ "INSERT_H_VIDX_PSEUDO\0"	---	9894	/* 22013 */ "INSERT_H_VIDX_PSEUDO\0"	---
9895	/* 22034 */ "INSERT_FW_VIDX_PSEUDO\0"	---	9895	/* 22034 */ "INSERT_FW_VIDX_PSEUDO\0"	---
9896	/* 22056 */ "INSERT_W_VIDX_PSEUDO\0"	---	9896	/* 22056 */ "INSERT_W_VIDX_PSEUDO\0"	---
9897	/* 22077 */ "DCLO\0"	---	9897	/* 22077 */ "DCLO\0"	---
9898	/* 22082 */ "PseudoMFLO\0"	---	9898	/* 22082 */ "PseudoMFLO\0"	---
9899	/* 22093 */ "SHILO\0"	---	9899	/* 22093 */ "SHILO\0"	---
9900	/* 22099 */ "MFTLO\0"	---	9900	/* 22099 */ "MFTLO\0"	---
9901	/* 22105 */ "MTLO\0"	---	9901	/* 22105 */ "MTLO\0"	---
9902	/* 22110 */ "MTTLO\0"	---	9902	/* 22110 */ "MTTLO\0"	---
9903	/* 22116 */ "G_SMULO\0"	---	9903	/* 22116 */ "G_SMULO\0"	---
9904	/* 22124 */ "G_UMULO\0"	---	9904	/* 22124 */ "G_UMULO\0"	---
9905	/* 22132 */ "G_BZERO\0"	---	9905	/* 22132 */ "G_BZERO\0"	---
9906	/* 22140 */ "STACKMAP\0"	---	9906	/* 22140 */ "STACKMAP\0"	---
9907	/* 22149 */ "TRAP\0"	---	9907	/* 22149 */ "TRAP\0"	---
9908	/* 22154 */ "G_ATOMICRMW_UDEC_WRAP\0"	---	9908	/* 22154 */ "G_ATOMICRMW_UDEC_WRAP\0"	---
9909	/* 22176 */ "G_ATOMICRMW_UINC_WRAP\0"	---	9909	/* 22176 */ "G_ATOMICRMW_UINC_WRAP\0"	---
9910	/* 22198 */ "G_BSWAP\0"	---	9910	/* 22198 */ "G_BSWAP\0"	---
9911	/* 22206 */ "DBITSWAP\0"	---	9911	/* 22206 */ "DBITSWAP\0"	---
9912	/* 22215 */ "SDBBP\0"	---	9912	/* 22215 */ "SDBBP\0"	---
9913	/* 22221 */ "TLBP\0"	---	9913	/* 22221 */ "TLBP\0"	---
9914	/* 22226 */ "EXTPDP\0"	---	9914	/* 22226 */ "EXTPDP\0"	---
9915	/* 22233 */ "G_SITOFP\0"	---	9915	/* 22233 */ "G_SITOFP\0"	---
9916	/* 22242 */ "G_UITOFP\0"	---	9916	/* 22242 */ "G_UITOFP\0"	---
9917	/* 22251 */ "TLBGP\0"	---	9917	/* 22251 */ "TLBGP\0"	---
9918	/* 22257 */ "MTHLIP\0"	---	9918	/* 22257 */ "MTHLIP\0"	---
9919	/* 22264 */ "G_FCMP\0"	---	9919	/* 22264 */ "G_FCMP\0"	---
9920	/* 22271 */ "G_ICMP\0"	---	9920	/* 22271 */ "G_ICMP\0"	---
9921	/* 22278 */ "SSNOP\0"	---	9921	/* 22278 */ "SSNOP\0"	---
9922	/* 22284 */ "DPOP\0"	---	9922	/* 22284 */ "DPOP\0"	---
9923	/* 22289 */ "G_CTPOP\0"	---	9923	/* 22289 */ "G_CTPOP\0"	---
9924	/* 22297 */ "PATCHABLE_OP\0"	---	9924	/* 22297 */ "PATCHABLE_OP\0"	---
9925	/* 22310 */ "FAULTING_OP\0"	---	9925	/* 22310 */ "FAULTING_OP\0"	---
9926	/* 22322 */ "LOAD_ACC64DSP\0"	---	9926	/* 22322 */ "LOAD_ACC64DSP\0"	---
9927	/* 22336 */ "STORE_ACC64DSP\0"	---	9927	/* 22336 */ "STORE_ACC64DSP\0"	---
9928	/* 22351 */ "RDDSP\0"	---	9928	/* 22351 */ "RDDSP\0"	---
9929	/* 22357 */ "WRDSP\0"	---	9929	/* 22357 */ "WRDSP\0"	---
9930	/* 22363 */ "MFTDSP\0"	---	9930	/* 22363 */ "MFTDSP\0"	---
9931	/* 22370 */ "MTTDSP\0"	---	9931	/* 22370 */ "MTTDSP\0"	---
9932	/* 22377 */ "LWDSP\0"	---	9932	/* 22377 */ "LWDSP\0"	---
9933	/* 22383 */ "SWDSP\0"	---	9933	/* 22383 */ "SWDSP\0"	---
9934	/* 22389 */ "MSUB_DSP\0"	---	9934	/* 22389 */ "MSUB_DSP\0"	---
9935	/* 22398 */ "MADD_DSP\0"	---	9935	/* 22398 */ "MADD_DSP\0"	---
9936	/* 22407 */ "LOAD_CCOND_DSP\0"	---	9936	/* 22407 */ "LOAD_CCOND_DSP\0"	---
9937	/* 22422 */ "STORE_CCOND_DSP\0"	---	9937	/* 22422 */ "STORE_CCOND_DSP\0"	---
9938	/* 22438 */ "MFHI_DSP\0"	---	9938	/* 22438 */ "MFHI_DSP\0"	---
9939	/* 22447 */ "PseudoMTLOHI_DSP\0"	---	9939	/* 22447 */ "PseudoMTLOHI_DSP\0"	---
9940	/* 22464 */ "MTHI_DSP\0"	---	9940	/* 22464 */ "MTHI_DSP\0"	---
9941	/* 22473 */ "MFLO_DSP\0"	---	9941	/* 22473 */ "MFLO_DSP\0"	---
9942	/* 22482 */ "MTLO_DSP\0"	---	9942	/* 22482 */ "MTLO_DSP\0"	---
9943	/* 22491 */ "MULT_DSP\0"	---	9943	/* 22491 */ "MULT_DSP\0"	---
9944	/* 22500 */ "MSUBU_DSP\0"	---	9944	/* 22500 */ "MSUBU_DSP\0"	---
9945	/* 22510 */ "MADDU_DSP\0"	---	9945	/* 22510 */ "MADDU_DSP\0"	---
9946	/* 22520 */ "MULTU_DSP\0"	---	9946	/* 22520 */ "MULTU_DSP\0"	---
9947	/* 22530 */ "JRADDIUSP\0"	---	9947	/* 22530 */ "JRADDIUSP\0"	---
9948	/* 22540 */ "EXTP\0"	---	9948	/* 22540 */ "EXTP\0"	---
9949	/* 22545 */ "ADJCALLSTACKUP\0"	---	9949	/* 22545 */ "ADJCALLSTACKUP\0"	---
9950	/* 22560 */ "PREALLOCATED_SETUP\0"	---	9950	/* 22560 */ "PREALLOCATED_SETUP\0"	---
9951	/* 22579 */ "DVP\0"	---	9951	/* 22579 */ "DVP\0"	---
9952	/* 22583 */ "EVP\0"	---	9952	/* 22583 */ "EVP\0"	---
9953	/* 22587 */ "G_FLDEXP\0"	---	9953	/* 22587 */ "G_FLDEXP\0"	---
9954	/* 22596 */ "G_STRICT_FLDEXP\0"	---	9954	/* 22596 */ "G_STRICT_FLDEXP\0"	---
9955	/* 22612 */ "G_FEXP\0"	---	9955	/* 22612 */ "G_FEXP\0"	---
9956	/* 22619 */ "G_FFREXP\0"	---	9956	/* 22619 */ "G_FFREXP\0"	---
9957	/* 22628 */ "BEQ\0"	---	9957	/* 22628 */ "BEQ\0"	---
9958	/* 22632 */ "SEQ\0"	---	9958	/* 22632 */ "SEQ\0"	---
9959	/* 22636 */ "TEQ\0"	---	9959	/* 22636 */ "TEQ\0"	---
9960	/* 22640 */ "TLBR\0"	---	9960	/* 22640 */ "TLBR\0"	---
9961	/* 22645 */ "MULEU_S_PH_QBR\0"	---	9961	/* 22645 */ "MULEU_S_PH_QBR\0"	---
9962	/* 22660 */ "PRECEU_PH_QBR\0"	---	9962	/* 22660 */ "PRECEU_PH_QBR\0"	---
9963	/* 22674 */ "PRECEQU_PH_QBR\0"	---	9963	/* 22674 */ "PRECEQU_PH_QBR\0"	---
9964	/* 22689 */ "DPAU_H_QBR\0"	---	9964	/* 22689 */ "DPAU_H_QBR\0"	---
9965	/* 22700 */ "DPSU_H_QBR\0"	---	9965	/* 22700 */ "DPSU_H_QBR\0"	---
9966	/* 22711 */ "G_BR\0"	---	9966	/* 22711 */ "G_BR\0"	---
9967	/* 22716 */ "BAL_BR\0"	---	9967	/* 22716 */ "BAL_BR\0"	---
9968	/* 22723 */ "INLINEASM_BR\0"	---	9968	/* 22723 */ "INLINEASM_BR\0"	---
9969	/* 22736 */ "G_BLOCK_ADDR\0"	---	9969	/* 22736 */ "G_BLOCK_ADDR\0"	---
9970	/* 22749 */ "LDR\0"	---	9970	/* 22749 */ "LDR\0"	---
9971	/* 22753 */ "SDR\0"	---	9971	/* 22753 */ "SDR\0"	---
9972	/* 22757 */ "MEMBARRIER\0"	---	9972	/* 22757 */ "MEMBARRIER\0"	---
9973	/* 22768 */ "G_CONSTANT_FOLD_BARRIER\0"	---	9973	/* 22768 */ "G_CONSTANT_FOLD_BARRIER\0"	---
9974	/* 22792 */ "PATCHABLE_FUNCTION_ENTER\0"	---	9974	/* 22792 */ "PATCHABLE_FUNCTION_ENTER\0"	---
9975	/* 22817 */ "G_READCYCLECOUNTER\0"	---	9975	/* 22817 */ "G_READCYCLECOUNTER\0"	---
9976	/* 22836 */ "G_READ_REGISTER\0"	---	9976	/* 22836 */ "G_READ_REGISTER\0"	---
9977	/* 22852 */ "G_WRITE_REGISTER\0"	---	9977	/* 22852 */ "G_WRITE_REGISTER\0"	---
9978	/* 22869 */ "TLBGR\0"	---	9978	/* 22869 */ "TLBGR\0"	---
9979	/* 22875 */ "LoadImmDoubleFGR\0"	---	9979	/* 22875 */ "LoadImmDoubleFGR\0"	---
9980	/* 22892 */ "LoadImmSingleFGR\0"	---	9980	/* 22892 */ "LoadImmSingleFGR\0"	---
9981	/* 22909 */ "MAQ_SA_W_PHR\0"	---	9981	/* 22909 */ "MAQ_SA_W_PHR\0"	---
9982	/* 22922 */ "PRECEQ_W_PHR\0"	---	9982	/* 22922 */ "PRECEQ_W_PHR\0"	---
9983	/* 22935 */ "MAQ_S_W_PHR\0"	---	9983	/* 22935 */ "MAQ_S_W_PHR\0"	---
9984	/* 22947 */ "MULEQ_S_W_PHR\0"	---	9984	/* 22947 */ "MULEQ_S_W_PHR\0"	---
9985	/* 22961 */ "G_ASHR\0"	---	9985	/* 22961 */ "G_ASHR\0"	---
9986	/* 22968 */ "G_FSHR\0"	---	9986	/* 22968 */ "G_FSHR\0"	---
9987	/* 22975 */ "G_LSHR\0"	---	9987	/* 22975 */ "G_LSHR\0"	---
9988	/* 22982 */ "JR\0"	---	9988	/* 22982 */ "JR\0"	---
9989	/* 22985 */ "JALR\0"	---	9989	/* 22985 */ "JALR\0"	---
9990	/* 22990 */ "NOR\0"	---	9990	/* 22990 */ "NOR\0"	---
9991	/* 22994 */ "G_FFLOOR\0"	---	9991	/* 22994 */ "G_FFLOOR\0"	---
9992	/* 23003 */ "DROR\0"	---	9992	/* 23003 */ "DROR\0"	---
9993	/* 23008 */ "G_BUILD_VECTOR\0"	---	9993	/* 23008 */ "G_BUILD_VECTOR\0"	---
9994	/* 23023 */ "G_SHUFFLE_VECTOR\0"	---	9994	/* 23023 */ "G_SHUFFLE_VECTOR\0"	---
9995	/* 23040 */ "G_VECREDUCE_XOR\0"	---	9995	/* 23040 */ "G_VECREDUCE_XOR\0"	---
9996	/* 23056 */ "G_XOR\0"	---	9996	/* 23056 */ "G_XOR\0"	---
9997	/* 23062 */ "G_ATOMICRMW_XOR\0"	---	9997	/* 23062 */ "G_ATOMICRMW_XOR\0"	---
9998	/* 23078 */ "G_VECREDUCE_OR\0"	---	9998	/* 23078 */ "G_VECREDUCE_OR\0"	---
9999	/* 23093 */ "G_OR\0"	---	9999	/* 23093 */ "G_OR\0"	---
10000	/* 23098 */ "G_ATOMICRMW_OR\0"	---	10000	/* 23098 */ "G_ATOMICRMW_OR\0"	---
10001	/* 23113 */ "MFTGPR\0"	---	10001	/* 23113 */ "MFTGPR\0"	---
10002	/* 23120 */ "MTTGPR\0"	---	10002	/* 23120 */ "MTTGPR\0"	---
10003	/* 23127 */ "LoadImmDoubleGPR\0"	---	10003	/* 23127 */ "LoadImmDoubleGPR\0"	---
10004	/* 23144 */ "LoadImmSingleGPR\0"	---	10004	/* 23144 */ "LoadImmSingleGPR\0"	---
10005	/* 23161 */ "MFTR\0"	---	10005	/* 23161 */ "MFTR\0"	---
10006	/* 23166 */ "DROTR\0"	---	10006	/* 23166 */ "DROTR\0"	---
10007	/* 23172 */ "G_ROTR\0"	---	10007	/* 23172 */ "G_ROTR\0"	---
10008	/* 23179 */ "G_INTTOPTR\0"	---	10008	/* 23179 */ "G_INTTOPTR\0"	---
10009	/* 23190 */ "MTTR\0"	---	10009	/* 23190 */ "MTTR\0"	---
10010	/* 23195 */ "TLBWR\0"	---	10010	/* 23195 */ "TLBWR\0"	---
10011	/* 23201 */ "TLBGWR\0"	---	10011	/* 23201 */ "TLBGWR\0"	---
10012	/* 23208 */ "RDHWR\0"	---	10012	/* 23208 */ "RDHWR\0"	---
10013	/* 23214 */ "LWR\0"	---	10013	/* 23214 */ "LWR\0"	---
10014	/* 23218 */ "SWR\0"	---	10014	/* 23218 */ "SWR\0"	---
10015	/* 23222 */ "G_FABS\0"	---	10015	/* 23222 */ "G_FABS\0"	---
10016	/* 23229 */ "G_ABS\0"	---	10016	/* 23229 */ "G_ABS\0"	---
10017	/* 23235 */ "G_UNMERGE_VALUES\0"	---	10017	/* 23235 */ "G_UNMERGE_VALUES\0"	---
10018	/* 23252 */ "G_MERGE_VALUES\0"	---	10018	/* 23252 */ "G_MERGE_VALUES\0"	---
10019	/* 23267 */ "CINS\0"	---	10019	/* 23267 */ "CINS\0"	---
10020	/* 23272 */ "DINS\0"	---	10020	/* 23272 */ "DINS\0"	---
10021	/* 23277 */ "G_FCOS\0"	---	10021	/* 23277 */ "G_FCOS\0"	---
10022	/* 23284 */ "G_CONCAT_VECTORS\0"	---	10022	/* 23284 */ "G_CONCAT_VECTORS\0"	---
10023	/* 23301 */ "COPY_TO_REGCLASS\0"	---	10023	/* 23301 */ "COPY_TO_REGCLASS\0"	---
10024	/* 23318 */ "G_IS_FPCLASS\0"	---	10024	/* 23318 */ "G_IS_FPCLASS\0"	---
10025	/* 23331 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"	---	10025	/* 23331 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"	---
10026	/* 23361 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"	---	10026	/* 23361 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"	---
10027	/* 23388 */ "EXTS\0"	---	10027	/* 23388 */ "EXTS\0"	---
10028	/* 23393 */ "CVT_D32_S\0"	---	10028	/* 23393 */ "CVT_D32_S\0"	---
10029	/* 23403 */ "CVT_D64_S\0"	---	10029	/* 23403 */ "CVT_D64_S\0"	---
10030	/* 23413 */ "MOVN_I64_S\0"	---	10030	/* 23413 */ "MOVN_I64_S\0"	---
10031	/* 23424 */ "MOVZ_I64_S\0"	---	10031	/* 23424 */ "MOVZ_I64_S\0"	---
10032	/* 23435 */ "MINA_S\0"	---	10032	/* 23435 */ "MINA_S\0"	---
10033	/* 23442 */ "MAXA_S\0"	---	10033	/* 23442 */ "MAXA_S\0"	---
10034	/* 23449 */ "FSUB_S\0"	---	10034	/* 23449 */ "FSUB_S\0"	---
10035	/* 23456 */ "NMSUB_S\0"	---	10035	/* 23456 */ "NMSUB_S\0"	---
10036	/* 23464 */ "FADD_S\0"	---	10036	/* 23464 */ "FADD_S\0"	---
10037	/* 23471 */ "NMADD_S\0"	---	10037	/* 23471 */ "NMADD_S\0"	---
10038	/* 23479 */ "C_NGE_S\0"	---	10038	/* 23479 */ "C_NGE_S\0"	---
10039	/* 23487 */ "C_NGLE_S\0"	---	10039	/* 23487 */ "C_NGLE_S\0"	---
10040	/* 23496 */ "C_OLE_S\0"	---	10040	/* 23496 */ "C_OLE_S\0"	---
10041	/* 23504 */ "CMP_SLE_S\0"	---	10041	/* 23504 */ "CMP_SLE_S\0"	---
10042	/* 23514 */ "CMP_SULE_S\0"	---	10042	/* 23514 */ "CMP_SULE_S\0"	---
10043	/* 23525 */ "C_ULE_S\0"	---	10043	/* 23525 */ "C_ULE_S\0"	---
10044	/* 23533 */ "CMP_ULE_S\0"	---	10044	/* 23533 */ "CMP_ULE_S\0"	---
10045	/* 23543 */ "C_LE_S\0"	---	10045	/* 23543 */ "C_LE_S\0"	---
10046	/* 23550 */ "CMP_LE_S\0"	---	10046	/* 23550 */ "CMP_LE_S\0"	---
10047	/* 23559 */ "CMP_SAF_S\0"	---	10047	/* 23559 */ "CMP_SAF_S\0"	---
10048	/* 23569 */ "MSUBF_S\0"	---	10048	/* 23569 */ "MSUBF_S\0"	---
10049	/* 23577 */ "MADDF_S\0"	---	10049	/* 23577 */ "MADDF_S\0"	---
10050	/* 23585 */ "C_SF_S\0"	---	10050	/* 23585 */ "C_SF_S\0"	---
10051	/* 23592 */ "MOVF_S\0"	---	10051	/* 23592 */ "MOVF_S\0"	---
10052	/* 23599 */ "C_F_S\0"	---	10052	/* 23599 */ "C_F_S\0"	---
10053	/* 23605 */ "PseudoSELECTFP_F_S\0"	---	10053	/* 23605 */ "PseudoSELECTFP_F_S\0"	---
10054	/* 23624 */ "CMP_F_S\0"	---	10054	/* 23624 */ "CMP_F_S\0"	---
10055	/* 23632 */ "FNEG_S\0"	---	10055	/* 23632 */ "FNEG_S\0"	---
10056	/* 23639 */ "MOVN_I_S\0"	---	10056	/* 23639 */ "MOVN_I_S\0"	---
10057	/* 23648 */ "MOVZ_I_S\0"	---	10057	/* 23648 */ "MOVZ_I_S\0"	---
10058	/* 23657 */ "SEL_S\0"	---	10058	/* 23657 */ "SEL_S\0"	---
10059	/* 23663 */ "C_NGL_S\0"	---	10059	/* 23663 */ "C_NGL_S\0"	---
10060	/* 23671 */ "FMUL_S\0"	---	10060	/* 23671 */ "FMUL_S\0"	---
10061	/* 23678 */ "TRUNC_L_S\0"	---	10061	/* 23678 */ "TRUNC_L_S\0"	---
10062	/* 23688 */ "ROUND_L_S\0"	---	10062	/* 23688 */ "ROUND_L_S\0"	---
10063	/* 23698 */ "CEIL_L_S\0"	---	10063	/* 23698 */ "CEIL_L_S\0"	---
10064	/* 23707 */ "FLOOR_L_S\0"	---	10064	/* 23707 */ "FLOOR_L_S\0"	---
10065	/* 23717 */ "CVT_L_S\0"	---	10065	/* 23717 */ "CVT_L_S\0"	---
10066	/* 23725 */ "MIN_S\0"	---	10066	/* 23725 */ "MIN_S\0"	---
10067	/* 23731 */ "CMP_SUN_S\0"	---	10067	/* 23731 */ "CMP_SUN_S\0"	---
10068	/* 23741 */ "C_UN_S\0"	---	10068	/* 23741 */ "C_UN_S\0"	---
10069	/* 23748 */ "CMP_UN_S\0"	---	10069	/* 23748 */ "CMP_UN_S\0"	---
10070	/* 23757 */ "RECIP_S\0"	---	10070	/* 23757 */ "RECIP_S\0"	---
10071	/* 23765 */ "C_SEQ_S\0"	---	10071	/* 23765 */ "C_SEQ_S\0"	---
10072	/* 23773 */ "CMP_SEQ_S\0"	---	10072	/* 23773 */ "CMP_SEQ_S\0"	---
10073	/* 23783 */ "CMP_SUEQ_S\0"	---	10073	/* 23783 */ "CMP_SUEQ_S\0"	---
10074	/* 23794 */ "C_UEQ_S\0"	---	10074	/* 23794 */ "C_UEQ_S\0"	---
10075	/* 23802 */ "CMP_UEQ_S\0"	---	10075	/* 23802 */ "CMP_UEQ_S\0"	---
10076	/* 23812 */ "C_EQ_S\0"	---	10076	/* 23812 */ "C_EQ_S\0"	---
10077	/* 23819 */ "CMP_EQ_S\0"	---	10077	/* 23819 */ "CMP_EQ_S\0"	---
10078	/* 23828 */ "FABS_S\0"	---	10078	/* 23828 */ "FABS_S\0"	---
10079	/* 23835 */ "CLASS_S\0"	---	10079	/* 23835 */ "CLASS_S\0"	---
10080	/* 23843 */ "PseudoSELECT_S\0"	---	10080	/* 23843 */ "PseudoSELECT_S\0"	---
10081	/* 23858 */ "C_NGT_S\0"	---	10081	/* 23858 */ "C_NGT_S\0"	---
10082	/* 23866 */ "C_OLT_S\0"	---	10082	/* 23866 */ "C_OLT_S\0"	---
10083	/* 23874 */ "CMP_SLT_S\0"	---	10083	/* 23874 */ "CMP_SLT_S\0"	---
10084	/* 23884 */ "CMP_SULT_S\0"	---	10084	/* 23884 */ "CMP_SULT_S\0"	---
10085	/* 23895 */ "C_ULT_S\0"	---	10085	/* 23895 */ "C_ULT_S\0"	---
10086	/* 23903 */ "CMP_ULT_S\0"	---	10086	/* 23903 */ "CMP_ULT_S\0"	---
10087	/* 23913 */ "C_LT_S\0"	---	10087	/* 23913 */ "C_LT_S\0"	---
10088	/* 23920 */ "CMP_LT_S\0"	---	10088	/* 23920 */ "CMP_LT_S\0"	---
10089	/* 23929 */ "RINT_S\0"	---	10089	/* 23929 */ "RINT_S\0"	---
10090	/* 23936 */ "FSQRT_S\0"	---	10090	/* 23936 */ "FSQRT_S\0"	---
10091	/* 23944 */ "RSQRT_S\0"	---	10091	/* 23944 */ "RSQRT_S\0"	---
10092	/* 23952 */ "MOVT_S\0"	---	10092	/* 23952 */ "MOVT_S\0"	---
10093	/* 23959 */ "PseudoSELECTFP_T_S\0"	---	10093	/* 23959 */ "PseudoSELECTFP_T_S\0"	---
10094	/* 23978 */ "FDIV_S\0"	---	10094	/* 23978 */ "FDIV_S\0"	---
10095	/* 23985 */ "FMOV_S\0"	---	10095	/* 23985 */ "FMOV_S\0"	---
10096	/* 23992 */ "PseudoTRUNC_W_S\0"	---	10096	/* 23992 */ "PseudoTRUNC_W_S\0"	---
10097	/* 24008 */ "ROUND_W_S\0"	---	10097	/* 24008 */ "ROUND_W_S\0"	---
10098	/* 24018 */ "CEIL_W_S\0"	---	10098	/* 24018 */ "CEIL_W_S\0"	---
10099	/* 24027 */ "FLOOR_W_S\0"	---	10099	/* 24027 */ "FLOOR_W_S\0"	---
10100	/* 24037 */ "CVT_W_S\0"	---	10100	/* 24037 */ "CVT_W_S\0"	---
10101	/* 24045 */ "MAX_S\0"	---	10101	/* 24045 */ "MAX_S\0"	---
10102	/* 24051 */ "SELNEZ_S\0"	---	10102	/* 24051 */ "SELNEZ_S\0"	---
10103	/* 24060 */ "SELEQZ_S\0"	---	10103	/* 24060 */ "SELEQZ_S\0"	---
10104	/* 24069 */ "BC1T\0"	---	10104	/* 24069 */ "BC1T\0"	---
10105	/* 24074 */ "G_SSUBSAT\0"	---	10105	/* 24074 */ "G_SSUBSAT\0"	---
10106	/* 24084 */ "G_USUBSAT\0"	---	10106	/* 24084 */ "G_USUBSAT\0"	---
10107	/* 24094 */ "G_SADDSAT\0"	---	10107	/* 24094 */ "G_SADDSAT\0"	---
10108	/* 24104 */ "G_UADDSAT\0"	---	10108	/* 24104 */ "G_UADDSAT\0"	---
10109	/* 24114 */ "G_SSHLSAT\0"	---	10109	/* 24114 */ "G_SSHLSAT\0"	---
10110	/* 24124 */ "G_USHLSAT\0"	---	10110	/* 24124 */ "G_USHLSAT\0"	---
10111	/* 24134 */ "G_SMULFIXSAT\0"	---	10111	/* 24134 */ "G_SMULFIXSAT\0"	---
10112	/* 24147 */ "G_UMULFIXSAT\0"	---	10112	/* 24147 */ "G_UMULFIXSAT\0"	---
10113	/* 24160 */ "G_SDIVFIXSAT\0"	---	10113	/* 24160 */ "G_SDIVFIXSAT\0"	---
10114	/* 24173 */ "G_UDIVFIXSAT\0"	---	10114	/* 24173 */ "G_UDIVFIXSAT\0"	---
10115	/* 24186 */ "G_EXTRACT\0"	---	10115	/* 24186 */ "G_EXTRACT\0"	---
10116	/* 24196 */ "G_SELECT\0"	---	10116	/* 24196 */ "G_SELECT\0"	---
10117	/* 24205 */ "G_BRINDIRECT\0"	---	10117	/* 24205 */ "G_BRINDIRECT\0"	---
10118	/* 24218 */ "DERET\0"	---	10118	/* 24218 */ "DERET\0"	---
10119	/* 24224 */ "PATCHABLE_RET\0"	---	10119	/* 24224 */ "PATCHABLE_RET\0"	---
10120	/* 24238 */ "G_MEMSET\0"	---	10120	/* 24238 */ "G_MEMSET\0"	---
10121	/* 24247 */ "BGT\0"	---	10121	/* 24247 */ "BGT\0"	---
10122	/* 24251 */ "WAIT\0"	---	10122	/* 24251 */ "WAIT\0"	---
10123	/* 24256 */ "PATCHABLE_FUNCTION_EXIT\0"	---	10123	/* 24256 */ "PATCHABLE_FUNCTION_EXIT\0"	---
10124	/* 24280 */ "G_BRJT\0"	---	10124	/* 24280 */ "G_BRJT\0"	---
10125	/* 24287 */ "BLT\0"	---	10125	/* 24287 */ "BLT\0"	---
10126	/* 24291 */ "G_EXTRACT_VECTOR_ELT\0"	---	10126	/* 24291 */ "G_EXTRACT_VECTOR_ELT\0"	---
10127	/* 24312 */ "G_INSERT_VECTOR_ELT\0"	---	10127	/* 24312 */ "G_INSERT_VECTOR_ELT\0"	---
10128	/* 24332 */ "SLT\0"	---	10128	/* 24332 */ "SLT\0"	---
10129	/* 24336 */ "TLT\0"	---	10129	/* 24336 */ "TLT\0"	---
10130	/* 24340 */ "PseudoDMULT\0"	---	10130	/* 24340 */ "PseudoDMULT\0"	---
10131	/* 24352 */ "PseudoMULT\0"	---	10131	/* 24352 */ "PseudoMULT\0"	---
10132	/* 24363 */ "DMT\0"	---	10132	/* 24363 */ "DMT\0"	---
10133	/* 24367 */ "EMT\0"	---	10133	/* 24367 */ "EMT\0"	---
10134	/* 24371 */ "G_FCONSTANT\0"	---	10134	/* 24371 */ "G_FCONSTANT\0"	---
10135	/* 24383 */ "G_CONSTANT\0"	---	10135	/* 24383 */ "G_CONSTANT\0"	---
10136	/* 24394 */ "STATEPOINT\0"	---	10136	/* 24394 */ "STATEPOINT\0"	---
10137	/* 24405 */ "PATCHPOINT\0"	---	10137	/* 24405 */ "PATCHPOINT\0"	---
10138	/* 24416 */ "G_PTRTOINT\0"	---	10138	/* 24416 */ "G_PTRTOINT\0"	---
10139	/* 24427 */ "G_FRINT\0"	---	10139	/* 24427 */ "G_FRINT\0"	---
10140	/* 24435 */ "G_INTRINSIC_LRINT\0"	---	10140	/* 24435 */ "G_INTRINSIC_LRINT\0"	---
10141	/* 24453 */ "G_FNEARBYINT\0"	---	10141	/* 24453 */ "G_FNEARBYINT\0"	---
10142	/* 24466 */ "G_VASTART\0"	---	10142	/* 24466 */ "G_VASTART\0"	---
10143	/* 24476 */ "LIFETIME_START\0"	---	10143	/* 24476 */ "LIFETIME_START\0"	---
10144	/* 24491 */ "G_INVOKE_REGION_START\0"	---	10144	/* 24491 */ "G_INVOKE_REGION_START\0"	---
10145	/* 24513 */ "G_INSERT\0"	---	10145	/* 24513 */ "G_INSERT\0"	---
10146	/* 24522 */ "G_FSQRT\0"	---	10146	/* 24522 */ "G_FSQRT\0"	---
10147	/* 24530 */ "G_STRICT_FSQRT\0"	---	10147	/* 24530 */ "G_STRICT_FSQRT\0"	---
10148	/* 24545 */ "G_BITCAST\0"	---	10148	/* 24545 */ "G_BITCAST\0"	---
10149	/* 24555 */ "G_ADDRSPACE_CAST\0"	---	10149	/* 24555 */ "G_ADDRSPACE_CAST\0"	---
10150	/* 24572 */ "DBG_VALUE_LIST\0"	---	10150	/* 24572 */ "DBG_VALUE_LIST\0"	---
10151	/* 24587 */ "GINVT\0"	---	10151	/* 24587 */ "GINVT\0"	---
10152	/* 24593 */ "DEXT\0"	---	10152	/* 24593 */ "DEXT\0"	---
10153	/* 24598 */ "G_FPEXT\0"	---	10153	/* 24598 */ "G_FPEXT\0"	---
10154	/* 24606 */ "G_SEXT\0"	---	10154	/* 24606 */ "G_SEXT\0"	---
10155	/* 24613 */ "G_ASSERT_SEXT\0"	---	10155	/* 24613 */ "G_ASSERT_SEXT\0"	---
10156	/* 24627 */ "G_ANYEXT\0"	---	10156	/* 24627 */ "G_ANYEXT\0"	---
10157	/* 24636 */ "G_ZEXT\0"	---	10157	/* 24636 */ "G_ZEXT\0"	---
10158	/* 24643 */ "G_ASSERT_ZEXT\0"	---	10158	/* 24643 */ "G_ASSERT_ZEXT\0"	---
10159	/* 24657 */ "PseudoMSUBU\0"	---	10159	/* 24657 */ "PseudoMSUBU\0"	---
10160	/* 24669 */ "PseudoMADDU\0"	---	10160	/* 24669 */ "PseudoMADDU\0"	---
10161	/* 24681 */ "DMODU\0"	---	10161	/* 24681 */ "DMODU\0"	---
10162	/* 24687 */ "BGEU\0"	---	10162	/* 24687 */ "BGEU\0"	---
10163	/* 24692 */ "SGEU\0"	---	10163	/* 24692 */ "SGEU\0"	---
10164	/* 24697 */ "TGEU\0"	---	10164	/* 24697 */ "TGEU\0"	---
10165	/* 24702 */ "BLEU\0"	---	10165	/* 24702 */ "BLEU\0"	---
10166	/* 24707 */ "SLEU\0"	---	10166	/* 24707 */ "SLEU\0"	---
10167	/* 24712 */ "DMUHU\0"	---	10167	/* 24712 */ "DMUHU\0"	---
10168	/* 24718 */ "TGEIU\0"	---	10168	/* 24718 */ "TGEIU\0"	---
10169	/* 24724 */ "TTLTIU\0"	---	10169	/* 24724 */ "TTLTIU\0"	---
10170	/* 24731 */ "V3MULU\0"	---	10170	/* 24731 */ "V3MULU\0"	---
10171	/* 24738 */ "DMULU\0"	---	10171	/* 24738 */ "DMULU\0"	---
10172	/* 24744 */ "VMULU\0"	---	10172	/* 24744 */ "VMULU\0"	---
10173	/* 24750 */ "DINSU\0"	---	10173	/* 24750 */ "DINSU\0"	---
10174	/* 24756 */ "BGTU\0"	---	10174	/* 24756 */ "BGTU\0"	---
10175	/* 24761 */ "BLTU\0"	---	10175	/* 24761 */ "BLTU\0"	---
10176	/* 24766 */ "TLTU\0"	---	10176	/* 24766 */ "TLTU\0"	---
10177	/* 24771 */ "DEXTU\0"	---	10177	/* 24771 */ "DEXTU\0"	---
10178	/* 24777 */ "DDIVU\0"	---	10178	/* 24777 */ "DDIVU\0"	---
10179	/* 24783 */ "DSRAV\0"	---	10179	/* 24783 */ "DSRAV\0"	---
10180	/* 24789 */ "BITREV\0"	---	10180	/* 24789 */ "BITREV\0"	---
10181	/* 24796 */ "DDIV\0"	---	10181	/* 24796 */ "DDIV\0"	---
10182	/* 24801 */ "G_FDIV\0"	---	10182	/* 24801 */ "G_FDIV\0"	---
10183	/* 24808 */ "G_STRICT_FDIV\0"	---	10183	/* 24808 */ "G_STRICT_FDIV\0"	---
10184	/* 24822 */ "PseudoDSDIV\0"	---	10184	/* 24822 */ "PseudoDSDIV\0"	---
10185	/* 24834 */ "G_SDIV\0"	---	10185	/* 24834 */ "G_SDIV\0"	---
10186	/* 24841 */ "PseudoSDIV\0"	---	10186	/* 24841 */ "PseudoSDIV\0"	---
10187	/* 24852 */ "PseudoDUDIV\0"	---	10187	/* 24852 */ "PseudoDUDIV\0"	---
10188	/* 24864 */ "G_UDIV\0"	---	10188	/* 24864 */ "G_UDIV\0"	---
10189	/* 24871 */ "PseudoUDIV\0"	---	10189	/* 24871 */ "PseudoUDIV\0"	---
10190	/* 24882 */ "DSLLV\0"	---	10190	/* 24882 */ "DSLLV\0"	---
10191	/* 24888 */ "DSRLV\0"	---	10191	/* 24888 */ "DSRLV\0"	---
10192	/* 24894 */ "TLBINV\0"	---	10192	/* 24894 */ "TLBINV\0"	---
10193	/* 24901 */ "TLBGINV\0"	---	10193	/* 24901 */ "TLBGINV\0"	---
10194	/* 24909 */ "SHILOV\0"	---	10194	/* 24909 */ "SHILOV\0"	---
10195	/* 24916 */ "EXTPDPV\0"	---	10195	/* 24916 */ "EXTPDPV\0"	---
10196	/* 24924 */ "EXTPV\0"	---	10196	/* 24924 */ "EXTPV\0"	---
10197	/* 24930 */ "DROTRV\0"	---	10197	/* 24930 */ "DROTRV\0"	---
10198	/* 24937 */ "INSV\0"	---	10198	/* 24937 */ "INSV\0"	---
10199	/* 24942 */ "AND_V\0"	---	10199	/* 24942 */ "AND_V\0"	---
10200	/* 24948 */ "MOVE_V\0"	---	10200	/* 24948 */ "MOVE_V\0"	---
10201	/* 24955 */ "BSEL_V\0"	---	10201	/* 24955 */ "BSEL_V\0"	---
10202	/* 24962 */ "NOR_V\0"	---	10202	/* 24962 */ "NOR_V\0"	---
10203	/* 24968 */ "XOR_V\0"	---	10203	/* 24968 */ "XOR_V\0"	---
10204	/* 24974 */ "BZ_V\0"	---	10204	/* 24974 */ "BZ_V\0"	---
10205	/* 24979 */ "BMZ_V\0"	---	10205	/* 24979 */ "BMZ_V\0"	---
10206	/* 24985 */ "BNZ_V\0"	---	10206	/* 24985 */ "BNZ_V\0"	---
10207	/* 24991 */ "BMNZ_V\0"	---	10207	/* 24991 */ "BMNZ_V\0"	---
10208	/* 24998 */ "CRC32W\0"	---	10208	/* 24998 */ "CRC32W\0"	---
10209	/* 25005 */ "CRC32CW\0"	---	10209	/* 25005 */ "CRC32CW\0"	---
10210	/* 25013 */ "LW\0"	---	10210	/* 25013 */ "LW\0"	---
10211	/* 25016 */ "G_FPOW\0"	---	10211	/* 25016 */ "G_FPOW\0"	---
10212	/* 25023 */ "SW\0"	---	10212	/* 25023 */ "SW\0"	---
10213	/* 25026 */ "PseudoCVT_D32_W\0"	---	10213	/* 25026 */ "PseudoCVT_D32_W\0"	---
10214	/* 25042 */ "FLOG2_W\0"	---	10214	/* 25042 */ "FLOG2_W\0"	---
10215	/* 25050 */ "FEXP2_W\0"	---	10215	/* 25050 */ "FEXP2_W\0"	---
10216	/* 25058 */ "PseudoCVT_D64_W\0"	---	10216	/* 25058 */ "PseudoCVT_D64_W\0"	---
10217	/* 25074 */ "SRA_W\0"	---	10217	/* 25074 */ "SRA_W\0"	---
10218	/* 25080 */ "ADD_A_W\0"	---	10218	/* 25080 */ "ADD_A_W\0"	---
10219	/* 25088 */ "FMIN_A_W\0"	---	10219	/* 25088 */ "FMIN_A_W\0"	---
10220	/* 25097 */ "ADDS_A_W\0"	---	10220	/* 25097 */ "ADDS_A_W\0"	---
10221	/* 25106 */ "FMAX_A_W\0"	---	10221	/* 25106 */ "FMAX_A_W\0"	---
10222	/* 25115 */ "FSUB_W\0"	---	10222	/* 25115 */ "FSUB_W\0"	---
10223	/* 25122 */ "FMSUB_W\0"	---	10223	/* 25122 */ "FMSUB_W\0"	---
10224	/* 25130 */ "NLOC_W\0"	---	10224	/* 25130 */ "NLOC_W\0"	---
10225	/* 25137 */ "NLZC_W\0"	---	10225	/* 25137 */ "NLZC_W\0"	---
10226	/* 25144 */ "FADD_W\0"	---	10226	/* 25144 */ "FADD_W\0"	---
10227	/* 25151 */ "FMADD_W\0"	---	10227	/* 25151 */ "FMADD_W\0"	---
10228	/* 25159 */ "SLD_W\0"	---	10228	/* 25159 */ "SLD_W\0"	---
10229	/* 25165 */ "PCKOD_W\0"	---	10229	/* 25165 */ "PCKOD_W\0"	---
10230	/* 25173 */ "ILVOD_W\0"	---	10230	/* 25173 */ "ILVOD_W\0"	---
10231	/* 25181 */ "FCLE_W\0"	---	10231	/* 25181 */ "FCLE_W\0"	---
10232	/* 25188 */ "FSLE_W\0"	---	10232	/* 25188 */ "FSLE_W\0"	---
10233	/* 25195 */ "FCULE_W\0"	---	10233	/* 25195 */ "FCULE_W\0"	---
10234	/* 25203 */ "FSULE_W\0"	---	10234	/* 25203 */ "FSULE_W\0"	---
10235	/* 25211 */ "FCNE_W\0"	---	10235	/* 25211 */ "FCNE_W\0"	---
10236	/* 25218 */ "FSNE_W\0"	---	10236	/* 25218 */ "FSNE_W\0"	---
10237	/* 25225 */ "FCUNE_W\0"	---	10237	/* 25225 */ "FCUNE_W\0"	---
10238	/* 25233 */ "FSUNE_W\0"	---	10238	/* 25233 */ "FSUNE_W\0"	---
10239	/* 25241 */ "INSVE_W\0"	---	10239	/* 25241 */ "INSVE_W\0"	---
10240	/* 25249 */ "FCAF_W\0"	---	10240	/* 25249 */ "FCAF_W\0"	---
10241	/* 25256 */ "FSAF_W\0"	---	10241	/* 25256 */ "FSAF_W\0"	---
10242	/* 25263 */ "VSHF_W\0"	---	10242	/* 25263 */ "VSHF_W\0"	---
10243	/* 25270 */ "BNEG_W\0"	---	10243	/* 25270 */ "BNEG_W\0"	---
10244	/* 25277 */ "PRECR_SRA_PH_W\0"	---	10244	/* 25277 */ "PRECR_SRA_PH_W\0"	---
10245	/* 25292 */ "PRECRQ_PH_W\0"	---	10245	/* 25292 */ "PRECRQ_PH_W\0"	---
10246	/* 25304 */ "PRECR_SRA_R_PH_W\0"	---	10246	/* 25304 */ "PRECR_SRA_R_PH_W\0"	---
10247	/* 25321 */ "PRECRQ_RS_PH_W\0"	---	10247	/* 25321 */ "PRECRQ_RS_PH_W\0"	---
10248	/* 25336 */ "SUBQH_W\0"	---	10248	/* 25336 */ "SUBQH_W\0"	---
10249	/* 25344 */ "ADDQH_W\0"	---	10249	/* 25344 */ "ADDQH_W\0"	---
10250	/* 25352 */ "SRAI_W\0"	---	10250	/* 25352 */ "SRAI_W\0"	---
10251	/* 25359 */ "SLDI_W\0"	---	10251	/* 25359 */ "SLDI_W\0"	---
10252	/* 25366 */ "BNEGI_W\0"	---	10252	/* 25366 */ "BNEGI_W\0"	---
10253	/* 25374 */ "SLLI_W\0"	---	10253	/* 25374 */ "SLLI_W\0"	---
10254	/* 25381 */ "SRLI_W\0"	---	10254	/* 25381 */ "SRLI_W\0"	---
10255	/* 25388 */ "BINSLI_W\0"	---	10255	/* 25388 */ "BINSLI_W\0"	---
10256	/* 25397 */ "CEQI_W\0"	---	10256	/* 25397 */ "CEQI_W\0"	---
10257	/* 25404 */ "SRARI_W\0"	---	10257	/* 25404 */ "SRARI_W\0"	---
10258	/* 25412 */ "BCLRI_W\0"	---	10258	/* 25412 */ "BCLRI_W\0"	---
10259	/* 25420 */ "SRLRI_W\0"	---	10259	/* 25420 */ "SRLRI_W\0"	---
10260	/* 25428 */ "BINSRI_W\0"	---	10260	/* 25428 */ "BINSRI_W\0"	---
10261	/* 25437 */ "SPLATI_W\0"	---	10261	/* 25437 */ "SPLATI_W\0"	---
10262	/* 25446 */ "BSETI_W\0"	---	10262	/* 25446 */ "BSETI_W\0"	---
10263	/* 25454 */ "SUBVI_W\0"	---	10263	/* 25454 */ "SUBVI_W\0"	---
10264	/* 25462 */ "ADDVI_W\0"	---	10264	/* 25462 */ "ADDVI_W\0"	---
10265	/* 25470 */ "FILL_W\0"	---	10265	/* 25470 */ "FILL_W\0"	---
10266	/* 25477 */ "SLL_W\0"	---	10266	/* 25477 */ "SLL_W\0"	---
10267	/* 25483 */ "FEXUPL_W\0"	---	10267	/* 25483 */ "FEXUPL_W\0"	---
10268	/* 25492 */ "FFQL_W\0"	---	10268	/* 25492 */ "FFQL_W\0"	---
10269	/* 25499 */ "SRL_W\0"	---	10269	/* 25499 */ "SRL_W\0"	---
10270	/* 25505 */ "BINSL_W\0"	---	10270	/* 25505 */ "BINSL_W\0"	---
10271	/* 25513 */ "FMUL_W\0"	---	10271	/* 25513 */ "FMUL_W\0"	---
10272	/* 25520 */ "ILVL_W\0"	---	10272	/* 25520 */ "ILVL_W\0"	---
10273	/* 25527 */ "DPAQ_SA_L_W\0"	---	10273	/* 25527 */ "DPAQ_SA_L_W\0"	---
10274	/* 25539 */ "DPSQ_SA_L_W\0"	---	10274	/* 25539 */ "DPSQ_SA_L_W\0"	---
10275	/* 25551 */ "FMIN_W\0"	---	10275	/* 25551 */ "FMIN_W\0"	---
10276	/* 25558 */ "FCUN_W\0"	---	10276	/* 25558 */ "FCUN_W\0"	---
10277	/* 25565 */ "FSUN_W\0"	---	10277	/* 25565 */ "FSUN_W\0"	---
10278	/* 25572 */ "FEXDO_W\0"	---	10278	/* 25572 */ "FEXDO_W\0"	---
10279	/* 25580 */ "FRCP_W\0"	---	10279	/* 25580 */ "FRCP_W\0"	---
10280	/* 25587 */ "FCEQ_W\0"	---	10280	/* 25587 */ "FCEQ_W\0"	---
10281	/* 25594 */ "FSEQ_W\0"	---	10281	/* 25594 */ "FSEQ_W\0"	---
10282	/* 25601 */ "FCUEQ_W\0"	---	10282	/* 25601 */ "FCUEQ_W\0"	---
10283	/* 25609 */ "FSUEQ_W\0"	---	10283	/* 25609 */ "FSUEQ_W\0"	---
10284	/* 25617 */ "FTQ_W\0"	---	10284	/* 25617 */ "FTQ_W\0"	---
10285	/* 25623 */ "MSUB_Q_W\0"	---	10285	/* 25623 */ "MSUB_Q_W\0"	---
10286	/* 25632 */ "MADD_Q_W\0"	---	10286	/* 25632 */ "MADD_Q_W\0"	---
10287	/* 25641 */ "MUL_Q_W\0"	---	10287	/* 25641 */ "MUL_Q_W\0"	---
10288	/* 25649 */ "MSUBR_Q_W\0"	---	10288	/* 25649 */ "MSUBR_Q_W\0"	---
10289	/* 25659 */ "MADDR_Q_W\0"	---	10289	/* 25659 */ "MADDR_Q_W\0"	---
10290	/* 25669 */ "MULR_Q_W\0"	---	10290	/* 25669 */ "MULR_Q_W\0"	---
10291	/* 25678 */ "SRAR_W\0"	---	10291	/* 25678 */ "SRAR_W\0"	---
10292	/* 25685 */ "LDR_W\0"	---	10292	/* 25685 */ "LDR_W\0"	---
10293	/* 25691 */ "BCLR_W\0"	---	10293	/* 25691 */ "BCLR_W\0"	---
10294	/* 25698 */ "SRLR_W\0"	---	10294	/* 25698 */ "SRLR_W\0"	---
10295	/* 25705 */ "FCOR_W\0"	---	10295	/* 25705 */ "FCOR_W\0"	---
10296	/* 25712 */ "FSOR_W\0"	---	10296	/* 25712 */ "FSOR_W\0"	---
10297	/* 25719 */ "FEXUPR_W\0"	---	10297	/* 25719 */ "FEXUPR_W\0"	---
10298	/* 25728 */ "FFQR_W\0"	---	10298	/* 25728 */ "FFQR_W\0"	---
10299	/* 25735 */ "BINSR_W\0"	---	10299	/* 25735 */ "BINSR_W\0"	---
10300	/* 25743 */ "STR_W\0"	---	10300	/* 25743 */ "STR_W\0"	---
10301	/* 25749 */ "EXTR_W\0"	---	10301	/* 25749 */ "EXTR_W\0"	---
10302	/* 25756 */ "ILVR_W\0"	---	10302	/* 25756 */ "ILVR_W\0"	---
10303	/* 25763 */ "SHRA_R_W\0"	---	10303	/* 25763 */ "SHRA_R_W\0"	---
10304	/* 25772 */ "SUBQH_R_W\0"	---	10304	/* 25772 */ "SUBQH_R_W\0"	---
10305	/* 25782 */ "ADDQH_R_W\0"	---	10305	/* 25782 */ "ADDQH_R_W\0"	---
10306	/* 25792 */ "EXTR_R_W\0"	---	10306	/* 25792 */ "EXTR_R_W\0"	---
10307	/* 25801 */ "SHRAV_R_W\0"	---	10307	/* 25801 */ "SHRAV_R_W\0"	---
10308	/* 25811 */ "EXTRV_R_W\0"	---	10308	/* 25811 */ "EXTRV_R_W\0"	---
10309	/* 25821 */ "FABS_W\0"	---	10309	/* 25821 */ "FABS_W\0"	---
10310	/* 25828 */ "MULQ_RS_W\0"	---	10310	/* 25828 */ "MULQ_RS_W\0"	---
10311	/* 25838 */ "EXTR_RS_W\0"	---	10311	/* 25838 */ "EXTR_RS_W\0"	---
10312	/* 25848 */ "EXTRV_RS_W\0"	---	10312	/* 25848 */ "EXTRV_RS_W\0"	---
10313	/* 25859 */ "FCLASS_W\0"	---	10313	/* 25859 */ "FCLASS_W\0"	---
10314	/* 25868 */ "ASUB_S_W\0"	---	10314	/* 25868 */ "ASUB_S_W\0"	---
10315	/* 25877 */ "HSUB_S_W\0"	---	10315	/* 25877 */ "HSUB_S_W\0"	---
10316	/* 25886 */ "DPSUB_S_W\0"	---	10316	/* 25886 */ "DPSUB_S_W\0"	---
10317	/* 25896 */ "FTRUNC_S_W\0"	---	10317	/* 25896 */ "FTRUNC_S_W\0"	---
10318	/* 25907 */ "HADD_S_W\0"	---	10318	/* 25907 */ "HADD_S_W\0"	---
10319	/* 25916 */ "DPADD_S_W\0"	---	10319	/* 25916 */ "DPADD_S_W\0"	---
10320	/* 25926 */ "MOD_S_W\0"	---	10320	/* 25926 */ "MOD_S_W\0"	---
10321	/* 25934 */ "CLE_S_W\0"	---	10321	/* 25934 */ "CLE_S_W\0"	---
10322	/* 25942 */ "AVE_S_W\0"	---	10322	/* 25942 */ "AVE_S_W\0"	---
10323	/* 25950 */ "CLEI_S_W\0"	---	10323	/* 25950 */ "CLEI_S_W\0"	---
10324	/* 25959 */ "MINI_S_W\0"	---	10324	/* 25959 */ "MINI_S_W\0"	---
10325	/* 25968 */ "CLTI_S_W\0"	---	10325	/* 25968 */ "CLTI_S_W\0"	---
10326	/* 25977 */ "MAXI_S_W\0"	---	10326	/* 25977 */ "MAXI_S_W\0"	---
10327	/* 25986 */ "SHLL_S_W\0"	---	10327	/* 25986 */ "SHLL_S_W\0"	---
10328	/* 25995 */ "MIN_S_W\0"	---	10328	/* 25995 */ "MIN_S_W\0"	---
10329	/* 26003 */ "DOTP_S_W\0"	---	10329	/* 26003 */ "DOTP_S_W\0"	---
10330	/* 26012 */ "SUBQ_S_W\0"	---	10330	/* 26012 */ "SUBQ_S_W\0"	---
10331	/* 26021 */ "ADDQ_S_W\0"	---	10331	/* 26021 */ "ADDQ_S_W\0"	---
10332	/* 26030 */ "MULQ_S_W\0"	---	10332	/* 26030 */ "MULQ_S_W\0"	---
10333	/* 26039 */ "ABSQ_S_W\0"	---	10333	/* 26039 */ "ABSQ_S_W\0"	---
10334	/* 26048 */ "AVER_S_W\0"	---	10334	/* 26048 */ "AVER_S_W\0"	---
10335	/* 26057 */ "SUBS_S_W\0"	---	10335	/* 26057 */ "SUBS_S_W\0"	---
10336	/* 26066 */ "ADDS_S_W\0"	---	10336	/* 26066 */ "ADDS_S_W\0"	---
10337	/* 26075 */ "SAT_S_W\0"	---	10337	/* 26075 */ "SAT_S_W\0"	---
10338	/* 26083 */ "CLT_S_W\0"	---	10338	/* 26083 */ "CLT_S_W\0"	---
10339	/* 26091 */ "FFINT_S_W\0"	---	10339	/* 26091 */ "FFINT_S_W\0"	---
10340	/* 26101 */ "FTINT_S_W\0"	---	10340	/* 26101 */ "FTINT_S_W\0"	---
10341	/* 26111 */ "PseudoCVT_S_W\0"	---	10341	/* 26111 */ "PseudoCVT_S_W\0"	---
10342	/* 26125 */ "SUBSUU_S_W\0"	---	10342	/* 26125 */ "SUBSUU_S_W\0"	---
10343	/* 26136 */ "DIV_S_W\0"	---	10343	/* 26136 */ "DIV_S_W\0"	---
10344	/* 26144 */ "SHLLV_S_W\0"	---	10344	/* 26144 */ "SHLLV_S_W\0"	---
10345	/* 26154 */ "MAX_S_W\0"	---	10345	/* 26154 */ "MAX_S_W\0"	---
10346	/* 26162 */ "COPY_S_W\0"	---	10346	/* 26162 */ "COPY_S_W\0"	---
10347	/* 26171 */ "SPLAT_W\0"	---	10347	/* 26171 */ "SPLAT_W\0"	---
10348	/* 26179 */ "BSET_W\0"	---	10348	/* 26179 */ "BSET_W\0"	---
10349	/* 26186 */ "FCLT_W\0"	---	10349	/* 26186 */ "FCLT_W\0"	---
10350	/* 26193 */ "FSLT_W\0"	---	10350	/* 26193 */ "FSLT_W\0"	---
10351	/* 26200 */ "FCULT_W\0"	---	10351	/* 26200 */ "FCULT_W\0"	---
10352	/* 26208 */ "FSULT_W\0"	---	10352	/* 26208 */ "FSULT_W\0"	---
10353	/* 26216 */ "PCNT_W\0"	---	10353	/* 26216 */ "PCNT_W\0"	---
10354	/* 26223 */ "FRINT_W\0"	---	10354	/* 26223 */ "FRINT_W\0"	---
10355	/* 26231 */ "INSERT_W\0"	---	10355	/* 26231 */ "INSERT_W\0"	---
10356	/* 26240 */ "FSQRT_W\0"	---	10356	/* 26240 */ "FSQRT_W\0"	---
10357	/* 26248 */ "FRSQRT_W\0"	---	10357	/* 26248 */ "FRSQRT_W\0"	---
10358	/* 26257 */ "ST_W\0"	---	10358	/* 26257 */ "ST_W\0"	---
10359	/* 26262 */ "ASUB_U_W\0"	---	10359	/* 26262 */ "ASUB_U_W\0"	---
10360	/* 26271 */ "HSUB_U_W\0"	---	10360	/* 26271 */ "HSUB_U_W\0"	---
10361	/* 26280 */ "DPSUB_U_W\0"	---	10361	/* 26280 */ "DPSUB_U_W\0"	---
10362	/* 26290 */ "FTRUNC_U_W\0"	---	10362	/* 26290 */ "FTRUNC_U_W\0"	---
10363	/* 26301 */ "HADD_U_W\0"	---	10363	/* 26301 */ "HADD_U_W\0"	---
10364	/* 26310 */ "DPADD_U_W\0"	---	10364	/* 26310 */ "DPADD_U_W\0"	---
10365	/* 26320 */ "MOD_U_W\0"	---	10365	/* 26320 */ "MOD_U_W\0"	---
10366	/* 26328 */ "CLE_U_W\0"	---	10366	/* 26328 */ "CLE_U_W\0"	---
10367	/* 26336 */ "AVE_U_W\0"	---	10367	/* 26336 */ "AVE_U_W\0"	---
10368	/* 26344 */ "CLEI_U_W\0"	---	10368	/* 26344 */ "CLEI_U_W\0"	---
10369	/* 26353 */ "MINI_U_W\0"	---	10369	/* 26353 */ "MINI_U_W\0"	---
10370	/* 26362 */ "CLTI_U_W\0"	---	10370	/* 26362 */ "CLTI_U_W\0"	---
10371	/* 26371 */ "MAXI_U_W\0"	---	10371	/* 26371 */ "MAXI_U_W\0"	---
10372	/* 26380 */ "MIN_U_W\0"	---	10372	/* 26380 */ "MIN_U_W\0"	---
10373	/* 26388 */ "DOTP_U_W\0"	---	10373	/* 26388 */ "DOTP_U_W\0"	---
10374	/* 26397 */ "AVER_U_W\0"	---	10374	/* 26397 */ "AVER_U_W\0"	---
10375	/* 26406 */ "SUBS_U_W\0"	---	10375	/* 26406 */ "SUBS_U_W\0"	---
10376	/* 26415 */ "ADDS_U_W\0"	---	10376	/* 26415 */ "ADDS_U_W\0"	---
10377	/* 26424 */ "SUBSUS_U_W\0"	---	10377	/* 26424 */ "SUBSUS_U_W\0"	---
10378	/* 26435 */ "SAT_U_W\0"	---	10378	/* 26435 */ "SAT_U_W\0"	---
10379	/* 26443 */ "CLT_U_W\0"	---	10379	/* 26443 */ "CLT_U_W\0"	---
10380	/* 26451 */ "FFINT_U_W\0"	---	10380	/* 26451 */ "FFINT_U_W\0"	---
10381	/* 26461 */ "FTINT_U_W\0"	---	10381	/* 26461 */ "FTINT_U_W\0"	---
10382	/* 26471 */ "DIV_U_W\0"	---	10382	/* 26471 */ "DIV_U_W\0"	---
10383	/* 26479 */ "MAX_U_W\0"	---	10383	/* 26479 */ "MAX_U_W\0"	---
10384	/* 26487 */ "COPY_U_W\0"	---	10384	/* 26487 */ "COPY_U_W\0"	---
10385	/* 26496 */ "MSUBV_W\0"	---	10385	/* 26496 */ "MSUBV_W\0"	---
10386	/* 26504 */ "MADDV_W\0"	---	10386	/* 26504 */ "MADDV_W\0"	---
10387	/* 26512 */ "PCKEV_W\0"	---	10387	/* 26512 */ "PCKEV_W\0"	---
10388	/* 26520 */ "ILVEV_W\0"	---	10388	/* 26520 */ "ILVEV_W\0"	---
10389	/* 26528 */ "FDIV_W\0"	---	10389	/* 26528 */ "FDIV_W\0"	---
10390	/* 26535 */ "MULV_W\0"	---	10390	/* 26535 */ "MULV_W\0"	---
10391	/* 26542 */ "EXTRV_W\0"	---	10391	/* 26542 */ "EXTRV_W\0"	---
10392	/* 26550 */ "FMAX_W\0"	---	10392	/* 26550 */ "FMAX_W\0"	---
10393	/* 26557 */ "BZ_W\0"	---	10393	/* 26557 */ "BZ_W\0"	---
10394	/* 26562 */ "BNZ_W\0"	---	10394	/* 26562 */ "BNZ_W\0"	---
10395	/* 26568 */ "G_VECREDUCE_FMAX\0"	---	10395	/* 26568 */ "G_VECREDUCE_FMAX\0"	---
10396	/* 26585 */ "G_ATOMICRMW_FMAX\0"	---	10396	/* 26585 */ "G_ATOMICRMW_FMAX\0"	---
10397	/* 26602 */ "G_VECREDUCE_SMAX\0"	---	10397	/* 26602 */ "G_VECREDUCE_SMAX\0"	---
10398	/* 26619 */ "G_SMAX\0"	---	10398	/* 26619 */ "G_SMAX\0"	---
10399	/* 26626 */ "G_VECREDUCE_UMAX\0"	---	10399	/* 26626 */ "G_VECREDUCE_UMAX\0"	---
10400	/* 26643 */ "G_UMAX\0"	---	10400	/* 26643 */ "G_UMAX\0"	---
10401	/* 26650 */ "G_ATOMICRMW_UMAX\0"	---	10401	/* 26650 */ "G_ATOMICRMW_UMAX\0"	---
10402	/* 26667 */ "G_ATOMICRMW_MAX\0"	---	10402	/* 26667 */ "G_ATOMICRMW_MAX\0"	---
10403	/* 26683 */ "MFTACX\0"	---	10403	/* 26683 */ "MFTACX\0"	---
10404	/* 26690 */ "MTTACX\0"	---	10404	/* 26690 */ "MTTACX\0"	---
10405	/* 26697 */ "G_FRAME_INDEX\0"	---	10405	/* 26697 */ "G_FRAME_INDEX\0"	---
10406	/* 26711 */ "G_SBFX\0"	---	10406	/* 26711 */ "G_SBFX\0"	---
10407	/* 26718 */ "G_UBFX\0"	---	10407	/* 26718 */ "G_UBFX\0"	---
10408	/* 26725 */ "LHX\0"	---	10408	/* 26725 */ "LHX\0"	---
10409	/* 26729 */ "G_SMULFIX\0"	---	10409	/* 26729 */ "G_SMULFIX\0"	---
10410	/* 26739 */ "G_UMULFIX\0"	---	10410	/* 26739 */ "G_UMULFIX\0"	---
10411	/* 26749 */ "G_SDIVFIX\0"	---	10411	/* 26749 */ "G_SDIVFIX\0"	---
10412	/* 26759 */ "G_UDIVFIX\0"	---	10412	/* 26759 */ "G_UDIVFIX\0"	---
10413	/* 26769 */ "JALX\0"	---	10413	/* 26769 */ "JALX\0"	---
10414	/* 26774 */ "LBUX\0"	---	10414	/* 26774 */ "LBUX\0"	---
10415	/* 26779 */ "LWX\0"	---	10415	/* 26779 */ "LWX\0"	---
10416	/* 26783 */ "G_MEMCPY\0"	---	10416	/* 26783 */ "G_MEMCPY\0"	---
10417	/* 26792 */ "COPY\0"	---	10417	/* 26792 */ "COPY\0"	---
10418	/* 26797 */ "CONSTPOOL_ENTRY\0"	---	10418	/* 26797 */ "CONSTPOOL_ENTRY\0"	---
10419	/* 26813 */ "BGEZ\0"	---	10419	/* 26813 */ "BGEZ\0"	---
10420	/* 26818 */ "BLEZ\0"	---	10420	/* 26818 */ "BLEZ\0"	---
10421	/* 26823 */ "BC1NEZ\0"	---	10421	/* 26823 */ "BC1NEZ\0"	---
10422	/* 26830 */ "BC2NEZ\0"	---	10422	/* 26830 */ "BC2NEZ\0"	---
10423	/* 26837 */ "SELNEZ\0"	---	10423	/* 26837 */ "SELNEZ\0"	---
10424	/* 26844 */ "DCLZ\0"	---	10424	/* 26844 */ "DCLZ\0"	---
10425	/* 26849 */ "G_CTLZ\0"	---	10425	/* 26849 */ "G_CTLZ\0"	---
10426	/* 26856 */ "BC1EQZ\0"	---	10426	/* 26856 */ "BC1EQZ\0"	---
10427	/* 26863 */ "BC2EQZ\0"	---	10427	/* 26863 */ "BC2EQZ\0"	---
10428	/* 26870 */ "SELEQZ\0"	---	10428	/* 26870 */ "SELEQZ\0"	---
10429	/* 26877 */ "BGTZ\0"	---	10429	/* 26877 */ "BGTZ\0"	---
10430	/* 26882 */ "BLTZ\0"	---	10430	/* 26882 */ "BLTZ\0"	---
10431	/* 26887 */ "G_CTTZ\0"	---	10431	/* 26887 */ "G_CTTZ\0"	---
10432	/* 26894 */ "SelBneZ\0"	---	10432	/* 26894 */ "SelBneZ\0"	---
10433	/* 26902 */ "SelBeqZ\0"	---	10433	/* 26902 */ "SelBeqZ\0"	---
10434	/* 26910 */ "JalOneReg\0"	---	10434	/* 26910 */ "JalOneReg\0"	---
10435	/* 26920 */ "JalTwoReg\0"	---	10435	/* 26920 */ "JalTwoReg\0"	---
10436	/* 26930 */ "PseudoIndirectHazardBranch\0"	---	10436	/* 26930 */ "PseudoIndirectHazardBranch\0"	---
10437	/* 26957 */ "PseudoIndirectBranch\0"	---	10437	/* 26957 */ "PseudoIndirectBranch\0"	---
10438	/* 26978 */ "Ulh\0"	---	10438	/* 26978 */ "Ulh\0"	---
10439	/* 26982 */ "Ush\0"	---	10439	/* 26982 */ "Ush\0"	---
10440	/* 26986 */ "DADDi\0"	---	10440	/* 26986 */ "DADDi\0"	---
10441	/* 26992 */ "ANDi\0"	---	10441	/* 26992 */ "ANDi\0"	---
10442	/* 26997 */ "SNEi\0"	---	10442	/* 26997 */ "SNEi\0"	---
10443	/* 27002 */ "SEQi\0"	---	10443	/* 27002 */ "SEQi\0"	---
10444	/* 27007 */ "XORi\0"	---	10444	/* 27007 */ "XORi\0"	---
10445	/* 27012 */ "SLTi\0"	---	10445	/* 27012 */ "SLTi\0"	---
10446	/* 27017 */ "LONG_BRANCH_LUi\0"	---	10446	/* 27017 */ "LONG_BRANCH_LUi\0"	---
10447	/* 27033 */ "SelTBtneZCmpi\0"	---	10447	/* 27033 */ "SelTBtneZCmpi\0"	---
10448	/* 27047 */ "SelTBteqZCmpi\0"	---	10448	/* 27047 */ "SelTBteqZCmpi\0"	---
10449	/* 27061 */ "SelTBtneZSlti\0"	---	10449	/* 27061 */ "SelTBtneZSlti\0"	---
10450	/* 27075 */ "SelTBteqZSlti\0"	---	10450	/* 27075 */ "SelTBteqZSlti\0"	---
10451	/* 27089 */ "SGEImm\0"	---	10451	/* 27089 */ "SGEImm\0"	---
10452	/* 27096 */ "SLEImm\0"	---	10452	/* 27096 */ "SLEImm\0"	---
10453	/* 27103 */ "DROLImm\0"	---	10453	/* 27103 */ "DROLImm\0"	---
10454	/* 27111 */ "NORImm\0"	---	10454	/* 27111 */ "NORImm\0"	---
10455	/* 27118 */ "DRORImm\0"	---	10455	/* 27118 */ "DRORImm\0"	---
10456	/* 27126 */ "SGTImm\0"	---	10456	/* 27126 */ "SGTImm\0"	---
10457	/* 27133 */ "SGEUImm\0"	---	10457	/* 27133 */ "SGEUImm\0"	---
10458	/* 27141 */ "SLEUImm\0"	---	10458	/* 27141 */ "SLEUImm\0"	---
10459	/* 27149 */ "SGTUImm\0"	---	10459	/* 27149 */ "SGTUImm\0"	---
10460	/* 27157 */ "BneImm\0"	---	10460	/* 27157 */ "BneImm\0"	---
10461	/* 27164 */ "BeqImm\0"	---	10461	/* 27164 */ "BeqImm\0"	---
10462	/* 27171 */ "PseudoReturn\0"	---	10462	/* 27171 */ "PseudoReturn\0"	---
10463	/* 27184 */ "JALRHB64Pseudo\0"	---	10463	/* 27184 */ "JALRHB64Pseudo\0"	---
10464	/* 27199 */ "JALR64Pseudo\0"	---	10464	/* 27199 */ "JALR64Pseudo\0"	---
10465	/* 27212 */ "JALRHBPseudo\0"	---	10465	/* 27212 */ "JALRHBPseudo\0"	---
10466	/* 27225 */ "JALRPseudo\0"	---	10466	/* 27225 */ "JALRPseudo\0"	---
10467	/* 27236 */ "B_MMR6_Pseudo\0"	---	10467	/* 27236 */ "B_MMR6_Pseudo\0"	---
10468	/* 27250 */ "B_MM_Pseudo\0"	---	10468	/* 27250 */ "B_MM_Pseudo\0"	---
10469	/* 27262 */ "SDIV_MM_Pseudo\0"	---	10469	/* 27262 */ "SDIV_MM_Pseudo\0"	---
10470	/* 27277 */ "UDIV_MM_Pseudo\0"	---	10470	/* 27277 */ "UDIV_MM_Pseudo\0"	---
10471	/* 27292 */ "LDMacro\0"	---	10471	/* 27292 */ "LDMacro\0"	---
10472	/* 27300 */ "SDMacro\0"	---	10472	/* 27300 */ "SDMacro\0"	---
10473	/* 27308 */ "SNEMacro\0"	---	10473	/* 27308 */ "SNEMacro\0"	---
10474	/* 27317 */ "SNEIMacro\0"	---	10474	/* 27317 */ "SNEIMacro\0"	---
10475	/* 27327 */ "SEQIMacro\0"	---	10475	/* 27327 */ "SEQIMacro\0"	---
10476	/* 27337 */ "DSRemIMacro\0"	---	10476	/* 27337 */ "DSRemIMacro\0"	---
10477	/* 27349 */ "DURemIMacro\0"	---	10477	/* 27349 */ "DURemIMacro\0"	---
10478	/* 27361 */ "DSDivIMacro\0"	---	10478	/* 27361 */ "DSDivIMacro\0"	---
10479	/* 27373 */ "DUDivIMacro\0"	---	10479	/* 27373 */ "DUDivIMacro\0"	---
10480	/* 27385 */ "DMULMacro\0"	---	10480	/* 27385 */ "DMULMacro\0"	---
10481	/* 27395 */ "DMULOMacro\0"	---	10481	/* 27395 */ "DMULOMacro\0"	---
10482	/* 27406 */ "SEQMacro\0"	---	10482	/* 27406 */ "SEQMacro\0"	---
10483	/* 27415 */ "ABSMacro\0"	---	10483	/* 27415 */ "ABSMacro\0"	---
10484	/* 27424 */ "DMULOUMacro\0"	---	10484	/* 27424 */ "DMULOUMacro\0"	---
10485	/* 27436 */ "DSRemMacro\0"	---	10485	/* 27436 */ "DSRemMacro\0"	---
10486	/* 27447 */ "DURemMacro\0"	---	10486	/* 27447 */ "DURemMacro\0"	---
10487	/* 27458 */ "BGEImmMacro\0"	---	10487	/* 27458 */ "BGEImmMacro\0"	---
10488	/* 27470 */ "BLEImmMacro\0"	---	10488	/* 27470 */ "BLEImmMacro\0"	---
10489	/* 27482 */ "BGELImmMacro\0"	---	10489	/* 27482 */ "BGELImmMacro\0"	---
10490	/* 27495 */ "BLELImmMacro\0"	---	10490	/* 27495 */ "BLELImmMacro\0"	---
10491	/* 27508 */ "BNELImmMacro\0"	---	10491	/* 27508 */ "BNELImmMacro\0"	---
10492	/* 27521 */ "BEQLImmMacro\0"	---	10492	/* 27521 */ "BEQLImmMacro\0"	---
10493	/* 27534 */ "BGTLImmMacro\0"	---	10493	/* 27534 */ "BGTLImmMacro\0"	---
10494	/* 27547 */ "BLTLImmMacro\0"	---	10494	/* 27547 */ "BLTLImmMacro\0"	---
10495	/* 27560 */ "BGEULImmMacro\0"	---	10495	/* 27560 */ "BGEULImmMacro\0"	---
10496	/* 27574 */ "BLEULImmMacro\0"	---	10496	/* 27574 */ "BLEULImmMacro\0"	---
10497	/* 27588 */ "DMULImmMacro\0"	---	10497	/* 27588 */ "DMULImmMacro\0"	---
10498	/* 27601 */ "BGTULImmMacro\0"	---	10498	/* 27601 */ "BGTULImmMacro\0"	---
10499	/* 27615 */ "BLTULImmMacro\0"	---	10499	/* 27615 */ "BLTULImmMacro\0"	---
10500	/* 27629 */ "BGTImmMacro\0"	---	10500	/* 27629 */ "BGTImmMacro\0"	---
10501	/* 27641 */ "BLTImmMacro\0"	---	10501	/* 27641 */ "BLTImmMacro\0"	---
10502	/* 27653 */ "BGEUImmMacro\0"	---	10502	/* 27653 */ "BGEUImmMacro\0"	---
10503	/* 27666 */ "BLEUImmMacro\0"	---	10503	/* 27666 */ "BLEUImmMacro\0"	---
10504	/* 27679 */ "BGTUImmMacro\0"	---	10504	/* 27679 */ "BGTUImmMacro\0"	---
10505	/* 27692 */ "BLTUImmMacro\0"	---	10505	/* 27692 */ "BLTUImmMacro\0"	---
10506	/* 27705 */ "DSDivMacro\0"	---	10506	/* 27705 */ "DSDivMacro\0"	---
10507	/* 27716 */ "DUDivMacro\0"	---	10507	/* 27716 */ "DUDivMacro\0"	---
10508	/* 27727 */ "LONG_BRANCH_LUi2Op\0"	---	10508	/* 27727 */ "LONG_BRANCH_LUi2Op\0"	---
10509	/* 27746 */ "LONG_BRANCH_DADDiu2Op\0"	---	10509	/* 27746 */ "LONG_BRANCH_DADDiu2Op\0"	---
10510	/* 27768 */ "LONG_BRANCH_ADDiu2Op\0"	---	10510	/* 27768 */ "LONG_BRANCH_ADDiu2Op\0"	---
10511	/* 27789 */ "SelTBtneZCmp\0"	---	10511	/* 27789 */ "SelTBtneZCmp\0"	---
10512	/* 27802 */ "SelTBteqZCmp\0"	---	10512	/* 27802 */ "SelTBteqZCmp\0"	---
10513	/* 27815 */ "SaaAddr\0"	---	10513	/* 27815 */ "SaaAddr\0"	---
10514	/* 27823 */ "SaadAddr\0"	---	10514	/* 27823 */ "SaadAddr\0"	---
10515	/* 27832 */ "ERet\0"	---	10515	/* 27832 */ "ERet\0"	---
10516	/* 27837 */ "SelTBtneZSlt\0"	---	10516	/* 27837 */ "SelTBtneZSlt\0"	---
10517	/* 27850 */ "SelTBteqZSlt\0"	---	10517	/* 27850 */ "SelTBteqZSlt\0"	---
10518	/* 27863 */ "LBu\0"	---	10518	/* 27863 */ "LBu\0"	---
10519	/* 27867 */ "DSUBu\0"	---	10519	/* 27867 */ "DSUBu\0"	---
10520	/* 27873 */ "BADDu\0"	---	10520	/* 27873 */ "BADDu\0"	---
10521	/* 27879 */ "DADDu\0"	---	10521	/* 27879 */ "DADDu\0"	---
10522	/* 27885 */ "LHu\0"	---	10522	/* 27885 */ "LHu\0"	---
10523	/* 27889 */ "SLTu\0"	---	10523	/* 27889 */ "SLTu\0"	---
10524	/* 27894 */ "PseudoDMULTu\0"	---	10524	/* 27894 */ "PseudoDMULTu\0"	---
10525	/* 27907 */ "PseudoMULTu\0"	---	10525	/* 27907 */ "PseudoMULTu\0"	---
10526	/* 27919 */ "LWu\0"	---	10526	/* 27919 */ "LWu\0"	---
10527	/* 27923 */ "Ulhu\0"	---	10527	/* 27923 */ "Ulhu\0"	---
10528	/* 27928 */ "LONG_BRANCH_DADDiu\0"	---	10528	/* 27928 */ "LONG_BRANCH_DADDiu\0"	---
10529	/* 27947 */ "LEA_ADDiu\0"	---	10529	/* 27947 */ "LEA_ADDiu\0"	---
10530	/* 27957 */ "LONG_BRANCH_ADDiu\0"	---	10530	/* 27957 */ "LONG_BRANCH_ADDiu\0"	---
10531	/* 27975 */ "SLTiu\0"	---	10531	/* 27975 */ "SLTiu\0"	---
10532	/* 27981 */ "SelTBtneZSltiu\0"	---	10532	/* 27981 */ "SelTBtneZSltiu\0"	---
10533	/* 27996 */ "SelTBteqZSltiu\0"	---	10533	/* 27996 */ "SelTBteqZSltiu\0"	---
10534	/* 28011 */ "SelTBtneZSltu\0"	---	10534	/* 28011 */ "SelTBtneZSltu\0"	---
10535	/* 28025 */ "SelTBteqZSltu\0"	---	10535	/* 28025 */ "SelTBteqZSltu\0"	---
10536	/* 28039 */ "Ulw\0"	---	10536	/* 28039 */ "Ulw\0"	---
10537	/* 28043 */ "Usw\0"	---	10537	/* 28043 */ "Usw\0"	---
10538	};	---	10538	};	---
10539	#ifdef __GNUC__	---	10539	#ifdef __GNUC__	---
10540	#pragma GCC diagnostic pop	---	10540	#pragma GCC diagnostic pop	---
10541	#endif	---	10541	#endif	---
10542		---	10542		---
10543	extern const unsigned MipsInstrNameIndices[] = {	---	10543	extern const unsigned MipsInstrNameIndices[] = {	---
10544	15358U, 20903U, 22723U, 21178U, 15706U, 15687U, 15715U, 15967U,	---	10544	15358U, 20903U, 22723U, 21178U, 15706U, 15687U, 15715U, 15967U,	---
10545	13725U, 13740U, 13605U, 13779U, 23301U, 13484U, 24572U, 13623U,	---	10545	13725U, 13740U, 13605U, 13779U, 23301U, 13484U, 24572U, 13623U,	---
10546	15354U, 15696U, 13233U, 26792U, 13355U, 24476U, 11679U, 13180U,	---	10546	15354U, 15696U, 13233U, 26792U, 13355U, 24476U, 11679U, 13180U,	---
10547	13221U, 22140U, 15939U, 24405U, 11769U, 22560U, 13842U, 24394U,	---	10547	13221U, 22140U, 15939U, 24405U, 11769U, 22560U, 13842U, 24394U,	---
10548	13408U, 22310U, 22297U, 22792U, 24224U, 24256U, 15871U, 15918U,	---	10548	13408U, 22310U, 22297U, 22792U, 24224U, 24256U, 15871U, 15918U,	---
10549	15891U, 15747U, 22757U, 24613U, 24643U, 21003U, 11562U, 10295U,	---	10549	15891U, 15747U, 22757U, 24613U, 24643U, 21003U, 11562U, 10295U,	---
10550	16123U, 24834U, 24864U, 16224U, 16231U, 16238U, 16248U, 11642U,	---	10550	16123U, 24834U, 24864U, 16224U, 16231U, 16238U, 16248U, 11642U,	---
10551	23093U, 23056U, 13603U, 15356U, 26697U, 13494U, 15977U, 24186U,	---	10551	23093U, 23056U, 13603U, 15356U, 26697U, 13494U, 15977U, 24186U,	---
10552	23235U, 24513U, 23252U, 23008U, 11181U, 23284U, 24416U, 23179U,	---	10552	23235U, 24513U, 23252U, 23008U, 11181U, 23284U, 24416U, 23179U,	---
10553	24545U, 13527U, 22768U, 11738U, 11155U, 11720U, 24435U, 20967U,	---	10553	24545U, 13527U, 22768U, 11738U, 11155U, 11720U, 24435U, 20967U,	---
10554	22817U, 11435U, 11379U, 11409U, 11420U, 11360U, 11390U, 13447U,	---	10554	22817U, 11435U, 11379U, 11409U, 11420U, 11360U, 11390U, 13447U,	---
10555	13431U, 23331U, 13793U, 13810U, 11578U, 10301U, 11648U, 11609U,	---	10555	13431U, 23331U, 13793U, 13810U, 11578U, 10301U, 11648U, 11609U,	---
10556	23098U, 23062U, 26667U, 21129U, 26650U, 21112U, 11518U, 10267U,	---	10556	23098U, 23062U, 26667U, 21129U, 26650U, 21112U, 11518U, 10267U,	---
10557	26585U, 21047U, 22176U, 22154U, 13213U, 11692U, 24205U, 24491U,	---	10557	26585U, 21047U, 22176U, 22154U, 13213U, 11692U, 24205U, 24491U,	---
10558	11067U, 23361U, 24627U, 11173U, 24383U, 24371U, 24466U, 13834U,	---	10558	11067U, 23361U, 24627U, 11173U, 24383U, 24371U, 24466U, 13834U,	---
10559	24606U, 13766U, 24636U, 15832U, 22975U, 22961U, 15825U, 22968U,	---	10559	24606U, 13766U, 24636U, 15832U, 22975U, 22961U, 15825U, 22968U,	---
10560	23172U, 16024U, 22271U, 22264U, 24196U, 21235U, 13258U, 21219U,	---	10560	23172U, 16024U, 22271U, 22264U, 24196U, 21235U, 13258U, 21219U,	---
10561	13205U, 21227U, 13250U, 21211U, 13197U, 22124U, 22116U, 13896U,	---	10561	13205U, 21227U, 13250U, 21211U, 13197U, 22124U, 22116U, 13896U,	---
10562	13888U, 24104U, 24094U, 24084U, 24074U, 24124U, 24114U, 26729U,	---	10562	13888U, 24104U, 24094U, 24084U, 24074U, 24124U, 24114U, 26729U,	---
10563	26739U, 24134U, 24147U, 26749U, 26759U, 24160U, 24173U, 11476U,	---	10563	26739U, 24134U, 24147U, 26749U, 26759U, 24160U, 24173U, 11476U,	---
10564	10246U, 16065U, 8500U, 11353U, 24801U, 16203U, 25016U, 15436U,	---	10564	10246U, 16065U, 8500U, 11353U, 24801U, 16203U, 25016U, 15436U,	---
10565	22612U, 1205U, 13827U, 1187U, 0U, 22587U, 22619U, 13654U,	---	10565	22612U, 1205U, 13827U, 1187U, 0U, 22587U, 22619U, 13654U,	---
10566	24598U, 11145U, 15384U, 15408U, 22233U, 22242U, 23222U, 21018U,	---	10566	24598U, 11145U, 15384U, 15408U, 22233U, 22242U, 23222U, 21018U,	---
10567	23318U, 13536U, 20947U, 20957U, 13266U, 13281U, 20925U, 20936U,	---	10567	23318U, 13536U, 20947U, 20957U, 13266U, 13281U, 20925U, 20936U,	---
10568	11568U, 15581U, 21081U, 26619U, 21105U, 26643U, 23229U, 11711U,	---	10568	11568U, 15581U, 21081U, 26619U, 21105U, 26643U, 23229U, 11711U,	---
10569	11701U, 22711U, 24280U, 24312U, 24291U, 23023U, 26887U, 13585U,	---	10569	11701U, 22711U, 24280U, 24312U, 24291U, 23023U, 26887U, 13585U,	---
10570	26849U, 13567U, 22289U, 22198U, 13465U, 15838U, 23277U, 21145U,	---	10570	26849U, 13567U, 22289U, 22198U, 13465U, 15838U, 23277U, 21145U,	---
10571	24522U, 22994U, 24427U, 24453U, 24555U, 22736U, 13342U, 11207U,	---	10571	24522U, 22994U, 24427U, 24453U, 24555U, 22736U, 13342U, 11207U,	---
10572	11504U, 10253U, 16093U, 24808U, 16210U, 8506U, 24530U, 22596U,	---	10572	11504U, 10253U, 16093U, 24808U, 16210U, 8506U, 24530U, 22596U,	---
10573	22836U, 22852U, 26783U, 13384U, 13509U, 24238U, 22132U, 11483U,	---	10573	22836U, 22852U, 26783U, 13384U, 13509U, 24238U, 22132U, 11483U,	---
10574	16072U, 11459U, 16048U, 26568U, 21030U, 11546U, 16107U, 11626U,	---	10574	16072U, 11459U, 16048U, 26568U, 21030U, 11546U, 16107U, 11626U,	---
10575	23078U, 23040U, 26602U, 21064U, 26626U, 21088U, 26711U, 26718U,	---	10575	23078U, 23040U, 26602U, 21064U, 26626U, 21088U, 26711U, 26718U,	---
10576	27415U, 21194U, 22545U, 21579U, 21663U, 21879U, 4064U, 9386U,	---	10576	27415U, 21194U, 22545U, 21579U, 21663U, 21879U, 4064U, 9386U,	---
10577	884U, 8742U, 3089U, 9064U, 8370U, 9701U, 3946U, 9226U,	---	10577	884U, 8742U, 3089U, 9064U, 8370U, 9701U, 3946U, 9226U,	---
10578	766U, 8582U, 2919U, 8904U, 8258U, 9547U, 3987U, 9281U,	---	10578	766U, 8582U, 2919U, 8904U, 8258U, 9547U, 3987U, 9281U,	---
10579	807U, 8637U, 2960U, 8959U, 8297U, 9600U, 4144U, 9494U,	---	10579	807U, 8637U, 2960U, 8959U, 8297U, 9600U, 4144U, 9494U,	---
10580	964U, 8850U, 3235U, 9172U, 8446U, 9805U, 4028U, 9336U,	---	10580	964U, 8850U, 3235U, 9172U, 8446U, 9805U, 4028U, 9336U,	---
10581	848U, 8692U, 3053U, 9014U, 8336U, 9653U, 3966U, 9253U,	---	10581	848U, 8692U, 3053U, 9014U, 8336U, 9653U, 3966U, 9253U,	---
10582	786U, 8609U, 2939U, 8931U, 8277U, 9573U, 4104U, 9440U,	---	10582	786U, 8609U, 2939U, 8931U, 8277U, 9573U, 4104U, 9440U,	---
10583	924U, 8796U, 3129U, 9118U, 8408U, 9753U, 3926U, 9199U,	---	10583	924U, 8796U, 3129U, 9118U, 8408U, 9753U, 3926U, 9199U,	---
10584	746U, 8555U, 2899U, 8877U, 8239U, 9521U, 4123U, 9466U,	---	10584	746U, 8555U, 2899U, 8877U, 8239U, 9521U, 4123U, 9466U,	---
10585	943U, 8822U, 3214U, 9144U, 8426U, 9778U, 4007U, 9308U,	---	10585	943U, 8822U, 3214U, 9144U, 8426U, 9778U, 4007U, 9308U,	---
10586	827U, 8664U, 3032U, 8986U, 8316U, 9626U, 4084U, 9413U,	---	10586	827U, 8664U, 3032U, 8986U, 8316U, 9626U, 4084U, 9413U,	---
10587	904U, 8769U, 3109U, 9091U, 8389U, 9727U, 4048U, 9363U,	---	10587	904U, 8769U, 3109U, 9091U, 8389U, 9727U, 4048U, 9363U,	---
10588	868U, 8719U, 3073U, 9041U, 8355U, 9679U, 9861U, 22716U,	---	10588	868U, 8719U, 3073U, 9041U, 8355U, 9679U, 9861U, 22716U,	---
10589	19481U, 27521U, 13309U, 27458U, 15732U, 27482U, 24687U, 27653U,	---	10589	19481U, 27521U, 13309U, 27458U, 15732U, 27482U, 24687U, 27653U,	---
10590	16031U, 27560U, 24247U, 27629U, 16014U, 27534U, 24756U, 27679U,	---	10590	16031U, 27560U, 24247U, 27629U, 16014U, 27534U, 24756U, 27679U,	---
10591	16129U, 27601U, 13351U, 27470U, 15737U, 27495U, 24702U, 27666U,	---	10591	16129U, 27601U, 13351U, 27470U, 15737U, 27495U, 24702U, 27666U,	---
10592	16037U, 27574U, 24287U, 27641U, 16019U, 27547U, 24761U, 27692U,	---	10592	16037U, 27574U, 24287U, 27641U, 16019U, 27547U, 24761U, 27692U,	---
10593	16135U, 27615U, 27508U, 21277U, 21565U, 21458U, 21758U, 21649U,	---	10593	16135U, 27615U, 27508U, 21277U, 21565U, 21458U, 21758U, 21649U,	---
10594	21865U, 17673U, 27236U, 27250U, 27164U, 27157U, 4668U, 4215U,	---	10594	21865U, 17673U, 27236U, 27250U, 27164U, 27157U, 4668U, 4215U,	---
10595	4696U, 4245U, 4726U, 4757U, 4654U, 4200U, 4682U, 4230U,	---	10595	4696U, 4245U, 4726U, 4757U, 4654U, 4200U, 4682U, 4230U,	---
10596	4710U, 4742U, 2777U, 3547U, 122U, 26797U, 21505U, 21805U,	---	10596	4710U, 4742U, 2777U, 3547U, 122U, 26797U, 21505U, 21805U,	---
10597	140U, 1144U, 27588U, 27385U, 27395U, 27424U, 15993U, 27103U,	---	10597	140U, 1144U, 27588U, 27385U, 27395U, 27424U, 15993U, 27103U,	---
10598	23003U, 27118U, 27361U, 27705U, 27337U, 27436U, 27373U, 27716U,	---	10598	23003U, 27118U, 27361U, 27705U, 27337U, 27436U, 27373U, 27716U,	---
10599	27349U, 27447U, 27832U, 2790U, 3563U, 12472U, 25821U, 21243U,	---	10599	27349U, 27447U, 27832U, 2790U, 3563U, 12472U, 25821U, 21243U,	---
10600	21260U, 21473U, 21773U, 4815U, 21293U, 21949U, 21340U, 21992U,	---	10600	21260U, 21473U, 21773U, 4815U, 21293U, 21949U, 21340U, 21992U,	---
10601	21488U, 21316U, 21970U, 21788U, 21386U, 22034U, 21363U, 22013U,	---	10601	21488U, 21316U, 21970U, 21788U, 21386U, 22034U, 21363U, 22013U,	---
10602	21410U, 22056U, 27199U, 27184U, 27212U, 27225U, 6952U, 26910U,	---	10602	21410U, 22056U, 27199U, 27184U, 27212U, 27225U, 6952U, 26910U,	---
10603	26920U, 27292U, 12401U, 25685U, 3912U, 8214U, 2044U, 22322U,	---	10603	26920U, 27292U, 12401U, 25685U, 3912U, 8214U, 2044U, 22322U,	---
10604	22407U, 27957U, 27768U, 27928U, 27746U, 27017U, 27727U, 3593U,	---	10604	22407U, 27957U, 27768U, 27928U, 27746U, 27017U, 27727U, 3593U,	---
10605	19025U, 1112U, 3803U, 1079U, 3615U, 1102U, 3793U, 22875U,	---	10605	19025U, 1112U, 3803U, 1079U, 3615U, 1102U, 3793U, 22875U,	---
10606	1059U, 23127U, 22892U, 23144U, 1142U, 26683U, 43U, 128U,	---	10606	1059U, 23127U, 22892U, 23144U, 1142U, 26683U, 43U, 128U,	---
10607	22363U, 23113U, 103U, 15362U, 22099U, 1126U, 3832U, 21520U,	---	10607	22363U, 23113U, 103U, 15362U, 22099U, 1126U, 3832U, 21520U,	---
10608	21820U, 21543U, 21843U, 26690U, 55U, 146U, 22370U, 23120U,	---	10608	21820U, 21543U, 21843U, 26690U, 55U, 146U, 22370U, 23120U,	---
10609	110U, 15373U, 22110U, 27589U, 27396U, 27425U, 5075U, 5208U,	---	10609	110U, 15373U, 22110U, 27589U, 27396U, 27425U, 5075U, 5208U,	---
10610	5107U, 5260U, 22280U, 27111U, 3726U, 21594U, 21678U, 21894U,	---	10610	5107U, 5260U, 22280U, 27111U, 3726U, 21594U, 21678U, 21894U,	---
10611	21595U, 21679U, 21895U, 10041U, 9943U, 10156U, 14058U, 13953U,	---	10611	21595U, 21679U, 21895U, 10041U, 9943U, 10156U, 14058U, 13953U,	---
10612	14218U, 25026U, 16173U, 25058U, 16189U, 26111U, 24340U, 27894U,	---	10612	14218U, 25026U, 16173U, 25058U, 16189U, 26111U, 24340U, 27894U,	---
10613	24822U, 24852U, 15510U, 3148U, 26957U, 3658U, 5320U, 8191U,	---	10613	24822U, 24852U, 15510U, 3148U, 26957U, 3658U, 5320U, 8191U,	---
10614	20765U, 7985U, 26930U, 3629U, 5290U, 8163U, 11535U, 24669U,	---	10614	20765U, 7985U, 26930U, 3629U, 5290U, 8163U, 11535U, 24669U,	---
10615	20209U, 18005U, 15330U, 2838U, 18657U, 22082U, 3283U, 19046U,	---	10615	20209U, 18005U, 15330U, 2838U, 18657U, 22082U, 3283U, 19046U,	---
10616	10284U, 24657U, 20194U, 17936U, 15341U, 2851U, 22447U, 18671U,	---	10616	10284U, 24657U, 20194U, 17936U, 15341U, 2851U, 22447U, 18671U,	---
10617	24352U, 20173U, 27907U, 20866U, 13987U, 9978U, 27171U, 3817U,	---	10617	24352U, 20173U, 27907U, 20866U, 13987U, 9978U, 27171U, 3817U,	---
10618	24841U, 379U, 2362U, 15473U, 2989U, 23605U, 635U, 2675U,	---	10618	24841U, 379U, 2362U, 15473U, 2989U, 23605U, 635U, 2675U,	---
10619	15549U, 3193U, 23959U, 550U, 2590U, 15527U, 3167U, 23843U,	---	10619	15549U, 3193U, 23959U, 550U, 2590U, 15527U, 3167U, 23843U,	---
10620	13124U, 674U, 23992U, 24871U, 15994U, 27104U, 23004U, 27119U,	---	10620	13124U, 674U, 23992U, 24871U, 15994U, 27104U, 23004U, 27119U,	---
10621	9831U, 3897U, 203U, 27262U, 27300U, 27362U, 27706U, 27327U,	---	10621	9831U, 3897U, 203U, 27262U, 27300U, 27362U, 27706U, 27327U,	---
10622	27406U, 13313U, 27089U, 3708U, 24692U, 27133U, 3753U, 27126U,	---	10622	27406U, 13313U, 27089U, 3708U, 24692U, 27133U, 3753U, 27126U,	---
10623	3735U, 27149U, 3773U, 13366U, 27096U, 3717U, 24707U, 27141U,	---	10623	3735U, 27149U, 3773U, 13366U, 27096U, 3717U, 24707U, 27141U,	---
10624	3763U, 3744U, 3783U, 27317U, 27308U, 21433U, 21624U, 21708U,	---	10624	3763U, 3744U, 3783U, 27317U, 27308U, 21433U, 21624U, 21708U,	---
10625	21733U, 21924U, 27338U, 27437U, 8226U, 2055U, 22336U, 22422U,	---	10625	21733U, 21924U, 27338U, 27437U, 8226U, 2055U, 22336U, 22422U,	---
10626	12459U, 25743U, 3919U, 19032U, 21446U, 21637U, 21721U, 21746U,	---	10626	12459U, 25743U, 3919U, 19032U, 21446U, 21637U, 21721U, 21746U,	---
10627	21937U, 27815U, 27823U, 26902U, 26894U, 27802U, 27047U, 27850U,	---	10627	21937U, 27815U, 27823U, 26902U, 26894U, 27802U, 27047U, 27850U,	---
10628	27075U, 27996U, 28025U, 27789U, 27033U, 27837U, 27061U, 27981U,	---	10628	27075U, 27996U, 28025U, 27789U, 27033U, 27837U, 27061U, 27981U,	---
10629	28011U, 5020U, 4479U, 4494U, 5032U, 5247U, 15846U, 13679U,	---	10629	28011U, 5020U, 4479U, 4494U, 5032U, 5247U, 15846U, 13679U,	---
10630	13661U, 13695U, 13711U, 13754U, 2808U, 9879U, 2000U, 18216U,	---	10630	13661U, 13695U, 13711U, 13754U, 2808U, 9879U, 2000U, 18216U,	---
10631	6829U, 18956U, 6961U, 22149U, 19077U, 27277U, 27374U, 27717U,	---	10631	6829U, 18956U, 6961U, 22149U, 19077U, 27277U, 27374U, 27717U,	---
10632	27350U, 27448U, 26978U, 27923U, 28039U, 26982U, 28043U, 21609U,	---	10632	27350U, 27448U, 26978U, 27923U, 28039U, 26982U, 28043U, 21609U,	---
10633	21693U, 21909U, 14177U, 18472U, 10101U, 1353U, 26039U, 20640U,	---	10633	21693U, 21909U, 14177U, 18472U, 10101U, 1353U, 26039U, 20640U,	---
10634	11455U, 11242U, 17958U, 6006U, 19157U, 16905U, 17318U, 19329U,	---	10634	11455U, 11242U, 17958U, 6006U, 19157U, 16905U, 17318U, 19329U,	---
10635	7871U, 13978U, 1456U, 14095U, 1511U, 25782U, 1869U, 25344U,	---	10635	7871U, 13978U, 1456U, 14095U, 1511U, 25782U, 1869U, 25344U,	---
10636	1841U, 14050U, 18368U, 14157U, 18459U, 26021U, 20628U, 3401U,	---	10636	1841U, 14050U, 18368U, 14157U, 18459U, 26021U, 20628U, 3401U,	---
10637	11266U, 17969U, 10339U, 11842U, 14457U, 25097U, 10747U, 12641U,	---	10637	11266U, 17969U, 10339U, 11842U, 14457U, 25097U, 10747U, 12641U,	---
10638	14946U, 26066U, 10939U, 13006U, 15195U, 26415U, 17535U, 5746U,	---	10638	14946U, 26066U, 10939U, 13006U, 15195U, 26415U, 17535U, 5746U,	---
10639	9969U, 1258U, 10079U, 1321U, 7841U, 14242U, 1599U, 10181U,	---	10639	9969U, 1258U, 10079U, 1321U, 7841U, 14242U, 1599U, 10181U,	---
10640	17859U, 14197U, 1571U, 10121U, 17806U, 10553U, 12206U, 14642U,	---	10640	17859U, 14197U, 1571U, 10121U, 17806U, 10553U, 12206U, 14642U,	---
10641	25462U, 11009U, 13087U, 15265U, 26505U, 11299U, 17978U, 10323U,	---	10641	25462U, 11009U, 13087U, 15265U, 26505U, 11299U, 17978U, 10323U,	---
10642	11825U, 14441U, 25080U, 18012U, 6228U, 26987U, 20789U, 27941U,	---	10642	11825U, 14441U, 25080U, 18012U, 6228U, 26987U, 20789U, 27941U,	---
10643	20885U, 27874U, 20843U, 20990U, 7019U, 11235U, 5994U, 11622U,	---	10643	20885U, 27874U, 20843U, 20990U, 7019U, 11235U, 5994U, 11622U,	---
10644	17346U, 5587U, 2178U, 17373U, 5620U, 10428U, 6884U, 18019U,	---	10644	17346U, 5587U, 2178U, 17373U, 5620U, 10428U, 6884U, 18019U,	---
10645	6237U, 24942U, 26992U, 3681U, 20797U, 11672U, 1413U, 10652U,	---	10645	6237U, 24942U, 26992U, 3681U, 20797U, 11672U, 1413U, 10652U,	---
10646	12488U, 14795U, 25868U, 10844U, 12853U, 15053U, 26262U, 15404U,	---	10646	12488U, 14795U, 25868U, 10844U, 12853U, 15053U, 26262U, 15404U,	---
10647	11229U, 5983U, 6912U, 10729U, 12623U, 14919U, 26048U, 10921U,	---	10647	11229U, 5983U, 6912U, 10729U, 12623U, 14919U, 26048U, 10921U,	---
10648	12988U, 15177U, 26397U, 10677U, 12562U, 14858U, 25942U, 10869U,	---	10648	12988U, 15177U, 26397U, 10677U, 12562U, 14858U, 25942U, 10869U,	---
10649	12927U, 15116U, 26336U, 4547U, 4423U, 4931U, 4575U, 4372U,	---	10649	12927U, 15116U, 26336U, 4547U, 4423U, 4931U, 4575U, 4372U,	---
10650	4871U, 4439U, 5234U, 5173U, 17330U, 27873U, 15591U, 11079U,	---	10650	4871U, 4439U, 5234U, 5173U, 17330U, 27873U, 15591U, 11079U,	---
10651	5862U, 20989U, 1774U, 76U, 222U, 216U, 230U, 11050U,	---	10651	5862U, 20989U, 1774U, 76U, 222U, 216U, 230U, 11050U,	---
10652	5527U, 26856U, 6169U, 13562U, 15767U, 18188U, 26823U, 6132U,	---	10652	5527U, 26856U, 6169U, 13562U, 15767U, 18188U, 26823U, 6132U,	---
10653	24069U, 16008U, 20134U, 26863U, 6182U, 26830U, 6145U, 10489U,	---	10653	24069U, 16008U, 20134U, 26863U, 6182U, 26830U, 6145U, 10489U,	---
10654	12156U, 14592U, 25412U, 10623U, 12407U, 14766U, 25691U, 5825U,	---	10654	12156U, 14592U, 25412U, 10623U, 12407U, 14766U, 25691U, 5825U,	---
10655	22628U, 3303U, 11261U, 2095U, 6029U, 15998U, 17580U, 11114U,	---	10655	22628U, 3303U, 11261U, 2095U, 6029U, 15998U, 17580U, 11114U,	---
10656	5922U, 11323U, 5574U, 2154U, 17996U, 6195U, 19378U, 11053U,	---	10656	5922U, 11323U, 5574U, 2154U, 17996U, 6195U, 19378U, 11053U,	---
10657	2067U, 5833U, 11277U, 2114U, 6068U, 26813U, 3501U, 15599U,	---	10657	2067U, 5833U, 11277U, 2114U, 6068U, 26813U, 3501U, 15599U,	---
10658	11090U, 5883U, 15951U, 19650U, 18791U, 11305U, 2130U, 6110U,	---	10658	11090U, 5883U, 15951U, 19650U, 18791U, 11305U, 2130U, 6110U,	---
10659	16149U, 20726U, 26877U, 3533U, 11122U, 5935U, 11329U, 2162U,	---	10659	16149U, 20726U, 26877U, 3533U, 11122U, 5935U, 11329U, 2162U,	---
10660	6206U, 16161U, 20749U, 10465U, 12132U, 14568U, 25388U, 10595U,	---	10660	6206U, 16161U, 20749U, 10465U, 12132U, 14568U, 25388U, 10595U,	---
10661	12255U, 14669U, 25505U, 10519U, 12172U, 14608U, 25428U, 10637U,	---	10661	12255U, 14669U, 25505U, 10519U, 12172U, 14608U, 25428U, 10637U,	---
10662	12451U, 14780U, 25735U, 24789U, 20273U, 22207U, 7039U, 26818U,	---	10662	12451U, 14780U, 25735U, 24789U, 20273U, 22207U, 7039U, 26818U,	---
10663	3508U, 11098U, 5896U, 11311U, 2138U, 6121U, 16155U, 20734U,	---	10663	3508U, 11098U, 5896U, 11311U, 2138U, 6121U, 16155U, 20734U,	---
10664	11272U, 2107U, 6058U, 11283U, 2122U, 6079U, 26882U, 3540U,	---	10664	11272U, 2107U, 6058U, 11283U, 2122U, 6079U, 26882U, 3540U,	---
10665	15606U, 11130U, 5948U, 15959U, 19661U, 18801U, 11335U, 2170U,	---	10665	15606U, 11130U, 5948U, 15959U, 19661U, 18801U, 11335U, 2170U,	---
10666	6217U, 16167U, 20757U, 10568U, 24991U, 10561U, 24979U, 13380U,	---	10666	6217U, 16167U, 20757U, 10568U, 24991U, 10561U, 24979U, 13380U,	---
10667	2771U, 11058U, 2074U, 5843U, 10435U, 12110U, 14546U, 25366U,	---	10667	2771U, 11058U, 2074U, 5843U, 10435U, 12110U, 14546U, 25366U,	---
10668	10407U, 12089U, 14525U, 25270U, 15742U, 17570U, 11106U, 5909U,	---	10668	10407U, 12089U, 14525U, 25270U, 15742U, 17570U, 11106U, 5909U,	---
10669	11317U, 5561U, 2146U, 17987U, 6158U, 18119U, 11289U, 6090U,	---	10669	11317U, 5561U, 2146U, 17987U, 6158U, 18119U, 11289U, 6090U,	---
10670	11044U, 13161U, 15300U, 24985U, 26562U, 11294U, 6100U, 737U,	---	10670	11044U, 13161U, 15300U, 24985U, 26562U, 11294U, 6100U, 737U,	---
10671	1933U, 16847U, 15570U, 17401U, 5642U, 18775U, 6941U, 10443U,	---	10671	1933U, 16847U, 15570U, 17401U, 5642U, 18775U, 6941U, 10443U,	---
10672	24955U, 10537U, 12190U, 14626U, 25446U, 10816U, 12730U, 15025U,	---	10672	24955U, 10537U, 12190U, 14626U, 25446U, 10816U, 12730U, 15025U,	---
10673	26179U, 11039U, 13147U, 15295U, 24974U, 26557U, 4958U, 4604U,	---	10673	26179U, 11039U, 13147U, 15295U, 24974U, 26557U, 4958U, 4604U,	---
10674	4970U, 4617U, 4946U, 4591U, 4857U, 5282U, 4781U, 5274U,	---	10674	4970U, 4617U, 4946U, 4591U, 4857U, 5282U, 4781U, 5274U,	---
10675	4772U, 13321U, 13296U, 18047U, 18073U, 6772U, 8107U, 2457U,	---	10675	4772U, 13321U, 13296U, 18047U, 18073U, 6772U, 8107U, 2457U,	---
10676	6435U, 23698U, 7419U, 704U, 2738U, 6704U, 20466U, 24018U,	---	10676	6435U, 23698U, 7419U, 704U, 2738U, 6704U, 20466U, 24018U,	---
10677	20098U, 7700U, 10474U, 12141U, 14577U, 25397U, 10610U, 12325U,	---	10677	20098U, 7700U, 10474U, 12141U, 14577U, 25397U, 10610U, 12325U,	---
10678	14692U, 25588U, 92U, 16296U, 16889U, 9842U, 23267U, 1006U,	---	10678	14692U, 25588U, 92U, 16296U, 16889U, 9842U, 23267U, 1006U,	---
10679	1039U, 1093U, 12480U, 6577U, 23835U, 7561U, 10685U, 12570U,	---	10679	1039U, 1093U, 12480U, 6577U, 23835U, 7561U, 10685U, 12570U,	---
10680	14866U, 25950U, 10877U, 12935U, 15124U, 26344U, 10669U, 12554U,	---	10680	14866U, 25950U, 10877U, 12935U, 15124U, 26344U, 10669U, 12554U,	---
10681	14850U, 25934U, 10861U, 12919U, 15108U, 26328U, 22078U, 19039U,	---	10681	14850U, 25934U, 10861U, 12919U, 15108U, 26328U, 22078U, 19039U,	---
10682	7030U, 8139U, 10703U, 12588U, 14884U, 25968U, 10895U, 12953U,	---	10682	7030U, 8139U, 10703U, 12588U, 14884U, 25968U, 10895U, 12953U,	---
10683	15142U, 26362U, 10764U, 12658U, 14963U, 26083U, 10967U, 13034U,	---	10683	15142U, 26362U, 10764U, 12658U, 14963U, 26083U, 10967U, 13034U,	---
10684	15223U, 26443U, 26845U, 20742U, 7964U, 8156U, 10016U, 1272U,	---	10684	15223U, 26443U, 26845U, 20742U, 7964U, 8156U, 10016U, 1272U,	---
10685	9918U, 1226U, 10131U, 1368U, 10029U, 17764U, 9931U, 17691U,	---	10685	9918U, 1226U, 10131U, 1368U, 10029U, 17764U, 9931U, 17691U,	---
10686	10144U, 17819U, 10047U, 17779U, 9949U, 17706U, 10162U, 17834U,	---	10686	10144U, 17819U, 10047U, 17779U, 9949U, 17706U, 10162U, 17834U,	---
10687	6354U, 7314U, 12385U, 6563U, 14064U, 18379U, 23819U, 7547U,	---	10687	6354U, 7314U, 12385U, 6563U, 14064U, 18379U, 23819U, 7547U,	---
10688	12081U, 23624U, 11987U, 6325U, 13959U, 18298U, 23550U, 7285U,	---	10688	12081U, 23624U, 11987U, 6325U, 13959U, 18298U, 23550U, 7285U,	---
10689	12798U, 6636U, 14224U, 18499U, 23920U, 7620U, 12048U, 6339U,	---	10689	12798U, 6636U, 14224U, 18499U, 23920U, 7620U, 12048U, 6339U,	---
10690	23559U, 7299U, 12338U, 6517U, 23773U, 7501U, 11940U, 6279U,	---	10690	23559U, 7299U, 12338U, 6517U, 23773U, 7501U, 11940U, 6279U,	---
10691	23504U, 7239U, 12751U, 6590U, 23874U, 7574U, 12364U, 6532U,	---	10691	23504U, 7239U, 12751U, 6590U, 23874U, 7574U, 12364U, 6532U,	---
10692	23783U, 7516U, 11966U, 6294U, 23514U, 7254U, 12777U, 6605U,	---	10692	23783U, 7516U, 11966U, 6294U, 23514U, 7254U, 12777U, 6605U,	---
10693	23884U, 7589U, 12298U, 6488U, 23731U, 7472U, 12375U, 6548U,	---	10693	23884U, 7589U, 12298U, 6488U, 23731U, 7472U, 12375U, 6548U,	---
10694	23802U, 7532U, 11977U, 6310U, 23533U, 7270U, 12788U, 6621U,	---	10694	23802U, 7532U, 11977U, 6310U, 23533U, 7270U, 12788U, 6621U,	---
10695	23903U, 7605U, 12308U, 6503U, 23748U, 7487U, 10799U, 12713U,	---	10695	23903U, 7605U, 12308U, 6503U, 23748U, 7487U, 10799U, 12713U,	---
10696	15008U, 26162U, 10991U, 15247U, 26487U, 9856U, 9863U, 11442U,	---	10696	15008U, 26162U, 10991U, 15247U, 26487U, 9856U, 9863U, 11442U,	---
10697	13876U, 25005U, 11341U, 13859U, 24998U, 117U, 16312U, 16897U,	---	10697	13876U, 25005U, 11341U, 13859U, 24998U, 117U, 16312U, 16897U,	---
10698	9849U, 23393U, 19696U, 25032U, 20385U, 16179U, 23403U, 19709U,	---	10698	9849U, 23393U, 19696U, 25032U, 20385U, 16179U, 23403U, 19709U,	---
10699	25064U, 20398U, 6993U, 2480U, 17103U, 6464U, 23717U, 19903U,	---	10699	25064U, 20398U, 6993U, 2480U, 17103U, 6464U, 23717U, 19903U,	---
10700	7448U, 3484U, 3451U, 3439U, 540U, 16708U, 2580U, 17191U,	---	10700	7448U, 3484U, 3451U, 3439U, 540U, 16708U, 2580U, 17191U,	---
10701	16195U, 7006U, 3260U, 3468U, 26117U, 20652U, 7939U, 727U,	---	10701	16195U, 7006U, 3260U, 3468U, 26117U, 20652U, 7939U, 727U,	---
10702	16834U, 2761U, 17305U, 24037U, 20123U, 7729U, 522U, 16684U,	---	10702	16834U, 2761U, 17305U, 24037U, 20123U, 7729U, 522U, 16684U,	---
10703	2562U, 17167U, 23812U, 19957U, 371U, 16545U, 2354U, 17055U,	---	10703	2562U, 17167U, 23812U, 19957U, 371U, 16545U, 2354U, 17055U,	---
10704	23599U, 19839U, 344U, 16509U, 2327U, 17031U, 23543U, 19809U,	---	10704	23599U, 19839U, 344U, 16509U, 2327U, 17031U, 23543U, 19809U,	---
10705	597U, 16760U, 2637U, 17243U, 23913U, 20010U, 303U, 16456U,	---	10705	597U, 16760U, 2637U, 17243U, 23913U, 20010U, 303U, 16456U,	---
10706	2286U, 16978U, 23479U, 19764U, 313U, 16469U, 2296U, 16991U,	---	10706	2286U, 16978U, 23479U, 19764U, 313U, 16469U, 2296U, 16991U,	---
10707	23487U, 19775U, 431U, 16596U, 2414U, 17078U, 23663U, 19882U,	---	10707	23487U, 19775U, 431U, 16596U, 2414U, 17078U, 23663U, 19882U,	---
10708	567U, 16721U, 2607U, 17204U, 23858U, 19977U, 324U, 16483U,	---	10708	567U, 16721U, 2607U, 17204U, 23858U, 19977U, 324U, 16483U,	---
10709	2307U, 17005U, 23496U, 19787U, 577U, 16734U, 2617U, 17217U,	---	10709	2307U, 17005U, 23496U, 19787U, 577U, 16734U, 2617U, 17217U,	---
10710	23866U, 19988U, 502U, 16658U, 2542U, 17141U, 23765U, 19935U,	---	10710	23866U, 19988U, 502U, 16658U, 2542U, 17141U, 23765U, 19935U,	---
10711	353U, 16521U, 2336U, 17043U, 23585U, 19819U, 512U, 16671U,	---	10711	353U, 16521U, 2336U, 17043U, 23585U, 19819U, 512U, 16671U,	---
10712	2552U, 17154U, 23794U, 19946U, 334U, 16496U, 2317U, 17018U,	---	10712	2552U, 17154U, 23794U, 19946U, 334U, 16496U, 2317U, 17018U,	---
10713	23525U, 19798U, 587U, 16747U, 2627U, 17230U, 23895U, 19999U,	---	10713	23525U, 19798U, 587U, 16747U, 2627U, 17230U, 23895U, 19999U,	---
10714	474U, 16621U, 2514U, 17116U, 23741U, 19914U, 5055U, 4894U,	---	10714	474U, 16621U, 2514U, 17116U, 23741U, 19914U, 5055U, 4894U,	---
10715	4521U, 11454U, 26986U, 27940U, 27879U, 15325U, 20996U, 15393U,	---	10715	4521U, 11454U, 26986U, 27940U, 27879U, 15325U, 20996U, 15393U,	---
10716	15403U, 22206U, 22077U, 8138U, 26844U, 8155U, 24796U, 24777U,	---	10716	15403U, 22206U, 22077U, 8138U, 26844U, 8155U, 24796U, 24777U,	---
10717	24218U, 20142U, 7781U, 24593U, 1049U, 20919U, 24771U, 15312U,	---	10717	24218U, 20142U, 7781U, 24593U, 1049U, 20919U, 24771U, 15312U,	---
10718	23272U, 20913U, 24750U, 24797U, 24778U, 7892U, 7902U, 10783U,	---	10718	23272U, 20913U, 24750U, 24797U, 24778U, 7892U, 7902U, 10783U,	---
10719	12697U, 14982U, 26136U, 10975U, 13062U, 15231U, 26471U, 18635U,	---	10719	12697U, 14982U, 26136U, 10975U, 13062U, 15231U, 26471U, 18635U,	---
10720	6886U, 9837U, 8070U, 9U, 97U, 1165U, 21152U, 15U,	---	10720	6886U, 9837U, 8070U, 9U, 97U, 1165U, 21152U, 15U,	---
10721	11764U, 24681U, 24363U, 49U, 134U, 1171U, 21165U, 36U,	---	10721	11764U, 24681U, 24363U, 49U, 134U, 1171U, 21165U, 36U,	---
10722	14430U, 24712U, 16043U, 24346U, 27900U, 24738U, 8130U, 12614U,	---	10722	14430U, 24712U, 16043U, 24346U, 27900U, 24738U, 8130U, 12614U,	---
10723	14910U, 26003U, 12979U, 15168U, 26388U, 12536U, 14832U, 25916U,	---	10723	14910U, 26003U, 12979U, 15168U, 26388U, 12536U, 14832U, 25916U,	---
10724	12901U, 15090U, 26310U, 14306U, 1656U, 14381U, 1708U, 25527U,	---	10724	12901U, 15090U, 26310U, 14306U, 1656U, 14381U, 1708U, 25527U,	---
10725	20476U, 14343U, 18548U, 15657U, 18864U, 22689U, 19453U, 14407U,	---	10725	20476U, 14343U, 18548U, 15657U, 18864U, 22689U, 19453U, 14407U,	---
10726	1744U, 14286U, 1626U, 22284U, 14320U, 1675U, 14394U, 1726U,	---	10726	1744U, 14286U, 1626U, 22284U, 14320U, 1675U, 14394U, 1726U,	---
10727	25539U, 20491U, 14369U, 18580U, 12506U, 14813U, 25886U, 12871U,	---	10727	25539U, 20491U, 14369U, 18580U, 12506U, 14813U, 25886U, 12871U,	---
10728	15071U, 26280U, 15668U, 18878U, 22700U, 19467U, 14417U, 1759U,	---	10728	15071U, 26280U, 15668U, 18878U, 22700U, 19467U, 14417U, 1759U,	---
10729	14334U, 1694U, 23166U, 998U, 24930U, 13866U, 24828U, 11594U,	---	10729	14334U, 1694U, 23166U, 998U, 24930U, 13866U, 24828U, 11594U,	---
10730	15972U, 984U, 1029U, 24882U, 8550U, 238U, 24783U, 16003U,	---	10730	15972U, 984U, 1029U, 24882U, 8550U, 238U, 24783U, 16003U,	---
10731	991U, 24888U, 10241U, 27867U, 24858U, 22579U, 13421U, 7111U,	---	10731	991U, 24888U, 10241U, 27867U, 24858U, 22579U, 13421U, 7111U,	---
10732	5141U, 5119U, 9875U, 17678U, 5777U, 15317U, 18643U, 6894U,	---	10732	5141U, 5119U, 9875U, 17678U, 5777U, 15317U, 18643U, 6894U,	---
10733	24367U, 24219U, 11138U, 5961U, 20143U, 7782U, 22583U, 13426U,	---	10733	24367U, 24219U, 11138U, 5961U, 20143U, 7782U, 22583U, 13426U,	---
10734	7120U, 24594U, 22540U, 22226U, 24916U, 20336U, 19102U, 24924U,	---	10734	7120U, 24594U, 22540U, 22226U, 24916U, 20336U, 19102U, 24924U,	---
10735	20347U, 19356U, 25848U, 20590U, 25811U, 20564U, 14990U, 18613U,	---	10735	20347U, 19356U, 25848U, 20590U, 25811U, 20564U, 14990U, 18613U,	---
10736	26542U, 20676U, 25838U, 20577U, 25792U, 20539U, 14928U, 18601U,	---	10736	26542U, 20676U, 25838U, 20577U, 25792U, 20539U, 14928U, 18601U,	---
10737	25749U, 20517U, 23388U, 1013U, 20187U, 7813U, 531U, 16696U,	---	10737	25749U, 20517U, 23388U, 1013U, 20187U, 7813U, 531U, 16696U,	---
10738	2571U, 17179U, 23828U, 19967U, 11889U, 284U, 16431U, 2267U,	---	10738	2571U, 17179U, 23828U, 19967U, 11889U, 284U, 16431U, 2267U,	---
10739	16966U, 3363U, 23464U, 19743U, 7227U, 25144U, 12034U, 25249U,	---	10739	16966U, 3363U, 23464U, 19743U, 7227U, 25144U, 12034U, 25249U,	---
10740	12324U, 25587U, 12479U, 25859U, 11926U, 25181U, 12737U, 26186U,	---	10740	12324U, 25587U, 12479U, 25859U, 11926U, 25181U, 12737U, 26186U,	---
10741	493U, 16646U, 2533U, 1020U, 16877U, 11996U, 25211U, 12421U,	---	10741	493U, 16646U, 2533U, 1020U, 16877U, 11996U, 25211U, 12421U,	---
10742	25705U, 12348U, 25601U, 11950U, 25195U, 12761U, 26200U, 12010U,	---	10742	25705U, 12348U, 25601U, 11950U, 25195U, 12761U, 26200U, 12010U,	---
10743	25225U, 12284U, 25558U, 13110U, 656U, 16810U, 2696U, 17281U,	---	10743	25225U, 12284U, 25558U, 13110U, 656U, 16810U, 2696U, 17281U,	---
10744	23978U, 20052U, 7646U, 26528U, 14684U, 25572U, 11797U, 25050U,	---	10744	23978U, 20052U, 7646U, 26528U, 14684U, 25572U, 11797U, 25050U,	---
10745	12233U, 25483U, 12435U, 25719U, 12666U, 26091U, 13042U, 26451U,	---	10745	12233U, 25483U, 12435U, 25719U, 12666U, 26091U, 13042U, 26451U,	---
10746	12242U, 25492U, 12444U, 25728U, 10576U, 12220U, 14650U, 25470U,	---	10746	12242U, 25492U, 12444U, 25728U, 10576U, 12220U, 14650U, 25470U,	---
10747	11789U, 25042U, 2468U, 6449U, 23707U, 7433U, 715U, 2749U,	---	10747	11789U, 25042U, 2468U, 6449U, 23707U, 7433U, 715U, 2749U,	---
10748	6718U, 20506U, 24027U, 20110U, 7714U, 11896U, 25151U, 11851U,	---	10748	6718U, 20506U, 24027U, 20110U, 7714U, 11896U, 25151U, 11851U,	---
10749	25106U, 13140U, 26550U, 11833U, 25088U, 12277U, 25551U, 665U,	---	10749	25106U, 13140U, 26550U, 11833U, 25088U, 12277U, 25551U, 665U,	---
10750	16822U, 2705U, 17293U, 6662U, 23985U, 20062U, 7658U, 11867U,	---	10750	16822U, 2705U, 17293U, 6662U, 23985U, 20062U, 7658U, 11867U,	---
10751	25122U, 12263U, 441U, 16609U, 2424U, 17091U, 3382U, 23671U,	---	10751	25122U, 12263U, 441U, 16609U, 2424U, 17091U, 3382U, 23671U,	---
10752	19893U, 7377U, 25513U, 400U, 16556U, 2383U, 17066U, 23632U,	---	10752	19893U, 7377U, 25513U, 400U, 16556U, 2383U, 17066U, 23632U,	---
10753	19848U, 7354U, 15576U, 12317U, 25580U, 12814U, 26223U, 12839U,	---	10753	19848U, 7354U, 15576U, 12317U, 25580U, 12814U, 26223U, 12839U,	---
10754	26248U, 12041U, 25256U, 12331U, 25594U, 11933U, 25188U, 12744U,	---	10754	26248U, 12041U, 25256U, 12331U, 25594U, 11933U, 25188U, 12744U,	---
10755	26193U, 12003U, 25218U, 12428U, 25712U, 12831U, 606U, 16772U,	---	10755	26193U, 12003U, 25218U, 12428U, 25712U, 12831U, 606U, 16772U,	---
10756	2646U, 17255U, 23936U, 20020U, 26240U, 11860U, 265U, 16406U,	---	10756	2646U, 17255U, 23936U, 20020U, 26240U, 11860U, 265U, 16406U,	---
10757	2248U, 16954U, 3353U, 23449U, 19722U, 7215U, 25115U, 12356U,	---	10757	2248U, 16954U, 3353U, 23449U, 19722U, 7215U, 25115U, 12356U,	---
10758	25609U, 11958U, 25203U, 12769U, 26208U, 12018U, 25233U, 12291U,	---	10758	25609U, 11958U, 25203U, 12769U, 26208U, 12018U, 25233U, 12291U,	---
10759	25565U, 12676U, 26101U, 13052U, 26461U, 14698U, 25617U, 12516U,	---	10759	25565U, 12676U, 26101U, 13052U, 26461U, 14698U, 25617U, 12516U,	---
10760	25896U, 12881U, 26290U, 15417U, 6930U, 24587U, 7802U, 12527U,	---	10760	25896U, 12881U, 26290U, 15417U, 6930U, 24587U, 7802U, 12527U,	---
10761	14823U, 25907U, 12892U, 15081U, 26301U, 12497U, 14804U, 25877U,	---	10761	14823U, 25907U, 12892U, 15081U, 26301U, 12497U, 14804U, 25877U,	---
10762	12862U, 15062U, 26271U, 15855U, 18968U, 11024U, 13102U, 15280U,	---	10762	12862U, 15062U, 26271U, 15855U, 18968U, 11024U, 13102U, 15280U,	---
10763	26520U, 10603U, 12270U, 14677U, 25520U, 10384U, 11918U, 14502U,	---	10763	26520U, 10603U, 12270U, 14677U, 25520U, 10384U, 11918U, 14502U,	---
10764	25173U, 10645U, 12465U, 14788U, 25756U, 23268U, 10830U, 12822U,	---	10764	25173U, 10645U, 12465U, 14788U, 25756U, 23268U, 10830U, 12822U,	---
10765	15039U, 26231U, 24937U, 10392U, 12026U, 14510U, 25241U, 20365U,	---	10765	15039U, 26231U, 24937U, 10392U, 12026U, 14510U, 25241U, 20365U,	---
10766	19672U, 7182U, 15568U, 15595U, 22985U, 17477U, 3314U, 5548U,	---	10766	19672U, 7182U, 15568U, 15595U, 22985U, 17477U, 3314U, 5548U,	---
10767	5786U, 6039U, 17496U, 19679U, 9899U, 2024U, 19570U, 19642U,	---	10767	5786U, 6039U, 17496U, 19679U, 9899U, 2024U, 19570U, 19642U,	---
10768	26769U, 20703U, 18784U, 11084U, 2087U, 5872U, 11063U, 2081U,	---	10768	26769U, 20703U, 18784U, 11084U, 2087U, 5872U, 11063U, 2081U,	---
10769	5853U, 22982U, 17469U, 3309U, 22530U, 17337U, 5537U, 7085U,	---	10769	5853U, 22982U, 17469U, 3309U, 22530U, 17337U, 5537U, 7085U,	---
10770	9893U, 2016U, 8043U, 8078U, 19564U, 18770U, 4865U, 3905U,	---	10770	9893U, 2016U, 8043U, 8078U, 19564U, 18770U, 4865U, 3905U,	---
10771	4798U, 4790U, 5004U, 4836U, 9907U, 2034U, 13176U, 18026U,	---	10771	4798U, 4790U, 5004U, 4836U, 9907U, 2034U, 13176U, 18026U,	---
10772	17516U, 26774U, 20711U, 7822U, 17685U, 5800U, 27863U, 3848U,	---	10772	17516U, 26774U, 20711U, 7822U, 17685U, 5800U, 27863U, 3848U,	---
10773	13552U, 18172U, 20828U, 11602U, 82U, 1948U, 5489U, 450U,	---	10773	13552U, 18172U, 20828U, 11602U, 82U, 1948U, 5489U, 450U,	---
10774	2490U, 1155U, 5407U, 8011U, 1913U, 10422U, 12104U, 14540U,	---	10774	2490U, 1155U, 5407U, 8011U, 1913U, 10422U, 12104U, 14540U,	---
10775	25360U, 15679U, 11224U, 22749U, 162U, 1962U, 10371U, 11905U,	---	10775	25360U, 15679U, 11224U, 22749U, 162U, 1962U, 10371U, 11905U,	---
10776	14489U, 25160U, 27947U, 3867U, 20881U, 13893U, 2828U, 13327U,	---	10776	14489U, 25160U, 27947U, 3867U, 20881U, 13893U, 2828U, 13327U,	---
10777	18082U, 17545U, 26725U, 20696U, 18246U, 27885U, 3854U, 13557U,	---	10777	18082U, 17545U, 26725U, 20696U, 18246U, 27885U, 3854U, 13557U,	---
10778	18180U, 20851U, 17393U, 5632U, 15852U, 3255U, 8062U, 11605U,	---	10778	18180U, 20851U, 17393U, 5632U, 15852U, 3255U, 8062U, 11605U,	---
10779	8100U, 13362U, 18096U, 18962U, 6967U, 8124U, 9838U, 5768U,	---	10779	8100U, 13362U, 18096U, 18962U, 6967U, 8124U, 9838U, 5768U,	---
10780	8071U, 6921U, 174U, 1978U, 16344U, 27029U, 3702U, 20821U,	---	10780	8071U, 6921U, 174U, 1978U, 16344U, 27029U, 3702U, 20821U,	---
10781	25013U, 17554U, 3479U, 152U, 16328U, 1177U, 5469U, 8027U,	---	10781	25013U, 17554U, 3479U, 152U, 16328U, 1177U, 5469U, 8027U,	---
10782	1923U, 22377U, 19188U, 13519U, 18158U, 19130U, 16141U, 3271U,	---	10782	1923U, 22377U, 19188U, 13519U, 18158U, 19130U, 16141U, 3271U,	---
10783	13370U, 18103U, 19011U, 17430U, 5677U, 16859U, 11256U, 6019U,	---	10783	13370U, 18103U, 19011U, 17430U, 5677U, 16859U, 11256U, 6019U,	---
10784	19364U, 23214U, 3341U, 13455U, 18133U, 19628U, 19340U, 11250U,	---	10784	19364U, 23214U, 3341U, 13455U, 18133U, 19628U, 19340U, 11250U,	---
10785	20258U, 26779U, 186U, 16362U, 19688U, 20719U, 20373U, 7923U,	---	10785	20258U, 26779U, 186U, 16362U, 19688U, 20719U, 20373U, 7923U,	---
10786	27919U, 4274U, 4338U, 4306U, 4355U, 4884U, 4625U, 4510U,	---	10786	27919U, 4274U, 4338U, 4306U, 4355U, 4884U, 4625U, 4510U,	---
10787	4984U, 4641U, 4391U, 4453U, 11541U, 12066U, 6381U, 23577U,	---	10787	4984U, 4641U, 4391U, 4453U, 11541U, 12066U, 6381U, 23577U,	---
10788	7341U, 14740U, 25659U, 24675U, 22510U, 19303U, 20215U, 11008U,	---	10788	7341U, 14740U, 25659U, 24675U, 22510U, 19303U, 20215U, 11008U,	---
10789	13086U, 15264U, 26504U, 294U, 16444U, 2277U, 22398U, 19218U,	---	10789	13086U, 15264U, 26504U, 294U, 16444U, 2277U, 22398U, 19218U,	---
10790	18011U, 14713U, 25632U, 23472U, 19754U, 15773U, 18892U, 22909U,	---	10790	18011U, 14713U, 25632U, 23472U, 19754U, 15773U, 18892U, 22909U,	---
10791	19500U, 15799U, 18924U, 22935U, 19532U, 11818U, 6267U, 23442U,	---	10791	19500U, 15799U, 18924U, 22935U, 19532U, 11818U, 6267U, 23442U,	---
10792	7203U, 10712U, 12597U, 14893U, 25977U, 10904U, 12962U, 15151U,	---	10792	7203U, 10712U, 12597U, 14893U, 25977U, 10904U, 12962U, 15151U,	---
10793	26371U, 10348U, 11852U, 14466U, 25107U, 13141U, 6733U, 24045U,	---	10793	26371U, 10348U, 11852U, 14466U, 25107U, 13141U, 6733U, 24045U,	---
10794	10791U, 12705U, 15000U, 7742U, 26154U, 10983U, 13070U, 15239U,	---	10794	10791U, 12705U, 15000U, 7742U, 26154U, 10983U, 13070U, 15239U,	---
10795	26479U, 10U, 5345U, 98U, 2184U, 16304U, 5387U, 1166U,	---	10795	26479U, 10U, 5345U, 98U, 2184U, 16304U, 5387U, 1166U,	---
10796	5427U, 16U, 16258U, 5355U, 245U, 16380U, 2193U, 16916U,	---	10796	5427U, 16U, 16258U, 5355U, 245U, 16380U, 2193U, 16916U,	---
10797	5437U, 22U, 16267U, 15336U, 17383U, 2844U, 22438U, 19230U,	---	10797	5437U, 22U, 16267U, 15336U, 17383U, 2844U, 22438U, 19230U,	---
10798	18663U, 22088U, 17448U, 3289U, 22473U, 19254U, 19052U, 23161U,	---	10798	18663U, 22088U, 17448U, 3289U, 22473U, 19254U, 19052U, 23161U,	---
10799	11805U, 6255U, 23435U, 7191U, 10694U, 12579U, 14875U, 25959U,	---	10799	11805U, 6255U, 23435U, 7191U, 10694U, 12579U, 14875U, 25959U,	---
10800	10886U, 12944U, 15133U, 26353U, 10331U, 11834U, 14449U, 25089U,	---	10800	10886U, 12944U, 15133U, 26353U, 10331U, 11834U, 14449U, 25089U,	---
10801	12278U, 6477U, 23725U, 10721U, 12606U, 14902U, 7461U, 25995U,	---	10801	12278U, 6477U, 23725U, 10721U, 12606U, 14902U, 7461U, 25995U,	---
10802	10913U, 12971U, 15160U, 26380U, 11765U, 10239U, 17926U, 24682U,	---	10802	10913U, 12971U, 15160U, 26380U, 11765U, 10239U, 17926U, 24682U,	---
10803	7851U, 6246U, 10661U, 12546U, 14842U, 25926U, 10853U, 12911U,	---	10803	7851U, 6246U, 10661U, 12546U, 14842U, 25926U, 10853U, 12911U,	---
10804	15100U, 26320U, 17355U, 5598U, 19112U, 7063U, 24948U, 362U,	---	10804	15100U, 26320U, 17355U, 5598U, 19112U, 7063U, 24948U, 362U,	---
10805	16533U, 2345U, 15466U, 2980U, 18730U, 23592U, 19829U, 2222U,	---	10805	16533U, 2345U, 15466U, 2980U, 18730U, 23592U, 19829U, 2222U,	---
10806	15444U, 2873U, 23413U, 409U, 16568U, 2392U, 15492U, 3010U,	---	10806	15444U, 2873U, 23413U, 409U, 16568U, 2392U, 15492U, 3010U,	---
10807	18740U, 23639U, 19858U, 626U, 16798U, 2666U, 15542U, 3184U,	---	10807	18740U, 23639U, 19858U, 626U, 16798U, 2666U, 15542U, 3184U,	---
10808	18750U, 23952U, 20042U, 2235U, 15455U, 2886U, 23424U, 420U,	---	10808	18750U, 23952U, 20042U, 2235U, 15455U, 2886U, 23424U, 420U,	---
10809	16582U, 2403U, 15501U, 3021U, 18760U, 23648U, 19870U, 10290U,	---	10809	16582U, 2403U, 15501U, 3021U, 18760U, 23648U, 19870U, 10290U,	---
10810	12058U, 6368U, 23569U, 7328U, 14730U, 25649U, 24663U, 22500U,	---	10810	12058U, 6368U, 23569U, 7328U, 14730U, 25649U, 24663U, 22500U,	---
10811	19290U, 20200U, 11000U, 13078U, 15256U, 26496U, 275U, 16419U,	---	10811	19290U, 20200U, 11000U, 13078U, 15256U, 26496U, 275U, 16419U,	---
10812	2258U, 22389U, 19206U, 17942U, 14704U, 25623U, 23457U, 19733U,	---	10812	2258U, 22389U, 19206U, 17942U, 14704U, 25623U, 23457U, 19733U,	---
10813	50U, 5377U, 135U, 2213U, 16942U, 16320U, 5397U, 1172U,	---	10813	50U, 5377U, 135U, 2213U, 16942U, 16320U, 5397U, 1172U,	---
10814	5459U, 37U, 16287U, 5366U, 255U, 16393U, 2203U, 16929U,	---	10814	5459U, 37U, 16287U, 5366U, 255U, 16393U, 2203U, 16929U,	---
10815	5448U, 29U, 16277U, 15368U, 2866U, 22464U, 19242U, 18687U,	---	10815	5448U, 29U, 16277U, 15368U, 2866U, 22464U, 19242U, 18687U,	---
10816	22257U, 19138U, 22105U, 3296U, 22482U, 19266U, 19069U, 66U,	---	10816	22257U, 19138U, 22105U, 3296U, 22482U, 19266U, 19069U, 66U,	---
10817	198U, 1195U, 71U, 211U, 1200U, 23190U, 14431U, 24713U,	---	10817	198U, 1195U, 71U, 211U, 1200U, 23190U, 14431U, 24713U,	---
10818	7861U, 6864U, 16044U, 15811U, 18939U, 22947U, 19547U, 15613U,	---	10818	7861U, 6864U, 16044U, 15811U, 18939U, 22947U, 19547U, 15613U,	---
10819	18811U, 22645U, 19400U, 14117U, 18419U, 25828U, 1884U, 14167U,	---	10819	18811U, 22645U, 19400U, 14117U, 18419U, 25828U, 1884U, 14167U,	---
10820	1541U, 26030U, 1899U, 3411U, 14750U, 25669U, 14355U, 18563U,	---	10820	1541U, 26030U, 1899U, 3411U, 14750U, 25669U, 14355U, 18563U,	---
10821	14295U, 1640U, 24347U, 22520U, 19316U, 22491U, 19278U, 20179U,	---	10821	14295U, 1640U, 24347U, 22520U, 19316U, 22491U, 19278U, 20179U,	---
10822	27901U, 20872U, 24733U, 7882U, 11032U, 13117U, 15288U, 26535U,	---	10822	27901U, 20872U, 24733U, 7882U, 11032U, 13117U, 15288U, 26535U,	---
10823	19004U, 6984U, 14035U, 1483U, 14722U, 25641U, 8131U, 14138U,	---	10823	19004U, 6984U, 14035U, 1483U, 14722U, 25641U, 8131U, 14138U,	---
10824	1527U, 4850U, 4977U, 4164U, 3887U, 10356U, 11875U, 14474U,	---	10824	1527U, 4850U, 4977U, 4164U, 3887U, 10356U, 11875U, 14474U,	---
10825	25130U, 10363U, 11882U, 14481U, 25137U, 293U, 16443U, 2276U,	---	10825	25130U, 10363U, 11882U, 14481U, 25137U, 293U, 16443U, 2276U,	---
10826	23471U, 19753U, 274U, 16418U, 2257U, 23456U, 19732U, 22990U,	---	10826	23471U, 19753U, 274U, 16418U, 2257U, 23456U, 19732U, 22990U,	---
10827	3321U, 10505U, 19578U, 7129U, 24962U, 17507U, 5723U, 5045U,	---	10827	3321U, 10505U, 19578U, 7129U, 24962U, 17507U, 5723U, 5045U,	---
10828	5086U, 22991U, 17488U, 5713U, 3322U, 10506U, 6903U, 19579U,	---	10828	5086U, 22991U, 17488U, 5713U, 3322U, 10506U, 6903U, 19579U,	---
10829	7130U, 24963U, 27008U, 3689U, 20806U, 5185U, 14025U, 18344U,	---	10829	7130U, 24963U, 27008U, 3689U, 20806U, 5185U, 14025U, 18344U,	---
10830	13478U, 18149U, 6795U, 11016U, 13094U, 15272U, 26512U, 10376U,	---	10830	13478U, 18149U, 6795U, 11016U, 13094U, 15272U, 26512U, 10376U,	---
10831	11910U, 14494U, 25165U, 10823U, 12807U, 15032U, 26216U, 13993U,	---	10831	11910U, 14494U, 25165U, 10823U, 12807U, 15032U, 26216U, 13993U,	---
10832	18311U, 9984U, 17720U, 3373U, 3421U, 22285U, 15642U, 8484U,	---	10832	18311U, 9984U, 17720U, 3373U, 3421U, 22285U, 15642U, 8484U,	---
10833	17608U, 18846U, 22674U, 8534U, 17645U, 19435U, 15786U, 18908U,	---	10833	17608U, 18846U, 22674U, 8534U, 17645U, 19435U, 15786U, 18908U,	---
10834	22922U, 19516U, 15628U, 8469U, 17590U, 18829U, 22660U, 8519U,	---	10834	22922U, 19516U, 15628U, 8469U, 17590U, 18829U, 22660U, 8519U,	---
10835	17627U, 19418U, 13937U, 18279U, 25292U, 20433U, 13912U, 18263U,	---	10835	17627U, 19418U, 13937U, 18279U, 25292U, 20433U, 13912U, 18263U,	---
10836	25321U, 20448U, 13925U, 1425U, 25277U, 1786U, 25304U, 1806U,	---	10836	25321U, 20448U, 13925U, 1425U, 25277U, 1786U, 25304U, 1806U,	---
10837	13618U, 13303U, 18057U, 20687U, 18196U, 6806U, 8116U, 11664U,	---	10837	13618U, 13303U, 18057U, 20687U, 18196U, 6806U, 8116U, 11664U,	---
10838	1400U, 3392U, 3430U, 10225U, 17906U, 22351U, 19170U, 23208U,	---	10838	1400U, 3392U, 3430U, 10225U, 17906U, 22351U, 19170U, 23208U,	---
10839	3333U, 19619U, 7171U, 7147U, 483U, 16633U, 2523U, 17128U,	---	10839	3333U, 19619U, 7171U, 7147U, 483U, 16633U, 2523U, 17128U,	---
10840	23757U, 19924U, 14268U, 18536U, 10207U, 17882U, 14009U, 18333U,	---	10840	23757U, 19924U, 14268U, 18536U, 10207U, 17882U, 14009U, 18333U,	---
10841	10000U, 17742U, 12815U, 6650U, 23929U, 7634U, 23167U, 24931U,	---	10841	10000U, 17742U, 12815U, 6650U, 23929U, 7634U, 23167U, 24931U,	---
10842	20356U, 19592U, 2445U, 6420U, 23688U, 7404U, 692U, 2726U,	---	10842	20356U, 19592U, 2445U, 6420U, 23688U, 7404U, 692U, 2726U,	---
10843	6689U, 20422U, 24008U, 20085U, 7685U, 616U, 16785U, 2656U,	---	10843	6689U, 20422U, 24008U, 20085U, 7685U, 616U, 16785U, 2656U,	---
10844	17268U, 23944U, 20031U, 4805U, 4181U, 8465U, 11348U, 10756U,	---	10844	17268U, 23944U, 20031U, 4805U, 4181U, 8465U, 11348U, 10756U,	---
10845	12650U, 14955U, 26075U, 10959U, 13026U, 15215U, 26435U, 10236U,	---	10845	12650U, 14955U, 26075U, 10959U, 13026U, 15215U, 26435U, 10236U,	---
10846	17329U, 5517U, 2039U, 13193U, 18033U, 17920U, 5808U, 11269U,	---	10846	17329U, 5517U, 2039U, 13193U, 18033U, 17920U, 5808U, 11269U,	---
10847	2102U, 8054U, 11450U, 8093U, 13246U, 18040U, 17972U, 6050U,	---	10847	2102U, 8054U, 11450U, 8093U, 13246U, 18040U, 17972U, 6050U,	---
10848	8087U, 11786U, 22215U, 17458U, 5699U, 19085U, 7052U, 8146U,	---	10848	8087U, 11786U, 22215U, 17458U, 5699U, 19085U, 7052U, 8146U,	---
10849	87U, 1955U, 5503U, 462U, 2502U, 1160U, 5417U, 8019U,	---	10849	87U, 1955U, 5503U, 462U, 2502U, 1160U, 5417U, 8019U,	---
10850	1918U, 24829U, 20283U, 15683U, 22753U, 168U, 1970U, 9871U,	---	10850	1918U, 24829U, 20283U, 15683U, 22753U, 168U, 1970U, 9871U,	---
10851	1994U, 17671U, 13884U, 2822U, 18239U, 26870U, 3524U, 13167U,	---	10851	1994U, 17671U, 13884U, 2822U, 18239U, 26870U, 3524U, 13167U,	---
10852	6758U, 7973U, 24060U, 7767U, 26837U, 3515U, 13152U, 6744U,	---	10852	6758U, 7973U, 24060U, 7767U, 26837U, 3515U, 13152U, 6744U,	---
10853	7952U, 24051U, 7753U, 12214U, 6394U, 23657U, 7366U, 22632U,	---	10853	7952U, 24051U, 7753U, 12214U, 6394U, 23657U, 7366U, 22632U,	---
10854	27002U, 14427U, 17365U, 5610U, 2833U, 13331U, 18089U, 10401U,	---	10854	27002U, 14427U, 17365U, 5610U, 2833U, 13331U, 18089U, 10401U,	---
10855	14519U, 25264U, 22093U, 24909U, 20326U, 19060U, 14259U, 18524U,	---	10855	14519U, 25264U, 22093U, 24909U, 20326U, 19060U, 14259U, 18524U,	---
10856	10198U, 17870U, 14207U, 18485U, 26144U, 20663U, 14001U, 18322U,	---	10856	10198U, 17870U, 14207U, 18485U, 26144U, 20663U, 14001U, 18322U,	---
10857	9992U, 17731U, 14128U, 18433U, 25986U, 20604U, 14250U, 18512U,	---	10857	9992U, 17731U, 14128U, 18433U, 25986U, 20604U, 14250U, 18512U,	---
10858	10189U, 1386U, 14106U, 18405U, 10090U, 1337U, 25801U, 20551U,	---	10858	10189U, 1386U, 14106U, 18405U, 10090U, 1337U, 25801U, 20551U,	---
10859	13904U, 18252U, 9910U, 1213U, 14074U, 18392U, 10058U, 1290U,	---	10859	13904U, 18252U, 9910U, 1213U, 14074U, 18392U, 10058U, 1290U,	---
10860	25763U, 20527U, 14277U, 1612U, 10216U, 17894U, 14017U, 1470U,	---	10860	25763U, 20527U, 14277U, 1612U, 10216U, 17894U, 14017U, 1470U,	---
10861	10008U, 17753U, 18595U, 6856U, 13335U, 6783U, 10421U, 12103U,	---	10861	10008U, 17753U, 18595U, 6856U, 13335U, 6783U, 10421U, 12103U,	---
10862	14539U, 25359U, 10370U, 11904U, 14488U, 25159U, 15973U, 17412U,	---	10862	14539U, 25359U, 10370U, 11904U, 14488U, 25159U, 15973U, 17412U,	---
10863	5655U, 1030U, 3584U, 10451U, 12118U, 14554U, 25374U, 24883U,	---	10863	5655U, 1030U, 3584U, 10451U, 12118U, 14554U, 25374U, 24883U,	---
10864	20299U, 10583U, 12227U, 14657U, 18990U, 6975U, 25477U, 24332U,	---	10864	20299U, 10583U, 12227U, 14657U, 18990U, 6975U, 25477U, 24332U,	---
10865	3462U, 20159U, 27012U, 3695U, 20813U, 27975U, 3879U, 20894U,	---	10865	3462U, 20159U, 27012U, 3695U, 20813U, 27975U, 3879U, 20894U,	---
10866	27889U, 3860U, 20858U, 13400U, 26997U, 10528U, 12181U, 14617U,	---	10866	27889U, 3860U, 20858U, 13400U, 26997U, 10528U, 12181U, 14617U,	---
10867	25437U, 10808U, 12722U, 15017U, 26171U, 8551U, 10414U, 12096U,	---	10867	25437U, 10808U, 12722U, 15017U, 26171U, 8551U, 10414U, 12096U,	---
10868	14532U, 25352U, 10481U, 12148U, 14584U, 25404U, 10616U, 12394U,	---	10868	14532U, 25352U, 10481U, 12148U, 14584U, 25404U, 10616U, 12394U,	---
10869	14759U, 25678U, 24784U, 20265U, 10317U, 11812U, 14435U, 17664U,	---	10869	14759U, 25678U, 24784U, 20265U, 10317U, 11812U, 14435U, 17664U,	---
10870	25074U, 16004U, 17421U, 5666U, 10458U, 12125U, 14561U, 25381U,	---	10870	25074U, 16004U, 17421U, 5666U, 10458U, 12125U, 14561U, 25381U,	---
10871	10497U, 12164U, 14600U, 25420U, 10630U, 12414U, 14773U, 25698U,	---	10871	10497U, 12164U, 14600U, 25420U, 10630U, 12414U, 14773U, 25698U,	---
10872	24889U, 20307U, 10589U, 12249U, 14663U, 18997U, 25499U, 22278U,	---	10872	24889U, 20307U, 10589U, 12249U, 14663U, 18997U, 25499U, 22278U,	---
10873	19148U, 7074U, 10839U, 12848U, 15048U, 26257U, 10242U, 13969U,	---	10873	19148U, 7074U, 10839U, 12848U, 15048U, 26257U, 10242U, 13969U,	---
10874	1442U, 14084U, 1495U, 25772U, 1854U, 25336U, 1828U, 14042U,	---	10874	1442U, 14084U, 1495U, 25772U, 1854U, 25336U, 1828U, 14042U,	---
10875	18357U, 14147U, 18446U, 26012U, 20616U, 10948U, 13015U, 15204U,	---	10875	18357U, 14147U, 18446U, 26012U, 20616U, 10948U, 13015U, 15204U,	---
10876	26424U, 10772U, 12686U, 14971U, 26125U, 10738U, 12632U, 14937U,	---	10876	26424U, 10772U, 12686U, 14971U, 26125U, 10738U, 12632U, 14937U,	---
10877	26057U, 10930U, 12997U, 15186U, 26406U, 17525U, 5734U, 9960U,	---	10877	26057U, 10930U, 12997U, 15186U, 26406U, 17525U, 5734U, 9960U,	---
10878	1244U, 10068U, 1305U, 7831U, 14234U, 1586U, 10173U, 17848U,	---	10878	1244U, 10068U, 1305U, 7831U, 14234U, 1586U, 10173U, 17848U,	---
10879	14187U, 1556U, 10111U, 17793U, 10545U, 12198U, 14634U, 25454U,	---	10879	14187U, 1556U, 10111U, 17793U, 10545U, 12198U, 14634U, 25454U,	---
10880	11001U, 13079U, 15257U, 26497U, 17929U, 5816U, 27868U, 20835U,	---	10880	11001U, 13079U, 15257U, 26497U, 17929U, 5816U, 27868U, 20835U,	---
10881	180U, 1986U, 16353U, 25023U, 17562U, 5758U, 3496U, 157U,	---	10881	180U, 1986U, 16353U, 25023U, 17562U, 5758U, 3496U, 157U,	---
10882	16336U, 1182U, 5479U, 8035U, 1928U, 22383U, 19197U, 13523U,	---	10882	16336U, 1182U, 5479U, 8035U, 1928U, 22383U, 19197U, 13523U,	---
10883	18165U, 16145U, 3277U, 13375U, 18111U, 19018U, 17439U, 5688U,	---	10883	18165U, 16145U, 3277U, 13375U, 18111U, 19018U, 17439U, 5688U,	---
10884	16868U, 19371U, 23218U, 3347U, 13460U, 18141U, 19635U, 19348U,	---	10884	16868U, 19371U, 23218U, 3347U, 13460U, 18141U, 19635U, 19348U,	---
10885	7101U, 192U, 16371U, 20379U, 7931U, 11202U, 15306U, 18626U,	---	10885	7101U, 192U, 16371U, 20379U, 7931U, 11202U, 15306U, 18626U,	---
10886	6873U, 17950U, 5973U, 15863U, 18979U, 4829U, 4192U, 4290U,	---	10886	6873U, 17950U, 5973U, 15863U, 18979U, 4829U, 4192U, 4290U,	---
10887	4996U, 5012U, 4322U, 4260U, 5151U, 5065U, 4906U, 4534U,	---	10887	4996U, 5012U, 4322U, 4260U, 5151U, 5065U, 4906U, 4534U,	---
10888	4918U, 4561U, 5096U, 4174U, 5130U, 4267U, 5162U, 5221U,	---	10888	4918U, 4561U, 5096U, 4174U, 5130U, 4267U, 5162U, 5221U,	---
10889	4407U, 4466U, 22636U, 15379U, 18695U, 19385U, 13317U, 15315U,	---	10889	4407U, 4466U, 22636U, 15379U, 18695U, 19385U, 13317U, 15315U,	---
10890	24718U, 20232U, 18641U, 24697U, 20224U, 18066U, 24901U, 13645U,	---	10890	24718U, 20232U, 18641U, 24697U, 20224U, 18066U, 24901U, 13645U,	---
10891	18204U, 20315U, 22251U, 19121U, 22869U, 19491U, 15429U, 18720U,	---	10891	18204U, 20315U, 22251U, 19121U, 22869U, 19491U, 15429U, 18720U,	---
10892	23201U, 19609U, 24894U, 13637U, 6816U, 7911U, 22221U, 19094U,	---	10892	23201U, 19609U, 24894U, 13637U, 6816U, 7911U, 22221U, 19094U,	---
10893	22640U, 19392U, 15423U, 18711U, 23195U, 19600U, 24336U, 15398U,	---	10893	22640U, 19392U, 15423U, 18711U, 23195U, 19600U, 24336U, 15398U,	---
10894	20241U, 18703U, 24766U, 20250U, 20166U, 13404U, 15320U, 18649U,	---	10894	20241U, 18703U, 24766U, 20250U, 20166U, 13404U, 15320U, 18649U,	---
10895	18126U, 2433U, 6405U, 23678U, 7389U, 680U, 2714U, 6674U,	---	10895	18126U, 2433U, 6405U, 23678U, 7389U, 680U, 2714U, 6674U,	---
10896	20411U, 23998U, 20072U, 7670U, 24724U, 24859U, 20291U, 24731U,	---	10896	20411U, 23998U, 20072U, 7670U, 24724U, 24859U, 20291U, 24731U,	---
10897	61U, 24744U, 10400U, 12074U, 14518U, 25263U, 24251U, 20151U,	---	10897	61U, 24744U, 10400U, 12074U, 14518U, 25263U, 24251U, 20151U,	---
10898	7792U, 22357U, 19179U, 7159U, 13871U, 18231U, 6846U, 23052U,	---	10898	7792U, 22357U, 19179U, 7159U, 13871U, 18231U, 6846U, 23052U,	---
10899	17487U, 5712U, 3327U, 10512U, 6902U, 19585U, 7138U, 24968U,	---	10899	17487U, 5712U, 3327U, 10512U, 6902U, 19585U, 7138U, 24968U,	---
10900	27007U, 3688U, 20805U, 5196U, 11599U,	---	10900	27007U, 3688U, 20805U, 5196U, 11599U,	---
10901	};	---	10901	};	---
10902		---	10902		---
10903	static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {	1	10903	static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {	1
10904	II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	1	10904	II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	1
10905	}	1	10905	}	1
10906		---	10906		---
10907	} // end namespace llvm	---	10907	} // end namespace llvm	---
10908	#endif // GET_INSTRINFO_MC_DESC	---	10908	#endif // GET_INSTRINFO_MC_DESC	---
10909		---	10909		---
10910	#ifdef GET_INSTRINFO_HEADER	---	10910	#ifdef GET_INSTRINFO_HEADER	---
10911	#undef GET_INSTRINFO_HEADER	---	10911	#undef GET_INSTRINFO_HEADER	---
10912	namespace llvm {	---	10912	namespace llvm {	---
10913	struct MipsGenInstrInfo : public TargetInstrInfo {	---	10913	struct MipsGenInstrInfo : public TargetInstrInfo {	---
10914	explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);	---	10914	explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);	---
10915	~MipsGenInstrInfo() override = default;	5	10915	~MipsGenInstrInfo() override = default;	5
10916		---	10916		---
10917	};	---	10917	};	---
10918	} // end namespace llvm	---	10918	} // end namespace llvm	---
10919	#endif // GET_INSTRINFO_HEADER	---	10919	#endif // GET_INSTRINFO_HEADER	---
10920		---	10920		---
10921	#ifdef GET_INSTRINFO_HELPER_DECLS	---	10921	#ifdef GET_INSTRINFO_HELPER_DECLS	---
10922	#undef GET_INSTRINFO_HELPER_DECLS	---	10922	#undef GET_INSTRINFO_HELPER_DECLS	---
10923		---	10923		---
10924		---	10924		---
10925	#endif // GET_INSTRINFO_HELPER_DECLS	---	10925	#endif // GET_INSTRINFO_HELPER_DECLS	---
10926		---	10926		---
10927	#ifdef GET_INSTRINFO_HELPERS	---	10927	#ifdef GET_INSTRINFO_HELPERS	---
10928	#undef GET_INSTRINFO_HELPERS	---	10928	#undef GET_INSTRINFO_HELPERS	---
10929		---	10929		---
10930	#endif // GET_INSTRINFO_HELPERS	---	10930	#endif // GET_INSTRINFO_HELPERS	---
10931		---	10931		---
10932	#ifdef GET_INSTRINFO_CTOR_DTOR	---	10932	#ifdef GET_INSTRINFO_CTOR_DTOR	---
10933	#undef GET_INSTRINFO_CTOR_DTOR	---	10933	#undef GET_INSTRINFO_CTOR_DTOR	---
10934	namespace llvm {	---	10934	namespace llvm {	---
10935	extern const MipsInstrTable MipsDescs;	---	10935	extern const MipsInstrTable MipsDescs;	---
10936	extern const unsigned MipsInstrNameIndices[];	---	10936	extern const unsigned MipsInstrNameIndices[];	---
10937	extern const char MipsInstrNameData[];	---	10937	extern const char MipsInstrNameData[];	---
10938	MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)	5	10938	MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)	5
10939	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {	5	10939	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {	5
10940	InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	5	10940	InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2853);	5
10941	}	5	10941	}	5
10942	} // end namespace llvm	---	10942	} // end namespace llvm	---
10943	#endif // GET_INSTRINFO_CTOR_DTOR	---	10943	#endif // GET_INSTRINFO_CTOR_DTOR	---
10944		---	10944		---
10945	#ifdef GET_INSTRINFO_OPERAND_ENUM	---	10945	#ifdef GET_INSTRINFO_OPERAND_ENUM	---
10946	#undef GET_INSTRINFO_OPERAND_ENUM	---	10946	#undef GET_INSTRINFO_OPERAND_ENUM	---
10947	namespace llvm {	---	10947	namespace llvm {	---
10948	namespace Mips {	---	10948	namespace Mips {	---
10949	namespace OpName {	---	10949	namespace OpName {	---
10950	enum {	---	10950	enum {	---
10951	OPERAND_LAST	---	10951	OPERAND_LAST	---
10952	};	---	10952	};	---
10953	} // end namespace OpName	---	10953	} // end namespace OpName	---
10954	} // end namespace Mips	---	10954	} // end namespace Mips	---
10955	} // end namespace llvm	---	10955	} // end namespace llvm	---
10956	#endif //GET_INSTRINFO_OPERAND_ENUM	---	10956	#endif //GET_INSTRINFO_OPERAND_ENUM	---
10957		---	10957		---
10958	#ifdef GET_INSTRINFO_NAMED_OPS	---	10958	#ifdef GET_INSTRINFO_NAMED_OPS	---
10959	#undef GET_INSTRINFO_NAMED_OPS	---	10959	#undef GET_INSTRINFO_NAMED_OPS	---
10960	namespace llvm {	---	10960	namespace llvm {	---
10961	namespace Mips {	---	10961	namespace Mips {	---
10962	LLVM_READONLY	---	10962	LLVM_READONLY	---
10963	int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {	---	10963	int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {	---
10964	return -1;	---	10964	return -1;	---
10965	}	---	10965	}	---
10966	} // end namespace Mips	---	10966	} // end namespace Mips	---
10967	} // end namespace llvm	---	10967	} // end namespace llvm	---
10968	#endif //GET_INSTRINFO_NAMED_OPS	---	10968	#endif //GET_INSTRINFO_NAMED_OPS	---
10969		---	10969		---
10970	#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM	---	10970	#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM	---
10971	#undef GET_INSTRINFO_OPERAND_TYPES_ENUM	---	10971	#undef GET_INSTRINFO_OPERAND_TYPES_ENUM	---
10972	namespace llvm {	---	10972	namespace llvm {	---
10973	namespace Mips {	---	10973	namespace Mips {	---
10974	namespace OpTypes {	---	10974	namespace OpTypes {	---
10975	enum OperandType {	---	10975	enum OperandType {	---
10976	InvertedImOperand = 0,	---	10976	InvertedImOperand = 0,	---
10977	InvertedImOperand64 = 1,	---	10977	InvertedImOperand64 = 1,	---
10978	PtrRC = 2,	---	10978	PtrRC = 2,	---
10979	brtarget = 3,	---	10979	brtarget = 3,	---
10980	brtarget1SImm16 = 4,	---	10980	brtarget1SImm16 = 4,	---
10981	brtarget7_mm = 5,	---	10981	brtarget7_mm = 5,	---
10982	brtarget10_mm = 6,	---	10982	brtarget10_mm = 6,	---
10983	brtarget21 = 7,	---	10983	brtarget21 = 7,	---
10984	brtarget21_mm = 8,	---	10984	brtarget21_mm = 8,	---
10985	brtarget26 = 9,	---	10985	brtarget26 = 9,	---
10986	brtarget26_mm = 10,	---	10986	brtarget26_mm = 10,	---
10987	brtarget_lsl2_mm = 11,	---	10987	brtarget_lsl2_mm = 11,	---
10988	brtarget_mm = 12,	---	10988	brtarget_mm = 12,	---
10989	brtargetr6 = 13,	---	10989	brtargetr6 = 13,	---
10990	calloffset16 = 14,	---	10990	calloffset16 = 14,	---
10991	calltarget = 15,	---	10991	calltarget = 15,	---
10992	calltarget_mm = 16,	---	10992	calltarget_mm = 16,	---
10993	condcode = 17,	---	10993	condcode = 17,	---
10994	cpinst_operand = 18,	---	10994	cpinst_operand = 18,	---
10995	f32imm = 19,	---	10995	f32imm = 19,	---
10996	f64imm = 20,	---	10996	f64imm = 20,	---
10997	i1imm = 21,	---	10997	i1imm = 21,	---
10998	i8imm = 22,	---	10998	i8imm = 22,	---
10999	i16imm = 23,	---	10999	i16imm = 23,	---
11000	i32imm = 24,	---	11000	i32imm = 24,	---
11001	i64imm = 25,	---	11001	i64imm = 25,	---
11002	imm64 = 26,	---	11002	imm64 = 26,	---
11003	jmpoffset16 = 27,	---	11003	jmpoffset16 = 27,	---
11004	jmptarget = 28,	---	11004	jmptarget = 28,	---
11005	jmptarget_mm = 29,	---	11005	jmptarget_mm = 29,	---
11006	li16_imm = 30,	---	11006	li16_imm = 30,	---
11007	mem = 31,	---	11007	mem = 31,	---
11008	mem16 = 32,	---	11008	mem16 = 32,	---
11009	mem16_ea = 33,	---	11009	mem16_ea = 33,	---
11010	mem16sp = 34,	---	11010	mem16sp = 34,	---
11011	mem_ea = 35,	---	11011	mem_ea = 35,	---
11012	mem_mm_4 = 36,	---	11012	mem_mm_4 = 36,	---
11013	mem_mm_4_lsl1 = 37,	---	11013	mem_mm_4_lsl1 = 37,	---
11014	mem_mm_4_lsl2 = 38,	---	11014	mem_mm_4_lsl2 = 38,	---
11015	mem_mm_4sp = 39,	---	11015	mem_mm_4sp = 39,	---
11016	mem_mm_9 = 40,	---	11016	mem_mm_9 = 40,	---
11017	mem_mm_11 = 41,	---	11017	mem_mm_11 = 41,	---
11018	mem_mm_12 = 42,	---	11018	mem_mm_12 = 42,	---
11019	mem_mm_16 = 43,	---	11019	mem_mm_16 = 43,	---
11020	mem_mm_gp_simm7_lsl2 = 44,	---	11020	mem_mm_gp_simm7_lsl2 = 44,	---
11021	mem_mm_sp_imm5_lsl2 = 45,	---	11021	mem_mm_sp_imm5_lsl2 = 45,	---
11022	mem_msa = 46,	---	11022	mem_msa = 46,	---
11023	mem_simm9 = 47,	---	11023	mem_simm9 = 47,	---
11024	mem_simm9_exp = 48,	---	11024	mem_simm9_exp = 48,	---
11025	mem_simm10 = 49,	---	11025	mem_simm10 = 49,	---
11026	mem_simm10_lsl1 = 50,	---	11026	mem_simm10_lsl1 = 50,	---
11027	mem_simm10_lsl2 = 51,	---	11027	mem_simm10_lsl2 = 51,	---
11028	mem_simm10_lsl3 = 52,	---	11028	mem_simm10_lsl3 = 52,	---
11029	mem_simm11 = 53,	---	11029	mem_simm11 = 53,	---
11030	mem_simm12 = 54,	---	11030	mem_simm12 = 54,	---
11031	mem_simm16 = 55,	---	11031	mem_simm16 = 55,	---
11032	mem_simmptr = 56,	---	11032	mem_simmptr = 56,	---
11033	pcrel16 = 57,	---	11033	pcrel16 = 57,	---
11034	ptype0 = 58,	---	11034	ptype0 = 58,	---
11035	ptype1 = 59,	---	11035	ptype1 = 59,	---
11036	ptype2 = 60,	---	11036	ptype2 = 60,	---
11037	ptype3 = 61,	---	11037	ptype3 = 61,	---
11038	ptype4 = 62,	---	11038	ptype4 = 62,	---
11039	ptype5 = 63,	---	11039	ptype5 = 63,	---
11040	reglist = 64,	---	11040	reglist = 64,	---
11041	reglist16 = 65,	---	11041	reglist16 = 65,	---
11042	simm3_lsa2 = 66,	---	11042	simm3_lsa2 = 66,	---
11043	simm4 = 67,	---	11043	simm4 = 67,	---
11044	simm5 = 68,	---	11044	simm5 = 68,	---
11045	simm6 = 69,	---	11045	simm6 = 69,	---
11046	simm7_lsl2 = 70,	---	11046	simm7_lsl2 = 70,	---
11047	simm9 = 71,	---	11047	simm9 = 71,	---
11048	simm9_addiusp = 72,	---	11048	simm9_addiusp = 72,	---
11049	simm10 = 73,	---	11049	simm10 = 73,	---
11050	simm10_64 = 74,	---	11050	simm10_64 = 74,	---
11051	simm10_lsl1 = 75,	---	11051	simm10_lsl1 = 75,	---
11052	simm10_lsl2 = 76,	---	11052	simm10_lsl2 = 76,	---
11053	simm10_lsl3 = 77,	---	11053	simm10_lsl3 = 77,	---
11054	simm11 = 78,	---	11054	simm11 = 78,	---
11055	simm12 = 79,	---	11055	simm12 = 79,	---
11056	simm16 = 80,	---	11056	simm16 = 80,	---
11057	simm16_64 = 81,	---	11057	simm16_64 = 81,	---
11058	simm16_relaxed = 82,	---	11058	simm16_relaxed = 82,	---
11059	simm18_lsl3 = 83,	---	11059	simm18_lsl3 = 83,	---
11060	simm19_lsl2 = 84,	---	11060	simm19_lsl2 = 84,	---
11061	simm23_lsl2 = 85,	---	11061	simm23_lsl2 = 85,	---
11062	simm32 = 86,	---	11062	simm32 = 86,	---
11063	simm32_relaxed = 87,	---	11063	simm32_relaxed = 87,	---
11064	size_ins = 88,	---	11064	size_ins = 88,	---
11065	type0 = 89,	---	11065	type0 = 89,	---
11066	type1 = 90,	---	11066	type1 = 90,	---
11067	type2 = 91,	---	11067	type2 = 91,	---
11068	type3 = 92,	---	11068	type3 = 92,	---
11069	type4 = 93,	---	11069	type4 = 93,	---
11070	type5 = 94,	---	11070	type5 = 94,	---
11071	uimm1 = 95,	---	11071	uimm1 = 95,	---
11072	uimm1_ptr = 96,	---	11072	uimm1_ptr = 96,	---
11073	uimm2 = 97,	---	11073	uimm2 = 97,	---
11074	uimm2_plus1 = 98,	---	11074	uimm2_plus1 = 98,	---
11075	uimm2_ptr = 99,	---	11075	uimm2_ptr = 99,	---
11076	uimm3 = 100,	---	11076	uimm3 = 100,	---
11077	uimm3_ptr = 101,	---	11077	uimm3_ptr = 101,	---
11078	uimm3_shift = 102,	---	11078	uimm3_shift = 102,	---
11079	uimm4 = 103,	---	11079	uimm4 = 103,	---
11080	uimm4_andi = 104,	---	11080	uimm4_andi = 104,	---
11081	uimm4_ptr = 105,	---	11081	uimm4_ptr = 105,	---
11082	uimm5 = 106,	---	11082	uimm5 = 106,	---
11083	uimm5_64 = 107,	---	11083	uimm5_64 = 107,	---
11084	uimm5_64_report_uimm6 = 108,	---	11084	uimm5_64_report_uimm6 = 108,	---
11085	uimm5_inssize_plus1 = 109,	---	11085	uimm5_inssize_plus1 = 109,	---
11086	uimm5_lsl2 = 110,	---	11086	uimm5_lsl2 = 110,	---
11087	uimm5_plus1 = 111,	---	11087	uimm5_plus1 = 111,	---
11088	uimm5_plus1_report_uimm6 = 112,	---	11088	uimm5_plus1_report_uimm6 = 112,	---
11089	uimm5_plus32 = 113,	---	11089	uimm5_plus32 = 113,	---
11090	uimm5_plus32_normalize = 114,	---	11090	uimm5_plus32_normalize = 114,	---
11091	uimm5_plus32_normalize_64 = 115,	---	11091	uimm5_plus32_normalize_64 = 115,	---
11092	uimm5_plus33 = 116,	---	11092	uimm5_plus33 = 116,	---
11093	uimm5_report_uimm6 = 117,	---	11093	uimm5_report_uimm6 = 117,	---
11094	uimm6 = 118,	---	11094	uimm6 = 118,	---
11095	uimm6_lsl2 = 119,	---	11095	uimm6_lsl2 = 119,	---
11096	uimm7 = 120,	---	11096	uimm7 = 120,	---
11097	uimm8 = 121,	---	11097	uimm8 = 121,	---
11098	uimm10 = 122,	---	11098	uimm10 = 122,	---
11099	uimm16 = 123,	---	11099	uimm16 = 123,	---
11100	uimm16_64 = 124,	---	11100	uimm16_64 = 124,	---
11101	uimm16_64_relaxed = 125,	---	11101	uimm16_64_relaxed = 125,	---
11102	uimm16_altrelaxed = 126,	---	11102	uimm16_altrelaxed = 126,	---
11103	uimm16_relaxed = 127,	---	11103	uimm16_relaxed = 127,	---
11104	uimm20 = 128,	---	11104	uimm20 = 128,	---
11105	uimm26 = 129,	---	11105	uimm26 = 129,	---
11106	uimm32_coerced = 130,	---	11106	uimm32_coerced = 130,	---
11107	uimm_range_2_64 = 131,	---	11107	uimm_range_2_64 = 131,	---
11108	uimmz = 132,	---	11108	uimmz = 132,	---
11109	untyped_imm_0 = 133,	---	11109	untyped_imm_0 = 133,	---
11110	vsplat_simm5 = 134,	---	11110	vsplat_simm5 = 134,	---
11111	vsplat_simm10 = 135,	---	11111	vsplat_simm10 = 135,	---
11112	vsplat_uimm1 = 136,	---	11112	vsplat_uimm1 = 136,	---
11113	vsplat_uimm2 = 137,	---	11113	vsplat_uimm2 = 137,	---
11114	vsplat_uimm3 = 138,	---	11114	vsplat_uimm3 = 138,	---
11115	vsplat_uimm4 = 139,	---	11115	vsplat_uimm4 = 139,	---
11116	vsplat_uimm5 = 140,	---	11116	vsplat_uimm5 = 140,	---
11117	vsplat_uimm6 = 141,	---	11117	vsplat_uimm6 = 141,	---
11118	vsplat_uimm8 = 142,	---	11118	vsplat_uimm8 = 142,	---
11119	ACC64DSPOpnd = 143,	---	11119	ACC64DSPOpnd = 143,	---
11120	AFGR64Opnd = 144,	---	11120	AFGR64Opnd = 144,	---
11121	CCROpnd = 145,	---	11121	CCROpnd = 145,	---
11122	COP0Opnd = 146,	---	11122	COP0Opnd = 146,	---
11123	COP2Opnd = 147,	---	11123	COP2Opnd = 147,	---
11124	COP3Opnd = 148,	---	11124	COP3Opnd = 148,	---
11125	DSPROpnd = 149,	---	11125	DSPROpnd = 149,	---
11126	FCCRegsOpnd = 150,	---	11126	FCCRegsOpnd = 150,	---
11127	FGR32Opnd = 151,	---	11127	FGR32Opnd = 151,	---
11128	FGR64Opnd = 152,	---	11128	FGR64Opnd = 152,	---
11129	FGRCCOpnd = 153,	---	11129	FGRCCOpnd = 153,	---
11130	GPR32NonZeroOpnd = 154,	---	11130	GPR32NonZeroOpnd = 154,	---
11131	GPR32Opnd = 155,	---	11131	GPR32Opnd = 155,	---
11132	GPR32ZeroOpnd = 156,	---	11132	GPR32ZeroOpnd = 156,	---
11133	GPR64Opnd = 157,	---	11133	GPR64Opnd = 157,	---
11134	GPRMM16Opnd = 158,	---	11134	GPRMM16Opnd = 158,	---
11135	GPRMM16OpndMoveP = 159,	---	11135	GPRMM16OpndMoveP = 159,	---
11136	GPRMM16OpndMovePPairFirst = 160,	---	11136	GPRMM16OpndMovePPairFirst = 160,	---
11137	GPRMM16OpndMovePPairSecond = 161,	---	11137	GPRMM16OpndMovePPairSecond = 161,	---
11138	GPRMM16OpndZero = 162,	---	11138	GPRMM16OpndZero = 162,	---
11139	HI32DSPOpnd = 163,	---	11139	HI32DSPOpnd = 163,	---
11140	HWRegsOpnd = 164,	---	11140	HWRegsOpnd = 164,	---
11141	LO32DSPOpnd = 165,	---	11141	LO32DSPOpnd = 165,	---
11142	MSA128BOpnd = 166,	---	11142	MSA128BOpnd = 166,	---
11143	MSA128CROpnd = 167,	---	11143	MSA128CROpnd = 167,	---
11144	MSA128DOpnd = 168,	---	11144	MSA128DOpnd = 168,	---
11145	MSA128F16Opnd = 169,	---	11145	MSA128F16Opnd = 169,	---
11146	MSA128HOpnd = 170,	---	11146	MSA128HOpnd = 170,	---
11147	MSA128WOpnd = 171,	---	11147	MSA128WOpnd = 171,	---
11148	StrictlyAFGR64Opnd = 172,	---	11148	StrictlyAFGR64Opnd = 172,	---
11149	StrictlyFGR32Opnd = 173,	---	11149	StrictlyFGR32Opnd = 173,	---
11150	StrictlyFGR64Opnd = 174,	---	11150	StrictlyFGR64Opnd = 174,	---
11151	ACC64 = 175,	---	11151	ACC64 = 175,	---
11152	ACC64DSP = 176,	---	11152	ACC64DSP = 176,	---
11153	ACC128 = 177,	---	11153	ACC128 = 177,	---
11154	AFGR64 = 178,	---	11154	AFGR64 = 178,	---
11155	CCR = 179,	---	11155	CCR = 179,	---
11156	COP0 = 180,	---	11156	COP0 = 180,	---
11157	COP2 = 181,	---	11157	COP2 = 181,	---
11158	COP3 = 182,	---	11158	COP3 = 182,	---
11159	CPU16Regs = 183,	---	11159	CPU16Regs = 183,	---
11160	CPU16RegsPlusSP = 184,	---	11160	CPU16RegsPlusSP = 184,	---
11161	CPURAReg = 185,	---	11161	CPURAReg = 185,	---
11162	CPUSPReg = 186,	---	11162	CPUSPReg = 186,	---
11163	DSPCC = 187,	---	11163	DSPCC = 187,	---
11164	DSPR = 188,	---	11164	DSPR = 188,	---
11165	FCC = 189,	---	11165	FCC = 189,	---
11166	FGR32 = 190,	---	11166	FGR32 = 190,	---
11167	FGR64 = 191,	---	11167	FGR64 = 191,	---
11168	FGRCC = 192,	---	11168	FGRCC = 192,	---
11169	GP32 = 193,	---	11169	GP32 = 193,	---
11170	GP64 = 194,	---	11170	GP64 = 194,	---
11171	GPR32 = 195,	---	11171	GPR32 = 195,	---
11172	GPR32NONZERO = 196,	---	11172	GPR32NONZERO = 196,	---
11173	GPR32ZERO = 197,	---	11173	GPR32ZERO = 197,	---
11174	GPR64 = 198,	---	11174	GPR64 = 198,	---
11175	GPRMM16 = 199,	---	11175	GPRMM16 = 199,	---
11176	GPRMM16MoveP = 200,	---	11176	GPRMM16MoveP = 200,	---
11177	GPRMM16MovePPairFirst = 201,	---	11177	GPRMM16MovePPairFirst = 201,	---
11178	GPRMM16MovePPairSecond = 202,	---	11178	GPRMM16MovePPairSecond = 202,	---
11179	GPRMM16Zero = 203,	---	11179	GPRMM16Zero = 203,	---
11180	HI32 = 204,	---	11180	HI32 = 204,	---
11181	HI32DSP = 205,	---	11181	HI32DSP = 205,	---
11182	HI64 = 206,	---	11182	HI64 = 206,	---
11183	HWRegs = 207,	---	11183	HWRegs = 207,	---
11184	LO32 = 208,	---	11184	LO32 = 208,	---
11185	LO32DSP = 209,	---	11185	LO32DSP = 209,	---
11186	LO64 = 210,	---	11186	LO64 = 210,	---
11187	MSA128B = 211,	---	11187	MSA128B = 211,	---
11188	MSA128D = 212,	---	11188	MSA128D = 212,	---
11189	MSA128F16 = 213,	---	11189	MSA128F16 = 213,	---
11190	MSA128H = 214,	---	11190	MSA128H = 214,	---
11191	MSA128W = 215,	---	11191	MSA128W = 215,	---
11192	MSA128WEvens = 216,	---	11192	MSA128WEvens = 216,	---
11193	MSACtrl = 217,	---	11193	MSACtrl = 217,	---
11194	OCTEON_MPL = 218,	---	11194	OCTEON_MPL = 218,	---
11195	OCTEON_P = 219,	---	11195	OCTEON_P = 219,	---
11196	SP32 = 220,	---	11196	SP32 = 220,	---
11197	SP64 = 221,	---	11197	SP64 = 221,	---
11198	OPERAND_TYPE_LIST_END	---	11198	OPERAND_TYPE_LIST_END	---
11199	};	---	11199	};	---
11200	} // end namespace OpTypes	---	11200	} // end namespace OpTypes	---
11201	} // end namespace Mips	---	11201	} // end namespace Mips	---
11202	} // end namespace llvm	---	11202	} // end namespace llvm	---
11203	#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM	---	11203	#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM	---
11204		---	11204		---
11205	#ifdef GET_INSTRINFO_OPERAND_TYPE	---	11205	#ifdef GET_INSTRINFO_OPERAND_TYPE	---
11206	#undef GET_INSTRINFO_OPERAND_TYPE	---	11206	#undef GET_INSTRINFO_OPERAND_TYPE	---
11207	namespace llvm {	---	11207	namespace llvm {	---
11208	namespace Mips {	---	11208	namespace Mips {	---
11209	LLVM_READONLY	---	11209	LLVM_READONLY	---
11210	static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {	---	11210	static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {	---
11211	static const uint16_t Offsets[] = {	---	11211	static const uint16_t Offsets[] = {	---
11212	/* PHI */	---	11212	/* PHI */	---
11213	0,	---	11213	0,	---
11214	/* INLINEASM */	---	11214	/* INLINEASM */	---
11215	1,	---	11215	1,	---
11216	/* INLINEASM_BR */	---	11216	/* INLINEASM_BR */	---
11217	1,	---	11217	1,	---
11218	/* CFI_INSTRUCTION */	---	11218	/* CFI_INSTRUCTION */	---
11219	1,	---	11219	1,	---
11220	/* EH_LABEL */	---	11220	/* EH_LABEL */	---
11221	2,	---	11221	2,	---
11222	/* GC_LABEL */	---	11222	/* GC_LABEL */	---
11223	3,	---	11223	3,	---
11224	/* ANNOTATION_LABEL */	---	11224	/* ANNOTATION_LABEL */	---
11225	4,	---	11225	4,	---
11226	/* KILL */	---	11226	/* KILL */	---
11227	5,	---	11227	5,	---
11228	/* EXTRACT_SUBREG */	---	11228	/* EXTRACT_SUBREG */	---
11229	5,	---	11229	5,	---
11230	/* INSERT_SUBREG */	---	11230	/* INSERT_SUBREG */	---
11231	8,	---	11231	8,	---
11232	/* IMPLICIT_DEF */	---	11232	/* IMPLICIT_DEF */	---
11233	12,	---	11233	12,	---
11234	/* SUBREG_TO_REG */	---	11234	/* SUBREG_TO_REG */	---
11235	13,	---	11235	13,	---
11236	/* COPY_TO_REGCLASS */	---	11236	/* COPY_TO_REGCLASS */	---
11237	17,	---	11237	17,	---
11238	/* DBG_VALUE */	---	11238	/* DBG_VALUE */	---
11239	20,	---	11239	20,	---
11240	/* DBG_VALUE_LIST */	---	11240	/* DBG_VALUE_LIST */	---
11241	20,	---	11241	20,	---
11242	/* DBG_INSTR_REF */	---	11242	/* DBG_INSTR_REF */	---
11243	20,	---	11243	20,	---
11244	/* DBG_PHI */	---	11244	/* DBG_PHI */	---
11245	20,	---	11245	20,	---
11246	/* DBG_LABEL */	---	11246	/* DBG_LABEL */	---
11247	20,	---	11247	20,	---
11248	/* REG_SEQUENCE */	---	11248	/* REG_SEQUENCE */	---
11249	21,	---	11249	21,	---
11250	/* COPY */	---	11250	/* COPY */	---
11251	23,	---	11251	23,	---
11252	/* BUNDLE */	---	11252	/* BUNDLE */	---
11253	25,	---	11253	25,	---
11254	/* LIFETIME_START */	---	11254	/* LIFETIME_START */	---
11255	25,	---	11255	25,	---
11256	/* LIFETIME_END */	---	11256	/* LIFETIME_END */	---
11257	26,	---	11257	26,	---
11258	/* PSEUDO_PROBE */	---	11258	/* PSEUDO_PROBE */	---
11259	27,	---	11259	27,	---
11260	/* ARITH_FENCE */	---	11260	/* ARITH_FENCE */	---
11261	31,	---	11261	31,	---
11262	/* STACKMAP */	---	11262	/* STACKMAP */	---
11263	33,	---	11263	33,	---
11264	/* FENTRY_CALL */	---	11264	/* FENTRY_CALL */	---
11265	35,	---	11265	35,	---
11266	/* PATCHPOINT */	---	11266	/* PATCHPOINT */	---
11267	35,	---	11267	35,	---
11268	/* LOAD_STACK_GUARD */	---	11268	/* LOAD_STACK_GUARD */	---
11269	41,	---	11269	41,	---
11270	/* PREALLOCATED_SETUP */	---	11270	/* PREALLOCATED_SETUP */	---
11271	42,	---	11271	42,	---
11272	/* PREALLOCATED_ARG */	---	11272	/* PREALLOCATED_ARG */	---
11273	43,	---	11273	43,	---
11274	/* STATEPOINT */	---	11274	/* STATEPOINT */	---
11275	46,	---	11275	46,	---
11276	/* LOCAL_ESCAPE */	---	11276	/* LOCAL_ESCAPE */	---
11277	46,	---	11277	46,	---
11278	/* FAULTING_OP */	---	11278	/* FAULTING_OP */	---
11279	48,	---	11279	48,	---
11280	/* PATCHABLE_OP */	---	11280	/* PATCHABLE_OP */	---
11281	49,	---	11281	49,	---
11282	/* PATCHABLE_FUNCTION_ENTER */	---	11282	/* PATCHABLE_FUNCTION_ENTER */	---
11283	49,	---	11283	49,	---
11284	/* PATCHABLE_RET */	---	11284	/* PATCHABLE_RET */	---
11285	49,	---	11285	49,	---
11286	/* PATCHABLE_FUNCTION_EXIT */	---	11286	/* PATCHABLE_FUNCTION_EXIT */	---
11287	49,	---	11287	49,	---
11288	/* PATCHABLE_TAIL_CALL */	---	11288	/* PATCHABLE_TAIL_CALL */	---
11289	49,	---	11289	49,	---
11290	/* PATCHABLE_EVENT_CALL */	---	11290	/* PATCHABLE_EVENT_CALL */	---
11291	49,	---	11291	49,	---
11292	/* PATCHABLE_TYPED_EVENT_CALL */	---	11292	/* PATCHABLE_TYPED_EVENT_CALL */	---
11293	51,	---	11293	51,	---
11294	/* ICALL_BRANCH_FUNNEL */	---	11294	/* ICALL_BRANCH_FUNNEL */	---
11295	54,	---	11295	54,	---
11296	/* MEMBARRIER */	---	11296	/* MEMBARRIER */	---
11297	54,	---	11297	54,	---
11298	/* G_ASSERT_SEXT */	---	11298	/* G_ASSERT_SEXT */	---
11299	54,	---	11299	54,	---
11300	/* G_ASSERT_ZEXT */	---	11300	/* G_ASSERT_ZEXT */	---
11301	57,	---	11301	57,	---
11302	/* G_ASSERT_ALIGN */	---	11302	/* G_ASSERT_ALIGN */	---
11303	60,	---	11303	60,	---
11304	/* G_ADD */	---	11304	/* G_ADD */	---
11305	63,	---	11305	63,	---
11306	/* G_SUB */	---	11306	/* G_SUB */	---
11307	66,	---	11307	66,	---
11308	/* G_MUL */	---	11308	/* G_MUL */	---
11309	69,	---	11309	69,	---
11310	/* G_SDIV */	---	11310	/* G_SDIV */	---
11311	72,	---	11311	72,	---
11312	/* G_UDIV */	---	11312	/* G_UDIV */	---
11313	75,	---	11313	75,	---
11314	/* G_SREM */	---	11314	/* G_SREM */	---
11315	78,	---	11315	78,	---
11316	/* G_UREM */	---	11316	/* G_UREM */	---
11317	81,	---	11317	81,	---
11318	/* G_SDIVREM */	---	11318	/* G_SDIVREM */	---
11319	84,	---	11319	84,	---
11320	/* G_UDIVREM */	---	11320	/* G_UDIVREM */	---
11321	88,	---	11321	88,	---
11322	/* G_AND */	---	11322	/* G_AND */	---
11323	92,	---	11323	92,	---
11324	/* G_OR */	---	11324	/* G_OR */	---
11325	95,	---	11325	95,	---
11326	/* G_XOR */	---	11326	/* G_XOR */	---
11327	98,	---	11327	98,	---
11328	/* G_IMPLICIT_DEF */	---	11328	/* G_IMPLICIT_DEF */	---
11329	101,	---	11329	101,	---
11330	/* G_PHI */	---	11330	/* G_PHI */	---
11331	102,	---	11331	102,	---
11332	/* G_FRAME_INDEX */	---	11332	/* G_FRAME_INDEX */	---
11333	103,	---	11333	103,	---
11334	/* G_GLOBAL_VALUE */	---	11334	/* G_GLOBAL_VALUE */	---
11335	105,	---	11335	105,	---
11336	/* G_CONSTANT_POOL */	---	11336	/* G_CONSTANT_POOL */	---
11337	107,	---	11337	107,	---
11338	/* G_EXTRACT */	---	11338	/* G_EXTRACT */	---
11339	109,	---	11339	109,	---
11340	/* G_UNMERGE_VALUES */	---	11340	/* G_UNMERGE_VALUES */	---
11341	112,	---	11341	112,	---
11342	/* G_INSERT */	---	11342	/* G_INSERT */	---
11343	114,	---	11343	114,	---
11344	/* G_MERGE_VALUES */	---	11344	/* G_MERGE_VALUES */	---
11345	118,	---	11345	118,	---
11346	/* G_BUILD_VECTOR */	---	11346	/* G_BUILD_VECTOR */	---
11347	120,	---	11347	120,	---
11348	/* G_BUILD_VECTOR_TRUNC */	---	11348	/* G_BUILD_VECTOR_TRUNC */	---
11349	122,	---	11349	122,	---
11350	/* G_CONCAT_VECTORS */	---	11350	/* G_CONCAT_VECTORS */	---
11351	124,	---	11351	124,	---
11352	/* G_PTRTOINT */	---	11352	/* G_PTRTOINT */	---
11353	126,	---	11353	126,	---
11354	/* G_INTTOPTR */	---	11354	/* G_INTTOPTR */	---
11355	128,	---	11355	128,	---
11356	/* G_BITCAST */	---	11356	/* G_BITCAST */	---
11357	130,	---	11357	130,	---
11358	/* G_FREEZE */	---	11358	/* G_FREEZE */	---
11359	132,	---	11359	132,	---
11360	/* G_CONSTANT_FOLD_BARRIER */	---	11360	/* G_CONSTANT_FOLD_BARRIER */	---
11361	134,	---	11361	134,	---
11362	/* G_INTRINSIC_FPTRUNC_ROUND */	---	11362	/* G_INTRINSIC_FPTRUNC_ROUND */	---
11363	136,	---	11363	136,	---
11364	/* G_INTRINSIC_TRUNC */	---	11364	/* G_INTRINSIC_TRUNC */	---
11365	139,	---	11365	139,	---
11366	/* G_INTRINSIC_ROUND */	---	11366	/* G_INTRINSIC_ROUND */	---
11367	141,	---	11367	141,	---
11368	/* G_INTRINSIC_LRINT */	---	11368	/* G_INTRINSIC_LRINT */	---
11369	143,	---	11369	143,	---
11370	/* G_INTRINSIC_ROUNDEVEN */	---	11370	/* G_INTRINSIC_ROUNDEVEN */	---
11371	145,	---	11371	145,	---
11372	/* G_READCYCLECOUNTER */	---	11372	/* G_READCYCLECOUNTER */	---
11373	147,	---	11373	147,	---
11374	/* G_LOAD */	---	11374	/* G_LOAD */	---
11375	148,	---	11375	148,	---
11376	/* G_SEXTLOAD */	---	11376	/* G_SEXTLOAD */	---
11377	150,	---	11377	150,	---
11378	/* G_ZEXTLOAD */	---	11378	/* G_ZEXTLOAD */	---
11379	152,	---	11379	152,	---
11380	/* G_INDEXED_LOAD */	---	11380	/* G_INDEXED_LOAD */	---
11381	154,	---	11381	154,	---
11382	/* G_INDEXED_SEXTLOAD */	---	11382	/* G_INDEXED_SEXTLOAD */	---
11383	159,	---	11383	159,	---
11384	/* G_INDEXED_ZEXTLOAD */	---	11384	/* G_INDEXED_ZEXTLOAD */	---
11385	164,	---	11385	164,	---
11386	/* G_STORE */	---	11386	/* G_STORE */	---
11387	169,	---	11387	169,	---
11388	/* G_INDEXED_STORE */	---	11388	/* G_INDEXED_STORE */	---
11389	171,	---	11389	171,	---
11390	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	---	11390	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	---
11391	176,	---	11391	176,	---
11392	/* G_ATOMIC_CMPXCHG */	---	11392	/* G_ATOMIC_CMPXCHG */	---
11393	181,	---	11393	181,	---
11394	/* G_ATOMICRMW_XCHG */	---	11394	/* G_ATOMICRMW_XCHG */	---
11395	185,	---	11395	185,	---
11396	/* G_ATOMICRMW_ADD */	---	11396	/* G_ATOMICRMW_ADD */	---
11397	188,	---	11397	188,	---
11398	/* G_ATOMICRMW_SUB */	---	11398	/* G_ATOMICRMW_SUB */	---
11399	191,	---	11399	191,	---
11400	/* G_ATOMICRMW_AND */	---	11400	/* G_ATOMICRMW_AND */	---
11401	194,	---	11401	194,	---
11402	/* G_ATOMICRMW_NAND */	---	11402	/* G_ATOMICRMW_NAND */	---
11403	197,	---	11403	197,	---
11404	/* G_ATOMICRMW_OR */	---	11404	/* G_ATOMICRMW_OR */	---
11405	200,	---	11405	200,	---
11406	/* G_ATOMICRMW_XOR */	---	11406	/* G_ATOMICRMW_XOR */	---
11407	203,	---	11407	203,	---
11408	/* G_ATOMICRMW_MAX */	---	11408	/* G_ATOMICRMW_MAX */	---
11409	206,	---	11409	206,	---
11410	/* G_ATOMICRMW_MIN */	---	11410	/* G_ATOMICRMW_MIN */	---
11411	209,	---	11411	209,	---
11412	/* G_ATOMICRMW_UMAX */	---	11412	/* G_ATOMICRMW_UMAX */	---
11413	212,	---	11413	212,	---
11414	/* G_ATOMICRMW_UMIN */	---	11414	/* G_ATOMICRMW_UMIN */	---
11415	215,	---	11415	215,	---
11416	/* G_ATOMICRMW_FADD */	---	11416	/* G_ATOMICRMW_FADD */	---
11417	218,	---	11417	218,	---
11418	/* G_ATOMICRMW_FSUB */	---	11418	/* G_ATOMICRMW_FSUB */	---
11419	221,	---	11419	221,	---
11420	/* G_ATOMICRMW_FMAX */	---	11420	/* G_ATOMICRMW_FMAX */	---
11421	224,	---	11421	224,	---
11422	/* G_ATOMICRMW_FMIN */	---	11422	/* G_ATOMICRMW_FMIN */	---
11423	227,	---	11423	227,	---
11424	/* G_ATOMICRMW_UINC_WRAP */	---	11424	/* G_ATOMICRMW_UINC_WRAP */	---
11425	230,	---	11425	230,	---
11426	/* G_ATOMICRMW_UDEC_WRAP */	---	11426	/* G_ATOMICRMW_UDEC_WRAP */	---
11427	233,	---	11427	233,	---
11428	/* G_FENCE */	---	11428	/* G_FENCE */	---
11429	236,	---	11429	236,	---
11430	/* G_BRCOND */	---	11430	/* G_BRCOND */	---
11431	238,	---	11431	238,	---
11432	/* G_BRINDIRECT */	---	11432	/* G_BRINDIRECT */	---
11433	240,	---	11433	240,	---
11434	/* G_INVOKE_REGION_START */	---	11434	/* G_INVOKE_REGION_START */	---
11435	241,	---	11435	241,	---
11436	/* G_INTRINSIC */	---	11436	/* G_INTRINSIC */	---
11437	241,	---	11437	241,	---
11438	/* G_INTRINSIC_W_SIDE_EFFECTS */	---	11438	/* G_INTRINSIC_W_SIDE_EFFECTS */	---
11439	242,	---	11439	242,	---
11440	/* G_ANYEXT */	---	11440	/* G_ANYEXT */	---
11441	243,	---	11441	243,	---
11442	/* G_TRUNC */	---	11442	/* G_TRUNC */	---
11443	245,	---	11443	245,	---
11444	/* G_CONSTANT */	---	11444	/* G_CONSTANT */	---
11445	247,	---	11445	247,	---
11446	/* G_FCONSTANT */	---	11446	/* G_FCONSTANT */	---
11447	249,	---	11447	249,	---
11448	/* G_VASTART */	---	11448	/* G_VASTART */	---
11449	251,	---	11449	251,	---
11450	/* G_VAARG */	---	11450	/* G_VAARG */	---
11451	252,	---	11451	252,	---
11452	/* G_SEXT */	---	11452	/* G_SEXT */	---
11453	255,	---	11453	255,	---
11454	/* G_SEXT_INREG */	---	11454	/* G_SEXT_INREG */	---
11455	257,	---	11455	257,	---
11456	/* G_ZEXT */	---	11456	/* G_ZEXT */	---
11457	260,	---	11457	260,	---
11458	/* G_SHL */	---	11458	/* G_SHL */	---
11459	262,	---	11459	262,	---
11460	/* G_LSHR */	---	11460	/* G_LSHR */	---
11461	265,	---	11461	265,	---
11462	/* G_ASHR */	---	11462	/* G_ASHR */	---
11463	268,	---	11463	268,	---
11464	/* G_FSHL */	---	11464	/* G_FSHL */	---
11465	271,	---	11465	271,	---
11466	/* G_FSHR */	---	11466	/* G_FSHR */	---
11467	275,	---	11467	275,	---
11468	/* G_ROTR */	---	11468	/* G_ROTR */	---
11469	279,	---	11469	279,	---
11470	/* G_ROTL */	---	11470	/* G_ROTL */	---
11471	282,	---	11471	282,	---
11472	/* G_ICMP */	---	11472	/* G_ICMP */	---
11473	285,	---	11473	285,	---
11474	/* G_FCMP */	---	11474	/* G_FCMP */	---
11475	289,	---	11475	289,	---
11476	/* G_SELECT */	---	11476	/* G_SELECT */	---
11477	293,	---	11477	293,	---
11478	/* G_UADDO */	---	11478	/* G_UADDO */	---
11479	297,	---	11479	297,	---
11480	/* G_UADDE */	---	11480	/* G_UADDE */	---
11481	301,	---	11481	301,	---
11482	/* G_USUBO */	---	11482	/* G_USUBO */	---
11483	306,	---	11483	306,	---
11484	/* G_USUBE */	---	11484	/* G_USUBE */	---
11485	310,	---	11485	310,	---
11486	/* G_SADDO */	---	11486	/* G_SADDO */	---
11487	315,	---	11487	315,	---
11488	/* G_SADDE */	---	11488	/* G_SADDE */	---
11489	319,	---	11489	319,	---
11490	/* G_SSUBO */	---	11490	/* G_SSUBO */	---
11491	324,	---	11491	324,	---
11492	/* G_SSUBE */	---	11492	/* G_SSUBE */	---
11493	328,	---	11493	328,	---
11494	/* G_UMULO */	---	11494	/* G_UMULO */	---
11495	333,	---	11495	333,	---
11496	/* G_SMULO */	---	11496	/* G_SMULO */	---
11497	337,	---	11497	337,	---
11498	/* G_UMULH */	---	11498	/* G_UMULH */	---
11499	341,	---	11499	341,	---
11500	/* G_SMULH */	---	11500	/* G_SMULH */	---
11501	344,	---	11501	344,	---
11502	/* G_UADDSAT */	---	11502	/* G_UADDSAT */	---
11503	347,	---	11503	347,	---
11504	/* G_SADDSAT */	---	11504	/* G_SADDSAT */	---
11505	350,	---	11505	350,	---
11506	/* G_USUBSAT */	---	11506	/* G_USUBSAT */	---
11507	353,	---	11507	353,	---
11508	/* G_SSUBSAT */	---	11508	/* G_SSUBSAT */	---
11509	356,	---	11509	356,	---
11510	/* G_USHLSAT */	---	11510	/* G_USHLSAT */	---
11511	359,	---	11511	359,	---
11512	/* G_SSHLSAT */	---	11512	/* G_SSHLSAT */	---
11513	362,	---	11513	362,	---
11514	/* G_SMULFIX */	---	11514	/* G_SMULFIX */	---
11515	365,	---	11515	365,	---
11516	/* G_UMULFIX */	---	11516	/* G_UMULFIX */	---
11517	369,	---	11517	369,	---
11518	/* G_SMULFIXSAT */	---	11518	/* G_SMULFIXSAT */	---
11519	373,	---	11519	373,	---
11520	/* G_UMULFIXSAT */	---	11520	/* G_UMULFIXSAT */	---
11521	377,	---	11521	377,	---
11522	/* G_SDIVFIX */	---	11522	/* G_SDIVFIX */	---
11523	381,	---	11523	381,	---
11524	/* G_UDIVFIX */	---	11524	/* G_UDIVFIX */	---
11525	385,	---	11525	385,	---
11526	/* G_SDIVFIXSAT */	---	11526	/* G_SDIVFIXSAT */	---
11527	389,	---	11527	389,	---
11528	/* G_UDIVFIXSAT */	---	11528	/* G_UDIVFIXSAT */	---
11529	393,	---	11529	393,	---
11530	/* G_FADD */	---	11530	/* G_FADD */	---
11531	397,	---	11531	397,	---
11532	/* G_FSUB */	---	11532	/* G_FSUB */	---
11533	400,	---	11533	400,	---
11534	/* G_FMUL */	---	11534	/* G_FMUL */	---
11535	403,	---	11535	403,	---
11536	/* G_FMA */	---	11536	/* G_FMA */	---
11537	406,	---	11537	406,	---
11538	/* G_FMAD */	---	11538	/* G_FMAD */	---
11539	410,	---	11539	410,	---
11540	/* G_FDIV */	---	11540	/* G_FDIV */	---
11541	414,	---	11541	414,	---
11542	/* G_FREM */	---	11542	/* G_FREM */	---
11543	417,	---	11543	417,	---
11544	/* G_FPOW */	---	11544	/* G_FPOW */	---
11545	420,	---	11545	420,	---
11546	/* G_FPOWI */	---	11546	/* G_FPOWI */	---
11547	423,	---	11547	423,	---
11548	/* G_FEXP */	---	11548	/* G_FEXP */	---
11549	426,	---	11549	426,	---
11550	/* G_FEXP2 */	---	11550	/* G_FEXP2 */	---
11551	428,	---	11551	428,	---
11552	/* G_FLOG */	---	11552	/* G_FLOG */	---
11553	430,	---	11553	430,	---
11554	/* G_FLOG2 */	---	11554	/* G_FLOG2 */	---
11555	432,	---	11555	432,	---
11556	/* G_FLOG10 */	---	11556	/* G_FLOG10 */	---
11557	434,	---	11557	434,	---
11558	/* G_FLDEXP */	---	11558	/* G_FLDEXP */	---
11559	436,	---	11559	436,	---
11560	/* G_FFREXP */	---	11560	/* G_FFREXP */	---
11561	439,	---	11561	439,	---
11562	/* G_FNEG */	---	11562	/* G_FNEG */	---
11563	442,	---	11563	442,	---
11564	/* G_FPEXT */	---	11564	/* G_FPEXT */	---
11565	444,	---	11565	444,	---
11566	/* G_FPTRUNC */	---	11566	/* G_FPTRUNC */	---
11567	446,	---	11567	446,	---
11568	/* G_FPTOSI */	---	11568	/* G_FPTOSI */	---
11569	448,	---	11569	448,	---
11570	/* G_FPTOUI */	---	11570	/* G_FPTOUI */	---
11571	450,	---	11571	450,	---
11572	/* G_SITOFP */	---	11572	/* G_SITOFP */	---
11573	452,	---	11573	452,	---
11574	/* G_UITOFP */	---	11574	/* G_UITOFP */	---
11575	454,	---	11575	454,	---
11576	/* G_FABS */	---	11576	/* G_FABS */	---
11577	456,	---	11577	456,	---
11578	/* G_FCOPYSIGN */	---	11578	/* G_FCOPYSIGN */	---
11579	458,	---	11579	458,	---
11580	/* G_IS_FPCLASS */	---	11580	/* G_IS_FPCLASS */	---
11581	461,	---	11581	461,	---
11582	/* G_FCANONICALIZE */	---	11582	/* G_FCANONICALIZE */	---
11583	464,	---	11583	464,	---
11584	/* G_FMINNUM */	---	11584	/* G_FMINNUM */	---
11585	466,	---	11585	466,	---
11586	/* G_FMAXNUM */	---	11586	/* G_FMAXNUM */	---
11587	469,	---	11587	469,	---
11588	/* G_FMINNUM_IEEE */	---	11588	/* G_FMINNUM_IEEE */	---
11589	472,	---	11589	472,	---
11590	/* G_FMAXNUM_IEEE */	---	11590	/* G_FMAXNUM_IEEE */	---
11591	475,	---	11591	475,	---
11592	/* G_FMINIMUM */	---	11592	/* G_FMINIMUM */	---
11593	478,	---	11593	478,	---
11594	/* G_FMAXIMUM */	---	11594	/* G_FMAXIMUM */	---
11595	481,	---	11595	481,	---
11596	/* G_PTR_ADD */	---	11596	/* G_PTR_ADD */	---
11597	484,	---	11597	484,	---
11598	/* G_PTRMASK */	---	11598	/* G_PTRMASK */	---
11599	487,	---	11599	487,	---
11600	/* G_SMIN */	---	11600	/* G_SMIN */	---
11601	490,	---	11601	490,	---
11602	/* G_SMAX */	---	11602	/* G_SMAX */	---
11603	493,	---	11603	493,	---
11604	/* G_UMIN */	---	11604	/* G_UMIN */	---
11605	496,	---	11605	496,	---
11606	/* G_UMAX */	---	11606	/* G_UMAX */	---
11607	499,	---	11607	499,	---
11608	/* G_ABS */	---	11608	/* G_ABS */	---
11609	502,	---	11609	502,	---
11610	/* G_LROUND */	---	11610	/* G_LROUND */	---
11611	504,	---	11611	504,	---
11612	/* G_LLROUND */	---	11612	/* G_LLROUND */	---
11613	506,	---	11613	506,	---
11614	/* G_BR */	---	11614	/* G_BR */	---
11615	508,	---	11615	508,	---
11616	/* G_BRJT */	---	11616	/* G_BRJT */	---
11617	509,	---	11617	509,	---
11618	/* G_INSERT_VECTOR_ELT */	---	11618	/* G_INSERT_VECTOR_ELT */	---
11619	512,	---	11619	512,	---
11620	/* G_EXTRACT_VECTOR_ELT */	---	11620	/* G_EXTRACT_VECTOR_ELT */	---
11621	516,	---	11621	516,	---
11622	/* G_SHUFFLE_VECTOR */	---	11622	/* G_SHUFFLE_VECTOR */	---
11623	519,	---	11623	519,	---
11624	/* G_CTTZ */	---	11624	/* G_CTTZ */	---
11625	523,	---	11625	523,	---
11626	/* G_CTTZ_ZERO_UNDEF */	---	11626	/* G_CTTZ_ZERO_UNDEF */	---
11627	525,	---	11627	525,	---
11628	/* G_CTLZ */	---	11628	/* G_CTLZ */	---
11629	527,	---	11629	527,	---
11630	/* G_CTLZ_ZERO_UNDEF */	---	11630	/* G_CTLZ_ZERO_UNDEF */	---
11631	529,	---	11631	529,	---
11632	/* G_CTPOP */	---	11632	/* G_CTPOP */	---
11633	531,	---	11633	531,	---
11634	/* G_BSWAP */	---	11634	/* G_BSWAP */	---
11635	533,	---	11635	533,	---
11636	/* G_BITREVERSE */	---	11636	/* G_BITREVERSE */	---
11637	535,	---	11637	535,	---
11638	/* G_FCEIL */	---	11638	/* G_FCEIL */	---
11639	537,	---	11639	537,	---
11640	/* G_FCOS */	---	11640	/* G_FCOS */	---
11641	539,	---	11641	539,	---
11642	/* G_FSIN */	---	11642	/* G_FSIN */	---
11643	541,	---	11643	541,	---
11644	/* G_FSQRT */	---	11644	/* G_FSQRT */	---
11645	543,	---	11645	543,	---
11646	/* G_FFLOOR */	---	11646	/* G_FFLOOR */	---
11647	545,	---	11647	545,	---
11648	/* G_FRINT */	---	11648	/* G_FRINT */	---
11649	547,	---	11649	547,	---
11650	/* G_FNEARBYINT */	---	11650	/* G_FNEARBYINT */	---
11651	549,	---	11651	549,	---
11652	/* G_ADDRSPACE_CAST */	---	11652	/* G_ADDRSPACE_CAST */	---
11653	551,	---	11653	551,	---
11654	/* G_BLOCK_ADDR */	---	11654	/* G_BLOCK_ADDR */	---
11655	553,	---	11655	553,	---
11656	/* G_JUMP_TABLE */	---	11656	/* G_JUMP_TABLE */	---
11657	555,	---	11657	555,	---
11658	/* G_DYN_STACKALLOC */	---	11658	/* G_DYN_STACKALLOC */	---
11659	557,	---	11659	557,	---
11660	/* G_STRICT_FADD */	---	11660	/* G_STRICT_FADD */	---
11661	560,	---	11661	560,	---
11662	/* G_STRICT_FSUB */	---	11662	/* G_STRICT_FSUB */	---
11663	563,	---	11663	563,	---
11664	/* G_STRICT_FMUL */	---	11664	/* G_STRICT_FMUL */	---
11665	566,	---	11665	566,	---
11666	/* G_STRICT_FDIV */	---	11666	/* G_STRICT_FDIV */	---
11667	569,	---	11667	569,	---
11668	/* G_STRICT_FREM */	---	11668	/* G_STRICT_FREM */	---
11669	572,	---	11669	572,	---
11670	/* G_STRICT_FMA */	---	11670	/* G_STRICT_FMA */	---
11671	575,	---	11671	575,	---
11672	/* G_STRICT_FSQRT */	---	11672	/* G_STRICT_FSQRT */	---
11673	579,	---	11673	579,	---
11674	/* G_STRICT_FLDEXP */	---	11674	/* G_STRICT_FLDEXP */	---
11675	581,	---	11675	581,	---
11676	/* G_READ_REGISTER */	---	11676	/* G_READ_REGISTER */	---
11677	584,	---	11677	584,	---
11678	/* G_WRITE_REGISTER */	---	11678	/* G_WRITE_REGISTER */	---
11679	586,	---	11679	586,	---
11680	/* G_MEMCPY */	---	11680	/* G_MEMCPY */	---
11681	588,	---	11681	588,	---
11682	/* G_MEMCPY_INLINE */	---	11682	/* G_MEMCPY_INLINE */	---
11683	592,	---	11683	592,	---
11684	/* G_MEMMOVE */	---	11684	/* G_MEMMOVE */	---
11685	595,	---	11685	595,	---
11686	/* G_MEMSET */	---	11686	/* G_MEMSET */	---
11687	599,	---	11687	599,	---
11688	/* G_BZERO */	---	11688	/* G_BZERO */	---
11689	603,	---	11689	603,	---
11690	/* G_VECREDUCE_SEQ_FADD */	---	11690	/* G_VECREDUCE_SEQ_FADD */	---
11691	606,	---	11691	606,	---
11692	/* G_VECREDUCE_SEQ_FMUL */	---	11692	/* G_VECREDUCE_SEQ_FMUL */	---
11693	609,	---	11693	609,	---
11694	/* G_VECREDUCE_FADD */	---	11694	/* G_VECREDUCE_FADD */	---
11695	612,	---	11695	612,	---
11696	/* G_VECREDUCE_FMUL */	---	11696	/* G_VECREDUCE_FMUL */	---
11697	614,	---	11697	614,	---
11698	/* G_VECREDUCE_FMAX */	---	11698	/* G_VECREDUCE_FMAX */	---
11699	616,	---	11699	616,	---
11700	/* G_VECREDUCE_FMIN */	---	11700	/* G_VECREDUCE_FMIN */	---
11701	618,	---	11701	618,	---
11702	/* G_VECREDUCE_ADD */	---	11702	/* G_VECREDUCE_ADD */	---
11703	620,	---	11703	620,	---
11704	/* G_VECREDUCE_MUL */	---	11704	/* G_VECREDUCE_MUL */	---
11705	622,	---	11705	622,	---
11706	/* G_VECREDUCE_AND */	---	11706	/* G_VECREDUCE_AND */	---
11707	624,	---	11707	624,	---
11708	/* G_VECREDUCE_OR */	---	11708	/* G_VECREDUCE_OR */	---
11709	626,	---	11709	626,	---
11710	/* G_VECREDUCE_XOR */	---	11710	/* G_VECREDUCE_XOR */	---
11711	628,	---	11711	628,	---
11712	/* G_VECREDUCE_SMAX */	---	11712	/* G_VECREDUCE_SMAX */	---
11713	630,	---	11713	630,	---
11714	/* G_VECREDUCE_SMIN */	---	11714	/* G_VECREDUCE_SMIN */	---
11715	632,	---	11715	632,	---
11716	/* G_VECREDUCE_UMAX */	---	11716	/* G_VECREDUCE_UMAX */	---
11717	634,	---	11717	634,	---
11718	/* G_VECREDUCE_UMIN */	---	11718	/* G_VECREDUCE_UMIN */	---
11719	636,	---	11719	636,	---
11720	/* G_SBFX */	---	11720	/* G_SBFX */	---
11721	638,	---	11721	638,	---
11722	/* G_UBFX */	---	11722	/* G_UBFX */	---
11723	642,	---	11723	642,	---
11724	/* ABSMacro */	---	11724	/* ABSMacro */	---
11725	646,	---	11725	646,	---
11726	/* ADJCALLSTACKDOWN */	---	11726	/* ADJCALLSTACKDOWN */	---
11727	648,	---	11727	648,	---
11728	/* ADJCALLSTACKUP */	---	11728	/* ADJCALLSTACKUP */	---
11729	650,	---	11729	650,	---
11730	/* AND_V_D_PSEUDO */	---	11730	/* AND_V_D_PSEUDO */	---
11731	652,	---	11731	652,	---
11732	/* AND_V_H_PSEUDO */	---	11732	/* AND_V_H_PSEUDO */	---
11733	655,	---	11733	655,	---
11734	/* AND_V_W_PSEUDO */	---	11734	/* AND_V_W_PSEUDO */	---
11735	658,	---	11735	658,	---
11736	/* ATOMIC_CMP_SWAP_I16 */	---	11736	/* ATOMIC_CMP_SWAP_I16 */	---
11737	661,	---	11737	661,	---
11738	/* ATOMIC_CMP_SWAP_I16_POSTRA */	---	11738	/* ATOMIC_CMP_SWAP_I16_POSTRA */	---
11739	665,	---	11739	665,	---
11740	/* ATOMIC_CMP_SWAP_I32 */	---	11740	/* ATOMIC_CMP_SWAP_I32 */	---
11741	672,	---	11741	672,	---
11742	/* ATOMIC_CMP_SWAP_I32_POSTRA */	---	11742	/* ATOMIC_CMP_SWAP_I32_POSTRA */	---
11743	676,	---	11743	676,	---
11744	/* ATOMIC_CMP_SWAP_I64 */	---	11744	/* ATOMIC_CMP_SWAP_I64 */	---
11745	680,	---	11745	680,	---
11746	/* ATOMIC_CMP_SWAP_I64_POSTRA */	---	11746	/* ATOMIC_CMP_SWAP_I64_POSTRA */	---
11747	684,	---	11747	684,	---
11748	/* ATOMIC_CMP_SWAP_I8 */	---	11748	/* ATOMIC_CMP_SWAP_I8 */	---
11749	688,	---	11749	688,	---
11750	/* ATOMIC_CMP_SWAP_I8_POSTRA */	---	11750	/* ATOMIC_CMP_SWAP_I8_POSTRA */	---
11751	692,	---	11751	692,	---
11752	/* ATOMIC_LOAD_ADD_I16 */	---	11752	/* ATOMIC_LOAD_ADD_I16 */	---
11753	699,	---	11753	699,	---
11754	/* ATOMIC_LOAD_ADD_I16_POSTRA */	---	11754	/* ATOMIC_LOAD_ADD_I16_POSTRA */	---
11755	702,	---	11755	702,	---
11756	/* ATOMIC_LOAD_ADD_I32 */	---	11756	/* ATOMIC_LOAD_ADD_I32 */	---
11757	708,	---	11757	708,	---
11758	/* ATOMIC_LOAD_ADD_I32_POSTRA */	---	11758	/* ATOMIC_LOAD_ADD_I32_POSTRA */	---
11759	711,	---	11759	711,	---
11760	/* ATOMIC_LOAD_ADD_I64 */	---	11760	/* ATOMIC_LOAD_ADD_I64 */	---
11761	714,	---	11761	714,	---
11762	/* ATOMIC_LOAD_ADD_I64_POSTRA */	---	11762	/* ATOMIC_LOAD_ADD_I64_POSTRA */	---
11763	717,	---	11763	717,	---
11764	/* ATOMIC_LOAD_ADD_I8 */	---	11764	/* ATOMIC_LOAD_ADD_I8 */	---
11765	720,	---	11765	720,	---
11766	/* ATOMIC_LOAD_ADD_I8_POSTRA */	---	11766	/* ATOMIC_LOAD_ADD_I8_POSTRA */	---
11767	723,	---	11767	723,	---
11768	/* ATOMIC_LOAD_AND_I16 */	---	11768	/* ATOMIC_LOAD_AND_I16 */	---
11769	729,	---	11769	729,	---
11770	/* ATOMIC_LOAD_AND_I16_POSTRA */	---	11770	/* ATOMIC_LOAD_AND_I16_POSTRA */	---
11771	732,	---	11771	732,	---
11772	/* ATOMIC_LOAD_AND_I32 */	---	11772	/* ATOMIC_LOAD_AND_I32 */	---
11773	738,	---	11773	738,	---
11774	/* ATOMIC_LOAD_AND_I32_POSTRA */	---	11774	/* ATOMIC_LOAD_AND_I32_POSTRA */	---
11775	741,	---	11775	741,	---
11776	/* ATOMIC_LOAD_AND_I64 */	---	11776	/* ATOMIC_LOAD_AND_I64 */	---
11777	744,	---	11777	744,	---
11778	/* ATOMIC_LOAD_AND_I64_POSTRA */	---	11778	/* ATOMIC_LOAD_AND_I64_POSTRA */	---
11779	747,	---	11779	747,	---
11780	/* ATOMIC_LOAD_AND_I8 */	---	11780	/* ATOMIC_LOAD_AND_I8 */	---
11781	750,	---	11781	750,	---
11782	/* ATOMIC_LOAD_AND_I8_POSTRA */	---	11782	/* ATOMIC_LOAD_AND_I8_POSTRA */	---
11783	753,	---	11783	753,	---
11784	/* ATOMIC_LOAD_MAX_I16 */	---	11784	/* ATOMIC_LOAD_MAX_I16 */	---
11785	759,	---	11785	759,	---
11786	/* ATOMIC_LOAD_MAX_I16_POSTRA */	---	11786	/* ATOMIC_LOAD_MAX_I16_POSTRA */	---
11787	762,	---	11787	762,	---
11788	/* ATOMIC_LOAD_MAX_I32 */	---	11788	/* ATOMIC_LOAD_MAX_I32 */	---
11789	768,	---	11789	768,	---
11790	/* ATOMIC_LOAD_MAX_I32_POSTRA */	---	11790	/* ATOMIC_LOAD_MAX_I32_POSTRA */	---
11791	771,	---	11791	771,	---
11792	/* ATOMIC_LOAD_MAX_I64 */	---	11792	/* ATOMIC_LOAD_MAX_I64 */	---
11793	774,	---	11793	774,	---
11794	/* ATOMIC_LOAD_MAX_I64_POSTRA */	---	11794	/* ATOMIC_LOAD_MAX_I64_POSTRA */	---
11795	777,	---	11795	777,	---
11796	/* ATOMIC_LOAD_MAX_I8 */	---	11796	/* ATOMIC_LOAD_MAX_I8 */	---
11797	780,	---	11797	780,	---
11798	/* ATOMIC_LOAD_MAX_I8_POSTRA */	---	11798	/* ATOMIC_LOAD_MAX_I8_POSTRA */	---
11799	783,	---	11799	783,	---
11800	/* ATOMIC_LOAD_MIN_I16 */	---	11800	/* ATOMIC_LOAD_MIN_I16 */	---
11801	789,	---	11801	789,	---
11802	/* ATOMIC_LOAD_MIN_I16_POSTRA */	---	11802	/* ATOMIC_LOAD_MIN_I16_POSTRA */	---
11803	792,	---	11803	792,	---
11804	/* ATOMIC_LOAD_MIN_I32 */	---	11804	/* ATOMIC_LOAD_MIN_I32 */	---
11805	798,	---	11805	798,	---
11806	/* ATOMIC_LOAD_MIN_I32_POSTRA */	---	11806	/* ATOMIC_LOAD_MIN_I32_POSTRA */	---
11807	801,	---	11807	801,	---
11808	/* ATOMIC_LOAD_MIN_I64 */	---	11808	/* ATOMIC_LOAD_MIN_I64 */	---
11809	804,	---	11809	804,	---
11810	/* ATOMIC_LOAD_MIN_I64_POSTRA */	---	11810	/* ATOMIC_LOAD_MIN_I64_POSTRA */	---
11811	807,	---	11811	807,	---
11812	/* ATOMIC_LOAD_MIN_I8 */	---	11812	/* ATOMIC_LOAD_MIN_I8 */	---
11813	810,	---	11813	810,	---
11814	/* ATOMIC_LOAD_MIN_I8_POSTRA */	---	11814	/* ATOMIC_LOAD_MIN_I8_POSTRA */	---
11815	813,	---	11815	813,	---
11816	/* ATOMIC_LOAD_NAND_I16 */	---	11816	/* ATOMIC_LOAD_NAND_I16 */	---
11817	819,	---	11817	819,	---
11818	/* ATOMIC_LOAD_NAND_I16_POSTRA */	---	11818	/* ATOMIC_LOAD_NAND_I16_POSTRA */	---
11819	822,	---	11819	822,	---
11820	/* ATOMIC_LOAD_NAND_I32 */	---	11820	/* ATOMIC_LOAD_NAND_I32 */	---
11821	828,	---	11821	828,	---
11822	/* ATOMIC_LOAD_NAND_I32_POSTRA */	---	11822	/* ATOMIC_LOAD_NAND_I32_POSTRA */	---
11823	831,	---	11823	831,	---
11824	/* ATOMIC_LOAD_NAND_I64 */	---	11824	/* ATOMIC_LOAD_NAND_I64 */	---
11825	834,	---	11825	834,	---
11826	/* ATOMIC_LOAD_NAND_I64_POSTRA */	---	11826	/* ATOMIC_LOAD_NAND_I64_POSTRA */	---
11827	837,	---	11827	837,	---
11828	/* ATOMIC_LOAD_NAND_I8 */	---	11828	/* ATOMIC_LOAD_NAND_I8 */	---
11829	840,	---	11829	840,	---
11830	/* ATOMIC_LOAD_NAND_I8_POSTRA */	---	11830	/* ATOMIC_LOAD_NAND_I8_POSTRA */	---
11831	843,	---	11831	843,	---
11832	/* ATOMIC_LOAD_OR_I16 */	---	11832	/* ATOMIC_LOAD_OR_I16 */	---
11833	849,	---	11833	849,	---
11834	/* ATOMIC_LOAD_OR_I16_POSTRA */	---	11834	/* ATOMIC_LOAD_OR_I16_POSTRA */	---
11835	852,	---	11835	852,	---
11836	/* ATOMIC_LOAD_OR_I32 */	---	11836	/* ATOMIC_LOAD_OR_I32 */	---
11837	858,	---	11837	858,	---
11838	/* ATOMIC_LOAD_OR_I32_POSTRA */	---	11838	/* ATOMIC_LOAD_OR_I32_POSTRA */	---
11839	861,	---	11839	861,	---
11840	/* ATOMIC_LOAD_OR_I64 */	---	11840	/* ATOMIC_LOAD_OR_I64 */	---
11841	864,	---	11841	864,	---
11842	/* ATOMIC_LOAD_OR_I64_POSTRA */	---	11842	/* ATOMIC_LOAD_OR_I64_POSTRA */	---
11843	867,	---	11843	867,	---
11844	/* ATOMIC_LOAD_OR_I8 */	---	11844	/* ATOMIC_LOAD_OR_I8 */	---
11845	870,	---	11845	870,	---
11846	/* ATOMIC_LOAD_OR_I8_POSTRA */	---	11846	/* ATOMIC_LOAD_OR_I8_POSTRA */	---
11847	873,	---	11847	873,	---
11848	/* ATOMIC_LOAD_SUB_I16 */	---	11848	/* ATOMIC_LOAD_SUB_I16 */	---
11849	879,	---	11849	879,	---
11850	/* ATOMIC_LOAD_SUB_I16_POSTRA */	---	11850	/* ATOMIC_LOAD_SUB_I16_POSTRA */	---
11851	882,	---	11851	882,	---
11852	/* ATOMIC_LOAD_SUB_I32 */	---	11852	/* ATOMIC_LOAD_SUB_I32 */	---
11853	888,	---	11853	888,	---
11854	/* ATOMIC_LOAD_SUB_I32_POSTRA */	---	11854	/* ATOMIC_LOAD_SUB_I32_POSTRA */	---
11855	891,	---	11855	891,	---
11856	/* ATOMIC_LOAD_SUB_I64 */	---	11856	/* ATOMIC_LOAD_SUB_I64 */	---
11857	894,	---	11857	894,	---
11858	/* ATOMIC_LOAD_SUB_I64_POSTRA */	---	11858	/* ATOMIC_LOAD_SUB_I64_POSTRA */	---
11859	897,	---	11859	897,	---
11860	/* ATOMIC_LOAD_SUB_I8 */	---	11860	/* ATOMIC_LOAD_SUB_I8 */	---
11861	900,	---	11861	900,	---
11862	/* ATOMIC_LOAD_SUB_I8_POSTRA */	---	11862	/* ATOMIC_LOAD_SUB_I8_POSTRA */	---
11863	903,	---	11863	903,	---
11864	/* ATOMIC_LOAD_UMAX_I16 */	---	11864	/* ATOMIC_LOAD_UMAX_I16 */	---
11865	909,	---	11865	909,	---
11866	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	---	11866	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	---
11867	912,	---	11867	912,	---
11868	/* ATOMIC_LOAD_UMAX_I32 */	---	11868	/* ATOMIC_LOAD_UMAX_I32 */	---
11869	918,	---	11869	918,	---
11870	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	---	11870	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	---
11871	921,	---	11871	921,	---
11872	/* ATOMIC_LOAD_UMAX_I64 */	---	11872	/* ATOMIC_LOAD_UMAX_I64 */	---
11873	924,	---	11873	924,	---
11874	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	---	11874	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	---
11875	927,	---	11875	927,	---
11876	/* ATOMIC_LOAD_UMAX_I8 */	---	11876	/* ATOMIC_LOAD_UMAX_I8 */	---
11877	930,	---	11877	930,	---
11878	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	---	11878	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	---
11879	933,	---	11879	933,	---
11880	/* ATOMIC_LOAD_UMIN_I16 */	---	11880	/* ATOMIC_LOAD_UMIN_I16 */	---
11881	939,	---	11881	939,	---
11882	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	---	11882	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	---
11883	942,	---	11883	942,	---
11884	/* ATOMIC_LOAD_UMIN_I32 */	---	11884	/* ATOMIC_LOAD_UMIN_I32 */	---
11885	948,	---	11885	948,	---
11886	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	---	11886	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	---
11887	951,	---	11887	951,	---
11888	/* ATOMIC_LOAD_UMIN_I64 */	---	11888	/* ATOMIC_LOAD_UMIN_I64 */	---
11889	954,	---	11889	954,	---
11890	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	---	11890	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	---
11891	957,	---	11891	957,	---
11892	/* ATOMIC_LOAD_UMIN_I8 */	---	11892	/* ATOMIC_LOAD_UMIN_I8 */	---
11893	960,	---	11893	960,	---
11894	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	---	11894	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	---
11895	963,	---	11895	963,	---
11896	/* ATOMIC_LOAD_XOR_I16 */	---	11896	/* ATOMIC_LOAD_XOR_I16 */	---
11897	969,	---	11897	969,	---
11898	/* ATOMIC_LOAD_XOR_I16_POSTRA */	---	11898	/* ATOMIC_LOAD_XOR_I16_POSTRA */	---
11899	972,	---	11899	972,	---
11900	/* ATOMIC_LOAD_XOR_I32 */	---	11900	/* ATOMIC_LOAD_XOR_I32 */	---
11901	978,	---	11901	978,	---
11902	/* ATOMIC_LOAD_XOR_I32_POSTRA */	---	11902	/* ATOMIC_LOAD_XOR_I32_POSTRA */	---
11903	981,	---	11903	981,	---
11904	/* ATOMIC_LOAD_XOR_I64 */	---	11904	/* ATOMIC_LOAD_XOR_I64 */	---
11905	984,	---	11905	984,	---
11906	/* ATOMIC_LOAD_XOR_I64_POSTRA */	---	11906	/* ATOMIC_LOAD_XOR_I64_POSTRA */	---
11907	987,	---	11907	987,	---
11908	/* ATOMIC_LOAD_XOR_I8 */	---	11908	/* ATOMIC_LOAD_XOR_I8 */	---
11909	990,	---	11909	990,	---
11910	/* ATOMIC_LOAD_XOR_I8_POSTRA */	---	11910	/* ATOMIC_LOAD_XOR_I8_POSTRA */	---
11911	993,	---	11911	993,	---
11912	/* ATOMIC_SWAP_I16 */	---	11912	/* ATOMIC_SWAP_I16 */	---
11913	999,	---	11913	999,	---
11914	/* ATOMIC_SWAP_I16_POSTRA */	---	11914	/* ATOMIC_SWAP_I16_POSTRA */	---
11915	1002,	---	11915	1002,	---
11916	/* ATOMIC_SWAP_I32 */	---	11916	/* ATOMIC_SWAP_I32 */	---
11917	1008,	---	11917	1008,	---
11918	/* ATOMIC_SWAP_I32_POSTRA */	---	11918	/* ATOMIC_SWAP_I32_POSTRA */	---
11919	1011,	---	11919	1011,	---
11920	/* ATOMIC_SWAP_I64 */	---	11920	/* ATOMIC_SWAP_I64 */	---
11921	1014,	---	11921	1014,	---
11922	/* ATOMIC_SWAP_I64_POSTRA */	---	11922	/* ATOMIC_SWAP_I64_POSTRA */	---
11923	1017,	---	11923	1017,	---
11924	/* ATOMIC_SWAP_I8 */	---	11924	/* ATOMIC_SWAP_I8 */	---
11925	1020,	---	11925	1020,	---
11926	/* ATOMIC_SWAP_I8_POSTRA */	---	11926	/* ATOMIC_SWAP_I8_POSTRA */	---
11927	1023,	---	11927	1023,	---
11928	/* B */	---	11928	/* B */	---
11929	1029,	---	11929	1029,	---
11930	/* BAL_BR */	---	11930	/* BAL_BR */	---
11931	1030,	---	11931	1030,	---
11932	/* BAL_BR_MM */	---	11932	/* BAL_BR_MM */	---
11933	1031,	---	11933	1031,	---
11934	/* BEQLImmMacro */	---	11934	/* BEQLImmMacro */	---
11935	1032,	---	11935	1032,	---
11936	/* BGE */	---	11936	/* BGE */	---
11937	1035,	---	11937	1035,	---
11938	/* BGEImmMacro */	---	11938	/* BGEImmMacro */	---
11939	1038,	---	11939	1038,	---
11940	/* BGEL */	---	11940	/* BGEL */	---
11941	1041,	---	11941	1041,	---
11942	/* BGELImmMacro */	---	11942	/* BGELImmMacro */	---
11943	1044,	---	11943	1044,	---
11944	/* BGEU */	---	11944	/* BGEU */	---
11945	1047,	---	11945	1047,	---
11946	/* BGEUImmMacro */	---	11946	/* BGEUImmMacro */	---
11947	1050,	---	11947	1050,	---
11948	/* BGEUL */	---	11948	/* BGEUL */	---
11949	1053,	---	11949	1053,	---
11950	/* BGEULImmMacro */	---	11950	/* BGEULImmMacro */	---
11951	1056,	---	11951	1056,	---
11952	/* BGT */	---	11952	/* BGT */	---
11953	1059,	---	11953	1059,	---
11954	/* BGTImmMacro */	---	11954	/* BGTImmMacro */	---
11955	1062,	---	11955	1062,	---
11956	/* BGTL */	---	11956	/* BGTL */	---
11957	1065,	---	11957	1065,	---
11958	/* BGTLImmMacro */	---	11958	/* BGTLImmMacro */	---
11959	1068,	---	11959	1068,	---
11960	/* BGTU */	---	11960	/* BGTU */	---
11961	1071,	---	11961	1071,	---
11962	/* BGTUImmMacro */	---	11962	/* BGTUImmMacro */	---
11963	1074,	---	11963	1074,	---
11964	/* BGTUL */	---	11964	/* BGTUL */	---
11965	1077,	---	11965	1077,	---
11966	/* BGTULImmMacro */	---	11966	/* BGTULImmMacro */	---
11967	1080,	---	11967	1080,	---
11968	/* BLE */	---	11968	/* BLE */	---
11969	1083,	---	11969	1083,	---
11970	/* BLEImmMacro */	---	11970	/* BLEImmMacro */	---
11971	1086,	---	11971	1086,	---
11972	/* BLEL */	---	11972	/* BLEL */	---
11973	1089,	---	11973	1089,	---
11974	/* BLELImmMacro */	---	11974	/* BLELImmMacro */	---
11975	1092,	---	11975	1092,	---
11976	/* BLEU */	---	11976	/* BLEU */	---
11977	1095,	---	11977	1095,	---
11978	/* BLEUImmMacro */	---	11978	/* BLEUImmMacro */	---
11979	1098,	---	11979	1098,	---
11980	/* BLEUL */	---	11980	/* BLEUL */	---
11981	1101,	---	11981	1101,	---
11982	/* BLEULImmMacro */	---	11982	/* BLEULImmMacro */	---
11983	1104,	---	11983	1104,	---
11984	/* BLT */	---	11984	/* BLT */	---
11985	1107,	---	11985	1107,	---
11986	/* BLTImmMacro */	---	11986	/* BLTImmMacro */	---
11987	1110,	---	11987	1110,	---
11988	/* BLTL */	---	11988	/* BLTL */	---
11989	1113,	---	11989	1113,	---
11990	/* BLTLImmMacro */	---	11990	/* BLTLImmMacro */	---
11991	1116,	---	11991	1116,	---
11992	/* BLTU */	---	11992	/* BLTU */	---
11993	1119,	---	11993	1119,	---
11994	/* BLTUImmMacro */	---	11994	/* BLTUImmMacro */	---
11995	1122,	---	11995	1122,	---
11996	/* BLTUL */	---	11996	/* BLTUL */	---
11997	1125,	---	11997	1125,	---
11998	/* BLTULImmMacro */	---	11998	/* BLTULImmMacro */	---
11999	1128,	---	11999	1128,	---
12000	/* BNELImmMacro */	---	12000	/* BNELImmMacro */	---
12001	1131,	---	12001	1131,	---
12002	/* BPOSGE32_PSEUDO */	---	12002	/* BPOSGE32_PSEUDO */	---
12003	1134,	---	12003	1134,	---
12004	/* BSEL_D_PSEUDO */	---	12004	/* BSEL_D_PSEUDO */	---
12005	1135,	---	12005	1135,	---
12006	/* BSEL_FD_PSEUDO */	---	12006	/* BSEL_FD_PSEUDO */	---
12007	1139,	---	12007	1139,	---
12008	/* BSEL_FW_PSEUDO */	---	12008	/* BSEL_FW_PSEUDO */	---
12009	1143,	---	12009	1143,	---
12010	/* BSEL_H_PSEUDO */	---	12010	/* BSEL_H_PSEUDO */	---
12011	1147,	---	12011	1147,	---
12012	/* BSEL_W_PSEUDO */	---	12012	/* BSEL_W_PSEUDO */	---
12013	1151,	---	12013	1151,	---
12014	/* B_MM */	---	12014	/* B_MM */	---
12015	1155,	---	12015	1155,	---
12016	/* B_MMR6_Pseudo */	---	12016	/* B_MMR6_Pseudo */	---
12017	1156,	---	12017	1156,	---
12018	/* B_MM_Pseudo */	---	12018	/* B_MM_Pseudo */	---
12019	1157,	---	12019	1157,	---
12020	/* BeqImm */	---	12020	/* BeqImm */	---
12021	1158,	---	12021	1158,	---
12022	/* BneImm */	---	12022	/* BneImm */	---
12023	1161,	---	12023	1161,	---
12024	/* BteqzT8CmpX16 */	---	12024	/* BteqzT8CmpX16 */	---
12025	1164,	---	12025	1164,	---
12026	/* BteqzT8CmpiX16 */	---	12026	/* BteqzT8CmpiX16 */	---
12027	1167,	---	12027	1167,	---
12028	/* BteqzT8SltX16 */	---	12028	/* BteqzT8SltX16 */	---
12029	1170,	---	12029	1170,	---
12030	/* BteqzT8SltiX16 */	---	12030	/* BteqzT8SltiX16 */	---
12031	1173,	---	12031	1173,	---
12032	/* BteqzT8SltiuX16 */	---	12032	/* BteqzT8SltiuX16 */	---
12033	1176,	---	12033	1176,	---
12034	/* BteqzT8SltuX16 */	---	12034	/* BteqzT8SltuX16 */	---
12035	1179,	---	12035	1179,	---
12036	/* BtnezT8CmpX16 */	---	12036	/* BtnezT8CmpX16 */	---
12037	1182,	---	12037	1182,	---
12038	/* BtnezT8CmpiX16 */	---	12038	/* BtnezT8CmpiX16 */	---
12039	1185,	---	12039	1185,	---
12040	/* BtnezT8SltX16 */	---	12040	/* BtnezT8SltX16 */	---
12041	1188,	---	12041	1188,	---
12042	/* BtnezT8SltiX16 */	---	12042	/* BtnezT8SltiX16 */	---
12043	1191,	---	12043	1191,	---
12044	/* BtnezT8SltiuX16 */	---	12044	/* BtnezT8SltiuX16 */	---
12045	1194,	---	12045	1194,	---
12046	/* BtnezT8SltuX16 */	---	12046	/* BtnezT8SltuX16 */	---
12047	1197,	---	12047	1197,	---
12048	/* BuildPairF64 */	---	12048	/* BuildPairF64 */	---
12049	1200,	---	12049	1200,	---
12050	/* BuildPairF64_64 */	---	12050	/* BuildPairF64_64 */	---
12051	1203,	---	12051	1203,	---
12052	/* CFTC1 */	---	12052	/* CFTC1 */	---
12053	1206,	---	12053	1206,	---
12054	/* CONSTPOOL_ENTRY */	---	12054	/* CONSTPOOL_ENTRY */	---
12055	1208,	---	12055	1208,	---
12056	/* COPY_FD_PSEUDO */	---	12056	/* COPY_FD_PSEUDO */	---
12057	1211,	---	12057	1211,	---
12058	/* COPY_FW_PSEUDO */	---	12058	/* COPY_FW_PSEUDO */	---
12059	1214,	---	12059	1214,	---
12060	/* CTTC1 */	---	12060	/* CTTC1 */	---
12061	1217,	---	12061	1217,	---
12062	/* Constant32 */	---	12062	/* Constant32 */	---
12063	1219,	---	12063	1219,	---
12064	/* DMULImmMacro */	---	12064	/* DMULImmMacro */	---
12065	1220,	---	12065	1220,	---
12066	/* DMULMacro */	---	12066	/* DMULMacro */	---
12067	1223,	---	12067	1223,	---
12068	/* DMULOMacro */	---	12068	/* DMULOMacro */	---
12069	1226,	---	12069	1226,	---
12070	/* DMULOUMacro */	---	12070	/* DMULOUMacro */	---
12071	1229,	---	12071	1229,	---
12072	/* DROL */	---	12072	/* DROL */	---
12073	1232,	---	12073	1232,	---
12074	/* DROLImm */	---	12074	/* DROLImm */	---
12075	1235,	---	12075	1235,	---
12076	/* DROR */	---	12076	/* DROR */	---
12077	1238,	---	12077	1238,	---
12078	/* DRORImm */	---	12078	/* DRORImm */	---
12079	1241,	---	12079	1241,	---
12080	/* DSDivIMacro */	---	12080	/* DSDivIMacro */	---
12081	1244,	---	12081	1244,	---
12082	/* DSDivMacro */	---	12082	/* DSDivMacro */	---
12083	1247,	---	12083	1247,	---
12084	/* DSRemIMacro */	---	12084	/* DSRemIMacro */	---
12085	1250,	---	12085	1250,	---
12086	/* DSRemMacro */	---	12086	/* DSRemMacro */	---
12087	1253,	---	12087	1253,	---
12088	/* DUDivIMacro */	---	12088	/* DUDivIMacro */	---
12089	1256,	---	12089	1256,	---
12090	/* DUDivMacro */	---	12090	/* DUDivMacro */	---
12091	1259,	---	12091	1259,	---
12092	/* DURemIMacro */	---	12092	/* DURemIMacro */	---
12093	1262,	---	12093	1262,	---
12094	/* DURemMacro */	---	12094	/* DURemMacro */	---
12095	1265,	---	12095	1265,	---
12096	/* ERet */	---	12096	/* ERet */	---
12097	1268,	---	12097	1268,	---
12098	/* ExtractElementF64 */	---	12098	/* ExtractElementF64 */	---
12099	1268,	---	12099	1268,	---
12100	/* ExtractElementF64_64 */	---	12100	/* ExtractElementF64_64 */	---
12101	1271,	---	12101	1271,	---
12102	/* FABS_D */	---	12102	/* FABS_D */	---
12103	1274,	---	12103	1274,	---
12104	/* FABS_W */	---	12104	/* FABS_W */	---
12105	1276,	---	12105	1276,	---
12106	/* FEXP2_D_1_PSEUDO */	---	12106	/* FEXP2_D_1_PSEUDO */	---
12107	1278,	---	12107	1278,	---
12108	/* FEXP2_W_1_PSEUDO */	---	12108	/* FEXP2_W_1_PSEUDO */	---
12109	1280,	---	12109	1280,	---
12110	/* FILL_FD_PSEUDO */	---	12110	/* FILL_FD_PSEUDO */	---
12111	1282,	---	12111	1282,	---
12112	/* FILL_FW_PSEUDO */	---	12112	/* FILL_FW_PSEUDO */	---
12113	1284,	---	12113	1284,	---
12114	/* GotPrologue16 */	---	12114	/* GotPrologue16 */	---
12115	1286,	---	12115	1286,	---
12116	/* INSERT_B_VIDX64_PSEUDO */	---	12116	/* INSERT_B_VIDX64_PSEUDO */	---
12117	1290,	---	12117	1290,	---
12118	/* INSERT_B_VIDX_PSEUDO */	---	12118	/* INSERT_B_VIDX_PSEUDO */	---
12119	1294,	---	12119	1294,	---
12120	/* INSERT_D_VIDX64_PSEUDO */	---	12120	/* INSERT_D_VIDX64_PSEUDO */	---
12121	1298,	---	12121	1298,	---
12122	/* INSERT_D_VIDX_PSEUDO */	---	12122	/* INSERT_D_VIDX_PSEUDO */	---
12123	1302,	---	12123	1302,	---
12124	/* INSERT_FD_PSEUDO */	---	12124	/* INSERT_FD_PSEUDO */	---
12125	1306,	---	12125	1306,	---
12126	/* INSERT_FD_VIDX64_PSEUDO */	---	12126	/* INSERT_FD_VIDX64_PSEUDO */	---
12127	1310,	---	12127	1310,	---
12128	/* INSERT_FD_VIDX_PSEUDO */	---	12128	/* INSERT_FD_VIDX_PSEUDO */	---
12129	1314,	---	12129	1314,	---
12130	/* INSERT_FW_PSEUDO */	---	12130	/* INSERT_FW_PSEUDO */	---
12131	1318,	---	12131	1318,	---
12132	/* INSERT_FW_VIDX64_PSEUDO */	---	12132	/* INSERT_FW_VIDX64_PSEUDO */	---
12133	1322,	---	12133	1322,	---
12134	/* INSERT_FW_VIDX_PSEUDO */	---	12134	/* INSERT_FW_VIDX_PSEUDO */	---
12135	1326,	---	12135	1326,	---
12136	/* INSERT_H_VIDX64_PSEUDO */	---	12136	/* INSERT_H_VIDX64_PSEUDO */	---
12137	1330,	---	12137	1330,	---
12138	/* INSERT_H_VIDX_PSEUDO */	---	12138	/* INSERT_H_VIDX_PSEUDO */	---
12139	1334,	---	12139	1334,	---
12140	/* INSERT_W_VIDX64_PSEUDO */	---	12140	/* INSERT_W_VIDX64_PSEUDO */	---
12141	1338,	---	12141	1338,	---
12142	/* INSERT_W_VIDX_PSEUDO */	---	12142	/* INSERT_W_VIDX_PSEUDO */	---
12143	1342,	---	12143	1342,	---
12144	/* JALR64Pseudo */	---	12144	/* JALR64Pseudo */	---
12145	1346,	---	12145	1346,	---
12146	/* JALRHB64Pseudo */	---	12146	/* JALRHB64Pseudo */	---
12147	1347,	---	12147	1347,	---
12148	/* JALRHBPseudo */	---	12148	/* JALRHBPseudo */	---
12149	1348,	---	12149	1348,	---
12150	/* JALRPseudo */	---	12150	/* JALRPseudo */	---
12151	1349,	---	12151	1349,	---
12152	/* JAL_MMR6 */	---	12152	/* JAL_MMR6 */	---
12153	1350,	---	12153	1350,	---
12154	/* JalOneReg */	---	12154	/* JalOneReg */	---
12155	1351,	---	12155	1351,	---
12156	/* JalTwoReg */	---	12156	/* JalTwoReg */	---
12157	1352,	---	12157	1352,	---
12158	/* LDMacro */	---	12158	/* LDMacro */	---
12159	1354,	---	12159	1354,	---
12160	/* LDR_D */	---	12160	/* LDR_D */	---
12161	1357,	---	12161	1357,	---
12162	/* LDR_W */	---	12162	/* LDR_W */	---
12163	1360,	---	12163	1360,	---
12164	/* LD_F16 */	---	12164	/* LD_F16 */	---
12165	1363,	---	12165	1363,	---
12166	/* LOAD_ACC128 */	---	12166	/* LOAD_ACC128 */	---
12167	1366,	---	12167	1366,	---
12168	/* LOAD_ACC64 */	---	12168	/* LOAD_ACC64 */	---
12169	1369,	---	12169	1369,	---
12170	/* LOAD_ACC64DSP */	---	12170	/* LOAD_ACC64DSP */	---
12171	1372,	---	12171	1372,	---
12172	/* LOAD_CCOND_DSP */	---	12172	/* LOAD_CCOND_DSP */	---
12173	1375,	---	12173	1375,	---
12174	/* LONG_BRANCH_ADDiu */	---	12174	/* LONG_BRANCH_ADDiu */	---
12175	1378,	---	12175	1378,	---
12176	/* LONG_BRANCH_ADDiu2Op */	---	12176	/* LONG_BRANCH_ADDiu2Op */	---
12177	1382,	---	12177	1382,	---
12178	/* LONG_BRANCH_DADDiu */	---	12178	/* LONG_BRANCH_DADDiu */	---
12179	1385,	---	12179	1385,	---
12180	/* LONG_BRANCH_DADDiu2Op */	---	12180	/* LONG_BRANCH_DADDiu2Op */	---
12181	1389,	---	12181	1389,	---
12182	/* LONG_BRANCH_LUi */	---	12182	/* LONG_BRANCH_LUi */	---
12183	1392,	---	12183	1392,	---
12184	/* LONG_BRANCH_LUi2Op */	---	12184	/* LONG_BRANCH_LUi2Op */	---
12185	1395,	---	12185	1395,	---
12186	/* LONG_BRANCH_LUi2Op_64 */	---	12186	/* LONG_BRANCH_LUi2Op_64 */	---
12187	1397,	---	12187	1397,	---
12188	/* LWM_MM */	---	12188	/* LWM_MM */	---
12189	1399,	---	12189	1399,	---
12190	/* LoadAddrImm32 */	---	12190	/* LoadAddrImm32 */	---
12191	1402,	---	12191	1402,	---
12192	/* LoadAddrImm64 */	---	12192	/* LoadAddrImm64 */	---
12193	1404,	---	12193	1404,	---
12194	/* LoadAddrReg32 */	---	12194	/* LoadAddrReg32 */	---
12195	1406,	---	12195	1406,	---
12196	/* LoadAddrReg64 */	---	12196	/* LoadAddrReg64 */	---
12197	1409,	---	12197	1409,	---
12198	/* LoadImm32 */	---	12198	/* LoadImm32 */	---
12199	1412,	---	12199	1412,	---
12200	/* LoadImm64 */	---	12200	/* LoadImm64 */	---
12201	1414,	---	12201	1414,	---
12202	/* LoadImmDoubleFGR */	---	12202	/* LoadImmDoubleFGR */	---
12203	1416,	---	12203	1416,	---
12204	/* LoadImmDoubleFGR_32 */	---	12204	/* LoadImmDoubleFGR_32 */	---
12205	1418,	---	12205	1418,	---
12206	/* LoadImmDoubleGPR */	---	12206	/* LoadImmDoubleGPR */	---
12207	1420,	---	12207	1420,	---
12208	/* LoadImmSingleFGR */	---	12208	/* LoadImmSingleFGR */	---
12209	1422,	---	12209	1422,	---
12210	/* LoadImmSingleGPR */	---	12210	/* LoadImmSingleGPR */	---
12211	1424,	---	12211	1424,	---
12212	/* LwConstant32 */	---	12212	/* LwConstant32 */	---
12213	1426,	---	12213	1426,	---
12214	/* MFTACX */	---	12214	/* MFTACX */	---
12215	1429,	---	12215	1429,	---
12216	/* MFTC0 */	---	12216	/* MFTC0 */	---
12217	1431,	---	12217	1431,	---
12218	/* MFTC1 */	---	12218	/* MFTC1 */	---
12219	1434,	---	12219	1434,	---
12220	/* MFTDSP */	---	12220	/* MFTDSP */	---
12221	1436,	---	12221	1436,	---
12222	/* MFTGPR */	---	12222	/* MFTGPR */	---
12223	1437,	---	12223	1437,	---
12224	/* MFTHC1 */	---	12224	/* MFTHC1 */	---
12225	1440,	---	12225	1440,	---
12226	/* MFTHI */	---	12226	/* MFTHI */	---
12227	1442,	---	12227	1442,	---
12228	/* MFTLO */	---	12228	/* MFTLO */	---
12229	1444,	---	12229	1444,	---
12230	/* MIPSeh_return32 */	---	12230	/* MIPSeh_return32 */	---
12231	1446,	---	12231	1446,	---
12232	/* MIPSeh_return64 */	---	12232	/* MIPSeh_return64 */	---
12233	1448,	---	12233	1448,	---
12234	/* MSA_FP_EXTEND_D_PSEUDO */	---	12234	/* MSA_FP_EXTEND_D_PSEUDO */	---
12235	1450,	---	12235	1450,	---
12236	/* MSA_FP_EXTEND_W_PSEUDO */	---	12236	/* MSA_FP_EXTEND_W_PSEUDO */	---
12237	1452,	---	12237	1452,	---
12238	/* MSA_FP_ROUND_D_PSEUDO */	---	12238	/* MSA_FP_ROUND_D_PSEUDO */	---
12239	1454,	---	12239	1454,	---
12240	/* MSA_FP_ROUND_W_PSEUDO */	---	12240	/* MSA_FP_ROUND_W_PSEUDO */	---
12241	1456,	---	12241	1456,	---
12242	/* MTTACX */	---	12242	/* MTTACX */	---
12243	1458,	---	12243	1458,	---
12244	/* MTTC0 */	---	12244	/* MTTC0 */	---
12245	1460,	---	12245	1460,	---
12246	/* MTTC1 */	---	12246	/* MTTC1 */	---
12247	1463,	---	12247	1463,	---
12248	/* MTTDSP */	---	12248	/* MTTDSP */	---
12249	1465,	---	12249	1465,	---
12250	/* MTTGPR */	---	12250	/* MTTGPR */	---
12251	1466,	---	12251	1466,	---
12252	/* MTTHC1 */	---	12252	/* MTTHC1 */	---
12253	1468,	---	12253	1468,	---
12254	/* MTTHI */	---	12254	/* MTTHI */	---
12255	1470,	---	12255	1470,	---
12256	/* MTTLO */	---	12256	/* MTTLO */	---
12257	1472,	---	12257	1472,	---
12258	/* MULImmMacro */	---	12258	/* MULImmMacro */	---
12259	1474,	---	12259	1474,	---
12260	/* MULOMacro */	---	12260	/* MULOMacro */	---
12261	1477,	---	12261	1477,	---
12262	/* MULOUMacro */	---	12262	/* MULOUMacro */	---
12263	1480,	---	12263	1480,	---
12264	/* MultRxRy16 */	---	12264	/* MultRxRy16 */	---
12265	1483,	---	12265	1483,	---
12266	/* MultRxRyRz16 */	---	12266	/* MultRxRyRz16 */	---
12267	1485,	---	12267	1485,	---
12268	/* MultuRxRy16 */	---	12268	/* MultuRxRy16 */	---
12269	1488,	---	12269	1488,	---
12270	/* MultuRxRyRz16 */	---	12270	/* MultuRxRyRz16 */	---
12271	1490,	---	12271	1490,	---
12272	/* NOP */	---	12272	/* NOP */	---
12273	1493,	---	12273	1493,	---
12274	/* NORImm */	---	12274	/* NORImm */	---
12275	1493,	---	12275	1493,	---
12276	/* NORImm64 */	---	12276	/* NORImm64 */	---
12277	1496,	---	12277	1496,	---
12278	/* NOR_V_D_PSEUDO */	---	12278	/* NOR_V_D_PSEUDO */	---
12279	1499,	---	12279	1499,	---
12280	/* NOR_V_H_PSEUDO */	---	12280	/* NOR_V_H_PSEUDO */	---
12281	1502,	---	12281	1502,	---
12282	/* NOR_V_W_PSEUDO */	---	12282	/* NOR_V_W_PSEUDO */	---
12283	1505,	---	12283	1505,	---
12284	/* OR_V_D_PSEUDO */	---	12284	/* OR_V_D_PSEUDO */	---
12285	1508,	---	12285	1508,	---
12286	/* OR_V_H_PSEUDO */	---	12286	/* OR_V_H_PSEUDO */	---
12287	1511,	---	12287	1511,	---
12288	/* OR_V_W_PSEUDO */	---	12288	/* OR_V_W_PSEUDO */	---
12289	1514,	---	12289	1514,	---
12290	/* PseudoCMPU_EQ_QB */	---	12290	/* PseudoCMPU_EQ_QB */	---
12291	1517,	---	12291	1517,	---
12292	/* PseudoCMPU_LE_QB */	---	12292	/* PseudoCMPU_LE_QB */	---
12293	1520,	---	12293	1520,	---
12294	/* PseudoCMPU_LT_QB */	---	12294	/* PseudoCMPU_LT_QB */	---
12295	1523,	---	12295	1523,	---
12296	/* PseudoCMP_EQ_PH */	---	12296	/* PseudoCMP_EQ_PH */	---
12297	1526,	---	12297	1526,	---
12298	/* PseudoCMP_LE_PH */	---	12298	/* PseudoCMP_LE_PH */	---
12299	1529,	---	12299	1529,	---
12300	/* PseudoCMP_LT_PH */	---	12300	/* PseudoCMP_LT_PH */	---
12301	1532,	---	12301	1532,	---
12302	/* PseudoCVT_D32_W */	---	12302	/* PseudoCVT_D32_W */	---
12303	1535,	---	12303	1535,	---
12304	/* PseudoCVT_D64_L */	---	12304	/* PseudoCVT_D64_L */	---
12305	1537,	---	12305	1537,	---
12306	/* PseudoCVT_D64_W */	---	12306	/* PseudoCVT_D64_W */	---
12307	1539,	---	12307	1539,	---
12308	/* PseudoCVT_S_L */	---	12308	/* PseudoCVT_S_L */	---
12309	1541,	---	12309	1541,	---
12310	/* PseudoCVT_S_W */	---	12310	/* PseudoCVT_S_W */	---
12311	1543,	---	12311	1543,	---
12312	/* PseudoDMULT */	---	12312	/* PseudoDMULT */	---
12313	1545,	---	12313	1545,	---
12314	/* PseudoDMULTu */	---	12314	/* PseudoDMULTu */	---
12315	1548,	---	12315	1548,	---
12316	/* PseudoDSDIV */	---	12316	/* PseudoDSDIV */	---
12317	1551,	---	12317	1551,	---
12318	/* PseudoDUDIV */	---	12318	/* PseudoDUDIV */	---
12319	1554,	---	12319	1554,	---
12320	/* PseudoD_SELECT_I */	---	12320	/* PseudoD_SELECT_I */	---
12321	1557,	---	12321	1557,	---
12322	/* PseudoD_SELECT_I64 */	---	12322	/* PseudoD_SELECT_I64 */	---
12323	1564,	---	12323	1564,	---
12324	/* PseudoIndirectBranch */	---	12324	/* PseudoIndirectBranch */	---
12325	1571,	---	12325	1571,	---
12326	/* PseudoIndirectBranch64 */	---	12326	/* PseudoIndirectBranch64 */	---
12327	1572,	---	12327	1572,	---
12328	/* PseudoIndirectBranch64R6 */	---	12328	/* PseudoIndirectBranch64R6 */	---
12329	1573,	---	12329	1573,	---
12330	/* PseudoIndirectBranchR6 */	---	12330	/* PseudoIndirectBranchR6 */	---
12331	1574,	---	12331	1574,	---
12332	/* PseudoIndirectBranch_MM */	---	12332	/* PseudoIndirectBranch_MM */	---
12333	1575,	---	12333	1575,	---
12334	/* PseudoIndirectBranch_MMR6 */	---	12334	/* PseudoIndirectBranch_MMR6 */	---
12335	1576,	---	12335	1576,	---
12336	/* PseudoIndirectHazardBranch */	---	12336	/* PseudoIndirectHazardBranch */	---
12337	1577,	---	12337	1577,	---
12338	/* PseudoIndirectHazardBranch64 */	---	12338	/* PseudoIndirectHazardBranch64 */	---
12339	1578,	---	12339	1578,	---
12340	/* PseudoIndrectHazardBranch64R6 */	---	12340	/* PseudoIndrectHazardBranch64R6 */	---
12341	1579,	---	12341	1579,	---
12342	/* PseudoIndrectHazardBranchR6 */	---	12342	/* PseudoIndrectHazardBranchR6 */	---
12343	1580,	---	12343	1580,	---
12344	/* PseudoMADD */	---	12344	/* PseudoMADD */	---
12345	1581,	---	12345	1581,	---
12346	/* PseudoMADDU */	---	12346	/* PseudoMADDU */	---
12347	1585,	---	12347	1585,	---
12348	/* PseudoMADDU_MM */	---	12348	/* PseudoMADDU_MM */	---
12349	1589,	---	12349	1589,	---
12350	/* PseudoMADD_MM */	---	12350	/* PseudoMADD_MM */	---
12351	1593,	---	12351	1593,	---
12352	/* PseudoMFHI */	---	12352	/* PseudoMFHI */	---
12353	1597,	---	12353	1597,	---
12354	/* PseudoMFHI64 */	---	12354	/* PseudoMFHI64 */	---
12355	1599,	---	12355	1599,	---
12356	/* PseudoMFHI_MM */	---	12356	/* PseudoMFHI_MM */	---
12357	1601,	---	12357	1601,	---
12358	/* PseudoMFLO */	---	12358	/* PseudoMFLO */	---
12359	1603,	---	12359	1603,	---
12360	/* PseudoMFLO64 */	---	12360	/* PseudoMFLO64 */	---
12361	1605,	---	12361	1605,	---
12362	/* PseudoMFLO_MM */	---	12362	/* PseudoMFLO_MM */	---
12363	1607,	---	12363	1607,	---
12364	/* PseudoMSUB */	---	12364	/* PseudoMSUB */	---
12365	1609,	---	12365	1609,	---
12366	/* PseudoMSUBU */	---	12366	/* PseudoMSUBU */	---
12367	1613,	---	12367	1613,	---
12368	/* PseudoMSUBU_MM */	---	12368	/* PseudoMSUBU_MM */	---
12369	1617,	---	12369	1617,	---
12370	/* PseudoMSUB_MM */	---	12370	/* PseudoMSUB_MM */	---
12371	1621,	---	12371	1621,	---
12372	/* PseudoMTLOHI */	---	12372	/* PseudoMTLOHI */	---
12373	1625,	---	12373	1625,	---
12374	/* PseudoMTLOHI64 */	---	12374	/* PseudoMTLOHI64 */	---
12375	1628,	---	12375	1628,	---
12376	/* PseudoMTLOHI_DSP */	---	12376	/* PseudoMTLOHI_DSP */	---
12377	1631,	---	12377	1631,	---
12378	/* PseudoMTLOHI_MM */	---	12378	/* PseudoMTLOHI_MM */	---
12379	1634,	---	12379	1634,	---
12380	/* PseudoMULT */	---	12380	/* PseudoMULT */	---
12381	1637,	---	12381	1637,	---
12382	/* PseudoMULT_MM */	---	12382	/* PseudoMULT_MM */	---
12383	1640,	---	12383	1640,	---
12384	/* PseudoMULTu */	---	12384	/* PseudoMULTu */	---
12385	1643,	---	12385	1643,	---
12386	/* PseudoMULTu_MM */	---	12386	/* PseudoMULTu_MM */	---
12387	1646,	---	12387	1646,	---
12388	/* PseudoPICK_PH */	---	12388	/* PseudoPICK_PH */	---
12389	1649,	---	12389	1649,	---
12390	/* PseudoPICK_QB */	---	12390	/* PseudoPICK_QB */	---
12391	1653,	---	12391	1653,	---
12392	/* PseudoReturn */	---	12392	/* PseudoReturn */	---
12393	1657,	---	12393	1657,	---
12394	/* PseudoReturn64 */	---	12394	/* PseudoReturn64 */	---
12395	1658,	---	12395	1658,	---
12396	/* PseudoSDIV */	---	12396	/* PseudoSDIV */	---
12397	1659,	---	12397	1659,	---
12398	/* PseudoSELECTFP_F_D32 */	---	12398	/* PseudoSELECTFP_F_D32 */	---
12399	1662,	---	12399	1662,	---
12400	/* PseudoSELECTFP_F_D64 */	---	12400	/* PseudoSELECTFP_F_D64 */	---
12401	1666,	---	12401	1666,	---
12402	/* PseudoSELECTFP_F_I */	---	12402	/* PseudoSELECTFP_F_I */	---
12403	1670,	---	12403	1670,	---
12404	/* PseudoSELECTFP_F_I64 */	---	12404	/* PseudoSELECTFP_F_I64 */	---
12405	1674,	---	12405	1674,	---
12406	/* PseudoSELECTFP_F_S */	---	12406	/* PseudoSELECTFP_F_S */	---
12407	1678,	---	12407	1678,	---
12408	/* PseudoSELECTFP_T_D32 */	---	12408	/* PseudoSELECTFP_T_D32 */	---
12409	1682,	---	12409	1682,	---
12410	/* PseudoSELECTFP_T_D64 */	---	12410	/* PseudoSELECTFP_T_D64 */	---
12411	1686,	---	12411	1686,	---
12412	/* PseudoSELECTFP_T_I */	---	12412	/* PseudoSELECTFP_T_I */	---
12413	1690,	---	12413	1690,	---
12414	/* PseudoSELECTFP_T_I64 */	---	12414	/* PseudoSELECTFP_T_I64 */	---
12415	1694,	---	12415	1694,	---
12416	/* PseudoSELECTFP_T_S */	---	12416	/* PseudoSELECTFP_T_S */	---
12417	1698,	---	12417	1698,	---
12418	/* PseudoSELECT_D32 */	---	12418	/* PseudoSELECT_D32 */	---
12419	1702,	---	12419	1702,	---
12420	/* PseudoSELECT_D64 */	---	12420	/* PseudoSELECT_D64 */	---
12421	1706,	---	12421	1706,	---
12422	/* PseudoSELECT_I */	---	12422	/* PseudoSELECT_I */	---
12423	1710,	---	12423	1710,	---
12424	/* PseudoSELECT_I64 */	---	12424	/* PseudoSELECT_I64 */	---
12425	1714,	---	12425	1714,	---
12426	/* PseudoSELECT_S */	---	12426	/* PseudoSELECT_S */	---
12427	1718,	---	12427	1718,	---
12428	/* PseudoTRUNC_W_D */	---	12428	/* PseudoTRUNC_W_D */	---
12429	1722,	---	12429	1722,	---
12430	/* PseudoTRUNC_W_D32 */	---	12430	/* PseudoTRUNC_W_D32 */	---
12431	1725,	---	12431	1725,	---
12432	/* PseudoTRUNC_W_S */	---	12432	/* PseudoTRUNC_W_S */	---
12433	1728,	---	12433	1728,	---
12434	/* PseudoUDIV */	---	12434	/* PseudoUDIV */	---
12435	1731,	---	12435	1731,	---
12436	/* ROL */	---	12436	/* ROL */	---
12437	1734,	---	12437	1734,	---
12438	/* ROLImm */	---	12438	/* ROLImm */	---
12439	1737,	---	12439	1737,	---
12440	/* ROR */	---	12440	/* ROR */	---
12441	1740,	---	12441	1740,	---
12442	/* RORImm */	---	12442	/* RORImm */	---
12443	1743,	---	12443	1743,	---
12444	/* RetRA */	---	12444	/* RetRA */	---
12445	1746,	---	12445	1746,	---
12446	/* RetRA16 */	---	12446	/* RetRA16 */	---
12447	1746,	---	12447	1746,	---
12448	/* SDC1_M1 */	---	12448	/* SDC1_M1 */	---
12449	1746,	---	12449	1746,	---
12450	/* SDIV_MM_Pseudo */	---	12450	/* SDIV_MM_Pseudo */	---
12451	1749,	---	12451	1749,	---
12452	/* SDMacro */	---	12452	/* SDMacro */	---
12453	1752,	---	12453	1752,	---
12454	/* SDivIMacro */	---	12454	/* SDivIMacro */	---
12455	1755,	---	12455	1755,	---
12456	/* SDivMacro */	---	12456	/* SDivMacro */	---
12457	1758,	---	12457	1758,	---
12458	/* SEQIMacro */	---	12458	/* SEQIMacro */	---
12459	1761,	---	12459	1761,	---
12460	/* SEQMacro */	---	12460	/* SEQMacro */	---
12461	1764,	---	12461	1764,	---
12462	/* SGE */	---	12462	/* SGE */	---
12463	1767,	---	12463	1767,	---
12464	/* SGEImm */	---	12464	/* SGEImm */	---
12465	1770,	---	12465	1770,	---
12466	/* SGEImm64 */	---	12466	/* SGEImm64 */	---
12467	1773,	---	12467	1773,	---
12468	/* SGEU */	---	12468	/* SGEU */	---
12469	1776,	---	12469	1776,	---
12470	/* SGEUImm */	---	12470	/* SGEUImm */	---
12471	1779,	---	12471	1779,	---
12472	/* SGEUImm64 */	---	12472	/* SGEUImm64 */	---
12473	1782,	---	12473	1782,	---
12474	/* SGTImm */	---	12474	/* SGTImm */	---
12475	1785,	---	12475	1785,	---
12476	/* SGTImm64 */	---	12476	/* SGTImm64 */	---
12477	1788,	---	12477	1788,	---
12478	/* SGTUImm */	---	12478	/* SGTUImm */	---
12479	1791,	---	12479	1791,	---
12480	/* SGTUImm64 */	---	12480	/* SGTUImm64 */	---
12481	1794,	---	12481	1794,	---
12482	/* SLE */	---	12482	/* SLE */	---
12483	1797,	---	12483	1797,	---
12484	/* SLEImm */	---	12484	/* SLEImm */	---
12485	1800,	---	12485	1800,	---
12486	/* SLEImm64 */	---	12486	/* SLEImm64 */	---
12487	1803,	---	12487	1803,	---
12488	/* SLEU */	---	12488	/* SLEU */	---
12489	1806,	---	12489	1806,	---
12490	/* SLEUImm */	---	12490	/* SLEUImm */	---
12491	1809,	---	12491	1809,	---
12492	/* SLEUImm64 */	---	12492	/* SLEUImm64 */	---
12493	1812,	---	12493	1812,	---
12494	/* SLTImm64 */	---	12494	/* SLTImm64 */	---
12495	1815,	---	12495	1815,	---
12496	/* SLTUImm64 */	---	12496	/* SLTUImm64 */	---
12497	1818,	---	12497	1818,	---
12498	/* SNEIMacro */	---	12498	/* SNEIMacro */	---
12499	1821,	---	12499	1821,	---
12500	/* SNEMacro */	---	12500	/* SNEMacro */	---
12501	1824,	---	12501	1824,	---
12502	/* SNZ_B_PSEUDO */	---	12502	/* SNZ_B_PSEUDO */	---
12503	1827,	---	12503	1827,	---
12504	/* SNZ_D_PSEUDO */	---	12504	/* SNZ_D_PSEUDO */	---
12505	1829,	---	12505	1829,	---
12506	/* SNZ_H_PSEUDO */	---	12506	/* SNZ_H_PSEUDO */	---
12507	1831,	---	12507	1831,	---
12508	/* SNZ_V_PSEUDO */	---	12508	/* SNZ_V_PSEUDO */	---
12509	1833,	---	12509	1833,	---
12510	/* SNZ_W_PSEUDO */	---	12510	/* SNZ_W_PSEUDO */	---
12511	1835,	---	12511	1835,	---
12512	/* SRemIMacro */	---	12512	/* SRemIMacro */	---
12513	1837,	---	12513	1837,	---
12514	/* SRemMacro */	---	12514	/* SRemMacro */	---
12515	1840,	---	12515	1840,	---
12516	/* STORE_ACC128 */	---	12516	/* STORE_ACC128 */	---
12517	1843,	---	12517	1843,	---
12518	/* STORE_ACC64 */	---	12518	/* STORE_ACC64 */	---
12519	1846,	---	12519	1846,	---
12520	/* STORE_ACC64DSP */	---	12520	/* STORE_ACC64DSP */	---
12521	1849,	---	12521	1849,	---
12522	/* STORE_CCOND_DSP */	---	12522	/* STORE_CCOND_DSP */	---
12523	1852,	---	12523	1852,	---
12524	/* STR_D */	---	12524	/* STR_D */	---
12525	1855,	---	12525	1855,	---
12526	/* STR_W */	---	12526	/* STR_W */	---
12527	1858,	---	12527	1858,	---
12528	/* ST_F16 */	---	12528	/* ST_F16 */	---
12529	1861,	---	12529	1861,	---
12530	/* SWM_MM */	---	12530	/* SWM_MM */	---
12531	1864,	---	12531	1864,	---
12532	/* SZ_B_PSEUDO */	---	12532	/* SZ_B_PSEUDO */	---
12533	1867,	---	12533	1867,	---
12534	/* SZ_D_PSEUDO */	---	12534	/* SZ_D_PSEUDO */	---
12535	1869,	---	12535	1869,	---
12536	/* SZ_H_PSEUDO */	---	12536	/* SZ_H_PSEUDO */	---
12537	1871,	---	12537	1871,	---
12538	/* SZ_V_PSEUDO */	---	12538	/* SZ_V_PSEUDO */	---
12539	1873,	---	12539	1873,	---
12540	/* SZ_W_PSEUDO */	---	12540	/* SZ_W_PSEUDO */	---
12541	1875,	---	12541	1875,	---
12542	/* SaaAddr */	---	12542	/* SaaAddr */	---
12543	1877,	---	12543	1877,	---
12544	/* SaadAddr */	---	12544	/* SaadAddr */	---
12545	1880,	---	12545	1880,	---
12546	/* SelBeqZ */	---	12546	/* SelBeqZ */	---
12547	1883,	---	12547	1883,	---
12548	/* SelBneZ */	---	12548	/* SelBneZ */	---
12549	1887,	---	12549	1887,	---
12550	/* SelTBteqZCmp */	---	12550	/* SelTBteqZCmp */	---
12551	1891,	---	12551	1891,	---
12552	/* SelTBteqZCmpi */	---	12552	/* SelTBteqZCmpi */	---
12553	1896,	---	12553	1896,	---
12554	/* SelTBteqZSlt */	---	12554	/* SelTBteqZSlt */	---
12555	1901,	---	12555	1901,	---
12556	/* SelTBteqZSlti */	---	12556	/* SelTBteqZSlti */	---
12557	1906,	---	12557	1906,	---
12558	/* SelTBteqZSltiu */	---	12558	/* SelTBteqZSltiu */	---
12559	1911,	---	12559	1911,	---
12560	/* SelTBteqZSltu */	---	12560	/* SelTBteqZSltu */	---
12561	1916,	---	12561	1916,	---
12562	/* SelTBtneZCmp */	---	12562	/* SelTBtneZCmp */	---
12563	1921,	---	12563	1921,	---
12564	/* SelTBtneZCmpi */	---	12564	/* SelTBtneZCmpi */	---
12565	1926,	---	12565	1926,	---
12566	/* SelTBtneZSlt */	---	12566	/* SelTBtneZSlt */	---
12567	1931,	---	12567	1931,	---
12568	/* SelTBtneZSlti */	---	12568	/* SelTBtneZSlti */	---
12569	1936,	---	12569	1936,	---
12570	/* SelTBtneZSltiu */	---	12570	/* SelTBtneZSltiu */	---
12571	1941,	---	12571	1941,	---
12572	/* SelTBtneZSltu */	---	12572	/* SelTBtneZSltu */	---
12573	1946,	---	12573	1946,	---
12574	/* SltCCRxRy16 */	---	12574	/* SltCCRxRy16 */	---
12575	1951,	---	12575	1951,	---
12576	/* SltiCCRxImmX16 */	---	12576	/* SltiCCRxImmX16 */	---
12577	1954,	---	12577	1954,	---
12578	/* SltiuCCRxImmX16 */	---	12578	/* SltiuCCRxImmX16 */	---
12579	1957,	---	12579	1957,	---
12580	/* SltuCCRxRy16 */	---	12580	/* SltuCCRxRy16 */	---
12581	1960,	---	12581	1960,	---
12582	/* SltuRxRyRz16 */	---	12582	/* SltuRxRyRz16 */	---
12583	1963,	---	12583	1963,	---
12584	/* TAILCALL */	---	12584	/* TAILCALL */	---
12585	1966,	---	12585	1966,	---
12586	/* TAILCALL64R6REG */	---	12586	/* TAILCALL64R6REG */	---
12587	1967,	---	12587	1967,	---
12588	/* TAILCALLHB64R6REG */	---	12588	/* TAILCALLHB64R6REG */	---
12589	1968,	---	12589	1968,	---
12590	/* TAILCALLHBR6REG */	---	12590	/* TAILCALLHBR6REG */	---
12591	1969,	---	12591	1969,	---
12592	/* TAILCALLR6REG */	---	12592	/* TAILCALLR6REG */	---
12593	1970,	---	12593	1970,	---
12594	/* TAILCALLREG */	---	12594	/* TAILCALLREG */	---
12595	1971,	---	12595	1971,	---
12596	/* TAILCALLREG64 */	---	12596	/* TAILCALLREG64 */	---
12597	1972,	---	12597	1972,	---
12598	/* TAILCALLREGHB */	---	12598	/* TAILCALLREGHB */	---
12599	1973,	---	12599	1973,	---
12600	/* TAILCALLREGHB64 */	---	12600	/* TAILCALLREGHB64 */	---
12601	1974,	---	12601	1974,	---
12602	/* TAILCALLREG_MM */	---	12602	/* TAILCALLREG_MM */	---
12603	1975,	---	12603	1975,	---
12604	/* TAILCALLREG_MMR6 */	---	12604	/* TAILCALLREG_MMR6 */	---
12605	1976,	---	12605	1976,	---
12606	/* TAILCALL_MM */	---	12606	/* TAILCALL_MM */	---
12607	1977,	---	12607	1977,	---
12608	/* TAILCALL_MMR6 */	---	12608	/* TAILCALL_MMR6 */	---
12609	1978,	---	12609	1978,	---
12610	/* TRAP */	---	12610	/* TRAP */	---
12611	1979,	---	12611	1979,	---
12612	/* TRAP_MM */	---	12612	/* TRAP_MM */	---
12613	1979,	---	12613	1979,	---
12614	/* UDIV_MM_Pseudo */	---	12614	/* UDIV_MM_Pseudo */	---
12615	1979,	---	12615	1979,	---
12616	/* UDivIMacro */	---	12616	/* UDivIMacro */	---
12617	1982,	---	12617	1982,	---
12618	/* UDivMacro */	---	12618	/* UDivMacro */	---
12619	1985,	---	12619	1985,	---
12620	/* URemIMacro */	---	12620	/* URemIMacro */	---
12621	1988,	---	12621	1988,	---
12622	/* URemMacro */	---	12622	/* URemMacro */	---
12623	1991,	---	12623	1991,	---
12624	/* Ulh */	---	12624	/* Ulh */	---
12625	1994,	---	12625	1994,	---
12626	/* Ulhu */	---	12626	/* Ulhu */	---
12627	1997,	---	12627	1997,	---
12628	/* Ulw */	---	12628	/* Ulw */	---
12629	2000,	---	12629	2000,	---
12630	/* Ush */	---	12630	/* Ush */	---
12631	2003,	---	12631	2003,	---
12632	/* Usw */	---	12632	/* Usw */	---
12633	2006,	---	12633	2006,	---
12634	/* XOR_V_D_PSEUDO */	---	12634	/* XOR_V_D_PSEUDO */	---
12635	2009,	---	12635	2009,	---
12636	/* XOR_V_H_PSEUDO */	---	12636	/* XOR_V_H_PSEUDO */	---
12637	2012,	---	12637	2012,	---
12638	/* XOR_V_W_PSEUDO */	---	12638	/* XOR_V_W_PSEUDO */	---
12639	2015,	---	12639	2015,	---
12640	/* ABSQ_S_PH */	---	12640	/* ABSQ_S_PH */	---
12641	2018,	---	12641	2018,	---
12642	/* ABSQ_S_PH_MM */	---	12642	/* ABSQ_S_PH_MM */	---
12643	2020,	---	12643	2020,	---
12644	/* ABSQ_S_QB */	---	12644	/* ABSQ_S_QB */	---
12645	2022,	---	12645	2022,	---
12646	/* ABSQ_S_QB_MMR2 */	---	12646	/* ABSQ_S_QB_MMR2 */	---
12647	2024,	---	12647	2024,	---
12648	/* ABSQ_S_W */	---	12648	/* ABSQ_S_W */	---
12649	2026,	---	12649	2026,	---
12650	/* ABSQ_S_W_MM */	---	12650	/* ABSQ_S_W_MM */	---
12651	2028,	---	12651	2028,	---
12652	/* ADD */	---	12652	/* ADD */	---
12653	2030,	---	12653	2030,	---
12654	/* ADDIUPC */	---	12654	/* ADDIUPC */	---
12655	2033,	---	12655	2033,	---
12656	/* ADDIUPC_MM */	---	12656	/* ADDIUPC_MM */	---
12657	2035,	---	12657	2035,	---
12658	/* ADDIUPC_MMR6 */	---	12658	/* ADDIUPC_MMR6 */	---
12659	2037,	---	12659	2037,	---
12660	/* ADDIUR1SP_MM */	---	12660	/* ADDIUR1SP_MM */	---
12661	2039,	---	12661	2039,	---
12662	/* ADDIUR2_MM */	---	12662	/* ADDIUR2_MM */	---
12663	2041,	---	12663	2041,	---
12664	/* ADDIUS5_MM */	---	12664	/* ADDIUS5_MM */	---
12665	2044,	---	12665	2044,	---
12666	/* ADDIUSP_MM */	---	12666	/* ADDIUSP_MM */	---
12667	2047,	---	12667	2047,	---
12668	/* ADDIU_MMR6 */	---	12668	/* ADDIU_MMR6 */	---
12669	2048,	---	12669	2048,	---
12670	/* ADDQH_PH */	---	12670	/* ADDQH_PH */	---
12671	2051,	---	12671	2051,	---
12672	/* ADDQH_PH_MMR2 */	---	12672	/* ADDQH_PH_MMR2 */	---
12673	2054,	---	12673	2054,	---
12674	/* ADDQH_R_PH */	---	12674	/* ADDQH_R_PH */	---
12675	2057,	---	12675	2057,	---
12676	/* ADDQH_R_PH_MMR2 */	---	12676	/* ADDQH_R_PH_MMR2 */	---
12677	2060,	---	12677	2060,	---
12678	/* ADDQH_R_W */	---	12678	/* ADDQH_R_W */	---
12679	2063,	---	12679	2063,	---
12680	/* ADDQH_R_W_MMR2 */	---	12680	/* ADDQH_R_W_MMR2 */	---
12681	2066,	---	12681	2066,	---
12682	/* ADDQH_W */	---	12682	/* ADDQH_W */	---
12683	2069,	---	12683	2069,	---
12684	/* ADDQH_W_MMR2 */	---	12684	/* ADDQH_W_MMR2 */	---
12685	2072,	---	12685	2072,	---
12686	/* ADDQ_PH */	---	12686	/* ADDQ_PH */	---
12687	2075,	---	12687	2075,	---
12688	/* ADDQ_PH_MM */	---	12688	/* ADDQ_PH_MM */	---
12689	2078,	---	12689	2078,	---
12690	/* ADDQ_S_PH */	---	12690	/* ADDQ_S_PH */	---
12691	2081,	---	12691	2081,	---
12692	/* ADDQ_S_PH_MM */	---	12692	/* ADDQ_S_PH_MM */	---
12693	2084,	---	12693	2084,	---
12694	/* ADDQ_S_W */	---	12694	/* ADDQ_S_W */	---
12695	2087,	---	12695	2087,	---
12696	/* ADDQ_S_W_MM */	---	12696	/* ADDQ_S_W_MM */	---
12697	2090,	---	12697	2090,	---
12698	/* ADDR_PS64 */	---	12698	/* ADDR_PS64 */	---
12699	2093,	---	12699	2093,	---
12700	/* ADDSC */	---	12700	/* ADDSC */	---
12701	2096,	---	12701	2096,	---
12702	/* ADDSC_MM */	---	12702	/* ADDSC_MM */	---
12703	2099,	---	12703	2099,	---
12704	/* ADDS_A_B */	---	12704	/* ADDS_A_B */	---
12705	2102,	---	12705	2102,	---
12706	/* ADDS_A_D */	---	12706	/* ADDS_A_D */	---
12707	2105,	---	12707	2105,	---
12708	/* ADDS_A_H */	---	12708	/* ADDS_A_H */	---
12709	2108,	---	12709	2108,	---
12710	/* ADDS_A_W */	---	12710	/* ADDS_A_W */	---
12711	2111,	---	12711	2111,	---
12712	/* ADDS_S_B */	---	12712	/* ADDS_S_B */	---
12713	2114,	---	12713	2114,	---
12714	/* ADDS_S_D */	---	12714	/* ADDS_S_D */	---
12715	2117,	---	12715	2117,	---
12716	/* ADDS_S_H */	---	12716	/* ADDS_S_H */	---
12717	2120,	---	12717	2120,	---
12718	/* ADDS_S_W */	---	12718	/* ADDS_S_W */	---
12719	2123,	---	12719	2123,	---
12720	/* ADDS_U_B */	---	12720	/* ADDS_U_B */	---
12721	2126,	---	12721	2126,	---
12722	/* ADDS_U_D */	---	12722	/* ADDS_U_D */	---
12723	2129,	---	12723	2129,	---
12724	/* ADDS_U_H */	---	12724	/* ADDS_U_H */	---
12725	2132,	---	12725	2132,	---
12726	/* ADDS_U_W */	---	12726	/* ADDS_U_W */	---
12727	2135,	---	12727	2135,	---
12728	/* ADDU16_MM */	---	12728	/* ADDU16_MM */	---
12729	2138,	---	12729	2138,	---
12730	/* ADDU16_MMR6 */	---	12730	/* ADDU16_MMR6 */	---
12731	2141,	---	12731	2141,	---
12732	/* ADDUH_QB */	---	12732	/* ADDUH_QB */	---
12733	2144,	---	12733	2144,	---
12734	/* ADDUH_QB_MMR2 */	---	12734	/* ADDUH_QB_MMR2 */	---
12735	2147,	---	12735	2147,	---
12736	/* ADDUH_R_QB */	---	12736	/* ADDUH_R_QB */	---
12737	2150,	---	12737	2150,	---
12738	/* ADDUH_R_QB_MMR2 */	---	12738	/* ADDUH_R_QB_MMR2 */	---
12739	2153,	---	12739	2153,	---
12740	/* ADDU_MMR6 */	---	12740	/* ADDU_MMR6 */	---
12741	2156,	---	12741	2156,	---
12742	/* ADDU_PH */	---	12742	/* ADDU_PH */	---
12743	2159,	---	12743	2159,	---
12744	/* ADDU_PH_MMR2 */	---	12744	/* ADDU_PH_MMR2 */	---
12745	2162,	---	12745	2162,	---
12746	/* ADDU_QB */	---	12746	/* ADDU_QB */	---
12747	2165,	---	12747	2165,	---
12748	/* ADDU_QB_MM */	---	12748	/* ADDU_QB_MM */	---
12749	2168,	---	12749	2168,	---
12750	/* ADDU_S_PH */	---	12750	/* ADDU_S_PH */	---
12751	2171,	---	12751	2171,	---
12752	/* ADDU_S_PH_MMR2 */	---	12752	/* ADDU_S_PH_MMR2 */	---
12753	2174,	---	12753	2174,	---
12754	/* ADDU_S_QB */	---	12754	/* ADDU_S_QB */	---
12755	2177,	---	12755	2177,	---
12756	/* ADDU_S_QB_MM */	---	12756	/* ADDU_S_QB_MM */	---
12757	2180,	---	12757	2180,	---
12758	/* ADDVI_B */	---	12758	/* ADDVI_B */	---
12759	2183,	---	12759	2183,	---
12760	/* ADDVI_D */	---	12760	/* ADDVI_D */	---
12761	2186,	---	12761	2186,	---
12762	/* ADDVI_H */	---	12762	/* ADDVI_H */	---
12763	2189,	---	12763	2189,	---
12764	/* ADDVI_W */	---	12764	/* ADDVI_W */	---
12765	2192,	---	12765	2192,	---
12766	/* ADDV_B */	---	12766	/* ADDV_B */	---
12767	2195,	---	12767	2195,	---
12768	/* ADDV_D */	---	12768	/* ADDV_D */	---
12769	2198,	---	12769	2198,	---
12770	/* ADDV_H */	---	12770	/* ADDV_H */	---
12771	2201,	---	12771	2201,	---
12772	/* ADDV_W */	---	12772	/* ADDV_W */	---
12773	2204,	---	12773	2204,	---
12774	/* ADDWC */	---	12774	/* ADDWC */	---
12775	2207,	---	12775	2207,	---
12776	/* ADDWC_MM */	---	12776	/* ADDWC_MM */	---
12777	2210,	---	12777	2210,	---
12778	/* ADD_A_B */	---	12778	/* ADD_A_B */	---
12779	2213,	---	12779	2213,	---
12780	/* ADD_A_D */	---	12780	/* ADD_A_D */	---
12781	2216,	---	12781	2216,	---
12782	/* ADD_A_H */	---	12782	/* ADD_A_H */	---
12783	2219,	---	12783	2219,	---
12784	/* ADD_A_W */	---	12784	/* ADD_A_W */	---
12785	2222,	---	12785	2222,	---
12786	/* ADD_MM */	---	12786	/* ADD_MM */	---
12787	2225,	---	12787	2225,	---
12788	/* ADD_MMR6 */	---	12788	/* ADD_MMR6 */	---
12789	2228,	---	12789	2228,	---
12790	/* ADDi */	---	12790	/* ADDi */	---
12791	2231,	---	12791	2231,	---
12792	/* ADDi_MM */	---	12792	/* ADDi_MM */	---
12793	2234,	---	12793	2234,	---
12794	/* ADDiu */	---	12794	/* ADDiu */	---
12795	2237,	---	12795	2237,	---
12796	/* ADDiu_MM */	---	12796	/* ADDiu_MM */	---
12797	2240,	---	12797	2240,	---
12798	/* ADDu */	---	12798	/* ADDu */	---
12799	2243,	---	12799	2243,	---
12800	/* ADDu_MM */	---	12800	/* ADDu_MM */	---
12801	2246,	---	12801	2246,	---
12802	/* ALIGN */	---	12802	/* ALIGN */	---
12803	2249,	---	12803	2249,	---
12804	/* ALIGN_MMR6 */	---	12804	/* ALIGN_MMR6 */	---
12805	2253,	---	12805	2253,	---
12806	/* ALUIPC */	---	12806	/* ALUIPC */	---
12807	2257,	---	12807	2257,	---
12808	/* ALUIPC_MMR6 */	---	12808	/* ALUIPC_MMR6 */	---
12809	2259,	---	12809	2259,	---
12810	/* AND */	---	12810	/* AND */	---
12811	2261,	---	12811	2261,	---
12812	/* AND16_MM */	---	12812	/* AND16_MM */	---
12813	2264,	---	12813	2264,	---
12814	/* AND16_MMR6 */	---	12814	/* AND16_MMR6 */	---
12815	2267,	---	12815	2267,	---
12816	/* AND64 */	---	12816	/* AND64 */	---
12817	2270,	---	12817	2270,	---
12818	/* ANDI16_MM */	---	12818	/* ANDI16_MM */	---
12819	2273,	---	12819	2273,	---
12820	/* ANDI16_MMR6 */	---	12820	/* ANDI16_MMR6 */	---
12821	2276,	---	12821	2276,	---
12822	/* ANDI_B */	---	12822	/* ANDI_B */	---
12823	2279,	---	12823	2279,	---
12824	/* ANDI_MMR6 */	---	12824	/* ANDI_MMR6 */	---
12825	2282,	---	12825	2282,	---
12826	/* AND_MM */	---	12826	/* AND_MM */	---
12827	2285,	---	12827	2285,	---
12828	/* AND_MMR6 */	---	12828	/* AND_MMR6 */	---
12829	2288,	---	12829	2288,	---
12830	/* AND_V */	---	12830	/* AND_V */	---
12831	2291,	---	12831	2291,	---
12832	/* ANDi */	---	12832	/* ANDi */	---
12833	2294,	---	12833	2294,	---
12834	/* ANDi64 */	---	12834	/* ANDi64 */	---
12835	2297,	---	12835	2297,	---
12836	/* ANDi_MM */	---	12836	/* ANDi_MM */	---
12837	2300,	---	12837	2300,	---
12838	/* APPEND */	---	12838	/* APPEND */	---
12839	2303,	---	12839	2303,	---
12840	/* APPEND_MMR2 */	---	12840	/* APPEND_MMR2 */	---
12841	2307,	---	12841	2307,	---
12842	/* ASUB_S_B */	---	12842	/* ASUB_S_B */	---
12843	2311,	---	12843	2311,	---
12844	/* ASUB_S_D */	---	12844	/* ASUB_S_D */	---
12845	2314,	---	12845	2314,	---
12846	/* ASUB_S_H */	---	12846	/* ASUB_S_H */	---
12847	2317,	---	12847	2317,	---
12848	/* ASUB_S_W */	---	12848	/* ASUB_S_W */	---
12849	2320,	---	12849	2320,	---
12850	/* ASUB_U_B */	---	12850	/* ASUB_U_B */	---
12851	2323,	---	12851	2323,	---
12852	/* ASUB_U_D */	---	12852	/* ASUB_U_D */	---
12853	2326,	---	12853	2326,	---
12854	/* ASUB_U_H */	---	12854	/* ASUB_U_H */	---
12855	2329,	---	12855	2329,	---
12856	/* ASUB_U_W */	---	12856	/* ASUB_U_W */	---
12857	2332,	---	12857	2332,	---
12858	/* AUI */	---	12858	/* AUI */	---
12859	2335,	---	12859	2335,	---
12860	/* AUIPC */	---	12860	/* AUIPC */	---
12861	2338,	---	12861	2338,	---
12862	/* AUIPC_MMR6 */	---	12862	/* AUIPC_MMR6 */	---
12863	2340,	---	12863	2340,	---
12864	/* AUI_MMR6 */	---	12864	/* AUI_MMR6 */	---
12865	2342,	---	12865	2342,	---
12866	/* AVER_S_B */	---	12866	/* AVER_S_B */	---
12867	2345,	---	12867	2345,	---
12868	/* AVER_S_D */	---	12868	/* AVER_S_D */	---
12869	2348,	---	12869	2348,	---
12870	/* AVER_S_H */	---	12870	/* AVER_S_H */	---
12871	2351,	---	12871	2351,	---
12872	/* AVER_S_W */	---	12872	/* AVER_S_W */	---
12873	2354,	---	12873	2354,	---
12874	/* AVER_U_B */	---	12874	/* AVER_U_B */	---
12875	2357,	---	12875	2357,	---
12876	/* AVER_U_D */	---	12876	/* AVER_U_D */	---
12877	2360,	---	12877	2360,	---
12878	/* AVER_U_H */	---	12878	/* AVER_U_H */	---
12879	2363,	---	12879	2363,	---
12880	/* AVER_U_W */	---	12880	/* AVER_U_W */	---
12881	2366,	---	12881	2366,	---
12882	/* AVE_S_B */	---	12882	/* AVE_S_B */	---
12883	2369,	---	12883	2369,	---
12884	/* AVE_S_D */	---	12884	/* AVE_S_D */	---
12885	2372,	---	12885	2372,	---
12886	/* AVE_S_H */	---	12886	/* AVE_S_H */	---
12887	2375,	---	12887	2375,	---
12888	/* AVE_S_W */	---	12888	/* AVE_S_W */	---
12889	2378,	---	12889	2378,	---
12890	/* AVE_U_B */	---	12890	/* AVE_U_B */	---
12891	2381,	---	12891	2381,	---
12892	/* AVE_U_D */	---	12892	/* AVE_U_D */	---
12893	2384,	---	12893	2384,	---
12894	/* AVE_U_H */	---	12894	/* AVE_U_H */	---
12895	2387,	---	12895	2387,	---
12896	/* AVE_U_W */	---	12896	/* AVE_U_W */	---
12897	2390,	---	12897	2390,	---
12898	/* AddiuRxImmX16 */	---	12898	/* AddiuRxImmX16 */	---
12899	2393,	---	12899	2393,	---
12900	/* AddiuRxPcImmX16 */	---	12900	/* AddiuRxPcImmX16 */	---
12901	2395,	---	12901	2395,	---
12902	/* AddiuRxRxImm16 */	---	12902	/* AddiuRxRxImm16 */	---
12903	2397,	---	12903	2397,	---
12904	/* AddiuRxRxImmX16 */	---	12904	/* AddiuRxRxImmX16 */	---
12905	2400,	---	12905	2400,	---
12906	/* AddiuRxRyOffMemX16 */	---	12906	/* AddiuRxRyOffMemX16 */	---
12907	2403,	---	12907	2403,	---
12908	/* AddiuSpImm16 */	---	12908	/* AddiuSpImm16 */	---
12909	2406,	---	12909	2406,	---
12910	/* AddiuSpImmX16 */	---	12910	/* AddiuSpImmX16 */	---
12911	2407,	---	12911	2407,	---
12912	/* AdduRxRyRz16 */	---	12912	/* AdduRxRyRz16 */	---
12913	2408,	---	12913	2408,	---
12914	/* AndRxRxRy16 */	---	12914	/* AndRxRxRy16 */	---
12915	2411,	---	12915	2411,	---
12916	/* B16_MM */	---	12916	/* B16_MM */	---
12917	2414,	---	12917	2414,	---
12918	/* BADDu */	---	12918	/* BADDu */	---
12919	2415,	---	12919	2415,	---
12920	/* BAL */	---	12920	/* BAL */	---
12921	2418,	---	12921	2418,	---
12922	/* BALC */	---	12922	/* BALC */	---
12923	2419,	---	12923	2419,	---
12924	/* BALC_MMR6 */	---	12924	/* BALC_MMR6 */	---
12925	2420,	---	12925	2420,	---
12926	/* BALIGN */	---	12926	/* BALIGN */	---
12927	2421,	---	12927	2421,	---
12928	/* BALIGN_MMR2 */	---	12928	/* BALIGN_MMR2 */	---
12929	2425,	---	12929	2425,	---
12930	/* BBIT0 */	---	12930	/* BBIT0 */	---
12931	2429,	---	12931	2429,	---
12932	/* BBIT032 */	---	12932	/* BBIT032 */	---
12933	2432,	---	12933	2432,	---
12934	/* BBIT1 */	---	12934	/* BBIT1 */	---
12935	2435,	---	12935	2435,	---
12936	/* BBIT132 */	---	12936	/* BBIT132 */	---
12937	2438,	---	12937	2438,	---
12938	/* BC */	---	12938	/* BC */	---
12939	2441,	---	12939	2441,	---
12940	/* BC16_MMR6 */	---	12940	/* BC16_MMR6 */	---
12941	2442,	---	12941	2442,	---
12942	/* BC1EQZ */	---	12942	/* BC1EQZ */	---
12943	2443,	---	12943	2443,	---
12944	/* BC1EQZC_MMR6 */	---	12944	/* BC1EQZC_MMR6 */	---
12945	2445,	---	12945	2445,	---
12946	/* BC1F */	---	12946	/* BC1F */	---
12947	2447,	---	12947	2447,	---
12948	/* BC1FL */	---	12948	/* BC1FL */	---
12949	2449,	---	12949	2449,	---
12950	/* BC1F_MM */	---	12950	/* BC1F_MM */	---
12951	2451,	---	12951	2451,	---
12952	/* BC1NEZ */	---	12952	/* BC1NEZ */	---
12953	2453,	---	12953	2453,	---
12954	/* BC1NEZC_MMR6 */	---	12954	/* BC1NEZC_MMR6 */	---
12955	2455,	---	12955	2455,	---
12956	/* BC1T */	---	12956	/* BC1T */	---
12957	2457,	---	12957	2457,	---
12958	/* BC1TL */	---	12958	/* BC1TL */	---
12959	2459,	---	12959	2459,	---
12960	/* BC1T_MM */	---	12960	/* BC1T_MM */	---
12961	2461,	---	12961	2461,	---
12962	/* BC2EQZ */	---	12962	/* BC2EQZ */	---
12963	2463,	---	12963	2463,	---
12964	/* BC2EQZC_MMR6 */	---	12964	/* BC2EQZC_MMR6 */	---
12965	2465,	---	12965	2465,	---
12966	/* BC2NEZ */	---	12966	/* BC2NEZ */	---
12967	2467,	---	12967	2467,	---
12968	/* BC2NEZC_MMR6 */	---	12968	/* BC2NEZC_MMR6 */	---
12969	2469,	---	12969	2469,	---
12970	/* BCLRI_B */	---	12970	/* BCLRI_B */	---
12971	2471,	---	12971	2471,	---
12972	/* BCLRI_D */	---	12972	/* BCLRI_D */	---
12973	2474,	---	12973	2474,	---
12974	/* BCLRI_H */	---	12974	/* BCLRI_H */	---
12975	2477,	---	12975	2477,	---
12976	/* BCLRI_W */	---	12976	/* BCLRI_W */	---
12977	2480,	---	12977	2480,	---
12978	/* BCLR_B */	---	12978	/* BCLR_B */	---
12979	2483,	---	12979	2483,	---
12980	/* BCLR_D */	---	12980	/* BCLR_D */	---
12981	2486,	---	12981	2486,	---
12982	/* BCLR_H */	---	12982	/* BCLR_H */	---
12983	2489,	---	12983	2489,	---
12984	/* BCLR_W */	---	12984	/* BCLR_W */	---
12985	2492,	---	12985	2492,	---
12986	/* BC_MMR6 */	---	12986	/* BC_MMR6 */	---
12987	2495,	---	12987	2495,	---
12988	/* BEQ */	---	12988	/* BEQ */	---
12989	2496,	---	12989	2496,	---
12990	/* BEQ64 */	---	12990	/* BEQ64 */	---
12991	2499,	---	12991	2499,	---
12992	/* BEQC */	---	12992	/* BEQC */	---
12993	2502,	---	12993	2502,	---
12994	/* BEQC64 */	---	12994	/* BEQC64 */	---
12995	2505,	---	12995	2505,	---
12996	/* BEQC_MMR6 */	---	12996	/* BEQC_MMR6 */	---
12997	2508,	---	12997	2508,	---
12998	/* BEQL */	---	12998	/* BEQL */	---
12999	2511,	---	12999	2511,	---
13000	/* BEQZ16_MM */	---	13000	/* BEQZ16_MM */	---
13001	2514,	---	13001	2514,	---
13002	/* BEQZALC */	---	13002	/* BEQZALC */	---
13003	2516,	---	13003	2516,	---
13004	/* BEQZALC_MMR6 */	---	13004	/* BEQZALC_MMR6 */	---
13005	2518,	---	13005	2518,	---
13006	/* BEQZC */	---	13006	/* BEQZC */	---
13007	2520,	---	13007	2520,	---
13008	/* BEQZC16_MMR6 */	---	13008	/* BEQZC16_MMR6 */	---
13009	2522,	---	13009	2522,	---
13010	/* BEQZC64 */	---	13010	/* BEQZC64 */	---
13011	2524,	---	13011	2524,	---
13012	/* BEQZC_MM */	---	13012	/* BEQZC_MM */	---
13013	2526,	---	13013	2526,	---
13014	/* BEQZC_MMR6 */	---	13014	/* BEQZC_MMR6 */	---
13015	2528,	---	13015	2528,	---
13016	/* BEQ_MM */	---	13016	/* BEQ_MM */	---
13017	2530,	---	13017	2530,	---
13018	/* BGEC */	---	13018	/* BGEC */	---
13019	2533,	---	13019	2533,	---
13020	/* BGEC64 */	---	13020	/* BGEC64 */	---
13021	2536,	---	13021	2536,	---
13022	/* BGEC_MMR6 */	---	13022	/* BGEC_MMR6 */	---
13023	2539,	---	13023	2539,	---
13024	/* BGEUC */	---	13024	/* BGEUC */	---
13025	2542,	---	13025	2542,	---
13026	/* BGEUC64 */	---	13026	/* BGEUC64 */	---
13027	2545,	---	13027	2545,	---
13028	/* BGEUC_MMR6 */	---	13028	/* BGEUC_MMR6 */	---
13029	2548,	---	13029	2548,	---
13030	/* BGEZ */	---	13030	/* BGEZ */	---
13031	2551,	---	13031	2551,	---
13032	/* BGEZ64 */	---	13032	/* BGEZ64 */	---
13033	2553,	---	13033	2553,	---
13034	/* BGEZAL */	---	13034	/* BGEZAL */	---
13035	2555,	---	13035	2555,	---
13036	/* BGEZALC */	---	13036	/* BGEZALC */	---
13037	2557,	---	13037	2557,	---
13038	/* BGEZALC_MMR6 */	---	13038	/* BGEZALC_MMR6 */	---
13039	2559,	---	13039	2559,	---
13040	/* BGEZALL */	---	13040	/* BGEZALL */	---
13041	2561,	---	13041	2561,	---
13042	/* BGEZALS_MM */	---	13042	/* BGEZALS_MM */	---
13043	2563,	---	13043	2563,	---
13044	/* BGEZAL_MM */	---	13044	/* BGEZAL_MM */	---
13045	2565,	---	13045	2565,	---
13046	/* BGEZC */	---	13046	/* BGEZC */	---
13047	2567,	---	13047	2567,	---
13048	/* BGEZC64 */	---	13048	/* BGEZC64 */	---
13049	2569,	---	13049	2569,	---
13050	/* BGEZC_MMR6 */	---	13050	/* BGEZC_MMR6 */	---
13051	2571,	---	13051	2571,	---
13052	/* BGEZL */	---	13052	/* BGEZL */	---
13053	2573,	---	13053	2573,	---
13054	/* BGEZ_MM */	---	13054	/* BGEZ_MM */	---
13055	2575,	---	13055	2575,	---
13056	/* BGTZ */	---	13056	/* BGTZ */	---
13057	2577,	---	13057	2577,	---
13058	/* BGTZ64 */	---	13058	/* BGTZ64 */	---
13059	2579,	---	13059	2579,	---
13060	/* BGTZALC */	---	13060	/* BGTZALC */	---
13061	2581,	---	13061	2581,	---
13062	/* BGTZALC_MMR6 */	---	13062	/* BGTZALC_MMR6 */	---
13063	2583,	---	13063	2583,	---
13064	/* BGTZC */	---	13064	/* BGTZC */	---
13065	2585,	---	13065	2585,	---
13066	/* BGTZC64 */	---	13066	/* BGTZC64 */	---
13067	2587,	---	13067	2587,	---
13068	/* BGTZC_MMR6 */	---	13068	/* BGTZC_MMR6 */	---
13069	2589,	---	13069	2589,	---
13070	/* BGTZL */	---	13070	/* BGTZL */	---
13071	2591,	---	13071	2591,	---
13072	/* BGTZ_MM */	---	13072	/* BGTZ_MM */	---
13073	2593,	---	13073	2593,	---
13074	/* BINSLI_B */	---	13074	/* BINSLI_B */	---
13075	2595,	---	13075	2595,	---
13076	/* BINSLI_D */	---	13076	/* BINSLI_D */	---
13077	2599,	---	13077	2599,	---
13078	/* BINSLI_H */	---	13078	/* BINSLI_H */	---
13079	2603,	---	13079	2603,	---
13080	/* BINSLI_W */	---	13080	/* BINSLI_W */	---
13081	2607,	---	13081	2607,	---
13082	/* BINSL_B */	---	13082	/* BINSL_B */	---
13083	2611,	---	13083	2611,	---
13084	/* BINSL_D */	---	13084	/* BINSL_D */	---
13085	2615,	---	13085	2615,	---
13086	/* BINSL_H */	---	13086	/* BINSL_H */	---
13087	2619,	---	13087	2619,	---
13088	/* BINSL_W */	---	13088	/* BINSL_W */	---
13089	2623,	---	13089	2623,	---
13090	/* BINSRI_B */	---	13090	/* BINSRI_B */	---
13091	2627,	---	13091	2627,	---
13092	/* BINSRI_D */	---	13092	/* BINSRI_D */	---
13093	2631,	---	13093	2631,	---
13094	/* BINSRI_H */	---	13094	/* BINSRI_H */	---
13095	2635,	---	13095	2635,	---
13096	/* BINSRI_W */	---	13096	/* BINSRI_W */	---
13097	2639,	---	13097	2639,	---
13098	/* BINSR_B */	---	13098	/* BINSR_B */	---
13099	2643,	---	13099	2643,	---
13100	/* BINSR_D */	---	13100	/* BINSR_D */	---
13101	2647,	---	13101	2647,	---
13102	/* BINSR_H */	---	13102	/* BINSR_H */	---
13103	2651,	---	13103	2651,	---
13104	/* BINSR_W */	---	13104	/* BINSR_W */	---
13105	2655,	---	13105	2655,	---
13106	/* BITREV */	---	13106	/* BITREV */	---
13107	2659,	---	13107	2659,	---
13108	/* BITREV_MM */	---	13108	/* BITREV_MM */	---
13109	2661,	---	13109	2661,	---
13110	/* BITSWAP */	---	13110	/* BITSWAP */	---
13111	2663,	---	13111	2663,	---
13112	/* BITSWAP_MMR6 */	---	13112	/* BITSWAP_MMR6 */	---
13113	2665,	---	13113	2665,	---
13114	/* BLEZ */	---	13114	/* BLEZ */	---
13115	2667,	---	13115	2667,	---
13116	/* BLEZ64 */	---	13116	/* BLEZ64 */	---
13117	2669,	---	13117	2669,	---
13118	/* BLEZALC */	---	13118	/* BLEZALC */	---
13119	2671,	---	13119	2671,	---
13120	/* BLEZALC_MMR6 */	---	13120	/* BLEZALC_MMR6 */	---
13121	2673,	---	13121	2673,	---
13122	/* BLEZC */	---	13122	/* BLEZC */	---
13123	2675,	---	13123	2675,	---
13124	/* BLEZC64 */	---	13124	/* BLEZC64 */	---
13125	2677,	---	13125	2677,	---
13126	/* BLEZC_MMR6 */	---	13126	/* BLEZC_MMR6 */	---
13127	2679,	---	13127	2679,	---
13128	/* BLEZL */	---	13128	/* BLEZL */	---
13129	2681,	---	13129	2681,	---
13130	/* BLEZ_MM */	---	13130	/* BLEZ_MM */	---
13131	2683,	---	13131	2683,	---
13132	/* BLTC */	---	13132	/* BLTC */	---
13133	2685,	---	13133	2685,	---
13134	/* BLTC64 */	---	13134	/* BLTC64 */	---
13135	2688,	---	13135	2688,	---
13136	/* BLTC_MMR6 */	---	13136	/* BLTC_MMR6 */	---
13137	2691,	---	13137	2691,	---
13138	/* BLTUC */	---	13138	/* BLTUC */	---
13139	2694,	---	13139	2694,	---
13140	/* BLTUC64 */	---	13140	/* BLTUC64 */	---
13141	2697,	---	13141	2697,	---
13142	/* BLTUC_MMR6 */	---	13142	/* BLTUC_MMR6 */	---
13143	2700,	---	13143	2700,	---
13144	/* BLTZ */	---	13144	/* BLTZ */	---
13145	2703,	---	13145	2703,	---
13146	/* BLTZ64 */	---	13146	/* BLTZ64 */	---
13147	2705,	---	13147	2705,	---
13148	/* BLTZAL */	---	13148	/* BLTZAL */	---
13149	2707,	---	13149	2707,	---
13150	/* BLTZALC */	---	13150	/* BLTZALC */	---
13151	2709,	---	13151	2709,	---
13152	/* BLTZALC_MMR6 */	---	13152	/* BLTZALC_MMR6 */	---
13153	2711,	---	13153	2711,	---
13154	/* BLTZALL */	---	13154	/* BLTZALL */	---
13155	2713,	---	13155	2713,	---
13156	/* BLTZALS_MM */	---	13156	/* BLTZALS_MM */	---
13157	2715,	---	13157	2715,	---
13158	/* BLTZAL_MM */	---	13158	/* BLTZAL_MM */	---
13159	2717,	---	13159	2717,	---
13160	/* BLTZC */	---	13160	/* BLTZC */	---
13161	2719,	---	13161	2719,	---
13162	/* BLTZC64 */	---	13162	/* BLTZC64 */	---
13163	2721,	---	13163	2721,	---
13164	/* BLTZC_MMR6 */	---	13164	/* BLTZC_MMR6 */	---
13165	2723,	---	13165	2723,	---
13166	/* BLTZL */	---	13166	/* BLTZL */	---
13167	2725,	---	13167	2725,	---
13168	/* BLTZ_MM */	---	13168	/* BLTZ_MM */	---
13169	2727,	---	13169	2727,	---
13170	/* BMNZI_B */	---	13170	/* BMNZI_B */	---
13171	2729,	---	13171	2729,	---
13172	/* BMNZ_V */	---	13172	/* BMNZ_V */	---
13173	2733,	---	13173	2733,	---
13174	/* BMZI_B */	---	13174	/* BMZI_B */	---
13175	2737,	---	13175	2737,	---
13176	/* BMZ_V */	---	13176	/* BMZ_V */	---
13177	2741,	---	13177	2741,	---
13178	/* BNE */	---	13178	/* BNE */	---
13179	2745,	---	13179	2745,	---
13180	/* BNE64 */	---	13180	/* BNE64 */	---
13181	2748,	---	13181	2748,	---
13182	/* BNEC */	---	13182	/* BNEC */	---
13183	2751,	---	13183	2751,	---
13184	/* BNEC64 */	---	13184	/* BNEC64 */	---
13185	2754,	---	13185	2754,	---
13186	/* BNEC_MMR6 */	---	13186	/* BNEC_MMR6 */	---
13187	2757,	---	13187	2757,	---
13188	/* BNEGI_B */	---	13188	/* BNEGI_B */	---
13189	2760,	---	13189	2760,	---
13190	/* BNEGI_D */	---	13190	/* BNEGI_D */	---
13191	2763,	---	13191	2763,	---
13192	/* BNEGI_H */	---	13192	/* BNEGI_H */	---
13193	2766,	---	13193	2766,	---
13194	/* BNEGI_W */	---	13194	/* BNEGI_W */	---
13195	2769,	---	13195	2769,	---
13196	/* BNEG_B */	---	13196	/* BNEG_B */	---
13197	2772,	---	13197	2772,	---
13198	/* BNEG_D */	---	13198	/* BNEG_D */	---
13199	2775,	---	13199	2775,	---
13200	/* BNEG_H */	---	13200	/* BNEG_H */	---
13201	2778,	---	13201	2778,	---
13202	/* BNEG_W */	---	13202	/* BNEG_W */	---
13203	2781,	---	13203	2781,	---
13204	/* BNEL */	---	13204	/* BNEL */	---
13205	2784,	---	13205	2784,	---
13206	/* BNEZ16_MM */	---	13206	/* BNEZ16_MM */	---
13207	2787,	---	13207	2787,	---
13208	/* BNEZALC */	---	13208	/* BNEZALC */	---
13209	2789,	---	13209	2789,	---
13210	/* BNEZALC_MMR6 */	---	13210	/* BNEZALC_MMR6 */	---
13211	2791,	---	13211	2791,	---
13212	/* BNEZC */	---	13212	/* BNEZC */	---
13213	2793,	---	13213	2793,	---
13214	/* BNEZC16_MMR6 */	---	13214	/* BNEZC16_MMR6 */	---
13215	2795,	---	13215	2795,	---
13216	/* BNEZC64 */	---	13216	/* BNEZC64 */	---
13217	2797,	---	13217	2797,	---
13218	/* BNEZC_MM */	---	13218	/* BNEZC_MM */	---
13219	2799,	---	13219	2799,	---
13220	/* BNEZC_MMR6 */	---	13220	/* BNEZC_MMR6 */	---
13221	2801,	---	13221	2801,	---
13222	/* BNE_MM */	---	13222	/* BNE_MM */	---
13223	2803,	---	13223	2803,	---
13224	/* BNVC */	---	13224	/* BNVC */	---
13225	2806,	---	13225	2806,	---
13226	/* BNVC_MMR6 */	---	13226	/* BNVC_MMR6 */	---
13227	2809,	---	13227	2809,	---
13228	/* BNZ_B */	---	13228	/* BNZ_B */	---
13229	2812,	---	13229	2812,	---
13230	/* BNZ_D */	---	13230	/* BNZ_D */	---
13231	2814,	---	13231	2814,	---
13232	/* BNZ_H */	---	13232	/* BNZ_H */	---
13233	2816,	---	13233	2816,	---
13234	/* BNZ_V */	---	13234	/* BNZ_V */	---
13235	2818,	---	13235	2818,	---
13236	/* BNZ_W */	---	13236	/* BNZ_W */	---
13237	2820,	---	13237	2820,	---
13238	/* BOVC */	---	13238	/* BOVC */	---
13239	2822,	---	13239	2822,	---
13240	/* BOVC_MMR6 */	---	13240	/* BOVC_MMR6 */	---
13241	2825,	---	13241	2825,	---
13242	/* BPOSGE32 */	---	13242	/* BPOSGE32 */	---
13243	2828,	---	13243	2828,	---
13244	/* BPOSGE32C_MMR3 */	---	13244	/* BPOSGE32C_MMR3 */	---
13245	2829,	---	13245	2829,	---
13246	/* BPOSGE32_MM */	---	13246	/* BPOSGE32_MM */	---
13247	2830,	---	13247	2830,	---
13248	/* BREAK */	---	13248	/* BREAK */	---
13249	2831,	---	13249	2831,	---
13250	/* BREAK16_MM */	---	13250	/* BREAK16_MM */	---
13251	2833,	---	13251	2833,	---
13252	/* BREAK16_MMR6 */	---	13252	/* BREAK16_MMR6 */	---
13253	2834,	---	13253	2834,	---
13254	/* BREAK_MM */	---	13254	/* BREAK_MM */	---
13255	2835,	---	13255	2835,	---
13256	/* BREAK_MMR6 */	---	13256	/* BREAK_MMR6 */	---
13257	2837,	---	13257	2837,	---
13258	/* BSELI_B */	---	13258	/* BSELI_B */	---
13259	2839,	---	13259	2839,	---
13260	/* BSEL_V */	---	13260	/* BSEL_V */	---
13261	2843,	---	13261	2843,	---
13262	/* BSETI_B */	---	13262	/* BSETI_B */	---
13263	2847,	---	13263	2847,	---
13264	/* BSETI_D */	---	13264	/* BSETI_D */	---
13265	2850,	---	13265	2850,	---
13266	/* BSETI_H */	---	13266	/* BSETI_H */	---
13267	2853,	---	13267	2853,	---
13268	/* BSETI_W */	---	13268	/* BSETI_W */	---
13269	2856,	---	13269	2856,	---
13270	/* BSET_B */	---	13270	/* BSET_B */	---
13271	2859,	---	13271	2859,	---
13272	/* BSET_D */	---	13272	/* BSET_D */	---
13273	2862,	---	13273	2862,	---
13274	/* BSET_H */	---	13274	/* BSET_H */	---
13275	2865,	---	13275	2865,	---
13276	/* BSET_W */	---	13276	/* BSET_W */	---
13277	2868,	---	13277	2868,	---
13278	/* BZ_B */	---	13278	/* BZ_B */	---
13279	2871,	---	13279	2871,	---
13280	/* BZ_D */	---	13280	/* BZ_D */	---
13281	2873,	---	13281	2873,	---
13282	/* BZ_H */	---	13282	/* BZ_H */	---
13283	2875,	---	13283	2875,	---
13284	/* BZ_V */	---	13284	/* BZ_V */	---
13285	2877,	---	13285	2877,	---
13286	/* BZ_W */	---	13286	/* BZ_W */	---
13287	2879,	---	13287	2879,	---
13288	/* BeqzRxImm16 */	---	13288	/* BeqzRxImm16 */	---
13289	2881,	---	13289	2881,	---
13290	/* BeqzRxImmX16 */	---	13290	/* BeqzRxImmX16 */	---
13291	2883,	---	13291	2883,	---
13292	/* Bimm16 */	---	13292	/* Bimm16 */	---
13293	2885,	---	13293	2885,	---
13294	/* BimmX16 */	---	13294	/* BimmX16 */	---
13295	2886,	---	13295	2886,	---
13296	/* BnezRxImm16 */	---	13296	/* BnezRxImm16 */	---
13297	2887,	---	13297	2887,	---
13298	/* BnezRxImmX16 */	---	13298	/* BnezRxImmX16 */	---
13299	2889,	---	13299	2889,	---
13300	/* Break16 */	---	13300	/* Break16 */	---
13301	2891,	---	13301	2891,	---
13302	/* Bteqz16 */	---	13302	/* Bteqz16 */	---
13303	2891,	---	13303	2891,	---
13304	/* BteqzX16 */	---	13304	/* BteqzX16 */	---
13305	2892,	---	13305	2892,	---
13306	/* Btnez16 */	---	13306	/* Btnez16 */	---
13307	2893,	---	13307	2893,	---
13308	/* BtnezX16 */	---	13308	/* BtnezX16 */	---
13309	2894,	---	13309	2894,	---
13310	/* CACHE */	---	13310	/* CACHE */	---
13311	2895,	---	13311	2895,	---
13312	/* CACHEE */	---	13312	/* CACHEE */	---
13313	2898,	---	13313	2898,	---
13314	/* CACHEE_MM */	---	13314	/* CACHEE_MM */	---
13315	2901,	---	13315	2901,	---
13316	/* CACHE_MM */	---	13316	/* CACHE_MM */	---
13317	2904,	---	13317	2904,	---
13318	/* CACHE_MMR6 */	---	13318	/* CACHE_MMR6 */	---
13319	2907,	---	13319	2907,	---
13320	/* CACHE_R6 */	---	13320	/* CACHE_R6 */	---
13321	2910,	---	13321	2910,	---
13322	/* CEIL_L_D64 */	---	13322	/* CEIL_L_D64 */	---
13323	2913,	---	13323	2913,	---
13324	/* CEIL_L_D_MMR6 */	---	13324	/* CEIL_L_D_MMR6 */	---
13325	2915,	---	13325	2915,	---
13326	/* CEIL_L_S */	---	13326	/* CEIL_L_S */	---
13327	2917,	---	13327	2917,	---
13328	/* CEIL_L_S_MMR6 */	---	13328	/* CEIL_L_S_MMR6 */	---
13329	2919,	---	13329	2919,	---
13330	/* CEIL_W_D32 */	---	13330	/* CEIL_W_D32 */	---
13331	2921,	---	13331	2921,	---
13332	/* CEIL_W_D64 */	---	13332	/* CEIL_W_D64 */	---
13333	2923,	---	13333	2923,	---
13334	/* CEIL_W_D_MMR6 */	---	13334	/* CEIL_W_D_MMR6 */	---
13335	2925,	---	13335	2925,	---
13336	/* CEIL_W_MM */	---	13336	/* CEIL_W_MM */	---
13337	2927,	---	13337	2927,	---
13338	/* CEIL_W_S */	---	13338	/* CEIL_W_S */	---
13339	2929,	---	13339	2929,	---
13340	/* CEIL_W_S_MM */	---	13340	/* CEIL_W_S_MM */	---
13341	2931,	---	13341	2931,	---
13342	/* CEIL_W_S_MMR6 */	---	13342	/* CEIL_W_S_MMR6 */	---
13343	2933,	---	13343	2933,	---
13344	/* CEQI_B */	---	13344	/* CEQI_B */	---
13345	2935,	---	13345	2935,	---
13346	/* CEQI_D */	---	13346	/* CEQI_D */	---
13347	2938,	---	13347	2938,	---
13348	/* CEQI_H */	---	13348	/* CEQI_H */	---
13349	2941,	---	13349	2941,	---
13350	/* CEQI_W */	---	13350	/* CEQI_W */	---
13351	2944,	---	13351	2944,	---
13352	/* CEQ_B */	---	13352	/* CEQ_B */	---
13353	2947,	---	13353	2947,	---
13354	/* CEQ_D */	---	13354	/* CEQ_D */	---
13355	2950,	---	13355	2950,	---
13356	/* CEQ_H */	---	13356	/* CEQ_H */	---
13357	2953,	---	13357	2953,	---
13358	/* CEQ_W */	---	13358	/* CEQ_W */	---
13359	2956,	---	13359	2956,	---
13360	/* CFC1 */	---	13360	/* CFC1 */	---
13361	2959,	---	13361	2959,	---
13362	/* CFC1_MM */	---	13362	/* CFC1_MM */	---
13363	2961,	---	13363	2961,	---
13364	/* CFC2_MM */	---	13364	/* CFC2_MM */	---
13365	2963,	---	13365	2963,	---
13366	/* CFCMSA */	---	13366	/* CFCMSA */	---
13367	2965,	---	13367	2965,	---
13368	/* CINS */	---	13368	/* CINS */	---
13369	2967,	---	13369	2967,	---
13370	/* CINS32 */	---	13370	/* CINS32 */	---
13371	2971,	---	13371	2971,	---
13372	/* CINS64_32 */	---	13372	/* CINS64_32 */	---
13373	2975,	---	13373	2975,	---
13374	/* CINS_i32 */	---	13374	/* CINS_i32 */	---
13375	2979,	---	13375	2979,	---
13376	/* CLASS_D */	---	13376	/* CLASS_D */	---
13377	2983,	---	13377	2983,	---
13378	/* CLASS_D_MMR6 */	---	13378	/* CLASS_D_MMR6 */	---
13379	2985,	---	13379	2985,	---
13380	/* CLASS_S */	---	13380	/* CLASS_S */	---
13381	2987,	---	13381	2987,	---
13382	/* CLASS_S_MMR6 */	---	13382	/* CLASS_S_MMR6 */	---
13383	2989,	---	13383	2989,	---
13384	/* CLEI_S_B */	---	13384	/* CLEI_S_B */	---
13385	2991,	---	13385	2991,	---
13386	/* CLEI_S_D */	---	13386	/* CLEI_S_D */	---
13387	2994,	---	13387	2994,	---
13388	/* CLEI_S_H */	---	13388	/* CLEI_S_H */	---
13389	2997,	---	13389	2997,	---
13390	/* CLEI_S_W */	---	13390	/* CLEI_S_W */	---
13391	3000,	---	13391	3000,	---
13392	/* CLEI_U_B */	---	13392	/* CLEI_U_B */	---
13393	3003,	---	13393	3003,	---
13394	/* CLEI_U_D */	---	13394	/* CLEI_U_D */	---
13395	3006,	---	13395	3006,	---
13396	/* CLEI_U_H */	---	13396	/* CLEI_U_H */	---
13397	3009,	---	13397	3009,	---
13398	/* CLEI_U_W */	---	13398	/* CLEI_U_W */	---
13399	3012,	---	13399	3012,	---
13400	/* CLE_S_B */	---	13400	/* CLE_S_B */	---
13401	3015,	---	13401	3015,	---
13402	/* CLE_S_D */	---	13402	/* CLE_S_D */	---
13403	3018,	---	13403	3018,	---
13404	/* CLE_S_H */	---	13404	/* CLE_S_H */	---
13405	3021,	---	13405	3021,	---
13406	/* CLE_S_W */	---	13406	/* CLE_S_W */	---
13407	3024,	---	13407	3024,	---
13408	/* CLE_U_B */	---	13408	/* CLE_U_B */	---
13409	3027,	---	13409	3027,	---
13410	/* CLE_U_D */	---	13410	/* CLE_U_D */	---
13411	3030,	---	13411	3030,	---
13412	/* CLE_U_H */	---	13412	/* CLE_U_H */	---
13413	3033,	---	13413	3033,	---
13414	/* CLE_U_W */	---	13414	/* CLE_U_W */	---
13415	3036,	---	13415	3036,	---
13416	/* CLO */	---	13416	/* CLO */	---
13417	3039,	---	13417	3039,	---
13418	/* CLO_MM */	---	13418	/* CLO_MM */	---
13419	3041,	---	13419	3041,	---
13420	/* CLO_MMR6 */	---	13420	/* CLO_MMR6 */	---
13421	3043,	---	13421	3043,	---
13422	/* CLO_R6 */	---	13422	/* CLO_R6 */	---
13423	3045,	---	13423	3045,	---
13424	/* CLTI_S_B */	---	13424	/* CLTI_S_B */	---
13425	3047,	---	13425	3047,	---
13426	/* CLTI_S_D */	---	13426	/* CLTI_S_D */	---
13427	3050,	---	13427	3050,	---
13428	/* CLTI_S_H */	---	13428	/* CLTI_S_H */	---
13429	3053,	---	13429	3053,	---
13430	/* CLTI_S_W */	---	13430	/* CLTI_S_W */	---
13431	3056,	---	13431	3056,	---
13432	/* CLTI_U_B */	---	13432	/* CLTI_U_B */	---
13433	3059,	---	13433	3059,	---
13434	/* CLTI_U_D */	---	13434	/* CLTI_U_D */	---
13435	3062,	---	13435	3062,	---
13436	/* CLTI_U_H */	---	13436	/* CLTI_U_H */	---
13437	3065,	---	13437	3065,	---
13438	/* CLTI_U_W */	---	13438	/* CLTI_U_W */	---
13439	3068,	---	13439	3068,	---
13440	/* CLT_S_B */	---	13440	/* CLT_S_B */	---
13441	3071,	---	13441	3071,	---
13442	/* CLT_S_D */	---	13442	/* CLT_S_D */	---
13443	3074,	---	13443	3074,	---
13444	/* CLT_S_H */	---	13444	/* CLT_S_H */	---
13445	3077,	---	13445	3077,	---
13446	/* CLT_S_W */	---	13446	/* CLT_S_W */	---
13447	3080,	---	13447	3080,	---
13448	/* CLT_U_B */	---	13448	/* CLT_U_B */	---
13449	3083,	---	13449	3083,	---
13450	/* CLT_U_D */	---	13450	/* CLT_U_D */	---
13451	3086,	---	13451	3086,	---
13452	/* CLT_U_H */	---	13452	/* CLT_U_H */	---
13453	3089,	---	13453	3089,	---
13454	/* CLT_U_W */	---	13454	/* CLT_U_W */	---
13455	3092,	---	13455	3092,	---
13456	/* CLZ */	---	13456	/* CLZ */	---
13457	3095,	---	13457	3095,	---
13458	/* CLZ_MM */	---	13458	/* CLZ_MM */	---
13459	3097,	---	13459	3097,	---
13460	/* CLZ_MMR6 */	---	13460	/* CLZ_MMR6 */	---
13461	3099,	---	13461	3099,	---
13462	/* CLZ_R6 */	---	13462	/* CLZ_R6 */	---
13463	3101,	---	13463	3101,	---
13464	/* CMPGDU_EQ_QB */	---	13464	/* CMPGDU_EQ_QB */	---
13465	3103,	---	13465	3103,	---
13466	/* CMPGDU_EQ_QB_MMR2 */	---	13466	/* CMPGDU_EQ_QB_MMR2 */	---
13467	3106,	---	13467	3106,	---
13468	/* CMPGDU_LE_QB */	---	13468	/* CMPGDU_LE_QB */	---
13469	3109,	---	13469	3109,	---
13470	/* CMPGDU_LE_QB_MMR2 */	---	13470	/* CMPGDU_LE_QB_MMR2 */	---
13471	3112,	---	13471	3112,	---
13472	/* CMPGDU_LT_QB */	---	13472	/* CMPGDU_LT_QB */	---
13473	3115,	---	13473	3115,	---
13474	/* CMPGDU_LT_QB_MMR2 */	---	13474	/* CMPGDU_LT_QB_MMR2 */	---
13475	3118,	---	13475	3118,	---
13476	/* CMPGU_EQ_QB */	---	13476	/* CMPGU_EQ_QB */	---
13477	3121,	---	13477	3121,	---
13478	/* CMPGU_EQ_QB_MM */	---	13478	/* CMPGU_EQ_QB_MM */	---
13479	3124,	---	13479	3124,	---
13480	/* CMPGU_LE_QB */	---	13480	/* CMPGU_LE_QB */	---
13481	3127,	---	13481	3127,	---
13482	/* CMPGU_LE_QB_MM */	---	13482	/* CMPGU_LE_QB_MM */	---
13483	3130,	---	13483	3130,	---
13484	/* CMPGU_LT_QB */	---	13484	/* CMPGU_LT_QB */	---
13485	3133,	---	13485	3133,	---
13486	/* CMPGU_LT_QB_MM */	---	13486	/* CMPGU_LT_QB_MM */	---
13487	3136,	---	13487	3136,	---
13488	/* CMPU_EQ_QB */	---	13488	/* CMPU_EQ_QB */	---
13489	3139,	---	13489	3139,	---
13490	/* CMPU_EQ_QB_MM */	---	13490	/* CMPU_EQ_QB_MM */	---
13491	3141,	---	13491	3141,	---
13492	/* CMPU_LE_QB */	---	13492	/* CMPU_LE_QB */	---
13493	3143,	---	13493	3143,	---
13494	/* CMPU_LE_QB_MM */	---	13494	/* CMPU_LE_QB_MM */	---
13495	3145,	---	13495	3145,	---
13496	/* CMPU_LT_QB */	---	13496	/* CMPU_LT_QB */	---
13497	3147,	---	13497	3147,	---
13498	/* CMPU_LT_QB_MM */	---	13498	/* CMPU_LT_QB_MM */	---
13499	3149,	---	13499	3149,	---
13500	/* CMP_AF_D_MMR6 */	---	13500	/* CMP_AF_D_MMR6 */	---
13501	3151,	---	13501	3151,	---
13502	/* CMP_AF_S_MMR6 */	---	13502	/* CMP_AF_S_MMR6 */	---
13503	3154,	---	13503	3154,	---
13504	/* CMP_EQ_D */	---	13504	/* CMP_EQ_D */	---
13505	3157,	---	13505	3157,	---
13506	/* CMP_EQ_D_MMR6 */	---	13506	/* CMP_EQ_D_MMR6 */	---
13507	3160,	---	13507	3160,	---
13508	/* CMP_EQ_PH */	---	13508	/* CMP_EQ_PH */	---
13509	3163,	---	13509	3163,	---
13510	/* CMP_EQ_PH_MM */	---	13510	/* CMP_EQ_PH_MM */	---
13511	3165,	---	13511	3165,	---
13512	/* CMP_EQ_S */	---	13512	/* CMP_EQ_S */	---
13513	3167,	---	13513	3167,	---
13514	/* CMP_EQ_S_MMR6 */	---	13514	/* CMP_EQ_S_MMR6 */	---
13515	3170,	---	13515	3170,	---
13516	/* CMP_F_D */	---	13516	/* CMP_F_D */	---
13517	3173,	---	13517	3173,	---
13518	/* CMP_F_S */	---	13518	/* CMP_F_S */	---
13519	3176,	---	13519	3176,	---
13520	/* CMP_LE_D */	---	13520	/* CMP_LE_D */	---
13521	3179,	---	13521	3179,	---
13522	/* CMP_LE_D_MMR6 */	---	13522	/* CMP_LE_D_MMR6 */	---
13523	3182,	---	13523	3182,	---
13524	/* CMP_LE_PH */	---	13524	/* CMP_LE_PH */	---
13525	3185,	---	13525	3185,	---
13526	/* CMP_LE_PH_MM */	---	13526	/* CMP_LE_PH_MM */	---
13527	3187,	---	13527	3187,	---
13528	/* CMP_LE_S */	---	13528	/* CMP_LE_S */	---
13529	3189,	---	13529	3189,	---
13530	/* CMP_LE_S_MMR6 */	---	13530	/* CMP_LE_S_MMR6 */	---
13531	3192,	---	13531	3192,	---
13532	/* CMP_LT_D */	---	13532	/* CMP_LT_D */	---
13533	3195,	---	13533	3195,	---
13534	/* CMP_LT_D_MMR6 */	---	13534	/* CMP_LT_D_MMR6 */	---
13535	3198,	---	13535	3198,	---
13536	/* CMP_LT_PH */	---	13536	/* CMP_LT_PH */	---
13537	3201,	---	13537	3201,	---
13538	/* CMP_LT_PH_MM */	---	13538	/* CMP_LT_PH_MM */	---
13539	3203,	---	13539	3203,	---
13540	/* CMP_LT_S */	---	13540	/* CMP_LT_S */	---
13541	3205,	---	13541	3205,	---
13542	/* CMP_LT_S_MMR6 */	---	13542	/* CMP_LT_S_MMR6 */	---
13543	3208,	---	13543	3208,	---
13544	/* CMP_SAF_D */	---	13544	/* CMP_SAF_D */	---
13545	3211,	---	13545	3211,	---
13546	/* CMP_SAF_D_MMR6 */	---	13546	/* CMP_SAF_D_MMR6 */	---
13547	3214,	---	13547	3214,	---
13548	/* CMP_SAF_S */	---	13548	/* CMP_SAF_S */	---
13549	3217,	---	13549	3217,	---
13550	/* CMP_SAF_S_MMR6 */	---	13550	/* CMP_SAF_S_MMR6 */	---
13551	3220,	---	13551	3220,	---
13552	/* CMP_SEQ_D */	---	13552	/* CMP_SEQ_D */	---
13553	3223,	---	13553	3223,	---
13554	/* CMP_SEQ_D_MMR6 */	---	13554	/* CMP_SEQ_D_MMR6 */	---
13555	3226,	---	13555	3226,	---
13556	/* CMP_SEQ_S */	---	13556	/* CMP_SEQ_S */	---
13557	3229,	---	13557	3229,	---
13558	/* CMP_SEQ_S_MMR6 */	---	13558	/* CMP_SEQ_S_MMR6 */	---
13559	3232,	---	13559	3232,	---
13560	/* CMP_SLE_D */	---	13560	/* CMP_SLE_D */	---
13561	3235,	---	13561	3235,	---
13562	/* CMP_SLE_D_MMR6 */	---	13562	/* CMP_SLE_D_MMR6 */	---
13563	3238,	---	13563	3238,	---
13564	/* CMP_SLE_S */	---	13564	/* CMP_SLE_S */	---
13565	3241,	---	13565	3241,	---
13566	/* CMP_SLE_S_MMR6 */	---	13566	/* CMP_SLE_S_MMR6 */	---
13567	3244,	---	13567	3244,	---
13568	/* CMP_SLT_D */	---	13568	/* CMP_SLT_D */	---
13569	3247,	---	13569	3247,	---
13570	/* CMP_SLT_D_MMR6 */	---	13570	/* CMP_SLT_D_MMR6 */	---
13571	3250,	---	13571	3250,	---
13572	/* CMP_SLT_S */	---	13572	/* CMP_SLT_S */	---
13573	3253,	---	13573	3253,	---
13574	/* CMP_SLT_S_MMR6 */	---	13574	/* CMP_SLT_S_MMR6 */	---
13575	3256,	---	13575	3256,	---
13576	/* CMP_SUEQ_D */	---	13576	/* CMP_SUEQ_D */	---
13577	3259,	---	13577	3259,	---
13578	/* CMP_SUEQ_D_MMR6 */	---	13578	/* CMP_SUEQ_D_MMR6 */	---
13579	3262,	---	13579	3262,	---
13580	/* CMP_SUEQ_S */	---	13580	/* CMP_SUEQ_S */	---
13581	3265,	---	13581	3265,	---
13582	/* CMP_SUEQ_S_MMR6 */	---	13582	/* CMP_SUEQ_S_MMR6 */	---
13583	3268,	---	13583	3268,	---
13584	/* CMP_SULE_D */	---	13584	/* CMP_SULE_D */	---
13585	3271,	---	13585	3271,	---
13586	/* CMP_SULE_D_MMR6 */	---	13586	/* CMP_SULE_D_MMR6 */	---
13587	3274,	---	13587	3274,	---
13588	/* CMP_SULE_S */	---	13588	/* CMP_SULE_S */	---
13589	3277,	---	13589	3277,	---
13590	/* CMP_SULE_S_MMR6 */	---	13590	/* CMP_SULE_S_MMR6 */	---
13591	3280,	---	13591	3280,	---
13592	/* CMP_SULT_D */	---	13592	/* CMP_SULT_D */	---
13593	3283,	---	13593	3283,	---
13594	/* CMP_SULT_D_MMR6 */	---	13594	/* CMP_SULT_D_MMR6 */	---
13595	3286,	---	13595	3286,	---
13596	/* CMP_SULT_S */	---	13596	/* CMP_SULT_S */	---
13597	3289,	---	13597	3289,	---
13598	/* CMP_SULT_S_MMR6 */	---	13598	/* CMP_SULT_S_MMR6 */	---
13599	3292,	---	13599	3292,	---
13600	/* CMP_SUN_D */	---	13600	/* CMP_SUN_D */	---
13601	3295,	---	13601	3295,	---
13602	/* CMP_SUN_D_MMR6 */	---	13602	/* CMP_SUN_D_MMR6 */	---
13603	3298,	---	13603	3298,	---
13604	/* CMP_SUN_S */	---	13604	/* CMP_SUN_S */	---
13605	3301,	---	13605	3301,	---
13606	/* CMP_SUN_S_MMR6 */	---	13606	/* CMP_SUN_S_MMR6 */	---
13607	3304,	---	13607	3304,	---
13608	/* CMP_UEQ_D */	---	13608	/* CMP_UEQ_D */	---
13609	3307,	---	13609	3307,	---
13610	/* CMP_UEQ_D_MMR6 */	---	13610	/* CMP_UEQ_D_MMR6 */	---
13611	3310,	---	13611	3310,	---
13612	/* CMP_UEQ_S */	---	13612	/* CMP_UEQ_S */	---
13613	3313,	---	13613	3313,	---
13614	/* CMP_UEQ_S_MMR6 */	---	13614	/* CMP_UEQ_S_MMR6 */	---
13615	3316,	---	13615	3316,	---
13616	/* CMP_ULE_D */	---	13616	/* CMP_ULE_D */	---
13617	3319,	---	13617	3319,	---
13618	/* CMP_ULE_D_MMR6 */	---	13618	/* CMP_ULE_D_MMR6 */	---
13619	3322,	---	13619	3322,	---
13620	/* CMP_ULE_S */	---	13620	/* CMP_ULE_S */	---
13621	3325,	---	13621	3325,	---
13622	/* CMP_ULE_S_MMR6 */	---	13622	/* CMP_ULE_S_MMR6 */	---
13623	3328,	---	13623	3328,	---
13624	/* CMP_ULT_D */	---	13624	/* CMP_ULT_D */	---
13625	3331,	---	13625	3331,	---
13626	/* CMP_ULT_D_MMR6 */	---	13626	/* CMP_ULT_D_MMR6 */	---
13627	3334,	---	13627	3334,	---
13628	/* CMP_ULT_S */	---	13628	/* CMP_ULT_S */	---
13629	3337,	---	13629	3337,	---
13630	/* CMP_ULT_S_MMR6 */	---	13630	/* CMP_ULT_S_MMR6 */	---
13631	3340,	---	13631	3340,	---
13632	/* CMP_UN_D */	---	13632	/* CMP_UN_D */	---
13633	3343,	---	13633	3343,	---
13634	/* CMP_UN_D_MMR6 */	---	13634	/* CMP_UN_D_MMR6 */	---
13635	3346,	---	13635	3346,	---
13636	/* CMP_UN_S */	---	13636	/* CMP_UN_S */	---
13637	3349,	---	13637	3349,	---
13638	/* CMP_UN_S_MMR6 */	---	13638	/* CMP_UN_S_MMR6 */	---
13639	3352,	---	13639	3352,	---
13640	/* COPY_S_B */	---	13640	/* COPY_S_B */	---
13641	3355,	---	13641	3355,	---
13642	/* COPY_S_D */	---	13642	/* COPY_S_D */	---
13643	3358,	---	13643	3358,	---
13644	/* COPY_S_H */	---	13644	/* COPY_S_H */	---
13645	3361,	---	13645	3361,	---
13646	/* COPY_S_W */	---	13646	/* COPY_S_W */	---
13647	3364,	---	13647	3364,	---
13648	/* COPY_U_B */	---	13648	/* COPY_U_B */	---
13649	3367,	---	13649	3367,	---
13650	/* COPY_U_H */	---	13650	/* COPY_U_H */	---
13651	3370,	---	13651	3370,	---
13652	/* COPY_U_W */	---	13652	/* COPY_U_W */	---
13653	3373,	---	13653	3373,	---
13654	/* CRC32B */	---	13654	/* CRC32B */	---
13655	3376,	---	13655	3376,	---
13656	/* CRC32CB */	---	13656	/* CRC32CB */	---
13657	3379,	---	13657	3379,	---
13658	/* CRC32CD */	---	13658	/* CRC32CD */	---
13659	3382,	---	13659	3382,	---
13660	/* CRC32CH */	---	13660	/* CRC32CH */	---
13661	3385,	---	13661	3385,	---
13662	/* CRC32CW */	---	13662	/* CRC32CW */	---
13663	3388,	---	13663	3388,	---
13664	/* CRC32D */	---	13664	/* CRC32D */	---
13665	3391,	---	13665	3391,	---
13666	/* CRC32H */	---	13666	/* CRC32H */	---
13667	3394,	---	13667	3394,	---
13668	/* CRC32W */	---	13668	/* CRC32W */	---
13669	3397,	---	13669	3397,	---
13670	/* CTC1 */	---	13670	/* CTC1 */	---
13671	3400,	---	13671	3400,	---
13672	/* CTC1_MM */	---	13672	/* CTC1_MM */	---
13673	3402,	---	13673	3402,	---
13674	/* CTC2_MM */	---	13674	/* CTC2_MM */	---
13675	3404,	---	13675	3404,	---
13676	/* CTCMSA */	---	13676	/* CTCMSA */	---
13677	3406,	---	13677	3406,	---
13678	/* CVT_D32_S */	---	13678	/* CVT_D32_S */	---
13679	3408,	---	13679	3408,	---
13680	/* CVT_D32_S_MM */	---	13680	/* CVT_D32_S_MM */	---
13681	3410,	---	13681	3410,	---
13682	/* CVT_D32_W */	---	13682	/* CVT_D32_W */	---
13683	3412,	---	13683	3412,	---
13684	/* CVT_D32_W_MM */	---	13684	/* CVT_D32_W_MM */	---
13685	3414,	---	13685	3414,	---
13686	/* CVT_D64_L */	---	13686	/* CVT_D64_L */	---
13687	3416,	---	13687	3416,	---
13688	/* CVT_D64_S */	---	13688	/* CVT_D64_S */	---
13689	3418,	---	13689	3418,	---
13690	/* CVT_D64_S_MM */	---	13690	/* CVT_D64_S_MM */	---
13691	3420,	---	13691	3420,	---
13692	/* CVT_D64_W */	---	13692	/* CVT_D64_W */	---
13693	3422,	---	13693	3422,	---
13694	/* CVT_D64_W_MM */	---	13694	/* CVT_D64_W_MM */	---
13695	3424,	---	13695	3424,	---
13696	/* CVT_D_L_MMR6 */	---	13696	/* CVT_D_L_MMR6 */	---
13697	3426,	---	13697	3426,	---
13698	/* CVT_L_D64 */	---	13698	/* CVT_L_D64 */	---
13699	3428,	---	13699	3428,	---
13700	/* CVT_L_D64_MM */	---	13700	/* CVT_L_D64_MM */	---
13701	3430,	---	13701	3430,	---
13702	/* CVT_L_D_MMR6 */	---	13702	/* CVT_L_D_MMR6 */	---
13703	3432,	---	13703	3432,	---
13704	/* CVT_L_S */	---	13704	/* CVT_L_S */	---
13705	3434,	---	13705	3434,	---
13706	/* CVT_L_S_MM */	---	13706	/* CVT_L_S_MM */	---
13707	3436,	---	13707	3436,	---
13708	/* CVT_L_S_MMR6 */	---	13708	/* CVT_L_S_MMR6 */	---
13709	3438,	---	13709	3438,	---
13710	/* CVT_PS_PW64 */	---	13710	/* CVT_PS_PW64 */	---
13711	3440,	---	13711	3440,	---
13712	/* CVT_PS_S64 */	---	13712	/* CVT_PS_S64 */	---
13713	3442,	---	13713	3442,	---
13714	/* CVT_PW_PS64 */	---	13714	/* CVT_PW_PS64 */	---
13715	3445,	---	13715	3445,	---
13716	/* CVT_S_D32 */	---	13716	/* CVT_S_D32 */	---
13717	3447,	---	13717	3447,	---
13718	/* CVT_S_D32_MM */	---	13718	/* CVT_S_D32_MM */	---
13719	3449,	---	13719	3449,	---
13720	/* CVT_S_D64 */	---	13720	/* CVT_S_D64 */	---
13721	3451,	---	13721	3451,	---
13722	/* CVT_S_D64_MM */	---	13722	/* CVT_S_D64_MM */	---
13723	3453,	---	13723	3453,	---
13724	/* CVT_S_L */	---	13724	/* CVT_S_L */	---
13725	3455,	---	13725	3455,	---
13726	/* CVT_S_L_MMR6 */	---	13726	/* CVT_S_L_MMR6 */	---
13727	3457,	---	13727	3457,	---
13728	/* CVT_S_PL64 */	---	13728	/* CVT_S_PL64 */	---
13729	3459,	---	13729	3459,	---
13730	/* CVT_S_PU64 */	---	13730	/* CVT_S_PU64 */	---
13731	3461,	---	13731	3461,	---
13732	/* CVT_S_W */	---	13732	/* CVT_S_W */	---
13733	3463,	---	13733	3463,	---
13734	/* CVT_S_W_MM */	---	13734	/* CVT_S_W_MM */	---
13735	3465,	---	13735	3465,	---
13736	/* CVT_S_W_MMR6 */	---	13736	/* CVT_S_W_MMR6 */	---
13737	3467,	---	13737	3467,	---
13738	/* CVT_W_D32 */	---	13738	/* CVT_W_D32 */	---
13739	3469,	---	13739	3469,	---
13740	/* CVT_W_D32_MM */	---	13740	/* CVT_W_D32_MM */	---
13741	3471,	---	13741	3471,	---
13742	/* CVT_W_D64 */	---	13742	/* CVT_W_D64 */	---
13743	3473,	---	13743	3473,	---
13744	/* CVT_W_D64_MM */	---	13744	/* CVT_W_D64_MM */	---
13745	3475,	---	13745	3475,	---
13746	/* CVT_W_S */	---	13746	/* CVT_W_S */	---
13747	3477,	---	13747	3477,	---
13748	/* CVT_W_S_MM */	---	13748	/* CVT_W_S_MM */	---
13749	3479,	---	13749	3479,	---
13750	/* CVT_W_S_MMR6 */	---	13750	/* CVT_W_S_MMR6 */	---
13751	3481,	---	13751	3481,	---
13752	/* C_EQ_D32 */	---	13752	/* C_EQ_D32 */	---
13753	3483,	---	13753	3483,	---
13754	/* C_EQ_D32_MM */	---	13754	/* C_EQ_D32_MM */	---
13755	3486,	---	13755	3486,	---
13756	/* C_EQ_D64 */	---	13756	/* C_EQ_D64 */	---
13757	3489,	---	13757	3489,	---
13758	/* C_EQ_D64_MM */	---	13758	/* C_EQ_D64_MM */	---
13759	3492,	---	13759	3492,	---
13760	/* C_EQ_S */	---	13760	/* C_EQ_S */	---
13761	3495,	---	13761	3495,	---
13762	/* C_EQ_S_MM */	---	13762	/* C_EQ_S_MM */	---
13763	3498,	---	13763	3498,	---
13764	/* C_F_D32 */	---	13764	/* C_F_D32 */	---
13765	3501,	---	13765	3501,	---
13766	/* C_F_D32_MM */	---	13766	/* C_F_D32_MM */	---
13767	3504,	---	13767	3504,	---
13768	/* C_F_D64 */	---	13768	/* C_F_D64 */	---
13769	3507,	---	13769	3507,	---
13770	/* C_F_D64_MM */	---	13770	/* C_F_D64_MM */	---
13771	3510,	---	13771	3510,	---
13772	/* C_F_S */	---	13772	/* C_F_S */	---
13773	3513,	---	13773	3513,	---
13774	/* C_F_S_MM */	---	13774	/* C_F_S_MM */	---
13775	3516,	---	13775	3516,	---
13776	/* C_LE_D32 */	---	13776	/* C_LE_D32 */	---
13777	3519,	---	13777	3519,	---
13778	/* C_LE_D32_MM */	---	13778	/* C_LE_D32_MM */	---
13779	3522,	---	13779	3522,	---
13780	/* C_LE_D64 */	---	13780	/* C_LE_D64 */	---
13781	3525,	---	13781	3525,	---
13782	/* C_LE_D64_MM */	---	13782	/* C_LE_D64_MM */	---
13783	3528,	---	13783	3528,	---
13784	/* C_LE_S */	---	13784	/* C_LE_S */	---
13785	3531,	---	13785	3531,	---
13786	/* C_LE_S_MM */	---	13786	/* C_LE_S_MM */	---
13787	3534,	---	13787	3534,	---
13788	/* C_LT_D32 */	---	13788	/* C_LT_D32 */	---
13789	3537,	---	13789	3537,	---
13790	/* C_LT_D32_MM */	---	13790	/* C_LT_D32_MM */	---
13791	3540,	---	13791	3540,	---
13792	/* C_LT_D64 */	---	13792	/* C_LT_D64 */	---
13793	3543,	---	13793	3543,	---
13794	/* C_LT_D64_MM */	---	13794	/* C_LT_D64_MM */	---
13795	3546,	---	13795	3546,	---
13796	/* C_LT_S */	---	13796	/* C_LT_S */	---
13797	3549,	---	13797	3549,	---
13798	/* C_LT_S_MM */	---	13798	/* C_LT_S_MM */	---
13799	3552,	---	13799	3552,	---
13800	/* C_NGE_D32 */	---	13800	/* C_NGE_D32 */	---
13801	3555,	---	13801	3555,	---
13802	/* C_NGE_D32_MM */	---	13802	/* C_NGE_D32_MM */	---
13803	3558,	---	13803	3558,	---
13804	/* C_NGE_D64 */	---	13804	/* C_NGE_D64 */	---
13805	3561,	---	13805	3561,	---
13806	/* C_NGE_D64_MM */	---	13806	/* C_NGE_D64_MM */	---
13807	3564,	---	13807	3564,	---
13808	/* C_NGE_S */	---	13808	/* C_NGE_S */	---
13809	3567,	---	13809	3567,	---
13810	/* C_NGE_S_MM */	---	13810	/* C_NGE_S_MM */	---
13811	3570,	---	13811	3570,	---
13812	/* C_NGLE_D32 */	---	13812	/* C_NGLE_D32 */	---
13813	3573,	---	13813	3573,	---
13814	/* C_NGLE_D32_MM */	---	13814	/* C_NGLE_D32_MM */	---
13815	3576,	---	13815	3576,	---
13816	/* C_NGLE_D64 */	---	13816	/* C_NGLE_D64 */	---
13817	3579,	---	13817	3579,	---
13818	/* C_NGLE_D64_MM */	---	13818	/* C_NGLE_D64_MM */	---
13819	3582,	---	13819	3582,	---
13820	/* C_NGLE_S */	---	13820	/* C_NGLE_S */	---
13821	3585,	---	13821	3585,	---
13822	/* C_NGLE_S_MM */	---	13822	/* C_NGLE_S_MM */	---
13823	3588,	---	13823	3588,	---
13824	/* C_NGL_D32 */	---	13824	/* C_NGL_D32 */	---
13825	3591,	---	13825	3591,	---
13826	/* C_NGL_D32_MM */	---	13826	/* C_NGL_D32_MM */	---
13827	3594,	---	13827	3594,	---
13828	/* C_NGL_D64 */	---	13828	/* C_NGL_D64 */	---
13829	3597,	---	13829	3597,	---
13830	/* C_NGL_D64_MM */	---	13830	/* C_NGL_D64_MM */	---
13831	3600,	---	13831	3600,	---
13832	/* C_NGL_S */	---	13832	/* C_NGL_S */	---
13833	3603,	---	13833	3603,	---
13834	/* C_NGL_S_MM */	---	13834	/* C_NGL_S_MM */	---
13835	3606,	---	13835	3606,	---
13836	/* C_NGT_D32 */	---	13836	/* C_NGT_D32 */	---
13837	3609,	---	13837	3609,	---
13838	/* C_NGT_D32_MM */	---	13838	/* C_NGT_D32_MM */	---
13839	3612,	---	13839	3612,	---
13840	/* C_NGT_D64 */	---	13840	/* C_NGT_D64 */	---
13841	3615,	---	13841	3615,	---
13842	/* C_NGT_D64_MM */	---	13842	/* C_NGT_D64_MM */	---
13843	3618,	---	13843	3618,	---
13844	/* C_NGT_S */	---	13844	/* C_NGT_S */	---
13845	3621,	---	13845	3621,	---
13846	/* C_NGT_S_MM */	---	13846	/* C_NGT_S_MM */	---
13847	3624,	---	13847	3624,	---
13848	/* C_OLE_D32 */	---	13848	/* C_OLE_D32 */	---
13849	3627,	---	13849	3627,	---
13850	/* C_OLE_D32_MM */	---	13850	/* C_OLE_D32_MM */	---
13851	3630,	---	13851	3630,	---
13852	/* C_OLE_D64 */	---	13852	/* C_OLE_D64 */	---
13853	3633,	---	13853	3633,	---
13854	/* C_OLE_D64_MM */	---	13854	/* C_OLE_D64_MM */	---
13855	3636,	---	13855	3636,	---
13856	/* C_OLE_S */	---	13856	/* C_OLE_S */	---
13857	3639,	---	13857	3639,	---
13858	/* C_OLE_S_MM */	---	13858	/* C_OLE_S_MM */	---
13859	3642,	---	13859	3642,	---
13860	/* C_OLT_D32 */	---	13860	/* C_OLT_D32 */	---
13861	3645,	---	13861	3645,	---
13862	/* C_OLT_D32_MM */	---	13862	/* C_OLT_D32_MM */	---
13863	3648,	---	13863	3648,	---
13864	/* C_OLT_D64 */	---	13864	/* C_OLT_D64 */	---
13865	3651,	---	13865	3651,	---
13866	/* C_OLT_D64_MM */	---	13866	/* C_OLT_D64_MM */	---
13867	3654,	---	13867	3654,	---
13868	/* C_OLT_S */	---	13868	/* C_OLT_S */	---
13869	3657,	---	13869	3657,	---
13870	/* C_OLT_S_MM */	---	13870	/* C_OLT_S_MM */	---
13871	3660,	---	13871	3660,	---
13872	/* C_SEQ_D32 */	---	13872	/* C_SEQ_D32 */	---
13873	3663,	---	13873	3663,	---
13874	/* C_SEQ_D32_MM */	---	13874	/* C_SEQ_D32_MM */	---
13875	3666,	---	13875	3666,	---
13876	/* C_SEQ_D64 */	---	13876	/* C_SEQ_D64 */	---
13877	3669,	---	13877	3669,	---
13878	/* C_SEQ_D64_MM */	---	13878	/* C_SEQ_D64_MM */	---
13879	3672,	---	13879	3672,	---
13880	/* C_SEQ_S */	---	13880	/* C_SEQ_S */	---
13881	3675,	---	13881	3675,	---
13882	/* C_SEQ_S_MM */	---	13882	/* C_SEQ_S_MM */	---
13883	3678,	---	13883	3678,	---
13884	/* C_SF_D32 */	---	13884	/* C_SF_D32 */	---
13885	3681,	---	13885	3681,	---
13886	/* C_SF_D32_MM */	---	13886	/* C_SF_D32_MM */	---
13887	3684,	---	13887	3684,	---
13888	/* C_SF_D64 */	---	13888	/* C_SF_D64 */	---
13889	3687,	---	13889	3687,	---
13890	/* C_SF_D64_MM */	---	13890	/* C_SF_D64_MM */	---
13891	3690,	---	13891	3690,	---
13892	/* C_SF_S */	---	13892	/* C_SF_S */	---
13893	3693,	---	13893	3693,	---
13894	/* C_SF_S_MM */	---	13894	/* C_SF_S_MM */	---
13895	3696,	---	13895	3696,	---
13896	/* C_UEQ_D32 */	---	13896	/* C_UEQ_D32 */	---
13897	3699,	---	13897	3699,	---
13898	/* C_UEQ_D32_MM */	---	13898	/* C_UEQ_D32_MM */	---
13899	3702,	---	13899	3702,	---
13900	/* C_UEQ_D64 */	---	13900	/* C_UEQ_D64 */	---
13901	3705,	---	13901	3705,	---
13902	/* C_UEQ_D64_MM */	---	13902	/* C_UEQ_D64_MM */	---
13903	3708,	---	13903	3708,	---
13904	/* C_UEQ_S */	---	13904	/* C_UEQ_S */	---
13905	3711,	---	13905	3711,	---
13906	/* C_UEQ_S_MM */	---	13906	/* C_UEQ_S_MM */	---
13907	3714,	---	13907	3714,	---
13908	/* C_ULE_D32 */	---	13908	/* C_ULE_D32 */	---
13909	3717,	---	13909	3717,	---
13910	/* C_ULE_D32_MM */	---	13910	/* C_ULE_D32_MM */	---
13911	3720,	---	13911	3720,	---
13912	/* C_ULE_D64 */	---	13912	/* C_ULE_D64 */	---
13913	3723,	---	13913	3723,	---
13914	/* C_ULE_D64_MM */	---	13914	/* C_ULE_D64_MM */	---
13915	3726,	---	13915	3726,	---
13916	/* C_ULE_S */	---	13916	/* C_ULE_S */	---
13917	3729,	---	13917	3729,	---
13918	/* C_ULE_S_MM */	---	13918	/* C_ULE_S_MM */	---
13919	3732,	---	13919	3732,	---
13920	/* C_ULT_D32 */	---	13920	/* C_ULT_D32 */	---
13921	3735,	---	13921	3735,	---
13922	/* C_ULT_D32_MM */	---	13922	/* C_ULT_D32_MM */	---
13923	3738,	---	13923	3738,	---
13924	/* C_ULT_D64 */	---	13924	/* C_ULT_D64 */	---
13925	3741,	---	13925	3741,	---
13926	/* C_ULT_D64_MM */	---	13926	/* C_ULT_D64_MM */	---
13927	3744,	---	13927	3744,	---
13928	/* C_ULT_S */	---	13928	/* C_ULT_S */	---
13929	3747,	---	13929	3747,	---
13930	/* C_ULT_S_MM */	---	13930	/* C_ULT_S_MM */	---
13931	3750,	---	13931	3750,	---
13932	/* C_UN_D32 */	---	13932	/* C_UN_D32 */	---
13933	3753,	---	13933	3753,	---
13934	/* C_UN_D32_MM */	---	13934	/* C_UN_D32_MM */	---
13935	3756,	---	13935	3756,	---
13936	/* C_UN_D64 */	---	13936	/* C_UN_D64 */	---
13937	3759,	---	13937	3759,	---
13938	/* C_UN_D64_MM */	---	13938	/* C_UN_D64_MM */	---
13939	3762,	---	13939	3762,	---
13940	/* C_UN_S */	---	13940	/* C_UN_S */	---
13941	3765,	---	13941	3765,	---
13942	/* C_UN_S_MM */	---	13942	/* C_UN_S_MM */	---
13943	3768,	---	13943	3768,	---
13944	/* CmpRxRy16 */	---	13944	/* CmpRxRy16 */	---
13945	3771,	---	13945	3771,	---
13946	/* CmpiRxImm16 */	---	13946	/* CmpiRxImm16 */	---
13947	3773,	---	13947	3773,	---
13948	/* CmpiRxImmX16 */	---	13948	/* CmpiRxImmX16 */	---
13949	3775,	---	13949	3775,	---
13950	/* DADD */	---	13950	/* DADD */	---
13951	3777,	---	13951	3777,	---
13952	/* DADDi */	---	13952	/* DADDi */	---
13953	3780,	---	13953	3780,	---
13954	/* DADDiu */	---	13954	/* DADDiu */	---
13955	3783,	---	13955	3783,	---
13956	/* DADDu */	---	13956	/* DADDu */	---
13957	3786,	---	13957	3786,	---
13958	/* DAHI */	---	13958	/* DAHI */	---
13959	3789,	---	13959	3789,	---
13960	/* DALIGN */	---	13960	/* DALIGN */	---
13961	3792,	---	13961	3792,	---
13962	/* DATI */	---	13962	/* DATI */	---
13963	3796,	---	13963	3796,	---
13964	/* DAUI */	---	13964	/* DAUI */	---
13965	3799,	---	13965	3799,	---
13966	/* DBITSWAP */	---	13966	/* DBITSWAP */	---
13967	3802,	---	13967	3802,	---
13968	/* DCLO */	---	13968	/* DCLO */	---
13969	3804,	---	13969	3804,	---
13970	/* DCLO_R6 */	---	13970	/* DCLO_R6 */	---
13971	3806,	---	13971	3806,	---
13972	/* DCLZ */	---	13972	/* DCLZ */	---
13973	3808,	---	13973	3808,	---
13974	/* DCLZ_R6 */	---	13974	/* DCLZ_R6 */	---
13975	3810,	---	13975	3810,	---
13976	/* DDIV */	---	13976	/* DDIV */	---
13977	3812,	---	13977	3812,	---
13978	/* DDIVU */	---	13978	/* DDIVU */	---
13979	3815,	---	13979	3815,	---
13980	/* DERET */	---	13980	/* DERET */	---
13981	3818,	---	13981	3818,	---
13982	/* DERET_MM */	---	13982	/* DERET_MM */	---
13983	3818,	---	13983	3818,	---
13984	/* DERET_MMR6 */	---	13984	/* DERET_MMR6 */	---
13985	3818,	---	13985	3818,	---
13986	/* DEXT */	---	13986	/* DEXT */	---
13987	3818,	---	13987	3818,	---
13988	/* DEXT64_32 */	---	13988	/* DEXT64_32 */	---
13989	3822,	---	13989	3822,	---
13990	/* DEXTM */	---	13990	/* DEXTM */	---
13991	3826,	---	13991	3826,	---
13992	/* DEXTU */	---	13992	/* DEXTU */	---
13993	3830,	---	13993	3830,	---
13994	/* DI */	---	13994	/* DI */	---
13995	3834,	---	13995	3834,	---
13996	/* DINS */	---	13996	/* DINS */	---
13997	3835,	---	13997	3835,	---
13998	/* DINSM */	---	13998	/* DINSM */	---
13999	3840,	---	13999	3840,	---
14000	/* DINSU */	---	14000	/* DINSU */	---
14001	3845,	---	14001	3845,	---
14002	/* DIV */	---	14002	/* DIV */	---
14003	3850,	---	14003	3850,	---
14004	/* DIVU */	---	14004	/* DIVU */	---
14005	3853,	---	14005	3853,	---
14006	/* DIVU_MMR6 */	---	14006	/* DIVU_MMR6 */	---
14007	3856,	---	14007	3856,	---
14008	/* DIV_MMR6 */	---	14008	/* DIV_MMR6 */	---
14009	3859,	---	14009	3859,	---
14010	/* DIV_S_B */	---	14010	/* DIV_S_B */	---
14011	3862,	---	14011	3862,	---
14012	/* DIV_S_D */	---	14012	/* DIV_S_D */	---
14013	3865,	---	14013	3865,	---
14014	/* DIV_S_H */	---	14014	/* DIV_S_H */	---
14015	3868,	---	14015	3868,	---
14016	/* DIV_S_W */	---	14016	/* DIV_S_W */	---
14017	3871,	---	14017	3871,	---
14018	/* DIV_U_B */	---	14018	/* DIV_U_B */	---
14019	3874,	---	14019	3874,	---
14020	/* DIV_U_D */	---	14020	/* DIV_U_D */	---
14021	3877,	---	14021	3877,	---
14022	/* DIV_U_H */	---	14022	/* DIV_U_H */	---
14023	3880,	---	14023	3880,	---
14024	/* DIV_U_W */	---	14024	/* DIV_U_W */	---
14025	3883,	---	14025	3883,	---
14026	/* DI_MM */	---	14026	/* DI_MM */	---
14027	3886,	---	14027	3886,	---
14028	/* DI_MMR6 */	---	14028	/* DI_MMR6 */	---
14029	3887,	---	14029	3887,	---
14030	/* DLSA */	---	14030	/* DLSA */	---
14031	3888,	---	14031	3888,	---
14032	/* DLSA_R6 */	---	14032	/* DLSA_R6 */	---
14033	3892,	---	14033	3892,	---
14034	/* DMFC0 */	---	14034	/* DMFC0 */	---
14035	3896,	---	14035	3896,	---
14036	/* DMFC1 */	---	14036	/* DMFC1 */	---
14037	3899,	---	14037	3899,	---
14038	/* DMFC2 */	---	14038	/* DMFC2 */	---
14039	3901,	---	14039	3901,	---
14040	/* DMFC2_OCTEON */	---	14040	/* DMFC2_OCTEON */	---
14041	3904,	---	14041	3904,	---
14042	/* DMFGC0 */	---	14042	/* DMFGC0 */	---
14043	3906,	---	14043	3906,	---
14044	/* DMOD */	---	14044	/* DMOD */	---
14045	3909,	---	14045	3909,	---
14046	/* DMODU */	---	14046	/* DMODU */	---
14047	3912,	---	14047	3912,	---
14048	/* DMT */	---	14048	/* DMT */	---
14049	3915,	---	14049	3915,	---
14050	/* DMTC0 */	---	14050	/* DMTC0 */	---
14051	3916,	---	14051	3916,	---
14052	/* DMTC1 */	---	14052	/* DMTC1 */	---
14053	3919,	---	14053	3919,	---
14054	/* DMTC2 */	---	14054	/* DMTC2 */	---
14055	3921,	---	14055	3921,	---
14056	/* DMTC2_OCTEON */	---	14056	/* DMTC2_OCTEON */	---
14057	3924,	---	14057	3924,	---
14058	/* DMTGC0 */	---	14058	/* DMTGC0 */	---
14059	3926,	---	14059	3926,	---
14060	/* DMUH */	---	14060	/* DMUH */	---
14061	3929,	---	14061	3929,	---
14062	/* DMUHU */	---	14062	/* DMUHU */	---
14063	3932,	---	14063	3932,	---
14064	/* DMUL */	---	14064	/* DMUL */	---
14065	3935,	---	14065	3935,	---
14066	/* DMULT */	---	14066	/* DMULT */	---
14067	3938,	---	14067	3938,	---
14068	/* DMULTu */	---	14068	/* DMULTu */	---
14069	3940,	---	14069	3940,	---
14070	/* DMULU */	---	14070	/* DMULU */	---
14071	3942,	---	14071	3942,	---
14072	/* DMUL_R6 */	---	14072	/* DMUL_R6 */	---
14073	3945,	---	14073	3945,	---
14074	/* DOTP_S_D */	---	14074	/* DOTP_S_D */	---
14075	3948,	---	14075	3948,	---
14076	/* DOTP_S_H */	---	14076	/* DOTP_S_H */	---
14077	3951,	---	14077	3951,	---
14078	/* DOTP_S_W */	---	14078	/* DOTP_S_W */	---
14079	3954,	---	14079	3954,	---
14080	/* DOTP_U_D */	---	14080	/* DOTP_U_D */	---
14081	3957,	---	14081	3957,	---
14082	/* DOTP_U_H */	---	14082	/* DOTP_U_H */	---
14083	3960,	---	14083	3960,	---
14084	/* DOTP_U_W */	---	14084	/* DOTP_U_W */	---
14085	3963,	---	14085	3963,	---
14086	/* DPADD_S_D */	---	14086	/* DPADD_S_D */	---
14087	3966,	---	14087	3966,	---
14088	/* DPADD_S_H */	---	14088	/* DPADD_S_H */	---
14089	3970,	---	14089	3970,	---
14090	/* DPADD_S_W */	---	14090	/* DPADD_S_W */	---
14091	3974,	---	14091	3974,	---
14092	/* DPADD_U_D */	---	14092	/* DPADD_U_D */	---
14093	3978,	---	14093	3978,	---
14094	/* DPADD_U_H */	---	14094	/* DPADD_U_H */	---
14095	3982,	---	14095	3982,	---
14096	/* DPADD_U_W */	---	14096	/* DPADD_U_W */	---
14097	3986,	---	14097	3986,	---
14098	/* DPAQX_SA_W_PH */	---	14098	/* DPAQX_SA_W_PH */	---
14099	3990,	---	14099	3990,	---
14100	/* DPAQX_SA_W_PH_MMR2 */	---	14100	/* DPAQX_SA_W_PH_MMR2 */	---
14101	3994,	---	14101	3994,	---
14102	/* DPAQX_S_W_PH */	---	14102	/* DPAQX_S_W_PH */	---
14103	3998,	---	14103	3998,	---
14104	/* DPAQX_S_W_PH_MMR2 */	---	14104	/* DPAQX_S_W_PH_MMR2 */	---
14105	4002,	---	14105	4002,	---
14106	/* DPAQ_SA_L_W */	---	14106	/* DPAQ_SA_L_W */	---
14107	4006,	---	14107	4006,	---
14108	/* DPAQ_SA_L_W_MM */	---	14108	/* DPAQ_SA_L_W_MM */	---
14109	4010,	---	14109	4010,	---
14110	/* DPAQ_S_W_PH */	---	14110	/* DPAQ_S_W_PH */	---
14111	4014,	---	14111	4014,	---
14112	/* DPAQ_S_W_PH_MM */	---	14112	/* DPAQ_S_W_PH_MM */	---
14113	4018,	---	14113	4018,	---
14114	/* DPAU_H_QBL */	---	14114	/* DPAU_H_QBL */	---
14115	4022,	---	14115	4022,	---
14116	/* DPAU_H_QBL_MM */	---	14116	/* DPAU_H_QBL_MM */	---
14117	4026,	---	14117	4026,	---
14118	/* DPAU_H_QBR */	---	14118	/* DPAU_H_QBR */	---
14119	4030,	---	14119	4030,	---
14120	/* DPAU_H_QBR_MM */	---	14120	/* DPAU_H_QBR_MM */	---
14121	4034,	---	14121	4034,	---
14122	/* DPAX_W_PH */	---	14122	/* DPAX_W_PH */	---
14123	4038,	---	14123	4038,	---
14124	/* DPAX_W_PH_MMR2 */	---	14124	/* DPAX_W_PH_MMR2 */	---
14125	4042,	---	14125	4042,	---
14126	/* DPA_W_PH */	---	14126	/* DPA_W_PH */	---
14127	4046,	---	14127	4046,	---
14128	/* DPA_W_PH_MMR2 */	---	14128	/* DPA_W_PH_MMR2 */	---
14129	4050,	---	14129	4050,	---
14130	/* DPOP */	---	14130	/* DPOP */	---
14131	4054,	---	14131	4054,	---
14132	/* DPSQX_SA_W_PH */	---	14132	/* DPSQX_SA_W_PH */	---
14133	4056,	---	14133	4056,	---
14134	/* DPSQX_SA_W_PH_MMR2 */	---	14134	/* DPSQX_SA_W_PH_MMR2 */	---
14135	4060,	---	14135	4060,	---
14136	/* DPSQX_S_W_PH */	---	14136	/* DPSQX_S_W_PH */	---
14137	4064,	---	14137	4064,	---
14138	/* DPSQX_S_W_PH_MMR2 */	---	14138	/* DPSQX_S_W_PH_MMR2 */	---
14139	4068,	---	14139	4068,	---
14140	/* DPSQ_SA_L_W */	---	14140	/* DPSQ_SA_L_W */	---
14141	4072,	---	14141	4072,	---
14142	/* DPSQ_SA_L_W_MM */	---	14142	/* DPSQ_SA_L_W_MM */	---
14143	4076,	---	14143	4076,	---
14144	/* DPSQ_S_W_PH */	---	14144	/* DPSQ_S_W_PH */	---
14145	4080,	---	14145	4080,	---
14146	/* DPSQ_S_W_PH_MM */	---	14146	/* DPSQ_S_W_PH_MM */	---
14147	4084,	---	14147	4084,	---
14148	/* DPSUB_S_D */	---	14148	/* DPSUB_S_D */	---
14149	4088,	---	14149	4088,	---
14150	/* DPSUB_S_H */	---	14150	/* DPSUB_S_H */	---
14151	4092,	---	14151	4092,	---
14152	/* DPSUB_S_W */	---	14152	/* DPSUB_S_W */	---
14153	4096,	---	14153	4096,	---
14154	/* DPSUB_U_D */	---	14154	/* DPSUB_U_D */	---
14155	4100,	---	14155	4100,	---
14156	/* DPSUB_U_H */	---	14156	/* DPSUB_U_H */	---
14157	4104,	---	14157	4104,	---
14158	/* DPSUB_U_W */	---	14158	/* DPSUB_U_W */	---
14159	4108,	---	14159	4108,	---
14160	/* DPSU_H_QBL */	---	14160	/* DPSU_H_QBL */	---
14161	4112,	---	14161	4112,	---
14162	/* DPSU_H_QBL_MM */	---	14162	/* DPSU_H_QBL_MM */	---
14163	4116,	---	14163	4116,	---
14164	/* DPSU_H_QBR */	---	14164	/* DPSU_H_QBR */	---
14165	4120,	---	14165	4120,	---
14166	/* DPSU_H_QBR_MM */	---	14166	/* DPSU_H_QBR_MM */	---
14167	4124,	---	14167	4124,	---
14168	/* DPSX_W_PH */	---	14168	/* DPSX_W_PH */	---
14169	4128,	---	14169	4128,	---
14170	/* DPSX_W_PH_MMR2 */	---	14170	/* DPSX_W_PH_MMR2 */	---
14171	4132,	---	14171	4132,	---
14172	/* DPS_W_PH */	---	14172	/* DPS_W_PH */	---
14173	4136,	---	14173	4136,	---
14174	/* DPS_W_PH_MMR2 */	---	14174	/* DPS_W_PH_MMR2 */	---
14175	4140,	---	14175	4140,	---
14176	/* DROTR */	---	14176	/* DROTR */	---
14177	4144,	---	14177	4144,	---
14178	/* DROTR32 */	---	14178	/* DROTR32 */	---
14179	4147,	---	14179	4147,	---
14180	/* DROTRV */	---	14180	/* DROTRV */	---
14181	4150,	---	14181	4150,	---
14182	/* DSBH */	---	14182	/* DSBH */	---
14183	4153,	---	14183	4153,	---
14184	/* DSDIV */	---	14184	/* DSDIV */	---
14185	4155,	---	14185	4155,	---
14186	/* DSHD */	---	14186	/* DSHD */	---
14187	4157,	---	14187	4157,	---
14188	/* DSLL */	---	14188	/* DSLL */	---
14189	4159,	---	14189	4159,	---
14190	/* DSLL32 */	---	14190	/* DSLL32 */	---
14191	4162,	---	14191	4162,	---
14192	/* DSLL64_32 */	---	14192	/* DSLL64_32 */	---
14193	4165,	---	14193	4165,	---
14194	/* DSLLV */	---	14194	/* DSLLV */	---
14195	4167,	---	14195	4167,	---
14196	/* DSRA */	---	14196	/* DSRA */	---
14197	4170,	---	14197	4170,	---
14198	/* DSRA32 */	---	14198	/* DSRA32 */	---
14199	4173,	---	14199	4173,	---
14200	/* DSRAV */	---	14200	/* DSRAV */	---
14201	4176,	---	14201	4176,	---
14202	/* DSRL */	---	14202	/* DSRL */	---
14203	4179,	---	14203	4179,	---
14204	/* DSRL32 */	---	14204	/* DSRL32 */	---
14205	4182,	---	14205	4182,	---
14206	/* DSRLV */	---	14206	/* DSRLV */	---
14207	4185,	---	14207	4185,	---
14208	/* DSUB */	---	14208	/* DSUB */	---
14209	4188,	---	14209	4188,	---
14210	/* DSUBu */	---	14210	/* DSUBu */	---
14211	4191,	---	14211	4191,	---
14212	/* DUDIV */	---	14212	/* DUDIV */	---
14213	4194,	---	14213	4194,	---
14214	/* DVP */	---	14214	/* DVP */	---
14215	4196,	---	14215	4196,	---
14216	/* DVPE */	---	14216	/* DVPE */	---
14217	4197,	---	14217	4197,	---
14218	/* DVP_MMR6 */	---	14218	/* DVP_MMR6 */	---
14219	4198,	---	14219	4198,	---
14220	/* DivRxRy16 */	---	14220	/* DivRxRy16 */	---
14221	4199,	---	14221	4199,	---
14222	/* DivuRxRy16 */	---	14222	/* DivuRxRy16 */	---
14223	4201,	---	14223	4201,	---
14224	/* EHB */	---	14224	/* EHB */	---
14225	4203,	---	14225	4203,	---
14226	/* EHB_MM */	---	14226	/* EHB_MM */	---
14227	4203,	---	14227	4203,	---
14228	/* EHB_MMR6 */	---	14228	/* EHB_MMR6 */	---
14229	4203,	---	14229	4203,	---
14230	/* EI */	---	14230	/* EI */	---
14231	4203,	---	14231	4203,	---
14232	/* EI_MM */	---	14232	/* EI_MM */	---
14233	4204,	---	14233	4204,	---
14234	/* EI_MMR6 */	---	14234	/* EI_MMR6 */	---
14235	4205,	---	14235	4205,	---
14236	/* EMT */	---	14236	/* EMT */	---
14237	4206,	---	14237	4206,	---
14238	/* ERET */	---	14238	/* ERET */	---
14239	4207,	---	14239	4207,	---
14240	/* ERETNC */	---	14240	/* ERETNC */	---
14241	4207,	---	14241	4207,	---
14242	/* ERETNC_MMR6 */	---	14242	/* ERETNC_MMR6 */	---
14243	4207,	---	14243	4207,	---
14244	/* ERET_MM */	---	14244	/* ERET_MM */	---
14245	4207,	---	14245	4207,	---
14246	/* ERET_MMR6 */	---	14246	/* ERET_MMR6 */	---
14247	4207,	---	14247	4207,	---
14248	/* EVP */	---	14248	/* EVP */	---
14249	4207,	---	14249	4207,	---
14250	/* EVPE */	---	14250	/* EVPE */	---
14251	4208,	---	14251	4208,	---
14252	/* EVP_MMR6 */	---	14252	/* EVP_MMR6 */	---
14253	4209,	---	14253	4209,	---
14254	/* EXT */	---	14254	/* EXT */	---
14255	4210,	---	14255	4210,	---
14256	/* EXTP */	---	14256	/* EXTP */	---
14257	4214,	---	14257	4214,	---
14258	/* EXTPDP */	---	14258	/* EXTPDP */	---
14259	4217,	---	14259	4217,	---
14260	/* EXTPDPV */	---	14260	/* EXTPDPV */	---
14261	4220,	---	14261	4220,	---
14262	/* EXTPDPV_MM */	---	14262	/* EXTPDPV_MM */	---
14263	4223,	---	14263	4223,	---
14264	/* EXTPDP_MM */	---	14264	/* EXTPDP_MM */	---
14265	4226,	---	14265	4226,	---
14266	/* EXTPV */	---	14266	/* EXTPV */	---
14267	4229,	---	14267	4229,	---
14268	/* EXTPV_MM */	---	14268	/* EXTPV_MM */	---
14269	4232,	---	14269	4232,	---
14270	/* EXTP_MM */	---	14270	/* EXTP_MM */	---
14271	4235,	---	14271	4235,	---
14272	/* EXTRV_RS_W */	---	14272	/* EXTRV_RS_W */	---
14273	4238,	---	14273	4238,	---
14274	/* EXTRV_RS_W_MM */	---	14274	/* EXTRV_RS_W_MM */	---
14275	4241,	---	14275	4241,	---
14276	/* EXTRV_R_W */	---	14276	/* EXTRV_R_W */	---
14277	4244,	---	14277	4244,	---
14278	/* EXTRV_R_W_MM */	---	14278	/* EXTRV_R_W_MM */	---
14279	4247,	---	14279	4247,	---
14280	/* EXTRV_S_H */	---	14280	/* EXTRV_S_H */	---
14281	4250,	---	14281	4250,	---
14282	/* EXTRV_S_H_MM */	---	14282	/* EXTRV_S_H_MM */	---
14283	4253,	---	14283	4253,	---
14284	/* EXTRV_W */	---	14284	/* EXTRV_W */	---
14285	4256,	---	14285	4256,	---
14286	/* EXTRV_W_MM */	---	14286	/* EXTRV_W_MM */	---
14287	4259,	---	14287	4259,	---
14288	/* EXTR_RS_W */	---	14288	/* EXTR_RS_W */	---
14289	4262,	---	14289	4262,	---
14290	/* EXTR_RS_W_MM */	---	14290	/* EXTR_RS_W_MM */	---
14291	4265,	---	14291	4265,	---
14292	/* EXTR_R_W */	---	14292	/* EXTR_R_W */	---
14293	4268,	---	14293	4268,	---
14294	/* EXTR_R_W_MM */	---	14294	/* EXTR_R_W_MM */	---
14295	4271,	---	14295	4271,	---
14296	/* EXTR_S_H */	---	14296	/* EXTR_S_H */	---
14297	4274,	---	14297	4274,	---
14298	/* EXTR_S_H_MM */	---	14298	/* EXTR_S_H_MM */	---
14299	4277,	---	14299	4277,	---
14300	/* EXTR_W */	---	14300	/* EXTR_W */	---
14301	4280,	---	14301	4280,	---
14302	/* EXTR_W_MM */	---	14302	/* EXTR_W_MM */	---
14303	4283,	---	14303	4283,	---
14304	/* EXTS */	---	14304	/* EXTS */	---
14305	4286,	---	14305	4286,	---
14306	/* EXTS32 */	---	14306	/* EXTS32 */	---
14307	4290,	---	14307	4290,	---
14308	/* EXT_MM */	---	14308	/* EXT_MM */	---
14309	4294,	---	14309	4294,	---
14310	/* EXT_MMR6 */	---	14310	/* EXT_MMR6 */	---
14311	4298,	---	14311	4298,	---
14312	/* FABS_D32 */	---	14312	/* FABS_D32 */	---
14313	4302,	---	14313	4302,	---
14314	/* FABS_D32_MM */	---	14314	/* FABS_D32_MM */	---
14315	4304,	---	14315	4304,	---
14316	/* FABS_D64 */	---	14316	/* FABS_D64 */	---
14317	4306,	---	14317	4306,	---
14318	/* FABS_D64_MM */	---	14318	/* FABS_D64_MM */	---
14319	4308,	---	14319	4308,	---
14320	/* FABS_S */	---	14320	/* FABS_S */	---
14321	4310,	---	14321	4310,	---
14322	/* FABS_S_MM */	---	14322	/* FABS_S_MM */	---
14323	4312,	---	14323	4312,	---
14324	/* FADD_D */	---	14324	/* FADD_D */	---
14325	4314,	---	14325	4314,	---
14326	/* FADD_D32 */	---	14326	/* FADD_D32 */	---
14327	4317,	---	14327	4317,	---
14328	/* FADD_D32_MM */	---	14328	/* FADD_D32_MM */	---
14329	4320,	---	14329	4320,	---
14330	/* FADD_D64 */	---	14330	/* FADD_D64 */	---
14331	4323,	---	14331	4323,	---
14332	/* FADD_D64_MM */	---	14332	/* FADD_D64_MM */	---
14333	4326,	---	14333	4326,	---
14334	/* FADD_PS64 */	---	14334	/* FADD_PS64 */	---
14335	4329,	---	14335	4329,	---
14336	/* FADD_S */	---	14336	/* FADD_S */	---
14337	4332,	---	14337	4332,	---
14338	/* FADD_S_MM */	---	14338	/* FADD_S_MM */	---
14339	4335,	---	14339	4335,	---
14340	/* FADD_S_MMR6 */	---	14340	/* FADD_S_MMR6 */	---
14341	4338,	---	14341	4338,	---
14342	/* FADD_W */	---	14342	/* FADD_W */	---
14343	4341,	---	14343	4341,	---
14344	/* FCAF_D */	---	14344	/* FCAF_D */	---
14345	4344,	---	14345	4344,	---
14346	/* FCAF_W */	---	14346	/* FCAF_W */	---
14347	4347,	---	14347	4347,	---
14348	/* FCEQ_D */	---	14348	/* FCEQ_D */	---
14349	4350,	---	14349	4350,	---
14350	/* FCEQ_W */	---	14350	/* FCEQ_W */	---
14351	4353,	---	14351	4353,	---
14352	/* FCLASS_D */	---	14352	/* FCLASS_D */	---
14353	4356,	---	14353	4356,	---
14354	/* FCLASS_W */	---	14354	/* FCLASS_W */	---
14355	4358,	---	14355	4358,	---
14356	/* FCLE_D */	---	14356	/* FCLE_D */	---
14357	4360,	---	14357	4360,	---
14358	/* FCLE_W */	---	14358	/* FCLE_W */	---
14359	4363,	---	14359	4363,	---
14360	/* FCLT_D */	---	14360	/* FCLT_D */	---
14361	4366,	---	14361	4366,	---
14362	/* FCLT_W */	---	14362	/* FCLT_W */	---
14363	4369,	---	14363	4369,	---
14364	/* FCMP_D32 */	---	14364	/* FCMP_D32 */	---
14365	4372,	---	14365	4372,	---
14366	/* FCMP_D32_MM */	---	14366	/* FCMP_D32_MM */	---
14367	4375,	---	14367	4375,	---
14368	/* FCMP_D64 */	---	14368	/* FCMP_D64 */	---
14369	4378,	---	14369	4378,	---
14370	/* FCMP_S32 */	---	14370	/* FCMP_S32 */	---
14371	4381,	---	14371	4381,	---
14372	/* FCMP_S32_MM */	---	14372	/* FCMP_S32_MM */	---
14373	4384,	---	14373	4384,	---
14374	/* FCNE_D */	---	14374	/* FCNE_D */	---
14375	4387,	---	14375	4387,	---
14376	/* FCNE_W */	---	14376	/* FCNE_W */	---
14377	4390,	---	14377	4390,	---
14378	/* FCOR_D */	---	14378	/* FCOR_D */	---
14379	4393,	---	14379	4393,	---
14380	/* FCOR_W */	---	14380	/* FCOR_W */	---
14381	4396,	---	14381	4396,	---
14382	/* FCUEQ_D */	---	14382	/* FCUEQ_D */	---
14383	4399,	---	14383	4399,	---
14384	/* FCUEQ_W */	---	14384	/* FCUEQ_W */	---
14385	4402,	---	14385	4402,	---
14386	/* FCULE_D */	---	14386	/* FCULE_D */	---
14387	4405,	---	14387	4405,	---
14388	/* FCULE_W */	---	14388	/* FCULE_W */	---
14389	4408,	---	14389	4408,	---
14390	/* FCULT_D */	---	14390	/* FCULT_D */	---
14391	4411,	---	14391	4411,	---
14392	/* FCULT_W */	---	14392	/* FCULT_W */	---
14393	4414,	---	14393	4414,	---
14394	/* FCUNE_D */	---	14394	/* FCUNE_D */	---
14395	4417,	---	14395	4417,	---
14396	/* FCUNE_W */	---	14396	/* FCUNE_W */	---
14397	4420,	---	14397	4420,	---
14398	/* FCUN_D */	---	14398	/* FCUN_D */	---
14399	4423,	---	14399	4423,	---
14400	/* FCUN_W */	---	14400	/* FCUN_W */	---
14401	4426,	---	14401	4426,	---
14402	/* FDIV_D */	---	14402	/* FDIV_D */	---
14403	4429,	---	14403	4429,	---
14404	/* FDIV_D32 */	---	14404	/* FDIV_D32 */	---
14405	4432,	---	14405	4432,	---
14406	/* FDIV_D32_MM */	---	14406	/* FDIV_D32_MM */	---
14407	4435,	---	14407	4435,	---
14408	/* FDIV_D64 */	---	14408	/* FDIV_D64 */	---
14409	4438,	---	14409	4438,	---
14410	/* FDIV_D64_MM */	---	14410	/* FDIV_D64_MM */	---
14411	4441,	---	14411	4441,	---
14412	/* FDIV_S */	---	14412	/* FDIV_S */	---
14413	4444,	---	14413	4444,	---
14414	/* FDIV_S_MM */	---	14414	/* FDIV_S_MM */	---
14415	4447,	---	14415	4447,	---
14416	/* FDIV_S_MMR6 */	---	14416	/* FDIV_S_MMR6 */	---
14417	4450,	---	14417	4450,	---
14418	/* FDIV_W */	---	14418	/* FDIV_W */	---
14419	4453,	---	14419	4453,	---
14420	/* FEXDO_H */	---	14420	/* FEXDO_H */	---
14421	4456,	---	14421	4456,	---
14422	/* FEXDO_W */	---	14422	/* FEXDO_W */	---
14423	4459,	---	14423	4459,	---
14424	/* FEXP2_D */	---	14424	/* FEXP2_D */	---
14425	4462,	---	14425	4462,	---
14426	/* FEXP2_W */	---	14426	/* FEXP2_W */	---
14427	4465,	---	14427	4465,	---
14428	/* FEXUPL_D */	---	14428	/* FEXUPL_D */	---
14429	4468,	---	14429	4468,	---
14430	/* FEXUPL_W */	---	14430	/* FEXUPL_W */	---
14431	4470,	---	14431	4470,	---
14432	/* FEXUPR_D */	---	14432	/* FEXUPR_D */	---
14433	4472,	---	14433	4472,	---
14434	/* FEXUPR_W */	---	14434	/* FEXUPR_W */	---
14435	4474,	---	14435	4474,	---
14436	/* FFINT_S_D */	---	14436	/* FFINT_S_D */	---
14437	4476,	---	14437	4476,	---
14438	/* FFINT_S_W */	---	14438	/* FFINT_S_W */	---
14439	4478,	---	14439	4478,	---
14440	/* FFINT_U_D */	---	14440	/* FFINT_U_D */	---
14441	4480,	---	14441	4480,	---
14442	/* FFINT_U_W */	---	14442	/* FFINT_U_W */	---
14443	4482,	---	14443	4482,	---
14444	/* FFQL_D */	---	14444	/* FFQL_D */	---
14445	4484,	---	14445	4484,	---
14446	/* FFQL_W */	---	14446	/* FFQL_W */	---
14447	4486,	---	14447	4486,	---
14448	/* FFQR_D */	---	14448	/* FFQR_D */	---
14449	4488,	---	14449	4488,	---
14450	/* FFQR_W */	---	14450	/* FFQR_W */	---
14451	4490,	---	14451	4490,	---
14452	/* FILL_B */	---	14452	/* FILL_B */	---
14453	4492,	---	14453	4492,	---
14454	/* FILL_D */	---	14454	/* FILL_D */	---
14455	4494,	---	14455	4494,	---
14456	/* FILL_H */	---	14456	/* FILL_H */	---
14457	4496,	---	14457	4496,	---
14458	/* FILL_W */	---	14458	/* FILL_W */	---
14459	4498,	---	14459	4498,	---
14460	/* FLOG2_D */	---	14460	/* FLOG2_D */	---
14461	4500,	---	14461	4500,	---
14462	/* FLOG2_W */	---	14462	/* FLOG2_W */	---
14463	4502,	---	14463	4502,	---
14464	/* FLOOR_L_D64 */	---	14464	/* FLOOR_L_D64 */	---
14465	4504,	---	14465	4504,	---
14466	/* FLOOR_L_D_MMR6 */	---	14466	/* FLOOR_L_D_MMR6 */	---
14467	4506,	---	14467	4506,	---
14468	/* FLOOR_L_S */	---	14468	/* FLOOR_L_S */	---
14469	4508,	---	14469	4508,	---
14470	/* FLOOR_L_S_MMR6 */	---	14470	/* FLOOR_L_S_MMR6 */	---
14471	4510,	---	14471	4510,	---
14472	/* FLOOR_W_D32 */	---	14472	/* FLOOR_W_D32 */	---
14473	4512,	---	14473	4512,	---
14474	/* FLOOR_W_D64 */	---	14474	/* FLOOR_W_D64 */	---
14475	4514,	---	14475	4514,	---
14476	/* FLOOR_W_D_MMR6 */	---	14476	/* FLOOR_W_D_MMR6 */	---
14477	4516,	---	14477	4516,	---
14478	/* FLOOR_W_MM */	---	14478	/* FLOOR_W_MM */	---
14479	4518,	---	14479	4518,	---
14480	/* FLOOR_W_S */	---	14480	/* FLOOR_W_S */	---
14481	4520,	---	14481	4520,	---
14482	/* FLOOR_W_S_MM */	---	14482	/* FLOOR_W_S_MM */	---
14483	4522,	---	14483	4522,	---
14484	/* FLOOR_W_S_MMR6 */	---	14484	/* FLOOR_W_S_MMR6 */	---
14485	4524,	---	14485	4524,	---
14486	/* FMADD_D */	---	14486	/* FMADD_D */	---
14487	4526,	---	14487	4526,	---
14488	/* FMADD_W */	---	14488	/* FMADD_W */	---
14489	4530,	---	14489	4530,	---
14490	/* FMAX_A_D */	---	14490	/* FMAX_A_D */	---
14491	4534,	---	14491	4534,	---
14492	/* FMAX_A_W */	---	14492	/* FMAX_A_W */	---
14493	4537,	---	14493	4537,	---
14494	/* FMAX_D */	---	14494	/* FMAX_D */	---
14495	4540,	---	14495	4540,	---
14496	/* FMAX_W */	---	14496	/* FMAX_W */	---
14497	4543,	---	14497	4543,	---
14498	/* FMIN_A_D */	---	14498	/* FMIN_A_D */	---
14499	4546,	---	14499	4546,	---
14500	/* FMIN_A_W */	---	14500	/* FMIN_A_W */	---
14501	4549,	---	14501	4549,	---
14502	/* FMIN_D */	---	14502	/* FMIN_D */	---
14503	4552,	---	14503	4552,	---
14504	/* FMIN_W */	---	14504	/* FMIN_W */	---
14505	4555,	---	14505	4555,	---
14506	/* FMOV_D32 */	---	14506	/* FMOV_D32 */	---
14507	4558,	---	14507	4558,	---
14508	/* FMOV_D32_MM */	---	14508	/* FMOV_D32_MM */	---
14509	4560,	---	14509	4560,	---
14510	/* FMOV_D64 */	---	14510	/* FMOV_D64 */	---
14511	4562,	---	14511	4562,	---
14512	/* FMOV_D64_MM */	---	14512	/* FMOV_D64_MM */	---
14513	4564,	---	14513	4564,	---
14514	/* FMOV_D_MMR6 */	---	14514	/* FMOV_D_MMR6 */	---
14515	4566,	---	14515	4566,	---
14516	/* FMOV_S */	---	14516	/* FMOV_S */	---
14517	4568,	---	14517	4568,	---
14518	/* FMOV_S_MM */	---	14518	/* FMOV_S_MM */	---
14519	4570,	---	14519	4570,	---
14520	/* FMOV_S_MMR6 */	---	14520	/* FMOV_S_MMR6 */	---
14521	4572,	---	14521	4572,	---
14522	/* FMSUB_D */	---	14522	/* FMSUB_D */	---
14523	4574,	---	14523	4574,	---
14524	/* FMSUB_W */	---	14524	/* FMSUB_W */	---
14525	4578,	---	14525	4578,	---
14526	/* FMUL_D */	---	14526	/* FMUL_D */	---
14527	4582,	---	14527	4582,	---
14528	/* FMUL_D32 */	---	14528	/* FMUL_D32 */	---
14529	4585,	---	14529	4585,	---
14530	/* FMUL_D32_MM */	---	14530	/* FMUL_D32_MM */	---
14531	4588,	---	14531	4588,	---
14532	/* FMUL_D64 */	---	14532	/* FMUL_D64 */	---
14533	4591,	---	14533	4591,	---
14534	/* FMUL_D64_MM */	---	14534	/* FMUL_D64_MM */	---
14535	4594,	---	14535	4594,	---
14536	/* FMUL_PS64 */	---	14536	/* FMUL_PS64 */	---
14537	4597,	---	14537	4597,	---
14538	/* FMUL_S */	---	14538	/* FMUL_S */	---
14539	4600,	---	14539	4600,	---
14540	/* FMUL_S_MM */	---	14540	/* FMUL_S_MM */	---
14541	4603,	---	14541	4603,	---
14542	/* FMUL_S_MMR6 */	---	14542	/* FMUL_S_MMR6 */	---
14543	4606,	---	14543	4606,	---
14544	/* FMUL_W */	---	14544	/* FMUL_W */	---
14545	4609,	---	14545	4609,	---
14546	/* FNEG_D32 */	---	14546	/* FNEG_D32 */	---
14547	4612,	---	14547	4612,	---
14548	/* FNEG_D32_MM */	---	14548	/* FNEG_D32_MM */	---
14549	4614,	---	14549	4614,	---
14550	/* FNEG_D64 */	---	14550	/* FNEG_D64 */	---
14551	4616,	---	14551	4616,	---
14552	/* FNEG_D64_MM */	---	14552	/* FNEG_D64_MM */	---
14553	4618,	---	14553	4618,	---
14554	/* FNEG_S */	---	14554	/* FNEG_S */	---
14555	4620,	---	14555	4620,	---
14556	/* FNEG_S_MM */	---	14556	/* FNEG_S_MM */	---
14557	4622,	---	14557	4622,	---
14558	/* FNEG_S_MMR6 */	---	14558	/* FNEG_S_MMR6 */	---
14559	4624,	---	14559	4624,	---
14560	/* FORK */	---	14560	/* FORK */	---
14561	4626,	---	14561	4626,	---
14562	/* FRCP_D */	---	14562	/* FRCP_D */	---
14563	4629,	---	14563	4629,	---
14564	/* FRCP_W */	---	14564	/* FRCP_W */	---
14565	4631,	---	14565	4631,	---
14566	/* FRINT_D */	---	14566	/* FRINT_D */	---
14567	4633,	---	14567	4633,	---
14568	/* FRINT_W */	---	14568	/* FRINT_W */	---
14569	4635,	---	14569	4635,	---
14570	/* FRSQRT_D */	---	14570	/* FRSQRT_D */	---
14571	4637,	---	14571	4637,	---
14572	/* FRSQRT_W */	---	14572	/* FRSQRT_W */	---
14573	4639,	---	14573	4639,	---
14574	/* FSAF_D */	---	14574	/* FSAF_D */	---
14575	4641,	---	14575	4641,	---
14576	/* FSAF_W */	---	14576	/* FSAF_W */	---
14577	4644,	---	14577	4644,	---
14578	/* FSEQ_D */	---	14578	/* FSEQ_D */	---
14579	4647,	---	14579	4647,	---
14580	/* FSEQ_W */	---	14580	/* FSEQ_W */	---
14581	4650,	---	14581	4650,	---
14582	/* FSLE_D */	---	14582	/* FSLE_D */	---
14583	4653,	---	14583	4653,	---
14584	/* FSLE_W */	---	14584	/* FSLE_W */	---
14585	4656,	---	14585	4656,	---
14586	/* FSLT_D */	---	14586	/* FSLT_D */	---
14587	4659,	---	14587	4659,	---
14588	/* FSLT_W */	---	14588	/* FSLT_W */	---
14589	4662,	---	14589	4662,	---
14590	/* FSNE_D */	---	14590	/* FSNE_D */	---
14591	4665,	---	14591	4665,	---
14592	/* FSNE_W */	---	14592	/* FSNE_W */	---
14593	4668,	---	14593	4668,	---
14594	/* FSOR_D */	---	14594	/* FSOR_D */	---
14595	4671,	---	14595	4671,	---
14596	/* FSOR_W */	---	14596	/* FSOR_W */	---
14597	4674,	---	14597	4674,	---
14598	/* FSQRT_D */	---	14598	/* FSQRT_D */	---
14599	4677,	---	14599	4677,	---
14600	/* FSQRT_D32 */	---	14600	/* FSQRT_D32 */	---
14601	4679,	---	14601	4679,	---
14602	/* FSQRT_D32_MM */	---	14602	/* FSQRT_D32_MM */	---
14603	4681,	---	14603	4681,	---
14604	/* FSQRT_D64 */	---	14604	/* FSQRT_D64 */	---
14605	4683,	---	14605	4683,	---
14606	/* FSQRT_D64_MM */	---	14606	/* FSQRT_D64_MM */	---
14607	4685,	---	14607	4685,	---
14608	/* FSQRT_S */	---	14608	/* FSQRT_S */	---
14609	4687,	---	14609	4687,	---
14610	/* FSQRT_S_MM */	---	14610	/* FSQRT_S_MM */	---
14611	4689,	---	14611	4689,	---
14612	/* FSQRT_W */	---	14612	/* FSQRT_W */	---
14613	4691,	---	14613	4691,	---
14614	/* FSUB_D */	---	14614	/* FSUB_D */	---
14615	4693,	---	14615	4693,	---
14616	/* FSUB_D32 */	---	14616	/* FSUB_D32 */	---
14617	4696,	---	14617	4696,	---
14618	/* FSUB_D32_MM */	---	14618	/* FSUB_D32_MM */	---
14619	4699,	---	14619	4699,	---
14620	/* FSUB_D64 */	---	14620	/* FSUB_D64 */	---
14621	4702,	---	14621	4702,	---
14622	/* FSUB_D64_MM */	---	14622	/* FSUB_D64_MM */	---
14623	4705,	---	14623	4705,	---
14624	/* FSUB_PS64 */	---	14624	/* FSUB_PS64 */	---
14625	4708,	---	14625	4708,	---
14626	/* FSUB_S */	---	14626	/* FSUB_S */	---
14627	4711,	---	14627	4711,	---
14628	/* FSUB_S_MM */	---	14628	/* FSUB_S_MM */	---
14629	4714,	---	14629	4714,	---
14630	/* FSUB_S_MMR6 */	---	14630	/* FSUB_S_MMR6 */	---
14631	4717,	---	14631	4717,	---
14632	/* FSUB_W */	---	14632	/* FSUB_W */	---
14633	4720,	---	14633	4720,	---
14634	/* FSUEQ_D */	---	14634	/* FSUEQ_D */	---
14635	4723,	---	14635	4723,	---
14636	/* FSUEQ_W */	---	14636	/* FSUEQ_W */	---
14637	4726,	---	14637	4726,	---
14638	/* FSULE_D */	---	14638	/* FSULE_D */	---
14639	4729,	---	14639	4729,	---
14640	/* FSULE_W */	---	14640	/* FSULE_W */	---
14641	4732,	---	14641	4732,	---
14642	/* FSULT_D */	---	14642	/* FSULT_D */	---
14643	4735,	---	14643	4735,	---
14644	/* FSULT_W */	---	14644	/* FSULT_W */	---
14645	4738,	---	14645	4738,	---
14646	/* FSUNE_D */	---	14646	/* FSUNE_D */	---
14647	4741,	---	14647	4741,	---
14648	/* FSUNE_W */	---	14648	/* FSUNE_W */	---
14649	4744,	---	14649	4744,	---
14650	/* FSUN_D */	---	14650	/* FSUN_D */	---
14651	4747,	---	14651	4747,	---
14652	/* FSUN_W */	---	14652	/* FSUN_W */	---
14653	4750,	---	14653	4750,	---
14654	/* FTINT_S_D */	---	14654	/* FTINT_S_D */	---
14655	4753,	---	14655	4753,	---
14656	/* FTINT_S_W */	---	14656	/* FTINT_S_W */	---
14657	4755,	---	14657	4755,	---
14658	/* FTINT_U_D */	---	14658	/* FTINT_U_D */	---
14659	4757,	---	14659	4757,	---
14660	/* FTINT_U_W */	---	14660	/* FTINT_U_W */	---
14661	4759,	---	14661	4759,	---
14662	/* FTQ_H */	---	14662	/* FTQ_H */	---
14663	4761,	---	14663	4761,	---
14664	/* FTQ_W */	---	14664	/* FTQ_W */	---
14665	4764,	---	14665	4764,	---
14666	/* FTRUNC_S_D */	---	14666	/* FTRUNC_S_D */	---
14667	4767,	---	14667	4767,	---
14668	/* FTRUNC_S_W */	---	14668	/* FTRUNC_S_W */	---
14669	4769,	---	14669	4769,	---
14670	/* FTRUNC_U_D */	---	14670	/* FTRUNC_U_D */	---
14671	4771,	---	14671	4771,	---
14672	/* FTRUNC_U_W */	---	14672	/* FTRUNC_U_W */	---
14673	4773,	---	14673	4773,	---
14674	/* GINVI */	---	14674	/* GINVI */	---
14675	4775,	---	14675	4775,	---
14676	/* GINVI_MMR6 */	---	14676	/* GINVI_MMR6 */	---
14677	4776,	---	14677	4776,	---
14678	/* GINVT */	---	14678	/* GINVT */	---
14679	4777,	---	14679	4777,	---
14680	/* GINVT_MMR6 */	---	14680	/* GINVT_MMR6 */	---
14681	4779,	---	14681	4779,	---
14682	/* HADD_S_D */	---	14682	/* HADD_S_D */	---
14683	4781,	---	14683	4781,	---
14684	/* HADD_S_H */	---	14684	/* HADD_S_H */	---
14685	4784,	---	14685	4784,	---
14686	/* HADD_S_W */	---	14686	/* HADD_S_W */	---
14687	4787,	---	14687	4787,	---
14688	/* HADD_U_D */	---	14688	/* HADD_U_D */	---
14689	4790,	---	14689	4790,	---
14690	/* HADD_U_H */	---	14690	/* HADD_U_H */	---
14691	4793,	---	14691	4793,	---
14692	/* HADD_U_W */	---	14692	/* HADD_U_W */	---
14693	4796,	---	14693	4796,	---
14694	/* HSUB_S_D */	---	14694	/* HSUB_S_D */	---
14695	4799,	---	14695	4799,	---
14696	/* HSUB_S_H */	---	14696	/* HSUB_S_H */	---
14697	4802,	---	14697	4802,	---
14698	/* HSUB_S_W */	---	14698	/* HSUB_S_W */	---
14699	4805,	---	14699	4805,	---
14700	/* HSUB_U_D */	---	14700	/* HSUB_U_D */	---
14701	4808,	---	14701	4808,	---
14702	/* HSUB_U_H */	---	14702	/* HSUB_U_H */	---
14703	4811,	---	14703	4811,	---
14704	/* HSUB_U_W */	---	14704	/* HSUB_U_W */	---
14705	4814,	---	14705	4814,	---
14706	/* HYPCALL */	---	14706	/* HYPCALL */	---
14707	4817,	---	14707	4817,	---
14708	/* HYPCALL_MM */	---	14708	/* HYPCALL_MM */	---
14709	4818,	---	14709	4818,	---
14710	/* ILVEV_B */	---	14710	/* ILVEV_B */	---
14711	4819,	---	14711	4819,	---
14712	/* ILVEV_D */	---	14712	/* ILVEV_D */	---
14713	4822,	---	14713	4822,	---
14714	/* ILVEV_H */	---	14714	/* ILVEV_H */	---
14715	4825,	---	14715	4825,	---
14716	/* ILVEV_W */	---	14716	/* ILVEV_W */	---
14717	4828,	---	14717	4828,	---
14718	/* ILVL_B */	---	14718	/* ILVL_B */	---
14719	4831,	---	14719	4831,	---
14720	/* ILVL_D */	---	14720	/* ILVL_D */	---
14721	4834,	---	14721	4834,	---
14722	/* ILVL_H */	---	14722	/* ILVL_H */	---
14723	4837,	---	14723	4837,	---
14724	/* ILVL_W */	---	14724	/* ILVL_W */	---
14725	4840,	---	14725	4840,	---
14726	/* ILVOD_B */	---	14726	/* ILVOD_B */	---
14727	4843,	---	14727	4843,	---
14728	/* ILVOD_D */	---	14728	/* ILVOD_D */	---
14729	4846,	---	14729	4846,	---
14730	/* ILVOD_H */	---	14730	/* ILVOD_H */	---
14731	4849,	---	14731	4849,	---
14732	/* ILVOD_W */	---	14732	/* ILVOD_W */	---
14733	4852,	---	14733	4852,	---
14734	/* ILVR_B */	---	14734	/* ILVR_B */	---
14735	4855,	---	14735	4855,	---
14736	/* ILVR_D */	---	14736	/* ILVR_D */	---
14737	4858,	---	14737	4858,	---
14738	/* ILVR_H */	---	14738	/* ILVR_H */	---
14739	4861,	---	14739	4861,	---
14740	/* ILVR_W */	---	14740	/* ILVR_W */	---
14741	4864,	---	14741	4864,	---
14742	/* INS */	---	14742	/* INS */	---
14743	4867,	---	14743	4867,	---
14744	/* INSERT_B */	---	14744	/* INSERT_B */	---
14745	4872,	---	14745	4872,	---
14746	/* INSERT_D */	---	14746	/* INSERT_D */	---
14747	4876,	---	14747	4876,	---
14748	/* INSERT_H */	---	14748	/* INSERT_H */	---
14749	4880,	---	14749	4880,	---
14750	/* INSERT_W */	---	14750	/* INSERT_W */	---
14751	4884,	---	14751	4884,	---
14752	/* INSV */	---	14752	/* INSV */	---
14753	4888,	---	14753	4888,	---
14754	/* INSVE_B */	---	14754	/* INSVE_B */	---
14755	4891,	---	14755	4891,	---
14756	/* INSVE_D */	---	14756	/* INSVE_D */	---
14757	4896,	---	14757	4896,	---
14758	/* INSVE_H */	---	14758	/* INSVE_H */	---
14759	4901,	---	14759	4901,	---
14760	/* INSVE_W */	---	14760	/* INSVE_W */	---
14761	4906,	---	14761	4906,	---
14762	/* INSV_MM */	---	14762	/* INSV_MM */	---
14763	4911,	---	14763	4911,	---
14764	/* INS_MM */	---	14764	/* INS_MM */	---
14765	4914,	---	14765	4914,	---
14766	/* INS_MMR6 */	---	14766	/* INS_MMR6 */	---
14767	4919,	---	14767	4919,	---
14768	/* J */	---	14768	/* J */	---
14769	4924,	---	14769	4924,	---
14770	/* JAL */	---	14770	/* JAL */	---
14771	4925,	---	14771	4925,	---
14772	/* JALR */	---	14772	/* JALR */	---
14773	4926,	---	14773	4926,	---
14774	/* JALR16_MM */	---	14774	/* JALR16_MM */	---
14775	4928,	---	14775	4928,	---
14776	/* JALR64 */	---	14776	/* JALR64 */	---
14777	4929,	---	14777	4929,	---
14778	/* JALRC16_MMR6 */	---	14778	/* JALRC16_MMR6 */	---
14779	4931,	---	14779	4931,	---
14780	/* JALRC_HB_MMR6 */	---	14780	/* JALRC_HB_MMR6 */	---
14781	4932,	---	14781	4932,	---
14782	/* JALRC_MMR6 */	---	14782	/* JALRC_MMR6 */	---
14783	4934,	---	14783	4934,	---
14784	/* JALRS16_MM */	---	14784	/* JALRS16_MM */	---
14785	4936,	---	14785	4936,	---
14786	/* JALRS_MM */	---	14786	/* JALRS_MM */	---
14787	4937,	---	14787	4937,	---
14788	/* JALR_HB */	---	14788	/* JALR_HB */	---
14789	4939,	---	14789	4939,	---
14790	/* JALR_HB64 */	---	14790	/* JALR_HB64 */	---
14791	4941,	---	14791	4941,	---
14792	/* JALR_MM */	---	14792	/* JALR_MM */	---
14793	4943,	---	14793	4943,	---
14794	/* JALS_MM */	---	14794	/* JALS_MM */	---
14795	4945,	---	14795	4945,	---
14796	/* JALX */	---	14796	/* JALX */	---
14797	4946,	---	14797	4946,	---
14798	/* JALX_MM */	---	14798	/* JALX_MM */	---
14799	4947,	---	14799	4947,	---
14800	/* JAL_MM */	---	14800	/* JAL_MM */	---
14801	4948,	---	14801	4948,	---
14802	/* JIALC */	---	14802	/* JIALC */	---
14803	4949,	---	14803	4949,	---
14804	/* JIALC64 */	---	14804	/* JIALC64 */	---
14805	4951,	---	14805	4951,	---
14806	/* JIALC_MMR6 */	---	14806	/* JIALC_MMR6 */	---
14807	4953,	---	14807	4953,	---
14808	/* JIC */	---	14808	/* JIC */	---
14809	4955,	---	14809	4955,	---
14810	/* JIC64 */	---	14810	/* JIC64 */	---
14811	4957,	---	14811	4957,	---
14812	/* JIC_MMR6 */	---	14812	/* JIC_MMR6 */	---
14813	4959,	---	14813	4959,	---
14814	/* JR */	---	14814	/* JR */	---
14815	4961,	---	14815	4961,	---
14816	/* JR16_MM */	---	14816	/* JR16_MM */	---
14817	4962,	---	14817	4962,	---
14818	/* JR64 */	---	14818	/* JR64 */	---
14819	4963,	---	14819	4963,	---
14820	/* JRADDIUSP */	---	14820	/* JRADDIUSP */	---
14821	4964,	---	14821	4964,	---
14822	/* JRC16_MM */	---	14822	/* JRC16_MM */	---
14823	4965,	---	14823	4965,	---
14824	/* JRC16_MMR6 */	---	14824	/* JRC16_MMR6 */	---
14825	4966,	---	14825	4966,	---
14826	/* JRCADDIUSP_MMR6 */	---	14826	/* JRCADDIUSP_MMR6 */	---
14827	4967,	---	14827	4967,	---
14828	/* JR_HB */	---	14828	/* JR_HB */	---
14829	4968,	---	14829	4968,	---
14830	/* JR_HB64 */	---	14830	/* JR_HB64 */	---
14831	4969,	---	14831	4969,	---
14832	/* JR_HB64_R6 */	---	14832	/* JR_HB64_R6 */	---
14833	4970,	---	14833	4970,	---
14834	/* JR_HB_R6 */	---	14834	/* JR_HB_R6 */	---
14835	4971,	---	14835	4971,	---
14836	/* JR_MM */	---	14836	/* JR_MM */	---
14837	4972,	---	14837	4972,	---
14838	/* J_MM */	---	14838	/* J_MM */	---
14839	4973,	---	14839	4973,	---
14840	/* Jal16 */	---	14840	/* Jal16 */	---
14841	4974,	---	14841	4974,	---
14842	/* JalB16 */	---	14842	/* JalB16 */	---
14843	4975,	---	14843	4975,	---
14844	/* JrRa16 */	---	14844	/* JrRa16 */	---
14845	4976,	---	14845	4976,	---
14846	/* JrcRa16 */	---	14846	/* JrcRa16 */	---
14847	4976,	---	14847	4976,	---
14848	/* JrcRx16 */	---	14848	/* JrcRx16 */	---
14849	4976,	---	14849	4976,	---
14850	/* JumpLinkReg16 */	---	14850	/* JumpLinkReg16 */	---
14851	4977,	---	14851	4977,	---
14852	/* LB */	---	14852	/* LB */	---
14853	4978,	---	14853	4978,	---
14854	/* LB64 */	---	14854	/* LB64 */	---
14855	4981,	---	14855	4981,	---
14856	/* LBE */	---	14856	/* LBE */	---
14857	4984,	---	14857	4984,	---
14858	/* LBE_MM */	---	14858	/* LBE_MM */	---
14859	4987,	---	14859	4987,	---
14860	/* LBU16_MM */	---	14860	/* LBU16_MM */	---
14861	4990,	---	14861	4990,	---
14862	/* LBUX */	---	14862	/* LBUX */	---
14863	4993,	---	14863	4993,	---
14864	/* LBUX_MM */	---	14864	/* LBUX_MM */	---
14865	4996,	---	14865	4996,	---
14866	/* LBU_MMR6 */	---	14866	/* LBU_MMR6 */	---
14867	4999,	---	14867	4999,	---
14868	/* LB_MM */	---	14868	/* LB_MM */	---
14869	5002,	---	14869	5002,	---
14870	/* LB_MMR6 */	---	14870	/* LB_MMR6 */	---
14871	5005,	---	14871	5005,	---
14872	/* LBu */	---	14872	/* LBu */	---
14873	5008,	---	14873	5008,	---
14874	/* LBu64 */	---	14874	/* LBu64 */	---
14875	5011,	---	14875	5011,	---
14876	/* LBuE */	---	14876	/* LBuE */	---
14877	5014,	---	14877	5014,	---
14878	/* LBuE_MM */	---	14878	/* LBuE_MM */	---
14879	5017,	---	14879	5017,	---
14880	/* LBu_MM */	---	14880	/* LBu_MM */	---
14881	5020,	---	14881	5020,	---
14882	/* LD */	---	14882	/* LD */	---
14883	5023,	---	14883	5023,	---
14884	/* LDC1 */	---	14884	/* LDC1 */	---
14885	5026,	---	14885	5026,	---
14886	/* LDC164 */	---	14886	/* LDC164 */	---
14887	5029,	---	14887	5029,	---
14888	/* LDC1_D64_MMR6 */	---	14888	/* LDC1_D64_MMR6 */	---
14889	5032,	---	14889	5032,	---
14890	/* LDC1_MM_D32 */	---	14890	/* LDC1_MM_D32 */	---
14891	5035,	---	14891	5035,	---
14892	/* LDC1_MM_D64 */	---	14892	/* LDC1_MM_D64 */	---
14893	5038,	---	14893	5038,	---
14894	/* LDC2 */	---	14894	/* LDC2 */	---
14895	5041,	---	14895	5041,	---
14896	/* LDC2_MMR6 */	---	14896	/* LDC2_MMR6 */	---
14897	5044,	---	14897	5044,	---
14898	/* LDC2_R6 */	---	14898	/* LDC2_R6 */	---
14899	5047,	---	14899	5047,	---
14900	/* LDC3 */	---	14900	/* LDC3 */	---
14901	5050,	---	14901	5050,	---
14902	/* LDI_B */	---	14902	/* LDI_B */	---
14903	5053,	---	14903	5053,	---
14904	/* LDI_D */	---	14904	/* LDI_D */	---
14905	5055,	---	14905	5055,	---
14906	/* LDI_H */	---	14906	/* LDI_H */	---
14907	5057,	---	14907	5057,	---
14908	/* LDI_W */	---	14908	/* LDI_W */	---
14909	5059,	---	14909	5059,	---
14910	/* LDL */	---	14910	/* LDL */	---
14911	5061,	---	14911	5061,	---
14912	/* LDPC */	---	14912	/* LDPC */	---
14913	5065,	---	14913	5065,	---
14914	/* LDR */	---	14914	/* LDR */	---
14915	5067,	---	14915	5067,	---
14916	/* LDXC1 */	---	14916	/* LDXC1 */	---
14917	5071,	---	14917	5071,	---
14918	/* LDXC164 */	---	14918	/* LDXC164 */	---
14919	5074,	---	14919	5074,	---
14920	/* LD_B */	---	14920	/* LD_B */	---
14921	5077,	---	14921	5077,	---
14922	/* LD_D */	---	14922	/* LD_D */	---
14923	5080,	---	14923	5080,	---
14924	/* LD_H */	---	14924	/* LD_H */	---
14925	5083,	---	14925	5083,	---
14926	/* LD_W */	---	14926	/* LD_W */	---
14927	5086,	---	14927	5086,	---
14928	/* LEA_ADDiu */	---	14928	/* LEA_ADDiu */	---
14929	5089,	---	14929	5089,	---
14930	/* LEA_ADDiu64 */	---	14930	/* LEA_ADDiu64 */	---
14931	5092,	---	14931	5092,	---
14932	/* LEA_ADDiu_MM */	---	14932	/* LEA_ADDiu_MM */	---
14933	5095,	---	14933	5095,	---
14934	/* LH */	---	14934	/* LH */	---
14935	5098,	---	14935	5098,	---
14936	/* LH64 */	---	14936	/* LH64 */	---
14937	5101,	---	14937	5101,	---
14938	/* LHE */	---	14938	/* LHE */	---
14939	5104,	---	14939	5104,	---
14940	/* LHE_MM */	---	14940	/* LHE_MM */	---
14941	5107,	---	14941	5107,	---
14942	/* LHU16_MM */	---	14942	/* LHU16_MM */	---
14943	5110,	---	14943	5110,	---
14944	/* LHX */	---	14944	/* LHX */	---
14945	5113,	---	14945	5113,	---
14946	/* LHX_MM */	---	14946	/* LHX_MM */	---
14947	5116,	---	14947	5116,	---
14948	/* LH_MM */	---	14948	/* LH_MM */	---
14949	5119,	---	14949	5119,	---
14950	/* LHu */	---	14950	/* LHu */	---
14951	5122,	---	14951	5122,	---
14952	/* LHu64 */	---	14952	/* LHu64 */	---
14953	5125,	---	14953	5125,	---
14954	/* LHuE */	---	14954	/* LHuE */	---
14955	5128,	---	14955	5128,	---
14956	/* LHuE_MM */	---	14956	/* LHuE_MM */	---
14957	5131,	---	14957	5131,	---
14958	/* LHu_MM */	---	14958	/* LHu_MM */	---
14959	5134,	---	14959	5134,	---
14960	/* LI16_MM */	---	14960	/* LI16_MM */	---
14961	5137,	---	14961	5137,	---
14962	/* LI16_MMR6 */	---	14962	/* LI16_MMR6 */	---
14963	5139,	---	14963	5139,	---
14964	/* LL */	---	14964	/* LL */	---
14965	5141,	---	14965	5141,	---
14966	/* LL64 */	---	14966	/* LL64 */	---
14967	5144,	---	14967	5144,	---
14968	/* LL64_R6 */	---	14968	/* LL64_R6 */	---
14969	5147,	---	14969	5147,	---
14970	/* LLD */	---	14970	/* LLD */	---
14971	5150,	---	14971	5150,	---
14972	/* LLD_R6 */	---	14972	/* LLD_R6 */	---
14973	5153,	---	14973	5153,	---
14974	/* LLE */	---	14974	/* LLE */	---
14975	5156,	---	14975	5156,	---
14976	/* LLE_MM */	---	14976	/* LLE_MM */	---
14977	5159,	---	14977	5159,	---
14978	/* LL_MM */	---	14978	/* LL_MM */	---
14979	5162,	---	14979	5162,	---
14980	/* LL_MMR6 */	---	14980	/* LL_MMR6 */	---
14981	5165,	---	14981	5165,	---
14982	/* LL_R6 */	---	14982	/* LL_R6 */	---
14983	5168,	---	14983	5168,	---
14984	/* LSA */	---	14984	/* LSA */	---
14985	5171,	---	14985	5171,	---
14986	/* LSA_MMR6 */	---	14986	/* LSA_MMR6 */	---
14987	5175,	---	14987	5175,	---
14988	/* LSA_R6 */	---	14988	/* LSA_R6 */	---
14989	5179,	---	14989	5179,	---
14990	/* LUI_MMR6 */	---	14990	/* LUI_MMR6 */	---
14991	5183,	---	14991	5183,	---
14992	/* LUXC1 */	---	14992	/* LUXC1 */	---
14993	5185,	---	14993	5185,	---
14994	/* LUXC164 */	---	14994	/* LUXC164 */	---
14995	5188,	---	14995	5188,	---
14996	/* LUXC1_MM */	---	14996	/* LUXC1_MM */	---
14997	5191,	---	14997	5191,	---
14998	/* LUi */	---	14998	/* LUi */	---
14999	5194,	---	14999	5194,	---
15000	/* LUi64 */	---	15000	/* LUi64 */	---
15001	5196,	---	15001	5196,	---
15002	/* LUi_MM */	---	15002	/* LUi_MM */	---
15003	5198,	---	15003	5198,	---
15004	/* LW */	---	15004	/* LW */	---
15005	5200,	---	15005	5200,	---
15006	/* LW16_MM */	---	15006	/* LW16_MM */	---
15007	5203,	---	15007	5203,	---
15008	/* LW64 */	---	15008	/* LW64 */	---
15009	5206,	---	15009	5206,	---
15010	/* LWC1 */	---	15010	/* LWC1 */	---
15011	5209,	---	15011	5209,	---
15012	/* LWC1_MM */	---	15012	/* LWC1_MM */	---
15013	5212,	---	15013	5212,	---
15014	/* LWC2 */	---	15014	/* LWC2 */	---
15015	5215,	---	15015	5215,	---
15016	/* LWC2_MMR6 */	---	15016	/* LWC2_MMR6 */	---
15017	5218,	---	15017	5218,	---
15018	/* LWC2_R6 */	---	15018	/* LWC2_R6 */	---
15019	5221,	---	15019	5221,	---
15020	/* LWC3 */	---	15020	/* LWC3 */	---
15021	5224,	---	15021	5224,	---
15022	/* LWDSP */	---	15022	/* LWDSP */	---
15023	5227,	---	15023	5227,	---
15024	/* LWDSP_MM */	---	15024	/* LWDSP_MM */	---
15025	5230,	---	15025	5230,	---
15026	/* LWE */	---	15026	/* LWE */	---
15027	5233,	---	15027	5233,	---
15028	/* LWE_MM */	---	15028	/* LWE_MM */	---
15029	5236,	---	15029	5236,	---
15030	/* LWGP_MM */	---	15030	/* LWGP_MM */	---
15031	5239,	---	15031	5239,	---
15032	/* LWL */	---	15032	/* LWL */	---
15033	5242,	---	15033	5242,	---
15034	/* LWL64 */	---	15034	/* LWL64 */	---
15035	5246,	---	15035	5246,	---
15036	/* LWLE */	---	15036	/* LWLE */	---
15037	5250,	---	15037	5250,	---
15038	/* LWLE_MM */	---	15038	/* LWLE_MM */	---
15039	5254,	---	15039	5254,	---
15040	/* LWL_MM */	---	15040	/* LWL_MM */	---
15041	5258,	---	15041	5258,	---
15042	/* LWM16_MM */	---	15042	/* LWM16_MM */	---
15043	5262,	---	15043	5262,	---
15044	/* LWM16_MMR6 */	---	15044	/* LWM16_MMR6 */	---
15045	5265,	---	15045	5265,	---
15046	/* LWM32_MM */	---	15046	/* LWM32_MM */	---
15047	5268,	---	15047	5268,	---
15048	/* LWPC */	---	15048	/* LWPC */	---
15049	5271,	---	15049	5271,	---
15050	/* LWPC_MMR6 */	---	15050	/* LWPC_MMR6 */	---
15051	5273,	---	15051	5273,	---
15052	/* LWP_MM */	---	15052	/* LWP_MM */	---
15053	5275,	---	15053	5275,	---
15054	/* LWR */	---	15054	/* LWR */	---
15055	5279,	---	15055	5279,	---
15056	/* LWR64 */	---	15056	/* LWR64 */	---
15057	5283,	---	15057	5283,	---
15058	/* LWRE */	---	15058	/* LWRE */	---
15059	5287,	---	15059	5287,	---
15060	/* LWRE_MM */	---	15060	/* LWRE_MM */	---
15061	5291,	---	15061	5291,	---
15062	/* LWR_MM */	---	15062	/* LWR_MM */	---
15063	5295,	---	15063	5295,	---
15064	/* LWSP_MM */	---	15064	/* LWSP_MM */	---
15065	5299,	---	15065	5299,	---
15066	/* LWUPC */	---	15066	/* LWUPC */	---
15067	5302,	---	15067	5302,	---
15068	/* LWU_MM */	---	15068	/* LWU_MM */	---
15069	5304,	---	15069	5304,	---
15070	/* LWX */	---	15070	/* LWX */	---
15071	5307,	---	15071	5307,	---
15072	/* LWXC1 */	---	15072	/* LWXC1 */	---
15073	5310,	---	15073	5310,	---
15074	/* LWXC1_MM */	---	15074	/* LWXC1_MM */	---
15075	5313,	---	15075	5313,	---
15076	/* LWXS_MM */	---	15076	/* LWXS_MM */	---
15077	5316,	---	15077	5316,	---
15078	/* LWX_MM */	---	15078	/* LWX_MM */	---
15079	5319,	---	15079	5319,	---
15080	/* LW_MM */	---	15080	/* LW_MM */	---
15081	5322,	---	15081	5322,	---
15082	/* LW_MMR6 */	---	15082	/* LW_MMR6 */	---
15083	5325,	---	15083	5325,	---
15084	/* LWu */	---	15084	/* LWu */	---
15085	5328,	---	15085	5328,	---
15086	/* LbRxRyOffMemX16 */	---	15086	/* LbRxRyOffMemX16 */	---
15087	5331,	---	15087	5331,	---
15088	/* LbuRxRyOffMemX16 */	---	15088	/* LbuRxRyOffMemX16 */	---
15089	5334,	---	15089	5334,	---
15090	/* LhRxRyOffMemX16 */	---	15090	/* LhRxRyOffMemX16 */	---
15091	5337,	---	15091	5337,	---
15092	/* LhuRxRyOffMemX16 */	---	15092	/* LhuRxRyOffMemX16 */	---
15093	5340,	---	15093	5340,	---
15094	/* LiRxImm16 */	---	15094	/* LiRxImm16 */	---
15095	5343,	---	15095	5343,	---
15096	/* LiRxImmAlignX16 */	---	15096	/* LiRxImmAlignX16 */	---
15097	5345,	---	15097	5345,	---
15098	/* LiRxImmX16 */	---	15098	/* LiRxImmX16 */	---
15099	5347,	---	15099	5347,	---
15100	/* LwRxPcTcp16 */	---	15100	/* LwRxPcTcp16 */	---
15101	5349,	---	15101	5349,	---
15102	/* LwRxPcTcpX16 */	---	15102	/* LwRxPcTcpX16 */	---
15103	5352,	---	15103	5352,	---
15104	/* LwRxRyOffMemX16 */	---	15104	/* LwRxRyOffMemX16 */	---
15105	5355,	---	15105	5355,	---
15106	/* LwRxSpImmX16 */	---	15106	/* LwRxSpImmX16 */	---
15107	5358,	---	15107	5358,	---
15108	/* MADD */	---	15108	/* MADD */	---
15109	5361,	---	15109	5361,	---
15110	/* MADDF_D */	---	15110	/* MADDF_D */	---
15111	5363,	---	15111	5363,	---
15112	/* MADDF_D_MMR6 */	---	15112	/* MADDF_D_MMR6 */	---
15113	5367,	---	15113	5367,	---
15114	/* MADDF_S */	---	15114	/* MADDF_S */	---
15115	5371,	---	15115	5371,	---
15116	/* MADDF_S_MMR6 */	---	15116	/* MADDF_S_MMR6 */	---
15117	5375,	---	15117	5375,	---
15118	/* MADDR_Q_H */	---	15118	/* MADDR_Q_H */	---
15119	5379,	---	15119	5379,	---
15120	/* MADDR_Q_W */	---	15120	/* MADDR_Q_W */	---
15121	5383,	---	15121	5383,	---
15122	/* MADDU */	---	15122	/* MADDU */	---
15123	5387,	---	15123	5387,	---
15124	/* MADDU_DSP */	---	15124	/* MADDU_DSP */	---
15125	5389,	---	15125	5389,	---
15126	/* MADDU_DSP_MM */	---	15126	/* MADDU_DSP_MM */	---
15127	5393,	---	15127	5393,	---
15128	/* MADDU_MM */	---	15128	/* MADDU_MM */	---
15129	5397,	---	15129	5397,	---
15130	/* MADDV_B */	---	15130	/* MADDV_B */	---
15131	5399,	---	15131	5399,	---
15132	/* MADDV_D */	---	15132	/* MADDV_D */	---
15133	5403,	---	15133	5403,	---
15134	/* MADDV_H */	---	15134	/* MADDV_H */	---
15135	5407,	---	15135	5407,	---
15136	/* MADDV_W */	---	15136	/* MADDV_W */	---
15137	5411,	---	15137	5411,	---
15138	/* MADD_D32 */	---	15138	/* MADD_D32 */	---
15139	5415,	---	15139	5415,	---
15140	/* MADD_D32_MM */	---	15140	/* MADD_D32_MM */	---
15141	5419,	---	15141	5419,	---
15142	/* MADD_D64 */	---	15142	/* MADD_D64 */	---
15143	5423,	---	15143	5423,	---
15144	/* MADD_DSP */	---	15144	/* MADD_DSP */	---
15145	5427,	---	15145	5427,	---
15146	/* MADD_DSP_MM */	---	15146	/* MADD_DSP_MM */	---
15147	5431,	---	15147	5431,	---
15148	/* MADD_MM */	---	15148	/* MADD_MM */	---
15149	5435,	---	15149	5435,	---
15150	/* MADD_Q_H */	---	15150	/* MADD_Q_H */	---
15151	5437,	---	15151	5437,	---
15152	/* MADD_Q_W */	---	15152	/* MADD_Q_W */	---
15153	5441,	---	15153	5441,	---
15154	/* MADD_S */	---	15154	/* MADD_S */	---
15155	5445,	---	15155	5445,	---
15156	/* MADD_S_MM */	---	15156	/* MADD_S_MM */	---
15157	5449,	---	15157	5449,	---
15158	/* MAQ_SA_W_PHL */	---	15158	/* MAQ_SA_W_PHL */	---
15159	5453,	---	15159	5453,	---
15160	/* MAQ_SA_W_PHL_MM */	---	15160	/* MAQ_SA_W_PHL_MM */	---
15161	5457,	---	15161	5457,	---
15162	/* MAQ_SA_W_PHR */	---	15162	/* MAQ_SA_W_PHR */	---
15163	5461,	---	15163	5461,	---
15164	/* MAQ_SA_W_PHR_MM */	---	15164	/* MAQ_SA_W_PHR_MM */	---
15165	5465,	---	15165	5465,	---
15166	/* MAQ_S_W_PHL */	---	15166	/* MAQ_S_W_PHL */	---
15167	5469,	---	15167	5469,	---
15168	/* MAQ_S_W_PHL_MM */	---	15168	/* MAQ_S_W_PHL_MM */	---
15169	5473,	---	15169	5473,	---
15170	/* MAQ_S_W_PHR */	---	15170	/* MAQ_S_W_PHR */	---
15171	5477,	---	15171	5477,	---
15172	/* MAQ_S_W_PHR_MM */	---	15172	/* MAQ_S_W_PHR_MM */	---
15173	5481,	---	15173	5481,	---
15174	/* MAXA_D */	---	15174	/* MAXA_D */	---
15175	5485,	---	15175	5485,	---
15176	/* MAXA_D_MMR6 */	---	15176	/* MAXA_D_MMR6 */	---
15177	5488,	---	15177	5488,	---
15178	/* MAXA_S */	---	15178	/* MAXA_S */	---
15179	5491,	---	15179	5491,	---
15180	/* MAXA_S_MMR6 */	---	15180	/* MAXA_S_MMR6 */	---
15181	5494,	---	15181	5494,	---
15182	/* MAXI_S_B */	---	15182	/* MAXI_S_B */	---
15183	5497,	---	15183	5497,	---
15184	/* MAXI_S_D */	---	15184	/* MAXI_S_D */	---
15185	5500,	---	15185	5500,	---
15186	/* MAXI_S_H */	---	15186	/* MAXI_S_H */	---
15187	5503,	---	15187	5503,	---
15188	/* MAXI_S_W */	---	15188	/* MAXI_S_W */	---
15189	5506,	---	15189	5506,	---
15190	/* MAXI_U_B */	---	15190	/* MAXI_U_B */	---
15191	5509,	---	15191	5509,	---
15192	/* MAXI_U_D */	---	15192	/* MAXI_U_D */	---
15193	5512,	---	15193	5512,	---
15194	/* MAXI_U_H */	---	15194	/* MAXI_U_H */	---
15195	5515,	---	15195	5515,	---
15196	/* MAXI_U_W */	---	15196	/* MAXI_U_W */	---
15197	5518,	---	15197	5518,	---
15198	/* MAX_A_B */	---	15198	/* MAX_A_B */	---
15199	5521,	---	15199	5521,	---
15200	/* MAX_A_D */	---	15200	/* MAX_A_D */	---
15201	5524,	---	15201	5524,	---
15202	/* MAX_A_H */	---	15202	/* MAX_A_H */	---
15203	5527,	---	15203	5527,	---
15204	/* MAX_A_W */	---	15204	/* MAX_A_W */	---
15205	5530,	---	15205	5530,	---
15206	/* MAX_D */	---	15206	/* MAX_D */	---
15207	5533,	---	15207	5533,	---
15208	/* MAX_D_MMR6 */	---	15208	/* MAX_D_MMR6 */	---
15209	5536,	---	15209	5536,	---
15210	/* MAX_S */	---	15210	/* MAX_S */	---
15211	5539,	---	15211	5539,	---
15212	/* MAX_S_B */	---	15212	/* MAX_S_B */	---
15213	5542,	---	15213	5542,	---
15214	/* MAX_S_D */	---	15214	/* MAX_S_D */	---
15215	5545,	---	15215	5545,	---
15216	/* MAX_S_H */	---	15216	/* MAX_S_H */	---
15217	5548,	---	15217	5548,	---
15218	/* MAX_S_MMR6 */	---	15218	/* MAX_S_MMR6 */	---
15219	5551,	---	15219	5551,	---
15220	/* MAX_S_W */	---	15220	/* MAX_S_W */	---
15221	5554,	---	15221	5554,	---
15222	/* MAX_U_B */	---	15222	/* MAX_U_B */	---
15223	5557,	---	15223	5557,	---
15224	/* MAX_U_D */	---	15224	/* MAX_U_D */	---
15225	5560,	---	15225	5560,	---
15226	/* MAX_U_H */	---	15226	/* MAX_U_H */	---
15227	5563,	---	15227	5563,	---
15228	/* MAX_U_W */	---	15228	/* MAX_U_W */	---
15229	5566,	---	15229	5566,	---
15230	/* MFC0 */	---	15230	/* MFC0 */	---
15231	5569,	---	15231	5569,	---
15232	/* MFC0_MMR6 */	---	15232	/* MFC0_MMR6 */	---
15233	5572,	---	15233	5572,	---
15234	/* MFC1 */	---	15234	/* MFC1 */	---
15235	5575,	---	15235	5575,	---
15236	/* MFC1_D64 */	---	15236	/* MFC1_D64 */	---
15237	5577,	---	15237	5577,	---
15238	/* MFC1_MM */	---	15238	/* MFC1_MM */	---
15239	5579,	---	15239	5579,	---
15240	/* MFC1_MMR6 */	---	15240	/* MFC1_MMR6 */	---
15241	5581,	---	15241	5581,	---
15242	/* MFC2 */	---	15242	/* MFC2 */	---
15243	5583,	---	15243	5583,	---
15244	/* MFC2_MMR6 */	---	15244	/* MFC2_MMR6 */	---
15245	5586,	---	15245	5586,	---
15246	/* MFGC0 */	---	15246	/* MFGC0 */	---
15247	5588,	---	15247	5588,	---
15248	/* MFGC0_MM */	---	15248	/* MFGC0_MM */	---
15249	5591,	---	15249	5591,	---
15250	/* MFHC0_MMR6 */	---	15250	/* MFHC0_MMR6 */	---
15251	5594,	---	15251	5594,	---
15252	/* MFHC1_D32 */	---	15252	/* MFHC1_D32 */	---
15253	5597,	---	15253	5597,	---
15254	/* MFHC1_D32_MM */	---	15254	/* MFHC1_D32_MM */	---
15255	5599,	---	15255	5599,	---
15256	/* MFHC1_D64 */	---	15256	/* MFHC1_D64 */	---
15257	5601,	---	15257	5601,	---
15258	/* MFHC1_D64_MM */	---	15258	/* MFHC1_D64_MM */	---
15259	5603,	---	15259	5603,	---
15260	/* MFHC2_MMR6 */	---	15260	/* MFHC2_MMR6 */	---
15261	5605,	---	15261	5605,	---
15262	/* MFHGC0 */	---	15262	/* MFHGC0 */	---
15263	5607,	---	15263	5607,	---
15264	/* MFHGC0_MM */	---	15264	/* MFHGC0_MM */	---
15265	5610,	---	15265	5610,	---
15266	/* MFHI */	---	15266	/* MFHI */	---
15267	5613,	---	15267	5613,	---
15268	/* MFHI16_MM */	---	15268	/* MFHI16_MM */	---
15269	5614,	---	15269	5614,	---
15270	/* MFHI64 */	---	15270	/* MFHI64 */	---
15271	5615,	---	15271	5615,	---
15272	/* MFHI_DSP */	---	15272	/* MFHI_DSP */	---
15273	5616,	---	15273	5616,	---
15274	/* MFHI_DSP_MM */	---	15274	/* MFHI_DSP_MM */	---
15275	5618,	---	15275	5618,	---
15276	/* MFHI_MM */	---	15276	/* MFHI_MM */	---
15277	5620,	---	15277	5620,	---
15278	/* MFLO */	---	15278	/* MFLO */	---
15279	5621,	---	15279	5621,	---
15280	/* MFLO16_MM */	---	15280	/* MFLO16_MM */	---
15281	5622,	---	15281	5622,	---
15282	/* MFLO64 */	---	15282	/* MFLO64 */	---
15283	5623,	---	15283	5623,	---
15284	/* MFLO_DSP */	---	15284	/* MFLO_DSP */	---
15285	5624,	---	15285	5624,	---
15286	/* MFLO_DSP_MM */	---	15286	/* MFLO_DSP_MM */	---
15287	5626,	---	15287	5626,	---
15288	/* MFLO_MM */	---	15288	/* MFLO_MM */	---
15289	5628,	---	15289	5628,	---
15290	/* MFTR */	---	15290	/* MFTR */	---
15291	5629,	---	15291	5629,	---
15292	/* MINA_D */	---	15292	/* MINA_D */	---
15293	5634,	---	15293	5634,	---
15294	/* MINA_D_MMR6 */	---	15294	/* MINA_D_MMR6 */	---
15295	5637,	---	15295	5637,	---
15296	/* MINA_S */	---	15296	/* MINA_S */	---
15297	5640,	---	15297	5640,	---
15298	/* MINA_S_MMR6 */	---	15298	/* MINA_S_MMR6 */	---
15299	5643,	---	15299	5643,	---
15300	/* MINI_S_B */	---	15300	/* MINI_S_B */	---
15301	5646,	---	15301	5646,	---
15302	/* MINI_S_D */	---	15302	/* MINI_S_D */	---
15303	5649,	---	15303	5649,	---
15304	/* MINI_S_H */	---	15304	/* MINI_S_H */	---
15305	5652,	---	15305	5652,	---
15306	/* MINI_S_W */	---	15306	/* MINI_S_W */	---
15307	5655,	---	15307	5655,	---
15308	/* MINI_U_B */	---	15308	/* MINI_U_B */	---
15309	5658,	---	15309	5658,	---
15310	/* MINI_U_D */	---	15310	/* MINI_U_D */	---
15311	5661,	---	15311	5661,	---
15312	/* MINI_U_H */	---	15312	/* MINI_U_H */	---
15313	5664,	---	15313	5664,	---
15314	/* MINI_U_W */	---	15314	/* MINI_U_W */	---
15315	5667,	---	15315	5667,	---
15316	/* MIN_A_B */	---	15316	/* MIN_A_B */	---
15317	5670,	---	15317	5670,	---
15318	/* MIN_A_D */	---	15318	/* MIN_A_D */	---
15319	5673,	---	15319	5673,	---
15320	/* MIN_A_H */	---	15320	/* MIN_A_H */	---
15321	5676,	---	15321	5676,	---
15322	/* MIN_A_W */	---	15322	/* MIN_A_W */	---
15323	5679,	---	15323	5679,	---
15324	/* MIN_D */	---	15324	/* MIN_D */	---
15325	5682,	---	15325	5682,	---
15326	/* MIN_D_MMR6 */	---	15326	/* MIN_D_MMR6 */	---
15327	5685,	---	15327	5685,	---
15328	/* MIN_S */	---	15328	/* MIN_S */	---
15329	5688,	---	15329	5688,	---
15330	/* MIN_S_B */	---	15330	/* MIN_S_B */	---
15331	5691,	---	15331	5691,	---
15332	/* MIN_S_D */	---	15332	/* MIN_S_D */	---
15333	5694,	---	15333	5694,	---
15334	/* MIN_S_H */	---	15334	/* MIN_S_H */	---
15335	5697,	---	15335	5697,	---
15336	/* MIN_S_MMR6 */	---	15336	/* MIN_S_MMR6 */	---
15337	5700,	---	15337	5700,	---
15338	/* MIN_S_W */	---	15338	/* MIN_S_W */	---
15339	5703,	---	15339	5703,	---
15340	/* MIN_U_B */	---	15340	/* MIN_U_B */	---
15341	5706,	---	15341	5706,	---
15342	/* MIN_U_D */	---	15342	/* MIN_U_D */	---
15343	5709,	---	15343	5709,	---
15344	/* MIN_U_H */	---	15344	/* MIN_U_H */	---
15345	5712,	---	15345	5712,	---
15346	/* MIN_U_W */	---	15346	/* MIN_U_W */	---
15347	5715,	---	15347	5715,	---
15348	/* MOD */	---	15348	/* MOD */	---
15349	5718,	---	15349	5718,	---
15350	/* MODSUB */	---	15350	/* MODSUB */	---
15351	5721,	---	15351	5721,	---
15352	/* MODSUB_MM */	---	15352	/* MODSUB_MM */	---
15353	5724,	---	15353	5724,	---
15354	/* MODU */	---	15354	/* MODU */	---
15355	5727,	---	15355	5727,	---
15356	/* MODU_MMR6 */	---	15356	/* MODU_MMR6 */	---
15357	5730,	---	15357	5730,	---
15358	/* MOD_MMR6 */	---	15358	/* MOD_MMR6 */	---
15359	5733,	---	15359	5733,	---
15360	/* MOD_S_B */	---	15360	/* MOD_S_B */	---
15361	5736,	---	15361	5736,	---
15362	/* MOD_S_D */	---	15362	/* MOD_S_D */	---
15363	5739,	---	15363	5739,	---
15364	/* MOD_S_H */	---	15364	/* MOD_S_H */	---
15365	5742,	---	15365	5742,	---
15366	/* MOD_S_W */	---	15366	/* MOD_S_W */	---
15367	5745,	---	15367	5745,	---
15368	/* MOD_U_B */	---	15368	/* MOD_U_B */	---
15369	5748,	---	15369	5748,	---
15370	/* MOD_U_D */	---	15370	/* MOD_U_D */	---
15371	5751,	---	15371	5751,	---
15372	/* MOD_U_H */	---	15372	/* MOD_U_H */	---
15373	5754,	---	15373	5754,	---
15374	/* MOD_U_W */	---	15374	/* MOD_U_W */	---
15375	5757,	---	15375	5757,	---
15376	/* MOVE16_MM */	---	15376	/* MOVE16_MM */	---
15377	5760,	---	15377	5760,	---
15378	/* MOVE16_MMR6 */	---	15378	/* MOVE16_MMR6 */	---
15379	5762,	---	15379	5762,	---
15380	/* MOVEP_MM */	---	15380	/* MOVEP_MM */	---
15381	5764,	---	15381	5764,	---
15382	/* MOVEP_MMR6 */	---	15382	/* MOVEP_MMR6 */	---
15383	5768,	---	15383	5768,	---
15384	/* MOVE_V */	---	15384	/* MOVE_V */	---
15385	5772,	---	15385	5772,	---
15386	/* MOVF_D32 */	---	15386	/* MOVF_D32 */	---
15387	5774,	---	15387	5774,	---
15388	/* MOVF_D32_MM */	---	15388	/* MOVF_D32_MM */	---
15389	5778,	---	15389	5778,	---
15390	/* MOVF_D64 */	---	15390	/* MOVF_D64 */	---
15391	5782,	---	15391	5782,	---
15392	/* MOVF_I */	---	15392	/* MOVF_I */	---
15393	5786,	---	15393	5786,	---
15394	/* MOVF_I64 */	---	15394	/* MOVF_I64 */	---
15395	5790,	---	15395	5790,	---
15396	/* MOVF_I_MM */	---	15396	/* MOVF_I_MM */	---
15397	5794,	---	15397	5794,	---
15398	/* MOVF_S */	---	15398	/* MOVF_S */	---
15399	5798,	---	15399	5798,	---
15400	/* MOVF_S_MM */	---	15400	/* MOVF_S_MM */	---
15401	5802,	---	15401	5802,	---
15402	/* MOVN_I64_D64 */	---	15402	/* MOVN_I64_D64 */	---
15403	5806,	---	15403	5806,	---
15404	/* MOVN_I64_I */	---	15404	/* MOVN_I64_I */	---
15405	5810,	---	15405	5810,	---
15406	/* MOVN_I64_I64 */	---	15406	/* MOVN_I64_I64 */	---
15407	5814,	---	15407	5814,	---
15408	/* MOVN_I64_S */	---	15408	/* MOVN_I64_S */	---
15409	5818,	---	15409	5818,	---
15410	/* MOVN_I_D32 */	---	15410	/* MOVN_I_D32 */	---
15411	5822,	---	15411	5822,	---
15412	/* MOVN_I_D32_MM */	---	15412	/* MOVN_I_D32_MM */	---
15413	5826,	---	15413	5826,	---
15414	/* MOVN_I_D64 */	---	15414	/* MOVN_I_D64 */	---
15415	5830,	---	15415	5830,	---
15416	/* MOVN_I_I */	---	15416	/* MOVN_I_I */	---
15417	5834,	---	15417	5834,	---
15418	/* MOVN_I_I64 */	---	15418	/* MOVN_I_I64 */	---
15419	5838,	---	15419	5838,	---
15420	/* MOVN_I_MM */	---	15420	/* MOVN_I_MM */	---
15421	5842,	---	15421	5842,	---
15422	/* MOVN_I_S */	---	15422	/* MOVN_I_S */	---
15423	5846,	---	15423	5846,	---
15424	/* MOVN_I_S_MM */	---	15424	/* MOVN_I_S_MM */	---
15425	5850,	---	15425	5850,	---
15426	/* MOVT_D32 */	---	15426	/* MOVT_D32 */	---
15427	5854,	---	15427	5854,	---
15428	/* MOVT_D32_MM */	---	15428	/* MOVT_D32_MM */	---
15429	5858,	---	15429	5858,	---
15430	/* MOVT_D64 */	---	15430	/* MOVT_D64 */	---
15431	5862,	---	15431	5862,	---
15432	/* MOVT_I */	---	15432	/* MOVT_I */	---
15433	5866,	---	15433	5866,	---
15434	/* MOVT_I64 */	---	15434	/* MOVT_I64 */	---
15435	5870,	---	15435	5870,	---
15436	/* MOVT_I_MM */	---	15436	/* MOVT_I_MM */	---
15437	5874,	---	15437	5874,	---
15438	/* MOVT_S */	---	15438	/* MOVT_S */	---
15439	5878,	---	15439	5878,	---
15440	/* MOVT_S_MM */	---	15440	/* MOVT_S_MM */	---
15441	5882,	---	15441	5882,	---
15442	/* MOVZ_I64_D64 */	---	15442	/* MOVZ_I64_D64 */	---
15443	5886,	---	15443	5886,	---
15444	/* MOVZ_I64_I */	---	15444	/* MOVZ_I64_I */	---
15445	5890,	---	15445	5890,	---
15446	/* MOVZ_I64_I64 */	---	15446	/* MOVZ_I64_I64 */	---
15447	5894,	---	15447	5894,	---
15448	/* MOVZ_I64_S */	---	15448	/* MOVZ_I64_S */	---
15449	5898,	---	15449	5898,	---
15450	/* MOVZ_I_D32 */	---	15450	/* MOVZ_I_D32 */	---
15451	5902,	---	15451	5902,	---
15452	/* MOVZ_I_D32_MM */	---	15452	/* MOVZ_I_D32_MM */	---
15453	5906,	---	15453	5906,	---
15454	/* MOVZ_I_D64 */	---	15454	/* MOVZ_I_D64 */	---
15455	5910,	---	15455	5910,	---
15456	/* MOVZ_I_I */	---	15456	/* MOVZ_I_I */	---
15457	5914,	---	15457	5914,	---
15458	/* MOVZ_I_I64 */	---	15458	/* MOVZ_I_I64 */	---
15459	5918,	---	15459	5918,	---
15460	/* MOVZ_I_MM */	---	15460	/* MOVZ_I_MM */	---
15461	5922,	---	15461	5922,	---
15462	/* MOVZ_I_S */	---	15462	/* MOVZ_I_S */	---
15463	5926,	---	15463	5926,	---
15464	/* MOVZ_I_S_MM */	---	15464	/* MOVZ_I_S_MM */	---
15465	5930,	---	15465	5930,	---
15466	/* MSUB */	---	15466	/* MSUB */	---
15467	5934,	---	15467	5934,	---
15468	/* MSUBF_D */	---	15468	/* MSUBF_D */	---
15469	5936,	---	15469	5936,	---
15470	/* MSUBF_D_MMR6 */	---	15470	/* MSUBF_D_MMR6 */	---
15471	5940,	---	15471	5940,	---
15472	/* MSUBF_S */	---	15472	/* MSUBF_S */	---
15473	5944,	---	15473	5944,	---
15474	/* MSUBF_S_MMR6 */	---	15474	/* MSUBF_S_MMR6 */	---
15475	5948,	---	15475	5948,	---
15476	/* MSUBR_Q_H */	---	15476	/* MSUBR_Q_H */	---
15477	5952,	---	15477	5952,	---
15478	/* MSUBR_Q_W */	---	15478	/* MSUBR_Q_W */	---
15479	5956,	---	15479	5956,	---
15480	/* MSUBU */	---	15480	/* MSUBU */	---
15481	5960,	---	15481	5960,	---
15482	/* MSUBU_DSP */	---	15482	/* MSUBU_DSP */	---
15483	5962,	---	15483	5962,	---
15484	/* MSUBU_DSP_MM */	---	15484	/* MSUBU_DSP_MM */	---
15485	5966,	---	15485	5966,	---
15486	/* MSUBU_MM */	---	15486	/* MSUBU_MM */	---
15487	5970,	---	15487	5970,	---
15488	/* MSUBV_B */	---	15488	/* MSUBV_B */	---
15489	5972,	---	15489	5972,	---
15490	/* MSUBV_D */	---	15490	/* MSUBV_D */	---
15491	5976,	---	15491	5976,	---
15492	/* MSUBV_H */	---	15492	/* MSUBV_H */	---
15493	5980,	---	15493	5980,	---
15494	/* MSUBV_W */	---	15494	/* MSUBV_W */	---
15495	5984,	---	15495	5984,	---
15496	/* MSUB_D32 */	---	15496	/* MSUB_D32 */	---
15497	5988,	---	15497	5988,	---
15498	/* MSUB_D32_MM */	---	15498	/* MSUB_D32_MM */	---
15499	5992,	---	15499	5992,	---
15500	/* MSUB_D64 */	---	15500	/* MSUB_D64 */	---
15501	5996,	---	15501	5996,	---
15502	/* MSUB_DSP */	---	15502	/* MSUB_DSP */	---
15503	6000,	---	15503	6000,	---
15504	/* MSUB_DSP_MM */	---	15504	/* MSUB_DSP_MM */	---
15505	6004,	---	15505	6004,	---
15506	/* MSUB_MM */	---	15506	/* MSUB_MM */	---
15507	6008,	---	15507	6008,	---
15508	/* MSUB_Q_H */	---	15508	/* MSUB_Q_H */	---
15509	6010,	---	15509	6010,	---
15510	/* MSUB_Q_W */	---	15510	/* MSUB_Q_W */	---
15511	6014,	---	15511	6014,	---
15512	/* MSUB_S */	---	15512	/* MSUB_S */	---
15513	6018,	---	15513	6018,	---
15514	/* MSUB_S_MM */	---	15514	/* MSUB_S_MM */	---
15515	6022,	---	15515	6022,	---
15516	/* MTC0 */	---	15516	/* MTC0 */	---
15517	6026,	---	15517	6026,	---
15518	/* MTC0_MMR6 */	---	15518	/* MTC0_MMR6 */	---
15519	6029,	---	15519	6029,	---
15520	/* MTC1 */	---	15520	/* MTC1 */	---
15521	6032,	---	15521	6032,	---
15522	/* MTC1_D64 */	---	15522	/* MTC1_D64 */	---
15523	6034,	---	15523	6034,	---
15524	/* MTC1_D64_MM */	---	15524	/* MTC1_D64_MM */	---
15525	6036,	---	15525	6036,	---
15526	/* MTC1_MM */	---	15526	/* MTC1_MM */	---
15527	6038,	---	15527	6038,	---
15528	/* MTC1_MMR6 */	---	15528	/* MTC1_MMR6 */	---
15529	6040,	---	15529	6040,	---
15530	/* MTC2 */	---	15530	/* MTC2 */	---
15531	6042,	---	15531	6042,	---
15532	/* MTC2_MMR6 */	---	15532	/* MTC2_MMR6 */	---
15533	6045,	---	15533	6045,	---
15534	/* MTGC0 */	---	15534	/* MTGC0 */	---
15535	6047,	---	15535	6047,	---
15536	/* MTGC0_MM */	---	15536	/* MTGC0_MM */	---
15537	6050,	---	15537	6050,	---
15538	/* MTHC0_MMR6 */	---	15538	/* MTHC0_MMR6 */	---
15539	6053,	---	15539	6053,	---
15540	/* MTHC1_D32 */	---	15540	/* MTHC1_D32 */	---
15541	6056,	---	15541	6056,	---
15542	/* MTHC1_D32_MM */	---	15542	/* MTHC1_D32_MM */	---
15543	6059,	---	15543	6059,	---
15544	/* MTHC1_D64 */	---	15544	/* MTHC1_D64 */	---
15545	6062,	---	15545	6062,	---
15546	/* MTHC1_D64_MM */	---	15546	/* MTHC1_D64_MM */	---
15547	6065,	---	15547	6065,	---
15548	/* MTHC2_MMR6 */	---	15548	/* MTHC2_MMR6 */	---
15549	6068,	---	15549	6068,	---
15550	/* MTHGC0 */	---	15550	/* MTHGC0 */	---
15551	6070,	---	15551	6070,	---
15552	/* MTHGC0_MM */	---	15552	/* MTHGC0_MM */	---
15553	6073,	---	15553	6073,	---
15554	/* MTHI */	---	15554	/* MTHI */	---
15555	6076,	---	15555	6076,	---
15556	/* MTHI64 */	---	15556	/* MTHI64 */	---
15557	6077,	---	15557	6077,	---
15558	/* MTHI_DSP */	---	15558	/* MTHI_DSP */	---
15559	6078,	---	15559	6078,	---
15560	/* MTHI_DSP_MM */	---	15560	/* MTHI_DSP_MM */	---
15561	6080,	---	15561	6080,	---
15562	/* MTHI_MM */	---	15562	/* MTHI_MM */	---
15563	6082,	---	15563	6082,	---
15564	/* MTHLIP */	---	15564	/* MTHLIP */	---
15565	6083,	---	15565	6083,	---
15566	/* MTHLIP_MM */	---	15566	/* MTHLIP_MM */	---
15567	6086,	---	15567	6086,	---
15568	/* MTLO */	---	15568	/* MTLO */	---
15569	6089,	---	15569	6089,	---
15570	/* MTLO64 */	---	15570	/* MTLO64 */	---
15571	6090,	---	15571	6090,	---
15572	/* MTLO_DSP */	---	15572	/* MTLO_DSP */	---
15573	6091,	---	15573	6091,	---
15574	/* MTLO_DSP_MM */	---	15574	/* MTLO_DSP_MM */	---
15575	6093,	---	15575	6093,	---
15576	/* MTLO_MM */	---	15576	/* MTLO_MM */	---
15577	6095,	---	15577	6095,	---
15578	/* MTM0 */	---	15578	/* MTM0 */	---
15579	6096,	---	15579	6096,	---
15580	/* MTM1 */	---	15580	/* MTM1 */	---
15581	6097,	---	15581	6097,	---
15582	/* MTM2 */	---	15582	/* MTM2 */	---
15583	6098,	---	15583	6098,	---
15584	/* MTP0 */	---	15584	/* MTP0 */	---
15585	6099,	---	15585	6099,	---
15586	/* MTP1 */	---	15586	/* MTP1 */	---
15587	6100,	---	15587	6100,	---
15588	/* MTP2 */	---	15588	/* MTP2 */	---
15589	6101,	---	15589	6101,	---
15590	/* MTTR */	---	15590	/* MTTR */	---
15591	6102,	---	15591	6102,	---
15592	/* MUH */	---	15592	/* MUH */	---
15593	6107,	---	15593	6107,	---
15594	/* MUHU */	---	15594	/* MUHU */	---
15595	6110,	---	15595	6110,	---
15596	/* MUHU_MMR6 */	---	15596	/* MUHU_MMR6 */	---
15597	6113,	---	15597	6113,	---
15598	/* MUH_MMR6 */	---	15598	/* MUH_MMR6 */	---
15599	6116,	---	15599	6116,	---
15600	/* MUL */	---	15600	/* MUL */	---
15601	6119,	---	15601	6119,	---
15602	/* MULEQ_S_W_PHL */	---	15602	/* MULEQ_S_W_PHL */	---
15603	6122,	---	15603	6122,	---
15604	/* MULEQ_S_W_PHL_MM */	---	15604	/* MULEQ_S_W_PHL_MM */	---
15605	6125,	---	15605	6125,	---
15606	/* MULEQ_S_W_PHR */	---	15606	/* MULEQ_S_W_PHR */	---
15607	6128,	---	15607	6128,	---
15608	/* MULEQ_S_W_PHR_MM */	---	15608	/* MULEQ_S_W_PHR_MM */	---
15609	6131,	---	15609	6131,	---
15610	/* MULEU_S_PH_QBL */	---	15610	/* MULEU_S_PH_QBL */	---
15611	6134,	---	15611	6134,	---
15612	/* MULEU_S_PH_QBL_MM */	---	15612	/* MULEU_S_PH_QBL_MM */	---
15613	6137,	---	15613	6137,	---
15614	/* MULEU_S_PH_QBR */	---	15614	/* MULEU_S_PH_QBR */	---
15615	6140,	---	15615	6140,	---
15616	/* MULEU_S_PH_QBR_MM */	---	15616	/* MULEU_S_PH_QBR_MM */	---
15617	6143,	---	15617	6143,	---
15618	/* MULQ_RS_PH */	---	15618	/* MULQ_RS_PH */	---
15619	6146,	---	15619	6146,	---
15620	/* MULQ_RS_PH_MM */	---	15620	/* MULQ_RS_PH_MM */	---
15621	6149,	---	15621	6149,	---
15622	/* MULQ_RS_W */	---	15622	/* MULQ_RS_W */	---
15623	6152,	---	15623	6152,	---
15624	/* MULQ_RS_W_MMR2 */	---	15624	/* MULQ_RS_W_MMR2 */	---
15625	6155,	---	15625	6155,	---
15626	/* MULQ_S_PH */	---	15626	/* MULQ_S_PH */	---
15627	6158,	---	15627	6158,	---
15628	/* MULQ_S_PH_MMR2 */	---	15628	/* MULQ_S_PH_MMR2 */	---
15629	6161,	---	15629	6161,	---
15630	/* MULQ_S_W */	---	15630	/* MULQ_S_W */	---
15631	6164,	---	15631	6164,	---
15632	/* MULQ_S_W_MMR2 */	---	15632	/* MULQ_S_W_MMR2 */	---
15633	6167,	---	15633	6167,	---
15634	/* MULR_PS64 */	---	15634	/* MULR_PS64 */	---
15635	6170,	---	15635	6170,	---
15636	/* MULR_Q_H */	---	15636	/* MULR_Q_H */	---
15637	6173,	---	15637	6173,	---
15638	/* MULR_Q_W */	---	15638	/* MULR_Q_W */	---
15639	6176,	---	15639	6176,	---
15640	/* MULSAQ_S_W_PH */	---	15640	/* MULSAQ_S_W_PH */	---
15641	6179,	---	15641	6179,	---
15642	/* MULSAQ_S_W_PH_MM */	---	15642	/* MULSAQ_S_W_PH_MM */	---
15643	6183,	---	15643	6183,	---
15644	/* MULSA_W_PH */	---	15644	/* MULSA_W_PH */	---
15645	6187,	---	15645	6187,	---
15646	/* MULSA_W_PH_MMR2 */	---	15646	/* MULSA_W_PH_MMR2 */	---
15647	6191,	---	15647	6191,	---
15648	/* MULT */	---	15648	/* MULT */	---
15649	6195,	---	15649	6195,	---
15650	/* MULTU_DSP */	---	15650	/* MULTU_DSP */	---
15651	6197,	---	15651	6197,	---
15652	/* MULTU_DSP_MM */	---	15652	/* MULTU_DSP_MM */	---
15653	6200,	---	15653	6200,	---
15654	/* MULT_DSP */	---	15654	/* MULT_DSP */	---
15655	6203,	---	15655	6203,	---
15656	/* MULT_DSP_MM */	---	15656	/* MULT_DSP_MM */	---
15657	6206,	---	15657	6206,	---
15658	/* MULT_MM */	---	15658	/* MULT_MM */	---
15659	6209,	---	15659	6209,	---
15660	/* MULTu */	---	15660	/* MULTu */	---
15661	6211,	---	15661	6211,	---
15662	/* MULTu_MM */	---	15662	/* MULTu_MM */	---
15663	6213,	---	15663	6213,	---
15664	/* MULU */	---	15664	/* MULU */	---
15665	6215,	---	15665	6215,	---
15666	/* MULU_MMR6 */	---	15666	/* MULU_MMR6 */	---
15667	6218,	---	15667	6218,	---
15668	/* MULV_B */	---	15668	/* MULV_B */	---
15669	6221,	---	15669	6221,	---
15670	/* MULV_D */	---	15670	/* MULV_D */	---
15671	6224,	---	15671	6224,	---
15672	/* MULV_H */	---	15672	/* MULV_H */	---
15673	6227,	---	15673	6227,	---
15674	/* MULV_W */	---	15674	/* MULV_W */	---
15675	6230,	---	15675	6230,	---
15676	/* MUL_MM */	---	15676	/* MUL_MM */	---
15677	6233,	---	15677	6233,	---
15678	/* MUL_MMR6 */	---	15678	/* MUL_MMR6 */	---
15679	6236,	---	15679	6236,	---
15680	/* MUL_PH */	---	15680	/* MUL_PH */	---
15681	6239,	---	15681	6239,	---
15682	/* MUL_PH_MMR2 */	---	15682	/* MUL_PH_MMR2 */	---
15683	6242,	---	15683	6242,	---
15684	/* MUL_Q_H */	---	15684	/* MUL_Q_H */	---
15685	6245,	---	15685	6245,	---
15686	/* MUL_Q_W */	---	15686	/* MUL_Q_W */	---
15687	6248,	---	15687	6248,	---
15688	/* MUL_R6 */	---	15688	/* MUL_R6 */	---
15689	6251,	---	15689	6251,	---
15690	/* MUL_S_PH */	---	15690	/* MUL_S_PH */	---
15691	6254,	---	15691	6254,	---
15692	/* MUL_S_PH_MMR2 */	---	15692	/* MUL_S_PH_MMR2 */	---
15693	6257,	---	15693	6257,	---
15694	/* Mfhi16 */	---	15694	/* Mfhi16 */	---
15695	6260,	---	15695	6260,	---
15696	/* Mflo16 */	---	15696	/* Mflo16 */	---
15697	6261,	---	15697	6261,	---
15698	/* Move32R16 */	---	15698	/* Move32R16 */	---
15699	6262,	---	15699	6262,	---
15700	/* MoveR3216 */	---	15700	/* MoveR3216 */	---
15701	6264,	---	15701	6264,	---
15702	/* NLOC_B */	---	15702	/* NLOC_B */	---
15703	6266,	---	15703	6266,	---
15704	/* NLOC_D */	---	15704	/* NLOC_D */	---
15705	6268,	---	15705	6268,	---
15706	/* NLOC_H */	---	15706	/* NLOC_H */	---
15707	6270,	---	15707	6270,	---
15708	/* NLOC_W */	---	15708	/* NLOC_W */	---
15709	6272,	---	15709	6272,	---
15710	/* NLZC_B */	---	15710	/* NLZC_B */	---
15711	6274,	---	15711	6274,	---
15712	/* NLZC_D */	---	15712	/* NLZC_D */	---
15713	6276,	---	15713	6276,	---
15714	/* NLZC_H */	---	15714	/* NLZC_H */	---
15715	6278,	---	15715	6278,	---
15716	/* NLZC_W */	---	15716	/* NLZC_W */	---
15717	6280,	---	15717	6280,	---
15718	/* NMADD_D32 */	---	15718	/* NMADD_D32 */	---
15719	6282,	---	15719	6282,	---
15720	/* NMADD_D32_MM */	---	15720	/* NMADD_D32_MM */	---
15721	6286,	---	15721	6286,	---
15722	/* NMADD_D64 */	---	15722	/* NMADD_D64 */	---
15723	6290,	---	15723	6290,	---
15724	/* NMADD_S */	---	15724	/* NMADD_S */	---
15725	6294,	---	15725	6294,	---
15726	/* NMADD_S_MM */	---	15726	/* NMADD_S_MM */	---
15727	6298,	---	15727	6298,	---
15728	/* NMSUB_D32 */	---	15728	/* NMSUB_D32 */	---
15729	6302,	---	15729	6302,	---
15730	/* NMSUB_D32_MM */	---	15730	/* NMSUB_D32_MM */	---
15731	6306,	---	15731	6306,	---
15732	/* NMSUB_D64 */	---	15732	/* NMSUB_D64 */	---
15733	6310,	---	15733	6310,	---
15734	/* NMSUB_S */	---	15734	/* NMSUB_S */	---
15735	6314,	---	15735	6314,	---
15736	/* NMSUB_S_MM */	---	15736	/* NMSUB_S_MM */	---
15737	6318,	---	15737	6318,	---
15738	/* NOR */	---	15738	/* NOR */	---
15739	6322,	---	15739	6322,	---
15740	/* NOR64 */	---	15740	/* NOR64 */	---
15741	6325,	---	15741	6325,	---
15742	/* NORI_B */	---	15742	/* NORI_B */	---
15743	6328,	---	15743	6328,	---
15744	/* NOR_MM */	---	15744	/* NOR_MM */	---
15745	6331,	---	15745	6331,	---
15746	/* NOR_MMR6 */	---	15746	/* NOR_MMR6 */	---
15747	6334,	---	15747	6334,	---
15748	/* NOR_V */	---	15748	/* NOR_V */	---
15749	6337,	---	15749	6337,	---
15750	/* NOT16_MM */	---	15750	/* NOT16_MM */	---
15751	6340,	---	15751	6340,	---
15752	/* NOT16_MMR6 */	---	15752	/* NOT16_MMR6 */	---
15753	6342,	---	15753	6342,	---
15754	/* NegRxRy16 */	---	15754	/* NegRxRy16 */	---
15755	6344,	---	15755	6344,	---
15756	/* NotRxRy16 */	---	15756	/* NotRxRy16 */	---
15757	6346,	---	15757	6346,	---
15758	/* OR */	---	15758	/* OR */	---
15759	6348,	---	15759	6348,	---
15760	/* OR16_MM */	---	15760	/* OR16_MM */	---
15761	6351,	---	15761	6351,	---
15762	/* OR16_MMR6 */	---	15762	/* OR16_MMR6 */	---
15763	6354,	---	15763	6354,	---
15764	/* OR64 */	---	15764	/* OR64 */	---
15765	6357,	---	15765	6357,	---
15766	/* ORI_B */	---	15766	/* ORI_B */	---
15767	6360,	---	15767	6360,	---
15768	/* ORI_MMR6 */	---	15768	/* ORI_MMR6 */	---
15769	6363,	---	15769	6363,	---
15770	/* OR_MM */	---	15770	/* OR_MM */	---
15771	6366,	---	15771	6366,	---
15772	/* OR_MMR6 */	---	15772	/* OR_MMR6 */	---
15773	6369,	---	15773	6369,	---
15774	/* OR_V */	---	15774	/* OR_V */	---
15775	6372,	---	15775	6372,	---
15776	/* ORi */	---	15776	/* ORi */	---
15777	6375,	---	15777	6375,	---
15778	/* ORi64 */	---	15778	/* ORi64 */	---
15779	6378,	---	15779	6378,	---
15780	/* ORi_MM */	---	15780	/* ORi_MM */	---
15781	6381,	---	15781	6381,	---
15782	/* OrRxRxRy16 */	---	15782	/* OrRxRxRy16 */	---
15783	6384,	---	15783	6384,	---
15784	/* PACKRL_PH */	---	15784	/* PACKRL_PH */	---
15785	6387,	---	15785	6387,	---
15786	/* PACKRL_PH_MM */	---	15786	/* PACKRL_PH_MM */	---
15787	6390,	---	15787	6390,	---
15788	/* PAUSE */	---	15788	/* PAUSE */	---
15789	6393,	---	15789	6393,	---
15790	/* PAUSE_MM */	---	15790	/* PAUSE_MM */	---
15791	6393,	---	15791	6393,	---
15792	/* PAUSE_MMR6 */	---	15792	/* PAUSE_MMR6 */	---
15793	6393,	---	15793	6393,	---
15794	/* PCKEV_B */	---	15794	/* PCKEV_B */	---
15795	6393,	---	15795	6393,	---
15796	/* PCKEV_D */	---	15796	/* PCKEV_D */	---
15797	6396,	---	15797	6396,	---
15798	/* PCKEV_H */	---	15798	/* PCKEV_H */	---
15799	6399,	---	15799	6399,	---
15800	/* PCKEV_W */	---	15800	/* PCKEV_W */	---
15801	6402,	---	15801	6402,	---
15802	/* PCKOD_B */	---	15802	/* PCKOD_B */	---
15803	6405,	---	15803	6405,	---
15804	/* PCKOD_D */	---	15804	/* PCKOD_D */	---
15805	6408,	---	15805	6408,	---
15806	/* PCKOD_H */	---	15806	/* PCKOD_H */	---
15807	6411,	---	15807	6411,	---
15808	/* PCKOD_W */	---	15808	/* PCKOD_W */	---
15809	6414,	---	15809	6414,	---
15810	/* PCNT_B */	---	15810	/* PCNT_B */	---
15811	6417,	---	15811	6417,	---
15812	/* PCNT_D */	---	15812	/* PCNT_D */	---
15813	6419,	---	15813	6419,	---
15814	/* PCNT_H */	---	15814	/* PCNT_H */	---
15815	6421,	---	15815	6421,	---
15816	/* PCNT_W */	---	15816	/* PCNT_W */	---
15817	6423,	---	15817	6423,	---
15818	/* PICK_PH */	---	15818	/* PICK_PH */	---
15819	6425,	---	15819	6425,	---
15820	/* PICK_PH_MM */	---	15820	/* PICK_PH_MM */	---
15821	6428,	---	15821	6428,	---
15822	/* PICK_QB */	---	15822	/* PICK_QB */	---
15823	6431,	---	15823	6431,	---
15824	/* PICK_QB_MM */	---	15824	/* PICK_QB_MM */	---
15825	6434,	---	15825	6434,	---
15826	/* PLL_PS64 */	---	15826	/* PLL_PS64 */	---
15827	6437,	---	15827	6437,	---
15828	/* PLU_PS64 */	---	15828	/* PLU_PS64 */	---
15829	6440,	---	15829	6440,	---
15830	/* POP */	---	15830	/* POP */	---
15831	6443,	---	15831	6443,	---
15832	/* PRECEQU_PH_QBL */	---	15832	/* PRECEQU_PH_QBL */	---
15833	6445,	---	15833	6445,	---
15834	/* PRECEQU_PH_QBLA */	---	15834	/* PRECEQU_PH_QBLA */	---
15835	6447,	---	15835	6447,	---
15836	/* PRECEQU_PH_QBLA_MM */	---	15836	/* PRECEQU_PH_QBLA_MM */	---
15837	6449,	---	15837	6449,	---
15838	/* PRECEQU_PH_QBL_MM */	---	15838	/* PRECEQU_PH_QBL_MM */	---
15839	6451,	---	15839	6451,	---
15840	/* PRECEQU_PH_QBR */	---	15840	/* PRECEQU_PH_QBR */	---
15841	6453,	---	15841	6453,	---
15842	/* PRECEQU_PH_QBRA */	---	15842	/* PRECEQU_PH_QBRA */	---
15843	6455,	---	15843	6455,	---
15844	/* PRECEQU_PH_QBRA_MM */	---	15844	/* PRECEQU_PH_QBRA_MM */	---
15845	6457,	---	15845	6457,	---
15846	/* PRECEQU_PH_QBR_MM */	---	15846	/* PRECEQU_PH_QBR_MM */	---
15847	6459,	---	15847	6459,	---
15848	/* PRECEQ_W_PHL */	---	15848	/* PRECEQ_W_PHL */	---
15849	6461,	---	15849	6461,	---
15850	/* PRECEQ_W_PHL_MM */	---	15850	/* PRECEQ_W_PHL_MM */	---
15851	6463,	---	15851	6463,	---
15852	/* PRECEQ_W_PHR */	---	15852	/* PRECEQ_W_PHR */	---
15853	6465,	---	15853	6465,	---
15854	/* PRECEQ_W_PHR_MM */	---	15854	/* PRECEQ_W_PHR_MM */	---
15855	6467,	---	15855	6467,	---
15856	/* PRECEU_PH_QBL */	---	15856	/* PRECEU_PH_QBL */	---
15857	6469,	---	15857	6469,	---
15858	/* PRECEU_PH_QBLA */	---	15858	/* PRECEU_PH_QBLA */	---
15859	6471,	---	15859	6471,	---
15860	/* PRECEU_PH_QBLA_MM */	---	15860	/* PRECEU_PH_QBLA_MM */	---
15861	6473,	---	15861	6473,	---
15862	/* PRECEU_PH_QBL_MM */	---	15862	/* PRECEU_PH_QBL_MM */	---
15863	6475,	---	15863	6475,	---
15864	/* PRECEU_PH_QBR */	---	15864	/* PRECEU_PH_QBR */	---
15865	6477,	---	15865	6477,	---
15866	/* PRECEU_PH_QBRA */	---	15866	/* PRECEU_PH_QBRA */	---
15867	6479,	---	15867	6479,	---
15868	/* PRECEU_PH_QBRA_MM */	---	15868	/* PRECEU_PH_QBRA_MM */	---
15869	6481,	---	15869	6481,	---
15870	/* PRECEU_PH_QBR_MM */	---	15870	/* PRECEU_PH_QBR_MM */	---
15871	6483,	---	15871	6483,	---
15872	/* PRECRQU_S_QB_PH */	---	15872	/* PRECRQU_S_QB_PH */	---
15873	6485,	---	15873	6485,	---
15874	/* PRECRQU_S_QB_PH_MM */	---	15874	/* PRECRQU_S_QB_PH_MM */	---
15875	6488,	---	15875	6488,	---
15876	/* PRECRQ_PH_W */	---	15876	/* PRECRQ_PH_W */	---
15877	6491,	---	15877	6491,	---
15878	/* PRECRQ_PH_W_MM */	---	15878	/* PRECRQ_PH_W_MM */	---
15879	6494,	---	15879	6494,	---
15880	/* PRECRQ_QB_PH */	---	15880	/* PRECRQ_QB_PH */	---
15881	6497,	---	15881	6497,	---
15882	/* PRECRQ_QB_PH_MM */	---	15882	/* PRECRQ_QB_PH_MM */	---
15883	6500,	---	15883	6500,	---
15884	/* PRECRQ_RS_PH_W */	---	15884	/* PRECRQ_RS_PH_W */	---
15885	6503,	---	15885	6503,	---
15886	/* PRECRQ_RS_PH_W_MM */	---	15886	/* PRECRQ_RS_PH_W_MM */	---
15887	6506,	---	15887	6506,	---
15888	/* PRECR_QB_PH */	---	15888	/* PRECR_QB_PH */	---
15889	6509,	---	15889	6509,	---
15890	/* PRECR_QB_PH_MMR2 */	---	15890	/* PRECR_QB_PH_MMR2 */	---
15891	6512,	---	15891	6512,	---
15892	/* PRECR_SRA_PH_W */	---	15892	/* PRECR_SRA_PH_W */	---
15893	6515,	---	15893	6515,	---
15894	/* PRECR_SRA_PH_W_MMR2 */	---	15894	/* PRECR_SRA_PH_W_MMR2 */	---
15895	6519,	---	15895	6519,	---
15896	/* PRECR_SRA_R_PH_W */	---	15896	/* PRECR_SRA_R_PH_W */	---
15897	6523,	---	15897	6523,	---
15898	/* PRECR_SRA_R_PH_W_MMR2 */	---	15898	/* PRECR_SRA_R_PH_W_MMR2 */	---
15899	6527,	---	15899	6527,	---
15900	/* PREF */	---	15900	/* PREF */	---
15901	6531,	---	15901	6531,	---
15902	/* PREFE */	---	15902	/* PREFE */	---
15903	6534,	---	15903	6534,	---
15904	/* PREFE_MM */	---	15904	/* PREFE_MM */	---
15905	6537,	---	15905	6537,	---
15906	/* PREFX_MM */	---	15906	/* PREFX_MM */	---
15907	6540,	---	15907	6540,	---
15908	/* PREF_MM */	---	15908	/* PREF_MM */	---
15909	6543,	---	15909	6543,	---
15910	/* PREF_MMR6 */	---	15910	/* PREF_MMR6 */	---
15911	6546,	---	15911	6546,	---
15912	/* PREF_R6 */	---	15912	/* PREF_R6 */	---
15913	6549,	---	15913	6549,	---
15914	/* PREPEND */	---	15914	/* PREPEND */	---
15915	6552,	---	15915	6552,	---
15916	/* PREPEND_MMR2 */	---	15916	/* PREPEND_MMR2 */	---
15917	6556,	---	15917	6556,	---
15918	/* PUL_PS64 */	---	15918	/* PUL_PS64 */	---
15919	6560,	---	15919	6560,	---
15920	/* PUU_PS64 */	---	15920	/* PUU_PS64 */	---
15921	6563,	---	15921	6563,	---
15922	/* RADDU_W_QB */	---	15922	/* RADDU_W_QB */	---
15923	6566,	---	15923	6566,	---
15924	/* RADDU_W_QB_MM */	---	15924	/* RADDU_W_QB_MM */	---
15925	6568,	---	15925	6568,	---
15926	/* RDDSP */	---	15926	/* RDDSP */	---
15927	6570,	---	15927	6570,	---
15928	/* RDDSP_MM */	---	15928	/* RDDSP_MM */	---
15929	6572,	---	15929	6572,	---
15930	/* RDHWR */	---	15930	/* RDHWR */	---
15931	6574,	---	15931	6574,	---
15932	/* RDHWR64 */	---	15932	/* RDHWR64 */	---
15933	6577,	---	15933	6577,	---
15934	/* RDHWR_MM */	---	15934	/* RDHWR_MM */	---
15935	6580,	---	15935	6580,	---
15936	/* RDHWR_MMR6 */	---	15936	/* RDHWR_MMR6 */	---
15937	6583,	---	15937	6583,	---
15938	/* RDPGPR_MMR6 */	---	15938	/* RDPGPR_MMR6 */	---
15939	6586,	---	15939	6586,	---
15940	/* RECIP_D32 */	---	15940	/* RECIP_D32 */	---
15941	6588,	---	15941	6588,	---
15942	/* RECIP_D32_MM */	---	15942	/* RECIP_D32_MM */	---
15943	6590,	---	15943	6590,	---
15944	/* RECIP_D64 */	---	15944	/* RECIP_D64 */	---
15945	6592,	---	15945	6592,	---
15946	/* RECIP_D64_MM */	---	15946	/* RECIP_D64_MM */	---
15947	6594,	---	15947	6594,	---
15948	/* RECIP_S */	---	15948	/* RECIP_S */	---
15949	6596,	---	15949	6596,	---
15950	/* RECIP_S_MM */	---	15950	/* RECIP_S_MM */	---
15951	6598,	---	15951	6598,	---
15952	/* REPLV_PH */	---	15952	/* REPLV_PH */	---
15953	6600,	---	15953	6600,	---
15954	/* REPLV_PH_MM */	---	15954	/* REPLV_PH_MM */	---
15955	6602,	---	15955	6602,	---
15956	/* REPLV_QB */	---	15956	/* REPLV_QB */	---
15957	6604,	---	15957	6604,	---
15958	/* REPLV_QB_MM */	---	15958	/* REPLV_QB_MM */	---
15959	6606,	---	15959	6606,	---
15960	/* REPL_PH */	---	15960	/* REPL_PH */	---
15961	6608,	---	15961	6608,	---
15962	/* REPL_PH_MM */	---	15962	/* REPL_PH_MM */	---
15963	6610,	---	15963	6610,	---
15964	/* REPL_QB */	---	15964	/* REPL_QB */	---
15965	6612,	---	15965	6612,	---
15966	/* REPL_QB_MM */	---	15966	/* REPL_QB_MM */	---
15967	6614,	---	15967	6614,	---
15968	/* RINT_D */	---	15968	/* RINT_D */	---
15969	6616,	---	15969	6616,	---
15970	/* RINT_D_MMR6 */	---	15970	/* RINT_D_MMR6 */	---
15971	6618,	---	15971	6618,	---
15972	/* RINT_S */	---	15972	/* RINT_S */	---
15973	6620,	---	15973	6620,	---
15974	/* RINT_S_MMR6 */	---	15974	/* RINT_S_MMR6 */	---
15975	6622,	---	15975	6622,	---
15976	/* ROTR */	---	15976	/* ROTR */	---
15977	6624,	---	15977	6624,	---
15978	/* ROTRV */	---	15978	/* ROTRV */	---
15979	6627,	---	15979	6627,	---
15980	/* ROTRV_MM */	---	15980	/* ROTRV_MM */	---
15981	6630,	---	15981	6630,	---
15982	/* ROTR_MM */	---	15982	/* ROTR_MM */	---
15983	6633,	---	15983	6633,	---
15984	/* ROUND_L_D64 */	---	15984	/* ROUND_L_D64 */	---
15985	6636,	---	15985	6636,	---
15986	/* ROUND_L_D_MMR6 */	---	15986	/* ROUND_L_D_MMR6 */	---
15987	6638,	---	15987	6638,	---
15988	/* ROUND_L_S */	---	15988	/* ROUND_L_S */	---
15989	6640,	---	15989	6640,	---
15990	/* ROUND_L_S_MMR6 */	---	15990	/* ROUND_L_S_MMR6 */	---
15991	6642,	---	15991	6642,	---
15992	/* ROUND_W_D32 */	---	15992	/* ROUND_W_D32 */	---
15993	6644,	---	15993	6644,	---
15994	/* ROUND_W_D64 */	---	15994	/* ROUND_W_D64 */	---
15995	6646,	---	15995	6646,	---
15996	/* ROUND_W_D_MMR6 */	---	15996	/* ROUND_W_D_MMR6 */	---
15997	6648,	---	15997	6648,	---
15998	/* ROUND_W_MM */	---	15998	/* ROUND_W_MM */	---
15999	6650,	---	15999	6650,	---
16000	/* ROUND_W_S */	---	16000	/* ROUND_W_S */	---
16001	6652,	---	16001	6652,	---
16002	/* ROUND_W_S_MM */	---	16002	/* ROUND_W_S_MM */	---
16003	6654,	---	16003	6654,	---
16004	/* ROUND_W_S_MMR6 */	---	16004	/* ROUND_W_S_MMR6 */	---
16005	6656,	---	16005	6656,	---
16006	/* RSQRT_D32 */	---	16006	/* RSQRT_D32 */	---
16007	6658,	---	16007	6658,	---
16008	/* RSQRT_D32_MM */	---	16008	/* RSQRT_D32_MM */	---
16009	6660,	---	16009	6660,	---
16010	/* RSQRT_D64 */	---	16010	/* RSQRT_D64 */	---
16011	6662,	---	16011	6662,	---
16012	/* RSQRT_D64_MM */	---	16012	/* RSQRT_D64_MM */	---
16013	6664,	---	16013	6664,	---
16014	/* RSQRT_S */	---	16014	/* RSQRT_S */	---
16015	6666,	---	16015	6666,	---
16016	/* RSQRT_S_MM */	---	16016	/* RSQRT_S_MM */	---
16017	6668,	---	16017	6668,	---
16018	/* Restore16 */	---	16018	/* Restore16 */	---
16019	6670,	---	16019	6670,	---
16020	/* RestoreX16 */	---	16020	/* RestoreX16 */	---
16021	6670,	---	16021	6670,	---
16022	/* SAA */	---	16022	/* SAA */	---
16023	6670,	---	16023	6670,	---
16024	/* SAAD */	---	16024	/* SAAD */	---
16025	6672,	---	16025	6672,	---
16026	/* SAT_S_B */	---	16026	/* SAT_S_B */	---
16027	6674,	---	16027	6674,	---
16028	/* SAT_S_D */	---	16028	/* SAT_S_D */	---
16029	6677,	---	16029	6677,	---
16030	/* SAT_S_H */	---	16030	/* SAT_S_H */	---
16031	6680,	---	16031	6680,	---
16032	/* SAT_S_W */	---	16032	/* SAT_S_W */	---
16033	6683,	---	16033	6683,	---
16034	/* SAT_U_B */	---	16034	/* SAT_U_B */	---
16035	6686,	---	16035	6686,	---
16036	/* SAT_U_D */	---	16036	/* SAT_U_D */	---
16037	6689,	---	16037	6689,	---
16038	/* SAT_U_H */	---	16038	/* SAT_U_H */	---
16039	6692,	---	16039	6692,	---
16040	/* SAT_U_W */	---	16040	/* SAT_U_W */	---
16041	6695,	---	16041	6695,	---
16042	/* SB */	---	16042	/* SB */	---
16043	6698,	---	16043	6698,	---
16044	/* SB16_MM */	---	16044	/* SB16_MM */	---
16045	6701,	---	16045	6701,	---
16046	/* SB16_MMR6 */	---	16046	/* SB16_MMR6 */	---
16047	6704,	---	16047	6704,	---
16048	/* SB64 */	---	16048	/* SB64 */	---
16049	6707,	---	16049	6707,	---
16050	/* SBE */	---	16050	/* SBE */	---
16051	6710,	---	16051	6710,	---
16052	/* SBE_MM */	---	16052	/* SBE_MM */	---
16053	6713,	---	16053	6713,	---
16054	/* SB_MM */	---	16054	/* SB_MM */	---
16055	6716,	---	16055	6716,	---
16056	/* SB_MMR6 */	---	16056	/* SB_MMR6 */	---
16057	6719,	---	16057	6719,	---
16058	/* SC */	---	16058	/* SC */	---
16059	6722,	---	16059	6722,	---
16060	/* SC64 */	---	16060	/* SC64 */	---
16061	6726,	---	16061	6726,	---
16062	/* SC64_R6 */	---	16062	/* SC64_R6 */	---
16063	6730,	---	16063	6730,	---
16064	/* SCD */	---	16064	/* SCD */	---
16065	6734,	---	16065	6734,	---
16066	/* SCD_R6 */	---	16066	/* SCD_R6 */	---
16067	6738,	---	16067	6738,	---
16068	/* SCE */	---	16068	/* SCE */	---
16069	6742,	---	16069	6742,	---
16070	/* SCE_MM */	---	16070	/* SCE_MM */	---
16071	6746,	---	16071	6746,	---
16072	/* SC_MM */	---	16072	/* SC_MM */	---
16073	6750,	---	16073	6750,	---
16074	/* SC_MMR6 */	---	16074	/* SC_MMR6 */	---
16075	6754,	---	16075	6754,	---
16076	/* SC_R6 */	---	16076	/* SC_R6 */	---
16077	6758,	---	16077	6758,	---
16078	/* SD */	---	16078	/* SD */	---
16079	6762,	---	16079	6762,	---
16080	/* SDBBP */	---	16080	/* SDBBP */	---
16081	6765,	---	16081	6765,	---
16082	/* SDBBP16_MM */	---	16082	/* SDBBP16_MM */	---
16083	6766,	---	16083	6766,	---
16084	/* SDBBP16_MMR6 */	---	16084	/* SDBBP16_MMR6 */	---
16085	6767,	---	16085	6767,	---
16086	/* SDBBP_MM */	---	16086	/* SDBBP_MM */	---
16087	6768,	---	16087	6768,	---
16088	/* SDBBP_MMR6 */	---	16088	/* SDBBP_MMR6 */	---
16089	6769,	---	16089	6769,	---
16090	/* SDBBP_R6 */	---	16090	/* SDBBP_R6 */	---
16091	6770,	---	16091	6770,	---
16092	/* SDC1 */	---	16092	/* SDC1 */	---
16093	6771,	---	16093	6771,	---
16094	/* SDC164 */	---	16094	/* SDC164 */	---
16095	6774,	---	16095	6774,	---
16096	/* SDC1_D64_MMR6 */	---	16096	/* SDC1_D64_MMR6 */	---
16097	6777,	---	16097	6777,	---
16098	/* SDC1_MM_D32 */	---	16098	/* SDC1_MM_D32 */	---
16099	6780,	---	16099	6780,	---
16100	/* SDC1_MM_D64 */	---	16100	/* SDC1_MM_D64 */	---
16101	6783,	---	16101	6783,	---
16102	/* SDC2 */	---	16102	/* SDC2 */	---
16103	6786,	---	16103	6786,	---
16104	/* SDC2_MMR6 */	---	16104	/* SDC2_MMR6 */	---
16105	6789,	---	16105	6789,	---
16106	/* SDC2_R6 */	---	16106	/* SDC2_R6 */	---
16107	6792,	---	16107	6792,	---
16108	/* SDC3 */	---	16108	/* SDC3 */	---
16109	6795,	---	16109	6795,	---
16110	/* SDIV */	---	16110	/* SDIV */	---
16111	6798,	---	16111	6798,	---
16112	/* SDIV_MM */	---	16112	/* SDIV_MM */	---
16113	6800,	---	16113	6800,	---
16114	/* SDL */	---	16114	/* SDL */	---
16115	6802,	---	16115	6802,	---
16116	/* SDR */	---	16116	/* SDR */	---
16117	6805,	---	16117	6805,	---
16118	/* SDXC1 */	---	16118	/* SDXC1 */	---
16119	6808,	---	16119	6808,	---
16120	/* SDXC164 */	---	16120	/* SDXC164 */	---
16121	6811,	---	16121	6811,	---
16122	/* SEB */	---	16122	/* SEB */	---
16123	6814,	---	16123	6814,	---
16124	/* SEB64 */	---	16124	/* SEB64 */	---
16125	6816,	---	16125	6816,	---
16126	/* SEB_MM */	---	16126	/* SEB_MM */	---
16127	6818,	---	16127	6818,	---
16128	/* SEH */	---	16128	/* SEH */	---
16129	6820,	---	16129	6820,	---
16130	/* SEH64 */	---	16130	/* SEH64 */	---
16131	6822,	---	16131	6822,	---
16132	/* SEH_MM */	---	16132	/* SEH_MM */	---
16133	6824,	---	16133	6824,	---
16134	/* SELEQZ */	---	16134	/* SELEQZ */	---
16135	6826,	---	16135	6826,	---
16136	/* SELEQZ64 */	---	16136	/* SELEQZ64 */	---
16137	6829,	---	16137	6829,	---
16138	/* SELEQZ_D */	---	16138	/* SELEQZ_D */	---
16139	6832,	---	16139	6832,	---
16140	/* SELEQZ_D_MMR6 */	---	16140	/* SELEQZ_D_MMR6 */	---
16141	6835,	---	16141	6835,	---
16142	/* SELEQZ_MMR6 */	---	16142	/* SELEQZ_MMR6 */	---
16143	6838,	---	16143	6838,	---
16144	/* SELEQZ_S */	---	16144	/* SELEQZ_S */	---
16145	6841,	---	16145	6841,	---
16146	/* SELEQZ_S_MMR6 */	---	16146	/* SELEQZ_S_MMR6 */	---
16147	6844,	---	16147	6844,	---
16148	/* SELNEZ */	---	16148	/* SELNEZ */	---
16149	6847,	---	16149	6847,	---
16150	/* SELNEZ64 */	---	16150	/* SELNEZ64 */	---
16151	6850,	---	16151	6850,	---
16152	/* SELNEZ_D */	---	16152	/* SELNEZ_D */	---
16153	6853,	---	16153	6853,	---
16154	/* SELNEZ_D_MMR6 */	---	16154	/* SELNEZ_D_MMR6 */	---
16155	6856,	---	16155	6856,	---
16156	/* SELNEZ_MMR6 */	---	16156	/* SELNEZ_MMR6 */	---
16157	6859,	---	16157	6859,	---
16158	/* SELNEZ_S */	---	16158	/* SELNEZ_S */	---
16159	6862,	---	16159	6862,	---
16160	/* SELNEZ_S_MMR6 */	---	16160	/* SELNEZ_S_MMR6 */	---
16161	6865,	---	16161	6865,	---
16162	/* SEL_D */	---	16162	/* SEL_D */	---
16163	6868,	---	16163	6868,	---
16164	/* SEL_D_MMR6 */	---	16164	/* SEL_D_MMR6 */	---
16165	6872,	---	16165	6872,	---
16166	/* SEL_S */	---	16166	/* SEL_S */	---
16167	6876,	---	16167	6876,	---
16168	/* SEL_S_MMR6 */	---	16168	/* SEL_S_MMR6 */	---
16169	6880,	---	16169	6880,	---
16170	/* SEQ */	---	16170	/* SEQ */	---
16171	6884,	---	16171	6884,	---
16172	/* SEQi */	---	16172	/* SEQi */	---
16173	6887,	---	16173	6887,	---
16174	/* SH */	---	16174	/* SH */	---
16175	6890,	---	16175	6890,	---
16176	/* SH16_MM */	---	16176	/* SH16_MM */	---
16177	6893,	---	16177	6893,	---
16178	/* SH16_MMR6 */	---	16178	/* SH16_MMR6 */	---
16179	6896,	---	16179	6896,	---
16180	/* SH64 */	---	16180	/* SH64 */	---
16181	6899,	---	16181	6899,	---
16182	/* SHE */	---	16182	/* SHE */	---
16183	6902,	---	16183	6902,	---
16184	/* SHE_MM */	---	16184	/* SHE_MM */	---
16185	6905,	---	16185	6905,	---
16186	/* SHF_B */	---	16186	/* SHF_B */	---
16187	6908,	---	16187	6908,	---
16188	/* SHF_H */	---	16188	/* SHF_H */	---
16189	6911,	---	16189	6911,	---
16190	/* SHF_W */	---	16190	/* SHF_W */	---
16191	6914,	---	16191	6914,	---
16192	/* SHILO */	---	16192	/* SHILO */	---
16193	6917,	---	16193	6917,	---
16194	/* SHILOV */	---	16194	/* SHILOV */	---
16195	6920,	---	16195	6920,	---
16196	/* SHILOV_MM */	---	16196	/* SHILOV_MM */	---
16197	6923,	---	16197	6923,	---
16198	/* SHILO_MM */	---	16198	/* SHILO_MM */	---
16199	6926,	---	16199	6926,	---
16200	/* SHLLV_PH */	---	16200	/* SHLLV_PH */	---
16201	6929,	---	16201	6929,	---
16202	/* SHLLV_PH_MM */	---	16202	/* SHLLV_PH_MM */	---
16203	6932,	---	16203	6932,	---
16204	/* SHLLV_QB */	---	16204	/* SHLLV_QB */	---
16205	6935,	---	16205	6935,	---
16206	/* SHLLV_QB_MM */	---	16206	/* SHLLV_QB_MM */	---
16207	6938,	---	16207	6938,	---
16208	/* SHLLV_S_PH */	---	16208	/* SHLLV_S_PH */	---
16209	6941,	---	16209	6941,	---
16210	/* SHLLV_S_PH_MM */	---	16210	/* SHLLV_S_PH_MM */	---
16211	6944,	---	16211	6944,	---
16212	/* SHLLV_S_W */	---	16212	/* SHLLV_S_W */	---
16213	6947,	---	16213	6947,	---
16214	/* SHLLV_S_W_MM */	---	16214	/* SHLLV_S_W_MM */	---
16215	6950,	---	16215	6950,	---
16216	/* SHLL_PH */	---	16216	/* SHLL_PH */	---
16217	6953,	---	16217	6953,	---
16218	/* SHLL_PH_MM */	---	16218	/* SHLL_PH_MM */	---
16219	6956,	---	16219	6956,	---
16220	/* SHLL_QB */	---	16220	/* SHLL_QB */	---
16221	6959,	---	16221	6959,	---
16222	/* SHLL_QB_MM */	---	16222	/* SHLL_QB_MM */	---
16223	6962,	---	16223	6962,	---
16224	/* SHLL_S_PH */	---	16224	/* SHLL_S_PH */	---
16225	6965,	---	16225	6965,	---
16226	/* SHLL_S_PH_MM */	---	16226	/* SHLL_S_PH_MM */	---
16227	6968,	---	16227	6968,	---
16228	/* SHLL_S_W */	---	16228	/* SHLL_S_W */	---
16229	6971,	---	16229	6971,	---
16230	/* SHLL_S_W_MM */	---	16230	/* SHLL_S_W_MM */	---
16231	6974,	---	16231	6974,	---
16232	/* SHRAV_PH */	---	16232	/* SHRAV_PH */	---
16233	6977,	---	16233	6977,	---
16234	/* SHRAV_PH_MM */	---	16234	/* SHRAV_PH_MM */	---
16235	6980,	---	16235	6980,	---
16236	/* SHRAV_QB */	---	16236	/* SHRAV_QB */	---
16237	6983,	---	16237	6983,	---
16238	/* SHRAV_QB_MMR2 */	---	16238	/* SHRAV_QB_MMR2 */	---
16239	6986,	---	16239	6986,	---
16240	/* SHRAV_R_PH */	---	16240	/* SHRAV_R_PH */	---
16241	6989,	---	16241	6989,	---
16242	/* SHRAV_R_PH_MM */	---	16242	/* SHRAV_R_PH_MM */	---
16243	6992,	---	16243	6992,	---
16244	/* SHRAV_R_QB */	---	16244	/* SHRAV_R_QB */	---
16245	6995,	---	16245	6995,	---
16246	/* SHRAV_R_QB_MMR2 */	---	16246	/* SHRAV_R_QB_MMR2 */	---
16247	6998,	---	16247	6998,	---
16248	/* SHRAV_R_W */	---	16248	/* SHRAV_R_W */	---
16249	7001,	---	16249	7001,	---
16250	/* SHRAV_R_W_MM */	---	16250	/* SHRAV_R_W_MM */	---
16251	7004,	---	16251	7004,	---
16252	/* SHRA_PH */	---	16252	/* SHRA_PH */	---
16253	7007,	---	16253	7007,	---
16254	/* SHRA_PH_MM */	---	16254	/* SHRA_PH_MM */	---
16255	7010,	---	16255	7010,	---
16256	/* SHRA_QB */	---	16256	/* SHRA_QB */	---
16257	7013,	---	16257	7013,	---
16258	/* SHRA_QB_MMR2 */	---	16258	/* SHRA_QB_MMR2 */	---
16259	7016,	---	16259	7016,	---
16260	/* SHRA_R_PH */	---	16260	/* SHRA_R_PH */	---
16261	7019,	---	16261	7019,	---
16262	/* SHRA_R_PH_MM */	---	16262	/* SHRA_R_PH_MM */	---
16263	7022,	---	16263	7022,	---
16264	/* SHRA_R_QB */	---	16264	/* SHRA_R_QB */	---
16265	7025,	---	16265	7025,	---
16266	/* SHRA_R_QB_MMR2 */	---	16266	/* SHRA_R_QB_MMR2 */	---
16267	7028,	---	16267	7028,	---
16268	/* SHRA_R_W */	---	16268	/* SHRA_R_W */	---
16269	7031,	---	16269	7031,	---
16270	/* SHRA_R_W_MM */	---	16270	/* SHRA_R_W_MM */	---
16271	7034,	---	16271	7034,	---
16272	/* SHRLV_PH */	---	16272	/* SHRLV_PH */	---
16273	7037,	---	16273	7037,	---
16274	/* SHRLV_PH_MMR2 */	---	16274	/* SHRLV_PH_MMR2 */	---
16275	7040,	---	16275	7040,	---
16276	/* SHRLV_QB */	---	16276	/* SHRLV_QB */	---
16277	7043,	---	16277	7043,	---
16278	/* SHRLV_QB_MM */	---	16278	/* SHRLV_QB_MM */	---
16279	7046,	---	16279	7046,	---
16280	/* SHRL_PH */	---	16280	/* SHRL_PH */	---
16281	7049,	---	16281	7049,	---
16282	/* SHRL_PH_MMR2 */	---	16282	/* SHRL_PH_MMR2 */	---
16283	7052,	---	16283	7052,	---
16284	/* SHRL_QB */	---	16284	/* SHRL_QB */	---
16285	7055,	---	16285	7055,	---
16286	/* SHRL_QB_MM */	---	16286	/* SHRL_QB_MM */	---
16287	7058,	---	16287	7058,	---
16288	/* SH_MM */	---	16288	/* SH_MM */	---
16289	7061,	---	16289	7061,	---
16290	/* SH_MMR6 */	---	16290	/* SH_MMR6 */	---
16291	7064,	---	16291	7064,	---
16292	/* SIGRIE */	---	16292	/* SIGRIE */	---
16293	7067,	---	16293	7067,	---
16294	/* SIGRIE_MMR6 */	---	16294	/* SIGRIE_MMR6 */	---
16295	7068,	---	16295	7068,	---
16296	/* SLDI_B */	---	16296	/* SLDI_B */	---
16297	7069,	---	16297	7069,	---
16298	/* SLDI_D */	---	16298	/* SLDI_D */	---
16299	7073,	---	16299	7073,	---
16300	/* SLDI_H */	---	16300	/* SLDI_H */	---
16301	7077,	---	16301	7077,	---
16302	/* SLDI_W */	---	16302	/* SLDI_W */	---
16303	7081,	---	16303	7081,	---
16304	/* SLD_B */	---	16304	/* SLD_B */	---
16305	7085,	---	16305	7085,	---
16306	/* SLD_D */	---	16306	/* SLD_D */	---
16307	7089,	---	16307	7089,	---
16308	/* SLD_H */	---	16308	/* SLD_H */	---
16309	7093,	---	16309	7093,	---
16310	/* SLD_W */	---	16310	/* SLD_W */	---
16311	7097,	---	16311	7097,	---
16312	/* SLL */	---	16312	/* SLL */	---
16313	7101,	---	16313	7101,	---
16314	/* SLL16_MM */	---	16314	/* SLL16_MM */	---
16315	7104,	---	16315	7104,	---
16316	/* SLL16_MMR6 */	---	16316	/* SLL16_MMR6 */	---
16317	7107,	---	16317	7107,	---
16318	/* SLL64_32 */	---	16318	/* SLL64_32 */	---
16319	7110,	---	16319	7110,	---
16320	/* SLL64_64 */	---	16320	/* SLL64_64 */	---
16321	7112,	---	16321	7112,	---
16322	/* SLLI_B */	---	16322	/* SLLI_B */	---
16323	7114,	---	16323	7114,	---
16324	/* SLLI_D */	---	16324	/* SLLI_D */	---
16325	7117,	---	16325	7117,	---
16326	/* SLLI_H */	---	16326	/* SLLI_H */	---
16327	7120,	---	16327	7120,	---
16328	/* SLLI_W */	---	16328	/* SLLI_W */	---
16329	7123,	---	16329	7123,	---
16330	/* SLLV */	---	16330	/* SLLV */	---
16331	7126,	---	16331	7126,	---
16332	/* SLLV_MM */	---	16332	/* SLLV_MM */	---
16333	7129,	---	16333	7129,	---
16334	/* SLL_B */	---	16334	/* SLL_B */	---
16335	7132,	---	16335	7132,	---
16336	/* SLL_D */	---	16336	/* SLL_D */	---
16337	7135,	---	16337	7135,	---
16338	/* SLL_H */	---	16338	/* SLL_H */	---
16339	7138,	---	16339	7138,	---
16340	/* SLL_MM */	---	16340	/* SLL_MM */	---
16341	7141,	---	16341	7141,	---
16342	/* SLL_MMR6 */	---	16342	/* SLL_MMR6 */	---
16343	7144,	---	16343	7144,	---
16344	/* SLL_W */	---	16344	/* SLL_W */	---
16345	7147,	---	16345	7147,	---
16346	/* SLT */	---	16346	/* SLT */	---
16347	7150,	---	16347	7150,	---
16348	/* SLT64 */	---	16348	/* SLT64 */	---
16349	7153,	---	16349	7153,	---
16350	/* SLT_MM */	---	16350	/* SLT_MM */	---
16351	7156,	---	16351	7156,	---
16352	/* SLTi */	---	16352	/* SLTi */	---
16353	7159,	---	16353	7159,	---
16354	/* SLTi64 */	---	16354	/* SLTi64 */	---
16355	7162,	---	16355	7162,	---
16356	/* SLTi_MM */	---	16356	/* SLTi_MM */	---
16357	7165,	---	16357	7165,	---
16358	/* SLTiu */	---	16358	/* SLTiu */	---
16359	7168,	---	16359	7168,	---
16360	/* SLTiu64 */	---	16360	/* SLTiu64 */	---
16361	7171,	---	16361	7171,	---
16362	/* SLTiu_MM */	---	16362	/* SLTiu_MM */	---
16363	7174,	---	16363	7174,	---
16364	/* SLTu */	---	16364	/* SLTu */	---
16365	7177,	---	16365	7177,	---
16366	/* SLTu64 */	---	16366	/* SLTu64 */	---
16367	7180,	---	16367	7180,	---
16368	/* SLTu_MM */	---	16368	/* SLTu_MM */	---
16369	7183,	---	16369	7183,	---
16370	/* SNE */	---	16370	/* SNE */	---
16371	7186,	---	16371	7186,	---
16372	/* SNEi */	---	16372	/* SNEi */	---
16373	7189,	---	16373	7189,	---
16374	/* SPLATI_B */	---	16374	/* SPLATI_B */	---
16375	7192,	---	16375	7192,	---
16376	/* SPLATI_D */	---	16376	/* SPLATI_D */	---
16377	7195,	---	16377	7195,	---
16378	/* SPLATI_H */	---	16378	/* SPLATI_H */	---
16379	7198,	---	16379	7198,	---
16380	/* SPLATI_W */	---	16380	/* SPLATI_W */	---
16381	7201,	---	16381	7201,	---
16382	/* SPLAT_B */	---	16382	/* SPLAT_B */	---
16383	7204,	---	16383	7204,	---
16384	/* SPLAT_D */	---	16384	/* SPLAT_D */	---
16385	7207,	---	16385	7207,	---
16386	/* SPLAT_H */	---	16386	/* SPLAT_H */	---
16387	7210,	---	16387	7210,	---
16388	/* SPLAT_W */	---	16388	/* SPLAT_W */	---
16389	7213,	---	16389	7213,	---
16390	/* SRA */	---	16390	/* SRA */	---
16391	7216,	---	16391	7216,	---
16392	/* SRAI_B */	---	16392	/* SRAI_B */	---
16393	7219,	---	16393	7219,	---
16394	/* SRAI_D */	---	16394	/* SRAI_D */	---
16395	7222,	---	16395	7222,	---
16396	/* SRAI_H */	---	16396	/* SRAI_H */	---
16397	7225,	---	16397	7225,	---
16398	/* SRAI_W */	---	16398	/* SRAI_W */	---
16399	7228,	---	16399	7228,	---
16400	/* SRARI_B */	---	16400	/* SRARI_B */	---
16401	7231,	---	16401	7231,	---
16402	/* SRARI_D */	---	16402	/* SRARI_D */	---
16403	7234,	---	16403	7234,	---
16404	/* SRARI_H */	---	16404	/* SRARI_H */	---
16405	7237,	---	16405	7237,	---
16406	/* SRARI_W */	---	16406	/* SRARI_W */	---
16407	7240,	---	16407	7240,	---
16408	/* SRAR_B */	---	16408	/* SRAR_B */	---
16409	7243,	---	16409	7243,	---
16410	/* SRAR_D */	---	16410	/* SRAR_D */	---
16411	7246,	---	16411	7246,	---
16412	/* SRAR_H */	---	16412	/* SRAR_H */	---
16413	7249,	---	16413	7249,	---
16414	/* SRAR_W */	---	16414	/* SRAR_W */	---
16415	7252,	---	16415	7252,	---
16416	/* SRAV */	---	16416	/* SRAV */	---
16417	7255,	---	16417	7255,	---
16418	/* SRAV_MM */	---	16418	/* SRAV_MM */	---
16419	7258,	---	16419	7258,	---
16420	/* SRA_B */	---	16420	/* SRA_B */	---
16421	7261,	---	16421	7261,	---
16422	/* SRA_D */	---	16422	/* SRA_D */	---
16423	7264,	---	16423	7264,	---
16424	/* SRA_H */	---	16424	/* SRA_H */	---
16425	7267,	---	16425	7267,	---
16426	/* SRA_MM */	---	16426	/* SRA_MM */	---
16427	7270,	---	16427	7270,	---
16428	/* SRA_W */	---	16428	/* SRA_W */	---
16429	7273,	---	16429	7273,	---
16430	/* SRL */	---	16430	/* SRL */	---
16431	7276,	---	16431	7276,	---
16432	/* SRL16_MM */	---	16432	/* SRL16_MM */	---
16433	7279,	---	16433	7279,	---
16434	/* SRL16_MMR6 */	---	16434	/* SRL16_MMR6 */	---
16435	7282,	---	16435	7282,	---
16436	/* SRLI_B */	---	16436	/* SRLI_B */	---
16437	7285,	---	16437	7285,	---
16438	/* SRLI_D */	---	16438	/* SRLI_D */	---
16439	7288,	---	16439	7288,	---
16440	/* SRLI_H */	---	16440	/* SRLI_H */	---
16441	7291,	---	16441	7291,	---
16442	/* SRLI_W */	---	16442	/* SRLI_W */	---
16443	7294,	---	16443	7294,	---
16444	/* SRLRI_B */	---	16444	/* SRLRI_B */	---
16445	7297,	---	16445	7297,	---
16446	/* SRLRI_D */	---	16446	/* SRLRI_D */	---
16447	7300,	---	16447	7300,	---
16448	/* SRLRI_H */	---	16448	/* SRLRI_H */	---
16449	7303,	---	16449	7303,	---
16450	/* SRLRI_W */	---	16450	/* SRLRI_W */	---
16451	7306,	---	16451	7306,	---
16452	/* SRLR_B */	---	16452	/* SRLR_B */	---
16453	7309,	---	16453	7309,	---
16454	/* SRLR_D */	---	16454	/* SRLR_D */	---
16455	7312,	---	16455	7312,	---
16456	/* SRLR_H */	---	16456	/* SRLR_H */	---
16457	7315,	---	16457	7315,	---
16458	/* SRLR_W */	---	16458	/* SRLR_W */	---
16459	7318,	---	16459	7318,	---
16460	/* SRLV */	---	16460	/* SRLV */	---
16461	7321,	---	16461	7321,	---
16462	/* SRLV_MM */	---	16462	/* SRLV_MM */	---
16463	7324,	---	16463	7324,	---
16464	/* SRL_B */	---	16464	/* SRL_B */	---
16465	7327,	---	16465	7327,	---
16466	/* SRL_D */	---	16466	/* SRL_D */	---
16467	7330,	---	16467	7330,	---
16468	/* SRL_H */	---	16468	/* SRL_H */	---
16469	7333,	---	16469	7333,	---
16470	/* SRL_MM */	---	16470	/* SRL_MM */	---
16471	7336,	---	16471	7336,	---
16472	/* SRL_W */	---	16472	/* SRL_W */	---
16473	7339,	---	16473	7339,	---
16474	/* SSNOP */	---	16474	/* SSNOP */	---
16475	7342,	---	16475	7342,	---
16476	/* SSNOP_MM */	---	16476	/* SSNOP_MM */	---
16477	7342,	---	16477	7342,	---
16478	/* SSNOP_MMR6 */	---	16478	/* SSNOP_MMR6 */	---
16479	7342,	---	16479	7342,	---
16480	/* ST_B */	---	16480	/* ST_B */	---
16481	7342,	---	16481	7342,	---
16482	/* ST_D */	---	16482	/* ST_D */	---
16483	7345,	---	16483	7345,	---
16484	/* ST_H */	---	16484	/* ST_H */	---
16485	7348,	---	16485	7348,	---
16486	/* ST_W */	---	16486	/* ST_W */	---
16487	7351,	---	16487	7351,	---
16488	/* SUB */	---	16488	/* SUB */	---
16489	7354,	---	16489	7354,	---
16490	/* SUBQH_PH */	---	16490	/* SUBQH_PH */	---
16491	7357,	---	16491	7357,	---
16492	/* SUBQH_PH_MMR2 */	---	16492	/* SUBQH_PH_MMR2 */	---
16493	7360,	---	16493	7360,	---
16494	/* SUBQH_R_PH */	---	16494	/* SUBQH_R_PH */	---
16495	7363,	---	16495	7363,	---
16496	/* SUBQH_R_PH_MMR2 */	---	16496	/* SUBQH_R_PH_MMR2 */	---
16497	7366,	---	16497	7366,	---
16498	/* SUBQH_R_W */	---	16498	/* SUBQH_R_W */	---
16499	7369,	---	16499	7369,	---
16500	/* SUBQH_R_W_MMR2 */	---	16500	/* SUBQH_R_W_MMR2 */	---
16501	7372,	---	16501	7372,	---
16502	/* SUBQH_W */	---	16502	/* SUBQH_W */	---
16503	7375,	---	16503	7375,	---
16504	/* SUBQH_W_MMR2 */	---	16504	/* SUBQH_W_MMR2 */	---
16505	7378,	---	16505	7378,	---
16506	/* SUBQ_PH */	---	16506	/* SUBQ_PH */	---
16507	7381,	---	16507	7381,	---
16508	/* SUBQ_PH_MM */	---	16508	/* SUBQ_PH_MM */	---
16509	7384,	---	16509	7384,	---
16510	/* SUBQ_S_PH */	---	16510	/* SUBQ_S_PH */	---
16511	7387,	---	16511	7387,	---
16512	/* SUBQ_S_PH_MM */	---	16512	/* SUBQ_S_PH_MM */	---
16513	7390,	---	16513	7390,	---
16514	/* SUBQ_S_W */	---	16514	/* SUBQ_S_W */	---
16515	7393,	---	16515	7393,	---
16516	/* SUBQ_S_W_MM */	---	16516	/* SUBQ_S_W_MM */	---
16517	7396,	---	16517	7396,	---
16518	/* SUBSUS_U_B */	---	16518	/* SUBSUS_U_B */	---
16519	7399,	---	16519	7399,	---
16520	/* SUBSUS_U_D */	---	16520	/* SUBSUS_U_D */	---
16521	7402,	---	16521	7402,	---
16522	/* SUBSUS_U_H */	---	16522	/* SUBSUS_U_H */	---
16523	7405,	---	16523	7405,	---
16524	/* SUBSUS_U_W */	---	16524	/* SUBSUS_U_W */	---
16525	7408,	---	16525	7408,	---
16526	/* SUBSUU_S_B */	---	16526	/* SUBSUU_S_B */	---
16527	7411,	---	16527	7411,	---
16528	/* SUBSUU_S_D */	---	16528	/* SUBSUU_S_D */	---
16529	7414,	---	16529	7414,	---
16530	/* SUBSUU_S_H */	---	16530	/* SUBSUU_S_H */	---
16531	7417,	---	16531	7417,	---
16532	/* SUBSUU_S_W */	---	16532	/* SUBSUU_S_W */	---
16533	7420,	---	16533	7420,	---
16534	/* SUBS_S_B */	---	16534	/* SUBS_S_B */	---
16535	7423,	---	16535	7423,	---
16536	/* SUBS_S_D */	---	16536	/* SUBS_S_D */	---
16537	7426,	---	16537	7426,	---
16538	/* SUBS_S_H */	---	16538	/* SUBS_S_H */	---
16539	7429,	---	16539	7429,	---
16540	/* SUBS_S_W */	---	16540	/* SUBS_S_W */	---
16541	7432,	---	16541	7432,	---
16542	/* SUBS_U_B */	---	16542	/* SUBS_U_B */	---
16543	7435,	---	16543	7435,	---
16544	/* SUBS_U_D */	---	16544	/* SUBS_U_D */	---
16545	7438,	---	16545	7438,	---
16546	/* SUBS_U_H */	---	16546	/* SUBS_U_H */	---
16547	7441,	---	16547	7441,	---
16548	/* SUBS_U_W */	---	16548	/* SUBS_U_W */	---
16549	7444,	---	16549	7444,	---
16550	/* SUBU16_MM */	---	16550	/* SUBU16_MM */	---
16551	7447,	---	16551	7447,	---
16552	/* SUBU16_MMR6 */	---	16552	/* SUBU16_MMR6 */	---
16553	7450,	---	16553	7450,	---
16554	/* SUBUH_QB */	---	16554	/* SUBUH_QB */	---
16555	7453,	---	16555	7453,	---
16556	/* SUBUH_QB_MMR2 */	---	16556	/* SUBUH_QB_MMR2 */	---
16557	7456,	---	16557	7456,	---
16558	/* SUBUH_R_QB */	---	16558	/* SUBUH_R_QB */	---
16559	7459,	---	16559	7459,	---
16560	/* SUBUH_R_QB_MMR2 */	---	16560	/* SUBUH_R_QB_MMR2 */	---
16561	7462,	---	16561	7462,	---
16562	/* SUBU_MMR6 */	---	16562	/* SUBU_MMR6 */	---
16563	7465,	---	16563	7465,	---
16564	/* SUBU_PH */	---	16564	/* SUBU_PH */	---
16565	7468,	---	16565	7468,	---
16566	/* SUBU_PH_MMR2 */	---	16566	/* SUBU_PH_MMR2 */	---
16567	7471,	---	16567	7471,	---
16568	/* SUBU_QB */	---	16568	/* SUBU_QB */	---
16569	7474,	---	16569	7474,	---
16570	/* SUBU_QB_MM */	---	16570	/* SUBU_QB_MM */	---
16571	7477,	---	16571	7477,	---
16572	/* SUBU_S_PH */	---	16572	/* SUBU_S_PH */	---
16573	7480,	---	16573	7480,	---
16574	/* SUBU_S_PH_MMR2 */	---	16574	/* SUBU_S_PH_MMR2 */	---
16575	7483,	---	16575	7483,	---
16576	/* SUBU_S_QB */	---	16576	/* SUBU_S_QB */	---
16577	7486,	---	16577	7486,	---
16578	/* SUBU_S_QB_MM */	---	16578	/* SUBU_S_QB_MM */	---
16579	7489,	---	16579	7489,	---
16580	/* SUBVI_B */	---	16580	/* SUBVI_B */	---
16581	7492,	---	16581	7492,	---
16582	/* SUBVI_D */	---	16582	/* SUBVI_D */	---
16583	7495,	---	16583	7495,	---
16584	/* SUBVI_H */	---	16584	/* SUBVI_H */	---
16585	7498,	---	16585	7498,	---
16586	/* SUBVI_W */	---	16586	/* SUBVI_W */	---
16587	7501,	---	16587	7501,	---
16588	/* SUBV_B */	---	16588	/* SUBV_B */	---
16589	7504,	---	16589	7504,	---
16590	/* SUBV_D */	---	16590	/* SUBV_D */	---
16591	7507,	---	16591	7507,	---
16592	/* SUBV_H */	---	16592	/* SUBV_H */	---
16593	7510,	---	16593	7510,	---
16594	/* SUBV_W */	---	16594	/* SUBV_W */	---
16595	7513,	---	16595	7513,	---
16596	/* SUB_MM */	---	16596	/* SUB_MM */	---
16597	7516,	---	16597	7516,	---
16598	/* SUB_MMR6 */	---	16598	/* SUB_MMR6 */	---
16599	7519,	---	16599	7519,	---
16600	/* SUBu */	---	16600	/* SUBu */	---
16601	7522,	---	16601	7522,	---
16602	/* SUBu_MM */	---	16602	/* SUBu_MM */	---
16603	7525,	---	16603	7525,	---
16604	/* SUXC1 */	---	16604	/* SUXC1 */	---
16605	7528,	---	16605	7528,	---
16606	/* SUXC164 */	---	16606	/* SUXC164 */	---
16607	7531,	---	16607	7531,	---
16608	/* SUXC1_MM */	---	16608	/* SUXC1_MM */	---
16609	7534,	---	16609	7534,	---
16610	/* SW */	---	16610	/* SW */	---
16611	7537,	---	16611	7537,	---
16612	/* SW16_MM */	---	16612	/* SW16_MM */	---
16613	7540,	---	16613	7540,	---
16614	/* SW16_MMR6 */	---	16614	/* SW16_MMR6 */	---
16615	7543,	---	16615	7543,	---
16616	/* SW64 */	---	16616	/* SW64 */	---
16617	7546,	---	16617	7546,	---
16618	/* SWC1 */	---	16618	/* SWC1 */	---
16619	7549,	---	16619	7549,	---
16620	/* SWC1_MM */	---	16620	/* SWC1_MM */	---
16621	7552,	---	16621	7552,	---
16622	/* SWC2 */	---	16622	/* SWC2 */	---
16623	7555,	---	16623	7555,	---
16624	/* SWC2_MMR6 */	---	16624	/* SWC2_MMR6 */	---
16625	7558,	---	16625	7558,	---
16626	/* SWC2_R6 */	---	16626	/* SWC2_R6 */	---
16627	7561,	---	16627	7561,	---
16628	/* SWC3 */	---	16628	/* SWC3 */	---
16629	7564,	---	16629	7564,	---
16630	/* SWDSP */	---	16630	/* SWDSP */	---
16631	7567,	---	16631	7567,	---
16632	/* SWDSP_MM */	---	16632	/* SWDSP_MM */	---
16633	7570,	---	16633	7570,	---
16634	/* SWE */	---	16634	/* SWE */	---
16635	7573,	---	16635	7573,	---
16636	/* SWE_MM */	---	16636	/* SWE_MM */	---
16637	7576,	---	16637	7576,	---
16638	/* SWL */	---	16638	/* SWL */	---
16639	7579,	---	16639	7579,	---
16640	/* SWL64 */	---	16640	/* SWL64 */	---
16641	7582,	---	16641	7582,	---
16642	/* SWLE */	---	16642	/* SWLE */	---
16643	7585,	---	16643	7585,	---
16644	/* SWLE_MM */	---	16644	/* SWLE_MM */	---
16645	7588,	---	16645	7588,	---
16646	/* SWL_MM */	---	16646	/* SWL_MM */	---
16647	7591,	---	16647	7591,	---
16648	/* SWM16_MM */	---	16648	/* SWM16_MM */	---
16649	7594,	---	16649	7594,	---
16650	/* SWM16_MMR6 */	---	16650	/* SWM16_MMR6 */	---
16651	7597,	---	16651	7597,	---
16652	/* SWM32_MM */	---	16652	/* SWM32_MM */	---
16653	7600,	---	16653	7600,	---
16654	/* SWP_MM */	---	16654	/* SWP_MM */	---
16655	7603,	---	16655	7603,	---
16656	/* SWR */	---	16656	/* SWR */	---
16657	7607,	---	16657	7607,	---
16658	/* SWR64 */	---	16658	/* SWR64 */	---
16659	7610,	---	16659	7610,	---
16660	/* SWRE */	---	16660	/* SWRE */	---
16661	7613,	---	16661	7613,	---
16662	/* SWRE_MM */	---	16662	/* SWRE_MM */	---
16663	7616,	---	16663	7616,	---
16664	/* SWR_MM */	---	16664	/* SWR_MM */	---
16665	7619,	---	16665	7619,	---
16666	/* SWSP_MM */	---	16666	/* SWSP_MM */	---
16667	7622,	---	16667	7622,	---
16668	/* SWSP_MMR6 */	---	16668	/* SWSP_MMR6 */	---
16669	7625,	---	16669	7625,	---
16670	/* SWXC1 */	---	16670	/* SWXC1 */	---
16671	7628,	---	16671	7628,	---
16672	/* SWXC1_MM */	---	16672	/* SWXC1_MM */	---
16673	7631,	---	16673	7631,	---
16674	/* SW_MM */	---	16674	/* SW_MM */	---
16675	7634,	---	16675	7634,	---
16676	/* SW_MMR6 */	---	16676	/* SW_MMR6 */	---
16677	7637,	---	16677	7637,	---
16678	/* SYNC */	---	16678	/* SYNC */	---
16679	7640,	---	16679	7640,	---
16680	/* SYNCI */	---	16680	/* SYNCI */	---
16681	7641,	---	16681	7641,	---
16682	/* SYNCI_MM */	---	16682	/* SYNCI_MM */	---
16683	7643,	---	16683	7643,	---
16684	/* SYNCI_MMR6 */	---	16684	/* SYNCI_MMR6 */	---
16685	7645,	---	16685	7645,	---
16686	/* SYNC_MM */	---	16686	/* SYNC_MM */	---
16687	7647,	---	16687	7647,	---
16688	/* SYNC_MMR6 */	---	16688	/* SYNC_MMR6 */	---
16689	7648,	---	16689	7648,	---
16690	/* SYSCALL */	---	16690	/* SYSCALL */	---
16691	7649,	---	16691	7649,	---
16692	/* SYSCALL_MM */	---	16692	/* SYSCALL_MM */	---
16693	7650,	---	16693	7650,	---
16694	/* Save16 */	---	16694	/* Save16 */	---
16695	7651,	---	16695	7651,	---
16696	/* SaveX16 */	---	16696	/* SaveX16 */	---
16697	7651,	---	16697	7651,	---
16698	/* SbRxRyOffMemX16 */	---	16698	/* SbRxRyOffMemX16 */	---
16699	7651,	---	16699	7651,	---
16700	/* SebRx16 */	---	16700	/* SebRx16 */	---
16701	7654,	---	16701	7654,	---
16702	/* SehRx16 */	---	16702	/* SehRx16 */	---
16703	7656,	---	16703	7656,	---
16704	/* ShRxRyOffMemX16 */	---	16704	/* ShRxRyOffMemX16 */	---
16705	7658,	---	16705	7658,	---
16706	/* SllX16 */	---	16706	/* SllX16 */	---
16707	7661,	---	16707	7661,	---
16708	/* SllvRxRy16 */	---	16708	/* SllvRxRy16 */	---
16709	7664,	---	16709	7664,	---
16710	/* SltRxRy16 */	---	16710	/* SltRxRy16 */	---
16711	7667,	---	16711	7667,	---
16712	/* SltiRxImm16 */	---	16712	/* SltiRxImm16 */	---
16713	7669,	---	16713	7669,	---
16714	/* SltiRxImmX16 */	---	16714	/* SltiRxImmX16 */	---
16715	7671,	---	16715	7671,	---
16716	/* SltiuRxImm16 */	---	16716	/* SltiuRxImm16 */	---
16717	7673,	---	16717	7673,	---
16718	/* SltiuRxImmX16 */	---	16718	/* SltiuRxImmX16 */	---
16719	7675,	---	16719	7675,	---
16720	/* SltuRxRy16 */	---	16720	/* SltuRxRy16 */	---
16721	7677,	---	16721	7677,	---
16722	/* SraX16 */	---	16722	/* SraX16 */	---
16723	7679,	---	16723	7679,	---
16724	/* SravRxRy16 */	---	16724	/* SravRxRy16 */	---
16725	7682,	---	16725	7682,	---
16726	/* SrlX16 */	---	16726	/* SrlX16 */	---
16727	7685,	---	16727	7685,	---
16728	/* SrlvRxRy16 */	---	16728	/* SrlvRxRy16 */	---
16729	7688,	---	16729	7688,	---
16730	/* SubuRxRyRz16 */	---	16730	/* SubuRxRyRz16 */	---
16731	7691,	---	16731	7691,	---
16732	/* SwRxRyOffMemX16 */	---	16732	/* SwRxRyOffMemX16 */	---
16733	7694,	---	16733	7694,	---
16734	/* SwRxSpImmX16 */	---	16734	/* SwRxSpImmX16 */	---
16735	7697,	---	16735	7697,	---
16736	/* TEQ */	---	16736	/* TEQ */	---
16737	7700,	---	16737	7700,	---
16738	/* TEQI */	---	16738	/* TEQI */	---
16739	7703,	---	16739	7703,	---
16740	/* TEQI_MM */	---	16740	/* TEQI_MM */	---
16741	7705,	---	16741	7705,	---
16742	/* TEQ_MM */	---	16742	/* TEQ_MM */	---
16743	7707,	---	16743	7707,	---
16744	/* TGE */	---	16744	/* TGE */	---
16745	7710,	---	16745	7710,	---
16746	/* TGEI */	---	16746	/* TGEI */	---
16747	7713,	---	16747	7713,	---
16748	/* TGEIU */	---	16748	/* TGEIU */	---
16749	7715,	---	16749	7715,	---
16750	/* TGEIU_MM */	---	16750	/* TGEIU_MM */	---
16751	7717,	---	16751	7717,	---
16752	/* TGEI_MM */	---	16752	/* TGEI_MM */	---
16753	7719,	---	16753	7719,	---
16754	/* TGEU */	---	16754	/* TGEU */	---
16755	7721,	---	16755	7721,	---
16756	/* TGEU_MM */	---	16756	/* TGEU_MM */	---
16757	7724,	---	16757	7724,	---
16758	/* TGE_MM */	---	16758	/* TGE_MM */	---
16759	7727,	---	16759	7727,	---
16760	/* TLBGINV */	---	16760	/* TLBGINV */	---
16761	7730,	---	16761	7730,	---
16762	/* TLBGINVF */	---	16762	/* TLBGINVF */	---
16763	7730,	---	16763	7730,	---
16764	/* TLBGINVF_MM */	---	16764	/* TLBGINVF_MM */	---
16765	7730,	---	16765	7730,	---
16766	/* TLBGINV_MM */	---	16766	/* TLBGINV_MM */	---
16767	7730,	---	16767	7730,	---
16768	/* TLBGP */	---	16768	/* TLBGP */	---
16769	7730,	---	16769	7730,	---
16770	/* TLBGP_MM */	---	16770	/* TLBGP_MM */	---
16771	7730,	---	16771	7730,	---
16772	/* TLBGR */	---	16772	/* TLBGR */	---
16773	7730,	---	16773	7730,	---
16774	/* TLBGR_MM */	---	16774	/* TLBGR_MM */	---
16775	7730,	---	16775	7730,	---
16776	/* TLBGWI */	---	16776	/* TLBGWI */	---
16777	7730,	---	16777	7730,	---
16778	/* TLBGWI_MM */	---	16778	/* TLBGWI_MM */	---
16779	7730,	---	16779	7730,	---
16780	/* TLBGWR */	---	16780	/* TLBGWR */	---
16781	7730,	---	16781	7730,	---
16782	/* TLBGWR_MM */	---	16782	/* TLBGWR_MM */	---
16783	7730,	---	16783	7730,	---
16784	/* TLBINV */	---	16784	/* TLBINV */	---
16785	7730,	---	16785	7730,	---
16786	/* TLBINVF */	---	16786	/* TLBINVF */	---
16787	7730,	---	16787	7730,	---
16788	/* TLBINVF_MMR6 */	---	16788	/* TLBINVF_MMR6 */	---
16789	7730,	---	16789	7730,	---
16790	/* TLBINV_MMR6 */	---	16790	/* TLBINV_MMR6 */	---
16791	7730,	---	16791	7730,	---
16792	/* TLBP */	---	16792	/* TLBP */	---
16793	7730,	---	16793	7730,	---
16794	/* TLBP_MM */	---	16794	/* TLBP_MM */	---
16795	7730,	---	16795	7730,	---
16796	/* TLBR */	---	16796	/* TLBR */	---
16797	7730,	---	16797	7730,	---
16798	/* TLBR_MM */	---	16798	/* TLBR_MM */	---
16799	7730,	---	16799	7730,	---
16800	/* TLBWI */	---	16800	/* TLBWI */	---
16801	7730,	---	16801	7730,	---
16802	/* TLBWI_MM */	---	16802	/* TLBWI_MM */	---
16803	7730,	---	16803	7730,	---
16804	/* TLBWR */	---	16804	/* TLBWR */	---
16805	7730,	---	16805	7730,	---
16806	/* TLBWR_MM */	---	16806	/* TLBWR_MM */	---
16807	7730,	---	16807	7730,	---
16808	/* TLT */	---	16808	/* TLT */	---
16809	7730,	---	16809	7730,	---
16810	/* TLTI */	---	16810	/* TLTI */	---
16811	7733,	---	16811	7733,	---
16812	/* TLTIU_MM */	---	16812	/* TLTIU_MM */	---
16813	7735,	---	16813	7735,	---
16814	/* TLTI_MM */	---	16814	/* TLTI_MM */	---
16815	7737,	---	16815	7737,	---
16816	/* TLTU */	---	16816	/* TLTU */	---
16817	7739,	---	16817	7739,	---
16818	/* TLTU_MM */	---	16818	/* TLTU_MM */	---
16819	7742,	---	16819	7742,	---
16820	/* TLT_MM */	---	16820	/* TLT_MM */	---
16821	7745,	---	16821	7745,	---
16822	/* TNE */	---	16822	/* TNE */	---
16823	7748,	---	16823	7748,	---
16824	/* TNEI */	---	16824	/* TNEI */	---
16825	7751,	---	16825	7751,	---
16826	/* TNEI_MM */	---	16826	/* TNEI_MM */	---
16827	7753,	---	16827	7753,	---
16828	/* TNE_MM */	---	16828	/* TNE_MM */	---
16829	7755,	---	16829	7755,	---
16830	/* TRUNC_L_D64 */	---	16830	/* TRUNC_L_D64 */	---
16831	7758,	---	16831	7758,	---
16832	/* TRUNC_L_D_MMR6 */	---	16832	/* TRUNC_L_D_MMR6 */	---
16833	7760,	---	16833	7760,	---
16834	/* TRUNC_L_S */	---	16834	/* TRUNC_L_S */	---
16835	7762,	---	16835	7762,	---
16836	/* TRUNC_L_S_MMR6 */	---	16836	/* TRUNC_L_S_MMR6 */	---
16837	7764,	---	16837	7764,	---
16838	/* TRUNC_W_D32 */	---	16838	/* TRUNC_W_D32 */	---
16839	7766,	---	16839	7766,	---
16840	/* TRUNC_W_D64 */	---	16840	/* TRUNC_W_D64 */	---
16841	7768,	---	16841	7768,	---
16842	/* TRUNC_W_D_MMR6 */	---	16842	/* TRUNC_W_D_MMR6 */	---
16843	7770,	---	16843	7770,	---
16844	/* TRUNC_W_MM */	---	16844	/* TRUNC_W_MM */	---
16845	7772,	---	16845	7772,	---
16846	/* TRUNC_W_S */	---	16846	/* TRUNC_W_S */	---
16847	7774,	---	16847	7774,	---
16848	/* TRUNC_W_S_MM */	---	16848	/* TRUNC_W_S_MM */	---
16849	7776,	---	16849	7776,	---
16850	/* TRUNC_W_S_MMR6 */	---	16850	/* TRUNC_W_S_MMR6 */	---
16851	7778,	---	16851	7778,	---
16852	/* TTLTIU */	---	16852	/* TTLTIU */	---
16853	7780,	---	16853	7780,	---
16854	/* UDIV */	---	16854	/* UDIV */	---
16855	7782,	---	16855	7782,	---
16856	/* UDIV_MM */	---	16856	/* UDIV_MM */	---
16857	7784,	---	16857	7784,	---
16858	/* V3MULU */	---	16858	/* V3MULU */	---
16859	7786,	---	16859	7786,	---
16860	/* VMM0 */	---	16860	/* VMM0 */	---
16861	7789,	---	16861	7789,	---
16862	/* VMULU */	---	16862	/* VMULU */	---
16863	7792,	---	16863	7792,	---
16864	/* VSHF_B */	---	16864	/* VSHF_B */	---
16865	7795,	---	16865	7795,	---
16866	/* VSHF_D */	---	16866	/* VSHF_D */	---
16867	7799,	---	16867	7799,	---
16868	/* VSHF_H */	---	16868	/* VSHF_H */	---
16869	7803,	---	16869	7803,	---
16870	/* VSHF_W */	---	16870	/* VSHF_W */	---
16871	7807,	---	16871	7807,	---
16872	/* WAIT */	---	16872	/* WAIT */	---
16873	7811,	---	16873	7811,	---
16874	/* WAIT_MM */	---	16874	/* WAIT_MM */	---
16875	7811,	---	16875	7811,	---
16876	/* WAIT_MMR6 */	---	16876	/* WAIT_MMR6 */	---
16877	7812,	---	16877	7812,	---
16878	/* WRDSP */	---	16878	/* WRDSP */	---
16879	7813,	---	16879	7813,	---
16880	/* WRDSP_MM */	---	16880	/* WRDSP_MM */	---
16881	7815,	---	16881	7815,	---
16882	/* WRPGPR_MMR6 */	---	16882	/* WRPGPR_MMR6 */	---
16883	7817,	---	16883	7817,	---
16884	/* WSBH */	---	16884	/* WSBH */	---
16885	7819,	---	16885	7819,	---
16886	/* WSBH_MM */	---	16886	/* WSBH_MM */	---
16887	7821,	---	16887	7821,	---
16888	/* WSBH_MMR6 */	---	16888	/* WSBH_MMR6 */	---
16889	7823,	---	16889	7823,	---
16890	/* XOR */	---	16890	/* XOR */	---
16891	7825,	---	16891	7825,	---
16892	/* XOR16_MM */	---	16892	/* XOR16_MM */	---
16893	7828,	---	16893	7828,	---
16894	/* XOR16_MMR6 */	---	16894	/* XOR16_MMR6 */	---
16895	7831,	---	16895	7831,	---
16896	/* XOR64 */	---	16896	/* XOR64 */	---
16897	7834,	---	16897	7834,	---
16898	/* XORI_B */	---	16898	/* XORI_B */	---
16899	7837,	---	16899	7837,	---
16900	/* XORI_MMR6 */	---	16900	/* XORI_MMR6 */	---
16901	7840,	---	16901	7840,	---
16902	/* XOR_MM */	---	16902	/* XOR_MM */	---
16903	7843,	---	16903	7843,	---
16904	/* XOR_MMR6 */	---	16904	/* XOR_MMR6 */	---
16905	7846,	---	16905	7846,	---
16906	/* XOR_V */	---	16906	/* XOR_V */	---
16907	7849,	---	16907	7849,	---
16908	/* XORi */	---	16908	/* XORi */	---
16909	7852,	---	16909	7852,	---
16910	/* XORi64 */	---	16910	/* XORi64 */	---
16911	7855,	---	16911	7855,	---
16912	/* XORi_MM */	---	16912	/* XORi_MM */	---
16913	7858,	---	16913	7858,	---
16914	/* XorRxRxRy16 */	---	16914	/* XorRxRxRy16 */	---
16915	7861,	---	16915	7861,	---
16916	/* YIELD */	---	16916	/* YIELD */	---
16917	7864,	---	16917	7864,	---
16918	};	---	16918	};	---
16919		---	16919		---
16920	using namespace OpTypes;	---	16920	using namespace OpTypes;	---
16921	static const int16_t OpcodeOperandTypes[] = {	---	16921	static const int16_t OpcodeOperandTypes[] = {	---
16922		---	16922		---
16923	/* PHI */	---	16923	/* PHI */	---
16924	-1,	---	16924	-1,	---
16925	/* INLINEASM */	---	16925	/* INLINEASM */	---
16926	/* INLINEASM_BR */	---	16926	/* INLINEASM_BR */	---
16927	/* CFI_INSTRUCTION */	---	16927	/* CFI_INSTRUCTION */	---
16928	i32imm,	---	16928	i32imm,	---
16929	/* EH_LABEL */	---	16929	/* EH_LABEL */	---
16930	i32imm,	---	16930	i32imm,	---
16931	/* GC_LABEL */	---	16931	/* GC_LABEL */	---
16932	i32imm,	---	16932	i32imm,	---
16933	/* ANNOTATION_LABEL */	---	16933	/* ANNOTATION_LABEL */	---
16934	i32imm,	---	16934	i32imm,	---
16935	/* KILL */	---	16935	/* KILL */	---
16936	/* EXTRACT_SUBREG */	---	16936	/* EXTRACT_SUBREG */	---
16937	-1, -1, i32imm,	---	16937	-1, -1, i32imm,	---
16938	/* INSERT_SUBREG */	---	16938	/* INSERT_SUBREG */	---
16939	-1, -1, -1, i32imm,	---	16939	-1, -1, -1, i32imm,	---
16940	/* IMPLICIT_DEF */	---	16940	/* IMPLICIT_DEF */	---
16941	-1,	---	16941	-1,	---
16942	/* SUBREG_TO_REG */	---	16942	/* SUBREG_TO_REG */	---
16943	-1, -1, -1, i32imm,	---	16943	-1, -1, -1, i32imm,	---
16944	/* COPY_TO_REGCLASS */	---	16944	/* COPY_TO_REGCLASS */	---
16945	-1, -1, i32imm,	---	16945	-1, -1, i32imm,	---
16946	/* DBG_VALUE */	---	16946	/* DBG_VALUE */	---
16947	/* DBG_VALUE_LIST */	---	16947	/* DBG_VALUE_LIST */	---
16948	/* DBG_INSTR_REF */	---	16948	/* DBG_INSTR_REF */	---
16949	/* DBG_PHI */	---	16949	/* DBG_PHI */	---
16950	/* DBG_LABEL */	---	16950	/* DBG_LABEL */	---
16951	-1,	---	16951	-1,	---
16952	/* REG_SEQUENCE */	---	16952	/* REG_SEQUENCE */	---
16953	-1, -1,	---	16953	-1, -1,	---
16954	/* COPY */	---	16954	/* COPY */	---
16955	-1, -1,	---	16955	-1, -1,	---
16956	/* BUNDLE */	---	16956	/* BUNDLE */	---
16957	/* LIFETIME_START */	---	16957	/* LIFETIME_START */	---
16958	i32imm,	---	16958	i32imm,	---
16959	/* LIFETIME_END */	---	16959	/* LIFETIME_END */	---
16960	i32imm,	---	16960	i32imm,	---
16961	/* PSEUDO_PROBE */	---	16961	/* PSEUDO_PROBE */	---
16962	i64imm, i64imm, i8imm, i32imm,	---	16962	i64imm, i64imm, i8imm, i32imm,	---
16963	/* ARITH_FENCE */	---	16963	/* ARITH_FENCE */	---
16964	-1, -1,	---	16964	-1, -1,	---
16965	/* STACKMAP */	---	16965	/* STACKMAP */	---
16966	i64imm, i32imm,	---	16966	i64imm, i32imm,	---
16967	/* FENTRY_CALL */	---	16967	/* FENTRY_CALL */	---
16968	/* PATCHPOINT */	---	16968	/* PATCHPOINT */	---
16969	-1, i64imm, i32imm, -1, i32imm, i32imm,	---	16969	-1, i64imm, i32imm, -1, i32imm, i32imm,	---
16970	/* LOAD_STACK_GUARD */	---	16970	/* LOAD_STACK_GUARD */	---
16971	-1,	---	16971	-1,	---
16972	/* PREALLOCATED_SETUP */	---	16972	/* PREALLOCATED_SETUP */	---
16973	i32imm,	---	16973	i32imm,	---
16974	/* PREALLOCATED_ARG */	---	16974	/* PREALLOCATED_ARG */	---
16975	-1, i32imm, i32imm,	---	16975	-1, i32imm, i32imm,	---
16976	/* STATEPOINT */	---	16976	/* STATEPOINT */	---
16977	/* LOCAL_ESCAPE */	---	16977	/* LOCAL_ESCAPE */	---
16978	-1, i32imm,	---	16978	-1, i32imm,	---
16979	/* FAULTING_OP */	---	16979	/* FAULTING_OP */	---
16980	-1,	---	16980	-1,	---
16981	/* PATCHABLE_OP */	---	16981	/* PATCHABLE_OP */	---
16982	/* PATCHABLE_FUNCTION_ENTER */	---	16982	/* PATCHABLE_FUNCTION_ENTER */	---
16983	/* PATCHABLE_RET */	---	16983	/* PATCHABLE_RET */	---
16984	/* PATCHABLE_FUNCTION_EXIT */	---	16984	/* PATCHABLE_FUNCTION_EXIT */	---
16985	/* PATCHABLE_TAIL_CALL */	---	16985	/* PATCHABLE_TAIL_CALL */	---
16986	/* PATCHABLE_EVENT_CALL */	---	16986	/* PATCHABLE_EVENT_CALL */	---
16987	-1, -1,	---	16987	-1, -1,	---
16988	/* PATCHABLE_TYPED_EVENT_CALL */	---	16988	/* PATCHABLE_TYPED_EVENT_CALL */	---
16989	-1, -1, -1,	---	16989	-1, -1, -1,	---
16990	/* ICALL_BRANCH_FUNNEL */	---	16990	/* ICALL_BRANCH_FUNNEL */	---
16991	/* MEMBARRIER */	---	16991	/* MEMBARRIER */	---
16992	/* G_ASSERT_SEXT */	---	16992	/* G_ASSERT_SEXT */	---
16993	type0, type0, untyped_imm_0,	---	16993	type0, type0, untyped_imm_0,	---
16994	/* G_ASSERT_ZEXT */	---	16994	/* G_ASSERT_ZEXT */	---
16995	type0, type0, untyped_imm_0,	---	16995	type0, type0, untyped_imm_0,	---
16996	/* G_ASSERT_ALIGN */	---	16996	/* G_ASSERT_ALIGN */	---
16997	type0, type0, untyped_imm_0,	---	16997	type0, type0, untyped_imm_0,	---
16998	/* G_ADD */	---	16998	/* G_ADD */	---
16999	type0, type0, type0,	---	16999	type0, type0, type0,	---
17000	/* G_SUB */	---	17000	/* G_SUB */	---
17001	type0, type0, type0,	---	17001	type0, type0, type0,	---
17002	/* G_MUL */	---	17002	/* G_MUL */	---
17003	type0, type0, type0,	---	17003	type0, type0, type0,	---
17004	/* G_SDIV */	---	17004	/* G_SDIV */	---
17005	type0, type0, type0,	---	17005	type0, type0, type0,	---
17006	/* G_UDIV */	---	17006	/* G_UDIV */	---
17007	type0, type0, type0,	---	17007	type0, type0, type0,	---
17008	/* G_SREM */	---	17008	/* G_SREM */	---
17009	type0, type0, type0,	---	17009	type0, type0, type0,	---
17010	/* G_UREM */	---	17010	/* G_UREM */	---
17011	type0, type0, type0,	---	17011	type0, type0, type0,	---
17012	/* G_SDIVREM */	---	17012	/* G_SDIVREM */	---
17013	type0, type0, type0, type0,	---	17013	type0, type0, type0, type0,	---
17014	/* G_UDIVREM */	---	17014	/* G_UDIVREM */	---
17015	type0, type0, type0, type0,	---	17015	type0, type0, type0, type0,	---
17016	/* G_AND */	---	17016	/* G_AND */	---
17017	type0, type0, type0,	---	17017	type0, type0, type0,	---
17018	/* G_OR */	---	17018	/* G_OR */	---
17019	type0, type0, type0,	---	17019	type0, type0, type0,	---
17020	/* G_XOR */	---	17020	/* G_XOR */	---
17021	type0, type0, type0,	---	17021	type0, type0, type0,	---
17022	/* G_IMPLICIT_DEF */	---	17022	/* G_IMPLICIT_DEF */	---
17023	type0,	---	17023	type0,	---
17024	/* G_PHI */	---	17024	/* G_PHI */	---
17025	type0,	---	17025	type0,	---
17026	/* G_FRAME_INDEX */	---	17026	/* G_FRAME_INDEX */	---
17027	type0, -1,	---	17027	type0, -1,	---
17028	/* G_GLOBAL_VALUE */	---	17028	/* G_GLOBAL_VALUE */	---
17029	type0, -1,	---	17029	type0, -1,	---
17030	/* G_CONSTANT_POOL */	---	17030	/* G_CONSTANT_POOL */	---
17031	type0, -1,	---	17031	type0, -1,	---
17032	/* G_EXTRACT */	---	17032	/* G_EXTRACT */	---
17033	type0, type1, untyped_imm_0,	---	17033	type0, type1, untyped_imm_0,	---
17034	/* G_UNMERGE_VALUES */	---	17034	/* G_UNMERGE_VALUES */	---
17035	type0, type1,	---	17035	type0, type1,	---
17036	/* G_INSERT */	---	17036	/* G_INSERT */	---
17037	type0, type0, type1, untyped_imm_0,	---	17037	type0, type0, type1, untyped_imm_0,	---
17038	/* G_MERGE_VALUES */	---	17038	/* G_MERGE_VALUES */	---
17039	type0, type1,	---	17039	type0, type1,	---
17040	/* G_BUILD_VECTOR */	---	17040	/* G_BUILD_VECTOR */	---
17041	type0, type1,	---	17041	type0, type1,	---
17042	/* G_BUILD_VECTOR_TRUNC */	---	17042	/* G_BUILD_VECTOR_TRUNC */	---
17043	type0, type1,	---	17043	type0, type1,	---
17044	/* G_CONCAT_VECTORS */	---	17044	/* G_CONCAT_VECTORS */	---
17045	type0, type1,	---	17045	type0, type1,	---
17046	/* G_PTRTOINT */	---	17046	/* G_PTRTOINT */	---
17047	type0, type1,	---	17047	type0, type1,	---
17048	/* G_INTTOPTR */	---	17048	/* G_INTTOPTR */	---
17049	type0, type1,	---	17049	type0, type1,	---
17050	/* G_BITCAST */	---	17050	/* G_BITCAST */	---
17051	type0, type1,	---	17051	type0, type1,	---
17052	/* G_FREEZE */	---	17052	/* G_FREEZE */	---
17053	type0, type0,	---	17053	type0, type0,	---
17054	/* G_CONSTANT_FOLD_BARRIER */	---	17054	/* G_CONSTANT_FOLD_BARRIER */	---
17055	type0, type0,	---	17055	type0, type0,	---
17056	/* G_INTRINSIC_FPTRUNC_ROUND */	---	17056	/* G_INTRINSIC_FPTRUNC_ROUND */	---
17057	type0, type1, i32imm,	---	17057	type0, type1, i32imm,	---
17058	/* G_INTRINSIC_TRUNC */	---	17058	/* G_INTRINSIC_TRUNC */	---
17059	type0, type0,	---	17059	type0, type0,	---
17060	/* G_INTRINSIC_ROUND */	---	17060	/* G_INTRINSIC_ROUND */	---
17061	type0, type0,	---	17061	type0, type0,	---
17062	/* G_INTRINSIC_LRINT */	---	17062	/* G_INTRINSIC_LRINT */	---
17063	type0, type1,	---	17063	type0, type1,	---
17064	/* G_INTRINSIC_ROUNDEVEN */	---	17064	/* G_INTRINSIC_ROUNDEVEN */	---
17065	type0, type0,	---	17065	type0, type0,	---
17066	/* G_READCYCLECOUNTER */	---	17066	/* G_READCYCLECOUNTER */	---
17067	type0,	---	17067	type0,	---
17068	/* G_LOAD */	---	17068	/* G_LOAD */	---
17069	type0, ptype1,	---	17069	type0, ptype1,	---
17070	/* G_SEXTLOAD */	---	17070	/* G_SEXTLOAD */	---
17071	type0, ptype1,	---	17071	type0, ptype1,	---
17072	/* G_ZEXTLOAD */	---	17072	/* G_ZEXTLOAD */	---
17073	type0, ptype1,	---	17073	type0, ptype1,	---
17074	/* G_INDEXED_LOAD */	---	17074	/* G_INDEXED_LOAD */	---
17075	type0, ptype1, ptype1, type2, -1,	---	17075	type0, ptype1, ptype1, type2, -1,	---
17076	/* G_INDEXED_SEXTLOAD */	---	17076	/* G_INDEXED_SEXTLOAD */	---
17077	type0, ptype1, ptype1, type2, -1,	---	17077	type0, ptype1, ptype1, type2, -1,	---
17078	/* G_INDEXED_ZEXTLOAD */	---	17078	/* G_INDEXED_ZEXTLOAD */	---
17079	type0, ptype1, ptype1, type2, -1,	---	17079	type0, ptype1, ptype1, type2, -1,	---
17080	/* G_STORE */	---	17080	/* G_STORE */	---
17081	type0, ptype1,	---	17081	type0, ptype1,	---
17082	/* G_INDEXED_STORE */	---	17082	/* G_INDEXED_STORE */	---
17083	ptype0, type1, ptype0, ptype2, -1,	---	17083	ptype0, type1, ptype0, ptype2, -1,	---
17084	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	---	17084	/* G_ATOMIC_CMPXCHG_WITH_SUCCESS */	---
17085	type0, type1, type2, type0, type0,	---	17085	type0, type1, type2, type0, type0,	---
17086	/* G_ATOMIC_CMPXCHG */	---	17086	/* G_ATOMIC_CMPXCHG */	---
17087	type0, ptype1, type0, type0,	---	17087	type0, ptype1, type0, type0,	---
17088	/* G_ATOMICRMW_XCHG */	---	17088	/* G_ATOMICRMW_XCHG */	---
17089	type0, ptype1, type0,	---	17089	type0, ptype1, type0,	---
17090	/* G_ATOMICRMW_ADD */	---	17090	/* G_ATOMICRMW_ADD */	---
17091	type0, ptype1, type0,	---	17091	type0, ptype1, type0,	---
17092	/* G_ATOMICRMW_SUB */	---	17092	/* G_ATOMICRMW_SUB */	---
17093	type0, ptype1, type0,	---	17093	type0, ptype1, type0,	---
17094	/* G_ATOMICRMW_AND */	---	17094	/* G_ATOMICRMW_AND */	---
17095	type0, ptype1, type0,	---	17095	type0, ptype1, type0,	---
17096	/* G_ATOMICRMW_NAND */	---	17096	/* G_ATOMICRMW_NAND */	---
17097	type0, ptype1, type0,	---	17097	type0, ptype1, type0,	---
17098	/* G_ATOMICRMW_OR */	---	17098	/* G_ATOMICRMW_OR */	---
17099	type0, ptype1, type0,	---	17099	type0, ptype1, type0,	---
17100	/* G_ATOMICRMW_XOR */	---	17100	/* G_ATOMICRMW_XOR */	---
17101	type0, ptype1, type0,	---	17101	type0, ptype1, type0,	---
17102	/* G_ATOMICRMW_MAX */	---	17102	/* G_ATOMICRMW_MAX */	---
17103	type0, ptype1, type0,	---	17103	type0, ptype1, type0,	---
17104	/* G_ATOMICRMW_MIN */	---	17104	/* G_ATOMICRMW_MIN */	---
17105	type0, ptype1, type0,	---	17105	type0, ptype1, type0,	---
17106	/* G_ATOMICRMW_UMAX */	---	17106	/* G_ATOMICRMW_UMAX */	---
17107	type0, ptype1, type0,	---	17107	type0, ptype1, type0,	---
17108	/* G_ATOMICRMW_UMIN */	---	17108	/* G_ATOMICRMW_UMIN */	---
17109	type0, ptype1, type0,	---	17109	type0, ptype1, type0,	---
17110	/* G_ATOMICRMW_FADD */	---	17110	/* G_ATOMICRMW_FADD */	---
17111	type0, ptype1, type0,	---	17111	type0, ptype1, type0,	---
17112	/* G_ATOMICRMW_FSUB */	---	17112	/* G_ATOMICRMW_FSUB */	---
17113	type0, ptype1, type0,	---	17113	type0, ptype1, type0,	---
17114	/* G_ATOMICRMW_FMAX */	---	17114	/* G_ATOMICRMW_FMAX */	---
17115	type0, ptype1, type0,	---	17115	type0, ptype1, type0,	---
17116	/* G_ATOMICRMW_FMIN */	---	17116	/* G_ATOMICRMW_FMIN */	---
17117	type0, ptype1, type0,	---	17117	type0, ptype1, type0,	---
17118	/* G_ATOMICRMW_UINC_WRAP */	---	17118	/* G_ATOMICRMW_UINC_WRAP */	---
17119	type0, ptype1, type0,	---	17119	type0, ptype1, type0,	---
17120	/* G_ATOMICRMW_UDEC_WRAP */	---	17120	/* G_ATOMICRMW_UDEC_WRAP */	---
17121	type0, ptype1, type0,	---	17121	type0, ptype1, type0,	---
17122	/* G_FENCE */	---	17122	/* G_FENCE */	---
17123	i32imm, i32imm,	---	17123	i32imm, i32imm,	---
17124	/* G_BRCOND */	---	17124	/* G_BRCOND */	---
17125	type0, -1,	---	17125	type0, -1,	---
17126	/* G_BRINDIRECT */	---	17126	/* G_BRINDIRECT */	---
17127	type0,	---	17127	type0,	---
17128	/* G_INVOKE_REGION_START */	---	17128	/* G_INVOKE_REGION_START */	---
17129	/* G_INTRINSIC */	---	17129	/* G_INTRINSIC */	---
17130	-1,	---	17130	-1,	---
17131	/* G_INTRINSIC_W_SIDE_EFFECTS */	---	17131	/* G_INTRINSIC_W_SIDE_EFFECTS */	---
17132	-1,	---	17132	-1,	---
17133	/* G_ANYEXT */	---	17133	/* G_ANYEXT */	---
17134	type0, type1,	---	17134	type0, type1,	---
17135	/* G_TRUNC */	---	17135	/* G_TRUNC */	---
17136	type0, type1,	---	17136	type0, type1,	---
17137	/* G_CONSTANT */	---	17137	/* G_CONSTANT */	---
17138	type0, -1,	---	17138	type0, -1,	---
17139	/* G_FCONSTANT */	---	17139	/* G_FCONSTANT */	---
17140	type0, -1,	---	17140	type0, -1,	---
17141	/* G_VASTART */	---	17141	/* G_VASTART */	---
17142	type0,	---	17142	type0,	---
17143	/* G_VAARG */	---	17143	/* G_VAARG */	---
17144	type0, type1, -1,	---	17144	type0, type1, -1,	---
17145	/* G_SEXT */	---	17145	/* G_SEXT */	---
17146	type0, type1,	---	17146	type0, type1,	---
17147	/* G_SEXT_INREG */	---	17147	/* G_SEXT_INREG */	---
17148	type0, type0, untyped_imm_0,	---	17148	type0, type0, untyped_imm_0,	---
17149	/* G_ZEXT */	---	17149	/* G_ZEXT */	---
17150	type0, type1,	---	17150	type0, type1,	---
17151	/* G_SHL */	---	17151	/* G_SHL */	---
17152	type0, type0, type1,	---	17152	type0, type0, type1,	---
17153	/* G_LSHR */	---	17153	/* G_LSHR */	---
17154	type0, type0, type1,	---	17154	type0, type0, type1,	---
17155	/* G_ASHR */	---	17155	/* G_ASHR */	---
17156	type0, type0, type1,	---	17156	type0, type0, type1,	---
17157	/* G_FSHL */	---	17157	/* G_FSHL */	---
17158	type0, type0, type0, type1,	---	17158	type0, type0, type0, type1,	---
17159	/* G_FSHR */	---	17159	/* G_FSHR */	---
17160	type0, type0, type0, type1,	---	17160	type0, type0, type0, type1,	---
17161	/* G_ROTR */	---	17161	/* G_ROTR */	---
17162	type0, type0, type1,	---	17162	type0, type0, type1,	---
17163	/* G_ROTL */	---	17163	/* G_ROTL */	---
17164	type0, type0, type1,	---	17164	type0, type0, type1,	---
17165	/* G_ICMP */	---	17165	/* G_ICMP */	---
17166	type0, -1, type1, type1,	---	17166	type0, -1, type1, type1,	---
17167	/* G_FCMP */	---	17167	/* G_FCMP */	---
17168	type0, -1, type1, type1,	---	17168	type0, -1, type1, type1,	---
17169	/* G_SELECT */	---	17169	/* G_SELECT */	---
17170	type0, type1, type0, type0,	---	17170	type0, type1, type0, type0,	---
17171	/* G_UADDO */	---	17171	/* G_UADDO */	---
17172	type0, type1, type0, type0,	---	17172	type0, type1, type0, type0,	---
17173	/* G_UADDE */	---	17173	/* G_UADDE */	---
17174	type0, type1, type0, type0, type1,	---	17174	type0, type1, type0, type0, type1,	---
17175	/* G_USUBO */	---	17175	/* G_USUBO */	---
17176	type0, type1, type0, type0,	---	17176	type0, type1, type0, type0,	---
17177	/* G_USUBE */	---	17177	/* G_USUBE */	---
17178	type0, type1, type0, type0, type1,	---	17178	type0, type1, type0, type0, type1,	---
17179	/* G_SADDO */	---	17179	/* G_SADDO */	---
17180	type0, type1, type0, type0,	---	17180	type0, type1, type0, type0,	---
17181	/* G_SADDE */	---	17181	/* G_SADDE */	---
17182	type0, type1, type0, type0, type1,	---	17182	type0, type1, type0, type0, type1,	---
17183	/* G_SSUBO */	---	17183	/* G_SSUBO */	---
17184	type0, type1, type0, type0,	---	17184	type0, type1, type0, type0,	---
17185	/* G_SSUBE */	---	17185	/* G_SSUBE */	---
17186	type0, type1, type0, type0, type1,	---	17186	type0, type1, type0, type0, type1,	---
17187	/* G_UMULO */	---	17187	/* G_UMULO */	---
17188	type0, type1, type0, type0,	---	17188	type0, type1, type0, type0,	---
17189	/* G_SMULO */	---	17189	/* G_SMULO */	---
17190	type0, type1, type0, type0,	---	17190	type0, type1, type0, type0,	---
17191	/* G_UMULH */	---	17191	/* G_UMULH */	---
17192	type0, type0, type0,	---	17192	type0, type0, type0,	---
17193	/* G_SMULH */	---	17193	/* G_SMULH */	---
17194	type0, type0, type0,	---	17194	type0, type0, type0,	---
17195	/* G_UADDSAT */	---	17195	/* G_UADDSAT */	---
17196	type0, type0, type0,	---	17196	type0, type0, type0,	---
17197	/* G_SADDSAT */	---	17197	/* G_SADDSAT */	---
17198	type0, type0, type0,	---	17198	type0, type0, type0,	---
17199	/* G_USUBSAT */	---	17199	/* G_USUBSAT */	---
17200	type0, type0, type0,	---	17200	type0, type0, type0,	---
17201	/* G_SSUBSAT */	---	17201	/* G_SSUBSAT */	---
17202	type0, type0, type0,	---	17202	type0, type0, type0,	---
17203	/* G_USHLSAT */	---	17203	/* G_USHLSAT */	---
17204	type0, type0, type1,	---	17204	type0, type0, type1,	---
17205	/* G_SSHLSAT */	---	17205	/* G_SSHLSAT */	---
17206	type0, type0, type1,	---	17206	type0, type0, type1,	---
17207	/* G_SMULFIX */	---	17207	/* G_SMULFIX */	---
17208	type0, type0, type0, untyped_imm_0,	---	17208	type0, type0, type0, untyped_imm_0,	---
17209	/* G_UMULFIX */	---	17209	/* G_UMULFIX */	---
17210	type0, type0, type0, untyped_imm_0,	---	17210	type0, type0, type0, untyped_imm_0,	---
17211	/* G_SMULFIXSAT */	---	17211	/* G_SMULFIXSAT */	---
17212	type0, type0, type0, untyped_imm_0,	---	17212	type0, type0, type0, untyped_imm_0,	---
17213	/* G_UMULFIXSAT */	---	17213	/* G_UMULFIXSAT */	---
17214	type0, type0, type0, untyped_imm_0,	---	17214	type0, type0, type0, untyped_imm_0,	---
17215	/* G_SDIVFIX */	---	17215	/* G_SDIVFIX */	---
17216	type0, type0, type0, untyped_imm_0,	---	17216	type0, type0, type0, untyped_imm_0,	---
17217	/* G_UDIVFIX */	---	17217	/* G_UDIVFIX */	---
17218	type0, type0, type0, untyped_imm_0,	---	17218	type0, type0, type0, untyped_imm_0,	---
17219	/* G_SDIVFIXSAT */	---	17219	/* G_SDIVFIXSAT */	---
17220	type0, type0, type0, untyped_imm_0,	---	17220	type0, type0, type0, untyped_imm_0,	---
17221	/* G_UDIVFIXSAT */	---	17221	/* G_UDIVFIXSAT */	---
17222	type0, type0, type0, untyped_imm_0,	---	17222	type0, type0, type0, untyped_imm_0,	---
17223	/* G_FADD */	---	17223	/* G_FADD */	---
17224	type0, type0, type0,	---	17224	type0, type0, type0,	---
17225	/* G_FSUB */	---	17225	/* G_FSUB */	---
17226	type0, type0, type0,	---	17226	type0, type0, type0,	---
17227	/* G_FMUL */	---	17227	/* G_FMUL */	---
17228	type0, type0, type0,	---	17228	type0, type0, type0,	---
17229	/* G_FMA */	---	17229	/* G_FMA */	---
17230	type0, type0, type0, type0,	---	17230	type0, type0, type0, type0,	---
17231	/* G_FMAD */	---	17231	/* G_FMAD */	---
17232	type0, type0, type0, type0,	---	17232	type0, type0, type0, type0,	---
17233	/* G_FDIV */	---	17233	/* G_FDIV */	---
17234	type0, type0, type0,	---	17234	type0, type0, type0,	---
17235	/* G_FREM */	---	17235	/* G_FREM */	---
17236	type0, type0, type0,	---	17236	type0, type0, type0,	---
17237	/* G_FPOW */	---	17237	/* G_FPOW */	---
17238	type0, type0, type0,	---	17238	type0, type0, type0,	---
17239	/* G_FPOWI */	---	17239	/* G_FPOWI */	---
17240	type0, type0, type1,	---	17240	type0, type0, type1,	---
17241	/* G_FEXP */	---	17241	/* G_FEXP */	---
17242	type0, type0,	---	17242	type0, type0,	---
17243	/* G_FEXP2 */	---	17243	/* G_FEXP2 */	---
17244	type0, type0,	---	17244	type0, type0,	---
17245	/* G_FLOG */	---	17245	/* G_FLOG */	---
17246	type0, type0,	---	17246	type0, type0,	---
17247	/* G_FLOG2 */	---	17247	/* G_FLOG2 */	---
17248	type0, type0,	---	17248	type0, type0,	---
17249	/* G_FLOG10 */	---	17249	/* G_FLOG10 */	---
17250	type0, type0,	---	17250	type0, type0,	---
17251	/* G_FLDEXP */	---	17251	/* G_FLDEXP */	---
17252	type0, type0, type1,	---	17252	type0, type0, type1,	---
17253	/* G_FFREXP */	---	17253	/* G_FFREXP */	---
17254	type0, type1, type0,	---	17254	type0, type1, type0,	---
17255	/* G_FNEG */	---	17255	/* G_FNEG */	---
17256	type0, type0,	---	17256	type0, type0,	---
17257	/* G_FPEXT */	---	17257	/* G_FPEXT */	---
17258	type0, type1,	---	17258	type0, type1,	---
17259	/* G_FPTRUNC */	---	17259	/* G_FPTRUNC */	---
17260	type0, type1,	---	17260	type0, type1,	---
17261	/* G_FPTOSI */	---	17261	/* G_FPTOSI */	---
17262	type0, type1,	---	17262	type0, type1,	---
17263	/* G_FPTOUI */	---	17263	/* G_FPTOUI */	---
17264	type0, type1,	---	17264	type0, type1,	---
17265	/* G_SITOFP */	---	17265	/* G_SITOFP */	---
17266	type0, type1,	---	17266	type0, type1,	---
17267	/* G_UITOFP */	---	17267	/* G_UITOFP */	---
17268	type0, type1,	---	17268	type0, type1,	---
17269	/* G_FABS */	---	17269	/* G_FABS */	---
17270	type0, type0,	---	17270	type0, type0,	---
17271	/* G_FCOPYSIGN */	---	17271	/* G_FCOPYSIGN */	---
17272	type0, type0, type1,	---	17272	type0, type0, type1,	---
17273	/* G_IS_FPCLASS */	---	17273	/* G_IS_FPCLASS */	---
17274	type0, type1, -1,	---	17274	type0, type1, -1,	---
17275	/* G_FCANONICALIZE */	---	17275	/* G_FCANONICALIZE */	---
17276	type0, type0,	---	17276	type0, type0,	---
17277	/* G_FMINNUM */	---	17277	/* G_FMINNUM */	---
17278	type0, type0, type0,	---	17278	type0, type0, type0,	---
17279	/* G_FMAXNUM */	---	17279	/* G_FMAXNUM */	---
17280	type0, type0, type0,	---	17280	type0, type0, type0,	---
17281	/* G_FMINNUM_IEEE */	---	17281	/* G_FMINNUM_IEEE */	---
17282	type0, type0, type0,	---	17282	type0, type0, type0,	---
17283	/* G_FMAXNUM_IEEE */	---	17283	/* G_FMAXNUM_IEEE */	---
17284	type0, type0, type0,	---	17284	type0, type0, type0,	---
17285	/* G_FMINIMUM */	---	17285	/* G_FMINIMUM */	---
17286	type0, type0, type0,	---	17286	type0, type0, type0,	---
17287	/* G_FMAXIMUM */	---	17287	/* G_FMAXIMUM */	---
17288	type0, type0, type0,	---	17288	type0, type0, type0,	---
17289	/* G_PTR_ADD */	---	17289	/* G_PTR_ADD */	---
17290	ptype0, ptype0, type1,	---	17290	ptype0, ptype0, type1,	---
17291	/* G_PTRMASK */	---	17291	/* G_PTRMASK */	---
17292	ptype0, ptype0, type1,	---	17292	ptype0, ptype0, type1,	---
17293	/* G_SMIN */	---	17293	/* G_SMIN */	---
17294	type0, type0, type0,	---	17294	type0, type0, type0,	---
17295	/* G_SMAX */	---	17295	/* G_SMAX */	---
17296	type0, type0, type0,	---	17296	type0, type0, type0,	---
17297	/* G_UMIN */	---	17297	/* G_UMIN */	---
17298	type0, type0, type0,	---	17298	type0, type0, type0,	---
17299	/* G_UMAX */	---	17299	/* G_UMAX */	---
17300	type0, type0, type0,	---	17300	type0, type0, type0,	---
17301	/* G_ABS */	---	17301	/* G_ABS */	---
17302	type0, type0,	---	17302	type0, type0,	---
17303	/* G_LROUND */	---	17303	/* G_LROUND */	---
17304	type0, type1,	---	17304	type0, type1,	---
17305	/* G_LLROUND */	---	17305	/* G_LLROUND */	---
17306	type0, type1,	---	17306	type0, type1,	---
17307	/* G_BR */	---	17307	/* G_BR */	---
17308	-1,	---	17308	-1,	---
17309	/* G_BRJT */	---	17309	/* G_BRJT */	---
17310	ptype0, -1, type1,	---	17310	ptype0, -1, type1,	---
17311	/* G_INSERT_VECTOR_ELT */	---	17311	/* G_INSERT_VECTOR_ELT */	---
17312	type0, type0, type1, type2,	---	17312	type0, type0, type1, type2,	---
17313	/* G_EXTRACT_VECTOR_ELT */	---	17313	/* G_EXTRACT_VECTOR_ELT */	---
17314	type0, type1, type2,	---	17314	type0, type1, type2,	---
17315	/* G_SHUFFLE_VECTOR */	---	17315	/* G_SHUFFLE_VECTOR */	---
17316	type0, type1, type1, -1,	---	17316	type0, type1, type1, -1,	---
17317	/* G_CTTZ */	---	17317	/* G_CTTZ */	---
17318	type0, type1,	---	17318	type0, type1,	---
17319	/* G_CTTZ_ZERO_UNDEF */	---	17319	/* G_CTTZ_ZERO_UNDEF */	---
17320	type0, type1,	---	17320	type0, type1,	---
17321	/* G_CTLZ */	---	17321	/* G_CTLZ */	---
17322	type0, type1,	---	17322	type0, type1,	---
17323	/* G_CTLZ_ZERO_UNDEF */	---	17323	/* G_CTLZ_ZERO_UNDEF */	---
17324	type0, type1,	---	17324	type0, type1,	---
17325	/* G_CTPOP */	---	17325	/* G_CTPOP */	---
17326	type0, type1,	---	17326	type0, type1,	---
17327	/* G_BSWAP */	---	17327	/* G_BSWAP */	---
17328	type0, type0,	---	17328	type0, type0,	---
17329	/* G_BITREVERSE */	---	17329	/* G_BITREVERSE */	---
17330	type0, type0,	---	17330	type0, type0,	---
17331	/* G_FCEIL */	---	17331	/* G_FCEIL */	---
17332	type0, type0,	---	17332	type0, type0,	---
17333	/* G_FCOS */	---	17333	/* G_FCOS */	---
17334	type0, type0,	---	17334	type0, type0,	---
17335	/* G_FSIN */	---	17335	/* G_FSIN */	---
17336	type0, type0,	---	17336	type0, type0,	---
17337	/* G_FSQRT */	---	17337	/* G_FSQRT */	---
17338	type0, type0,	---	17338	type0, type0,	---
17339	/* G_FFLOOR */	---	17339	/* G_FFLOOR */	---
17340	type0, type0,	---	17340	type0, type0,	---
17341	/* G_FRINT */	---	17341	/* G_FRINT */	---
17342	type0, type0,	---	17342	type0, type0,	---
17343	/* G_FNEARBYINT */	---	17343	/* G_FNEARBYINT */	---
17344	type0, type0,	---	17344	type0, type0,	---
17345	/* G_ADDRSPACE_CAST */	---	17345	/* G_ADDRSPACE_CAST */	---
17346	type0, type1,	---	17346	type0, type1,	---
17347	/* G_BLOCK_ADDR */	---	17347	/* G_BLOCK_ADDR */	---
17348	type0, -1,	---	17348	type0, -1,	---
17349	/* G_JUMP_TABLE */	---	17349	/* G_JUMP_TABLE */	---
17350	type0, -1,	---	17350	type0, -1,	---
17351	/* G_DYN_STACKALLOC */	---	17351	/* G_DYN_STACKALLOC */	---
17352	ptype0, type1, i32imm,	---	17352	ptype0, type1, i32imm,	---
17353	/* G_STRICT_FADD */	---	17353	/* G_STRICT_FADD */	---
17354	type0, type0, type0,	---	17354	type0, type0, type0,	---
17355	/* G_STRICT_FSUB */	---	17355	/* G_STRICT_FSUB */	---
17356	type0, type0, type0,	---	17356	type0, type0, type0,	---
17357	/* G_STRICT_FMUL */	---	17357	/* G_STRICT_FMUL */	---
17358	type0, type0, type0,	---	17358	type0, type0, type0,	---
17359	/* G_STRICT_FDIV */	---	17359	/* G_STRICT_FDIV */	---
17360	type0, type0, type0,	---	17360	type0, type0, type0,	---
17361	/* G_STRICT_FREM */	---	17361	/* G_STRICT_FREM */	---
17362	type0, type0, type0,	---	17362	type0, type0, type0,	---
17363	/* G_STRICT_FMA */	---	17363	/* G_STRICT_FMA */	---
17364	type0, type0, type0, type0,	---	17364	type0, type0, type0, type0,	---
17365	/* G_STRICT_FSQRT */	---	17365	/* G_STRICT_FSQRT */	---
17366	type0, type0,	---	17366	type0, type0,	---
17367	/* G_STRICT_FLDEXP */	---	17367	/* G_STRICT_FLDEXP */	---
17368	type0, type0, type1,	---	17368	type0, type0, type1,	---
17369	/* G_READ_REGISTER */	---	17369	/* G_READ_REGISTER */	---
17370	type0, -1,	---	17370	type0, -1,	---
17371	/* G_WRITE_REGISTER */	---	17371	/* G_WRITE_REGISTER */	---
17372	-1, type0,	---	17372	-1, type0,	---
17373	/* G_MEMCPY */	---	17373	/* G_MEMCPY */	---
17374	ptype0, ptype1, type2, untyped_imm_0,	---	17374	ptype0, ptype1, type2, untyped_imm_0,	---
17375	/* G_MEMCPY_INLINE */	---	17375	/* G_MEMCPY_INLINE */	---
17376	ptype0, ptype1, type2,	---	17376	ptype0, ptype1, type2,	---
17377	/* G_MEMMOVE */	---	17377	/* G_MEMMOVE */	---
17378	ptype0, ptype1, type2, untyped_imm_0,	---	17378	ptype0, ptype1, type2, untyped_imm_0,	---
17379	/* G_MEMSET */	---	17379	/* G_MEMSET */	---
17380	ptype0, type1, type2, untyped_imm_0,	---	17380	ptype0, type1, type2, untyped_imm_0,	---
17381	/* G_BZERO */	---	17381	/* G_BZERO */	---
17382	ptype0, type1, untyped_imm_0,	---	17382	ptype0, type1, untyped_imm_0,	---
17383	/* G_VECREDUCE_SEQ_FADD */	---	17383	/* G_VECREDUCE_SEQ_FADD */	---
17384	type0, type1, type2,	---	17384	type0, type1, type2,	---
17385	/* G_VECREDUCE_SEQ_FMUL */	---	17385	/* G_VECREDUCE_SEQ_FMUL */	---
17386	type0, type1, type2,	---	17386	type0, type1, type2,	---
17387	/* G_VECREDUCE_FADD */	---	17387	/* G_VECREDUCE_FADD */	---
17388	type0, type1,	---	17388	type0, type1,	---
17389	/* G_VECREDUCE_FMUL */	---	17389	/* G_VECREDUCE_FMUL */	---
17390	type0, type1,	---	17390	type0, type1,	---
17391	/* G_VECREDUCE_FMAX */	---	17391	/* G_VECREDUCE_FMAX */	---
17392	type0, type1,	---	17392	type0, type1,	---
17393	/* G_VECREDUCE_FMIN */	---	17393	/* G_VECREDUCE_FMIN */	---
17394	type0, type1,	---	17394	type0, type1,	---
17395	/* G_VECREDUCE_ADD */	---	17395	/* G_VECREDUCE_ADD */	---
17396	type0, type1,	---	17396	type0, type1,	---
17397	/* G_VECREDUCE_MUL */	---	17397	/* G_VECREDUCE_MUL */	---
17398	type0, type1,	---	17398	type0, type1,	---
17399	/* G_VECREDUCE_AND */	---	17399	/* G_VECREDUCE_AND */	---
17400	type0, type1,	---	17400	type0, type1,	---
17401	/* G_VECREDUCE_OR */	---	17401	/* G_VECREDUCE_OR */	---
17402	type0, type1,	---	17402	type0, type1,	---
17403	/* G_VECREDUCE_XOR */	---	17403	/* G_VECREDUCE_XOR */	---
17404	type0, type1,	---	17404	type0, type1,	---
17405	/* G_VECREDUCE_SMAX */	---	17405	/* G_VECREDUCE_SMAX */	---
17406	type0, type1,	---	17406	type0, type1,	---
17407	/* G_VECREDUCE_SMIN */	---	17407	/* G_VECREDUCE_SMIN */	---
17408	type0, type1,	---	17408	type0, type1,	---
17409	/* G_VECREDUCE_UMAX */	---	17409	/* G_VECREDUCE_UMAX */	---
17410	type0, type1,	---	17410	type0, type1,	---
17411	/* G_VECREDUCE_UMIN */	---	17411	/* G_VECREDUCE_UMIN */	---
17412	type0, type1,	---	17412	type0, type1,	---
17413	/* G_SBFX */	---	17413	/* G_SBFX */	---
17414	type0, type0, type1, type1,	---	17414	type0, type0, type1, type1,	---
17415	/* G_UBFX */	---	17415	/* G_UBFX */	---
17416	type0, type0, type1, type1,	---	17416	type0, type0, type1, type1,	---
17417	/* ABSMacro */	---	17417	/* ABSMacro */	---
17418	GPR32Opnd, GPR32Opnd,	---	17418	GPR32Opnd, GPR32Opnd,	---
17419	/* ADJCALLSTACKDOWN */	---	17419	/* ADJCALLSTACKDOWN */	---
17420	i32imm, i32imm,	---	17420	i32imm, i32imm,	---
17421	/* ADJCALLSTACKUP */	---	17421	/* ADJCALLSTACKUP */	---
17422	i32imm, i32imm,	---	17422	i32imm, i32imm,	---
17423	/* AND_V_D_PSEUDO */	---	17423	/* AND_V_D_PSEUDO */	---
17424	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	17424	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
17425	/* AND_V_H_PSEUDO */	---	17425	/* AND_V_H_PSEUDO */	---
17426	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	17426	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
17427	/* AND_V_W_PSEUDO */	---	17427	/* AND_V_W_PSEUDO */	---
17428	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	17428	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
17429	/* ATOMIC_CMP_SWAP_I16 */	---	17429	/* ATOMIC_CMP_SWAP_I16 */	---
17430	GPR32, -1, GPR32, GPR32,	---	17430	GPR32, -1, GPR32, GPR32,	---
17431	/* ATOMIC_CMP_SWAP_I16_POSTRA */	---	17431	/* ATOMIC_CMP_SWAP_I16_POSTRA */	---
17432	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	---	17432	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	---
17433	/* ATOMIC_CMP_SWAP_I32 */	---	17433	/* ATOMIC_CMP_SWAP_I32 */	---
17434	GPR32, -1, GPR32, GPR32,	---	17434	GPR32, -1, GPR32, GPR32,	---
17435	/* ATOMIC_CMP_SWAP_I32_POSTRA */	---	17435	/* ATOMIC_CMP_SWAP_I32_POSTRA */	---
17436	GPR32, -1, GPR32, GPR32,	---	17436	GPR32, -1, GPR32, GPR32,	---
17437	/* ATOMIC_CMP_SWAP_I64 */	---	17437	/* ATOMIC_CMP_SWAP_I64 */	---
17438	GPR64, -1, GPR64, GPR64,	---	17438	GPR64, -1, GPR64, GPR64,	---
17439	/* ATOMIC_CMP_SWAP_I64_POSTRA */	---	17439	/* ATOMIC_CMP_SWAP_I64_POSTRA */	---
17440	GPR64, -1, GPR64, GPR64,	---	17440	GPR64, -1, GPR64, GPR64,	---
17441	/* ATOMIC_CMP_SWAP_I8 */	---	17441	/* ATOMIC_CMP_SWAP_I8 */	---
17442	GPR32, -1, GPR32, GPR32,	---	17442	GPR32, -1, GPR32, GPR32,	---
17443	/* ATOMIC_CMP_SWAP_I8_POSTRA */	---	17443	/* ATOMIC_CMP_SWAP_I8_POSTRA */	---
17444	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	---	17444	GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,	---
17445	/* ATOMIC_LOAD_ADD_I16 */	---	17445	/* ATOMIC_LOAD_ADD_I16 */	---
17446	GPR32, -1, GPR32,	---	17446	GPR32, -1, GPR32,	---
17447	/* ATOMIC_LOAD_ADD_I16_POSTRA */	---	17447	/* ATOMIC_LOAD_ADD_I16_POSTRA */	---
17448	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17448	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17449	/* ATOMIC_LOAD_ADD_I32 */	---	17449	/* ATOMIC_LOAD_ADD_I32 */	---
17450	GPR32, -1, GPR32,	---	17450	GPR32, -1, GPR32,	---
17451	/* ATOMIC_LOAD_ADD_I32_POSTRA */	---	17451	/* ATOMIC_LOAD_ADD_I32_POSTRA */	---
17452	GPR32, -1, GPR32,	---	17452	GPR32, -1, GPR32,	---
17453	/* ATOMIC_LOAD_ADD_I64 */	---	17453	/* ATOMIC_LOAD_ADD_I64 */	---
17454	GPR64, -1, GPR64,	---	17454	GPR64, -1, GPR64,	---
17455	/* ATOMIC_LOAD_ADD_I64_POSTRA */	---	17455	/* ATOMIC_LOAD_ADD_I64_POSTRA */	---
17456	GPR64, -1, GPR64,	---	17456	GPR64, -1, GPR64,	---
17457	/* ATOMIC_LOAD_ADD_I8 */	---	17457	/* ATOMIC_LOAD_ADD_I8 */	---
17458	GPR32, -1, GPR32,	---	17458	GPR32, -1, GPR32,	---
17459	/* ATOMIC_LOAD_ADD_I8_POSTRA */	---	17459	/* ATOMIC_LOAD_ADD_I8_POSTRA */	---
17460	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17460	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17461	/* ATOMIC_LOAD_AND_I16 */	---	17461	/* ATOMIC_LOAD_AND_I16 */	---
17462	GPR32, -1, GPR32,	---	17462	GPR32, -1, GPR32,	---
17463	/* ATOMIC_LOAD_AND_I16_POSTRA */	---	17463	/* ATOMIC_LOAD_AND_I16_POSTRA */	---
17464	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17464	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17465	/* ATOMIC_LOAD_AND_I32 */	---	17465	/* ATOMIC_LOAD_AND_I32 */	---
17466	GPR32, -1, GPR32,	---	17466	GPR32, -1, GPR32,	---
17467	/* ATOMIC_LOAD_AND_I32_POSTRA */	---	17467	/* ATOMIC_LOAD_AND_I32_POSTRA */	---
17468	GPR32, -1, GPR32,	---	17468	GPR32, -1, GPR32,	---
17469	/* ATOMIC_LOAD_AND_I64 */	---	17469	/* ATOMIC_LOAD_AND_I64 */	---
17470	GPR64, -1, GPR64,	---	17470	GPR64, -1, GPR64,	---
17471	/* ATOMIC_LOAD_AND_I64_POSTRA */	---	17471	/* ATOMIC_LOAD_AND_I64_POSTRA */	---
17472	GPR64, -1, GPR64,	---	17472	GPR64, -1, GPR64,	---
17473	/* ATOMIC_LOAD_AND_I8 */	---	17473	/* ATOMIC_LOAD_AND_I8 */	---
17474	GPR32, -1, GPR32,	---	17474	GPR32, -1, GPR32,	---
17475	/* ATOMIC_LOAD_AND_I8_POSTRA */	---	17475	/* ATOMIC_LOAD_AND_I8_POSTRA */	---
17476	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17476	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17477	/* ATOMIC_LOAD_MAX_I16 */	---	17477	/* ATOMIC_LOAD_MAX_I16 */	---
17478	GPR32, -1, GPR32,	---	17478	GPR32, -1, GPR32,	---
17479	/* ATOMIC_LOAD_MAX_I16_POSTRA */	---	17479	/* ATOMIC_LOAD_MAX_I16_POSTRA */	---
17480	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17480	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17481	/* ATOMIC_LOAD_MAX_I32 */	---	17481	/* ATOMIC_LOAD_MAX_I32 */	---
17482	GPR32, -1, GPR32,	---	17482	GPR32, -1, GPR32,	---
17483	/* ATOMIC_LOAD_MAX_I32_POSTRA */	---	17483	/* ATOMIC_LOAD_MAX_I32_POSTRA */	---
17484	GPR32, -1, GPR32,	---	17484	GPR32, -1, GPR32,	---
17485	/* ATOMIC_LOAD_MAX_I64 */	---	17485	/* ATOMIC_LOAD_MAX_I64 */	---
17486	GPR64, -1, GPR64,	---	17486	GPR64, -1, GPR64,	---
17487	/* ATOMIC_LOAD_MAX_I64_POSTRA */	---	17487	/* ATOMIC_LOAD_MAX_I64_POSTRA */	---
17488	GPR64, -1, GPR64,	---	17488	GPR64, -1, GPR64,	---
17489	/* ATOMIC_LOAD_MAX_I8 */	---	17489	/* ATOMIC_LOAD_MAX_I8 */	---
17490	GPR32, -1, GPR32,	---	17490	GPR32, -1, GPR32,	---
17491	/* ATOMIC_LOAD_MAX_I8_POSTRA */	---	17491	/* ATOMIC_LOAD_MAX_I8_POSTRA */	---
17492	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17492	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17493	/* ATOMIC_LOAD_MIN_I16 */	---	17493	/* ATOMIC_LOAD_MIN_I16 */	---
17494	GPR32, -1, GPR32,	---	17494	GPR32, -1, GPR32,	---
17495	/* ATOMIC_LOAD_MIN_I16_POSTRA */	---	17495	/* ATOMIC_LOAD_MIN_I16_POSTRA */	---
17496	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17496	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17497	/* ATOMIC_LOAD_MIN_I32 */	---	17497	/* ATOMIC_LOAD_MIN_I32 */	---
17498	GPR32, -1, GPR32,	---	17498	GPR32, -1, GPR32,	---
17499	/* ATOMIC_LOAD_MIN_I32_POSTRA */	---	17499	/* ATOMIC_LOAD_MIN_I32_POSTRA */	---
17500	GPR32, -1, GPR32,	---	17500	GPR32, -1, GPR32,	---
17501	/* ATOMIC_LOAD_MIN_I64 */	---	17501	/* ATOMIC_LOAD_MIN_I64 */	---
17502	GPR64, -1, GPR64,	---	17502	GPR64, -1, GPR64,	---
17503	/* ATOMIC_LOAD_MIN_I64_POSTRA */	---	17503	/* ATOMIC_LOAD_MIN_I64_POSTRA */	---
17504	GPR64, -1, GPR64,	---	17504	GPR64, -1, GPR64,	---
17505	/* ATOMIC_LOAD_MIN_I8 */	---	17505	/* ATOMIC_LOAD_MIN_I8 */	---
17506	GPR32, -1, GPR32,	---	17506	GPR32, -1, GPR32,	---
17507	/* ATOMIC_LOAD_MIN_I8_POSTRA */	---	17507	/* ATOMIC_LOAD_MIN_I8_POSTRA */	---
17508	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17508	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17509	/* ATOMIC_LOAD_NAND_I16 */	---	17509	/* ATOMIC_LOAD_NAND_I16 */	---
17510	GPR32, -1, GPR32,	---	17510	GPR32, -1, GPR32,	---
17511	/* ATOMIC_LOAD_NAND_I16_POSTRA */	---	17511	/* ATOMIC_LOAD_NAND_I16_POSTRA */	---
17512	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17512	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17513	/* ATOMIC_LOAD_NAND_I32 */	---	17513	/* ATOMIC_LOAD_NAND_I32 */	---
17514	GPR32, -1, GPR32,	---	17514	GPR32, -1, GPR32,	---
17515	/* ATOMIC_LOAD_NAND_I32_POSTRA */	---	17515	/* ATOMIC_LOAD_NAND_I32_POSTRA */	---
17516	GPR32, -1, GPR32,	---	17516	GPR32, -1, GPR32,	---
17517	/* ATOMIC_LOAD_NAND_I64 */	---	17517	/* ATOMIC_LOAD_NAND_I64 */	---
17518	GPR64, -1, GPR64,	---	17518	GPR64, -1, GPR64,	---
17519	/* ATOMIC_LOAD_NAND_I64_POSTRA */	---	17519	/* ATOMIC_LOAD_NAND_I64_POSTRA */	---
17520	GPR64, -1, GPR64,	---	17520	GPR64, -1, GPR64,	---
17521	/* ATOMIC_LOAD_NAND_I8 */	---	17521	/* ATOMIC_LOAD_NAND_I8 */	---
17522	GPR32, -1, GPR32,	---	17522	GPR32, -1, GPR32,	---
17523	/* ATOMIC_LOAD_NAND_I8_POSTRA */	---	17523	/* ATOMIC_LOAD_NAND_I8_POSTRA */	---
17524	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17524	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17525	/* ATOMIC_LOAD_OR_I16 */	---	17525	/* ATOMIC_LOAD_OR_I16 */	---
17526	GPR32, -1, GPR32,	---	17526	GPR32, -1, GPR32,	---
17527	/* ATOMIC_LOAD_OR_I16_POSTRA */	---	17527	/* ATOMIC_LOAD_OR_I16_POSTRA */	---
17528	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17528	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17529	/* ATOMIC_LOAD_OR_I32 */	---	17529	/* ATOMIC_LOAD_OR_I32 */	---
17530	GPR32, -1, GPR32,	---	17530	GPR32, -1, GPR32,	---
17531	/* ATOMIC_LOAD_OR_I32_POSTRA */	---	17531	/* ATOMIC_LOAD_OR_I32_POSTRA */	---
17532	GPR32, -1, GPR32,	---	17532	GPR32, -1, GPR32,	---
17533	/* ATOMIC_LOAD_OR_I64 */	---	17533	/* ATOMIC_LOAD_OR_I64 */	---
17534	GPR64, -1, GPR64,	---	17534	GPR64, -1, GPR64,	---
17535	/* ATOMIC_LOAD_OR_I64_POSTRA */	---	17535	/* ATOMIC_LOAD_OR_I64_POSTRA */	---
17536	GPR64, -1, GPR64,	---	17536	GPR64, -1, GPR64,	---
17537	/* ATOMIC_LOAD_OR_I8 */	---	17537	/* ATOMIC_LOAD_OR_I8 */	---
17538	GPR32, -1, GPR32,	---	17538	GPR32, -1, GPR32,	---
17539	/* ATOMIC_LOAD_OR_I8_POSTRA */	---	17539	/* ATOMIC_LOAD_OR_I8_POSTRA */	---
17540	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17540	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17541	/* ATOMIC_LOAD_SUB_I16 */	---	17541	/* ATOMIC_LOAD_SUB_I16 */	---
17542	GPR32, -1, GPR32,	---	17542	GPR32, -1, GPR32,	---
17543	/* ATOMIC_LOAD_SUB_I16_POSTRA */	---	17543	/* ATOMIC_LOAD_SUB_I16_POSTRA */	---
17544	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17544	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17545	/* ATOMIC_LOAD_SUB_I32 */	---	17545	/* ATOMIC_LOAD_SUB_I32 */	---
17546	GPR32, -1, GPR32,	---	17546	GPR32, -1, GPR32,	---
17547	/* ATOMIC_LOAD_SUB_I32_POSTRA */	---	17547	/* ATOMIC_LOAD_SUB_I32_POSTRA */	---
17548	GPR32, -1, GPR32,	---	17548	GPR32, -1, GPR32,	---
17549	/* ATOMIC_LOAD_SUB_I64 */	---	17549	/* ATOMIC_LOAD_SUB_I64 */	---
17550	GPR64, -1, GPR64,	---	17550	GPR64, -1, GPR64,	---
17551	/* ATOMIC_LOAD_SUB_I64_POSTRA */	---	17551	/* ATOMIC_LOAD_SUB_I64_POSTRA */	---
17552	GPR64, -1, GPR64,	---	17552	GPR64, -1, GPR64,	---
17553	/* ATOMIC_LOAD_SUB_I8 */	---	17553	/* ATOMIC_LOAD_SUB_I8 */	---
17554	GPR32, -1, GPR32,	---	17554	GPR32, -1, GPR32,	---
17555	/* ATOMIC_LOAD_SUB_I8_POSTRA */	---	17555	/* ATOMIC_LOAD_SUB_I8_POSTRA */	---
17556	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17556	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17557	/* ATOMIC_LOAD_UMAX_I16 */	---	17557	/* ATOMIC_LOAD_UMAX_I16 */	---
17558	GPR32, -1, GPR32,	---	17558	GPR32, -1, GPR32,	---
17559	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	---	17559	/* ATOMIC_LOAD_UMAX_I16_POSTRA */	---
17560	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17560	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17561	/* ATOMIC_LOAD_UMAX_I32 */	---	17561	/* ATOMIC_LOAD_UMAX_I32 */	---
17562	GPR32, -1, GPR32,	---	17562	GPR32, -1, GPR32,	---
17563	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	---	17563	/* ATOMIC_LOAD_UMAX_I32_POSTRA */	---
17564	GPR32, -1, GPR32,	---	17564	GPR32, -1, GPR32,	---
17565	/* ATOMIC_LOAD_UMAX_I64 */	---	17565	/* ATOMIC_LOAD_UMAX_I64 */	---
17566	GPR64, -1, GPR64,	---	17566	GPR64, -1, GPR64,	---
17567	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	---	17567	/* ATOMIC_LOAD_UMAX_I64_POSTRA */	---
17568	GPR64, -1, GPR64,	---	17568	GPR64, -1, GPR64,	---
17569	/* ATOMIC_LOAD_UMAX_I8 */	---	17569	/* ATOMIC_LOAD_UMAX_I8 */	---
17570	GPR32, -1, GPR32,	---	17570	GPR32, -1, GPR32,	---
17571	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	---	17571	/* ATOMIC_LOAD_UMAX_I8_POSTRA */	---
17572	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17572	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17573	/* ATOMIC_LOAD_UMIN_I16 */	---	17573	/* ATOMIC_LOAD_UMIN_I16 */	---
17574	GPR32, -1, GPR32,	---	17574	GPR32, -1, GPR32,	---
17575	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	---	17575	/* ATOMIC_LOAD_UMIN_I16_POSTRA */	---
17576	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17576	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17577	/* ATOMIC_LOAD_UMIN_I32 */	---	17577	/* ATOMIC_LOAD_UMIN_I32 */	---
17578	GPR32, -1, GPR32,	---	17578	GPR32, -1, GPR32,	---
17579	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	---	17579	/* ATOMIC_LOAD_UMIN_I32_POSTRA */	---
17580	GPR32, -1, GPR32,	---	17580	GPR32, -1, GPR32,	---
17581	/* ATOMIC_LOAD_UMIN_I64 */	---	17581	/* ATOMIC_LOAD_UMIN_I64 */	---
17582	GPR64, -1, GPR64,	---	17582	GPR64, -1, GPR64,	---
17583	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	---	17583	/* ATOMIC_LOAD_UMIN_I64_POSTRA */	---
17584	GPR64, -1, GPR64,	---	17584	GPR64, -1, GPR64,	---
17585	/* ATOMIC_LOAD_UMIN_I8 */	---	17585	/* ATOMIC_LOAD_UMIN_I8 */	---
17586	GPR32, -1, GPR32,	---	17586	GPR32, -1, GPR32,	---
17587	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	---	17587	/* ATOMIC_LOAD_UMIN_I8_POSTRA */	---
17588	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17588	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17589	/* ATOMIC_LOAD_XOR_I16 */	---	17589	/* ATOMIC_LOAD_XOR_I16 */	---
17590	GPR32, -1, GPR32,	---	17590	GPR32, -1, GPR32,	---
17591	/* ATOMIC_LOAD_XOR_I16_POSTRA */	---	17591	/* ATOMIC_LOAD_XOR_I16_POSTRA */	---
17592	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17592	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17593	/* ATOMIC_LOAD_XOR_I32 */	---	17593	/* ATOMIC_LOAD_XOR_I32 */	---
17594	GPR32, -1, GPR32,	---	17594	GPR32, -1, GPR32,	---
17595	/* ATOMIC_LOAD_XOR_I32_POSTRA */	---	17595	/* ATOMIC_LOAD_XOR_I32_POSTRA */	---
17596	GPR32, -1, GPR32,	---	17596	GPR32, -1, GPR32,	---
17597	/* ATOMIC_LOAD_XOR_I64 */	---	17597	/* ATOMIC_LOAD_XOR_I64 */	---
17598	GPR64, -1, GPR64,	---	17598	GPR64, -1, GPR64,	---
17599	/* ATOMIC_LOAD_XOR_I64_POSTRA */	---	17599	/* ATOMIC_LOAD_XOR_I64_POSTRA */	---
17600	GPR64, -1, GPR64,	---	17600	GPR64, -1, GPR64,	---
17601	/* ATOMIC_LOAD_XOR_I8 */	---	17601	/* ATOMIC_LOAD_XOR_I8 */	---
17602	GPR32, -1, GPR32,	---	17602	GPR32, -1, GPR32,	---
17603	/* ATOMIC_LOAD_XOR_I8_POSTRA */	---	17603	/* ATOMIC_LOAD_XOR_I8_POSTRA */	---
17604	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17604	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17605	/* ATOMIC_SWAP_I16 */	---	17605	/* ATOMIC_SWAP_I16 */	---
17606	GPR32, -1, GPR32,	---	17606	GPR32, -1, GPR32,	---
17607	/* ATOMIC_SWAP_I16_POSTRA */	---	17607	/* ATOMIC_SWAP_I16_POSTRA */	---
17608	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17608	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17609	/* ATOMIC_SWAP_I32 */	---	17609	/* ATOMIC_SWAP_I32 */	---
17610	GPR32, -1, GPR32,	---	17610	GPR32, -1, GPR32,	---
17611	/* ATOMIC_SWAP_I32_POSTRA */	---	17611	/* ATOMIC_SWAP_I32_POSTRA */	---
17612	GPR32, -1, GPR32,	---	17612	GPR32, -1, GPR32,	---
17613	/* ATOMIC_SWAP_I64 */	---	17613	/* ATOMIC_SWAP_I64 */	---
17614	GPR64, -1, GPR64,	---	17614	GPR64, -1, GPR64,	---
17615	/* ATOMIC_SWAP_I64_POSTRA */	---	17615	/* ATOMIC_SWAP_I64_POSTRA */	---
17616	GPR64, -1, GPR64,	---	17616	GPR64, -1, GPR64,	---
17617	/* ATOMIC_SWAP_I8 */	---	17617	/* ATOMIC_SWAP_I8 */	---
17618	GPR32, -1, GPR32,	---	17618	GPR32, -1, GPR32,	---
17619	/* ATOMIC_SWAP_I8_POSTRA */	---	17619	/* ATOMIC_SWAP_I8_POSTRA */	---
17620	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---	17620	GPR32, -1, GPR32, GPR32, GPR32, GPR32,	---
17621	/* B */	---	17621	/* B */	---
17622	brtarget,	---	17622	brtarget,	---
17623	/* BAL_BR */	---	17623	/* BAL_BR */	---
17624	brtarget,	---	17624	brtarget,	---
17625	/* BAL_BR_MM */	---	17625	/* BAL_BR_MM */	---
17626	brtarget_mm,	---	17626	brtarget_mm,	---
17627	/* BEQLImmMacro */	---	17627	/* BEQLImmMacro */	---
17628	GPR32Opnd, imm64, brtarget,	---	17628	GPR32Opnd, imm64, brtarget,	---
17629	/* BGE */	---	17629	/* BGE */	---
17630	GPR32Opnd, GPR32Opnd, brtarget,	---	17630	GPR32Opnd, GPR32Opnd, brtarget,	---
17631	/* BGEImmMacro */	---	17631	/* BGEImmMacro */	---
17632	GPR32Opnd, imm64, brtarget,	---	17632	GPR32Opnd, imm64, brtarget,	---
17633	/* BGEL */	---	17633	/* BGEL */	---
17634	GPR32Opnd, GPR32Opnd, brtarget,	---	17634	GPR32Opnd, GPR32Opnd, brtarget,	---
17635	/* BGELImmMacro */	---	17635	/* BGELImmMacro */	---
17636	GPR32Opnd, imm64, brtarget,	---	17636	GPR32Opnd, imm64, brtarget,	---
17637	/* BGEU */	---	17637	/* BGEU */	---
17638	GPR32Opnd, GPR32Opnd, brtarget,	---	17638	GPR32Opnd, GPR32Opnd, brtarget,	---
17639	/* BGEUImmMacro */	---	17639	/* BGEUImmMacro */	---
17640	GPR32Opnd, imm64, brtarget,	---	17640	GPR32Opnd, imm64, brtarget,	---
17641	/* BGEUL */	---	17641	/* BGEUL */	---
17642	GPR32Opnd, GPR32Opnd, brtarget,	---	17642	GPR32Opnd, GPR32Opnd, brtarget,	---
17643	/* BGEULImmMacro */	---	17643	/* BGEULImmMacro */	---
17644	GPR32Opnd, imm64, brtarget,	---	17644	GPR32Opnd, imm64, brtarget,	---
17645	/* BGT */	---	17645	/* BGT */	---
17646	GPR32Opnd, GPR32Opnd, brtarget,	---	17646	GPR32Opnd, GPR32Opnd, brtarget,	---
17647	/* BGTImmMacro */	---	17647	/* BGTImmMacro */	---
17648	GPR32Opnd, imm64, brtarget,	---	17648	GPR32Opnd, imm64, brtarget,	---
17649	/* BGTL */	---	17649	/* BGTL */	---
17650	GPR32Opnd, GPR32Opnd, brtarget,	---	17650	GPR32Opnd, GPR32Opnd, brtarget,	---
17651	/* BGTLImmMacro */	---	17651	/* BGTLImmMacro */	---
17652	GPR32Opnd, imm64, brtarget,	---	17652	GPR32Opnd, imm64, brtarget,	---
17653	/* BGTU */	---	17653	/* BGTU */	---
17654	GPR32Opnd, GPR32Opnd, brtarget,	---	17654	GPR32Opnd, GPR32Opnd, brtarget,	---
17655	/* BGTUImmMacro */	---	17655	/* BGTUImmMacro */	---
17656	GPR32Opnd, imm64, brtarget,	---	17656	GPR32Opnd, imm64, brtarget,	---
17657	/* BGTUL */	---	17657	/* BGTUL */	---
17658	GPR32Opnd, GPR32Opnd, brtarget,	---	17658	GPR32Opnd, GPR32Opnd, brtarget,	---
17659	/* BGTULImmMacro */	---	17659	/* BGTULImmMacro */	---
17660	GPR32Opnd, imm64, brtarget,	---	17660	GPR32Opnd, imm64, brtarget,	---
17661	/* BLE */	---	17661	/* BLE */	---
17662	GPR32Opnd, GPR32Opnd, brtarget,	---	17662	GPR32Opnd, GPR32Opnd, brtarget,	---
17663	/* BLEImmMacro */	---	17663	/* BLEImmMacro */	---
17664	GPR32Opnd, imm64, brtarget,	---	17664	GPR32Opnd, imm64, brtarget,	---
17665	/* BLEL */	---	17665	/* BLEL */	---
17666	GPR32Opnd, GPR32Opnd, brtarget,	---	17666	GPR32Opnd, GPR32Opnd, brtarget,	---
17667	/* BLELImmMacro */	---	17667	/* BLELImmMacro */	---
17668	GPR32Opnd, imm64, brtarget,	---	17668	GPR32Opnd, imm64, brtarget,	---
17669	/* BLEU */	---	17669	/* BLEU */	---
17670	GPR32Opnd, GPR32Opnd, brtarget,	---	17670	GPR32Opnd, GPR32Opnd, brtarget,	---
17671	/* BLEUImmMacro */	---	17671	/* BLEUImmMacro */	---
17672	GPR32Opnd, imm64, brtarget,	---	17672	GPR32Opnd, imm64, brtarget,	---
17673	/* BLEUL */	---	17673	/* BLEUL */	---
17674	GPR32Opnd, GPR32Opnd, brtarget,	---	17674	GPR32Opnd, GPR32Opnd, brtarget,	---
17675	/* BLEULImmMacro */	---	17675	/* BLEULImmMacro */	---
17676	GPR32Opnd, imm64, brtarget,	---	17676	GPR32Opnd, imm64, brtarget,	---
17677	/* BLT */	---	17677	/* BLT */	---
17678	GPR32Opnd, GPR32Opnd, brtarget,	---	17678	GPR32Opnd, GPR32Opnd, brtarget,	---
17679	/* BLTImmMacro */	---	17679	/* BLTImmMacro */	---
17680	GPR32Opnd, imm64, brtarget,	---	17680	GPR32Opnd, imm64, brtarget,	---
17681	/* BLTL */	---	17681	/* BLTL */	---
17682	GPR32Opnd, GPR32Opnd, brtarget,	---	17682	GPR32Opnd, GPR32Opnd, brtarget,	---
17683	/* BLTLImmMacro */	---	17683	/* BLTLImmMacro */	---
17684	GPR32Opnd, imm64, brtarget,	---	17684	GPR32Opnd, imm64, brtarget,	---
17685	/* BLTU */	---	17685	/* BLTU */	---
17686	GPR32Opnd, GPR32Opnd, brtarget,	---	17686	GPR32Opnd, GPR32Opnd, brtarget,	---
17687	/* BLTUImmMacro */	---	17687	/* BLTUImmMacro */	---
17688	GPR32Opnd, imm64, brtarget,	---	17688	GPR32Opnd, imm64, brtarget,	---
17689	/* BLTUL */	---	17689	/* BLTUL */	---
17690	GPR32Opnd, GPR32Opnd, brtarget,	---	17690	GPR32Opnd, GPR32Opnd, brtarget,	---
17691	/* BLTULImmMacro */	---	17691	/* BLTULImmMacro */	---
17692	GPR32Opnd, imm64, brtarget,	---	17692	GPR32Opnd, imm64, brtarget,	---
17693	/* BNELImmMacro */	---	17693	/* BNELImmMacro */	---
17694	GPR32Opnd, imm64, brtarget,	---	17694	GPR32Opnd, imm64, brtarget,	---
17695	/* BPOSGE32_PSEUDO */	---	17695	/* BPOSGE32_PSEUDO */	---
17696	GPR32Opnd,	---	17696	GPR32Opnd,	---
17697	/* BSEL_D_PSEUDO */	---	17697	/* BSEL_D_PSEUDO */	---
17698	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	17698	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
17699	/* BSEL_FD_PSEUDO */	---	17699	/* BSEL_FD_PSEUDO */	---
17700	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	17700	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
17701	/* BSEL_FW_PSEUDO */	---	17701	/* BSEL_FW_PSEUDO */	---
17702	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	17702	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
17703	/* BSEL_H_PSEUDO */	---	17703	/* BSEL_H_PSEUDO */	---
17704	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	17704	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
17705	/* BSEL_W_PSEUDO */	---	17705	/* BSEL_W_PSEUDO */	---
17706	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	17706	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
17707	/* B_MM */	---	17707	/* B_MM */	---
17708	brtarget,	---	17708	brtarget,	---
17709	/* B_MMR6_Pseudo */	---	17709	/* B_MMR6_Pseudo */	---
17710	brtarget_mm,	---	17710	brtarget_mm,	---
17711	/* B_MM_Pseudo */	---	17711	/* B_MM_Pseudo */	---
17712	brtarget_mm,	---	17712	brtarget_mm,	---
17713	/* BeqImm */	---	17713	/* BeqImm */	---
17714	GPR32Opnd, imm64, brtarget,	---	17714	GPR32Opnd, imm64, brtarget,	---
17715	/* BneImm */	---	17715	/* BneImm */	---
17716	GPR32Opnd, imm64, brtarget,	---	17716	GPR32Opnd, imm64, brtarget,	---
17717	/* BteqzT8CmpX16 */	---	17717	/* BteqzT8CmpX16 */	---
17718	CPU16Regs, CPU16Regs, brtarget,	---	17718	CPU16Regs, CPU16Regs, brtarget,	---
17719	/* BteqzT8CmpiX16 */	---	17719	/* BteqzT8CmpiX16 */	---
17720	CPU16Regs, simm16, brtarget,	---	17720	CPU16Regs, simm16, brtarget,	---
17721	/* BteqzT8SltX16 */	---	17721	/* BteqzT8SltX16 */	---
17722	CPU16Regs, CPU16Regs, brtarget,	---	17722	CPU16Regs, CPU16Regs, brtarget,	---
17723	/* BteqzT8SltiX16 */	---	17723	/* BteqzT8SltiX16 */	---
17724	CPU16Regs, simm16, brtarget,	---	17724	CPU16Regs, simm16, brtarget,	---
17725	/* BteqzT8SltiuX16 */	---	17725	/* BteqzT8SltiuX16 */	---
17726	CPU16Regs, simm16, brtarget,	---	17726	CPU16Regs, simm16, brtarget,	---
17727	/* BteqzT8SltuX16 */	---	17727	/* BteqzT8SltuX16 */	---
17728	CPU16Regs, CPU16Regs, brtarget,	---	17728	CPU16Regs, CPU16Regs, brtarget,	---
17729	/* BtnezT8CmpX16 */	---	17729	/* BtnezT8CmpX16 */	---
17730	CPU16Regs, CPU16Regs, brtarget,	---	17730	CPU16Regs, CPU16Regs, brtarget,	---
17731	/* BtnezT8CmpiX16 */	---	17731	/* BtnezT8CmpiX16 */	---
17732	CPU16Regs, simm16, brtarget,	---	17732	CPU16Regs, simm16, brtarget,	---
17733	/* BtnezT8SltX16 */	---	17733	/* BtnezT8SltX16 */	---
17734	CPU16Regs, CPU16Regs, brtarget,	---	17734	CPU16Regs, CPU16Regs, brtarget,	---
17735	/* BtnezT8SltiX16 */	---	17735	/* BtnezT8SltiX16 */	---
17736	CPU16Regs, simm16, brtarget,	---	17736	CPU16Regs, simm16, brtarget,	---
17737	/* BtnezT8SltiuX16 */	---	17737	/* BtnezT8SltiuX16 */	---
17738	CPU16Regs, simm16, brtarget,	---	17738	CPU16Regs, simm16, brtarget,	---
17739	/* BtnezT8SltuX16 */	---	17739	/* BtnezT8SltuX16 */	---
17740	CPU16Regs, CPU16Regs, brtarget,	---	17740	CPU16Regs, CPU16Regs, brtarget,	---
17741	/* BuildPairF64 */	---	17741	/* BuildPairF64 */	---
17742	AFGR64Opnd, GPR32Opnd, GPR32Opnd,	---	17742	AFGR64Opnd, GPR32Opnd, GPR32Opnd,	---
17743	/* BuildPairF64_64 */	---	17743	/* BuildPairF64_64 */	---
17744	FGR64Opnd, GPR32Opnd, GPR32Opnd,	---	17744	FGR64Opnd, GPR32Opnd, GPR32Opnd,	---
17745	/* CFTC1 */	---	17745	/* CFTC1 */	---
17746	GPR32Opnd, FGRCCOpnd,	---	17746	GPR32Opnd, FGRCCOpnd,	---
17747	/* CONSTPOOL_ENTRY */	---	17747	/* CONSTPOOL_ENTRY */	---
17748	cpinst_operand, cpinst_operand, i32imm,	---	17748	cpinst_operand, cpinst_operand, i32imm,	---
17749	/* COPY_FD_PSEUDO */	---	17749	/* COPY_FD_PSEUDO */	---
17750	FGR64, MSA128D, uimm1_ptr,	---	17750	FGR64, MSA128D, uimm1_ptr,	---
17751	/* COPY_FW_PSEUDO */	---	17751	/* COPY_FW_PSEUDO */	---
17752	FGR32, MSA128W, uimm2_ptr,	---	17752	FGR32, MSA128W, uimm2_ptr,	---
17753	/* CTTC1 */	---	17753	/* CTTC1 */	---
17754	FGRCCOpnd, GPR32Opnd,	---	17754	FGRCCOpnd, GPR32Opnd,	---
17755	/* Constant32 */	---	17755	/* Constant32 */	---
17756	simm32,	---	17756	simm32,	---
17757	/* DMULImmMacro */	---	17757	/* DMULImmMacro */	---
17758	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---	17758	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---
17759	/* DMULMacro */	---	17759	/* DMULMacro */	---
17760	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17760	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17761	/* DMULOMacro */	---	17761	/* DMULOMacro */	---
17762	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17762	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17763	/* DMULOUMacro */	---	17763	/* DMULOUMacro */	---
17764	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17764	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17765	/* DROL */	---	17765	/* DROL */	---
17766	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	17766	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
17767	/* DROLImm */	---	17767	/* DROLImm */	---
17768	GPR32Opnd, GPR32Opnd, simm16,	---	17768	GPR32Opnd, GPR32Opnd, simm16,	---
17769	/* DROR */	---	17769	/* DROR */	---
17770	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	17770	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
17771	/* DRORImm */	---	17771	/* DRORImm */	---
17772	GPR32Opnd, GPR32Opnd, simm16,	---	17772	GPR32Opnd, GPR32Opnd, simm16,	---
17773	/* DSDivIMacro */	---	17773	/* DSDivIMacro */	---
17774	GPR64Opnd, GPR64Opnd, imm64,	---	17774	GPR64Opnd, GPR64Opnd, imm64,	---
17775	/* DSDivMacro */	---	17775	/* DSDivMacro */	---
17776	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17776	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17777	/* DSRemIMacro */	---	17777	/* DSRemIMacro */	---
17778	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---	17778	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---
17779	/* DSRemMacro */	---	17779	/* DSRemMacro */	---
17780	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17780	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17781	/* DUDivIMacro */	---	17781	/* DUDivIMacro */	---
17782	GPR64Opnd, GPR64Opnd, imm64,	---	17782	GPR64Opnd, GPR64Opnd, imm64,	---
17783	/* DUDivMacro */	---	17783	/* DUDivMacro */	---
17784	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17784	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17785	/* DURemIMacro */	---	17785	/* DURemIMacro */	---
17786	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---	17786	GPR64Opnd, GPR64Opnd, simm32_relaxed,	---
17787	/* DURemMacro */	---	17787	/* DURemMacro */	---
17788	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	17788	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
17789	/* ERet */	---	17789	/* ERet */	---
17790	/* ExtractElementF64 */	---	17790	/* ExtractElementF64 */	---
17791	GPR32Opnd, AFGR64Opnd, i32imm,	---	17791	GPR32Opnd, AFGR64Opnd, i32imm,	---
17792	/* ExtractElementF64_64 */	---	17792	/* ExtractElementF64_64 */	---
17793	GPR32Opnd, FGR64Opnd, i32imm,	---	17793	GPR32Opnd, FGR64Opnd, i32imm,	---
17794	/* FABS_D */	---	17794	/* FABS_D */	---
17795	MSA128DOpnd, MSA128DOpnd,	---	17795	MSA128DOpnd, MSA128DOpnd,	---
17796	/* FABS_W */	---	17796	/* FABS_W */	---
17797	MSA128WOpnd, MSA128WOpnd,	---	17797	MSA128WOpnd, MSA128WOpnd,	---
17798	/* FEXP2_D_1_PSEUDO */	---	17798	/* FEXP2_D_1_PSEUDO */	---
17799	MSA128D, MSA128D,	---	17799	MSA128D, MSA128D,	---
17800	/* FEXP2_W_1_PSEUDO */	---	17800	/* FEXP2_W_1_PSEUDO */	---
17801	MSA128W, MSA128W,	---	17801	MSA128W, MSA128W,	---
17802	/* FILL_FD_PSEUDO */	---	17802	/* FILL_FD_PSEUDO */	---
17803	MSA128D, FGR64,	---	17803	MSA128D, FGR64,	---
17804	/* FILL_FW_PSEUDO */	---	17804	/* FILL_FW_PSEUDO */	---
17805	MSA128W, FGR32,	---	17805	MSA128W, FGR32,	---
17806	/* GotPrologue16 */	---	17806	/* GotPrologue16 */	---
17807	CPU16Regs, CPU16Regs, simm16, simm16,	---	17807	CPU16Regs, CPU16Regs, simm16, simm16,	---
17808	/* INSERT_B_VIDX64_PSEUDO */	---	17808	/* INSERT_B_VIDX64_PSEUDO */	---
17809	MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,	---	17809	MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,	---
17810	/* INSERT_B_VIDX_PSEUDO */	---	17810	/* INSERT_B_VIDX_PSEUDO */	---
17811	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,	---	17811	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,	---
17812	/* INSERT_D_VIDX64_PSEUDO */	---	17812	/* INSERT_D_VIDX64_PSEUDO */	---
17813	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,	---	17813	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,	---
17814	/* INSERT_D_VIDX_PSEUDO */	---	17814	/* INSERT_D_VIDX_PSEUDO */	---
17815	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,	---	17815	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,	---
17816	/* INSERT_FD_PSEUDO */	---	17816	/* INSERT_FD_PSEUDO */	---
17817	MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,	---	17817	MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,	---
17818	/* INSERT_FD_VIDX64_PSEUDO */	---	17818	/* INSERT_FD_VIDX64_PSEUDO */	---
17819	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,	---	17819	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,	---
17820	/* INSERT_FD_VIDX_PSEUDO */	---	17820	/* INSERT_FD_VIDX_PSEUDO */	---
17821	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,	---	17821	MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,	---
17822	/* INSERT_FW_PSEUDO */	---	17822	/* INSERT_FW_PSEUDO */	---
17823	MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,	---	17823	MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,	---
17824	/* INSERT_FW_VIDX64_PSEUDO */	---	17824	/* INSERT_FW_VIDX64_PSEUDO */	---
17825	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,	---	17825	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,	---
17826	/* INSERT_FW_VIDX_PSEUDO */	---	17826	/* INSERT_FW_VIDX_PSEUDO */	---
17827	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,	---	17827	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,	---
17828	/* INSERT_H_VIDX64_PSEUDO */	---	17828	/* INSERT_H_VIDX64_PSEUDO */	---
17829	MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,	---	17829	MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,	---
17830	/* INSERT_H_VIDX_PSEUDO */	---	17830	/* INSERT_H_VIDX_PSEUDO */	---
17831	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,	---	17831	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,	---
17832	/* INSERT_W_VIDX64_PSEUDO */	---	17832	/* INSERT_W_VIDX64_PSEUDO */	---
17833	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,	---	17833	MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,	---
17834	/* INSERT_W_VIDX_PSEUDO */	---	17834	/* INSERT_W_VIDX_PSEUDO */	---
17835	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,	---	17835	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,	---
17836	/* JALR64Pseudo */	---	17836	/* JALR64Pseudo */	---
17837	GPR64Opnd,	---	17837	GPR64Opnd,	---
17838	/* JALRHB64Pseudo */	---	17838	/* JALRHB64Pseudo */	---
17839	GPR64Opnd,	---	17839	GPR64Opnd,	---
17840	/* JALRHBPseudo */	---	17840	/* JALRHBPseudo */	---
17841	GPR32Opnd,	---	17841	GPR32Opnd,	---
17842	/* JALRPseudo */	---	17842	/* JALRPseudo */	---
17843	GPR32Opnd,	---	17843	GPR32Opnd,	---
17844	/* JAL_MMR6 */	---	17844	/* JAL_MMR6 */	---
17845	calltarget,	---	17845	calltarget,	---
17846	/* JalOneReg */	---	17846	/* JalOneReg */	---
17847	GPR32Opnd,	---	17847	GPR32Opnd,	---
17848	/* JalTwoReg */	---	17848	/* JalTwoReg */	---
17849	GPR32Opnd, GPR32Opnd,	---	17849	GPR32Opnd, GPR32Opnd,	---
17850	/* LDMacro */	---	17850	/* LDMacro */	---
17851	GPR32Opnd, -1, simm16,	---	17851	GPR32Opnd, -1, simm16,	---
17852	/* LDR_D */	---	17852	/* LDR_D */	---
17853	MSA128DOpnd, -1, GPR32,	---	17853	MSA128DOpnd, -1, GPR32,	---
17854	/* LDR_W */	---	17854	/* LDR_W */	---
17855	MSA128WOpnd, -1, GPR32,	---	17855	MSA128WOpnd, -1, GPR32,	---
17856	/* LD_F16 */	---	17856	/* LD_F16 */	---
17857	MSA128F16, -1, simm10,	---	17857	MSA128F16, -1, simm10,	---
17858	/* LOAD_ACC128 */	---	17858	/* LOAD_ACC128 */	---
17859	ACC128, -1, simm16,	---	17859	ACC128, -1, simm16,	---
17860	/* LOAD_ACC64 */	---	17860	/* LOAD_ACC64 */	---
17861	ACC64, -1, simm16,	---	17861	ACC64, -1, simm16,	---
17862	/* LOAD_ACC64DSP */	---	17862	/* LOAD_ACC64DSP */	---
17863	ACC64DSPOpnd, -1, simm16,	---	17863	ACC64DSPOpnd, -1, simm16,	---
17864	/* LOAD_CCOND_DSP */	---	17864	/* LOAD_CCOND_DSP */	---
17865	DSPCC, -1, simm16,	---	17865	DSPCC, -1, simm16,	---
17866	/* LONG_BRANCH_ADDiu */	---	17866	/* LONG_BRANCH_ADDiu */	---
17867	GPR32Opnd, GPR32Opnd, brtarget, brtarget,	---	17867	GPR32Opnd, GPR32Opnd, brtarget, brtarget,	---
17868	/* LONG_BRANCH_ADDiu2Op */	---	17868	/* LONG_BRANCH_ADDiu2Op */	---
17869	GPR32Opnd, GPR32Opnd, brtarget,	---	17869	GPR32Opnd, GPR32Opnd, brtarget,	---
17870	/* LONG_BRANCH_DADDiu */	---	17870	/* LONG_BRANCH_DADDiu */	---
17871	GPR64Opnd, GPR64Opnd, brtarget, brtarget,	---	17871	GPR64Opnd, GPR64Opnd, brtarget, brtarget,	---
17872	/* LONG_BRANCH_DADDiu2Op */	---	17872	/* LONG_BRANCH_DADDiu2Op */	---
17873	GPR64Opnd, GPR64Opnd, brtarget,	---	17873	GPR64Opnd, GPR64Opnd, brtarget,	---
17874	/* LONG_BRANCH_LUi */	---	17874	/* LONG_BRANCH_LUi */	---
17875	GPR32Opnd, brtarget, brtarget,	---	17875	GPR32Opnd, brtarget, brtarget,	---
17876	/* LONG_BRANCH_LUi2Op */	---	17876	/* LONG_BRANCH_LUi2Op */	---
17877	GPR32Opnd, brtarget,	---	17877	GPR32Opnd, brtarget,	---
17878	/* LONG_BRANCH_LUi2Op_64 */	---	17878	/* LONG_BRANCH_LUi2Op_64 */	---
17879	GPR64Opnd, brtarget,	---	17879	GPR64Opnd, brtarget,	---
17880	/* LWM_MM */	---	17880	/* LWM_MM */	---
17881	reglist, -1, simm12,	---	17881	reglist, -1, simm12,	---
17882	/* LoadAddrImm32 */	---	17882	/* LoadAddrImm32 */	---
17883	GPR32Opnd, i32imm,	---	17883	GPR32Opnd, i32imm,	---
17884	/* LoadAddrImm64 */	---	17884	/* LoadAddrImm64 */	---
17885	GPR64Opnd, imm64,	---	17885	GPR64Opnd, imm64,	---
17886	/* LoadAddrReg32 */	---	17886	/* LoadAddrReg32 */	---
17887	GPR32Opnd, -1, simm16,	---	17887	GPR32Opnd, -1, simm16,	---
17888	/* LoadAddrReg64 */	---	17888	/* LoadAddrReg64 */	---
17889	GPR64Opnd, -1, simm16,	---	17889	GPR64Opnd, -1, simm16,	---
17890	/* LoadImm32 */	---	17890	/* LoadImm32 */	---
17891	GPR32Opnd, uimm32_coerced,	---	17891	GPR32Opnd, uimm32_coerced,	---
17892	/* LoadImm64 */	---	17892	/* LoadImm64 */	---
17893	GPR64Opnd, imm64,	---	17893	GPR64Opnd, imm64,	---
17894	/* LoadImmDoubleFGR */	---	17894	/* LoadImmDoubleFGR */	---
17895	StrictlyFGR64Opnd, imm64,	---	17895	StrictlyFGR64Opnd, imm64,	---
17896	/* LoadImmDoubleFGR_32 */	---	17896	/* LoadImmDoubleFGR_32 */	---
17897	StrictlyAFGR64Opnd, imm64,	---	17897	StrictlyAFGR64Opnd, imm64,	---
17898	/* LoadImmDoubleGPR */	---	17898	/* LoadImmDoubleGPR */	---
17899	GPR32Opnd, imm64,	---	17899	GPR32Opnd, imm64,	---
17900	/* LoadImmSingleFGR */	---	17900	/* LoadImmSingleFGR */	---
17901	StrictlyFGR32Opnd, imm64,	---	17901	StrictlyFGR32Opnd, imm64,	---
17902	/* LoadImmSingleGPR */	---	17902	/* LoadImmSingleGPR */	---
17903	GPR32Opnd, imm64,	---	17903	GPR32Opnd, imm64,	---
17904	/* LwConstant32 */	---	17904	/* LwConstant32 */	---
17905	CPU16Regs, simm32, simm32,	---	17905	CPU16Regs, simm32, simm32,	---
17906	/* MFTACX */	---	17906	/* MFTACX */	---
17907	GPR32Opnd, ACC64DSPOpnd,	---	17907	GPR32Opnd, ACC64DSPOpnd,	---
17908	/* MFTC0 */	---	17908	/* MFTC0 */	---
17909	GPR32Opnd, COP0Opnd, uimm3,	---	17909	GPR32Opnd, COP0Opnd, uimm3,	---
17910	/* MFTC1 */	---	17910	/* MFTC1 */	---
17911	GPR32Opnd, FGR32Opnd,	---	17911	GPR32Opnd, FGR32Opnd,	---
17912	/* MFTDSP */	---	17912	/* MFTDSP */	---
17913	GPR32Opnd,	---	17913	GPR32Opnd,	---
17914	/* MFTGPR */	---	17914	/* MFTGPR */	---
17915	GPR32Opnd, GPR32Opnd, uimm3,	---	17915	GPR32Opnd, GPR32Opnd, uimm3,	---
17916	/* MFTHC1 */	---	17916	/* MFTHC1 */	---
17917	GPR32Opnd, FGR32Opnd,	---	17917	GPR32Opnd, FGR32Opnd,	---
17918	/* MFTHI */	---	17918	/* MFTHI */	---
17919	GPR32Opnd, ACC64DSPOpnd,	---	17919	GPR32Opnd, ACC64DSPOpnd,	---
17920	/* MFTLO */	---	17920	/* MFTLO */	---
17921	GPR32Opnd, ACC64DSPOpnd,	---	17921	GPR32Opnd, ACC64DSPOpnd,	---
17922	/* MIPSeh_return32 */	---	17922	/* MIPSeh_return32 */	---
17923	GPR32, GPR32,	---	17923	GPR32, GPR32,	---
17924	/* MIPSeh_return64 */	---	17924	/* MIPSeh_return64 */	---
17925	GPR64, GPR64,	---	17925	GPR64, GPR64,	---
17926	/* MSA_FP_EXTEND_D_PSEUDO */	---	17926	/* MSA_FP_EXTEND_D_PSEUDO */	---
17927	FGR64Opnd, MSA128F16,	---	17927	FGR64Opnd, MSA128F16,	---
17928	/* MSA_FP_EXTEND_W_PSEUDO */	---	17928	/* MSA_FP_EXTEND_W_PSEUDO */	---
17929	FGR32Opnd, MSA128F16,	---	17929	FGR32Opnd, MSA128F16,	---
17930	/* MSA_FP_ROUND_D_PSEUDO */	---	17930	/* MSA_FP_ROUND_D_PSEUDO */	---
17931	MSA128F16, FGR64Opnd,	---	17931	MSA128F16, FGR64Opnd,	---
17932	/* MSA_FP_ROUND_W_PSEUDO */	---	17932	/* MSA_FP_ROUND_W_PSEUDO */	---
17933	MSA128F16, FGR32Opnd,	---	17933	MSA128F16, FGR32Opnd,	---
17934	/* MTTACX */	---	17934	/* MTTACX */	---
17935	ACC64DSPOpnd, GPR32Opnd,	---	17935	ACC64DSPOpnd, GPR32Opnd,	---
17936	/* MTTC0 */	---	17936	/* MTTC0 */	---
17937	COP0Opnd, GPR32Opnd, uimm3,	---	17937	COP0Opnd, GPR32Opnd, uimm3,	---
17938	/* MTTC1 */	---	17938	/* MTTC1 */	---
17939	FGR32Opnd, GPR32Opnd,	---	17939	FGR32Opnd, GPR32Opnd,	---
17940	/* MTTDSP */	---	17940	/* MTTDSP */	---
17941	GPR32Opnd,	---	17941	GPR32Opnd,	---
17942	/* MTTGPR */	---	17942	/* MTTGPR */	---
17943	GPR32Opnd, GPR32Opnd,	---	17943	GPR32Opnd, GPR32Opnd,	---
17944	/* MTTHC1 */	---	17944	/* MTTHC1 */	---
17945	FGR32Opnd, GPR32Opnd,	---	17945	FGR32Opnd, GPR32Opnd,	---
17946	/* MTTHI */	---	17946	/* MTTHI */	---
17947	ACC64DSPOpnd, GPR32Opnd,	---	17947	ACC64DSPOpnd, GPR32Opnd,	---
17948	/* MTTLO */	---	17948	/* MTTLO */	---
17949	ACC64DSPOpnd, GPR32Opnd,	---	17949	ACC64DSPOpnd, GPR32Opnd,	---
17950	/* MULImmMacro */	---	17950	/* MULImmMacro */	---
17951	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	17951	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
17952	/* MULOMacro */	---	17952	/* MULOMacro */	---
17953	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	17953	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
17954	/* MULOUMacro */	---	17954	/* MULOUMacro */	---
17955	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	17955	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
17956	/* MultRxRy16 */	---	17956	/* MultRxRy16 */	---
17957	CPU16Regs, CPU16Regs,	---	17957	CPU16Regs, CPU16Regs,	---
17958	/* MultRxRyRz16 */	---	17958	/* MultRxRyRz16 */	---
17959	CPU16Regs, CPU16Regs, CPU16Regs,	---	17959	CPU16Regs, CPU16Regs, CPU16Regs,	---
17960	/* MultuRxRy16 */	---	17960	/* MultuRxRy16 */	---
17961	CPU16Regs, CPU16Regs,	---	17961	CPU16Regs, CPU16Regs,	---
17962	/* MultuRxRyRz16 */	---	17962	/* MultuRxRyRz16 */	---
17963	CPU16Regs, CPU16Regs, CPU16Regs,	---	17963	CPU16Regs, CPU16Regs, CPU16Regs,	---
17964	/* NOP */	---	17964	/* NOP */	---
17965	/* NORImm */	---	17965	/* NORImm */	---
17966	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	17966	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
17967	/* NORImm64 */	---	17967	/* NORImm64 */	---
17968	GPR64Opnd, GPR64Opnd, imm64,	---	17968	GPR64Opnd, GPR64Opnd, imm64,	---
17969	/* NOR_V_D_PSEUDO */	---	17969	/* NOR_V_D_PSEUDO */	---
17970	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	17970	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
17971	/* NOR_V_H_PSEUDO */	---	17971	/* NOR_V_H_PSEUDO */	---
17972	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	17972	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
17973	/* NOR_V_W_PSEUDO */	---	17973	/* NOR_V_W_PSEUDO */	---
17974	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	17974	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
17975	/* OR_V_D_PSEUDO */	---	17975	/* OR_V_D_PSEUDO */	---
17976	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	17976	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
17977	/* OR_V_H_PSEUDO */	---	17977	/* OR_V_H_PSEUDO */	---
17978	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	17978	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
17979	/* OR_V_W_PSEUDO */	---	17979	/* OR_V_W_PSEUDO */	---
17980	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	17980	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
17981	/* PseudoCMPU_EQ_QB */	---	17981	/* PseudoCMPU_EQ_QB */	---
17982	DSPCC, DSPROpnd, DSPROpnd,	---	17982	DSPCC, DSPROpnd, DSPROpnd,	---
17983	/* PseudoCMPU_LE_QB */	---	17983	/* PseudoCMPU_LE_QB */	---
17984	DSPCC, DSPROpnd, DSPROpnd,	---	17984	DSPCC, DSPROpnd, DSPROpnd,	---
17985	/* PseudoCMPU_LT_QB */	---	17985	/* PseudoCMPU_LT_QB */	---
17986	DSPCC, DSPROpnd, DSPROpnd,	---	17986	DSPCC, DSPROpnd, DSPROpnd,	---
17987	/* PseudoCMP_EQ_PH */	---	17987	/* PseudoCMP_EQ_PH */	---
17988	DSPCC, DSPROpnd, DSPROpnd,	---	17988	DSPCC, DSPROpnd, DSPROpnd,	---
17989	/* PseudoCMP_LE_PH */	---	17989	/* PseudoCMP_LE_PH */	---
17990	DSPCC, DSPROpnd, DSPROpnd,	---	17990	DSPCC, DSPROpnd, DSPROpnd,	---
17991	/* PseudoCMP_LT_PH */	---	17991	/* PseudoCMP_LT_PH */	---
17992	DSPCC, DSPROpnd, DSPROpnd,	---	17992	DSPCC, DSPROpnd, DSPROpnd,	---
17993	/* PseudoCVT_D32_W */	---	17993	/* PseudoCVT_D32_W */	---
17994	AFGR64Opnd, GPR32Opnd,	---	17994	AFGR64Opnd, GPR32Opnd,	---
17995	/* PseudoCVT_D64_L */	---	17995	/* PseudoCVT_D64_L */	---
17996	FGR64Opnd, GPR64Opnd,	---	17996	FGR64Opnd, GPR64Opnd,	---
17997	/* PseudoCVT_D64_W */	---	17997	/* PseudoCVT_D64_W */	---
17998	FGR64Opnd, GPR32Opnd,	---	17998	FGR64Opnd, GPR32Opnd,	---
17999	/* PseudoCVT_S_L */	---	17999	/* PseudoCVT_S_L */	---
18000	FGR64Opnd, GPR64Opnd,	---	18000	FGR64Opnd, GPR64Opnd,	---
18001	/* PseudoCVT_S_W */	---	18001	/* PseudoCVT_S_W */	---
18002	FGR32Opnd, GPR32Opnd,	---	18002	FGR32Opnd, GPR32Opnd,	---
18003	/* PseudoDMULT */	---	18003	/* PseudoDMULT */	---
18004	ACC128, GPR64Opnd, GPR64Opnd,	---	18004	ACC128, GPR64Opnd, GPR64Opnd,	---
18005	/* PseudoDMULTu */	---	18005	/* PseudoDMULTu */	---
18006	ACC128, GPR64Opnd, GPR64Opnd,	---	18006	ACC128, GPR64Opnd, GPR64Opnd,	---
18007	/* PseudoDSDIV */	---	18007	/* PseudoDSDIV */	---
18008	ACC128, GPR64Opnd, GPR64Opnd,	---	18008	ACC128, GPR64Opnd, GPR64Opnd,	---
18009	/* PseudoDUDIV */	---	18009	/* PseudoDUDIV */	---
18010	ACC128, GPR64Opnd, GPR64Opnd,	---	18010	ACC128, GPR64Opnd, GPR64Opnd,	---
18011	/* PseudoD_SELECT_I */	---	18011	/* PseudoD_SELECT_I */	---
18012	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18012	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18013	/* PseudoD_SELECT_I64 */	---	18013	/* PseudoD_SELECT_I64 */	---
18014	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	18014	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
18015	/* PseudoIndirectBranch */	---	18015	/* PseudoIndirectBranch */	---
18016	GPR32Opnd,	---	18016	GPR32Opnd,	---
18017	/* PseudoIndirectBranch64 */	---	18017	/* PseudoIndirectBranch64 */	---
18018	GPR64Opnd,	---	18018	GPR64Opnd,	---
18019	/* PseudoIndirectBranch64R6 */	---	18019	/* PseudoIndirectBranch64R6 */	---
18020	GPR64Opnd,	---	18020	GPR64Opnd,	---
18021	/* PseudoIndirectBranchR6 */	---	18021	/* PseudoIndirectBranchR6 */	---
18022	GPR32Opnd,	---	18022	GPR32Opnd,	---
18023	/* PseudoIndirectBranch_MM */	---	18023	/* PseudoIndirectBranch_MM */	---
18024	GPR32Opnd,	---	18024	GPR32Opnd,	---
18025	/* PseudoIndirectBranch_MMR6 */	---	18025	/* PseudoIndirectBranch_MMR6 */	---
18026	GPR32Opnd,	---	18026	GPR32Opnd,	---
18027	/* PseudoIndirectHazardBranch */	---	18027	/* PseudoIndirectHazardBranch */	---
18028	GPR32Opnd,	---	18028	GPR32Opnd,	---
18029	/* PseudoIndirectHazardBranch64 */	---	18029	/* PseudoIndirectHazardBranch64 */	---
18030	GPR64Opnd,	---	18030	GPR64Opnd,	---
18031	/* PseudoIndrectHazardBranch64R6 */	---	18031	/* PseudoIndrectHazardBranch64R6 */	---
18032	GPR64Opnd,	---	18032	GPR64Opnd,	---
18033	/* PseudoIndrectHazardBranchR6 */	---	18033	/* PseudoIndrectHazardBranchR6 */	---
18034	GPR32Opnd,	---	18034	GPR32Opnd,	---
18035	/* PseudoMADD */	---	18035	/* PseudoMADD */	---
18036	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18036	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18037	/* PseudoMADDU */	---	18037	/* PseudoMADDU */	---
18038	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18038	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18039	/* PseudoMADDU_MM */	---	18039	/* PseudoMADDU_MM */	---
18040	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18040	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18041	/* PseudoMADD_MM */	---	18041	/* PseudoMADD_MM */	---
18042	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18042	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18043	/* PseudoMFHI */	---	18043	/* PseudoMFHI */	---
18044	GPR32, ACC64,	---	18044	GPR32, ACC64,	---
18045	/* PseudoMFHI64 */	---	18045	/* PseudoMFHI64 */	---
18046	GPR64, ACC128,	---	18046	GPR64, ACC128,	---
18047	/* PseudoMFHI_MM */	---	18047	/* PseudoMFHI_MM */	---
18048	GPR32, ACC64,	---	18048	GPR32, ACC64,	---
18049	/* PseudoMFLO */	---	18049	/* PseudoMFLO */	---
18050	GPR32, ACC64,	---	18050	GPR32, ACC64,	---
18051	/* PseudoMFLO64 */	---	18051	/* PseudoMFLO64 */	---
18052	GPR64, ACC128,	---	18052	GPR64, ACC128,	---
18053	/* PseudoMFLO_MM */	---	18053	/* PseudoMFLO_MM */	---
18054	GPR32, ACC64,	---	18054	GPR32, ACC64,	---
18055	/* PseudoMSUB */	---	18055	/* PseudoMSUB */	---
18056	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18056	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18057	/* PseudoMSUBU */	---	18057	/* PseudoMSUBU */	---
18058	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18058	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18059	/* PseudoMSUBU_MM */	---	18059	/* PseudoMSUBU_MM */	---
18060	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18060	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18061	/* PseudoMSUB_MM */	---	18061	/* PseudoMSUB_MM */	---
18062	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---	18062	ACC64, GPR32Opnd, GPR32Opnd, ACC64,	---
18063	/* PseudoMTLOHI */	---	18063	/* PseudoMTLOHI */	---
18064	ACC64, GPR32, GPR32,	---	18064	ACC64, GPR32, GPR32,	---
18065	/* PseudoMTLOHI64 */	---	18065	/* PseudoMTLOHI64 */	---
18066	ACC128, GPR64, GPR64,	---	18066	ACC128, GPR64, GPR64,	---
18067	/* PseudoMTLOHI_DSP */	---	18067	/* PseudoMTLOHI_DSP */	---
18068	ACC64DSP, GPR32, GPR32,	---	18068	ACC64DSP, GPR32, GPR32,	---
18069	/* PseudoMTLOHI_MM */	---	18069	/* PseudoMTLOHI_MM */	---
18070	ACC64, GPR32, GPR32,	---	18070	ACC64, GPR32, GPR32,	---
18071	/* PseudoMULT */	---	18071	/* PseudoMULT */	---
18072	ACC64, GPR32Opnd, GPR32Opnd,	---	18072	ACC64, GPR32Opnd, GPR32Opnd,	---
18073	/* PseudoMULT_MM */	---	18073	/* PseudoMULT_MM */	---
18074	ACC64, GPR32Opnd, GPR32Opnd,	---	18074	ACC64, GPR32Opnd, GPR32Opnd,	---
18075	/* PseudoMULTu */	---	18075	/* PseudoMULTu */	---
18076	ACC64, GPR32Opnd, GPR32Opnd,	---	18076	ACC64, GPR32Opnd, GPR32Opnd,	---
18077	/* PseudoMULTu_MM */	---	18077	/* PseudoMULTu_MM */	---
18078	ACC64, GPR32Opnd, GPR32Opnd,	---	18078	ACC64, GPR32Opnd, GPR32Opnd,	---
18079	/* PseudoPICK_PH */	---	18079	/* PseudoPICK_PH */	---
18080	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	---	18080	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	---
18081	/* PseudoPICK_QB */	---	18081	/* PseudoPICK_QB */	---
18082	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	---	18082	DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,	---
18083	/* PseudoReturn */	---	18083	/* PseudoReturn */	---
18084	GPR32Opnd,	---	18084	GPR32Opnd,	---
18085	/* PseudoReturn64 */	---	18085	/* PseudoReturn64 */	---
18086	GPR64Opnd,	---	18086	GPR64Opnd,	---
18087	/* PseudoSDIV */	---	18087	/* PseudoSDIV */	---
18088	ACC64, GPR32Opnd, GPR32Opnd,	---	18088	ACC64, GPR32Opnd, GPR32Opnd,	---
18089	/* PseudoSELECTFP_F_D32 */	---	18089	/* PseudoSELECTFP_F_D32 */	---
18090	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	18090	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
18091	/* PseudoSELECTFP_F_D64 */	---	18091	/* PseudoSELECTFP_F_D64 */	---
18092	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	18092	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
18093	/* PseudoSELECTFP_F_I */	---	18093	/* PseudoSELECTFP_F_I */	---
18094	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	---	18094	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	---
18095	/* PseudoSELECTFP_F_I64 */	---	18095	/* PseudoSELECTFP_F_I64 */	---
18096	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	---	18096	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	---
18097	/* PseudoSELECTFP_F_S */	---	18097	/* PseudoSELECTFP_F_S */	---
18098	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	18098	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
18099	/* PseudoSELECTFP_T_D32 */	---	18099	/* PseudoSELECTFP_T_D32 */	---
18100	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	18100	AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
18101	/* PseudoSELECTFP_T_D64 */	---	18101	/* PseudoSELECTFP_T_D64 */	---
18102	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	18102	FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
18103	/* PseudoSELECTFP_T_I */	---	18103	/* PseudoSELECTFP_T_I */	---
18104	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	---	18104	GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,	---
18105	/* PseudoSELECTFP_T_I64 */	---	18105	/* PseudoSELECTFP_T_I64 */	---
18106	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	---	18106	GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,	---
18107	/* PseudoSELECTFP_T_S */	---	18107	/* PseudoSELECTFP_T_S */	---
18108	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	18108	FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
18109	/* PseudoSELECT_D32 */	---	18109	/* PseudoSELECT_D32 */	---
18110	AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,	---	18110	AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,	---
18111	/* PseudoSELECT_D64 */	---	18111	/* PseudoSELECT_D64 */	---
18112	FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,	---	18112	FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,	---
18113	/* PseudoSELECT_I */	---	18113	/* PseudoSELECT_I */	---
18114	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18114	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18115	/* PseudoSELECT_I64 */	---	18115	/* PseudoSELECT_I64 */	---
18116	GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,	---	18116	GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,	---
18117	/* PseudoSELECT_S */	---	18117	/* PseudoSELECT_S */	---
18118	FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,	---	18118	FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,	---
18119	/* PseudoTRUNC_W_D */	---	18119	/* PseudoTRUNC_W_D */	---
18120	FGR32Opnd, FGR64Opnd, GPR32Opnd,	---	18120	FGR32Opnd, FGR64Opnd, GPR32Opnd,	---
18121	/* PseudoTRUNC_W_D32 */	---	18121	/* PseudoTRUNC_W_D32 */	---
18122	FGR32Opnd, AFGR64Opnd, GPR32Opnd,	---	18122	FGR32Opnd, AFGR64Opnd, GPR32Opnd,	---
18123	/* PseudoTRUNC_W_S */	---	18123	/* PseudoTRUNC_W_S */	---
18124	FGR32Opnd, FGR32Opnd, GPR32Opnd,	---	18124	FGR32Opnd, FGR32Opnd, GPR32Opnd,	---
18125	/* PseudoUDIV */	---	18125	/* PseudoUDIV */	---
18126	ACC64, GPR32Opnd, GPR32Opnd,	---	18126	ACC64, GPR32Opnd, GPR32Opnd,	---
18127	/* ROL */	---	18127	/* ROL */	---
18128	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18128	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18129	/* ROLImm */	---	18129	/* ROLImm */	---
18130	GPR32Opnd, GPR32Opnd, simm16,	---	18130	GPR32Opnd, GPR32Opnd, simm16,	---
18131	/* ROR */	---	18131	/* ROR */	---
18132	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18132	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18133	/* RORImm */	---	18133	/* RORImm */	---
18134	GPR32Opnd, GPR32Opnd, simm16,	---	18134	GPR32Opnd, GPR32Opnd, simm16,	---
18135	/* RetRA */	---	18135	/* RetRA */	---
18136	/* RetRA16 */	---	18136	/* RetRA16 */	---
18137	/* SDC1_M1 */	---	18137	/* SDC1_M1 */	---
18138	AFGR64Opnd, -1, simm16,	---	18138	AFGR64Opnd, -1, simm16,	---
18139	/* SDIV_MM_Pseudo */	---	18139	/* SDIV_MM_Pseudo */	---
18140	ACC64, GPR32Opnd, GPR32Opnd,	---	18140	ACC64, GPR32Opnd, GPR32Opnd,	---
18141	/* SDMacro */	---	18141	/* SDMacro */	---
18142	GPR32Opnd, -1, simm16,	---	18142	GPR32Opnd, -1, simm16,	---
18143	/* SDivIMacro */	---	18143	/* SDivIMacro */	---
18144	GPR32Opnd, GPR32Opnd, simm32,	---	18144	GPR32Opnd, GPR32Opnd, simm32,	---
18145	/* SDivMacro */	---	18145	/* SDivMacro */	---
18146	GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,	---	18146	GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,	---
18147	/* SEQIMacro */	---	18147	/* SEQIMacro */	---
18148	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	18148	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
18149	/* SEQMacro */	---	18149	/* SEQMacro */	---
18150	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18150	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18151	/* SGE */	---	18151	/* SGE */	---
18152	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18152	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18153	/* SGEImm */	---	18153	/* SGEImm */	---
18154	GPR32Opnd, GPR32Opnd, simm32,	---	18154	GPR32Opnd, GPR32Opnd, simm32,	---
18155	/* SGEImm64 */	---	18155	/* SGEImm64 */	---
18156	GPR64Opnd, GPR64Opnd, imm64,	---	18156	GPR64Opnd, GPR64Opnd, imm64,	---
18157	/* SGEU */	---	18157	/* SGEU */	---
18158	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18158	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18159	/* SGEUImm */	---	18159	/* SGEUImm */	---
18160	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---	18160	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---
18161	/* SGEUImm64 */	---	18161	/* SGEUImm64 */	---
18162	GPR64Opnd, GPR64Opnd, imm64,	---	18162	GPR64Opnd, GPR64Opnd, imm64,	---
18163	/* SGTImm */	---	18163	/* SGTImm */	---
18164	GPR32Opnd, GPR32Opnd, simm32,	---	18164	GPR32Opnd, GPR32Opnd, simm32,	---
18165	/* SGTImm64 */	---	18165	/* SGTImm64 */	---
18166	GPR64Opnd, GPR64Opnd, imm64,	---	18166	GPR64Opnd, GPR64Opnd, imm64,	---
18167	/* SGTUImm */	---	18167	/* SGTUImm */	---
18168	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---	18168	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---
18169	/* SGTUImm64 */	---	18169	/* SGTUImm64 */	---
18170	GPR64Opnd, GPR64Opnd, imm64,	---	18170	GPR64Opnd, GPR64Opnd, imm64,	---
18171	/* SLE */	---	18171	/* SLE */	---
18172	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18172	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18173	/* SLEImm */	---	18173	/* SLEImm */	---
18174	GPR32Opnd, GPR32Opnd, simm32,	---	18174	GPR32Opnd, GPR32Opnd, simm32,	---
18175	/* SLEImm64 */	---	18175	/* SLEImm64 */	---
18176	GPR64Opnd, GPR64Opnd, imm64,	---	18176	GPR64Opnd, GPR64Opnd, imm64,	---
18177	/* SLEU */	---	18177	/* SLEU */	---
18178	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18178	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18179	/* SLEUImm */	---	18179	/* SLEUImm */	---
18180	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---	18180	GPR32Opnd, GPR32Opnd, uimm32_coerced,	---
18181	/* SLEUImm64 */	---	18181	/* SLEUImm64 */	---
18182	GPR64Opnd, GPR64Opnd, imm64,	---	18182	GPR64Opnd, GPR64Opnd, imm64,	---
18183	/* SLTImm64 */	---	18183	/* SLTImm64 */	---
18184	GPR64Opnd, GPR64Opnd, imm64,	---	18184	GPR64Opnd, GPR64Opnd, imm64,	---
18185	/* SLTUImm64 */	---	18185	/* SLTUImm64 */	---
18186	GPR64Opnd, GPR64Opnd, imm64,	---	18186	GPR64Opnd, GPR64Opnd, imm64,	---
18187	/* SNEIMacro */	---	18187	/* SNEIMacro */	---
18188	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	18188	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
18189	/* SNEMacro */	---	18189	/* SNEMacro */	---
18190	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18190	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18191	/* SNZ_B_PSEUDO */	---	18191	/* SNZ_B_PSEUDO */	---
18192	GPR32, MSA128B,	---	18192	GPR32, MSA128B,	---
18193	/* SNZ_D_PSEUDO */	---	18193	/* SNZ_D_PSEUDO */	---
18194	GPR32, MSA128D,	---	18194	GPR32, MSA128D,	---
18195	/* SNZ_H_PSEUDO */	---	18195	/* SNZ_H_PSEUDO */	---
18196	GPR32, MSA128H,	---	18196	GPR32, MSA128H,	---
18197	/* SNZ_V_PSEUDO */	---	18197	/* SNZ_V_PSEUDO */	---
18198	GPR32, MSA128B,	---	18198	GPR32, MSA128B,	---
18199	/* SNZ_W_PSEUDO */	---	18199	/* SNZ_W_PSEUDO */	---
18200	GPR32, MSA128W,	---	18200	GPR32, MSA128W,	---
18201	/* SRemIMacro */	---	18201	/* SRemIMacro */	---
18202	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	18202	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
18203	/* SRemMacro */	---	18203	/* SRemMacro */	---
18204	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18204	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18205	/* STORE_ACC128 */	---	18205	/* STORE_ACC128 */	---
18206	ACC128, -1, simm16,	---	18206	ACC128, -1, simm16,	---
18207	/* STORE_ACC64 */	---	18207	/* STORE_ACC64 */	---
18208	ACC64, -1, simm16,	---	18208	ACC64, -1, simm16,	---
18209	/* STORE_ACC64DSP */	---	18209	/* STORE_ACC64DSP */	---
18210	ACC64DSPOpnd, -1, simm16,	---	18210	ACC64DSPOpnd, -1, simm16,	---
18211	/* STORE_CCOND_DSP */	---	18211	/* STORE_CCOND_DSP */	---
18212	DSPCC, -1, simm16,	---	18212	DSPCC, -1, simm16,	---
18213	/* STR_D */	---	18213	/* STR_D */	---
18214	MSA128DOpnd, -1, GPR32,	---	18214	MSA128DOpnd, -1, GPR32,	---
18215	/* STR_W */	---	18215	/* STR_W */	---
18216	MSA128WOpnd, -1, GPR32,	---	18216	MSA128WOpnd, -1, GPR32,	---
18217	/* ST_F16 */	---	18217	/* ST_F16 */	---
18218	MSA128F16, -1, simm10,	---	18218	MSA128F16, -1, simm10,	---
18219	/* SWM_MM */	---	18219	/* SWM_MM */	---
18220	reglist, -1, simm12,	---	18220	reglist, -1, simm12,	---
18221	/* SZ_B_PSEUDO */	---	18221	/* SZ_B_PSEUDO */	---
18222	GPR32, MSA128B,	---	18222	GPR32, MSA128B,	---
18223	/* SZ_D_PSEUDO */	---	18223	/* SZ_D_PSEUDO */	---
18224	GPR32, MSA128D,	---	18224	GPR32, MSA128D,	---
18225	/* SZ_H_PSEUDO */	---	18225	/* SZ_H_PSEUDO */	---
18226	GPR32, MSA128H,	---	18226	GPR32, MSA128H,	---
18227	/* SZ_V_PSEUDO */	---	18227	/* SZ_V_PSEUDO */	---
18228	GPR32, MSA128B,	---	18228	GPR32, MSA128B,	---
18229	/* SZ_W_PSEUDO */	---	18229	/* SZ_W_PSEUDO */	---
18230	GPR32, MSA128W,	---	18230	GPR32, MSA128W,	---
18231	/* SaaAddr */	---	18231	/* SaaAddr */	---
18232	GPR64Opnd, -1, simm16,	---	18232	GPR64Opnd, -1, simm16,	---
18233	/* SaadAddr */	---	18233	/* SaadAddr */	---
18234	GPR64Opnd, -1, simm16,	---	18234	GPR64Opnd, -1, simm16,	---
18235	/* SelBeqZ */	---	18235	/* SelBeqZ */	---
18236	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18236	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18237	/* SelBneZ */	---	18237	/* SelBneZ */	---
18238	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18238	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18239	/* SelTBteqZCmp */	---	18239	/* SelTBteqZCmp */	---
18240	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18240	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18241	/* SelTBteqZCmpi */	---	18241	/* SelTBteqZCmpi */	---
18242	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18242	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18243	/* SelTBteqZSlt */	---	18243	/* SelTBteqZSlt */	---
18244	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18244	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18245	/* SelTBteqZSlti */	---	18245	/* SelTBteqZSlti */	---
18246	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18246	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18247	/* SelTBteqZSltiu */	---	18247	/* SelTBteqZSltiu */	---
18248	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18248	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18249	/* SelTBteqZSltu */	---	18249	/* SelTBteqZSltu */	---
18250	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18250	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18251	/* SelTBtneZCmp */	---	18251	/* SelTBtneZCmp */	---
18252	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18252	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18253	/* SelTBtneZCmpi */	---	18253	/* SelTBtneZCmpi */	---
18254	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18254	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18255	/* SelTBtneZSlt */	---	18255	/* SelTBtneZSlt */	---
18256	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18256	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18257	/* SelTBtneZSlti */	---	18257	/* SelTBtneZSlti */	---
18258	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18258	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18259	/* SelTBtneZSltiu */	---	18259	/* SelTBtneZSltiu */	---
18260	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---	18260	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,	---
18261	/* SelTBtneZSltu */	---	18261	/* SelTBtneZSltu */	---
18262	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---	18262	CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,	---
18263	/* SltCCRxRy16 */	---	18263	/* SltCCRxRy16 */	---
18264	CPU16Regs, CPU16Regs, CPU16Regs,	---	18264	CPU16Regs, CPU16Regs, CPU16Regs,	---
18265	/* SltiCCRxImmX16 */	---	18265	/* SltiCCRxImmX16 */	---
18266	CPU16Regs, CPU16Regs, simm16,	---	18266	CPU16Regs, CPU16Regs, simm16,	---
18267	/* SltiuCCRxImmX16 */	---	18267	/* SltiuCCRxImmX16 */	---
18268	CPU16Regs, CPU16Regs, simm16,	---	18268	CPU16Regs, CPU16Regs, simm16,	---
18269	/* SltuCCRxRy16 */	---	18269	/* SltuCCRxRy16 */	---
18270	CPU16Regs, CPU16Regs, CPU16Regs,	---	18270	CPU16Regs, CPU16Regs, CPU16Regs,	---
18271	/* SltuRxRyRz16 */	---	18271	/* SltuRxRyRz16 */	---
18272	CPU16Regs, CPU16Regs, CPU16Regs,	---	18272	CPU16Regs, CPU16Regs, CPU16Regs,	---
18273	/* TAILCALL */	---	18273	/* TAILCALL */	---
18274	calltarget,	---	18274	calltarget,	---
18275	/* TAILCALL64R6REG */	---	18275	/* TAILCALL64R6REG */	---
18276	GPR64Opnd,	---	18276	GPR64Opnd,	---
18277	/* TAILCALLHB64R6REG */	---	18277	/* TAILCALLHB64R6REG */	---
18278	GPR64Opnd,	---	18278	GPR64Opnd,	---
18279	/* TAILCALLHBR6REG */	---	18279	/* TAILCALLHBR6REG */	---
18280	GPR32Opnd,	---	18280	GPR32Opnd,	---
18281	/* TAILCALLR6REG */	---	18281	/* TAILCALLR6REG */	---
18282	GPR32Opnd,	---	18282	GPR32Opnd,	---
18283	/* TAILCALLREG */	---	18283	/* TAILCALLREG */	---
18284	GPR32Opnd,	---	18284	GPR32Opnd,	---
18285	/* TAILCALLREG64 */	---	18285	/* TAILCALLREG64 */	---
18286	GPR64Opnd,	---	18286	GPR64Opnd,	---
18287	/* TAILCALLREGHB */	---	18287	/* TAILCALLREGHB */	---
18288	GPR32Opnd,	---	18288	GPR32Opnd,	---
18289	/* TAILCALLREGHB64 */	---	18289	/* TAILCALLREGHB64 */	---
18290	GPR64Opnd,	---	18290	GPR64Opnd,	---
18291	/* TAILCALLREG_MM */	---	18291	/* TAILCALLREG_MM */	---
18292	GPR32Opnd,	---	18292	GPR32Opnd,	---
18293	/* TAILCALLREG_MMR6 */	---	18293	/* TAILCALLREG_MMR6 */	---
18294	GPR32Opnd,	---	18294	GPR32Opnd,	---
18295	/* TAILCALL_MM */	---	18295	/* TAILCALL_MM */	---
18296	calltarget,	---	18296	calltarget,	---
18297	/* TAILCALL_MMR6 */	---	18297	/* TAILCALL_MMR6 */	---
18298	calltarget,	---	18298	calltarget,	---
18299	/* TRAP */	---	18299	/* TRAP */	---
18300	/* TRAP_MM */	---	18300	/* TRAP_MM */	---
18301	/* UDIV_MM_Pseudo */	---	18301	/* UDIV_MM_Pseudo */	---
18302	ACC64, GPR32Opnd, GPR32Opnd,	---	18302	ACC64, GPR32Opnd, GPR32Opnd,	---
18303	/* UDivIMacro */	---	18303	/* UDivIMacro */	---
18304	GPR32Opnd, GPR32Opnd, simm32,	---	18304	GPR32Opnd, GPR32Opnd, simm32,	---
18305	/* UDivMacro */	---	18305	/* UDivMacro */	---
18306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18307	/* URemIMacro */	---	18307	/* URemIMacro */	---
18308	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---	18308	GPR32Opnd, GPR32Opnd, simm32_relaxed,	---
18309	/* URemMacro */	---	18309	/* URemMacro */	---
18310	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18310	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18311	/* Ulh */	---	18311	/* Ulh */	---
18312	GPR32Opnd, -1, simm16,	---	18312	GPR32Opnd, -1, simm16,	---
18313	/* Ulhu */	---	18313	/* Ulhu */	---
18314	GPR32Opnd, -1, simm16,	---	18314	GPR32Opnd, -1, simm16,	---
18315	/* Ulw */	---	18315	/* Ulw */	---
18316	GPR32Opnd, -1, simm16,	---	18316	GPR32Opnd, -1, simm16,	---
18317	/* Ush */	---	18317	/* Ush */	---
18318	GPR32Opnd, -1, simm16,	---	18318	GPR32Opnd, -1, simm16,	---
18319	/* Usw */	---	18319	/* Usw */	---
18320	GPR32Opnd, -1, simm16,	---	18320	GPR32Opnd, -1, simm16,	---
18321	/* XOR_V_D_PSEUDO */	---	18321	/* XOR_V_D_PSEUDO */	---
18322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18323	/* XOR_V_H_PSEUDO */	---	18323	/* XOR_V_H_PSEUDO */	---
18324	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18324	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18325	/* XOR_V_W_PSEUDO */	---	18325	/* XOR_V_W_PSEUDO */	---
18326	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18326	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18327	/* ABSQ_S_PH */	---	18327	/* ABSQ_S_PH */	---
18328	DSPROpnd, DSPROpnd,	---	18328	DSPROpnd, DSPROpnd,	---
18329	/* ABSQ_S_PH_MM */	---	18329	/* ABSQ_S_PH_MM */	---
18330	DSPROpnd, DSPROpnd,	---	18330	DSPROpnd, DSPROpnd,	---
18331	/* ABSQ_S_QB */	---	18331	/* ABSQ_S_QB */	---
18332	DSPROpnd, DSPROpnd,	---	18332	DSPROpnd, DSPROpnd,	---
18333	/* ABSQ_S_QB_MMR2 */	---	18333	/* ABSQ_S_QB_MMR2 */	---
18334	DSPROpnd, DSPROpnd,	---	18334	DSPROpnd, DSPROpnd,	---
18335	/* ABSQ_S_W */	---	18335	/* ABSQ_S_W */	---
18336	GPR32Opnd, GPR32Opnd,	---	18336	GPR32Opnd, GPR32Opnd,	---
18337	/* ABSQ_S_W_MM */	---	18337	/* ABSQ_S_W_MM */	---
18338	GPR32Opnd, GPR32Opnd,	---	18338	GPR32Opnd, GPR32Opnd,	---
18339	/* ADD */	---	18339	/* ADD */	---
18340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18341	/* ADDIUPC */	---	18341	/* ADDIUPC */	---
18342	GPR32Opnd, simm19_lsl2,	---	18342	GPR32Opnd, simm19_lsl2,	---
18343	/* ADDIUPC_MM */	---	18343	/* ADDIUPC_MM */	---
18344	GPRMM16Opnd, simm23_lsl2,	---	18344	GPRMM16Opnd, simm23_lsl2,	---
18345	/* ADDIUPC_MMR6 */	---	18345	/* ADDIUPC_MMR6 */	---
18346	GPR32Opnd, simm19_lsl2,	---	18346	GPR32Opnd, simm19_lsl2,	---
18347	/* ADDIUR1SP_MM */	---	18347	/* ADDIUR1SP_MM */	---
18348	GPRMM16Opnd, uimm6_lsl2,	---	18348	GPRMM16Opnd, uimm6_lsl2,	---
18349	/* ADDIUR2_MM */	---	18349	/* ADDIUR2_MM */	---
18350	GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,	---	18350	GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,	---
18351	/* ADDIUS5_MM */	---	18351	/* ADDIUS5_MM */	---
18352	GPR32Opnd, GPR32Opnd, simm4,	---	18352	GPR32Opnd, GPR32Opnd, simm4,	---
18353	/* ADDIUSP_MM */	---	18353	/* ADDIUSP_MM */	---
18354	simm9_addiusp,	---	18354	simm9_addiusp,	---
18355	/* ADDIU_MMR6 */	---	18355	/* ADDIU_MMR6 */	---
18356	GPR32Opnd, GPR32Opnd, simm16,	---	18356	GPR32Opnd, GPR32Opnd, simm16,	---
18357	/* ADDQH_PH */	---	18357	/* ADDQH_PH */	---
18358	DSPROpnd, DSPROpnd, DSPROpnd,	---	18358	DSPROpnd, DSPROpnd, DSPROpnd,	---
18359	/* ADDQH_PH_MMR2 */	---	18359	/* ADDQH_PH_MMR2 */	---
18360	DSPROpnd, DSPROpnd, DSPROpnd,	---	18360	DSPROpnd, DSPROpnd, DSPROpnd,	---
18361	/* ADDQH_R_PH */	---	18361	/* ADDQH_R_PH */	---
18362	DSPROpnd, DSPROpnd, DSPROpnd,	---	18362	DSPROpnd, DSPROpnd, DSPROpnd,	---
18363	/* ADDQH_R_PH_MMR2 */	---	18363	/* ADDQH_R_PH_MMR2 */	---
18364	DSPROpnd, DSPROpnd, DSPROpnd,	---	18364	DSPROpnd, DSPROpnd, DSPROpnd,	---
18365	/* ADDQH_R_W */	---	18365	/* ADDQH_R_W */	---
18366	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18366	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18367	/* ADDQH_R_W_MMR2 */	---	18367	/* ADDQH_R_W_MMR2 */	---
18368	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18368	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18369	/* ADDQH_W */	---	18369	/* ADDQH_W */	---
18370	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18370	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18371	/* ADDQH_W_MMR2 */	---	18371	/* ADDQH_W_MMR2 */	---
18372	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18372	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18373	/* ADDQ_PH */	---	18373	/* ADDQ_PH */	---
18374	DSPROpnd, DSPROpnd, DSPROpnd,	---	18374	DSPROpnd, DSPROpnd, DSPROpnd,	---
18375	/* ADDQ_PH_MM */	---	18375	/* ADDQ_PH_MM */	---
18376	DSPROpnd, DSPROpnd, DSPROpnd,	---	18376	DSPROpnd, DSPROpnd, DSPROpnd,	---
18377	/* ADDQ_S_PH */	---	18377	/* ADDQ_S_PH */	---
18378	DSPROpnd, DSPROpnd, DSPROpnd,	---	18378	DSPROpnd, DSPROpnd, DSPROpnd,	---
18379	/* ADDQ_S_PH_MM */	---	18379	/* ADDQ_S_PH_MM */	---
18380	DSPROpnd, DSPROpnd, DSPROpnd,	---	18380	DSPROpnd, DSPROpnd, DSPROpnd,	---
18381	/* ADDQ_S_W */	---	18381	/* ADDQ_S_W */	---
18382	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18382	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18383	/* ADDQ_S_W_MM */	---	18383	/* ADDQ_S_W_MM */	---
18384	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18384	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18385	/* ADDR_PS64 */	---	18385	/* ADDR_PS64 */	---
18386	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	18386	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
18387	/* ADDSC */	---	18387	/* ADDSC */	---
18388	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18388	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18389	/* ADDSC_MM */	---	18389	/* ADDSC_MM */	---
18390	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18390	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18391	/* ADDS_A_B */	---	18391	/* ADDS_A_B */	---
18392	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18392	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18393	/* ADDS_A_D */	---	18393	/* ADDS_A_D */	---
18394	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18394	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18395	/* ADDS_A_H */	---	18395	/* ADDS_A_H */	---
18396	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18396	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18397	/* ADDS_A_W */	---	18397	/* ADDS_A_W */	---
18398	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18398	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18399	/* ADDS_S_B */	---	18399	/* ADDS_S_B */	---
18400	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18400	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18401	/* ADDS_S_D */	---	18401	/* ADDS_S_D */	---
18402	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18402	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18403	/* ADDS_S_H */	---	18403	/* ADDS_S_H */	---
18404	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18404	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18405	/* ADDS_S_W */	---	18405	/* ADDS_S_W */	---
18406	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18406	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18407	/* ADDS_U_B */	---	18407	/* ADDS_U_B */	---
18408	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18408	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18409	/* ADDS_U_D */	---	18409	/* ADDS_U_D */	---
18410	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18410	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18411	/* ADDS_U_H */	---	18411	/* ADDS_U_H */	---
18412	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18412	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18413	/* ADDS_U_W */	---	18413	/* ADDS_U_W */	---
18414	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18414	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18415	/* ADDU16_MM */	---	18415	/* ADDU16_MM */	---
18416	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	18416	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
18417	/* ADDU16_MMR6 */	---	18417	/* ADDU16_MMR6 */	---
18418	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	18418	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
18419	/* ADDUH_QB */	---	18419	/* ADDUH_QB */	---
18420	DSPROpnd, DSPROpnd, DSPROpnd,	---	18420	DSPROpnd, DSPROpnd, DSPROpnd,	---
18421	/* ADDUH_QB_MMR2 */	---	18421	/* ADDUH_QB_MMR2 */	---
18422	DSPROpnd, DSPROpnd, DSPROpnd,	---	18422	DSPROpnd, DSPROpnd, DSPROpnd,	---
18423	/* ADDUH_R_QB */	---	18423	/* ADDUH_R_QB */	---
18424	DSPROpnd, DSPROpnd, DSPROpnd,	---	18424	DSPROpnd, DSPROpnd, DSPROpnd,	---
18425	/* ADDUH_R_QB_MMR2 */	---	18425	/* ADDUH_R_QB_MMR2 */	---
18426	DSPROpnd, DSPROpnd, DSPROpnd,	---	18426	DSPROpnd, DSPROpnd, DSPROpnd,	---
18427	/* ADDU_MMR6 */	---	18427	/* ADDU_MMR6 */	---
18428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18429	/* ADDU_PH */	---	18429	/* ADDU_PH */	---
18430	DSPROpnd, DSPROpnd, DSPROpnd,	---	18430	DSPROpnd, DSPROpnd, DSPROpnd,	---
18431	/* ADDU_PH_MMR2 */	---	18431	/* ADDU_PH_MMR2 */	---
18432	DSPROpnd, DSPROpnd, DSPROpnd,	---	18432	DSPROpnd, DSPROpnd, DSPROpnd,	---
18433	/* ADDU_QB */	---	18433	/* ADDU_QB */	---
18434	DSPROpnd, DSPROpnd, DSPROpnd,	---	18434	DSPROpnd, DSPROpnd, DSPROpnd,	---
18435	/* ADDU_QB_MM */	---	18435	/* ADDU_QB_MM */	---
18436	DSPROpnd, DSPROpnd, DSPROpnd,	---	18436	DSPROpnd, DSPROpnd, DSPROpnd,	---
18437	/* ADDU_S_PH */	---	18437	/* ADDU_S_PH */	---
18438	DSPROpnd, DSPROpnd, DSPROpnd,	---	18438	DSPROpnd, DSPROpnd, DSPROpnd,	---
18439	/* ADDU_S_PH_MMR2 */	---	18439	/* ADDU_S_PH_MMR2 */	---
18440	DSPROpnd, DSPROpnd, DSPROpnd,	---	18440	DSPROpnd, DSPROpnd, DSPROpnd,	---
18441	/* ADDU_S_QB */	---	18441	/* ADDU_S_QB */	---
18442	DSPROpnd, DSPROpnd, DSPROpnd,	---	18442	DSPROpnd, DSPROpnd, DSPROpnd,	---
18443	/* ADDU_S_QB_MM */	---	18443	/* ADDU_S_QB_MM */	---
18444	DSPROpnd, DSPROpnd, DSPROpnd,	---	18444	DSPROpnd, DSPROpnd, DSPROpnd,	---
18445	/* ADDVI_B */	---	18445	/* ADDVI_B */	---
18446	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	18446	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
18447	/* ADDVI_D */	---	18447	/* ADDVI_D */	---
18448	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	18448	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
18449	/* ADDVI_H */	---	18449	/* ADDVI_H */	---
18450	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	18450	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
18451	/* ADDVI_W */	---	18451	/* ADDVI_W */	---
18452	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18452	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18453	/* ADDV_B */	---	18453	/* ADDV_B */	---
18454	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18454	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18455	/* ADDV_D */	---	18455	/* ADDV_D */	---
18456	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18456	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18457	/* ADDV_H */	---	18457	/* ADDV_H */	---
18458	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18458	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18459	/* ADDV_W */	---	18459	/* ADDV_W */	---
18460	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18460	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18461	/* ADDWC */	---	18461	/* ADDWC */	---
18462	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18462	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18463	/* ADDWC_MM */	---	18463	/* ADDWC_MM */	---
18464	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18464	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18465	/* ADD_A_B */	---	18465	/* ADD_A_B */	---
18466	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18466	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18467	/* ADD_A_D */	---	18467	/* ADD_A_D */	---
18468	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18468	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18469	/* ADD_A_H */	---	18469	/* ADD_A_H */	---
18470	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18470	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18471	/* ADD_A_W */	---	18471	/* ADD_A_W */	---
18472	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18472	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18473	/* ADD_MM */	---	18473	/* ADD_MM */	---
18474	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18474	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18475	/* ADD_MMR6 */	---	18475	/* ADD_MMR6 */	---
18476	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18476	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18477	/* ADDi */	---	18477	/* ADDi */	---
18478	GPR32Opnd, GPR32Opnd, simm16_relaxed,	---	18478	GPR32Opnd, GPR32Opnd, simm16_relaxed,	---
18479	/* ADDi_MM */	---	18479	/* ADDi_MM */	---
18480	GPR32Opnd, GPR32Opnd, simm16,	---	18480	GPR32Opnd, GPR32Opnd, simm16,	---
18481	/* ADDiu */	---	18481	/* ADDiu */	---
18482	GPR32Opnd, GPR32Opnd, simm16_relaxed,	---	18482	GPR32Opnd, GPR32Opnd, simm16_relaxed,	---
18483	/* ADDiu_MM */	---	18483	/* ADDiu_MM */	---
18484	GPR32Opnd, GPR32Opnd, simm16,	---	18484	GPR32Opnd, GPR32Opnd, simm16,	---
18485	/* ADDu */	---	18485	/* ADDu */	---
18486	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18486	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18487	/* ADDu_MM */	---	18487	/* ADDu_MM */	---
18488	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18488	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18489	/* ALIGN */	---	18489	/* ALIGN */	---
18490	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	---	18490	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	---
18491	/* ALIGN_MMR6 */	---	18491	/* ALIGN_MMR6 */	---
18492	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	---	18492	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,	---
18493	/* ALUIPC */	---	18493	/* ALUIPC */	---
18494	GPR32Opnd, simm16,	---	18494	GPR32Opnd, simm16,	---
18495	/* ALUIPC_MMR6 */	---	18495	/* ALUIPC_MMR6 */	---
18496	GPR32Opnd, simm16,	---	18496	GPR32Opnd, simm16,	---
18497	/* AND */	---	18497	/* AND */	---
18498	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18498	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18499	/* AND16_MM */	---	18499	/* AND16_MM */	---
18500	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	18500	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
18501	/* AND16_MMR6 */	---	18501	/* AND16_MMR6 */	---
18502	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	18502	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
18503	/* AND64 */	---	18503	/* AND64 */	---
18504	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	18504	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
18505	/* ANDI16_MM */	---	18505	/* ANDI16_MM */	---
18506	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	---	18506	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	---
18507	/* ANDI16_MMR6 */	---	18507	/* ANDI16_MMR6 */	---
18508	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	---	18508	GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,	---
18509	/* ANDI_B */	---	18509	/* ANDI_B */	---
18510	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	18510	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
18511	/* ANDI_MMR6 */	---	18511	/* ANDI_MMR6 */	---
18512	GPR32Opnd, GPR32Opnd, uimm16,	---	18512	GPR32Opnd, GPR32Opnd, uimm16,	---
18513	/* AND_MM */	---	18513	/* AND_MM */	---
18514	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18514	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18515	/* AND_MMR6 */	---	18515	/* AND_MMR6 */	---
18516	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	18516	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
18517	/* AND_V */	---	18517	/* AND_V */	---
18518	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18518	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18519	/* ANDi */	---	18519	/* ANDi */	---
18520	GPR32Opnd, GPR32Opnd, uimm16,	---	18520	GPR32Opnd, GPR32Opnd, uimm16,	---
18521	/* ANDi64 */	---	18521	/* ANDi64 */	---
18522	GPR64Opnd, GPR64Opnd, uimm16_64,	---	18522	GPR64Opnd, GPR64Opnd, uimm16_64,	---
18523	/* ANDi_MM */	---	18523	/* ANDi_MM */	---
18524	GPR32Opnd, GPR32Opnd, uimm16,	---	18524	GPR32Opnd, GPR32Opnd, uimm16,	---
18525	/* APPEND */	---	18525	/* APPEND */	---
18526	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---	18526	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---
18527	/* APPEND_MMR2 */	---	18527	/* APPEND_MMR2 */	---
18528	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---	18528	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---
18529	/* ASUB_S_B */	---	18529	/* ASUB_S_B */	---
18530	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18530	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18531	/* ASUB_S_D */	---	18531	/* ASUB_S_D */	---
18532	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18532	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18533	/* ASUB_S_H */	---	18533	/* ASUB_S_H */	---
18534	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18534	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18535	/* ASUB_S_W */	---	18535	/* ASUB_S_W */	---
18536	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18536	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18537	/* ASUB_U_B */	---	18537	/* ASUB_U_B */	---
18538	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18538	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18539	/* ASUB_U_D */	---	18539	/* ASUB_U_D */	---
18540	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18540	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18541	/* ASUB_U_H */	---	18541	/* ASUB_U_H */	---
18542	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18542	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18543	/* ASUB_U_W */	---	18543	/* ASUB_U_W */	---
18544	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18544	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18545	/* AUI */	---	18545	/* AUI */	---
18546	GPR32Opnd, GPR32Opnd, uimm16,	---	18546	GPR32Opnd, GPR32Opnd, uimm16,	---
18547	/* AUIPC */	---	18547	/* AUIPC */	---
18548	GPR32Opnd, simm16,	---	18548	GPR32Opnd, simm16,	---
18549	/* AUIPC_MMR6 */	---	18549	/* AUIPC_MMR6 */	---
18550	GPR32Opnd, simm16,	---	18550	GPR32Opnd, simm16,	---
18551	/* AUI_MMR6 */	---	18551	/* AUI_MMR6 */	---
18552	GPR32Opnd, GPR32Opnd, uimm16,	---	18552	GPR32Opnd, GPR32Opnd, uimm16,	---
18553	/* AVER_S_B */	---	18553	/* AVER_S_B */	---
18554	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18554	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18555	/* AVER_S_D */	---	18555	/* AVER_S_D */	---
18556	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18556	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18557	/* AVER_S_H */	---	18557	/* AVER_S_H */	---
18558	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18558	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18559	/* AVER_S_W */	---	18559	/* AVER_S_W */	---
18560	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18560	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18561	/* AVER_U_B */	---	18561	/* AVER_U_B */	---
18562	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18562	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18563	/* AVER_U_D */	---	18563	/* AVER_U_D */	---
18564	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18564	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18565	/* AVER_U_H */	---	18565	/* AVER_U_H */	---
18566	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18566	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18567	/* AVER_U_W */	---	18567	/* AVER_U_W */	---
18568	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18568	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18569	/* AVE_S_B */	---	18569	/* AVE_S_B */	---
18570	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18570	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18571	/* AVE_S_D */	---	18571	/* AVE_S_D */	---
18572	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18572	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18573	/* AVE_S_H */	---	18573	/* AVE_S_H */	---
18574	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18574	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18575	/* AVE_S_W */	---	18575	/* AVE_S_W */	---
18576	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18576	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18577	/* AVE_U_B */	---	18577	/* AVE_U_B */	---
18578	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18578	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18579	/* AVE_U_D */	---	18579	/* AVE_U_D */	---
18580	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18580	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18581	/* AVE_U_H */	---	18581	/* AVE_U_H */	---
18582	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18582	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18583	/* AVE_U_W */	---	18583	/* AVE_U_W */	---
18584	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18584	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18585	/* AddiuRxImmX16 */	---	18585	/* AddiuRxImmX16 */	---
18586	CPU16Regs, simm16,	---	18586	CPU16Regs, simm16,	---
18587	/* AddiuRxPcImmX16 */	---	18587	/* AddiuRxPcImmX16 */	---
18588	CPU16Regs, simm16,	---	18588	CPU16Regs, simm16,	---
18589	/* AddiuRxRxImm16 */	---	18589	/* AddiuRxRxImm16 */	---
18590	CPU16Regs, CPU16Regs, simm16,	---	18590	CPU16Regs, CPU16Regs, simm16,	---
18591	/* AddiuRxRxImmX16 */	---	18591	/* AddiuRxRxImmX16 */	---
18592	CPU16Regs, CPU16Regs, simm16,	---	18592	CPU16Regs, CPU16Regs, simm16,	---
18593	/* AddiuRxRyOffMemX16 */	---	18593	/* AddiuRxRyOffMemX16 */	---
18594	CPU16Regs, CPU16RegsPlusSP, simm16,	---	18594	CPU16Regs, CPU16RegsPlusSP, simm16,	---
18595	/* AddiuSpImm16 */	---	18595	/* AddiuSpImm16 */	---
18596	simm16,	---	18596	simm16,	---
18597	/* AddiuSpImmX16 */	---	18597	/* AddiuSpImmX16 */	---
18598	simm16,	---	18598	simm16,	---
18599	/* AdduRxRyRz16 */	---	18599	/* AdduRxRyRz16 */	---
18600	CPU16Regs, CPU16Regs, CPU16Regs,	---	18600	CPU16Regs, CPU16Regs, CPU16Regs,	---
18601	/* AndRxRxRy16 */	---	18601	/* AndRxRxRy16 */	---
18602	CPU16Regs, CPU16Regs, CPU16Regs,	---	18602	CPU16Regs, CPU16Regs, CPU16Regs,	---
18603	/* B16_MM */	---	18603	/* B16_MM */	---
18604	brtarget10_mm,	---	18604	brtarget10_mm,	---
18605	/* BADDu */	---	18605	/* BADDu */	---
18606	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	18606	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
18607	/* BAL */	---	18607	/* BAL */	---
18608	brtarget,	---	18608	brtarget,	---
18609	/* BALC */	---	18609	/* BALC */	---
18610	brtarget26,	---	18610	brtarget26,	---
18611	/* BALC_MMR6 */	---	18611	/* BALC_MMR6 */	---
18612	brtarget26_mm,	---	18612	brtarget26_mm,	---
18613	/* BALIGN */	---	18613	/* BALIGN */	---
18614	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	---	18614	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	---
18615	/* BALIGN_MMR2 */	---	18615	/* BALIGN_MMR2 */	---
18616	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	---	18616	GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,	---
18617	/* BBIT0 */	---	18617	/* BBIT0 */	---
18618	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	---	18618	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	---
18619	/* BBIT032 */	---	18619	/* BBIT032 */	---
18620	GPR64Opnd, uimm5_64, brtarget,	---	18620	GPR64Opnd, uimm5_64, brtarget,	---
18621	/* BBIT1 */	---	18621	/* BBIT1 */	---
18622	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	---	18622	GPR64Opnd, uimm5_64_report_uimm6, brtarget,	---
18623	/* BBIT132 */	---	18623	/* BBIT132 */	---
18624	GPR64Opnd, uimm5_64, brtarget,	---	18624	GPR64Opnd, uimm5_64, brtarget,	---
18625	/* BC */	---	18625	/* BC */	---
18626	brtarget26,	---	18626	brtarget26,	---
18627	/* BC16_MMR6 */	---	18627	/* BC16_MMR6 */	---
18628	brtarget10_mm,	---	18628	brtarget10_mm,	---
18629	/* BC1EQZ */	---	18629	/* BC1EQZ */	---
18630	FGR64Opnd, brtarget,	---	18630	FGR64Opnd, brtarget,	---
18631	/* BC1EQZC_MMR6 */	---	18631	/* BC1EQZC_MMR6 */	---
18632	FGR64Opnd, brtarget_mm,	---	18632	FGR64Opnd, brtarget_mm,	---
18633	/* BC1F */	---	18633	/* BC1F */	---
18634	FCCRegsOpnd, brtarget,	---	18634	FCCRegsOpnd, brtarget,	---
18635	/* BC1FL */	---	18635	/* BC1FL */	---
18636	FCCRegsOpnd, brtarget,	---	18636	FCCRegsOpnd, brtarget,	---
18637	/* BC1F_MM */	---	18637	/* BC1F_MM */	---
18638	FCCRegsOpnd, brtarget_mm,	---	18638	FCCRegsOpnd, brtarget_mm,	---
18639	/* BC1NEZ */	---	18639	/* BC1NEZ */	---
18640	FGR64Opnd, brtarget,	---	18640	FGR64Opnd, brtarget,	---
18641	/* BC1NEZC_MMR6 */	---	18641	/* BC1NEZC_MMR6 */	---
18642	FGR64Opnd, brtarget_mm,	---	18642	FGR64Opnd, brtarget_mm,	---
18643	/* BC1T */	---	18643	/* BC1T */	---
18644	FCCRegsOpnd, brtarget,	---	18644	FCCRegsOpnd, brtarget,	---
18645	/* BC1TL */	---	18645	/* BC1TL */	---
18646	FCCRegsOpnd, brtarget,	---	18646	FCCRegsOpnd, brtarget,	---
18647	/* BC1T_MM */	---	18647	/* BC1T_MM */	---
18648	FCCRegsOpnd, brtarget_mm,	---	18648	FCCRegsOpnd, brtarget_mm,	---
18649	/* BC2EQZ */	---	18649	/* BC2EQZ */	---
18650	COP2Opnd, brtarget,	---	18650	COP2Opnd, brtarget,	---
18651	/* BC2EQZC_MMR6 */	---	18651	/* BC2EQZC_MMR6 */	---
18652	COP2Opnd, brtarget_mm,	---	18652	COP2Opnd, brtarget_mm,	---
18653	/* BC2NEZ */	---	18653	/* BC2NEZ */	---
18654	COP2Opnd, brtarget,	---	18654	COP2Opnd, brtarget,	---
18655	/* BC2NEZC_MMR6 */	---	18655	/* BC2NEZC_MMR6 */	---
18656	COP2Opnd, brtarget_mm,	---	18656	COP2Opnd, brtarget_mm,	---
18657	/* BCLRI_B */	---	18657	/* BCLRI_B */	---
18658	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	18658	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
18659	/* BCLRI_D */	---	18659	/* BCLRI_D */	---
18660	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	18660	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
18661	/* BCLRI_H */	---	18661	/* BCLRI_H */	---
18662	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	18662	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
18663	/* BCLRI_W */	---	18663	/* BCLRI_W */	---
18664	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18664	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18665	/* BCLR_B */	---	18665	/* BCLR_B */	---
18666	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18666	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18667	/* BCLR_D */	---	18667	/* BCLR_D */	---
18668	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18668	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18669	/* BCLR_H */	---	18669	/* BCLR_H */	---
18670	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18670	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18671	/* BCLR_W */	---	18671	/* BCLR_W */	---
18672	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18672	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18673	/* BC_MMR6 */	---	18673	/* BC_MMR6 */	---
18674	brtarget26_mm,	---	18674	brtarget26_mm,	---
18675	/* BEQ */	---	18675	/* BEQ */	---
18676	GPR32Opnd, GPR32Opnd, brtarget,	---	18676	GPR32Opnd, GPR32Opnd, brtarget,	---
18677	/* BEQ64 */	---	18677	/* BEQ64 */	---
18678	GPR64Opnd, GPR64Opnd, brtarget,	---	18678	GPR64Opnd, GPR64Opnd, brtarget,	---
18679	/* BEQC */	---	18679	/* BEQC */	---
18680	GPR32Opnd, GPR32Opnd, brtarget,	---	18680	GPR32Opnd, GPR32Opnd, brtarget,	---
18681	/* BEQC64 */	---	18681	/* BEQC64 */	---
18682	GPR64Opnd, GPR64Opnd, brtarget,	---	18682	GPR64Opnd, GPR64Opnd, brtarget,	---
18683	/* BEQC_MMR6 */	---	18683	/* BEQC_MMR6 */	---
18684	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18684	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18685	/* BEQL */	---	18685	/* BEQL */	---
18686	GPR32Opnd, GPR32Opnd, brtarget,	---	18686	GPR32Opnd, GPR32Opnd, brtarget,	---
18687	/* BEQZ16_MM */	---	18687	/* BEQZ16_MM */	---
18688	GPRMM16Opnd, brtarget7_mm,	---	18688	GPRMM16Opnd, brtarget7_mm,	---
18689	/* BEQZALC */	---	18689	/* BEQZALC */	---
18690	GPR32Opnd, brtarget,	---	18690	GPR32Opnd, brtarget,	---
18691	/* BEQZALC_MMR6 */	---	18691	/* BEQZALC_MMR6 */	---
18692	GPR32Opnd, brtarget_mm,	---	18692	GPR32Opnd, brtarget_mm,	---
18693	/* BEQZC */	---	18693	/* BEQZC */	---
18694	GPR32Opnd, brtarget21,	---	18694	GPR32Opnd, brtarget21,	---
18695	/* BEQZC16_MMR6 */	---	18695	/* BEQZC16_MMR6 */	---
18696	GPRMM16Opnd, brtarget7_mm,	---	18696	GPRMM16Opnd, brtarget7_mm,	---
18697	/* BEQZC64 */	---	18697	/* BEQZC64 */	---
18698	GPR64Opnd, brtarget21,	---	18698	GPR64Opnd, brtarget21,	---
18699	/* BEQZC_MM */	---	18699	/* BEQZC_MM */	---
18700	GPR32Opnd, brtarget_mm,	---	18700	GPR32Opnd, brtarget_mm,	---
18701	/* BEQZC_MMR6 */	---	18701	/* BEQZC_MMR6 */	---
18702	GPR32Opnd, brtarget21_mm,	---	18702	GPR32Opnd, brtarget21_mm,	---
18703	/* BEQ_MM */	---	18703	/* BEQ_MM */	---
18704	GPR32Opnd, GPR32Opnd, brtarget_mm,	---	18704	GPR32Opnd, GPR32Opnd, brtarget_mm,	---
18705	/* BGEC */	---	18705	/* BGEC */	---
18706	GPR32Opnd, GPR32Opnd, brtarget,	---	18706	GPR32Opnd, GPR32Opnd, brtarget,	---
18707	/* BGEC64 */	---	18707	/* BGEC64 */	---
18708	GPR64Opnd, GPR64Opnd, brtarget,	---	18708	GPR64Opnd, GPR64Opnd, brtarget,	---
18709	/* BGEC_MMR6 */	---	18709	/* BGEC_MMR6 */	---
18710	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18710	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18711	/* BGEUC */	---	18711	/* BGEUC */	---
18712	GPR32Opnd, GPR32Opnd, brtarget,	---	18712	GPR32Opnd, GPR32Opnd, brtarget,	---
18713	/* BGEUC64 */	---	18713	/* BGEUC64 */	---
18714	GPR64Opnd, GPR64Opnd, brtarget,	---	18714	GPR64Opnd, GPR64Opnd, brtarget,	---
18715	/* BGEUC_MMR6 */	---	18715	/* BGEUC_MMR6 */	---
18716	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18716	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18717	/* BGEZ */	---	18717	/* BGEZ */	---
18718	GPR32Opnd, brtarget,	---	18718	GPR32Opnd, brtarget,	---
18719	/* BGEZ64 */	---	18719	/* BGEZ64 */	---
18720	GPR64Opnd, brtarget,	---	18720	GPR64Opnd, brtarget,	---
18721	/* BGEZAL */	---	18721	/* BGEZAL */	---
18722	GPR32Opnd, brtarget,	---	18722	GPR32Opnd, brtarget,	---
18723	/* BGEZALC */	---	18723	/* BGEZALC */	---
18724	GPR32Opnd, brtarget,	---	18724	GPR32Opnd, brtarget,	---
18725	/* BGEZALC_MMR6 */	---	18725	/* BGEZALC_MMR6 */	---
18726	GPR32Opnd, brtarget_mm,	---	18726	GPR32Opnd, brtarget_mm,	---
18727	/* BGEZALL */	---	18727	/* BGEZALL */	---
18728	GPR32Opnd, brtarget,	---	18728	GPR32Opnd, brtarget,	---
18729	/* BGEZALS_MM */	---	18729	/* BGEZALS_MM */	---
18730	GPR32Opnd, brtarget_mm,	---	18730	GPR32Opnd, brtarget_mm,	---
18731	/* BGEZAL_MM */	---	18731	/* BGEZAL_MM */	---
18732	GPR32Opnd, brtarget_mm,	---	18732	GPR32Opnd, brtarget_mm,	---
18733	/* BGEZC */	---	18733	/* BGEZC */	---
18734	GPR32Opnd, brtarget,	---	18734	GPR32Opnd, brtarget,	---
18735	/* BGEZC64 */	---	18735	/* BGEZC64 */	---
18736	GPR64Opnd, brtarget,	---	18736	GPR64Opnd, brtarget,	---
18737	/* BGEZC_MMR6 */	---	18737	/* BGEZC_MMR6 */	---
18738	GPR32Opnd, brtarget_lsl2_mm,	---	18738	GPR32Opnd, brtarget_lsl2_mm,	---
18739	/* BGEZL */	---	18739	/* BGEZL */	---
18740	GPR32Opnd, brtarget,	---	18740	GPR32Opnd, brtarget,	---
18741	/* BGEZ_MM */	---	18741	/* BGEZ_MM */	---
18742	GPR32Opnd, brtarget_mm,	---	18742	GPR32Opnd, brtarget_mm,	---
18743	/* BGTZ */	---	18743	/* BGTZ */	---
18744	GPR32Opnd, brtarget,	---	18744	GPR32Opnd, brtarget,	---
18745	/* BGTZ64 */	---	18745	/* BGTZ64 */	---
18746	GPR64Opnd, brtarget,	---	18746	GPR64Opnd, brtarget,	---
18747	/* BGTZALC */	---	18747	/* BGTZALC */	---
18748	GPR32Opnd, brtarget,	---	18748	GPR32Opnd, brtarget,	---
18749	/* BGTZALC_MMR6 */	---	18749	/* BGTZALC_MMR6 */	---
18750	GPR32Opnd, brtarget_mm,	---	18750	GPR32Opnd, brtarget_mm,	---
18751	/* BGTZC */	---	18751	/* BGTZC */	---
18752	GPR32Opnd, brtarget,	---	18752	GPR32Opnd, brtarget,	---
18753	/* BGTZC64 */	---	18753	/* BGTZC64 */	---
18754	GPR64Opnd, brtarget,	---	18754	GPR64Opnd, brtarget,	---
18755	/* BGTZC_MMR6 */	---	18755	/* BGTZC_MMR6 */	---
18756	GPR32Opnd, brtarget_lsl2_mm,	---	18756	GPR32Opnd, brtarget_lsl2_mm,	---
18757	/* BGTZL */	---	18757	/* BGTZL */	---
18758	GPR32Opnd, brtarget,	---	18758	GPR32Opnd, brtarget,	---
18759	/* BGTZ_MM */	---	18759	/* BGTZ_MM */	---
18760	GPR32Opnd, brtarget_mm,	---	18760	GPR32Opnd, brtarget_mm,	---
18761	/* BINSLI_B */	---	18761	/* BINSLI_B */	---
18762	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	18762	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
18763	/* BINSLI_D */	---	18763	/* BINSLI_D */	---
18764	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	18764	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
18765	/* BINSLI_H */	---	18765	/* BINSLI_H */	---
18766	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	18766	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
18767	/* BINSLI_W */	---	18767	/* BINSLI_W */	---
18768	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18768	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18769	/* BINSL_B */	---	18769	/* BINSL_B */	---
18770	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18770	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18771	/* BINSL_D */	---	18771	/* BINSL_D */	---
18772	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18772	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18773	/* BINSL_H */	---	18773	/* BINSL_H */	---
18774	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18774	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18775	/* BINSL_W */	---	18775	/* BINSL_W */	---
18776	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18776	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18777	/* BINSRI_B */	---	18777	/* BINSRI_B */	---
18778	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	18778	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
18779	/* BINSRI_D */	---	18779	/* BINSRI_D */	---
18780	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	18780	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
18781	/* BINSRI_H */	---	18781	/* BINSRI_H */	---
18782	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	18782	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
18783	/* BINSRI_W */	---	18783	/* BINSRI_W */	---
18784	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18784	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18785	/* BINSR_B */	---	18785	/* BINSR_B */	---
18786	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18786	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18787	/* BINSR_D */	---	18787	/* BINSR_D */	---
18788	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18788	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18789	/* BINSR_H */	---	18789	/* BINSR_H */	---
18790	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18790	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18791	/* BINSR_W */	---	18791	/* BINSR_W */	---
18792	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18792	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18793	/* BITREV */	---	18793	/* BITREV */	---
18794	GPR32Opnd, GPR32Opnd,	---	18794	GPR32Opnd, GPR32Opnd,	---
18795	/* BITREV_MM */	---	18795	/* BITREV_MM */	---
18796	GPR32Opnd, GPR32Opnd,	---	18796	GPR32Opnd, GPR32Opnd,	---
18797	/* BITSWAP */	---	18797	/* BITSWAP */	---
18798	GPR32Opnd, GPR32Opnd,	---	18798	GPR32Opnd, GPR32Opnd,	---
18799	/* BITSWAP_MMR6 */	---	18799	/* BITSWAP_MMR6 */	---
18800	GPR32Opnd, GPR32Opnd,	---	18800	GPR32Opnd, GPR32Opnd,	---
18801	/* BLEZ */	---	18801	/* BLEZ */	---
18802	GPR32Opnd, brtarget,	---	18802	GPR32Opnd, brtarget,	---
18803	/* BLEZ64 */	---	18803	/* BLEZ64 */	---
18804	GPR64Opnd, brtarget,	---	18804	GPR64Opnd, brtarget,	---
18805	/* BLEZALC */	---	18805	/* BLEZALC */	---
18806	GPR32Opnd, brtarget,	---	18806	GPR32Opnd, brtarget,	---
18807	/* BLEZALC_MMR6 */	---	18807	/* BLEZALC_MMR6 */	---
18808	GPR32Opnd, brtarget_mm,	---	18808	GPR32Opnd, brtarget_mm,	---
18809	/* BLEZC */	---	18809	/* BLEZC */	---
18810	GPR32Opnd, brtarget,	---	18810	GPR32Opnd, brtarget,	---
18811	/* BLEZC64 */	---	18811	/* BLEZC64 */	---
18812	GPR64Opnd, brtarget,	---	18812	GPR64Opnd, brtarget,	---
18813	/* BLEZC_MMR6 */	---	18813	/* BLEZC_MMR6 */	---
18814	GPR32Opnd, brtarget_lsl2_mm,	---	18814	GPR32Opnd, brtarget_lsl2_mm,	---
18815	/* BLEZL */	---	18815	/* BLEZL */	---
18816	GPR32Opnd, brtarget,	---	18816	GPR32Opnd, brtarget,	---
18817	/* BLEZ_MM */	---	18817	/* BLEZ_MM */	---
18818	GPR32Opnd, brtarget_mm,	---	18818	GPR32Opnd, brtarget_mm,	---
18819	/* BLTC */	---	18819	/* BLTC */	---
18820	GPR32Opnd, GPR32Opnd, brtarget,	---	18820	GPR32Opnd, GPR32Opnd, brtarget,	---
18821	/* BLTC64 */	---	18821	/* BLTC64 */	---
18822	GPR64Opnd, GPR64Opnd, brtarget,	---	18822	GPR64Opnd, GPR64Opnd, brtarget,	---
18823	/* BLTC_MMR6 */	---	18823	/* BLTC_MMR6 */	---
18824	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18824	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18825	/* BLTUC */	---	18825	/* BLTUC */	---
18826	GPR32Opnd, GPR32Opnd, brtarget,	---	18826	GPR32Opnd, GPR32Opnd, brtarget,	---
18827	/* BLTUC64 */	---	18827	/* BLTUC64 */	---
18828	GPR64Opnd, GPR64Opnd, brtarget,	---	18828	GPR64Opnd, GPR64Opnd, brtarget,	---
18829	/* BLTUC_MMR6 */	---	18829	/* BLTUC_MMR6 */	---
18830	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18830	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18831	/* BLTZ */	---	18831	/* BLTZ */	---
18832	GPR32Opnd, brtarget,	---	18832	GPR32Opnd, brtarget,	---
18833	/* BLTZ64 */	---	18833	/* BLTZ64 */	---
18834	GPR64Opnd, brtarget,	---	18834	GPR64Opnd, brtarget,	---
18835	/* BLTZAL */	---	18835	/* BLTZAL */	---
18836	GPR32Opnd, brtarget,	---	18836	GPR32Opnd, brtarget,	---
18837	/* BLTZALC */	---	18837	/* BLTZALC */	---
18838	GPR32Opnd, brtarget,	---	18838	GPR32Opnd, brtarget,	---
18839	/* BLTZALC_MMR6 */	---	18839	/* BLTZALC_MMR6 */	---
18840	GPR32Opnd, brtarget_mm,	---	18840	GPR32Opnd, brtarget_mm,	---
18841	/* BLTZALL */	---	18841	/* BLTZALL */	---
18842	GPR32Opnd, brtarget,	---	18842	GPR32Opnd, brtarget,	---
18843	/* BLTZALS_MM */	---	18843	/* BLTZALS_MM */	---
18844	GPR32Opnd, brtarget_mm,	---	18844	GPR32Opnd, brtarget_mm,	---
18845	/* BLTZAL_MM */	---	18845	/* BLTZAL_MM */	---
18846	GPR32Opnd, brtarget_mm,	---	18846	GPR32Opnd, brtarget_mm,	---
18847	/* BLTZC */	---	18847	/* BLTZC */	---
18848	GPR32Opnd, brtarget,	---	18848	GPR32Opnd, brtarget,	---
18849	/* BLTZC64 */	---	18849	/* BLTZC64 */	---
18850	GPR64Opnd, brtarget,	---	18850	GPR64Opnd, brtarget,	---
18851	/* BLTZC_MMR6 */	---	18851	/* BLTZC_MMR6 */	---
18852	GPR32Opnd, brtarget_lsl2_mm,	---	18852	GPR32Opnd, brtarget_lsl2_mm,	---
18853	/* BLTZL */	---	18853	/* BLTZL */	---
18854	GPR32Opnd, brtarget,	---	18854	GPR32Opnd, brtarget,	---
18855	/* BLTZ_MM */	---	18855	/* BLTZ_MM */	---
18856	GPR32Opnd, brtarget_mm,	---	18856	GPR32Opnd, brtarget_mm,	---
18857	/* BMNZI_B */	---	18857	/* BMNZI_B */	---
18858	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	18858	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
18859	/* BMNZ_V */	---	18859	/* BMNZ_V */	---
18860	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18860	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18861	/* BMZI_B */	---	18861	/* BMZI_B */	---
18862	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	18862	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
18863	/* BMZ_V */	---	18863	/* BMZ_V */	---
18864	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18864	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18865	/* BNE */	---	18865	/* BNE */	---
18866	GPR32Opnd, GPR32Opnd, brtarget,	---	18866	GPR32Opnd, GPR32Opnd, brtarget,	---
18867	/* BNE64 */	---	18867	/* BNE64 */	---
18868	GPR64Opnd, GPR64Opnd, brtarget,	---	18868	GPR64Opnd, GPR64Opnd, brtarget,	---
18869	/* BNEC */	---	18869	/* BNEC */	---
18870	GPR32Opnd, GPR32Opnd, brtarget,	---	18870	GPR32Opnd, GPR32Opnd, brtarget,	---
18871	/* BNEC64 */	---	18871	/* BNEC64 */	---
18872	GPR64Opnd, GPR64Opnd, brtarget,	---	18872	GPR64Opnd, GPR64Opnd, brtarget,	---
18873	/* BNEC_MMR6 */	---	18873	/* BNEC_MMR6 */	---
18874	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---	18874	GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,	---
18875	/* BNEGI_B */	---	18875	/* BNEGI_B */	---
18876	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	18876	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
18877	/* BNEGI_D */	---	18877	/* BNEGI_D */	---
18878	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	18878	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
18879	/* BNEGI_H */	---	18879	/* BNEGI_H */	---
18880	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	18880	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
18881	/* BNEGI_W */	---	18881	/* BNEGI_W */	---
18882	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18882	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18883	/* BNEG_B */	---	18883	/* BNEG_B */	---
18884	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18884	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18885	/* BNEG_D */	---	18885	/* BNEG_D */	---
18886	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18886	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18887	/* BNEG_H */	---	18887	/* BNEG_H */	---
18888	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18888	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18889	/* BNEG_W */	---	18889	/* BNEG_W */	---
18890	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18890	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18891	/* BNEL */	---	18891	/* BNEL */	---
18892	GPR32Opnd, GPR32Opnd, brtarget,	---	18892	GPR32Opnd, GPR32Opnd, brtarget,	---
18893	/* BNEZ16_MM */	---	18893	/* BNEZ16_MM */	---
18894	GPRMM16Opnd, brtarget7_mm,	---	18894	GPRMM16Opnd, brtarget7_mm,	---
18895	/* BNEZALC */	---	18895	/* BNEZALC */	---
18896	GPR32Opnd, brtarget,	---	18896	GPR32Opnd, brtarget,	---
18897	/* BNEZALC_MMR6 */	---	18897	/* BNEZALC_MMR6 */	---
18898	GPR32Opnd, brtarget_mm,	---	18898	GPR32Opnd, brtarget_mm,	---
18899	/* BNEZC */	---	18899	/* BNEZC */	---
18900	GPR32Opnd, brtarget21,	---	18900	GPR32Opnd, brtarget21,	---
18901	/* BNEZC16_MMR6 */	---	18901	/* BNEZC16_MMR6 */	---
18902	GPRMM16Opnd, brtarget7_mm,	---	18902	GPRMM16Opnd, brtarget7_mm,	---
18903	/* BNEZC64 */	---	18903	/* BNEZC64 */	---
18904	GPR64Opnd, brtarget21,	---	18904	GPR64Opnd, brtarget21,	---
18905	/* BNEZC_MM */	---	18905	/* BNEZC_MM */	---
18906	GPR32Opnd, brtarget_mm,	---	18906	GPR32Opnd, brtarget_mm,	---
18907	/* BNEZC_MMR6 */	---	18907	/* BNEZC_MMR6 */	---
18908	GPR32Opnd, brtarget21_mm,	---	18908	GPR32Opnd, brtarget21_mm,	---
18909	/* BNE_MM */	---	18909	/* BNE_MM */	---
18910	GPR32Opnd, GPR32Opnd, brtarget_mm,	---	18910	GPR32Opnd, GPR32Opnd, brtarget_mm,	---
18911	/* BNVC */	---	18911	/* BNVC */	---
18912	GPR32Opnd, GPR32Opnd, brtarget,	---	18912	GPR32Opnd, GPR32Opnd, brtarget,	---
18913	/* BNVC_MMR6 */	---	18913	/* BNVC_MMR6 */	---
18914	GPR32Opnd, GPR32Opnd, brtargetr6,	---	18914	GPR32Opnd, GPR32Opnd, brtargetr6,	---
18915	/* BNZ_B */	---	18915	/* BNZ_B */	---
18916	MSA128BOpnd, brtarget,	---	18916	MSA128BOpnd, brtarget,	---
18917	/* BNZ_D */	---	18917	/* BNZ_D */	---
18918	MSA128DOpnd, brtarget,	---	18918	MSA128DOpnd, brtarget,	---
18919	/* BNZ_H */	---	18919	/* BNZ_H */	---
18920	MSA128HOpnd, brtarget,	---	18920	MSA128HOpnd, brtarget,	---
18921	/* BNZ_V */	---	18921	/* BNZ_V */	---
18922	MSA128BOpnd, brtarget,	---	18922	MSA128BOpnd, brtarget,	---
18923	/* BNZ_W */	---	18923	/* BNZ_W */	---
18924	MSA128WOpnd, brtarget,	---	18924	MSA128WOpnd, brtarget,	---
18925	/* BOVC */	---	18925	/* BOVC */	---
18926	GPR32Opnd, GPR32Opnd, brtarget,	---	18926	GPR32Opnd, GPR32Opnd, brtarget,	---
18927	/* BOVC_MMR6 */	---	18927	/* BOVC_MMR6 */	---
18928	GPR32Opnd, GPR32Opnd, brtargetr6,	---	18928	GPR32Opnd, GPR32Opnd, brtargetr6,	---
18929	/* BPOSGE32 */	---	18929	/* BPOSGE32 */	---
18930	brtarget,	---	18930	brtarget,	---
18931	/* BPOSGE32C_MMR3 */	---	18931	/* BPOSGE32C_MMR3 */	---
18932	brtarget1SImm16,	---	18932	brtarget1SImm16,	---
18933	/* BPOSGE32_MM */	---	18933	/* BPOSGE32_MM */	---
18934	brtarget_mm,	---	18934	brtarget_mm,	---
18935	/* BREAK */	---	18935	/* BREAK */	---
18936	uimm10, uimm10,	---	18936	uimm10, uimm10,	---
18937	/* BREAK16_MM */	---	18937	/* BREAK16_MM */	---
18938	uimm4,	---	18938	uimm4,	---
18939	/* BREAK16_MMR6 */	---	18939	/* BREAK16_MMR6 */	---
18940	uimm4,	---	18940	uimm4,	---
18941	/* BREAK_MM */	---	18941	/* BREAK_MM */	---
18942	uimm10, uimm10,	---	18942	uimm10, uimm10,	---
18943	/* BREAK_MMR6 */	---	18943	/* BREAK_MMR6 */	---
18944	uimm10, uimm10,	---	18944	uimm10, uimm10,	---
18945	/* BSELI_B */	---	18945	/* BSELI_B */	---
18946	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	18946	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
18947	/* BSEL_V */	---	18947	/* BSEL_V */	---
18948	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18948	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18949	/* BSETI_B */	---	18949	/* BSETI_B */	---
18950	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	18950	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
18951	/* BSETI_D */	---	18951	/* BSETI_D */	---
18952	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	18952	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
18953	/* BSETI_H */	---	18953	/* BSETI_H */	---
18954	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	18954	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
18955	/* BSETI_W */	---	18955	/* BSETI_W */	---
18956	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	18956	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
18957	/* BSET_B */	---	18957	/* BSET_B */	---
18958	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	18958	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
18959	/* BSET_D */	---	18959	/* BSET_D */	---
18960	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	18960	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
18961	/* BSET_H */	---	18961	/* BSET_H */	---
18962	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	18962	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
18963	/* BSET_W */	---	18963	/* BSET_W */	---
18964	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	18964	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
18965	/* BZ_B */	---	18965	/* BZ_B */	---
18966	MSA128BOpnd, brtarget,	---	18966	MSA128BOpnd, brtarget,	---
18967	/* BZ_D */	---	18967	/* BZ_D */	---
18968	MSA128DOpnd, brtarget,	---	18968	MSA128DOpnd, brtarget,	---
18969	/* BZ_H */	---	18969	/* BZ_H */	---
18970	MSA128HOpnd, brtarget,	---	18970	MSA128HOpnd, brtarget,	---
18971	/* BZ_V */	---	18971	/* BZ_V */	---
18972	MSA128BOpnd, brtarget,	---	18972	MSA128BOpnd, brtarget,	---
18973	/* BZ_W */	---	18973	/* BZ_W */	---
18974	MSA128WOpnd, brtarget,	---	18974	MSA128WOpnd, brtarget,	---
18975	/* BeqzRxImm16 */	---	18975	/* BeqzRxImm16 */	---
18976	CPU16Regs, brtarget,	---	18976	CPU16Regs, brtarget,	---
18977	/* BeqzRxImmX16 */	---	18977	/* BeqzRxImmX16 */	---
18978	CPU16Regs, brtarget,	---	18978	CPU16Regs, brtarget,	---
18979	/* Bimm16 */	---	18979	/* Bimm16 */	---
18980	brtarget,	---	18980	brtarget,	---
18981	/* BimmX16 */	---	18981	/* BimmX16 */	---
18982	brtarget,	---	18982	brtarget,	---
18983	/* BnezRxImm16 */	---	18983	/* BnezRxImm16 */	---
18984	CPU16Regs, brtarget,	---	18984	CPU16Regs, brtarget,	---
18985	/* BnezRxImmX16 */	---	18985	/* BnezRxImmX16 */	---
18986	CPU16Regs, brtarget,	---	18986	CPU16Regs, brtarget,	---
18987	/* Break16 */	---	18987	/* Break16 */	---
18988	/* Bteqz16 */	---	18988	/* Bteqz16 */	---
18989	simm16,	---	18989	simm16,	---
18990	/* BteqzX16 */	---	18990	/* BteqzX16 */	---
18991	simm16,	---	18991	simm16,	---
18992	/* Btnez16 */	---	18992	/* Btnez16 */	---
18993	simm16,	---	18993	simm16,	---
18994	/* BtnezX16 */	---	18994	/* BtnezX16 */	---
18995	simm16,	---	18995	simm16,	---
18996	/* CACHE */	---	18996	/* CACHE */	---
18997	-1, simm16, uimm5,	---	18997	-1, simm16, uimm5,	---
18998	/* CACHEE */	---	18998	/* CACHEE */	---
18999	-1, simm9, uimm5,	---	18999	-1, simm9, uimm5,	---
19000	/* CACHEE_MM */	---	19000	/* CACHEE_MM */	---
19001	-1, simm9, uimm5,	---	19001	-1, simm9, uimm5,	---
19002	/* CACHE_MM */	---	19002	/* CACHE_MM */	---
19003	-1, simm12, uimm5,	---	19003	-1, simm12, uimm5,	---
19004	/* CACHE_MMR6 */	---	19004	/* CACHE_MMR6 */	---
19005	-1, simm12, uimm5,	---	19005	-1, simm12, uimm5,	---
19006	/* CACHE_R6 */	---	19006	/* CACHE_R6 */	---
19007	-1, simm9, uimm5,	---	19007	-1, simm9, uimm5,	---
19008	/* CEIL_L_D64 */	---	19008	/* CEIL_L_D64 */	---
19009	FGR64Opnd, FGR64Opnd,	---	19009	FGR64Opnd, FGR64Opnd,	---
19010	/* CEIL_L_D_MMR6 */	---	19010	/* CEIL_L_D_MMR6 */	---
19011	FGR64Opnd, FGR64Opnd,	---	19011	FGR64Opnd, FGR64Opnd,	---
19012	/* CEIL_L_S */	---	19012	/* CEIL_L_S */	---
19013	FGR64Opnd, FGR32Opnd,	---	19013	FGR64Opnd, FGR32Opnd,	---
19014	/* CEIL_L_S_MMR6 */	---	19014	/* CEIL_L_S_MMR6 */	---
19015	FGR64Opnd, FGR32Opnd,	---	19015	FGR64Opnd, FGR32Opnd,	---
19016	/* CEIL_W_D32 */	---	19016	/* CEIL_W_D32 */	---
19017	FGR32Opnd, AFGR64Opnd,	---	19017	FGR32Opnd, AFGR64Opnd,	---
19018	/* CEIL_W_D64 */	---	19018	/* CEIL_W_D64 */	---
19019	FGR32Opnd, FGR64Opnd,	---	19019	FGR32Opnd, FGR64Opnd,	---
19020	/* CEIL_W_D_MMR6 */	---	19020	/* CEIL_W_D_MMR6 */	---
19021	FGR32Opnd, AFGR64Opnd,	---	19021	FGR32Opnd, AFGR64Opnd,	---
19022	/* CEIL_W_MM */	---	19022	/* CEIL_W_MM */	---
19023	FGR32Opnd, AFGR64Opnd,	---	19023	FGR32Opnd, AFGR64Opnd,	---
19024	/* CEIL_W_S */	---	19024	/* CEIL_W_S */	---
19025	FGR32Opnd, FGR32Opnd,	---	19025	FGR32Opnd, FGR32Opnd,	---
19026	/* CEIL_W_S_MM */	---	19026	/* CEIL_W_S_MM */	---
19027	FGR32Opnd, FGR32Opnd,	---	19027	FGR32Opnd, FGR32Opnd,	---
19028	/* CEIL_W_S_MMR6 */	---	19028	/* CEIL_W_S_MMR6 */	---
19029	FGR32Opnd, FGR32Opnd,	---	19029	FGR32Opnd, FGR32Opnd,	---
19030	/* CEQI_B */	---	19030	/* CEQI_B */	---
19031	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---	19031	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---
19032	/* CEQI_D */	---	19032	/* CEQI_D */	---
19033	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---	19033	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---
19034	/* CEQI_H */	---	19034	/* CEQI_H */	---
19035	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---	19035	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---
19036	/* CEQI_W */	---	19036	/* CEQI_W */	---
19037	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---	19037	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---
19038	/* CEQ_B */	---	19038	/* CEQ_B */	---
19039	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19039	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19040	/* CEQ_D */	---	19040	/* CEQ_D */	---
19041	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19041	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19042	/* CEQ_H */	---	19042	/* CEQ_H */	---
19043	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19043	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19044	/* CEQ_W */	---	19044	/* CEQ_W */	---
19045	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19045	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19046	/* CFC1 */	---	19046	/* CFC1 */	---
19047	GPR32Opnd, CCROpnd,	---	19047	GPR32Opnd, CCROpnd,	---
19048	/* CFC1_MM */	---	19048	/* CFC1_MM */	---
19049	GPR32Opnd, CCROpnd,	---	19049	GPR32Opnd, CCROpnd,	---
19050	/* CFC2_MM */	---	19050	/* CFC2_MM */	---
19051	GPR32Opnd, COP2Opnd,	---	19051	GPR32Opnd, COP2Opnd,	---
19052	/* CFCMSA */	---	19052	/* CFCMSA */	---
19053	GPR32Opnd, MSA128CROpnd,	---	19053	GPR32Opnd, MSA128CROpnd,	---
19054	/* CINS */	---	19054	/* CINS */	---
19055	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---	19055	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---
19056	/* CINS32 */	---	19056	/* CINS32 */	---
19057	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---	19057	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---
19058	/* CINS64_32 */	---	19058	/* CINS64_32 */	---
19059	GPR64Opnd, GPR32Opnd, uimm5, uimm5,	---	19059	GPR64Opnd, GPR32Opnd, uimm5, uimm5,	---
19060	/* CINS_i32 */	---	19060	/* CINS_i32 */	---
19061	GPR32Opnd, GPR32Opnd, uimm5, uimm5,	---	19061	GPR32Opnd, GPR32Opnd, uimm5, uimm5,	---
19062	/* CLASS_D */	---	19062	/* CLASS_D */	---
19063	FGR64Opnd, FGR64Opnd,	---	19063	FGR64Opnd, FGR64Opnd,	---
19064	/* CLASS_D_MMR6 */	---	19064	/* CLASS_D_MMR6 */	---
19065	FGR64Opnd, FGR64Opnd,	---	19065	FGR64Opnd, FGR64Opnd,	---
19066	/* CLASS_S */	---	19066	/* CLASS_S */	---
19067	FGR32Opnd, FGR32Opnd,	---	19067	FGR32Opnd, FGR32Opnd,	---
19068	/* CLASS_S_MMR6 */	---	19068	/* CLASS_S_MMR6 */	---
19069	FGR32Opnd, FGR32Opnd,	---	19069	FGR32Opnd, FGR32Opnd,	---
19070	/* CLEI_S_B */	---	19070	/* CLEI_S_B */	---
19071	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---	19071	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---
19072	/* CLEI_S_D */	---	19072	/* CLEI_S_D */	---
19073	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---	19073	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---
19074	/* CLEI_S_H */	---	19074	/* CLEI_S_H */	---
19075	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---	19075	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---
19076	/* CLEI_S_W */	---	19076	/* CLEI_S_W */	---
19077	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---	19077	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---
19078	/* CLEI_U_B */	---	19078	/* CLEI_U_B */	---
19079	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	19079	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
19080	/* CLEI_U_D */	---	19080	/* CLEI_U_D */	---
19081	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	19081	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
19082	/* CLEI_U_H */	---	19082	/* CLEI_U_H */	---
19083	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	19083	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
19084	/* CLEI_U_W */	---	19084	/* CLEI_U_W */	---
19085	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	19085	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
19086	/* CLE_S_B */	---	19086	/* CLE_S_B */	---
19087	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19087	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19088	/* CLE_S_D */	---	19088	/* CLE_S_D */	---
19089	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19089	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19090	/* CLE_S_H */	---	19090	/* CLE_S_H */	---
19091	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19091	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19092	/* CLE_S_W */	---	19092	/* CLE_S_W */	---
19093	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19093	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19094	/* CLE_U_B */	---	19094	/* CLE_U_B */	---
19095	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19095	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19096	/* CLE_U_D */	---	19096	/* CLE_U_D */	---
19097	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19097	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19098	/* CLE_U_H */	---	19098	/* CLE_U_H */	---
19099	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19099	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19100	/* CLE_U_W */	---	19100	/* CLE_U_W */	---
19101	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19101	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19102	/* CLO */	---	19102	/* CLO */	---
19103	GPR32Opnd, GPR32Opnd,	---	19103	GPR32Opnd, GPR32Opnd,	---
19104	/* CLO_MM */	---	19104	/* CLO_MM */	---
19105	GPR32Opnd, GPR32Opnd,	---	19105	GPR32Opnd, GPR32Opnd,	---
19106	/* CLO_MMR6 */	---	19106	/* CLO_MMR6 */	---
19107	GPR32Opnd, GPR32Opnd,	---	19107	GPR32Opnd, GPR32Opnd,	---
19108	/* CLO_R6 */	---	19108	/* CLO_R6 */	---
19109	GPR32Opnd, GPR32Opnd,	---	19109	GPR32Opnd, GPR32Opnd,	---
19110	/* CLTI_S_B */	---	19110	/* CLTI_S_B */	---
19111	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---	19111	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---
19112	/* CLTI_S_D */	---	19112	/* CLTI_S_D */	---
19113	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---	19113	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---
19114	/* CLTI_S_H */	---	19114	/* CLTI_S_H */	---
19115	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---	19115	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---
19116	/* CLTI_S_W */	---	19116	/* CLTI_S_W */	---
19117	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---	19117	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---
19118	/* CLTI_U_B */	---	19118	/* CLTI_U_B */	---
19119	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	19119	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
19120	/* CLTI_U_D */	---	19120	/* CLTI_U_D */	---
19121	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	19121	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
19122	/* CLTI_U_H */	---	19122	/* CLTI_U_H */	---
19123	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	19123	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
19124	/* CLTI_U_W */	---	19124	/* CLTI_U_W */	---
19125	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	19125	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
19126	/* CLT_S_B */	---	19126	/* CLT_S_B */	---
19127	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19127	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19128	/* CLT_S_D */	---	19128	/* CLT_S_D */	---
19129	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19129	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19130	/* CLT_S_H */	---	19130	/* CLT_S_H */	---
19131	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19131	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19132	/* CLT_S_W */	---	19132	/* CLT_S_W */	---
19133	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19133	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19134	/* CLT_U_B */	---	19134	/* CLT_U_B */	---
19135	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19135	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19136	/* CLT_U_D */	---	19136	/* CLT_U_D */	---
19137	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19137	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19138	/* CLT_U_H */	---	19138	/* CLT_U_H */	---
19139	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19139	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19140	/* CLT_U_W */	---	19140	/* CLT_U_W */	---
19141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19142	/* CLZ */	---	19142	/* CLZ */	---
19143	GPR32Opnd, GPR32Opnd,	---	19143	GPR32Opnd, GPR32Opnd,	---
19144	/* CLZ_MM */	---	19144	/* CLZ_MM */	---
19145	GPR32Opnd, GPR32Opnd,	---	19145	GPR32Opnd, GPR32Opnd,	---
19146	/* CLZ_MMR6 */	---	19146	/* CLZ_MMR6 */	---
19147	GPR32Opnd, GPR32Opnd,	---	19147	GPR32Opnd, GPR32Opnd,	---
19148	/* CLZ_R6 */	---	19148	/* CLZ_R6 */	---
19149	GPR32Opnd, GPR32Opnd,	---	19149	GPR32Opnd, GPR32Opnd,	---
19150	/* CMPGDU_EQ_QB */	---	19150	/* CMPGDU_EQ_QB */	---
19151	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19151	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19152	/* CMPGDU_EQ_QB_MMR2 */	---	19152	/* CMPGDU_EQ_QB_MMR2 */	---
19153	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19153	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19154	/* CMPGDU_LE_QB */	---	19154	/* CMPGDU_LE_QB */	---
19155	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19155	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19156	/* CMPGDU_LE_QB_MMR2 */	---	19156	/* CMPGDU_LE_QB_MMR2 */	---
19157	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19157	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19158	/* CMPGDU_LT_QB */	---	19158	/* CMPGDU_LT_QB */	---
19159	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19159	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19160	/* CMPGDU_LT_QB_MMR2 */	---	19160	/* CMPGDU_LT_QB_MMR2 */	---
19161	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19161	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19162	/* CMPGU_EQ_QB */	---	19162	/* CMPGU_EQ_QB */	---
19163	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19163	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19164	/* CMPGU_EQ_QB_MM */	---	19164	/* CMPGU_EQ_QB_MM */	---
19165	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19165	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19166	/* CMPGU_LE_QB */	---	19166	/* CMPGU_LE_QB */	---
19167	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19167	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19168	/* CMPGU_LE_QB_MM */	---	19168	/* CMPGU_LE_QB_MM */	---
19169	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19169	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19170	/* CMPGU_LT_QB */	---	19170	/* CMPGU_LT_QB */	---
19171	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19171	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19172	/* CMPGU_LT_QB_MM */	---	19172	/* CMPGU_LT_QB_MM */	---
19173	GPR32Opnd, DSPROpnd, DSPROpnd,	---	19173	GPR32Opnd, DSPROpnd, DSPROpnd,	---
19174	/* CMPU_EQ_QB */	---	19174	/* CMPU_EQ_QB */	---
19175	DSPROpnd, DSPROpnd,	---	19175	DSPROpnd, DSPROpnd,	---
19176	/* CMPU_EQ_QB_MM */	---	19176	/* CMPU_EQ_QB_MM */	---
19177	DSPROpnd, DSPROpnd,	---	19177	DSPROpnd, DSPROpnd,	---
19178	/* CMPU_LE_QB */	---	19178	/* CMPU_LE_QB */	---
19179	DSPROpnd, DSPROpnd,	---	19179	DSPROpnd, DSPROpnd,	---
19180	/* CMPU_LE_QB_MM */	---	19180	/* CMPU_LE_QB_MM */	---
19181	DSPROpnd, DSPROpnd,	---	19181	DSPROpnd, DSPROpnd,	---
19182	/* CMPU_LT_QB */	---	19182	/* CMPU_LT_QB */	---
19183	DSPROpnd, DSPROpnd,	---	19183	DSPROpnd, DSPROpnd,	---
19184	/* CMPU_LT_QB_MM */	---	19184	/* CMPU_LT_QB_MM */	---
19185	DSPROpnd, DSPROpnd,	---	19185	DSPROpnd, DSPROpnd,	---
19186	/* CMP_AF_D_MMR6 */	---	19186	/* CMP_AF_D_MMR6 */	---
19187	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19187	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19188	/* CMP_AF_S_MMR6 */	---	19188	/* CMP_AF_S_MMR6 */	---
19189	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19189	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19190	/* CMP_EQ_D */	---	19190	/* CMP_EQ_D */	---
19191	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19191	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19192	/* CMP_EQ_D_MMR6 */	---	19192	/* CMP_EQ_D_MMR6 */	---
19193	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19193	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19194	/* CMP_EQ_PH */	---	19194	/* CMP_EQ_PH */	---
19195	DSPROpnd, DSPROpnd,	---	19195	DSPROpnd, DSPROpnd,	---
19196	/* CMP_EQ_PH_MM */	---	19196	/* CMP_EQ_PH_MM */	---
19197	DSPROpnd, DSPROpnd,	---	19197	DSPROpnd, DSPROpnd,	---
19198	/* CMP_EQ_S */	---	19198	/* CMP_EQ_S */	---
19199	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19199	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19200	/* CMP_EQ_S_MMR6 */	---	19200	/* CMP_EQ_S_MMR6 */	---
19201	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19201	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19202	/* CMP_F_D */	---	19202	/* CMP_F_D */	---
19203	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19203	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19204	/* CMP_F_S */	---	19204	/* CMP_F_S */	---
19205	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19205	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19206	/* CMP_LE_D */	---	19206	/* CMP_LE_D */	---
19207	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19207	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19208	/* CMP_LE_D_MMR6 */	---	19208	/* CMP_LE_D_MMR6 */	---
19209	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19209	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19210	/* CMP_LE_PH */	---	19210	/* CMP_LE_PH */	---
19211	DSPROpnd, DSPROpnd,	---	19211	DSPROpnd, DSPROpnd,	---
19212	/* CMP_LE_PH_MM */	---	19212	/* CMP_LE_PH_MM */	---
19213	DSPROpnd, DSPROpnd,	---	19213	DSPROpnd, DSPROpnd,	---
19214	/* CMP_LE_S */	---	19214	/* CMP_LE_S */	---
19215	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19215	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19216	/* CMP_LE_S_MMR6 */	---	19216	/* CMP_LE_S_MMR6 */	---
19217	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19217	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19218	/* CMP_LT_D */	---	19218	/* CMP_LT_D */	---
19219	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19219	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19220	/* CMP_LT_D_MMR6 */	---	19220	/* CMP_LT_D_MMR6 */	---
19221	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19221	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19222	/* CMP_LT_PH */	---	19222	/* CMP_LT_PH */	---
19223	DSPROpnd, DSPROpnd,	---	19223	DSPROpnd, DSPROpnd,	---
19224	/* CMP_LT_PH_MM */	---	19224	/* CMP_LT_PH_MM */	---
19225	DSPROpnd, DSPROpnd,	---	19225	DSPROpnd, DSPROpnd,	---
19226	/* CMP_LT_S */	---	19226	/* CMP_LT_S */	---
19227	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19227	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19228	/* CMP_LT_S_MMR6 */	---	19228	/* CMP_LT_S_MMR6 */	---
19229	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19229	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19230	/* CMP_SAF_D */	---	19230	/* CMP_SAF_D */	---
19231	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19231	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19232	/* CMP_SAF_D_MMR6 */	---	19232	/* CMP_SAF_D_MMR6 */	---
19233	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19233	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19234	/* CMP_SAF_S */	---	19234	/* CMP_SAF_S */	---
19235	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19235	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19236	/* CMP_SAF_S_MMR6 */	---	19236	/* CMP_SAF_S_MMR6 */	---
19237	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19237	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19238	/* CMP_SEQ_D */	---	19238	/* CMP_SEQ_D */	---
19239	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19239	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19240	/* CMP_SEQ_D_MMR6 */	---	19240	/* CMP_SEQ_D_MMR6 */	---
19241	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19241	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19242	/* CMP_SEQ_S */	---	19242	/* CMP_SEQ_S */	---
19243	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19243	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19244	/* CMP_SEQ_S_MMR6 */	---	19244	/* CMP_SEQ_S_MMR6 */	---
19245	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19245	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19246	/* CMP_SLE_D */	---	19246	/* CMP_SLE_D */	---
19247	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19247	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19248	/* CMP_SLE_D_MMR6 */	---	19248	/* CMP_SLE_D_MMR6 */	---
19249	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19249	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19250	/* CMP_SLE_S */	---	19250	/* CMP_SLE_S */	---
19251	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19251	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19252	/* CMP_SLE_S_MMR6 */	---	19252	/* CMP_SLE_S_MMR6 */	---
19253	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19253	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19254	/* CMP_SLT_D */	---	19254	/* CMP_SLT_D */	---
19255	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19255	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19256	/* CMP_SLT_D_MMR6 */	---	19256	/* CMP_SLT_D_MMR6 */	---
19257	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19257	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19258	/* CMP_SLT_S */	---	19258	/* CMP_SLT_S */	---
19259	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19259	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19260	/* CMP_SLT_S_MMR6 */	---	19260	/* CMP_SLT_S_MMR6 */	---
19261	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19261	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19262	/* CMP_SUEQ_D */	---	19262	/* CMP_SUEQ_D */	---
19263	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19263	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19264	/* CMP_SUEQ_D_MMR6 */	---	19264	/* CMP_SUEQ_D_MMR6 */	---
19265	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19265	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19266	/* CMP_SUEQ_S */	---	19266	/* CMP_SUEQ_S */	---
19267	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19267	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19268	/* CMP_SUEQ_S_MMR6 */	---	19268	/* CMP_SUEQ_S_MMR6 */	---
19269	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19269	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19270	/* CMP_SULE_D */	---	19270	/* CMP_SULE_D */	---
19271	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19271	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19272	/* CMP_SULE_D_MMR6 */	---	19272	/* CMP_SULE_D_MMR6 */	---
19273	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19273	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19274	/* CMP_SULE_S */	---	19274	/* CMP_SULE_S */	---
19275	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19275	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19276	/* CMP_SULE_S_MMR6 */	---	19276	/* CMP_SULE_S_MMR6 */	---
19277	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19277	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19278	/* CMP_SULT_D */	---	19278	/* CMP_SULT_D */	---
19279	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19279	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19280	/* CMP_SULT_D_MMR6 */	---	19280	/* CMP_SULT_D_MMR6 */	---
19281	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19281	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19282	/* CMP_SULT_S */	---	19282	/* CMP_SULT_S */	---
19283	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19283	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19284	/* CMP_SULT_S_MMR6 */	---	19284	/* CMP_SULT_S_MMR6 */	---
19285	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19285	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19286	/* CMP_SUN_D */	---	19286	/* CMP_SUN_D */	---
19287	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19287	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19288	/* CMP_SUN_D_MMR6 */	---	19288	/* CMP_SUN_D_MMR6 */	---
19289	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19289	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19290	/* CMP_SUN_S */	---	19290	/* CMP_SUN_S */	---
19291	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19291	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19292	/* CMP_SUN_S_MMR6 */	---	19292	/* CMP_SUN_S_MMR6 */	---
19293	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19293	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19294	/* CMP_UEQ_D */	---	19294	/* CMP_UEQ_D */	---
19295	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19295	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19296	/* CMP_UEQ_D_MMR6 */	---	19296	/* CMP_UEQ_D_MMR6 */	---
19297	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19297	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19298	/* CMP_UEQ_S */	---	19298	/* CMP_UEQ_S */	---
19299	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19299	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19300	/* CMP_UEQ_S_MMR6 */	---	19300	/* CMP_UEQ_S_MMR6 */	---
19301	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19301	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19302	/* CMP_ULE_D */	---	19302	/* CMP_ULE_D */	---
19303	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19303	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19304	/* CMP_ULE_D_MMR6 */	---	19304	/* CMP_ULE_D_MMR6 */	---
19305	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19305	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19306	/* CMP_ULE_S */	---	19306	/* CMP_ULE_S */	---
19307	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19307	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19308	/* CMP_ULE_S_MMR6 */	---	19308	/* CMP_ULE_S_MMR6 */	---
19309	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19309	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19310	/* CMP_ULT_D */	---	19310	/* CMP_ULT_D */	---
19311	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19311	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19312	/* CMP_ULT_D_MMR6 */	---	19312	/* CMP_ULT_D_MMR6 */	---
19313	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19313	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19314	/* CMP_ULT_S */	---	19314	/* CMP_ULT_S */	---
19315	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19315	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19316	/* CMP_ULT_S_MMR6 */	---	19316	/* CMP_ULT_S_MMR6 */	---
19317	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19317	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19318	/* CMP_UN_D */	---	19318	/* CMP_UN_D */	---
19319	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19319	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19320	/* CMP_UN_D_MMR6 */	---	19320	/* CMP_UN_D_MMR6 */	---
19321	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---	19321	FGRCCOpnd, FGR64Opnd, FGR64Opnd,	---
19322	/* CMP_UN_S */	---	19322	/* CMP_UN_S */	---
19323	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19323	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19324	/* CMP_UN_S_MMR6 */	---	19324	/* CMP_UN_S_MMR6 */	---
19325	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	19325	FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
19326	/* COPY_S_B */	---	19326	/* COPY_S_B */	---
19327	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	---	19327	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	---
19328	/* COPY_S_D */	---	19328	/* COPY_S_D */	---
19329	GPR64Opnd, MSA128DOpnd, uimm1_ptr,	---	19329	GPR64Opnd, MSA128DOpnd, uimm1_ptr,	---
19330	/* COPY_S_H */	---	19330	/* COPY_S_H */	---
19331	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	---	19331	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	---
19332	/* COPY_S_W */	---	19332	/* COPY_S_W */	---
19333	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	---	19333	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	---
19334	/* COPY_U_B */	---	19334	/* COPY_U_B */	---
19335	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	---	19335	GPR32Opnd, MSA128BOpnd, uimm4_ptr,	---
19336	/* COPY_U_H */	---	19336	/* COPY_U_H */	---
19337	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	---	19337	GPR32Opnd, MSA128HOpnd, uimm3_ptr,	---
19338	/* COPY_U_W */	---	19338	/* COPY_U_W */	---
19339	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	---	19339	GPR32Opnd, MSA128WOpnd, uimm2_ptr,	---
19340	/* CRC32B */	---	19340	/* CRC32B */	---
19341	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19341	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19342	/* CRC32CB */	---	19342	/* CRC32CB */	---
19343	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19343	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19344	/* CRC32CD */	---	19344	/* CRC32CD */	---
19345	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19345	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19346	/* CRC32CH */	---	19346	/* CRC32CH */	---
19347	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19347	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19348	/* CRC32CW */	---	19348	/* CRC32CW */	---
19349	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19349	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19350	/* CRC32D */	---	19350	/* CRC32D */	---
19351	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19351	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19352	/* CRC32H */	---	19352	/* CRC32H */	---
19353	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19353	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19354	/* CRC32W */	---	19354	/* CRC32W */	---
19355	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19355	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19356	/* CTC1 */	---	19356	/* CTC1 */	---
19357	CCROpnd, GPR32Opnd,	---	19357	CCROpnd, GPR32Opnd,	---
19358	/* CTC1_MM */	---	19358	/* CTC1_MM */	---
19359	CCROpnd, GPR32Opnd,	---	19359	CCROpnd, GPR32Opnd,	---
19360	/* CTC2_MM */	---	19360	/* CTC2_MM */	---
19361	COP2Opnd, GPR32Opnd,	---	19361	COP2Opnd, GPR32Opnd,	---
19362	/* CTCMSA */	---	19362	/* CTCMSA */	---
19363	MSA128CROpnd, GPR32Opnd,	---	19363	MSA128CROpnd, GPR32Opnd,	---
19364	/* CVT_D32_S */	---	19364	/* CVT_D32_S */	---
19365	AFGR64Opnd, FGR32Opnd,	---	19365	AFGR64Opnd, FGR32Opnd,	---
19366	/* CVT_D32_S_MM */	---	19366	/* CVT_D32_S_MM */	---
19367	AFGR64Opnd, FGR32Opnd,	---	19367	AFGR64Opnd, FGR32Opnd,	---
19368	/* CVT_D32_W */	---	19368	/* CVT_D32_W */	---
19369	AFGR64Opnd, FGR32Opnd,	---	19369	AFGR64Opnd, FGR32Opnd,	---
19370	/* CVT_D32_W_MM */	---	19370	/* CVT_D32_W_MM */	---
19371	AFGR64Opnd, FGR32Opnd,	---	19371	AFGR64Opnd, FGR32Opnd,	---
19372	/* CVT_D64_L */	---	19372	/* CVT_D64_L */	---
19373	FGR64Opnd, FGR64Opnd,	---	19373	FGR64Opnd, FGR64Opnd,	---
19374	/* CVT_D64_S */	---	19374	/* CVT_D64_S */	---
19375	FGR64Opnd, FGR32Opnd,	---	19375	FGR64Opnd, FGR32Opnd,	---
19376	/* CVT_D64_S_MM */	---	19376	/* CVT_D64_S_MM */	---
19377	FGR64Opnd, FGR32Opnd,	---	19377	FGR64Opnd, FGR32Opnd,	---
19378	/* CVT_D64_W */	---	19378	/* CVT_D64_W */	---
19379	FGR64Opnd, FGR32Opnd,	---	19379	FGR64Opnd, FGR32Opnd,	---
19380	/* CVT_D64_W_MM */	---	19380	/* CVT_D64_W_MM */	---
19381	FGR64Opnd, FGR32Opnd,	---	19381	FGR64Opnd, FGR32Opnd,	---
19382	/* CVT_D_L_MMR6 */	---	19382	/* CVT_D_L_MMR6 */	---
19383	FGR64Opnd, FGR64Opnd,	---	19383	FGR64Opnd, FGR64Opnd,	---
19384	/* CVT_L_D64 */	---	19384	/* CVT_L_D64 */	---
19385	FGR64Opnd, FGR64Opnd,	---	19385	FGR64Opnd, FGR64Opnd,	---
19386	/* CVT_L_D64_MM */	---	19386	/* CVT_L_D64_MM */	---
19387	FGR64Opnd, FGR64Opnd,	---	19387	FGR64Opnd, FGR64Opnd,	---
19388	/* CVT_L_D_MMR6 */	---	19388	/* CVT_L_D_MMR6 */	---
19389	FGR64Opnd, FGR64Opnd,	---	19389	FGR64Opnd, FGR64Opnd,	---
19390	/* CVT_L_S */	---	19390	/* CVT_L_S */	---
19391	FGR64Opnd, FGR32Opnd,	---	19391	FGR64Opnd, FGR32Opnd,	---
19392	/* CVT_L_S_MM */	---	19392	/* CVT_L_S_MM */	---
19393	FGR64Opnd, FGR32Opnd,	---	19393	FGR64Opnd, FGR32Opnd,	---
19394	/* CVT_L_S_MMR6 */	---	19394	/* CVT_L_S_MMR6 */	---
19395	FGR64Opnd, FGR32Opnd,	---	19395	FGR64Opnd, FGR32Opnd,	---
19396	/* CVT_PS_PW64 */	---	19396	/* CVT_PS_PW64 */	---
19397	FGR64Opnd, FGR64Opnd,	---	19397	FGR64Opnd, FGR64Opnd,	---
19398	/* CVT_PS_S64 */	---	19398	/* CVT_PS_S64 */	---
19399	FGR64Opnd, FGR32Opnd, FGR32Opnd,	---	19399	FGR64Opnd, FGR32Opnd, FGR32Opnd,	---
19400	/* CVT_PW_PS64 */	---	19400	/* CVT_PW_PS64 */	---
19401	FGR64Opnd, FGR64Opnd,	---	19401	FGR64Opnd, FGR64Opnd,	---
19402	/* CVT_S_D32 */	---	19402	/* CVT_S_D32 */	---
19403	FGR32Opnd, AFGR64Opnd,	---	19403	FGR32Opnd, AFGR64Opnd,	---
19404	/* CVT_S_D32_MM */	---	19404	/* CVT_S_D32_MM */	---
19405	FGR32Opnd, AFGR64Opnd,	---	19405	FGR32Opnd, AFGR64Opnd,	---
19406	/* CVT_S_D64 */	---	19406	/* CVT_S_D64 */	---
19407	FGR32Opnd, FGR64Opnd,	---	19407	FGR32Opnd, FGR64Opnd,	---
19408	/* CVT_S_D64_MM */	---	19408	/* CVT_S_D64_MM */	---
19409	FGR32Opnd, FGR64Opnd,	---	19409	FGR32Opnd, FGR64Opnd,	---
19410	/* CVT_S_L */	---	19410	/* CVT_S_L */	---
19411	FGR32Opnd, FGR64Opnd,	---	19411	FGR32Opnd, FGR64Opnd,	---
19412	/* CVT_S_L_MMR6 */	---	19412	/* CVT_S_L_MMR6 */	---
19413	FGR64Opnd, FGR32Opnd,	---	19413	FGR64Opnd, FGR32Opnd,	---
19414	/* CVT_S_PL64 */	---	19414	/* CVT_S_PL64 */	---
19415	FGR32Opnd, FGR64Opnd,	---	19415	FGR32Opnd, FGR64Opnd,	---
19416	/* CVT_S_PU64 */	---	19416	/* CVT_S_PU64 */	---
19417	FGR32Opnd, FGR64Opnd,	---	19417	FGR32Opnd, FGR64Opnd,	---
19418	/* CVT_S_W */	---	19418	/* CVT_S_W */	---
19419	FGR32Opnd, FGR32Opnd,	---	19419	FGR32Opnd, FGR32Opnd,	---
19420	/* CVT_S_W_MM */	---	19420	/* CVT_S_W_MM */	---
19421	FGR32Opnd, FGR32Opnd,	---	19421	FGR32Opnd, FGR32Opnd,	---
19422	/* CVT_S_W_MMR6 */	---	19422	/* CVT_S_W_MMR6 */	---
19423	FGR32Opnd, FGR32Opnd,	---	19423	FGR32Opnd, FGR32Opnd,	---
19424	/* CVT_W_D32 */	---	19424	/* CVT_W_D32 */	---
19425	FGR32Opnd, AFGR64Opnd,	---	19425	FGR32Opnd, AFGR64Opnd,	---
19426	/* CVT_W_D32_MM */	---	19426	/* CVT_W_D32_MM */	---
19427	FGR32Opnd, AFGR64Opnd,	---	19427	FGR32Opnd, AFGR64Opnd,	---
19428	/* CVT_W_D64 */	---	19428	/* CVT_W_D64 */	---
19429	FGR32Opnd, FGR64Opnd,	---	19429	FGR32Opnd, FGR64Opnd,	---
19430	/* CVT_W_D64_MM */	---	19430	/* CVT_W_D64_MM */	---
19431	FGR32Opnd, FGR64Opnd,	---	19431	FGR32Opnd, FGR64Opnd,	---
19432	/* CVT_W_S */	---	19432	/* CVT_W_S */	---
19433	FGR32Opnd, FGR32Opnd,	---	19433	FGR32Opnd, FGR32Opnd,	---
19434	/* CVT_W_S_MM */	---	19434	/* CVT_W_S_MM */	---
19435	FGR32Opnd, FGR32Opnd,	---	19435	FGR32Opnd, FGR32Opnd,	---
19436	/* CVT_W_S_MMR6 */	---	19436	/* CVT_W_S_MMR6 */	---
19437	FGR32Opnd, FGR32Opnd,	---	19437	FGR32Opnd, FGR32Opnd,	---
19438	/* C_EQ_D32 */	---	19438	/* C_EQ_D32 */	---
19439	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19439	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19440	/* C_EQ_D32_MM */	---	19440	/* C_EQ_D32_MM */	---
19441	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19441	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19442	/* C_EQ_D64 */	---	19442	/* C_EQ_D64 */	---
19443	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19443	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19444	/* C_EQ_D64_MM */	---	19444	/* C_EQ_D64_MM */	---
19445	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19445	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19446	/* C_EQ_S */	---	19446	/* C_EQ_S */	---
19447	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19447	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19448	/* C_EQ_S_MM */	---	19448	/* C_EQ_S_MM */	---
19449	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19449	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19450	/* C_F_D32 */	---	19450	/* C_F_D32 */	---
19451	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19451	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19452	/* C_F_D32_MM */	---	19452	/* C_F_D32_MM */	---
19453	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19453	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19454	/* C_F_D64 */	---	19454	/* C_F_D64 */	---
19455	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19455	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19456	/* C_F_D64_MM */	---	19456	/* C_F_D64_MM */	---
19457	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19457	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19458	/* C_F_S */	---	19458	/* C_F_S */	---
19459	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19459	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19460	/* C_F_S_MM */	---	19460	/* C_F_S_MM */	---
19461	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19461	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19462	/* C_LE_D32 */	---	19462	/* C_LE_D32 */	---
19463	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19463	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19464	/* C_LE_D32_MM */	---	19464	/* C_LE_D32_MM */	---
19465	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19465	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19466	/* C_LE_D64 */	---	19466	/* C_LE_D64 */	---
19467	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19467	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19468	/* C_LE_D64_MM */	---	19468	/* C_LE_D64_MM */	---
19469	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19469	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19470	/* C_LE_S */	---	19470	/* C_LE_S */	---
19471	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19471	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19472	/* C_LE_S_MM */	---	19472	/* C_LE_S_MM */	---
19473	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19473	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19474	/* C_LT_D32 */	---	19474	/* C_LT_D32 */	---
19475	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19475	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19476	/* C_LT_D32_MM */	---	19476	/* C_LT_D32_MM */	---
19477	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19477	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19478	/* C_LT_D64 */	---	19478	/* C_LT_D64 */	---
19479	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19479	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19480	/* C_LT_D64_MM */	---	19480	/* C_LT_D64_MM */	---
19481	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19481	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19482	/* C_LT_S */	---	19482	/* C_LT_S */	---
19483	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19483	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19484	/* C_LT_S_MM */	---	19484	/* C_LT_S_MM */	---
19485	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19485	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19486	/* C_NGE_D32 */	---	19486	/* C_NGE_D32 */	---
19487	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19487	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19488	/* C_NGE_D32_MM */	---	19488	/* C_NGE_D32_MM */	---
19489	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19489	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19490	/* C_NGE_D64 */	---	19490	/* C_NGE_D64 */	---
19491	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19491	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19492	/* C_NGE_D64_MM */	---	19492	/* C_NGE_D64_MM */	---
19493	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19493	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19494	/* C_NGE_S */	---	19494	/* C_NGE_S */	---
19495	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19495	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19496	/* C_NGE_S_MM */	---	19496	/* C_NGE_S_MM */	---
19497	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19497	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19498	/* C_NGLE_D32 */	---	19498	/* C_NGLE_D32 */	---
19499	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19499	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19500	/* C_NGLE_D32_MM */	---	19500	/* C_NGLE_D32_MM */	---
19501	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19501	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19502	/* C_NGLE_D64 */	---	19502	/* C_NGLE_D64 */	---
19503	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19503	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19504	/* C_NGLE_D64_MM */	---	19504	/* C_NGLE_D64_MM */	---
19505	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19505	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19506	/* C_NGLE_S */	---	19506	/* C_NGLE_S */	---
19507	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19507	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19508	/* C_NGLE_S_MM */	---	19508	/* C_NGLE_S_MM */	---
19509	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19509	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19510	/* C_NGL_D32 */	---	19510	/* C_NGL_D32 */	---
19511	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19511	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19512	/* C_NGL_D32_MM */	---	19512	/* C_NGL_D32_MM */	---
19513	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19513	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19514	/* C_NGL_D64 */	---	19514	/* C_NGL_D64 */	---
19515	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19515	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19516	/* C_NGL_D64_MM */	---	19516	/* C_NGL_D64_MM */	---
19517	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19517	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19518	/* C_NGL_S */	---	19518	/* C_NGL_S */	---
19519	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19519	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19520	/* C_NGL_S_MM */	---	19520	/* C_NGL_S_MM */	---
19521	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19521	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19522	/* C_NGT_D32 */	---	19522	/* C_NGT_D32 */	---
19523	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19523	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19524	/* C_NGT_D32_MM */	---	19524	/* C_NGT_D32_MM */	---
19525	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19525	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19526	/* C_NGT_D64 */	---	19526	/* C_NGT_D64 */	---
19527	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19527	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19528	/* C_NGT_D64_MM */	---	19528	/* C_NGT_D64_MM */	---
19529	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19529	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19530	/* C_NGT_S */	---	19530	/* C_NGT_S */	---
19531	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19531	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19532	/* C_NGT_S_MM */	---	19532	/* C_NGT_S_MM */	---
19533	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19533	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19534	/* C_OLE_D32 */	---	19534	/* C_OLE_D32 */	---
19535	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19535	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19536	/* C_OLE_D32_MM */	---	19536	/* C_OLE_D32_MM */	---
19537	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19537	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19538	/* C_OLE_D64 */	---	19538	/* C_OLE_D64 */	---
19539	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19539	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19540	/* C_OLE_D64_MM */	---	19540	/* C_OLE_D64_MM */	---
19541	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19541	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19542	/* C_OLE_S */	---	19542	/* C_OLE_S */	---
19543	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19543	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19544	/* C_OLE_S_MM */	---	19544	/* C_OLE_S_MM */	---
19545	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19545	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19546	/* C_OLT_D32 */	---	19546	/* C_OLT_D32 */	---
19547	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19547	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19548	/* C_OLT_D32_MM */	---	19548	/* C_OLT_D32_MM */	---
19549	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19549	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19550	/* C_OLT_D64 */	---	19550	/* C_OLT_D64 */	---
19551	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19551	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19552	/* C_OLT_D64_MM */	---	19552	/* C_OLT_D64_MM */	---
19553	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19553	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19554	/* C_OLT_S */	---	19554	/* C_OLT_S */	---
19555	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19555	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19556	/* C_OLT_S_MM */	---	19556	/* C_OLT_S_MM */	---
19557	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19557	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19558	/* C_SEQ_D32 */	---	19558	/* C_SEQ_D32 */	---
19559	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19559	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19560	/* C_SEQ_D32_MM */	---	19560	/* C_SEQ_D32_MM */	---
19561	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19561	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19562	/* C_SEQ_D64 */	---	19562	/* C_SEQ_D64 */	---
19563	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19563	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19564	/* C_SEQ_D64_MM */	---	19564	/* C_SEQ_D64_MM */	---
19565	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19565	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19566	/* C_SEQ_S */	---	19566	/* C_SEQ_S */	---
19567	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19567	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19568	/* C_SEQ_S_MM */	---	19568	/* C_SEQ_S_MM */	---
19569	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19569	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19570	/* C_SF_D32 */	---	19570	/* C_SF_D32 */	---
19571	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19571	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19572	/* C_SF_D32_MM */	---	19572	/* C_SF_D32_MM */	---
19573	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19573	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19574	/* C_SF_D64 */	---	19574	/* C_SF_D64 */	---
19575	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19575	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19576	/* C_SF_D64_MM */	---	19576	/* C_SF_D64_MM */	---
19577	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19577	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19578	/* C_SF_S */	---	19578	/* C_SF_S */	---
19579	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19579	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19580	/* C_SF_S_MM */	---	19580	/* C_SF_S_MM */	---
19581	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19581	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19582	/* C_UEQ_D32 */	---	19582	/* C_UEQ_D32 */	---
19583	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19583	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19584	/* C_UEQ_D32_MM */	---	19584	/* C_UEQ_D32_MM */	---
19585	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19585	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19586	/* C_UEQ_D64 */	---	19586	/* C_UEQ_D64 */	---
19587	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19587	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19588	/* C_UEQ_D64_MM */	---	19588	/* C_UEQ_D64_MM */	---
19589	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19589	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19590	/* C_UEQ_S */	---	19590	/* C_UEQ_S */	---
19591	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19591	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19592	/* C_UEQ_S_MM */	---	19592	/* C_UEQ_S_MM */	---
19593	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19593	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19594	/* C_ULE_D32 */	---	19594	/* C_ULE_D32 */	---
19595	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19595	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19596	/* C_ULE_D32_MM */	---	19596	/* C_ULE_D32_MM */	---
19597	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19597	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19598	/* C_ULE_D64 */	---	19598	/* C_ULE_D64 */	---
19599	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19599	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19600	/* C_ULE_D64_MM */	---	19600	/* C_ULE_D64_MM */	---
19601	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19601	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19602	/* C_ULE_S */	---	19602	/* C_ULE_S */	---
19603	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19603	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19604	/* C_ULE_S_MM */	---	19604	/* C_ULE_S_MM */	---
19605	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19605	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19606	/* C_ULT_D32 */	---	19606	/* C_ULT_D32 */	---
19607	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19607	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19608	/* C_ULT_D32_MM */	---	19608	/* C_ULT_D32_MM */	---
19609	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19609	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19610	/* C_ULT_D64 */	---	19610	/* C_ULT_D64 */	---
19611	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19611	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19612	/* C_ULT_D64_MM */	---	19612	/* C_ULT_D64_MM */	---
19613	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19613	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19614	/* C_ULT_S */	---	19614	/* C_ULT_S */	---
19615	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19615	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19616	/* C_ULT_S_MM */	---	19616	/* C_ULT_S_MM */	---
19617	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19617	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19618	/* C_UN_D32 */	---	19618	/* C_UN_D32 */	---
19619	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19619	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19620	/* C_UN_D32_MM */	---	19620	/* C_UN_D32_MM */	---
19621	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---	19621	FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,	---
19622	/* C_UN_D64 */	---	19622	/* C_UN_D64 */	---
19623	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19623	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19624	/* C_UN_D64_MM */	---	19624	/* C_UN_D64_MM */	---
19625	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---	19625	FCCRegsOpnd, FGR64Opnd, FGR64Opnd,	---
19626	/* C_UN_S */	---	19626	/* C_UN_S */	---
19627	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19627	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19628	/* C_UN_S_MM */	---	19628	/* C_UN_S_MM */	---
19629	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---	19629	FCCRegsOpnd, FGR32Opnd, FGR32Opnd,	---
19630	/* CmpRxRy16 */	---	19630	/* CmpRxRy16 */	---
19631	CPU16Regs, CPU16Regs,	---	19631	CPU16Regs, CPU16Regs,	---
19632	/* CmpiRxImm16 */	---	19632	/* CmpiRxImm16 */	---
19633	CPU16Regs, simm16,	---	19633	CPU16Regs, simm16,	---
19634	/* CmpiRxImmX16 */	---	19634	/* CmpiRxImmX16 */	---
19635	CPU16Regs, simm16,	---	19635	CPU16Regs, simm16,	---
19636	/* DADD */	---	19636	/* DADD */	---
19637	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19637	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19638	/* DADDi */	---	19638	/* DADDi */	---
19639	GPR64Opnd, GPR64Opnd, simm16_64,	---	19639	GPR64Opnd, GPR64Opnd, simm16_64,	---
19640	/* DADDiu */	---	19640	/* DADDiu */	---
19641	GPR64Opnd, GPR64Opnd, simm16_64,	---	19641	GPR64Opnd, GPR64Opnd, simm16_64,	---
19642	/* DADDu */	---	19642	/* DADDu */	---
19643	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19643	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19644	/* DAHI */	---	19644	/* DAHI */	---
19645	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	---	19645	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	---
19646	/* DALIGN */	---	19646	/* DALIGN */	---
19647	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,	---	19647	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,	---
19648	/* DATI */	---	19648	/* DATI */	---
19649	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	---	19649	GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,	---
19650	/* DAUI */	---	19650	/* DAUI */	---
19651	GPR64Opnd, GPR64Opnd, uimm16,	---	19651	GPR64Opnd, GPR64Opnd, uimm16,	---
19652	/* DBITSWAP */	---	19652	/* DBITSWAP */	---
19653	GPR64Opnd, GPR64Opnd,	---	19653	GPR64Opnd, GPR64Opnd,	---
19654	/* DCLO */	---	19654	/* DCLO */	---
19655	GPR64Opnd, GPR64Opnd,	---	19655	GPR64Opnd, GPR64Opnd,	---
19656	/* DCLO_R6 */	---	19656	/* DCLO_R6 */	---
19657	GPR64Opnd, GPR64Opnd,	---	19657	GPR64Opnd, GPR64Opnd,	---
19658	/* DCLZ */	---	19658	/* DCLZ */	---
19659	GPR64Opnd, GPR64Opnd,	---	19659	GPR64Opnd, GPR64Opnd,	---
19660	/* DCLZ_R6 */	---	19660	/* DCLZ_R6 */	---
19661	GPR64Opnd, GPR64Opnd,	---	19661	GPR64Opnd, GPR64Opnd,	---
19662	/* DDIV */	---	19662	/* DDIV */	---
19663	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19663	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19664	/* DDIVU */	---	19664	/* DDIVU */	---
19665	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19665	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19666	/* DERET */	---	19666	/* DERET */	---
19667	/* DERET_MM */	---	19667	/* DERET_MM */	---
19668	/* DERET_MMR6 */	---	19668	/* DERET_MMR6 */	---
19669	/* DEXT */	---	19669	/* DEXT */	---
19670	GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,	---	19670	GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,	---
19671	/* DEXT64_32 */	---	19671	/* DEXT64_32 */	---
19672	GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,	---	19672	GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,	---
19673	/* DEXTM */	---	19673	/* DEXTM */	---
19674	GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,	---	19674	GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,	---
19675	/* DEXTU */	---	19675	/* DEXTU */	---
19676	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,	---	19676	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,	---
19677	/* DI */	---	19677	/* DI */	---
19678	GPR32Opnd,	---	19678	GPR32Opnd,	---
19679	/* DINS */	---	19679	/* DINS */	---
19680	GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,	---	19680	GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,	---
19681	/* DINSM */	---	19681	/* DINSM */	---
19682	GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,	---	19682	GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,	---
19683	/* DINSU */	---	19683	/* DINSU */	---
19684	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,	---	19684	GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,	---
19685	/* DIV */	---	19685	/* DIV */	---
19686	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19686	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19687	/* DIVU */	---	19687	/* DIVU */	---
19688	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19688	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19689	/* DIVU_MMR6 */	---	19689	/* DIVU_MMR6 */	---
19690	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19690	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19691	/* DIV_MMR6 */	---	19691	/* DIV_MMR6 */	---
19692	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	19692	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
19693	/* DIV_S_B */	---	19693	/* DIV_S_B */	---
19694	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19694	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19695	/* DIV_S_D */	---	19695	/* DIV_S_D */	---
19696	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19696	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19697	/* DIV_S_H */	---	19697	/* DIV_S_H */	---
19698	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19698	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19699	/* DIV_S_W */	---	19699	/* DIV_S_W */	---
19700	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19700	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19701	/* DIV_U_B */	---	19701	/* DIV_U_B */	---
19702	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	19702	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
19703	/* DIV_U_D */	---	19703	/* DIV_U_D */	---
19704	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	19704	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
19705	/* DIV_U_H */	---	19705	/* DIV_U_H */	---
19706	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	19706	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
19707	/* DIV_U_W */	---	19707	/* DIV_U_W */	---
19708	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	19708	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
19709	/* DI_MM */	---	19709	/* DI_MM */	---
19710	GPR32Opnd,	---	19710	GPR32Opnd,	---
19711	/* DI_MMR6 */	---	19711	/* DI_MMR6 */	---
19712	GPR32Opnd,	---	19712	GPR32Opnd,	---
19713	/* DLSA */	---	19713	/* DLSA */	---
19714	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	---	19714	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	---
19715	/* DLSA_R6 */	---	19715	/* DLSA_R6 */	---
19716	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	---	19716	GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,	---
19717	/* DMFC0 */	---	19717	/* DMFC0 */	---
19718	GPR64Opnd, COP0Opnd, uimm3,	---	19718	GPR64Opnd, COP0Opnd, uimm3,	---
19719	/* DMFC1 */	---	19719	/* DMFC1 */	---
19720	GPR64Opnd, FGR64Opnd,	---	19720	GPR64Opnd, FGR64Opnd,	---
19721	/* DMFC2 */	---	19721	/* DMFC2 */	---
19722	GPR64Opnd, COP2Opnd, uimm3,	---	19722	GPR64Opnd, COP2Opnd, uimm3,	---
19723	/* DMFC2_OCTEON */	---	19723	/* DMFC2_OCTEON */	---
19724	GPR64Opnd, uimm16,	---	19724	GPR64Opnd, uimm16,	---
19725	/* DMFGC0 */	---	19725	/* DMFGC0 */	---
19726	GPR64Opnd, COP0Opnd, uimm3,	---	19726	GPR64Opnd, COP0Opnd, uimm3,	---
19727	/* DMOD */	---	19727	/* DMOD */	---
19728	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19728	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19729	/* DMODU */	---	19729	/* DMODU */	---
19730	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19730	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19731	/* DMT */	---	19731	/* DMT */	---
19732	GPR32Opnd,	---	19732	GPR32Opnd,	---
19733	/* DMTC0 */	---	19733	/* DMTC0 */	---
19734	COP0Opnd, GPR64Opnd, uimm3,	---	19734	COP0Opnd, GPR64Opnd, uimm3,	---
19735	/* DMTC1 */	---	19735	/* DMTC1 */	---
19736	FGR64Opnd, GPR64Opnd,	---	19736	FGR64Opnd, GPR64Opnd,	---
19737	/* DMTC2 */	---	19737	/* DMTC2 */	---
19738	COP2Opnd, GPR64Opnd, uimm3,	---	19738	COP2Opnd, GPR64Opnd, uimm3,	---
19739	/* DMTC2_OCTEON */	---	19739	/* DMTC2_OCTEON */	---
19740	GPR64Opnd, uimm16,	---	19740	GPR64Opnd, uimm16,	---
19741	/* DMTGC0 */	---	19741	/* DMTGC0 */	---
19742	COP0Opnd, GPR64Opnd, uimm3,	---	19742	COP0Opnd, GPR64Opnd, uimm3,	---
19743	/* DMUH */	---	19743	/* DMUH */	---
19744	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19744	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19745	/* DMUHU */	---	19745	/* DMUHU */	---
19746	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19746	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19747	/* DMUL */	---	19747	/* DMUL */	---
19748	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19748	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19749	/* DMULT */	---	19749	/* DMULT */	---
19750	GPR64Opnd, GPR64Opnd,	---	19750	GPR64Opnd, GPR64Opnd,	---
19751	/* DMULTu */	---	19751	/* DMULTu */	---
19752	GPR64Opnd, GPR64Opnd,	---	19752	GPR64Opnd, GPR64Opnd,	---
19753	/* DMULU */	---	19753	/* DMULU */	---
19754	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19754	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19755	/* DMUL_R6 */	---	19755	/* DMUL_R6 */	---
19756	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19756	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19757	/* DOTP_S_D */	---	19757	/* DOTP_S_D */	---
19758	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19758	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19759	/* DOTP_S_H */	---	19759	/* DOTP_S_H */	---
19760	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19760	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19761	/* DOTP_S_W */	---	19761	/* DOTP_S_W */	---
19762	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19762	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19763	/* DOTP_U_D */	---	19763	/* DOTP_U_D */	---
19764	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19764	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19765	/* DOTP_U_H */	---	19765	/* DOTP_U_H */	---
19766	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19766	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19767	/* DOTP_U_W */	---	19767	/* DOTP_U_W */	---
19768	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19768	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19769	/* DPADD_S_D */	---	19769	/* DPADD_S_D */	---
19770	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19770	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19771	/* DPADD_S_H */	---	19771	/* DPADD_S_H */	---
19772	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19772	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19773	/* DPADD_S_W */	---	19773	/* DPADD_S_W */	---
19774	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19774	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19775	/* DPADD_U_D */	---	19775	/* DPADD_U_D */	---
19776	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19776	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19777	/* DPADD_U_H */	---	19777	/* DPADD_U_H */	---
19778	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19778	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19779	/* DPADD_U_W */	---	19779	/* DPADD_U_W */	---
19780	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19780	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19781	/* DPAQX_SA_W_PH */	---	19781	/* DPAQX_SA_W_PH */	---
19782	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19782	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19783	/* DPAQX_SA_W_PH_MMR2 */	---	19783	/* DPAQX_SA_W_PH_MMR2 */	---
19784	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19784	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19785	/* DPAQX_S_W_PH */	---	19785	/* DPAQX_S_W_PH */	---
19786	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19786	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19787	/* DPAQX_S_W_PH_MMR2 */	---	19787	/* DPAQX_S_W_PH_MMR2 */	---
19788	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19788	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19789	/* DPAQ_SA_L_W */	---	19789	/* DPAQ_SA_L_W */	---
19790	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19790	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19791	/* DPAQ_SA_L_W_MM */	---	19791	/* DPAQ_SA_L_W_MM */	---
19792	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19792	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19793	/* DPAQ_S_W_PH */	---	19793	/* DPAQ_S_W_PH */	---
19794	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19794	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19795	/* DPAQ_S_W_PH_MM */	---	19795	/* DPAQ_S_W_PH_MM */	---
19796	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19796	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19797	/* DPAU_H_QBL */	---	19797	/* DPAU_H_QBL */	---
19798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19799	/* DPAU_H_QBL_MM */	---	19799	/* DPAU_H_QBL_MM */	---
19800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19801	/* DPAU_H_QBR */	---	19801	/* DPAU_H_QBR */	---
19802	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19802	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19803	/* DPAU_H_QBR_MM */	---	19803	/* DPAU_H_QBR_MM */	---
19804	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19804	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19805	/* DPAX_W_PH */	---	19805	/* DPAX_W_PH */	---
19806	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19806	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19807	/* DPAX_W_PH_MMR2 */	---	19807	/* DPAX_W_PH_MMR2 */	---
19808	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19808	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19809	/* DPA_W_PH */	---	19809	/* DPA_W_PH */	---
19810	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19810	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19811	/* DPA_W_PH_MMR2 */	---	19811	/* DPA_W_PH_MMR2 */	---
19812	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19812	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19813	/* DPOP */	---	19813	/* DPOP */	---
19814	GPR64Opnd, GPR64Opnd,	---	19814	GPR64Opnd, GPR64Opnd,	---
19815	/* DPSQX_SA_W_PH */	---	19815	/* DPSQX_SA_W_PH */	---
19816	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19816	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19817	/* DPSQX_SA_W_PH_MMR2 */	---	19817	/* DPSQX_SA_W_PH_MMR2 */	---
19818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19819	/* DPSQX_S_W_PH */	---	19819	/* DPSQX_S_W_PH */	---
19820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19821	/* DPSQX_S_W_PH_MMR2 */	---	19821	/* DPSQX_S_W_PH_MMR2 */	---
19822	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19822	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19823	/* DPSQ_SA_L_W */	---	19823	/* DPSQ_SA_L_W */	---
19824	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19824	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19825	/* DPSQ_SA_L_W_MM */	---	19825	/* DPSQ_SA_L_W_MM */	---
19826	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19826	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19827	/* DPSQ_S_W_PH */	---	19827	/* DPSQ_S_W_PH */	---
19828	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19828	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19829	/* DPSQ_S_W_PH_MM */	---	19829	/* DPSQ_S_W_PH_MM */	---
19830	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19830	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19831	/* DPSUB_S_D */	---	19831	/* DPSUB_S_D */	---
19832	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19832	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19833	/* DPSUB_S_H */	---	19833	/* DPSUB_S_H */	---
19834	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19834	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19835	/* DPSUB_S_W */	---	19835	/* DPSUB_S_W */	---
19836	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19836	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19837	/* DPSUB_U_D */	---	19837	/* DPSUB_U_D */	---
19838	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	19838	MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
19839	/* DPSUB_U_H */	---	19839	/* DPSUB_U_H */	---
19840	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	19840	MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
19841	/* DPSUB_U_W */	---	19841	/* DPSUB_U_W */	---
19842	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	19842	MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
19843	/* DPSU_H_QBL */	---	19843	/* DPSU_H_QBL */	---
19844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19845	/* DPSU_H_QBL_MM */	---	19845	/* DPSU_H_QBL_MM */	---
19846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19847	/* DPSU_H_QBR */	---	19847	/* DPSU_H_QBR */	---
19848	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19848	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19849	/* DPSU_H_QBR_MM */	---	19849	/* DPSU_H_QBR_MM */	---
19850	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19850	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19851	/* DPSX_W_PH */	---	19851	/* DPSX_W_PH */	---
19852	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19852	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19853	/* DPSX_W_PH_MMR2 */	---	19853	/* DPSX_W_PH_MMR2 */	---
19854	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19854	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19855	/* DPS_W_PH */	---	19855	/* DPS_W_PH */	---
19856	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19856	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19857	/* DPS_W_PH_MMR2 */	---	19857	/* DPS_W_PH_MMR2 */	---
19858	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	19858	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
19859	/* DROTR */	---	19859	/* DROTR */	---
19860	GPR64Opnd, GPR64Opnd, uimm6,	---	19860	GPR64Opnd, GPR64Opnd, uimm6,	---
19861	/* DROTR32 */	---	19861	/* DROTR32 */	---
19862	GPR64Opnd, GPR64Opnd, uimm5,	---	19862	GPR64Opnd, GPR64Opnd, uimm5,	---
19863	/* DROTRV */	---	19863	/* DROTRV */	---
19864	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---	19864	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---
19865	/* DSBH */	---	19865	/* DSBH */	---
19866	GPR64Opnd, GPR64Opnd,	---	19866	GPR64Opnd, GPR64Opnd,	---
19867	/* DSDIV */	---	19867	/* DSDIV */	---
19868	GPR64Opnd, GPR64Opnd,	---	19868	GPR64Opnd, GPR64Opnd,	---
19869	/* DSHD */	---	19869	/* DSHD */	---
19870	GPR64Opnd, GPR64Opnd,	---	19870	GPR64Opnd, GPR64Opnd,	---
19871	/* DSLL */	---	19871	/* DSLL */	---
19872	GPR64Opnd, GPR64Opnd, uimm6,	---	19872	GPR64Opnd, GPR64Opnd, uimm6,	---
19873	/* DSLL32 */	---	19873	/* DSLL32 */	---
19874	GPR64Opnd, GPR64Opnd, uimm5,	---	19874	GPR64Opnd, GPR64Opnd, uimm5,	---
19875	/* DSLL64_32 */	---	19875	/* DSLL64_32 */	---
19876	GPR64, GPR32,	---	19876	GPR64, GPR32,	---
19877	/* DSLLV */	---	19877	/* DSLLV */	---
19878	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---	19878	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---
19879	/* DSRA */	---	19879	/* DSRA */	---
19880	GPR64Opnd, GPR64Opnd, uimm6,	---	19880	GPR64Opnd, GPR64Opnd, uimm6,	---
19881	/* DSRA32 */	---	19881	/* DSRA32 */	---
19882	GPR64Opnd, GPR64Opnd, uimm5,	---	19882	GPR64Opnd, GPR64Opnd, uimm5,	---
19883	/* DSRAV */	---	19883	/* DSRAV */	---
19884	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---	19884	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---
19885	/* DSRL */	---	19885	/* DSRL */	---
19886	GPR64Opnd, GPR64Opnd, uimm6,	---	19886	GPR64Opnd, GPR64Opnd, uimm6,	---
19887	/* DSRL32 */	---	19887	/* DSRL32 */	---
19888	GPR64Opnd, GPR64Opnd, uimm5,	---	19888	GPR64Opnd, GPR64Opnd, uimm5,	---
19889	/* DSRLV */	---	19889	/* DSRLV */	---
19890	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---	19890	GPR64Opnd, GPR64Opnd, GPR32Opnd,	---
19891	/* DSUB */	---	19891	/* DSUB */	---
19892	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19892	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19893	/* DSUBu */	---	19893	/* DSUBu */	---
19894	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	19894	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
19895	/* DUDIV */	---	19895	/* DUDIV */	---
19896	GPR64Opnd, GPR64Opnd,	---	19896	GPR64Opnd, GPR64Opnd,	---
19897	/* DVP */	---	19897	/* DVP */	---
19898	GPR32Opnd,	---	19898	GPR32Opnd,	---
19899	/* DVPE */	---	19899	/* DVPE */	---
19900	GPR32Opnd,	---	19900	GPR32Opnd,	---
19901	/* DVP_MMR6 */	---	19901	/* DVP_MMR6 */	---
19902	GPR32Opnd,	---	19902	GPR32Opnd,	---
19903	/* DivRxRy16 */	---	19903	/* DivRxRy16 */	---
19904	CPU16Regs, CPU16Regs,	---	19904	CPU16Regs, CPU16Regs,	---
19905	/* DivuRxRy16 */	---	19905	/* DivuRxRy16 */	---
19906	CPU16Regs, CPU16Regs,	---	19906	CPU16Regs, CPU16Regs,	---
19907	/* EHB */	---	19907	/* EHB */	---
19908	/* EHB_MM */	---	19908	/* EHB_MM */	---
19909	/* EHB_MMR6 */	---	19909	/* EHB_MMR6 */	---
19910	/* EI */	---	19910	/* EI */	---
19911	GPR32Opnd,	---	19911	GPR32Opnd,	---
19912	/* EI_MM */	---	19912	/* EI_MM */	---
19913	GPR32Opnd,	---	19913	GPR32Opnd,	---
19914	/* EI_MMR6 */	---	19914	/* EI_MMR6 */	---
19915	GPR32Opnd,	---	19915	GPR32Opnd,	---
19916	/* EMT */	---	19916	/* EMT */	---
19917	GPR32Opnd,	---	19917	GPR32Opnd,	---
19918	/* ERET */	---	19918	/* ERET */	---
19919	/* ERETNC */	---	19919	/* ERETNC */	---
19920	/* ERETNC_MMR6 */	---	19920	/* ERETNC_MMR6 */	---
19921	/* ERET_MM */	---	19921	/* ERET_MM */	---
19922	/* ERET_MMR6 */	---	19922	/* ERET_MMR6 */	---
19923	/* EVP */	---	19923	/* EVP */	---
19924	GPR32Opnd,	---	19924	GPR32Opnd,	---
19925	/* EVPE */	---	19925	/* EVPE */	---
19926	GPR32Opnd,	---	19926	GPR32Opnd,	---
19927	/* EVP_MMR6 */	---	19927	/* EVP_MMR6 */	---
19928	GPR32Opnd,	---	19928	GPR32Opnd,	---
19929	/* EXT */	---	19929	/* EXT */	---
19930	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---	19930	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---
19931	/* EXTP */	---	19931	/* EXTP */	---
19932	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19932	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19933	/* EXTPDP */	---	19933	/* EXTPDP */	---
19934	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19934	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19935	/* EXTPDPV */	---	19935	/* EXTPDPV */	---
19936	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19936	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19937	/* EXTPDPV_MM */	---	19937	/* EXTPDPV_MM */	---
19938	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19938	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19939	/* EXTPDP_MM */	---	19939	/* EXTPDP_MM */	---
19940	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19940	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19941	/* EXTPV */	---	19941	/* EXTPV */	---
19942	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19942	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19943	/* EXTPV_MM */	---	19943	/* EXTPV_MM */	---
19944	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19944	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19945	/* EXTP_MM */	---	19945	/* EXTP_MM */	---
19946	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19946	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19947	/* EXTRV_RS_W */	---	19947	/* EXTRV_RS_W */	---
19948	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19948	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19949	/* EXTRV_RS_W_MM */	---	19949	/* EXTRV_RS_W_MM */	---
19950	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19950	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19951	/* EXTRV_R_W */	---	19951	/* EXTRV_R_W */	---
19952	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19952	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19953	/* EXTRV_R_W_MM */	---	19953	/* EXTRV_R_W_MM */	---
19954	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19954	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19955	/* EXTRV_S_H */	---	19955	/* EXTRV_S_H */	---
19956	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19956	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19957	/* EXTRV_S_H_MM */	---	19957	/* EXTRV_S_H_MM */	---
19958	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19958	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19959	/* EXTRV_W */	---	19959	/* EXTRV_W */	---
19960	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19960	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19961	/* EXTRV_W_MM */	---	19961	/* EXTRV_W_MM */	---
19962	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---	19962	GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,	---
19963	/* EXTR_RS_W */	---	19963	/* EXTR_RS_W */	---
19964	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19964	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19965	/* EXTR_RS_W_MM */	---	19965	/* EXTR_RS_W_MM */	---
19966	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19966	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19967	/* EXTR_R_W */	---	19967	/* EXTR_R_W */	---
19968	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19968	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19969	/* EXTR_R_W_MM */	---	19969	/* EXTR_R_W_MM */	---
19970	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19970	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19971	/* EXTR_S_H */	---	19971	/* EXTR_S_H */	---
19972	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19972	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19973	/* EXTR_S_H_MM */	---	19973	/* EXTR_S_H_MM */	---
19974	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19974	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19975	/* EXTR_W */	---	19975	/* EXTR_W */	---
19976	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19976	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19977	/* EXTR_W_MM */	---	19977	/* EXTR_W_MM */	---
19978	GPR32Opnd, ACC64DSPOpnd, uimm5,	---	19978	GPR32Opnd, ACC64DSPOpnd, uimm5,	---
19979	/* EXTS */	---	19979	/* EXTS */	---
19980	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---	19980	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---
19981	/* EXTS32 */	---	19981	/* EXTS32 */	---
19982	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---	19982	GPR64Opnd, GPR64Opnd, uimm5, uimm5,	---
19983	/* EXT_MM */	---	19983	/* EXT_MM */	---
19984	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---	19984	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---
19985	/* EXT_MMR6 */	---	19985	/* EXT_MMR6 */	---
19986	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---	19986	GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,	---
19987	/* FABS_D32 */	---	19987	/* FABS_D32 */	---
19988	AFGR64Opnd, AFGR64Opnd,	---	19988	AFGR64Opnd, AFGR64Opnd,	---
19989	/* FABS_D32_MM */	---	19989	/* FABS_D32_MM */	---
19990	AFGR64Opnd, AFGR64Opnd,	---	19990	AFGR64Opnd, AFGR64Opnd,	---
19991	/* FABS_D64 */	---	19991	/* FABS_D64 */	---
19992	FGR64Opnd, FGR64Opnd,	---	19992	FGR64Opnd, FGR64Opnd,	---
19993	/* FABS_D64_MM */	---	19993	/* FABS_D64_MM */	---
19994	FGR64Opnd, FGR64Opnd,	---	19994	FGR64Opnd, FGR64Opnd,	---
19995	/* FABS_S */	---	19995	/* FABS_S */	---
19996	FGR32Opnd, FGR32Opnd,	---	19996	FGR32Opnd, FGR32Opnd,	---
19997	/* FABS_S_MM */	---	19997	/* FABS_S_MM */	---
19998	FGR32Opnd, FGR32Opnd,	---	19998	FGR32Opnd, FGR32Opnd,	---
19999	/* FADD_D */	---	19999	/* FADD_D */	---
20000	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20000	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20001	/* FADD_D32 */	---	20001	/* FADD_D32 */	---
20002	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20002	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20003	/* FADD_D32_MM */	---	20003	/* FADD_D32_MM */	---
20004	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20004	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20005	/* FADD_D64 */	---	20005	/* FADD_D64 */	---
20006	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20006	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20007	/* FADD_D64_MM */	---	20007	/* FADD_D64_MM */	---
20008	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20008	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20009	/* FADD_PS64 */	---	20009	/* FADD_PS64 */	---
20010	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20010	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20011	/* FADD_S */	---	20011	/* FADD_S */	---
20012	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20012	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20013	/* FADD_S_MM */	---	20013	/* FADD_S_MM */	---
20014	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20014	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20015	/* FADD_S_MMR6 */	---	20015	/* FADD_S_MMR6 */	---
20016	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20016	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20017	/* FADD_W */	---	20017	/* FADD_W */	---
20018	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20018	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20019	/* FCAF_D */	---	20019	/* FCAF_D */	---
20020	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20020	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20021	/* FCAF_W */	---	20021	/* FCAF_W */	---
20022	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20022	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20023	/* FCEQ_D */	---	20023	/* FCEQ_D */	---
20024	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20024	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20025	/* FCEQ_W */	---	20025	/* FCEQ_W */	---
20026	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20026	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20027	/* FCLASS_D */	---	20027	/* FCLASS_D */	---
20028	MSA128DOpnd, MSA128DOpnd,	---	20028	MSA128DOpnd, MSA128DOpnd,	---
20029	/* FCLASS_W */	---	20029	/* FCLASS_W */	---
20030	MSA128WOpnd, MSA128WOpnd,	---	20030	MSA128WOpnd, MSA128WOpnd,	---
20031	/* FCLE_D */	---	20031	/* FCLE_D */	---
20032	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20032	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20033	/* FCLE_W */	---	20033	/* FCLE_W */	---
20034	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20034	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20035	/* FCLT_D */	---	20035	/* FCLT_D */	---
20036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20037	/* FCLT_W */	---	20037	/* FCLT_W */	---
20038	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20038	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20039	/* FCMP_D32 */	---	20039	/* FCMP_D32 */	---
20040	AFGR64, AFGR64, condcode,	---	20040	AFGR64, AFGR64, condcode,	---
20041	/* FCMP_D32_MM */	---	20041	/* FCMP_D32_MM */	---
20042	AFGR64, AFGR64, condcode,	---	20042	AFGR64, AFGR64, condcode,	---
20043	/* FCMP_D64 */	---	20043	/* FCMP_D64 */	---
20044	FGR64, FGR64, condcode,	---	20044	FGR64, FGR64, condcode,	---
20045	/* FCMP_S32 */	---	20045	/* FCMP_S32 */	---
20046	FGR32, FGR32, condcode,	---	20046	FGR32, FGR32, condcode,	---
20047	/* FCMP_S32_MM */	---	20047	/* FCMP_S32_MM */	---
20048	FGR32, FGR32, condcode,	---	20048	FGR32, FGR32, condcode,	---
20049	/* FCNE_D */	---	20049	/* FCNE_D */	---
20050	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20050	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20051	/* FCNE_W */	---	20051	/* FCNE_W */	---
20052	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20052	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20053	/* FCOR_D */	---	20053	/* FCOR_D */	---
20054	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20054	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20055	/* FCOR_W */	---	20055	/* FCOR_W */	---
20056	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20056	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20057	/* FCUEQ_D */	---	20057	/* FCUEQ_D */	---
20058	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20058	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20059	/* FCUEQ_W */	---	20059	/* FCUEQ_W */	---
20060	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20060	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20061	/* FCULE_D */	---	20061	/* FCULE_D */	---
20062	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20062	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20063	/* FCULE_W */	---	20063	/* FCULE_W */	---
20064	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20064	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20065	/* FCULT_D */	---	20065	/* FCULT_D */	---
20066	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20066	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20067	/* FCULT_W */	---	20067	/* FCULT_W */	---
20068	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20068	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20069	/* FCUNE_D */	---	20069	/* FCUNE_D */	---
20070	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20070	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20071	/* FCUNE_W */	---	20071	/* FCUNE_W */	---
20072	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20072	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20073	/* FCUN_D */	---	20073	/* FCUN_D */	---
20074	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20074	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20075	/* FCUN_W */	---	20075	/* FCUN_W */	---
20076	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20076	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20077	/* FDIV_D */	---	20077	/* FDIV_D */	---
20078	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20078	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20079	/* FDIV_D32 */	---	20079	/* FDIV_D32 */	---
20080	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20080	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20081	/* FDIV_D32_MM */	---	20081	/* FDIV_D32_MM */	---
20082	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20082	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20083	/* FDIV_D64 */	---	20083	/* FDIV_D64 */	---
20084	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20084	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20085	/* FDIV_D64_MM */	---	20085	/* FDIV_D64_MM */	---
20086	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20086	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20087	/* FDIV_S */	---	20087	/* FDIV_S */	---
20088	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20088	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20089	/* FDIV_S_MM */	---	20089	/* FDIV_S_MM */	---
20090	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20090	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20091	/* FDIV_S_MMR6 */	---	20091	/* FDIV_S_MMR6 */	---
20092	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20092	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20093	/* FDIV_W */	---	20093	/* FDIV_W */	---
20094	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20094	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20095	/* FEXDO_H */	---	20095	/* FEXDO_H */	---
20096	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	---	20096	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	---
20097	/* FEXDO_W */	---	20097	/* FEXDO_W */	---
20098	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	---	20098	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	---
20099	/* FEXP2_D */	---	20099	/* FEXP2_D */	---
20100	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20100	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20101	/* FEXP2_W */	---	20101	/* FEXP2_W */	---
20102	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20102	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20103	/* FEXUPL_D */	---	20103	/* FEXUPL_D */	---
20104	MSA128DOpnd, MSA128WOpnd,	---	20104	MSA128DOpnd, MSA128WOpnd,	---
20105	/* FEXUPL_W */	---	20105	/* FEXUPL_W */	---
20106	MSA128WOpnd, MSA128HOpnd,	---	20106	MSA128WOpnd, MSA128HOpnd,	---
20107	/* FEXUPR_D */	---	20107	/* FEXUPR_D */	---
20108	MSA128DOpnd, MSA128WOpnd,	---	20108	MSA128DOpnd, MSA128WOpnd,	---
20109	/* FEXUPR_W */	---	20109	/* FEXUPR_W */	---
20110	MSA128WOpnd, MSA128HOpnd,	---	20110	MSA128WOpnd, MSA128HOpnd,	---
20111	/* FFINT_S_D */	---	20111	/* FFINT_S_D */	---
20112	MSA128DOpnd, MSA128DOpnd,	---	20112	MSA128DOpnd, MSA128DOpnd,	---
20113	/* FFINT_S_W */	---	20113	/* FFINT_S_W */	---
20114	MSA128WOpnd, MSA128WOpnd,	---	20114	MSA128WOpnd, MSA128WOpnd,	---
20115	/* FFINT_U_D */	---	20115	/* FFINT_U_D */	---
20116	MSA128DOpnd, MSA128DOpnd,	---	20116	MSA128DOpnd, MSA128DOpnd,	---
20117	/* FFINT_U_W */	---	20117	/* FFINT_U_W */	---
20118	MSA128WOpnd, MSA128WOpnd,	---	20118	MSA128WOpnd, MSA128WOpnd,	---
20119	/* FFQL_D */	---	20119	/* FFQL_D */	---
20120	MSA128DOpnd, MSA128WOpnd,	---	20120	MSA128DOpnd, MSA128WOpnd,	---
20121	/* FFQL_W */	---	20121	/* FFQL_W */	---
20122	MSA128WOpnd, MSA128HOpnd,	---	20122	MSA128WOpnd, MSA128HOpnd,	---
20123	/* FFQR_D */	---	20123	/* FFQR_D */	---
20124	MSA128DOpnd, MSA128WOpnd,	---	20124	MSA128DOpnd, MSA128WOpnd,	---
20125	/* FFQR_W */	---	20125	/* FFQR_W */	---
20126	MSA128WOpnd, MSA128HOpnd,	---	20126	MSA128WOpnd, MSA128HOpnd,	---
20127	/* FILL_B */	---	20127	/* FILL_B */	---
20128	MSA128BOpnd, GPR32Opnd,	---	20128	MSA128BOpnd, GPR32Opnd,	---
20129	/* FILL_D */	---	20129	/* FILL_D */	---
20130	MSA128DOpnd, GPR64Opnd,	---	20130	MSA128DOpnd, GPR64Opnd,	---
20131	/* FILL_H */	---	20131	/* FILL_H */	---
20132	MSA128HOpnd, GPR32Opnd,	---	20132	MSA128HOpnd, GPR32Opnd,	---
20133	/* FILL_W */	---	20133	/* FILL_W */	---
20134	MSA128WOpnd, GPR32Opnd,	---	20134	MSA128WOpnd, GPR32Opnd,	---
20135	/* FLOG2_D */	---	20135	/* FLOG2_D */	---
20136	MSA128DOpnd, MSA128DOpnd,	---	20136	MSA128DOpnd, MSA128DOpnd,	---
20137	/* FLOG2_W */	---	20137	/* FLOG2_W */	---
20138	MSA128WOpnd, MSA128WOpnd,	---	20138	MSA128WOpnd, MSA128WOpnd,	---
20139	/* FLOOR_L_D64 */	---	20139	/* FLOOR_L_D64 */	---
20140	FGR64Opnd, FGR64Opnd,	---	20140	FGR64Opnd, FGR64Opnd,	---
20141	/* FLOOR_L_D_MMR6 */	---	20141	/* FLOOR_L_D_MMR6 */	---
20142	FGR64Opnd, FGR64Opnd,	---	20142	FGR64Opnd, FGR64Opnd,	---
20143	/* FLOOR_L_S */	---	20143	/* FLOOR_L_S */	---
20144	FGR64Opnd, FGR32Opnd,	---	20144	FGR64Opnd, FGR32Opnd,	---
20145	/* FLOOR_L_S_MMR6 */	---	20145	/* FLOOR_L_S_MMR6 */	---
20146	FGR64Opnd, FGR32Opnd,	---	20146	FGR64Opnd, FGR32Opnd,	---
20147	/* FLOOR_W_D32 */	---	20147	/* FLOOR_W_D32 */	---
20148	FGR32Opnd, AFGR64Opnd,	---	20148	FGR32Opnd, AFGR64Opnd,	---
20149	/* FLOOR_W_D64 */	---	20149	/* FLOOR_W_D64 */	---
20150	FGR32Opnd, FGR64Opnd,	---	20150	FGR32Opnd, FGR64Opnd,	---
20151	/* FLOOR_W_D_MMR6 */	---	20151	/* FLOOR_W_D_MMR6 */	---
20152	FGR32Opnd, AFGR64Opnd,	---	20152	FGR32Opnd, AFGR64Opnd,	---
20153	/* FLOOR_W_MM */	---	20153	/* FLOOR_W_MM */	---
20154	FGR32Opnd, AFGR64Opnd,	---	20154	FGR32Opnd, AFGR64Opnd,	---
20155	/* FLOOR_W_S */	---	20155	/* FLOOR_W_S */	---
20156	FGR32Opnd, FGR32Opnd,	---	20156	FGR32Opnd, FGR32Opnd,	---
20157	/* FLOOR_W_S_MM */	---	20157	/* FLOOR_W_S_MM */	---
20158	FGR32Opnd, FGR32Opnd,	---	20158	FGR32Opnd, FGR32Opnd,	---
20159	/* FLOOR_W_S_MMR6 */	---	20159	/* FLOOR_W_S_MMR6 */	---
20160	FGR32Opnd, FGR32Opnd,	---	20160	FGR32Opnd, FGR32Opnd,	---
20161	/* FMADD_D */	---	20161	/* FMADD_D */	---
20162	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20162	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20163	/* FMADD_W */	---	20163	/* FMADD_W */	---
20164	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20164	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20165	/* FMAX_A_D */	---	20165	/* FMAX_A_D */	---
20166	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20166	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20167	/* FMAX_A_W */	---	20167	/* FMAX_A_W */	---
20168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20169	/* FMAX_D */	---	20169	/* FMAX_D */	---
20170	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20170	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20171	/* FMAX_W */	---	20171	/* FMAX_W */	---
20172	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20172	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20173	/* FMIN_A_D */	---	20173	/* FMIN_A_D */	---
20174	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20174	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20175	/* FMIN_A_W */	---	20175	/* FMIN_A_W */	---
20176	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20176	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20177	/* FMIN_D */	---	20177	/* FMIN_D */	---
20178	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20178	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20179	/* FMIN_W */	---	20179	/* FMIN_W */	---
20180	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20180	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20181	/* FMOV_D32 */	---	20181	/* FMOV_D32 */	---
20182	AFGR64Opnd, AFGR64Opnd,	---	20182	AFGR64Opnd, AFGR64Opnd,	---
20183	/* FMOV_D32_MM */	---	20183	/* FMOV_D32_MM */	---
20184	AFGR64Opnd, AFGR64Opnd,	---	20184	AFGR64Opnd, AFGR64Opnd,	---
20185	/* FMOV_D64 */	---	20185	/* FMOV_D64 */	---
20186	FGR64Opnd, FGR64Opnd,	---	20186	FGR64Opnd, FGR64Opnd,	---
20187	/* FMOV_D64_MM */	---	20187	/* FMOV_D64_MM */	---
20188	FGR64Opnd, FGR64Opnd,	---	20188	FGR64Opnd, FGR64Opnd,	---
20189	/* FMOV_D_MMR6 */	---	20189	/* FMOV_D_MMR6 */	---
20190	FGR64Opnd, FGR64Opnd,	---	20190	FGR64Opnd, FGR64Opnd,	---
20191	/* FMOV_S */	---	20191	/* FMOV_S */	---
20192	FGR32Opnd, FGR32Opnd,	---	20192	FGR32Opnd, FGR32Opnd,	---
20193	/* FMOV_S_MM */	---	20193	/* FMOV_S_MM */	---
20194	FGR32Opnd, FGR32Opnd,	---	20194	FGR32Opnd, FGR32Opnd,	---
20195	/* FMOV_S_MMR6 */	---	20195	/* FMOV_S_MMR6 */	---
20196	FGR32Opnd, FGR32Opnd,	---	20196	FGR32Opnd, FGR32Opnd,	---
20197	/* FMSUB_D */	---	20197	/* FMSUB_D */	---
20198	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20198	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20199	/* FMSUB_W */	---	20199	/* FMSUB_W */	---
20200	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20200	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20201	/* FMUL_D */	---	20201	/* FMUL_D */	---
20202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20203	/* FMUL_D32 */	---	20203	/* FMUL_D32 */	---
20204	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20204	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20205	/* FMUL_D32_MM */	---	20205	/* FMUL_D32_MM */	---
20206	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20206	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20207	/* FMUL_D64 */	---	20207	/* FMUL_D64 */	---
20208	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20208	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20209	/* FMUL_D64_MM */	---	20209	/* FMUL_D64_MM */	---
20210	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20210	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20211	/* FMUL_PS64 */	---	20211	/* FMUL_PS64 */	---
20212	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20212	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20213	/* FMUL_S */	---	20213	/* FMUL_S */	---
20214	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20214	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20215	/* FMUL_S_MM */	---	20215	/* FMUL_S_MM */	---
20216	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20216	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20217	/* FMUL_S_MMR6 */	---	20217	/* FMUL_S_MMR6 */	---
20218	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20218	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20219	/* FMUL_W */	---	20219	/* FMUL_W */	---
20220	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20220	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20221	/* FNEG_D32 */	---	20221	/* FNEG_D32 */	---
20222	AFGR64Opnd, AFGR64Opnd,	---	20222	AFGR64Opnd, AFGR64Opnd,	---
20223	/* FNEG_D32_MM */	---	20223	/* FNEG_D32_MM */	---
20224	AFGR64Opnd, AFGR64Opnd,	---	20224	AFGR64Opnd, AFGR64Opnd,	---
20225	/* FNEG_D64 */	---	20225	/* FNEG_D64 */	---
20226	FGR64Opnd, FGR64Opnd,	---	20226	FGR64Opnd, FGR64Opnd,	---
20227	/* FNEG_D64_MM */	---	20227	/* FNEG_D64_MM */	---
20228	FGR64Opnd, FGR64Opnd,	---	20228	FGR64Opnd, FGR64Opnd,	---
20229	/* FNEG_S */	---	20229	/* FNEG_S */	---
20230	FGR32Opnd, FGR32Opnd,	---	20230	FGR32Opnd, FGR32Opnd,	---
20231	/* FNEG_S_MM */	---	20231	/* FNEG_S_MM */	---
20232	FGR32Opnd, FGR32Opnd,	---	20232	FGR32Opnd, FGR32Opnd,	---
20233	/* FNEG_S_MMR6 */	---	20233	/* FNEG_S_MMR6 */	---
20234	FGR32Opnd, FGR32Opnd,	---	20234	FGR32Opnd, FGR32Opnd,	---
20235	/* FORK */	---	20235	/* FORK */	---
20236	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	20236	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
20237	/* FRCP_D */	---	20237	/* FRCP_D */	---
20238	MSA128DOpnd, MSA128DOpnd,	---	20238	MSA128DOpnd, MSA128DOpnd,	---
20239	/* FRCP_W */	---	20239	/* FRCP_W */	---
20240	MSA128WOpnd, MSA128WOpnd,	---	20240	MSA128WOpnd, MSA128WOpnd,	---
20241	/* FRINT_D */	---	20241	/* FRINT_D */	---
20242	MSA128DOpnd, MSA128DOpnd,	---	20242	MSA128DOpnd, MSA128DOpnd,	---
20243	/* FRINT_W */	---	20243	/* FRINT_W */	---
20244	MSA128WOpnd, MSA128WOpnd,	---	20244	MSA128WOpnd, MSA128WOpnd,	---
20245	/* FRSQRT_D */	---	20245	/* FRSQRT_D */	---
20246	MSA128DOpnd, MSA128DOpnd,	---	20246	MSA128DOpnd, MSA128DOpnd,	---
20247	/* FRSQRT_W */	---	20247	/* FRSQRT_W */	---
20248	MSA128WOpnd, MSA128WOpnd,	---	20248	MSA128WOpnd, MSA128WOpnd,	---
20249	/* FSAF_D */	---	20249	/* FSAF_D */	---
20250	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20250	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20251	/* FSAF_W */	---	20251	/* FSAF_W */	---
20252	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20252	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20253	/* FSEQ_D */	---	20253	/* FSEQ_D */	---
20254	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20254	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20255	/* FSEQ_W */	---	20255	/* FSEQ_W */	---
20256	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20256	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20257	/* FSLE_D */	---	20257	/* FSLE_D */	---
20258	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20258	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20259	/* FSLE_W */	---	20259	/* FSLE_W */	---
20260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20261	/* FSLT_D */	---	20261	/* FSLT_D */	---
20262	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20262	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20263	/* FSLT_W */	---	20263	/* FSLT_W */	---
20264	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20264	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20265	/* FSNE_D */	---	20265	/* FSNE_D */	---
20266	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20266	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20267	/* FSNE_W */	---	20267	/* FSNE_W */	---
20268	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20268	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20269	/* FSOR_D */	---	20269	/* FSOR_D */	---
20270	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20270	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20271	/* FSOR_W */	---	20271	/* FSOR_W */	---
20272	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20272	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20273	/* FSQRT_D */	---	20273	/* FSQRT_D */	---
20274	MSA128DOpnd, MSA128DOpnd,	---	20274	MSA128DOpnd, MSA128DOpnd,	---
20275	/* FSQRT_D32 */	---	20275	/* FSQRT_D32 */	---
20276	AFGR64Opnd, AFGR64Opnd,	---	20276	AFGR64Opnd, AFGR64Opnd,	---
20277	/* FSQRT_D32_MM */	---	20277	/* FSQRT_D32_MM */	---
20278	AFGR64Opnd, AFGR64Opnd,	---	20278	AFGR64Opnd, AFGR64Opnd,	---
20279	/* FSQRT_D64 */	---	20279	/* FSQRT_D64 */	---
20280	FGR64Opnd, FGR64Opnd,	---	20280	FGR64Opnd, FGR64Opnd,	---
20281	/* FSQRT_D64_MM */	---	20281	/* FSQRT_D64_MM */	---
20282	FGR64Opnd, FGR64Opnd,	---	20282	FGR64Opnd, FGR64Opnd,	---
20283	/* FSQRT_S */	---	20283	/* FSQRT_S */	---
20284	FGR32Opnd, FGR32Opnd,	---	20284	FGR32Opnd, FGR32Opnd,	---
20285	/* FSQRT_S_MM */	---	20285	/* FSQRT_S_MM */	---
20286	FGR32Opnd, FGR32Opnd,	---	20286	FGR32Opnd, FGR32Opnd,	---
20287	/* FSQRT_W */	---	20287	/* FSQRT_W */	---
20288	MSA128WOpnd, MSA128WOpnd,	---	20288	MSA128WOpnd, MSA128WOpnd,	---
20289	/* FSUB_D */	---	20289	/* FSUB_D */	---
20290	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20290	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20291	/* FSUB_D32 */	---	20291	/* FSUB_D32 */	---
20292	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20292	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20293	/* FSUB_D32_MM */	---	20293	/* FSUB_D32_MM */	---
20294	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20294	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20295	/* FSUB_D64 */	---	20295	/* FSUB_D64 */	---
20296	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20296	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20297	/* FSUB_D64_MM */	---	20297	/* FSUB_D64_MM */	---
20298	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20298	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20299	/* FSUB_PS64 */	---	20299	/* FSUB_PS64 */	---
20300	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20300	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20301	/* FSUB_S */	---	20301	/* FSUB_S */	---
20302	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20302	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20303	/* FSUB_S_MM */	---	20303	/* FSUB_S_MM */	---
20304	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20304	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20305	/* FSUB_S_MMR6 */	---	20305	/* FSUB_S_MMR6 */	---
20306	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20306	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20307	/* FSUB_W */	---	20307	/* FSUB_W */	---
20308	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20308	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20309	/* FSUEQ_D */	---	20309	/* FSUEQ_D */	---
20310	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20310	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20311	/* FSUEQ_W */	---	20311	/* FSUEQ_W */	---
20312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20313	/* FSULE_D */	---	20313	/* FSULE_D */	---
20314	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20314	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20315	/* FSULE_W */	---	20315	/* FSULE_W */	---
20316	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20316	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20317	/* FSULT_D */	---	20317	/* FSULT_D */	---
20318	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20318	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20319	/* FSULT_W */	---	20319	/* FSULT_W */	---
20320	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20320	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20321	/* FSUNE_D */	---	20321	/* FSUNE_D */	---
20322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20322	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20323	/* FSUNE_W */	---	20323	/* FSUNE_W */	---
20324	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20324	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20325	/* FSUN_D */	---	20325	/* FSUN_D */	---
20326	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20326	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20327	/* FSUN_W */	---	20327	/* FSUN_W */	---
20328	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20328	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20329	/* FTINT_S_D */	---	20329	/* FTINT_S_D */	---
20330	MSA128DOpnd, MSA128DOpnd,	---	20330	MSA128DOpnd, MSA128DOpnd,	---
20331	/* FTINT_S_W */	---	20331	/* FTINT_S_W */	---
20332	MSA128WOpnd, MSA128WOpnd,	---	20332	MSA128WOpnd, MSA128WOpnd,	---
20333	/* FTINT_U_D */	---	20333	/* FTINT_U_D */	---
20334	MSA128DOpnd, MSA128DOpnd,	---	20334	MSA128DOpnd, MSA128DOpnd,	---
20335	/* FTINT_U_W */	---	20335	/* FTINT_U_W */	---
20336	MSA128WOpnd, MSA128WOpnd,	---	20336	MSA128WOpnd, MSA128WOpnd,	---
20337	/* FTQ_H */	---	20337	/* FTQ_H */	---
20338	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	---	20338	MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,	---
20339	/* FTQ_W */	---	20339	/* FTQ_W */	---
20340	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	---	20340	MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,	---
20341	/* FTRUNC_S_D */	---	20341	/* FTRUNC_S_D */	---
20342	MSA128DOpnd, MSA128DOpnd,	---	20342	MSA128DOpnd, MSA128DOpnd,	---
20343	/* FTRUNC_S_W */	---	20343	/* FTRUNC_S_W */	---
20344	MSA128WOpnd, MSA128WOpnd,	---	20344	MSA128WOpnd, MSA128WOpnd,	---
20345	/* FTRUNC_U_D */	---	20345	/* FTRUNC_U_D */	---
20346	MSA128DOpnd, MSA128DOpnd,	---	20346	MSA128DOpnd, MSA128DOpnd,	---
20347	/* FTRUNC_U_W */	---	20347	/* FTRUNC_U_W */	---
20348	MSA128WOpnd, MSA128WOpnd,	---	20348	MSA128WOpnd, MSA128WOpnd,	---
20349	/* GINVI */	---	20349	/* GINVI */	---
20350	GPR32Opnd,	---	20350	GPR32Opnd,	---
20351	/* GINVI_MMR6 */	---	20351	/* GINVI_MMR6 */	---
20352	GPR32Opnd,	---	20352	GPR32Opnd,	---
20353	/* GINVT */	---	20353	/* GINVT */	---
20354	GPR32Opnd, uimm2,	---	20354	GPR32Opnd, uimm2,	---
20355	/* GINVT_MMR6 */	---	20355	/* GINVT_MMR6 */	---
20356	GPR32Opnd, uimm2,	---	20356	GPR32Opnd, uimm2,	---
20357	/* HADD_S_D */	---	20357	/* HADD_S_D */	---
20358	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	20358	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
20359	/* HADD_S_H */	---	20359	/* HADD_S_H */	---
20360	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	20360	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
20361	/* HADD_S_W */	---	20361	/* HADD_S_W */	---
20362	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	20362	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
20363	/* HADD_U_D */	---	20363	/* HADD_U_D */	---
20364	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	20364	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
20365	/* HADD_U_H */	---	20365	/* HADD_U_H */	---
20366	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	20366	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
20367	/* HADD_U_W */	---	20367	/* HADD_U_W */	---
20368	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	20368	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
20369	/* HSUB_S_D */	---	20369	/* HSUB_S_D */	---
20370	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	20370	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
20371	/* HSUB_S_H */	---	20371	/* HSUB_S_H */	---
20372	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	20372	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
20373	/* HSUB_S_W */	---	20373	/* HSUB_S_W */	---
20374	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	20374	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
20375	/* HSUB_U_D */	---	20375	/* HSUB_U_D */	---
20376	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---	20376	MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,	---
20377	/* HSUB_U_H */	---	20377	/* HSUB_U_H */	---
20378	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---	20378	MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,	---
20379	/* HSUB_U_W */	---	20379	/* HSUB_U_W */	---
20380	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---	20380	MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,	---
20381	/* HYPCALL */	---	20381	/* HYPCALL */	---
20382	uimm10,	---	20382	uimm10,	---
20383	/* HYPCALL_MM */	---	20383	/* HYPCALL_MM */	---
20384	uimm10,	---	20384	uimm10,	---
20385	/* ILVEV_B */	---	20385	/* ILVEV_B */	---
20386	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20386	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20387	/* ILVEV_D */	---	20387	/* ILVEV_D */	---
20388	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20388	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20389	/* ILVEV_H */	---	20389	/* ILVEV_H */	---
20390	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20390	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20391	/* ILVEV_W */	---	20391	/* ILVEV_W */	---
20392	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20392	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20393	/* ILVL_B */	---	20393	/* ILVL_B */	---
20394	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20394	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20395	/* ILVL_D */	---	20395	/* ILVL_D */	---
20396	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20396	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20397	/* ILVL_H */	---	20397	/* ILVL_H */	---
20398	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20398	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20399	/* ILVL_W */	---	20399	/* ILVL_W */	---
20400	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20400	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20401	/* ILVOD_B */	---	20401	/* ILVOD_B */	---
20402	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20402	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20403	/* ILVOD_D */	---	20403	/* ILVOD_D */	---
20404	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20404	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20405	/* ILVOD_H */	---	20405	/* ILVOD_H */	---
20406	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20406	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20407	/* ILVOD_W */	---	20407	/* ILVOD_W */	---
20408	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20408	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20409	/* ILVR_B */	---	20409	/* ILVR_B */	---
20410	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20410	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20411	/* ILVR_D */	---	20411	/* ILVR_D */	---
20412	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20412	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20413	/* ILVR_H */	---	20413	/* ILVR_H */	---
20414	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20414	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20415	/* ILVR_W */	---	20415	/* ILVR_W */	---
20416	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20416	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20417	/* INS */	---	20417	/* INS */	---
20418	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---	20418	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---
20419	/* INSERT_B */	---	20419	/* INSERT_B */	---
20420	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,	---	20420	MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,	---
20421	/* INSERT_D */	---	20421	/* INSERT_D */	---
20422	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,	---	20422	MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,	---
20423	/* INSERT_H */	---	20423	/* INSERT_H */	---
20424	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,	---	20424	MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,	---
20425	/* INSERT_W */	---	20425	/* INSERT_W */	---
20426	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,	---	20426	MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,	---
20427	/* INSV */	---	20427	/* INSV */	---
20428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	20428	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
20429	/* INSVE_B */	---	20429	/* INSVE_B */	---
20430	MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,	---	20430	MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,	---
20431	/* INSVE_D */	---	20431	/* INSVE_D */	---
20432	MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,	---	20432	MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,	---
20433	/* INSVE_H */	---	20433	/* INSVE_H */	---
20434	MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,	---	20434	MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,	---
20435	/* INSVE_W */	---	20435	/* INSVE_W */	---
20436	MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,	---	20436	MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,	---
20437	/* INSV_MM */	---	20437	/* INSV_MM */	---
20438	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	20438	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
20439	/* INS_MM */	---	20439	/* INS_MM */	---
20440	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---	20440	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---
20441	/* INS_MMR6 */	---	20441	/* INS_MMR6 */	---
20442	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---	20442	GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,	---
20443	/* J */	---	20443	/* J */	---
20444	jmptarget,	---	20444	jmptarget,	---
20445	/* JAL */	---	20445	/* JAL */	---
20446	calltarget,	---	20446	calltarget,	---
20447	/* JALR */	---	20447	/* JALR */	---
20448	GPR32Opnd, GPR32Opnd,	---	20448	GPR32Opnd, GPR32Opnd,	---
20449	/* JALR16_MM */	---	20449	/* JALR16_MM */	---
20450	GPR32Opnd,	---	20450	GPR32Opnd,	---
20451	/* JALR64 */	---	20451	/* JALR64 */	---
20452	GPR64Opnd, GPR64Opnd,	---	20452	GPR64Opnd, GPR64Opnd,	---
20453	/* JALRC16_MMR6 */	---	20453	/* JALRC16_MMR6 */	---
20454	GPR32Opnd,	---	20454	GPR32Opnd,	---
20455	/* JALRC_HB_MMR6 */	---	20455	/* JALRC_HB_MMR6 */	---
20456	GPR32Opnd, GPR32Opnd,	---	20456	GPR32Opnd, GPR32Opnd,	---
20457	/* JALRC_MMR6 */	---	20457	/* JALRC_MMR6 */	---
20458	GPR32Opnd, GPR32Opnd,	---	20458	GPR32Opnd, GPR32Opnd,	---
20459	/* JALRS16_MM */	---	20459	/* JALRS16_MM */	---
20460	GPR32Opnd,	---	20460	GPR32Opnd,	---
20461	/* JALRS_MM */	---	20461	/* JALRS_MM */	---
20462	GPR32Opnd, GPR32Opnd,	---	20462	GPR32Opnd, GPR32Opnd,	---
20463	/* JALR_HB */	---	20463	/* JALR_HB */	---
20464	GPR32Opnd, GPR32Opnd,	---	20464	GPR32Opnd, GPR32Opnd,	---
20465	/* JALR_HB64 */	---	20465	/* JALR_HB64 */	---
20466	GPR64Opnd, GPR64Opnd,	---	20466	GPR64Opnd, GPR64Opnd,	---
20467	/* JALR_MM */	---	20467	/* JALR_MM */	---
20468	GPR32Opnd, GPR32Opnd,	---	20468	GPR32Opnd, GPR32Opnd,	---
20469	/* JALS_MM */	---	20469	/* JALS_MM */	---
20470	calltarget_mm,	---	20470	calltarget_mm,	---
20471	/* JALX */	---	20471	/* JALX */	---
20472	calltarget,	---	20472	calltarget,	---
20473	/* JALX_MM */	---	20473	/* JALX_MM */	---
20474	calltarget,	---	20474	calltarget,	---
20475	/* JAL_MM */	---	20475	/* JAL_MM */	---
20476	calltarget_mm,	---	20476	calltarget_mm,	---
20477	/* JIALC */	---	20477	/* JIALC */	---
20478	GPR32Opnd, calloffset16,	---	20478	GPR32Opnd, calloffset16,	---
20479	/* JIALC64 */	---	20479	/* JIALC64 */	---
20480	GPR64Opnd, calloffset16,	---	20480	GPR64Opnd, calloffset16,	---
20481	/* JIALC_MMR6 */	---	20481	/* JIALC_MMR6 */	---
20482	GPR32Opnd, calloffset16,	---	20482	GPR32Opnd, calloffset16,	---
20483	/* JIC */	---	20483	/* JIC */	---
20484	GPR32Opnd, jmpoffset16,	---	20484	GPR32Opnd, jmpoffset16,	---
20485	/* JIC64 */	---	20485	/* JIC64 */	---
20486	GPR64Opnd, jmpoffset16,	---	20486	GPR64Opnd, jmpoffset16,	---
20487	/* JIC_MMR6 */	---	20487	/* JIC_MMR6 */	---
20488	GPR32Opnd, jmpoffset16,	---	20488	GPR32Opnd, jmpoffset16,	---
20489	/* JR */	---	20489	/* JR */	---
20490	GPR32Opnd,	---	20490	GPR32Opnd,	---
20491	/* JR16_MM */	---	20491	/* JR16_MM */	---
20492	GPR32Opnd,	---	20492	GPR32Opnd,	---
20493	/* JR64 */	---	20493	/* JR64 */	---
20494	GPR64Opnd,	---	20494	GPR64Opnd,	---
20495	/* JRADDIUSP */	---	20495	/* JRADDIUSP */	---
20496	uimm5_lsl2,	---	20496	uimm5_lsl2,	---
20497	/* JRC16_MM */	---	20497	/* JRC16_MM */	---
20498	GPR32Opnd,	---	20498	GPR32Opnd,	---
20499	/* JRC16_MMR6 */	---	20499	/* JRC16_MMR6 */	---
20500	GPR32Opnd,	---	20500	GPR32Opnd,	---
20501	/* JRCADDIUSP_MMR6 */	---	20501	/* JRCADDIUSP_MMR6 */	---
20502	uimm5_lsl2,	---	20502	uimm5_lsl2,	---
20503	/* JR_HB */	---	20503	/* JR_HB */	---
20504	GPR32Opnd,	---	20504	GPR32Opnd,	---
20505	/* JR_HB64 */	---	20505	/* JR_HB64 */	---
20506	GPR64Opnd,	---	20506	GPR64Opnd,	---
20507	/* JR_HB64_R6 */	---	20507	/* JR_HB64_R6 */	---
20508	GPR64Opnd,	---	20508	GPR64Opnd,	---
20509	/* JR_HB_R6 */	---	20509	/* JR_HB_R6 */	---
20510	GPR32Opnd,	---	20510	GPR32Opnd,	---
20511	/* JR_MM */	---	20511	/* JR_MM */	---
20512	GPR32Opnd,	---	20512	GPR32Opnd,	---
20513	/* J_MM */	---	20513	/* J_MM */	---
20514	jmptarget_mm,	---	20514	jmptarget_mm,	---
20515	/* Jal16 */	---	20515	/* Jal16 */	---
20516	uimm26,	---	20516	uimm26,	---
20517	/* JalB16 */	---	20517	/* JalB16 */	---
20518	uimm26,	---	20518	uimm26,	---
20519	/* JrRa16 */	---	20519	/* JrRa16 */	---
20520	/* JrcRa16 */	---	20520	/* JrcRa16 */	---
20521	/* JrcRx16 */	---	20521	/* JrcRx16 */	---
20522	CPU16Regs,	---	20522	CPU16Regs,	---
20523	/* JumpLinkReg16 */	---	20523	/* JumpLinkReg16 */	---
20524	CPU16Regs,	---	20524	CPU16Regs,	---
20525	/* LB */	---	20525	/* LB */	---
20526	GPR32Opnd, -1, simm16,	---	20526	GPR32Opnd, -1, simm16,	---
20527	/* LB64 */	---	20527	/* LB64 */	---
20528	GPR64Opnd, -1, simm16,	---	20528	GPR64Opnd, -1, simm16,	---
20529	/* LBE */	---	20529	/* LBE */	---
20530	GPR32Opnd, -1, simm9,	---	20530	GPR32Opnd, -1, simm9,	---
20531	/* LBE_MM */	---	20531	/* LBE_MM */	---
20532	GPR32Opnd, -1, simm16,	---	20532	GPR32Opnd, -1, simm16,	---
20533	/* LBU16_MM */	---	20533	/* LBU16_MM */	---
20534	GPRMM16Opnd, -1, simm4,	---	20534	GPRMM16Opnd, -1, simm4,	---
20535	/* LBUX */	---	20535	/* LBUX */	---
20536	GPR32Opnd, -1, -1,	---	20536	GPR32Opnd, -1, -1,	---
20537	/* LBUX_MM */	---	20537	/* LBUX_MM */	---
20538	GPR32Opnd, -1, -1,	---	20538	GPR32Opnd, -1, -1,	---
20539	/* LBU_MMR6 */	---	20539	/* LBU_MMR6 */	---
20540	GPR32Opnd, -1, simm16,	---	20540	GPR32Opnd, -1, simm16,	---
20541	/* LB_MM */	---	20541	/* LB_MM */	---
20542	GPR32Opnd, -1, simm16,	---	20542	GPR32Opnd, -1, simm16,	---
20543	/* LB_MMR6 */	---	20543	/* LB_MMR6 */	---
20544	GPR32Opnd, -1, simm16,	---	20544	GPR32Opnd, -1, simm16,	---
20545	/* LBu */	---	20545	/* LBu */	---
20546	GPR32Opnd, -1, simm16,	---	20546	GPR32Opnd, -1, simm16,	---
20547	/* LBu64 */	---	20547	/* LBu64 */	---
20548	GPR64Opnd, -1, simm16,	---	20548	GPR64Opnd, -1, simm16,	---
20549	/* LBuE */	---	20549	/* LBuE */	---
20550	GPR32Opnd, -1, simm9,	---	20550	GPR32Opnd, -1, simm9,	---
20551	/* LBuE_MM */	---	20551	/* LBuE_MM */	---
20552	GPR32Opnd, -1, simm16,	---	20552	GPR32Opnd, -1, simm16,	---
20553	/* LBu_MM */	---	20553	/* LBu_MM */	---
20554	GPR32Opnd, -1, simm16,	---	20554	GPR32Opnd, -1, simm16,	---
20555	/* LD */	---	20555	/* LD */	---
20556	GPR64Opnd, -1, simm16,	---	20556	GPR64Opnd, -1, simm16,	---
20557	/* LDC1 */	---	20557	/* LDC1 */	---
20558	AFGR64Opnd, -1, simm16,	---	20558	AFGR64Opnd, -1, simm16,	---
20559	/* LDC164 */	---	20559	/* LDC164 */	---
20560	FGR64Opnd, -1, simm16,	---	20560	FGR64Opnd, -1, simm16,	---
20561	/* LDC1_D64_MMR6 */	---	20561	/* LDC1_D64_MMR6 */	---
20562	FGR64Opnd, -1, simm16,	---	20562	FGR64Opnd, -1, simm16,	---
20563	/* LDC1_MM_D32 */	---	20563	/* LDC1_MM_D32 */	---
20564	AFGR64Opnd, -1, simm16,	---	20564	AFGR64Opnd, -1, simm16,	---
20565	/* LDC1_MM_D64 */	---	20565	/* LDC1_MM_D64 */	---
20566	FGR64Opnd, -1, simm16,	---	20566	FGR64Opnd, -1, simm16,	---
20567	/* LDC2 */	---	20567	/* LDC2 */	---
20568	COP2Opnd, -1, simm16,	---	20568	COP2Opnd, -1, simm16,	---
20569	/* LDC2_MMR6 */	---	20569	/* LDC2_MMR6 */	---
20570	COP2Opnd, GPR32, simm11,	---	20570	COP2Opnd, GPR32, simm11,	---
20571	/* LDC2_R6 */	---	20571	/* LDC2_R6 */	---
20572	COP2Opnd, -1, simm11,	---	20572	COP2Opnd, -1, simm11,	---
20573	/* LDC3 */	---	20573	/* LDC3 */	---
20574	COP3Opnd, -1, simm16,	---	20574	COP3Opnd, -1, simm16,	---
20575	/* LDI_B */	---	20575	/* LDI_B */	---
20576	MSA128BOpnd, vsplat_simm10,	---	20576	MSA128BOpnd, vsplat_simm10,	---
20577	/* LDI_D */	---	20577	/* LDI_D */	---
20578	MSA128DOpnd, vsplat_simm10,	---	20578	MSA128DOpnd, vsplat_simm10,	---
20579	/* LDI_H */	---	20579	/* LDI_H */	---
20580	MSA128HOpnd, vsplat_simm10,	---	20580	MSA128HOpnd, vsplat_simm10,	---
20581	/* LDI_W */	---	20581	/* LDI_W */	---
20582	MSA128WOpnd, vsplat_simm10,	---	20582	MSA128WOpnd, vsplat_simm10,	---
20583	/* LDL */	---	20583	/* LDL */	---
20584	GPR64Opnd, -1, simm16, GPR64Opnd,	---	20584	GPR64Opnd, -1, simm16, GPR64Opnd,	---
20585	/* LDPC */	---	20585	/* LDPC */	---
20586	GPR64Opnd, simm18_lsl3,	---	20586	GPR64Opnd, simm18_lsl3,	---
20587	/* LDR */	---	20587	/* LDR */	---
20588	GPR64Opnd, -1, simm16, GPR64Opnd,	---	20588	GPR64Opnd, -1, simm16, GPR64Opnd,	---
20589	/* LDXC1 */	---	20589	/* LDXC1 */	---
20590	AFGR64Opnd, -1, -1,	---	20590	AFGR64Opnd, -1, -1,	---
20591	/* LDXC164 */	---	20591	/* LDXC164 */	---
20592	FGR64Opnd, -1, -1,	---	20592	FGR64Opnd, -1, -1,	---
20593	/* LD_B */	---	20593	/* LD_B */	---
20594	MSA128BOpnd, -1, simm10,	---	20594	MSA128BOpnd, -1, simm10,	---
20595	/* LD_D */	---	20595	/* LD_D */	---
20596	MSA128DOpnd, -1, simm10_lsl3,	---	20596	MSA128DOpnd, -1, simm10_lsl3,	---
20597	/* LD_H */	---	20597	/* LD_H */	---
20598	MSA128HOpnd, -1, simm10_lsl1,	---	20598	MSA128HOpnd, -1, simm10_lsl1,	---
20599	/* LD_W */	---	20599	/* LD_W */	---
20600	MSA128WOpnd, -1, simm10_lsl2,	---	20600	MSA128WOpnd, -1, simm10_lsl2,	---
20601	/* LEA_ADDiu */	---	20601	/* LEA_ADDiu */	---
20602	GPR32Opnd, -1, simm16,	---	20602	GPR32Opnd, -1, simm16,	---
20603	/* LEA_ADDiu64 */	---	20603	/* LEA_ADDiu64 */	---
20604	GPR64Opnd, -1, simm16,	---	20604	GPR64Opnd, -1, simm16,	---
20605	/* LEA_ADDiu_MM */	---	20605	/* LEA_ADDiu_MM */	---
20606	GPR32Opnd, -1, simm16,	---	20606	GPR32Opnd, -1, simm16,	---
20607	/* LH */	---	20607	/* LH */	---
20608	GPR32Opnd, -1, simm16,	---	20608	GPR32Opnd, -1, simm16,	---
20609	/* LH64 */	---	20609	/* LH64 */	---
20610	GPR64Opnd, -1, simm16,	---	20610	GPR64Opnd, -1, simm16,	---
20611	/* LHE */	---	20611	/* LHE */	---
20612	GPR32Opnd, -1, simm9,	---	20612	GPR32Opnd, -1, simm9,	---
20613	/* LHE_MM */	---	20613	/* LHE_MM */	---
20614	GPR32Opnd, -1, simm9,	---	20614	GPR32Opnd, -1, simm9,	---
20615	/* LHU16_MM */	---	20615	/* LHU16_MM */	---
20616	GPRMM16Opnd, -1, simm4,	---	20616	GPRMM16Opnd, -1, simm4,	---
20617	/* LHX */	---	20617	/* LHX */	---
20618	GPR32Opnd, -1, -1,	---	20618	GPR32Opnd, -1, -1,	---
20619	/* LHX_MM */	---	20619	/* LHX_MM */	---
20620	GPR32Opnd, -1, -1,	---	20620	GPR32Opnd, -1, -1,	---
20621	/* LH_MM */	---	20621	/* LH_MM */	---
20622	GPR32Opnd, -1, simm16,	---	20622	GPR32Opnd, -1, simm16,	---
20623	/* LHu */	---	20623	/* LHu */	---
20624	GPR32Opnd, -1, simm16,	---	20624	GPR32Opnd, -1, simm16,	---
20625	/* LHu64 */	---	20625	/* LHu64 */	---
20626	GPR64Opnd, -1, simm16,	---	20626	GPR64Opnd, -1, simm16,	---
20627	/* LHuE */	---	20627	/* LHuE */	---
20628	GPR32Opnd, -1, simm9,	---	20628	GPR32Opnd, -1, simm9,	---
20629	/* LHuE_MM */	---	20629	/* LHuE_MM */	---
20630	GPR32Opnd, -1, simm9,	---	20630	GPR32Opnd, -1, simm9,	---
20631	/* LHu_MM */	---	20631	/* LHu_MM */	---
20632	GPR32Opnd, -1, simm16,	---	20632	GPR32Opnd, -1, simm16,	---
20633	/* LI16_MM */	---	20633	/* LI16_MM */	---
20634	GPRMM16Opnd, li16_imm,	---	20634	GPRMM16Opnd, li16_imm,	---
20635	/* LI16_MMR6 */	---	20635	/* LI16_MMR6 */	---
20636	GPRMM16Opnd, li16_imm,	---	20636	GPRMM16Opnd, li16_imm,	---
20637	/* LL */	---	20637	/* LL */	---
20638	GPR32Opnd, -1, simm16,	---	20638	GPR32Opnd, -1, simm16,	---
20639	/* LL64 */	---	20639	/* LL64 */	---
20640	GPR32Opnd, -1, simm16,	---	20640	GPR32Opnd, -1, simm16,	---
20641	/* LL64_R6 */	---	20641	/* LL64_R6 */	---
20642	GPR32Opnd, -1, simm9,	---	20642	GPR32Opnd, -1, simm9,	---
20643	/* LLD */	---	20643	/* LLD */	---
20644	GPR64Opnd, -1, simm16,	---	20644	GPR64Opnd, -1, simm16,	---
20645	/* LLD_R6 */	---	20645	/* LLD_R6 */	---
20646	GPR64Opnd, -1, simm9,	---	20646	GPR64Opnd, -1, simm9,	---
20647	/* LLE */	---	20647	/* LLE */	---
20648	GPR32Opnd, -1, simm9,	---	20648	GPR32Opnd, -1, simm9,	---
20649	/* LLE_MM */	---	20649	/* LLE_MM */	---
20650	GPR32Opnd, -1, simm9,	---	20650	GPR32Opnd, -1, simm9,	---
20651	/* LL_MM */	---	20651	/* LL_MM */	---
20652	GPR32Opnd, -1, simm12,	---	20652	GPR32Opnd, -1, simm12,	---
20653	/* LL_MMR6 */	---	20653	/* LL_MMR6 */	---
20654	GPR32Opnd, -1, simm9,	---	20654	GPR32Opnd, -1, simm9,	---
20655	/* LL_R6 */	---	20655	/* LL_R6 */	---
20656	GPR32Opnd, -1, simm9,	---	20656	GPR32Opnd, -1, simm9,	---
20657	/* LSA */	---	20657	/* LSA */	---
20658	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---	20658	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---
20659	/* LSA_MMR6 */	---	20659	/* LSA_MMR6 */	---
20660	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---	20660	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---
20661	/* LSA_R6 */	---	20661	/* LSA_R6 */	---
20662	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---	20662	GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,	---
20663	/* LUI_MMR6 */	---	20663	/* LUI_MMR6 */	---
20664	GPR32Opnd, uimm16,	---	20664	GPR32Opnd, uimm16,	---
20665	/* LUXC1 */	---	20665	/* LUXC1 */	---
20666	AFGR64Opnd, -1, -1,	---	20666	AFGR64Opnd, -1, -1,	---
20667	/* LUXC164 */	---	20667	/* LUXC164 */	---
20668	FGR64Opnd, -1, -1,	---	20668	FGR64Opnd, -1, -1,	---
20669	/* LUXC1_MM */	---	20669	/* LUXC1_MM */	---
20670	FGR64Opnd, -1, -1,	---	20670	FGR64Opnd, -1, -1,	---
20671	/* LUi */	---	20671	/* LUi */	---
20672	GPR32Opnd, uimm16_relaxed,	---	20672	GPR32Opnd, uimm16_relaxed,	---
20673	/* LUi64 */	---	20673	/* LUi64 */	---
20674	GPR64Opnd, uimm16_64_relaxed,	---	20674	GPR64Opnd, uimm16_64_relaxed,	---
20675	/* LUi_MM */	---	20675	/* LUi_MM */	---
20676	GPR32Opnd, uimm16_relaxed,	---	20676	GPR32Opnd, uimm16_relaxed,	---
20677	/* LW */	---	20677	/* LW */	---
20678	GPR32Opnd, -1, simm16,	---	20678	GPR32Opnd, -1, simm16,	---
20679	/* LW16_MM */	---	20679	/* LW16_MM */	---
20680	GPRMM16Opnd, -1, simm4,	---	20680	GPRMM16Opnd, -1, simm4,	---
20681	/* LW64 */	---	20681	/* LW64 */	---
20682	GPR64Opnd, -1, simm16,	---	20682	GPR64Opnd, -1, simm16,	---
20683	/* LWC1 */	---	20683	/* LWC1 */	---
20684	FGR32Opnd, -1, simm16,	---	20684	FGR32Opnd, -1, simm16,	---
20685	/* LWC1_MM */	---	20685	/* LWC1_MM */	---
20686	FGR32Opnd, -1, simm16,	---	20686	FGR32Opnd, -1, simm16,	---
20687	/* LWC2 */	---	20687	/* LWC2 */	---
20688	COP2Opnd, -1, simm16,	---	20688	COP2Opnd, -1, simm16,	---
20689	/* LWC2_MMR6 */	---	20689	/* LWC2_MMR6 */	---
20690	COP2Opnd, GPR32, simm11,	---	20690	COP2Opnd, GPR32, simm11,	---
20691	/* LWC2_R6 */	---	20691	/* LWC2_R6 */	---
20692	COP2Opnd, -1, simm11,	---	20692	COP2Opnd, -1, simm11,	---
20693	/* LWC3 */	---	20693	/* LWC3 */	---
20694	COP3Opnd, -1, simm16,	---	20694	COP3Opnd, -1, simm16,	---
20695	/* LWDSP */	---	20695	/* LWDSP */	---
20696	DSPROpnd, -1, simm16,	---	20696	DSPROpnd, -1, simm16,	---
20697	/* LWDSP_MM */	---	20697	/* LWDSP_MM */	---
20698	DSPROpnd, -1, simm16,	---	20698	DSPROpnd, -1, simm16,	---
20699	/* LWE */	---	20699	/* LWE */	---
20700	GPR32Opnd, -1, simm9,	---	20700	GPR32Opnd, -1, simm9,	---
20701	/* LWE_MM */	---	20701	/* LWE_MM */	---
20702	GPR32Opnd, -1, simm9,	---	20702	GPR32Opnd, -1, simm9,	---
20703	/* LWGP_MM */	---	20703	/* LWGP_MM */	---
20704	GPRMM16Opnd, -1, simm7_lsl2,	---	20704	GPRMM16Opnd, -1, simm7_lsl2,	---
20705	/* LWL */	---	20705	/* LWL */	---
20706	GPR32Opnd, -1, simm16, GPR32Opnd,	---	20706	GPR32Opnd, -1, simm16, GPR32Opnd,	---
20707	/* LWL64 */	---	20707	/* LWL64 */	---
20708	GPR64Opnd, -1, simm16, GPR64Opnd,	---	20708	GPR64Opnd, -1, simm16, GPR64Opnd,	---
20709	/* LWLE */	---	20709	/* LWLE */	---
20710	GPR32Opnd, -1, simm9, GPR32Opnd,	---	20710	GPR32Opnd, -1, simm9, GPR32Opnd,	---
20711	/* LWLE_MM */	---	20711	/* LWLE_MM */	---
20712	GPR32Opnd, -1, simm9, GPR32Opnd,	---	20712	GPR32Opnd, -1, simm9, GPR32Opnd,	---
20713	/* LWL_MM */	---	20713	/* LWL_MM */	---
20714	GPR32Opnd, -1, simm12, GPR32Opnd,	---	20714	GPR32Opnd, -1, simm12, GPR32Opnd,	---
20715	/* LWM16_MM */	---	20715	/* LWM16_MM */	---
20716	reglist16, -1, uimm8,	---	20716	reglist16, -1, uimm8,	---
20717	/* LWM16_MMR6 */	---	20717	/* LWM16_MMR6 */	---
20718	reglist16, -1, uimm8,	---	20718	reglist16, -1, uimm8,	---
20719	/* LWM32_MM */	---	20719	/* LWM32_MM */	---
20720	reglist, -1, simm12,	---	20720	reglist, -1, simm12,	---
20721	/* LWPC */	---	20721	/* LWPC */	---
20722	GPR32Opnd, simm19_lsl2,	---	20722	GPR32Opnd, simm19_lsl2,	---
20723	/* LWPC_MMR6 */	---	20723	/* LWPC_MMR6 */	---
20724	GPR32Opnd, simm19_lsl2,	---	20724	GPR32Opnd, simm19_lsl2,	---
20725	/* LWP_MM */	---	20725	/* LWP_MM */	---
20726	GPR32Opnd, GPR32Opnd, -1, simm12,	---	20726	GPR32Opnd, GPR32Opnd, -1, simm12,	---
20727	/* LWR */	---	20727	/* LWR */	---
20728	GPR32Opnd, -1, simm16, GPR32Opnd,	---	20728	GPR32Opnd, -1, simm16, GPR32Opnd,	---
20729	/* LWR64 */	---	20729	/* LWR64 */	---
20730	GPR64Opnd, -1, simm16, GPR64Opnd,	---	20730	GPR64Opnd, -1, simm16, GPR64Opnd,	---
20731	/* LWRE */	---	20731	/* LWRE */	---
20732	GPR32Opnd, -1, simm9, GPR32Opnd,	---	20732	GPR32Opnd, -1, simm9, GPR32Opnd,	---
20733	/* LWRE_MM */	---	20733	/* LWRE_MM */	---
20734	GPR32Opnd, -1, simm9, GPR32Opnd,	---	20734	GPR32Opnd, -1, simm9, GPR32Opnd,	---
20735	/* LWR_MM */	---	20735	/* LWR_MM */	---
20736	GPR32Opnd, -1, simm12, GPR32Opnd,	---	20736	GPR32Opnd, -1, simm12, GPR32Opnd,	---
20737	/* LWSP_MM */	---	20737	/* LWSP_MM */	---
20738	GPR32Opnd, -1, simm5,	---	20738	GPR32Opnd, -1, simm5,	---
20739	/* LWUPC */	---	20739	/* LWUPC */	---
20740	GPR32Opnd, simm19_lsl2,	---	20740	GPR32Opnd, simm19_lsl2,	---
20741	/* LWU_MM */	---	20741	/* LWU_MM */	---
20742	GPR32Opnd, -1, simm12,	---	20742	GPR32Opnd, -1, simm12,	---
20743	/* LWX */	---	20743	/* LWX */	---
20744	GPR32Opnd, -1, -1,	---	20744	GPR32Opnd, -1, -1,	---
20745	/* LWXC1 */	---	20745	/* LWXC1 */	---
20746	FGR32Opnd, -1, -1,	---	20746	FGR32Opnd, -1, -1,	---
20747	/* LWXC1_MM */	---	20747	/* LWXC1_MM */	---
20748	FGR32Opnd, -1, -1,	---	20748	FGR32Opnd, -1, -1,	---
20749	/* LWXS_MM */	---	20749	/* LWXS_MM */	---
20750	GPR32Opnd, -1, -1,	---	20750	GPR32Opnd, -1, -1,	---
20751	/* LWX_MM */	---	20751	/* LWX_MM */	---
20752	GPR32Opnd, -1, -1,	---	20752	GPR32Opnd, -1, -1,	---
20753	/* LW_MM */	---	20753	/* LW_MM */	---
20754	GPR32Opnd, -1, simm16,	---	20754	GPR32Opnd, -1, simm16,	---
20755	/* LW_MMR6 */	---	20755	/* LW_MMR6 */	---
20756	GPR32Opnd, -1, simm16,	---	20756	GPR32Opnd, -1, simm16,	---
20757	/* LWu */	---	20757	/* LWu */	---
20758	GPR64Opnd, -1, simm16,	---	20758	GPR64Opnd, -1, simm16,	---
20759	/* LbRxRyOffMemX16 */	---	20759	/* LbRxRyOffMemX16 */	---
20760	CPU16Regs, CPU16Regs, simm16,	---	20760	CPU16Regs, CPU16Regs, simm16,	---
20761	/* LbuRxRyOffMemX16 */	---	20761	/* LbuRxRyOffMemX16 */	---
20762	CPU16Regs, CPU16Regs, simm16,	---	20762	CPU16Regs, CPU16Regs, simm16,	---
20763	/* LhRxRyOffMemX16 */	---	20763	/* LhRxRyOffMemX16 */	---
20764	CPU16Regs, CPU16Regs, simm16,	---	20764	CPU16Regs, CPU16Regs, simm16,	---
20765	/* LhuRxRyOffMemX16 */	---	20765	/* LhuRxRyOffMemX16 */	---
20766	CPU16Regs, CPU16Regs, simm16,	---	20766	CPU16Regs, CPU16Regs, simm16,	---
20767	/* LiRxImm16 */	---	20767	/* LiRxImm16 */	---
20768	CPU16Regs, simm16,	---	20768	CPU16Regs, simm16,	---
20769	/* LiRxImmAlignX16 */	---	20769	/* LiRxImmAlignX16 */	---
20770	CPU16Regs, simm16,	---	20770	CPU16Regs, simm16,	---
20771	/* LiRxImmX16 */	---	20771	/* LiRxImmX16 */	---
20772	CPU16Regs, simm16,	---	20772	CPU16Regs, simm16,	---
20773	/* LwRxPcTcp16 */	---	20773	/* LwRxPcTcp16 */	---
20774	CPU16Regs, pcrel16, i32imm,	---	20774	CPU16Regs, pcrel16, i32imm,	---
20775	/* LwRxPcTcpX16 */	---	20775	/* LwRxPcTcpX16 */	---
20776	CPU16Regs, pcrel16, i32imm,	---	20776	CPU16Regs, pcrel16, i32imm,	---
20777	/* LwRxRyOffMemX16 */	---	20777	/* LwRxRyOffMemX16 */	---
20778	CPU16Regs, CPU16Regs, simm16,	---	20778	CPU16Regs, CPU16Regs, simm16,	---
20779	/* LwRxSpImmX16 */	---	20779	/* LwRxSpImmX16 */	---
20780	CPU16Regs, CPU16RegsPlusSP, simm16,	---	20780	CPU16Regs, CPU16RegsPlusSP, simm16,	---
20781	/* MADD */	---	20781	/* MADD */	---
20782	GPR32Opnd, GPR32Opnd,	---	20782	GPR32Opnd, GPR32Opnd,	---
20783	/* MADDF_D */	---	20783	/* MADDF_D */	---
20784	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20784	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20785	/* MADDF_D_MMR6 */	---	20785	/* MADDF_D_MMR6 */	---
20786	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20786	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20787	/* MADDF_S */	---	20787	/* MADDF_S */	---
20788	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20788	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20789	/* MADDF_S_MMR6 */	---	20789	/* MADDF_S_MMR6 */	---
20790	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20790	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20791	/* MADDR_Q_H */	---	20791	/* MADDR_Q_H */	---
20792	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20792	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20793	/* MADDR_Q_W */	---	20793	/* MADDR_Q_W */	---
20794	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20794	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20795	/* MADDU */	---	20795	/* MADDU */	---
20796	GPR32Opnd, GPR32Opnd,	---	20796	GPR32Opnd, GPR32Opnd,	---
20797	/* MADDU_DSP */	---	20797	/* MADDU_DSP */	---
20798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20798	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20799	/* MADDU_DSP_MM */	---	20799	/* MADDU_DSP_MM */	---
20800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20800	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20801	/* MADDU_MM */	---	20801	/* MADDU_MM */	---
20802	GPR32Opnd, GPR32Opnd,	---	20802	GPR32Opnd, GPR32Opnd,	---
20803	/* MADDV_B */	---	20803	/* MADDV_B */	---
20804	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20804	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20805	/* MADDV_D */	---	20805	/* MADDV_D */	---
20806	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20806	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20807	/* MADDV_H */	---	20807	/* MADDV_H */	---
20808	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20808	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20809	/* MADDV_W */	---	20809	/* MADDV_W */	---
20810	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20810	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20811	/* MADD_D32 */	---	20811	/* MADD_D32 */	---
20812	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20812	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20813	/* MADD_D32_MM */	---	20813	/* MADD_D32_MM */	---
20814	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	20814	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
20815	/* MADD_D64 */	---	20815	/* MADD_D64 */	---
20816	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20816	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20817	/* MADD_DSP */	---	20817	/* MADD_DSP */	---
20818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20818	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20819	/* MADD_DSP_MM */	---	20819	/* MADD_DSP_MM */	---
20820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20820	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20821	/* MADD_MM */	---	20821	/* MADD_MM */	---
20822	GPR32Opnd, GPR32Opnd,	---	20822	GPR32Opnd, GPR32Opnd,	---
20823	/* MADD_Q_H */	---	20823	/* MADD_Q_H */	---
20824	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20824	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20825	/* MADD_Q_W */	---	20825	/* MADD_Q_W */	---
20826	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20826	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20827	/* MADD_S */	---	20827	/* MADD_S */	---
20828	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20828	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20829	/* MADD_S_MM */	---	20829	/* MADD_S_MM */	---
20830	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20830	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20831	/* MAQ_SA_W_PHL */	---	20831	/* MAQ_SA_W_PHL */	---
20832	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20832	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20833	/* MAQ_SA_W_PHL_MM */	---	20833	/* MAQ_SA_W_PHL_MM */	---
20834	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20834	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20835	/* MAQ_SA_W_PHR */	---	20835	/* MAQ_SA_W_PHR */	---
20836	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20836	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20837	/* MAQ_SA_W_PHR_MM */	---	20837	/* MAQ_SA_W_PHR_MM */	---
20838	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20838	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20839	/* MAQ_S_W_PHL */	---	20839	/* MAQ_S_W_PHL */	---
20840	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20840	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20841	/* MAQ_S_W_PHL_MM */	---	20841	/* MAQ_S_W_PHL_MM */	---
20842	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20842	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20843	/* MAQ_S_W_PHR */	---	20843	/* MAQ_S_W_PHR */	---
20844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20844	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20845	/* MAQ_S_W_PHR_MM */	---	20845	/* MAQ_S_W_PHR_MM */	---
20846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	20846	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
20847	/* MAXA_D */	---	20847	/* MAXA_D */	---
20848	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20848	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20849	/* MAXA_D_MMR6 */	---	20849	/* MAXA_D_MMR6 */	---
20850	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20850	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20851	/* MAXA_S */	---	20851	/* MAXA_S */	---
20852	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20852	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20853	/* MAXA_S_MMR6 */	---	20853	/* MAXA_S_MMR6 */	---
20854	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20854	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20855	/* MAXI_S_B */	---	20855	/* MAXI_S_B */	---
20856	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---	20856	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---
20857	/* MAXI_S_D */	---	20857	/* MAXI_S_D */	---
20858	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---	20858	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---
20859	/* MAXI_S_H */	---	20859	/* MAXI_S_H */	---
20860	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---	20860	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---
20861	/* MAXI_S_W */	---	20861	/* MAXI_S_W */	---
20862	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---	20862	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---
20863	/* MAXI_U_B */	---	20863	/* MAXI_U_B */	---
20864	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	20864	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
20865	/* MAXI_U_D */	---	20865	/* MAXI_U_D */	---
20866	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	20866	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
20867	/* MAXI_U_H */	---	20867	/* MAXI_U_H */	---
20868	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	20868	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
20869	/* MAXI_U_W */	---	20869	/* MAXI_U_W */	---
20870	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	20870	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
20871	/* MAX_A_B */	---	20871	/* MAX_A_B */	---
20872	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20872	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20873	/* MAX_A_D */	---	20873	/* MAX_A_D */	---
20874	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20874	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20875	/* MAX_A_H */	---	20875	/* MAX_A_H */	---
20876	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20876	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20877	/* MAX_A_W */	---	20877	/* MAX_A_W */	---
20878	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20878	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20879	/* MAX_D */	---	20879	/* MAX_D */	---
20880	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20880	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20881	/* MAX_D_MMR6 */	---	20881	/* MAX_D_MMR6 */	---
20882	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20882	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20883	/* MAX_S */	---	20883	/* MAX_S */	---
20884	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20884	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20885	/* MAX_S_B */	---	20885	/* MAX_S_B */	---
20886	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20886	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20887	/* MAX_S_D */	---	20887	/* MAX_S_D */	---
20888	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20888	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20889	/* MAX_S_H */	---	20889	/* MAX_S_H */	---
20890	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20890	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20891	/* MAX_S_MMR6 */	---	20891	/* MAX_S_MMR6 */	---
20892	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20892	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20893	/* MAX_S_W */	---	20893	/* MAX_S_W */	---
20894	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20894	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20895	/* MAX_U_B */	---	20895	/* MAX_U_B */	---
20896	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20896	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20897	/* MAX_U_D */	---	20897	/* MAX_U_D */	---
20898	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20898	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20899	/* MAX_U_H */	---	20899	/* MAX_U_H */	---
20900	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20900	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20901	/* MAX_U_W */	---	20901	/* MAX_U_W */	---
20902	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20902	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20903	/* MFC0 */	---	20903	/* MFC0 */	---
20904	GPR32Opnd, COP0Opnd, uimm3,	---	20904	GPR32Opnd, COP0Opnd, uimm3,	---
20905	/* MFC0_MMR6 */	---	20905	/* MFC0_MMR6 */	---
20906	GPR32Opnd, COP0Opnd, uimm3,	---	20906	GPR32Opnd, COP0Opnd, uimm3,	---
20907	/* MFC1 */	---	20907	/* MFC1 */	---
20908	GPR32Opnd, FGR32Opnd,	---	20908	GPR32Opnd, FGR32Opnd,	---
20909	/* MFC1_D64 */	---	20909	/* MFC1_D64 */	---
20910	GPR32Opnd, FGR64Opnd,	---	20910	GPR32Opnd, FGR64Opnd,	---
20911	/* MFC1_MM */	---	20911	/* MFC1_MM */	---
20912	GPR32Opnd, FGR32Opnd,	---	20912	GPR32Opnd, FGR32Opnd,	---
20913	/* MFC1_MMR6 */	---	20913	/* MFC1_MMR6 */	---
20914	GPR32Opnd, FGR32Opnd,	---	20914	GPR32Opnd, FGR32Opnd,	---
20915	/* MFC2 */	---	20915	/* MFC2 */	---
20916	GPR32Opnd, COP2Opnd, uimm3,	---	20916	GPR32Opnd, COP2Opnd, uimm3,	---
20917	/* MFC2_MMR6 */	---	20917	/* MFC2_MMR6 */	---
20918	GPR32Opnd, COP2Opnd,	---	20918	GPR32Opnd, COP2Opnd,	---
20919	/* MFGC0 */	---	20919	/* MFGC0 */	---
20920	GPR32Opnd, COP0Opnd, uimm3,	---	20920	GPR32Opnd, COP0Opnd, uimm3,	---
20921	/* MFGC0_MM */	---	20921	/* MFGC0_MM */	---
20922	GPR32Opnd, COP0Opnd, uimm3,	---	20922	GPR32Opnd, COP0Opnd, uimm3,	---
20923	/* MFHC0_MMR6 */	---	20923	/* MFHC0_MMR6 */	---
20924	GPR32Opnd, COP0Opnd, uimm3,	---	20924	GPR32Opnd, COP0Opnd, uimm3,	---
20925	/* MFHC1_D32 */	---	20925	/* MFHC1_D32 */	---
20926	GPR32Opnd, AFGR64Opnd,	---	20926	GPR32Opnd, AFGR64Opnd,	---
20927	/* MFHC1_D32_MM */	---	20927	/* MFHC1_D32_MM */	---
20928	GPR32Opnd, AFGR64Opnd,	---	20928	GPR32Opnd, AFGR64Opnd,	---
20929	/* MFHC1_D64 */	---	20929	/* MFHC1_D64 */	---
20930	GPR32Opnd, FGR64Opnd,	---	20930	GPR32Opnd, FGR64Opnd,	---
20931	/* MFHC1_D64_MM */	---	20931	/* MFHC1_D64_MM */	---
20932	GPR32Opnd, FGR64Opnd,	---	20932	GPR32Opnd, FGR64Opnd,	---
20933	/* MFHC2_MMR6 */	---	20933	/* MFHC2_MMR6 */	---
20934	GPR32Opnd, COP2Opnd,	---	20934	GPR32Opnd, COP2Opnd,	---
20935	/* MFHGC0 */	---	20935	/* MFHGC0 */	---
20936	GPR32Opnd, COP0Opnd, uimm3,	---	20936	GPR32Opnd, COP0Opnd, uimm3,	---
20937	/* MFHGC0_MM */	---	20937	/* MFHGC0_MM */	---
20938	GPR32Opnd, COP0Opnd, uimm3,	---	20938	GPR32Opnd, COP0Opnd, uimm3,	---
20939	/* MFHI */	---	20939	/* MFHI */	---
20940	GPR32Opnd,	---	20940	GPR32Opnd,	---
20941	/* MFHI16_MM */	---	20941	/* MFHI16_MM */	---
20942	GPR32Opnd,	---	20942	GPR32Opnd,	---
20943	/* MFHI64 */	---	20943	/* MFHI64 */	---
20944	GPR64Opnd,	---	20944	GPR64Opnd,	---
20945	/* MFHI_DSP */	---	20945	/* MFHI_DSP */	---
20946	GPR32Opnd, ACC64DSPOpnd,	---	20946	GPR32Opnd, ACC64DSPOpnd,	---
20947	/* MFHI_DSP_MM */	---	20947	/* MFHI_DSP_MM */	---
20948	GPR32Opnd, ACC64DSPOpnd,	---	20948	GPR32Opnd, ACC64DSPOpnd,	---
20949	/* MFHI_MM */	---	20949	/* MFHI_MM */	---
20950	GPR32Opnd,	---	20950	GPR32Opnd,	---
20951	/* MFLO */	---	20951	/* MFLO */	---
20952	GPR32Opnd,	---	20952	GPR32Opnd,	---
20953	/* MFLO16_MM */	---	20953	/* MFLO16_MM */	---
20954	GPR32Opnd,	---	20954	GPR32Opnd,	---
20955	/* MFLO64 */	---	20955	/* MFLO64 */	---
20956	GPR64Opnd,	---	20956	GPR64Opnd,	---
20957	/* MFLO_DSP */	---	20957	/* MFLO_DSP */	---
20958	GPR32Opnd, ACC64DSPOpnd,	---	20958	GPR32Opnd, ACC64DSPOpnd,	---
20959	/* MFLO_DSP_MM */	---	20959	/* MFLO_DSP_MM */	---
20960	GPR32Opnd, ACC64DSPOpnd,	---	20960	GPR32Opnd, ACC64DSPOpnd,	---
20961	/* MFLO_MM */	---	20961	/* MFLO_MM */	---
20962	GPR32Opnd,	---	20962	GPR32Opnd,	---
20963	/* MFTR */	---	20963	/* MFTR */	---
20964	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	---	20964	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	---
20965	/* MINA_D */	---	20965	/* MINA_D */	---
20966	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20966	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20967	/* MINA_D_MMR6 */	---	20967	/* MINA_D_MMR6 */	---
20968	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20968	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20969	/* MINA_S */	---	20969	/* MINA_S */	---
20970	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20970	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20971	/* MINA_S_MMR6 */	---	20971	/* MINA_S_MMR6 */	---
20972	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	20972	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
20973	/* MINI_S_B */	---	20973	/* MINI_S_B */	---
20974	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---	20974	MSA128BOpnd, MSA128BOpnd, vsplat_simm5,	---
20975	/* MINI_S_D */	---	20975	/* MINI_S_D */	---
20976	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---	20976	MSA128DOpnd, MSA128DOpnd, vsplat_simm5,	---
20977	/* MINI_S_H */	---	20977	/* MINI_S_H */	---
20978	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---	20978	MSA128HOpnd, MSA128HOpnd, vsplat_simm5,	---
20979	/* MINI_S_W */	---	20979	/* MINI_S_W */	---
20980	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---	20980	MSA128WOpnd, MSA128WOpnd, vsplat_simm5,	---
20981	/* MINI_U_B */	---	20981	/* MINI_U_B */	---
20982	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	20982	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
20983	/* MINI_U_D */	---	20983	/* MINI_U_D */	---
20984	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	20984	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
20985	/* MINI_U_H */	---	20985	/* MINI_U_H */	---
20986	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	20986	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
20987	/* MINI_U_W */	---	20987	/* MINI_U_W */	---
20988	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	20988	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
20989	/* MIN_A_B */	---	20989	/* MIN_A_B */	---
20990	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	20990	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
20991	/* MIN_A_D */	---	20991	/* MIN_A_D */	---
20992	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	20992	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
20993	/* MIN_A_H */	---	20993	/* MIN_A_H */	---
20994	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	20994	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
20995	/* MIN_A_W */	---	20995	/* MIN_A_W */	---
20996	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	20996	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
20997	/* MIN_D */	---	20997	/* MIN_D */	---
20998	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	20998	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
20999	/* MIN_D_MMR6 */	---	20999	/* MIN_D_MMR6 */	---
21000	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21000	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21001	/* MIN_S */	---	21001	/* MIN_S */	---
21002	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21002	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21003	/* MIN_S_B */	---	21003	/* MIN_S_B */	---
21004	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21004	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21005	/* MIN_S_D */	---	21005	/* MIN_S_D */	---
21006	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21006	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21007	/* MIN_S_H */	---	21007	/* MIN_S_H */	---
21008	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21008	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21009	/* MIN_S_MMR6 */	---	21009	/* MIN_S_MMR6 */	---
21010	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21010	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21011	/* MIN_S_W */	---	21011	/* MIN_S_W */	---
21012	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21012	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21013	/* MIN_U_B */	---	21013	/* MIN_U_B */	---
21014	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21014	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21015	/* MIN_U_D */	---	21015	/* MIN_U_D */	---
21016	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21016	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21017	/* MIN_U_H */	---	21017	/* MIN_U_H */	---
21018	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21018	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21019	/* MIN_U_W */	---	21019	/* MIN_U_W */	---
21020	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21020	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21021	/* MOD */	---	21021	/* MOD */	---
21022	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21022	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21023	/* MODSUB */	---	21023	/* MODSUB */	---
21024	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21024	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21025	/* MODSUB_MM */	---	21025	/* MODSUB_MM */	---
21026	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21026	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21027	/* MODU */	---	21027	/* MODU */	---
21028	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21028	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21029	/* MODU_MMR6 */	---	21029	/* MODU_MMR6 */	---
21030	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21030	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21031	/* MOD_MMR6 */	---	21031	/* MOD_MMR6 */	---
21032	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21032	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21033	/* MOD_S_B */	---	21033	/* MOD_S_B */	---
21034	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21034	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21035	/* MOD_S_D */	---	21035	/* MOD_S_D */	---
21036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21036	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21037	/* MOD_S_H */	---	21037	/* MOD_S_H */	---
21038	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21038	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21039	/* MOD_S_W */	---	21039	/* MOD_S_W */	---
21040	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21040	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21041	/* MOD_U_B */	---	21041	/* MOD_U_B */	---
21042	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21042	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21043	/* MOD_U_D */	---	21043	/* MOD_U_D */	---
21044	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21044	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21045	/* MOD_U_H */	---	21045	/* MOD_U_H */	---
21046	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21046	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21047	/* MOD_U_W */	---	21047	/* MOD_U_W */	---
21048	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21048	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21049	/* MOVE16_MM */	---	21049	/* MOVE16_MM */	---
21050	GPR32Opnd, GPR32Opnd,	---	21050	GPR32Opnd, GPR32Opnd,	---
21051	/* MOVE16_MMR6 */	---	21051	/* MOVE16_MMR6 */	---
21052	GPR32Opnd, GPR32Opnd,	---	21052	GPR32Opnd, GPR32Opnd,	---
21053	/* MOVEP_MM */	---	21053	/* MOVEP_MM */	---
21054	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	---	21054	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	---
21055	/* MOVEP_MMR6 */	---	21055	/* MOVEP_MMR6 */	---
21056	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	---	21056	GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,	---
21057	/* MOVE_V */	---	21057	/* MOVE_V */	---
21058	MSA128BOpnd, MSA128BOpnd,	---	21058	MSA128BOpnd, MSA128BOpnd,	---
21059	/* MOVF_D32 */	---	21059	/* MOVF_D32 */	---
21060	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---	21060	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---
21061	/* MOVF_D32_MM */	---	21061	/* MOVF_D32_MM */	---
21062	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---	21062	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---
21063	/* MOVF_D64 */	---	21063	/* MOVF_D64 */	---
21064	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	---	21064	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	---
21065	/* MOVF_I */	---	21065	/* MOVF_I */	---
21066	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---	21066	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---
21067	/* MOVF_I64 */	---	21067	/* MOVF_I64 */	---
21068	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	---	21068	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	---
21069	/* MOVF_I_MM */	---	21069	/* MOVF_I_MM */	---
21070	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---	21070	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---
21071	/* MOVF_S */	---	21071	/* MOVF_S */	---
21072	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---	21072	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---
21073	/* MOVF_S_MM */	---	21073	/* MOVF_S_MM */	---
21074	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---	21074	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---
21075	/* MOVN_I64_D64 */	---	21075	/* MOVN_I64_D64 */	---
21076	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	---	21076	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	---
21077	/* MOVN_I64_I */	---	21077	/* MOVN_I64_I */	---
21078	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	---	21078	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	---
21079	/* MOVN_I64_I64 */	---	21079	/* MOVN_I64_I64 */	---
21080	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21080	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21081	/* MOVN_I64_S */	---	21081	/* MOVN_I64_S */	---
21082	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	---	21082	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	---
21083	/* MOVN_I_D32 */	---	21083	/* MOVN_I_D32 */	---
21084	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---	21084	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---
21085	/* MOVN_I_D32_MM */	---	21085	/* MOVN_I_D32_MM */	---
21086	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---	21086	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---
21087	/* MOVN_I_D64 */	---	21087	/* MOVN_I_D64 */	---
21088	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	---	21088	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	---
21089	/* MOVN_I_I */	---	21089	/* MOVN_I_I */	---
21090	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21090	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21091	/* MOVN_I_I64 */	---	21091	/* MOVN_I_I64 */	---
21092	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	---	21092	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	---
21093	/* MOVN_I_MM */	---	21093	/* MOVN_I_MM */	---
21094	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21094	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21095	/* MOVN_I_S */	---	21095	/* MOVN_I_S */	---
21096	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---	21096	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---
21097	/* MOVN_I_S_MM */	---	21097	/* MOVN_I_S_MM */	---
21098	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---	21098	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---
21099	/* MOVT_D32 */	---	21099	/* MOVT_D32 */	---
21100	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---	21100	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---
21101	/* MOVT_D32_MM */	---	21101	/* MOVT_D32_MM */	---
21102	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---	21102	AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,	---
21103	/* MOVT_D64 */	---	21103	/* MOVT_D64 */	---
21104	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	---	21104	FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,	---
21105	/* MOVT_I */	---	21105	/* MOVT_I */	---
21106	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---	21106	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---
21107	/* MOVT_I64 */	---	21107	/* MOVT_I64 */	---
21108	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	---	21108	GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,	---
21109	/* MOVT_I_MM */	---	21109	/* MOVT_I_MM */	---
21110	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---	21110	GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,	---
21111	/* MOVT_S */	---	21111	/* MOVT_S */	---
21112	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---	21112	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---
21113	/* MOVT_S_MM */	---	21113	/* MOVT_S_MM */	---
21114	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---	21114	FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,	---
21115	/* MOVZ_I64_D64 */	---	21115	/* MOVZ_I64_D64 */	---
21116	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	---	21116	FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,	---
21117	/* MOVZ_I64_I */	---	21117	/* MOVZ_I64_I */	---
21118	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	---	21118	GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,	---
21119	/* MOVZ_I64_I64 */	---	21119	/* MOVZ_I64_I64 */	---
21120	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21120	GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21121	/* MOVZ_I64_S */	---	21121	/* MOVZ_I64_S */	---
21122	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	---	21122	FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,	---
21123	/* MOVZ_I_D32 */	---	21123	/* MOVZ_I_D32 */	---
21124	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---	21124	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---
21125	/* MOVZ_I_D32_MM */	---	21125	/* MOVZ_I_D32_MM */	---
21126	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---	21126	AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,	---
21127	/* MOVZ_I_D64 */	---	21127	/* MOVZ_I_D64 */	---
21128	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	---	21128	FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,	---
21129	/* MOVZ_I_I */	---	21129	/* MOVZ_I_I */	---
21130	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21130	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21131	/* MOVZ_I_I64 */	---	21131	/* MOVZ_I_I64 */	---
21132	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	---	21132	GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,	---
21133	/* MOVZ_I_MM */	---	21133	/* MOVZ_I_MM */	---
21134	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21134	GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21135	/* MOVZ_I_S */	---	21135	/* MOVZ_I_S */	---
21136	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---	21136	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---
21137	/* MOVZ_I_S_MM */	---	21137	/* MOVZ_I_S_MM */	---
21138	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---	21138	FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,	---
21139	/* MSUB */	---	21139	/* MSUB */	---
21140	GPR32Opnd, GPR32Opnd,	---	21140	GPR32Opnd, GPR32Opnd,	---
21141	/* MSUBF_D */	---	21141	/* MSUBF_D */	---
21142	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21142	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21143	/* MSUBF_D_MMR6 */	---	21143	/* MSUBF_D_MMR6 */	---
21144	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21144	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21145	/* MSUBF_S */	---	21145	/* MSUBF_S */	---
21146	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21146	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21147	/* MSUBF_S_MMR6 */	---	21147	/* MSUBF_S_MMR6 */	---
21148	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21148	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21149	/* MSUBR_Q_H */	---	21149	/* MSUBR_Q_H */	---
21150	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21150	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21151	/* MSUBR_Q_W */	---	21151	/* MSUBR_Q_W */	---
21152	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21152	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21153	/* MSUBU */	---	21153	/* MSUBU */	---
21154	GPR32Opnd, GPR32Opnd,	---	21154	GPR32Opnd, GPR32Opnd,	---
21155	/* MSUBU_DSP */	---	21155	/* MSUBU_DSP */	---
21156	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21156	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21157	/* MSUBU_DSP_MM */	---	21157	/* MSUBU_DSP_MM */	---
21158	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21158	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21159	/* MSUBU_MM */	---	21159	/* MSUBU_MM */	---
21160	GPR32Opnd, GPR32Opnd,	---	21160	GPR32Opnd, GPR32Opnd,	---
21161	/* MSUBV_B */	---	21161	/* MSUBV_B */	---
21162	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21162	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21163	/* MSUBV_D */	---	21163	/* MSUBV_D */	---
21164	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21164	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21165	/* MSUBV_H */	---	21165	/* MSUBV_H */	---
21166	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21166	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21167	/* MSUBV_W */	---	21167	/* MSUBV_W */	---
21168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21168	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21169	/* MSUB_D32 */	---	21169	/* MSUB_D32 */	---
21170	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21170	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21171	/* MSUB_D32_MM */	---	21171	/* MSUB_D32_MM */	---
21172	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21172	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21173	/* MSUB_D64 */	---	21173	/* MSUB_D64 */	---
21174	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21174	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21175	/* MSUB_DSP */	---	21175	/* MSUB_DSP */	---
21176	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21176	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21177	/* MSUB_DSP_MM */	---	21177	/* MSUB_DSP_MM */	---
21178	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21178	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21179	/* MSUB_MM */	---	21179	/* MSUB_MM */	---
21180	GPR32Opnd, GPR32Opnd,	---	21180	GPR32Opnd, GPR32Opnd,	---
21181	/* MSUB_Q_H */	---	21181	/* MSUB_Q_H */	---
21182	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21182	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21183	/* MSUB_Q_W */	---	21183	/* MSUB_Q_W */	---
21184	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21184	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21185	/* MSUB_S */	---	21185	/* MSUB_S */	---
21186	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21186	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21187	/* MSUB_S_MM */	---	21187	/* MSUB_S_MM */	---
21188	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21188	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21189	/* MTC0 */	---	21189	/* MTC0 */	---
21190	COP0Opnd, GPR32Opnd, uimm3,	---	21190	COP0Opnd, GPR32Opnd, uimm3,	---
21191	/* MTC0_MMR6 */	---	21191	/* MTC0_MMR6 */	---
21192	COP0Opnd, GPR32Opnd, uimm3,	---	21192	COP0Opnd, GPR32Opnd, uimm3,	---
21193	/* MTC1 */	---	21193	/* MTC1 */	---
21194	FGR32Opnd, GPR32Opnd,	---	21194	FGR32Opnd, GPR32Opnd,	---
21195	/* MTC1_D64 */	---	21195	/* MTC1_D64 */	---
21196	FGR64Opnd, GPR32Opnd,	---	21196	FGR64Opnd, GPR32Opnd,	---
21197	/* MTC1_D64_MM */	---	21197	/* MTC1_D64_MM */	---
21198	FGR64Opnd, GPR32Opnd,	---	21198	FGR64Opnd, GPR32Opnd,	---
21199	/* MTC1_MM */	---	21199	/* MTC1_MM */	---
21200	FGR32Opnd, GPR32Opnd,	---	21200	FGR32Opnd, GPR32Opnd,	---
21201	/* MTC1_MMR6 */	---	21201	/* MTC1_MMR6 */	---
21202	FGR32Opnd, GPR32Opnd,	---	21202	FGR32Opnd, GPR32Opnd,	---
21203	/* MTC2 */	---	21203	/* MTC2 */	---
21204	COP2Opnd, GPR32Opnd, uimm3,	---	21204	COP2Opnd, GPR32Opnd, uimm3,	---
21205	/* MTC2_MMR6 */	---	21205	/* MTC2_MMR6 */	---
21206	COP2Opnd, GPR32Opnd,	---	21206	COP2Opnd, GPR32Opnd,	---
21207	/* MTGC0 */	---	21207	/* MTGC0 */	---
21208	COP0Opnd, GPR32Opnd, uimm3,	---	21208	COP0Opnd, GPR32Opnd, uimm3,	---
21209	/* MTGC0_MM */	---	21209	/* MTGC0_MM */	---
21210	COP0Opnd, GPR32Opnd, uimm3,	---	21210	COP0Opnd, GPR32Opnd, uimm3,	---
21211	/* MTHC0_MMR6 */	---	21211	/* MTHC0_MMR6 */	---
21212	COP0Opnd, GPR32Opnd, uimm3,	---	21212	COP0Opnd, GPR32Opnd, uimm3,	---
21213	/* MTHC1_D32 */	---	21213	/* MTHC1_D32 */	---
21214	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	---	21214	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	---
21215	/* MTHC1_D32_MM */	---	21215	/* MTHC1_D32_MM */	---
21216	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	---	21216	AFGR64Opnd, AFGR64Opnd, GPR32Opnd,	---
21217	/* MTHC1_D64 */	---	21217	/* MTHC1_D64 */	---
21218	FGR64Opnd, FGR64Opnd, GPR32Opnd,	---	21218	FGR64Opnd, FGR64Opnd, GPR32Opnd,	---
21219	/* MTHC1_D64_MM */	---	21219	/* MTHC1_D64_MM */	---
21220	FGR64Opnd, FGR64Opnd, GPR32Opnd,	---	21220	FGR64Opnd, FGR64Opnd, GPR32Opnd,	---
21221	/* MTHC2_MMR6 */	---	21221	/* MTHC2_MMR6 */	---
21222	COP2Opnd, GPR32Opnd,	---	21222	COP2Opnd, GPR32Opnd,	---
21223	/* MTHGC0 */	---	21223	/* MTHGC0 */	---
21224	COP0Opnd, GPR32Opnd, uimm3,	---	21224	COP0Opnd, GPR32Opnd, uimm3,	---
21225	/* MTHGC0_MM */	---	21225	/* MTHGC0_MM */	---
21226	COP0Opnd, GPR32Opnd, uimm3,	---	21226	COP0Opnd, GPR32Opnd, uimm3,	---
21227	/* MTHI */	---	21227	/* MTHI */	---
21228	GPR32Opnd,	---	21228	GPR32Opnd,	---
21229	/* MTHI64 */	---	21229	/* MTHI64 */	---
21230	GPR64Opnd,	---	21230	GPR64Opnd,	---
21231	/* MTHI_DSP */	---	21231	/* MTHI_DSP */	---
21232	HI32DSPOpnd, GPR32Opnd,	---	21232	HI32DSPOpnd, GPR32Opnd,	---
21233	/* MTHI_DSP_MM */	---	21233	/* MTHI_DSP_MM */	---
21234	HI32DSPOpnd, GPR32Opnd,	---	21234	HI32DSPOpnd, GPR32Opnd,	---
21235	/* MTHI_MM */	---	21235	/* MTHI_MM */	---
21236	GPR32Opnd,	---	21236	GPR32Opnd,	---
21237	/* MTHLIP */	---	21237	/* MTHLIP */	---
21238	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---	21238	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---
21239	/* MTHLIP_MM */	---	21239	/* MTHLIP_MM */	---
21240	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---	21240	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---
21241	/* MTLO */	---	21241	/* MTLO */	---
21242	GPR32Opnd,	---	21242	GPR32Opnd,	---
21243	/* MTLO64 */	---	21243	/* MTLO64 */	---
21244	GPR64Opnd,	---	21244	GPR64Opnd,	---
21245	/* MTLO_DSP */	---	21245	/* MTLO_DSP */	---
21246	LO32DSPOpnd, GPR32Opnd,	---	21246	LO32DSPOpnd, GPR32Opnd,	---
21247	/* MTLO_DSP_MM */	---	21247	/* MTLO_DSP_MM */	---
21248	LO32DSPOpnd, GPR32Opnd,	---	21248	LO32DSPOpnd, GPR32Opnd,	---
21249	/* MTLO_MM */	---	21249	/* MTLO_MM */	---
21250	GPR32Opnd,	---	21250	GPR32Opnd,	---
21251	/* MTM0 */	---	21251	/* MTM0 */	---
21252	GPR64Opnd,	---	21252	GPR64Opnd,	---
21253	/* MTM1 */	---	21253	/* MTM1 */	---
21254	GPR64Opnd,	---	21254	GPR64Opnd,	---
21255	/* MTM2 */	---	21255	/* MTM2 */	---
21256	GPR64Opnd,	---	21256	GPR64Opnd,	---
21257	/* MTP0 */	---	21257	/* MTP0 */	---
21258	GPR64Opnd,	---	21258	GPR64Opnd,	---
21259	/* MTP1 */	---	21259	/* MTP1 */	---
21260	GPR64Opnd,	---	21260	GPR64Opnd,	---
21261	/* MTP2 */	---	21261	/* MTP2 */	---
21262	GPR64Opnd,	---	21262	GPR64Opnd,	---
21263	/* MTTR */	---	21263	/* MTTR */	---
21264	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	---	21264	GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,	---
21265	/* MUH */	---	21265	/* MUH */	---
21266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21267	/* MUHU */	---	21267	/* MUHU */	---
21268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21269	/* MUHU_MMR6 */	---	21269	/* MUHU_MMR6 */	---
21270	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21270	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21271	/* MUH_MMR6 */	---	21271	/* MUH_MMR6 */	---
21272	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21272	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21273	/* MUL */	---	21273	/* MUL */	---
21274	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21274	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21275	/* MULEQ_S_W_PHL */	---	21275	/* MULEQ_S_W_PHL */	---
21276	GPR32Opnd, DSPROpnd, DSPROpnd,	---	21276	GPR32Opnd, DSPROpnd, DSPROpnd,	---
21277	/* MULEQ_S_W_PHL_MM */	---	21277	/* MULEQ_S_W_PHL_MM */	---
21278	GPR32Opnd, DSPROpnd, DSPROpnd,	---	21278	GPR32Opnd, DSPROpnd, DSPROpnd,	---
21279	/* MULEQ_S_W_PHR */	---	21279	/* MULEQ_S_W_PHR */	---
21280	GPR32Opnd, DSPROpnd, DSPROpnd,	---	21280	GPR32Opnd, DSPROpnd, DSPROpnd,	---
21281	/* MULEQ_S_W_PHR_MM */	---	21281	/* MULEQ_S_W_PHR_MM */	---
21282	GPR32Opnd, DSPROpnd, DSPROpnd,	---	21282	GPR32Opnd, DSPROpnd, DSPROpnd,	---
21283	/* MULEU_S_PH_QBL */	---	21283	/* MULEU_S_PH_QBL */	---
21284	DSPROpnd, DSPROpnd, DSPROpnd,	---	21284	DSPROpnd, DSPROpnd, DSPROpnd,	---
21285	/* MULEU_S_PH_QBL_MM */	---	21285	/* MULEU_S_PH_QBL_MM */	---
21286	DSPROpnd, DSPROpnd, DSPROpnd,	---	21286	DSPROpnd, DSPROpnd, DSPROpnd,	---
21287	/* MULEU_S_PH_QBR */	---	21287	/* MULEU_S_PH_QBR */	---
21288	DSPROpnd, DSPROpnd, DSPROpnd,	---	21288	DSPROpnd, DSPROpnd, DSPROpnd,	---
21289	/* MULEU_S_PH_QBR_MM */	---	21289	/* MULEU_S_PH_QBR_MM */	---
21290	DSPROpnd, DSPROpnd, DSPROpnd,	---	21290	DSPROpnd, DSPROpnd, DSPROpnd,	---
21291	/* MULQ_RS_PH */	---	21291	/* MULQ_RS_PH */	---
21292	DSPROpnd, DSPROpnd, DSPROpnd,	---	21292	DSPROpnd, DSPROpnd, DSPROpnd,	---
21293	/* MULQ_RS_PH_MM */	---	21293	/* MULQ_RS_PH_MM */	---
21294	DSPROpnd, DSPROpnd, DSPROpnd,	---	21294	DSPROpnd, DSPROpnd, DSPROpnd,	---
21295	/* MULQ_RS_W */	---	21295	/* MULQ_RS_W */	---
21296	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21296	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21297	/* MULQ_RS_W_MMR2 */	---	21297	/* MULQ_RS_W_MMR2 */	---
21298	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21298	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21299	/* MULQ_S_PH */	---	21299	/* MULQ_S_PH */	---
21300	DSPROpnd, DSPROpnd, DSPROpnd,	---	21300	DSPROpnd, DSPROpnd, DSPROpnd,	---
21301	/* MULQ_S_PH_MMR2 */	---	21301	/* MULQ_S_PH_MMR2 */	---
21302	DSPROpnd, DSPROpnd, DSPROpnd,	---	21302	DSPROpnd, DSPROpnd, DSPROpnd,	---
21303	/* MULQ_S_W */	---	21303	/* MULQ_S_W */	---
21304	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21304	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21305	/* MULQ_S_W_MMR2 */	---	21305	/* MULQ_S_W_MMR2 */	---
21306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21306	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21307	/* MULR_PS64 */	---	21307	/* MULR_PS64 */	---
21308	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21308	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21309	/* MULR_Q_H */	---	21309	/* MULR_Q_H */	---
21310	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21310	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21311	/* MULR_Q_W */	---	21311	/* MULR_Q_W */	---
21312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21312	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21313	/* MULSAQ_S_W_PH */	---	21313	/* MULSAQ_S_W_PH */	---
21314	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21314	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21315	/* MULSAQ_S_W_PH_MM */	---	21315	/* MULSAQ_S_W_PH_MM */	---
21316	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21316	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21317	/* MULSA_W_PH */	---	21317	/* MULSA_W_PH */	---
21318	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21318	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21319	/* MULSA_W_PH_MMR2 */	---	21319	/* MULSA_W_PH_MMR2 */	---
21320	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---	21320	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,	---
21321	/* MULT */	---	21321	/* MULT */	---
21322	GPR32Opnd, GPR32Opnd,	---	21322	GPR32Opnd, GPR32Opnd,	---
21323	/* MULTU_DSP */	---	21323	/* MULTU_DSP */	---
21324	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---	21324	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---
21325	/* MULTU_DSP_MM */	---	21325	/* MULTU_DSP_MM */	---
21326	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---	21326	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---
21327	/* MULT_DSP */	---	21327	/* MULT_DSP */	---
21328	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---	21328	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---
21329	/* MULT_DSP_MM */	---	21329	/* MULT_DSP_MM */	---
21330	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---	21330	ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,	---
21331	/* MULT_MM */	---	21331	/* MULT_MM */	---
21332	GPR32Opnd, GPR32Opnd,	---	21332	GPR32Opnd, GPR32Opnd,	---
21333	/* MULTu */	---	21333	/* MULTu */	---
21334	GPR32Opnd, GPR32Opnd,	---	21334	GPR32Opnd, GPR32Opnd,	---
21335	/* MULTu_MM */	---	21335	/* MULTu_MM */	---
21336	GPR32Opnd, GPR32Opnd,	---	21336	GPR32Opnd, GPR32Opnd,	---
21337	/* MULU */	---	21337	/* MULU */	---
21338	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21338	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21339	/* MULU_MMR6 */	---	21339	/* MULU_MMR6 */	---
21340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21340	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21341	/* MULV_B */	---	21341	/* MULV_B */	---
21342	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21342	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21343	/* MULV_D */	---	21343	/* MULV_D */	---
21344	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21344	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21345	/* MULV_H */	---	21345	/* MULV_H */	---
21346	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21346	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21347	/* MULV_W */	---	21347	/* MULV_W */	---
21348	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21348	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21349	/* MUL_MM */	---	21349	/* MUL_MM */	---
21350	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21350	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21351	/* MUL_MMR6 */	---	21351	/* MUL_MMR6 */	---
21352	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21352	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21353	/* MUL_PH */	---	21353	/* MUL_PH */	---
21354	DSPROpnd, DSPROpnd, DSPROpnd,	---	21354	DSPROpnd, DSPROpnd, DSPROpnd,	---
21355	/* MUL_PH_MMR2 */	---	21355	/* MUL_PH_MMR2 */	---
21356	DSPROpnd, DSPROpnd, DSPROpnd,	---	21356	DSPROpnd, DSPROpnd, DSPROpnd,	---
21357	/* MUL_Q_H */	---	21357	/* MUL_Q_H */	---
21358	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21358	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21359	/* MUL_Q_W */	---	21359	/* MUL_Q_W */	---
21360	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21360	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21361	/* MUL_R6 */	---	21361	/* MUL_R6 */	---
21362	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21362	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21363	/* MUL_S_PH */	---	21363	/* MUL_S_PH */	---
21364	DSPROpnd, DSPROpnd, DSPROpnd,	---	21364	DSPROpnd, DSPROpnd, DSPROpnd,	---
21365	/* MUL_S_PH_MMR2 */	---	21365	/* MUL_S_PH_MMR2 */	---
21366	DSPROpnd, DSPROpnd, DSPROpnd,	---	21366	DSPROpnd, DSPROpnd, DSPROpnd,	---
21367	/* Mfhi16 */	---	21367	/* Mfhi16 */	---
21368	CPU16Regs,	---	21368	CPU16Regs,	---
21369	/* Mflo16 */	---	21369	/* Mflo16 */	---
21370	CPU16Regs,	---	21370	CPU16Regs,	---
21371	/* Move32R16 */	---	21371	/* Move32R16 */	---
21372	GPR32, CPU16Regs,	---	21372	GPR32, CPU16Regs,	---
21373	/* MoveR3216 */	---	21373	/* MoveR3216 */	---
21374	CPU16Regs, GPR32,	---	21374	CPU16Regs, GPR32,	---
21375	/* NLOC_B */	---	21375	/* NLOC_B */	---
21376	MSA128BOpnd, MSA128BOpnd,	---	21376	MSA128BOpnd, MSA128BOpnd,	---
21377	/* NLOC_D */	---	21377	/* NLOC_D */	---
21378	MSA128DOpnd, MSA128DOpnd,	---	21378	MSA128DOpnd, MSA128DOpnd,	---
21379	/* NLOC_H */	---	21379	/* NLOC_H */	---
21380	MSA128HOpnd, MSA128HOpnd,	---	21380	MSA128HOpnd, MSA128HOpnd,	---
21381	/* NLOC_W */	---	21381	/* NLOC_W */	---
21382	MSA128WOpnd, MSA128WOpnd,	---	21382	MSA128WOpnd, MSA128WOpnd,	---
21383	/* NLZC_B */	---	21383	/* NLZC_B */	---
21384	MSA128BOpnd, MSA128BOpnd,	---	21384	MSA128BOpnd, MSA128BOpnd,	---
21385	/* NLZC_D */	---	21385	/* NLZC_D */	---
21386	MSA128DOpnd, MSA128DOpnd,	---	21386	MSA128DOpnd, MSA128DOpnd,	---
21387	/* NLZC_H */	---	21387	/* NLZC_H */	---
21388	MSA128HOpnd, MSA128HOpnd,	---	21388	MSA128HOpnd, MSA128HOpnd,	---
21389	/* NLZC_W */	---	21389	/* NLZC_W */	---
21390	MSA128WOpnd, MSA128WOpnd,	---	21390	MSA128WOpnd, MSA128WOpnd,	---
21391	/* NMADD_D32 */	---	21391	/* NMADD_D32 */	---
21392	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21392	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21393	/* NMADD_D32_MM */	---	21393	/* NMADD_D32_MM */	---
21394	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21394	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21395	/* NMADD_D64 */	---	21395	/* NMADD_D64 */	---
21396	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21396	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21397	/* NMADD_S */	---	21397	/* NMADD_S */	---
21398	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21398	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21399	/* NMADD_S_MM */	---	21399	/* NMADD_S_MM */	---
21400	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21400	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21401	/* NMSUB_D32 */	---	21401	/* NMSUB_D32 */	---
21402	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21402	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21403	/* NMSUB_D32_MM */	---	21403	/* NMSUB_D32_MM */	---
21404	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---	21404	AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,	---
21405	/* NMSUB_D64 */	---	21405	/* NMSUB_D64 */	---
21406	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21406	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21407	/* NMSUB_S */	---	21407	/* NMSUB_S */	---
21408	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21408	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21409	/* NMSUB_S_MM */	---	21409	/* NMSUB_S_MM */	---
21410	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21410	FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21411	/* NOR */	---	21411	/* NOR */	---
21412	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21412	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21413	/* NOR64 */	---	21413	/* NOR64 */	---
21414	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21414	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21415	/* NORI_B */	---	21415	/* NORI_B */	---
21416	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	21416	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
21417	/* NOR_MM */	---	21417	/* NOR_MM */	---
21418	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21418	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21419	/* NOR_MMR6 */	---	21419	/* NOR_MMR6 */	---
21420	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21420	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21421	/* NOR_V */	---	21421	/* NOR_V */	---
21422	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21422	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21423	/* NOT16_MM */	---	21423	/* NOT16_MM */	---
21424	GPRMM16Opnd, GPRMM16Opnd,	---	21424	GPRMM16Opnd, GPRMM16Opnd,	---
21425	/* NOT16_MMR6 */	---	21425	/* NOT16_MMR6 */	---
21426	GPRMM16Opnd, GPRMM16Opnd,	---	21426	GPRMM16Opnd, GPRMM16Opnd,	---
21427	/* NegRxRy16 */	---	21427	/* NegRxRy16 */	---
21428	CPU16Regs, CPU16Regs,	---	21428	CPU16Regs, CPU16Regs,	---
21429	/* NotRxRy16 */	---	21429	/* NotRxRy16 */	---
21430	CPU16Regs, CPU16Regs,	---	21430	CPU16Regs, CPU16Regs,	---
21431	/* OR */	---	21431	/* OR */	---
21432	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21432	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21433	/* OR16_MM */	---	21433	/* OR16_MM */	---
21434	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	21434	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
21435	/* OR16_MMR6 */	---	21435	/* OR16_MMR6 */	---
21436	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	21436	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
21437	/* OR64 */	---	21437	/* OR64 */	---
21438	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21438	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21439	/* ORI_B */	---	21439	/* ORI_B */	---
21440	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	21440	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
21441	/* ORI_MMR6 */	---	21441	/* ORI_MMR6 */	---
21442	GPR32Opnd, GPR32Opnd, uimm16,	---	21442	GPR32Opnd, GPR32Opnd, uimm16,	---
21443	/* OR_MM */	---	21443	/* OR_MM */	---
21444	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21444	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21445	/* OR_MMR6 */	---	21445	/* OR_MMR6 */	---
21446	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21446	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21447	/* OR_V */	---	21447	/* OR_V */	---
21448	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21448	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21449	/* ORi */	---	21449	/* ORi */	---
21450	GPR32Opnd, GPR32Opnd, uimm16,	---	21450	GPR32Opnd, GPR32Opnd, uimm16,	---
21451	/* ORi64 */	---	21451	/* ORi64 */	---
21452	GPR64Opnd, GPR64Opnd, uimm16_64,	---	21452	GPR64Opnd, GPR64Opnd, uimm16_64,	---
21453	/* ORi_MM */	---	21453	/* ORi_MM */	---
21454	GPR32Opnd, GPR32Opnd, uimm16,	---	21454	GPR32Opnd, GPR32Opnd, uimm16,	---
21455	/* OrRxRxRy16 */	---	21455	/* OrRxRxRy16 */	---
21456	CPU16Regs, CPU16Regs, CPU16Regs,	---	21456	CPU16Regs, CPU16Regs, CPU16Regs,	---
21457	/* PACKRL_PH */	---	21457	/* PACKRL_PH */	---
21458	DSPROpnd, DSPROpnd, DSPROpnd,	---	21458	DSPROpnd, DSPROpnd, DSPROpnd,	---
21459	/* PACKRL_PH_MM */	---	21459	/* PACKRL_PH_MM */	---
21460	DSPROpnd, DSPROpnd, DSPROpnd,	---	21460	DSPROpnd, DSPROpnd, DSPROpnd,	---
21461	/* PAUSE */	---	21461	/* PAUSE */	---
21462	/* PAUSE_MM */	---	21462	/* PAUSE_MM */	---
21463	/* PAUSE_MMR6 */	---	21463	/* PAUSE_MMR6 */	---
21464	/* PCKEV_B */	---	21464	/* PCKEV_B */	---
21465	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21465	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21466	/* PCKEV_D */	---	21466	/* PCKEV_D */	---
21467	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21467	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21468	/* PCKEV_H */	---	21468	/* PCKEV_H */	---
21469	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21469	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21470	/* PCKEV_W */	---	21470	/* PCKEV_W */	---
21471	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21471	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21472	/* PCKOD_B */	---	21472	/* PCKOD_B */	---
21473	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	21473	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
21474	/* PCKOD_D */	---	21474	/* PCKOD_D */	---
21475	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	21475	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
21476	/* PCKOD_H */	---	21476	/* PCKOD_H */	---
21477	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	21477	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
21478	/* PCKOD_W */	---	21478	/* PCKOD_W */	---
21479	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	21479	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
21480	/* PCNT_B */	---	21480	/* PCNT_B */	---
21481	MSA128BOpnd, MSA128BOpnd,	---	21481	MSA128BOpnd, MSA128BOpnd,	---
21482	/* PCNT_D */	---	21482	/* PCNT_D */	---
21483	MSA128DOpnd, MSA128DOpnd,	---	21483	MSA128DOpnd, MSA128DOpnd,	---
21484	/* PCNT_H */	---	21484	/* PCNT_H */	---
21485	MSA128HOpnd, MSA128HOpnd,	---	21485	MSA128HOpnd, MSA128HOpnd,	---
21486	/* PCNT_W */	---	21486	/* PCNT_W */	---
21487	MSA128WOpnd, MSA128WOpnd,	---	21487	MSA128WOpnd, MSA128WOpnd,	---
21488	/* PICK_PH */	---	21488	/* PICK_PH */	---
21489	DSPROpnd, DSPROpnd, DSPROpnd,	---	21489	DSPROpnd, DSPROpnd, DSPROpnd,	---
21490	/* PICK_PH_MM */	---	21490	/* PICK_PH_MM */	---
21491	DSPROpnd, DSPROpnd, DSPROpnd,	---	21491	DSPROpnd, DSPROpnd, DSPROpnd,	---
21492	/* PICK_QB */	---	21492	/* PICK_QB */	---
21493	DSPROpnd, DSPROpnd, DSPROpnd,	---	21493	DSPROpnd, DSPROpnd, DSPROpnd,	---
21494	/* PICK_QB_MM */	---	21494	/* PICK_QB_MM */	---
21495	DSPROpnd, DSPROpnd, DSPROpnd,	---	21495	DSPROpnd, DSPROpnd, DSPROpnd,	---
21496	/* PLL_PS64 */	---	21496	/* PLL_PS64 */	---
21497	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21497	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21498	/* PLU_PS64 */	---	21498	/* PLU_PS64 */	---
21499	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21499	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21500	/* POP */	---	21500	/* POP */	---
21501	GPR32Opnd, GPR32Opnd,	---	21501	GPR32Opnd, GPR32Opnd,	---
21502	/* PRECEQU_PH_QBL */	---	21502	/* PRECEQU_PH_QBL */	---
21503	DSPROpnd, DSPROpnd,	---	21503	DSPROpnd, DSPROpnd,	---
21504	/* PRECEQU_PH_QBLA */	---	21504	/* PRECEQU_PH_QBLA */	---
21505	DSPROpnd, DSPROpnd,	---	21505	DSPROpnd, DSPROpnd,	---
21506	/* PRECEQU_PH_QBLA_MM */	---	21506	/* PRECEQU_PH_QBLA_MM */	---
21507	DSPROpnd, DSPROpnd,	---	21507	DSPROpnd, DSPROpnd,	---
21508	/* PRECEQU_PH_QBL_MM */	---	21508	/* PRECEQU_PH_QBL_MM */	---
21509	DSPROpnd, DSPROpnd,	---	21509	DSPROpnd, DSPROpnd,	---
21510	/* PRECEQU_PH_QBR */	---	21510	/* PRECEQU_PH_QBR */	---
21511	DSPROpnd, DSPROpnd,	---	21511	DSPROpnd, DSPROpnd,	---
21512	/* PRECEQU_PH_QBRA */	---	21512	/* PRECEQU_PH_QBRA */	---
21513	DSPROpnd, DSPROpnd,	---	21513	DSPROpnd, DSPROpnd,	---
21514	/* PRECEQU_PH_QBRA_MM */	---	21514	/* PRECEQU_PH_QBRA_MM */	---
21515	DSPROpnd, DSPROpnd,	---	21515	DSPROpnd, DSPROpnd,	---
21516	/* PRECEQU_PH_QBR_MM */	---	21516	/* PRECEQU_PH_QBR_MM */	---
21517	DSPROpnd, DSPROpnd,	---	21517	DSPROpnd, DSPROpnd,	---
21518	/* PRECEQ_W_PHL */	---	21518	/* PRECEQ_W_PHL */	---
21519	GPR32Opnd, DSPROpnd,	---	21519	GPR32Opnd, DSPROpnd,	---
21520	/* PRECEQ_W_PHL_MM */	---	21520	/* PRECEQ_W_PHL_MM */	---
21521	GPR32Opnd, DSPROpnd,	---	21521	GPR32Opnd, DSPROpnd,	---
21522	/* PRECEQ_W_PHR */	---	21522	/* PRECEQ_W_PHR */	---
21523	GPR32Opnd, DSPROpnd,	---	21523	GPR32Opnd, DSPROpnd,	---
21524	/* PRECEQ_W_PHR_MM */	---	21524	/* PRECEQ_W_PHR_MM */	---
21525	GPR32Opnd, DSPROpnd,	---	21525	GPR32Opnd, DSPROpnd,	---
21526	/* PRECEU_PH_QBL */	---	21526	/* PRECEU_PH_QBL */	---
21527	DSPROpnd, DSPROpnd,	---	21527	DSPROpnd, DSPROpnd,	---
21528	/* PRECEU_PH_QBLA */	---	21528	/* PRECEU_PH_QBLA */	---
21529	DSPROpnd, DSPROpnd,	---	21529	DSPROpnd, DSPROpnd,	---
21530	/* PRECEU_PH_QBLA_MM */	---	21530	/* PRECEU_PH_QBLA_MM */	---
21531	DSPROpnd, DSPROpnd,	---	21531	DSPROpnd, DSPROpnd,	---
21532	/* PRECEU_PH_QBL_MM */	---	21532	/* PRECEU_PH_QBL_MM */	---
21533	DSPROpnd, DSPROpnd,	---	21533	DSPROpnd, DSPROpnd,	---
21534	/* PRECEU_PH_QBR */	---	21534	/* PRECEU_PH_QBR */	---
21535	DSPROpnd, DSPROpnd,	---	21535	DSPROpnd, DSPROpnd,	---
21536	/* PRECEU_PH_QBRA */	---	21536	/* PRECEU_PH_QBRA */	---
21537	DSPROpnd, DSPROpnd,	---	21537	DSPROpnd, DSPROpnd,	---
21538	/* PRECEU_PH_QBRA_MM */	---	21538	/* PRECEU_PH_QBRA_MM */	---
21539	DSPROpnd, DSPROpnd,	---	21539	DSPROpnd, DSPROpnd,	---
21540	/* PRECEU_PH_QBR_MM */	---	21540	/* PRECEU_PH_QBR_MM */	---
21541	DSPROpnd, DSPROpnd,	---	21541	DSPROpnd, DSPROpnd,	---
21542	/* PRECRQU_S_QB_PH */	---	21542	/* PRECRQU_S_QB_PH */	---
21543	DSPROpnd, DSPROpnd, DSPROpnd,	---	21543	DSPROpnd, DSPROpnd, DSPROpnd,	---
21544	/* PRECRQU_S_QB_PH_MM */	---	21544	/* PRECRQU_S_QB_PH_MM */	---
21545	DSPROpnd, DSPROpnd, DSPROpnd,	---	21545	DSPROpnd, DSPROpnd, DSPROpnd,	---
21546	/* PRECRQ_PH_W */	---	21546	/* PRECRQ_PH_W */	---
21547	DSPROpnd, GPR32Opnd, GPR32Opnd,	---	21547	DSPROpnd, GPR32Opnd, GPR32Opnd,	---
21548	/* PRECRQ_PH_W_MM */	---	21548	/* PRECRQ_PH_W_MM */	---
21549	DSPROpnd, GPR32Opnd, GPR32Opnd,	---	21549	DSPROpnd, GPR32Opnd, GPR32Opnd,	---
21550	/* PRECRQ_QB_PH */	---	21550	/* PRECRQ_QB_PH */	---
21551	DSPROpnd, DSPROpnd, DSPROpnd,	---	21551	DSPROpnd, DSPROpnd, DSPROpnd,	---
21552	/* PRECRQ_QB_PH_MM */	---	21552	/* PRECRQ_QB_PH_MM */	---
21553	DSPROpnd, DSPROpnd, DSPROpnd,	---	21553	DSPROpnd, DSPROpnd, DSPROpnd,	---
21554	/* PRECRQ_RS_PH_W */	---	21554	/* PRECRQ_RS_PH_W */	---
21555	DSPROpnd, GPR32Opnd, GPR32Opnd,	---	21555	DSPROpnd, GPR32Opnd, GPR32Opnd,	---
21556	/* PRECRQ_RS_PH_W_MM */	---	21556	/* PRECRQ_RS_PH_W_MM */	---
21557	DSPROpnd, GPR32Opnd, GPR32Opnd,	---	21557	DSPROpnd, GPR32Opnd, GPR32Opnd,	---
21558	/* PRECR_QB_PH */	---	21558	/* PRECR_QB_PH */	---
21559	DSPROpnd, DSPROpnd, DSPROpnd,	---	21559	DSPROpnd, DSPROpnd, DSPROpnd,	---
21560	/* PRECR_QB_PH_MMR2 */	---	21560	/* PRECR_QB_PH_MMR2 */	---
21561	DSPROpnd, DSPROpnd, DSPROpnd,	---	21561	DSPROpnd, DSPROpnd, DSPROpnd,	---
21562	/* PRECR_SRA_PH_W */	---	21562	/* PRECR_SRA_PH_W */	---
21563	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21563	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21564	/* PRECR_SRA_PH_W_MMR2 */	---	21564	/* PRECR_SRA_PH_W_MMR2 */	---
21565	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21565	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21566	/* PRECR_SRA_R_PH_W */	---	21566	/* PRECR_SRA_R_PH_W */	---
21567	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21567	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21568	/* PRECR_SRA_R_PH_W_MMR2 */	---	21568	/* PRECR_SRA_R_PH_W_MMR2 */	---
21569	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21569	DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21570	/* PREF */	---	21570	/* PREF */	---
21571	-1, simm16, uimm5,	---	21571	-1, simm16, uimm5,	---
21572	/* PREFE */	---	21572	/* PREFE */	---
21573	-1, simm9, uimm5,	---	21573	-1, simm9, uimm5,	---
21574	/* PREFE_MM */	---	21574	/* PREFE_MM */	---
21575	-1, simm9, uimm5,	---	21575	-1, simm9, uimm5,	---
21576	/* PREFX_MM */	---	21576	/* PREFX_MM */	---
21577	-1, -1, uimm5,	---	21577	-1, -1, uimm5,	---
21578	/* PREF_MM */	---	21578	/* PREF_MM */	---
21579	-1, simm12, uimm5,	---	21579	-1, simm12, uimm5,	---
21580	/* PREF_MMR6 */	---	21580	/* PREF_MMR6 */	---
21581	-1, simm12, uimm5,	---	21581	-1, simm12, uimm5,	---
21582	/* PREF_R6 */	---	21582	/* PREF_R6 */	---
21583	-1, simm9, uimm5,	---	21583	-1, simm9, uimm5,	---
21584	/* PREPEND */	---	21584	/* PREPEND */	---
21585	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21585	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21586	/* PREPEND_MMR2 */	---	21586	/* PREPEND_MMR2 */	---
21587	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---	21587	GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,	---
21588	/* PUL_PS64 */	---	21588	/* PUL_PS64 */	---
21589	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21589	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21590	/* PUU_PS64 */	---	21590	/* PUU_PS64 */	---
21591	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21591	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21592	/* RADDU_W_QB */	---	21592	/* RADDU_W_QB */	---
21593	GPR32Opnd, DSPROpnd,	---	21593	GPR32Opnd, DSPROpnd,	---
21594	/* RADDU_W_QB_MM */	---	21594	/* RADDU_W_QB_MM */	---
21595	GPR32Opnd, DSPROpnd,	---	21595	GPR32Opnd, DSPROpnd,	---
21596	/* RDDSP */	---	21596	/* RDDSP */	---
21597	GPR32Opnd, uimm10,	---	21597	GPR32Opnd, uimm10,	---
21598	/* RDDSP_MM */	---	21598	/* RDDSP_MM */	---
21599	GPR32Opnd, uimm7,	---	21599	GPR32Opnd, uimm7,	---
21600	/* RDHWR */	---	21600	/* RDHWR */	---
21601	GPR32Opnd, HWRegsOpnd, uimm8,	---	21601	GPR32Opnd, HWRegsOpnd, uimm8,	---
21602	/* RDHWR64 */	---	21602	/* RDHWR64 */	---
21603	GPR64Opnd, HWRegsOpnd, uimm8,	---	21603	GPR64Opnd, HWRegsOpnd, uimm8,	---
21604	/* RDHWR_MM */	---	21604	/* RDHWR_MM */	---
21605	GPR32Opnd, HWRegsOpnd, uimm8,	---	21605	GPR32Opnd, HWRegsOpnd, uimm8,	---
21606	/* RDHWR_MMR6 */	---	21606	/* RDHWR_MMR6 */	---
21607	GPR32Opnd, HWRegsOpnd, uimm3,	---	21607	GPR32Opnd, HWRegsOpnd, uimm3,	---
21608	/* RDPGPR_MMR6 */	---	21608	/* RDPGPR_MMR6 */	---
21609	GPR32Opnd, GPR32Opnd,	---	21609	GPR32Opnd, GPR32Opnd,	---
21610	/* RECIP_D32 */	---	21610	/* RECIP_D32 */	---
21611	AFGR64Opnd, AFGR64Opnd,	---	21611	AFGR64Opnd, AFGR64Opnd,	---
21612	/* RECIP_D32_MM */	---	21612	/* RECIP_D32_MM */	---
21613	AFGR64Opnd, AFGR64Opnd,	---	21613	AFGR64Opnd, AFGR64Opnd,	---
21614	/* RECIP_D64 */	---	21614	/* RECIP_D64 */	---
21615	FGR64Opnd, FGR64Opnd,	---	21615	FGR64Opnd, FGR64Opnd,	---
21616	/* RECIP_D64_MM */	---	21616	/* RECIP_D64_MM */	---
21617	FGR64Opnd, FGR64Opnd,	---	21617	FGR64Opnd, FGR64Opnd,	---
21618	/* RECIP_S */	---	21618	/* RECIP_S */	---
21619	FGR32Opnd, FGR32Opnd,	---	21619	FGR32Opnd, FGR32Opnd,	---
21620	/* RECIP_S_MM */	---	21620	/* RECIP_S_MM */	---
21621	FGR32Opnd, FGR32Opnd,	---	21621	FGR32Opnd, FGR32Opnd,	---
21622	/* REPLV_PH */	---	21622	/* REPLV_PH */	---
21623	DSPROpnd, GPR32Opnd,	---	21623	DSPROpnd, GPR32Opnd,	---
21624	/* REPLV_PH_MM */	---	21624	/* REPLV_PH_MM */	---
21625	DSPROpnd, GPR32Opnd,	---	21625	DSPROpnd, GPR32Opnd,	---
21626	/* REPLV_QB */	---	21626	/* REPLV_QB */	---
21627	DSPROpnd, GPR32Opnd,	---	21627	DSPROpnd, GPR32Opnd,	---
21628	/* REPLV_QB_MM */	---	21628	/* REPLV_QB_MM */	---
21629	DSPROpnd, GPR32Opnd,	---	21629	DSPROpnd, GPR32Opnd,	---
21630	/* REPL_PH */	---	21630	/* REPL_PH */	---
21631	DSPROpnd, simm10,	---	21631	DSPROpnd, simm10,	---
21632	/* REPL_PH_MM */	---	21632	/* REPL_PH_MM */	---
21633	DSPROpnd, simm10,	---	21633	DSPROpnd, simm10,	---
21634	/* REPL_QB */	---	21634	/* REPL_QB */	---
21635	DSPROpnd, uimm8,	---	21635	DSPROpnd, uimm8,	---
21636	/* REPL_QB_MM */	---	21636	/* REPL_QB_MM */	---
21637	DSPROpnd, uimm8,	---	21637	DSPROpnd, uimm8,	---
21638	/* RINT_D */	---	21638	/* RINT_D */	---
21639	FGR64Opnd, FGR64Opnd,	---	21639	FGR64Opnd, FGR64Opnd,	---
21640	/* RINT_D_MMR6 */	---	21640	/* RINT_D_MMR6 */	---
21641	FGR64Opnd, FGR64Opnd,	---	21641	FGR64Opnd, FGR64Opnd,	---
21642	/* RINT_S */	---	21642	/* RINT_S */	---
21643	FGR32Opnd, FGR32Opnd,	---	21643	FGR32Opnd, FGR32Opnd,	---
21644	/* RINT_S_MMR6 */	---	21644	/* RINT_S_MMR6 */	---
21645	FGR32Opnd, FGR32Opnd,	---	21645	FGR32Opnd, FGR32Opnd,	---
21646	/* ROTR */	---	21646	/* ROTR */	---
21647	GPR32Opnd, GPR32Opnd, uimm5,	---	21647	GPR32Opnd, GPR32Opnd, uimm5,	---
21648	/* ROTRV */	---	21648	/* ROTRV */	---
21649	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21649	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21650	/* ROTRV_MM */	---	21650	/* ROTRV_MM */	---
21651	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21651	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21652	/* ROTR_MM */	---	21652	/* ROTR_MM */	---
21653	GPR32Opnd, GPR32Opnd, uimm5,	---	21653	GPR32Opnd, GPR32Opnd, uimm5,	---
21654	/* ROUND_L_D64 */	---	21654	/* ROUND_L_D64 */	---
21655	FGR64Opnd, FGR64Opnd,	---	21655	FGR64Opnd, FGR64Opnd,	---
21656	/* ROUND_L_D_MMR6 */	---	21656	/* ROUND_L_D_MMR6 */	---
21657	FGR64Opnd, FGR64Opnd,	---	21657	FGR64Opnd, FGR64Opnd,	---
21658	/* ROUND_L_S */	---	21658	/* ROUND_L_S */	---
21659	FGR64Opnd, FGR32Opnd,	---	21659	FGR64Opnd, FGR32Opnd,	---
21660	/* ROUND_L_S_MMR6 */	---	21660	/* ROUND_L_S_MMR6 */	---
21661	FGR64Opnd, FGR32Opnd,	---	21661	FGR64Opnd, FGR32Opnd,	---
21662	/* ROUND_W_D32 */	---	21662	/* ROUND_W_D32 */	---
21663	FGR32Opnd, AFGR64Opnd,	---	21663	FGR32Opnd, AFGR64Opnd,	---
21664	/* ROUND_W_D64 */	---	21664	/* ROUND_W_D64 */	---
21665	FGR32Opnd, FGR64Opnd,	---	21665	FGR32Opnd, FGR64Opnd,	---
21666	/* ROUND_W_D_MMR6 */	---	21666	/* ROUND_W_D_MMR6 */	---
21667	FGR64Opnd, FGR64Opnd,	---	21667	FGR64Opnd, FGR64Opnd,	---
21668	/* ROUND_W_MM */	---	21668	/* ROUND_W_MM */	---
21669	FGR32Opnd, AFGR64Opnd,	---	21669	FGR32Opnd, AFGR64Opnd,	---
21670	/* ROUND_W_S */	---	21670	/* ROUND_W_S */	---
21671	FGR32Opnd, FGR32Opnd,	---	21671	FGR32Opnd, FGR32Opnd,	---
21672	/* ROUND_W_S_MM */	---	21672	/* ROUND_W_S_MM */	---
21673	FGR32Opnd, FGR32Opnd,	---	21673	FGR32Opnd, FGR32Opnd,	---
21674	/* ROUND_W_S_MMR6 */	---	21674	/* ROUND_W_S_MMR6 */	---
21675	FGR32Opnd, FGR32Opnd,	---	21675	FGR32Opnd, FGR32Opnd,	---
21676	/* RSQRT_D32 */	---	21676	/* RSQRT_D32 */	---
21677	AFGR64Opnd, AFGR64Opnd,	---	21677	AFGR64Opnd, AFGR64Opnd,	---
21678	/* RSQRT_D32_MM */	---	21678	/* RSQRT_D32_MM */	---
21679	AFGR64Opnd, AFGR64Opnd,	---	21679	AFGR64Opnd, AFGR64Opnd,	---
21680	/* RSQRT_D64 */	---	21680	/* RSQRT_D64 */	---
21681	FGR64Opnd, FGR64Opnd,	---	21681	FGR64Opnd, FGR64Opnd,	---
21682	/* RSQRT_D64_MM */	---	21682	/* RSQRT_D64_MM */	---
21683	FGR64Opnd, FGR64Opnd,	---	21683	FGR64Opnd, FGR64Opnd,	---
21684	/* RSQRT_S */	---	21684	/* RSQRT_S */	---
21685	FGR32Opnd, FGR32Opnd,	---	21685	FGR32Opnd, FGR32Opnd,	---
21686	/* RSQRT_S_MM */	---	21686	/* RSQRT_S_MM */	---
21687	FGR32Opnd, FGR32Opnd,	---	21687	FGR32Opnd, FGR32Opnd,	---
21688	/* Restore16 */	---	21688	/* Restore16 */	---
21689	/* RestoreX16 */	---	21689	/* RestoreX16 */	---
21690	/* SAA */	---	21690	/* SAA */	---
21691	GPR64Opnd, GPR64Opnd,	---	21691	GPR64Opnd, GPR64Opnd,	---
21692	/* SAAD */	---	21692	/* SAAD */	---
21693	GPR64Opnd, GPR64Opnd,	---	21693	GPR64Opnd, GPR64Opnd,	---
21694	/* SAT_S_B */	---	21694	/* SAT_S_B */	---
21695	MSA128BOpnd, MSA128BOpnd, uimm3,	---	21695	MSA128BOpnd, MSA128BOpnd, uimm3,	---
21696	/* SAT_S_D */	---	21696	/* SAT_S_D */	---
21697	MSA128DOpnd, MSA128DOpnd, uimm6,	---	21697	MSA128DOpnd, MSA128DOpnd, uimm6,	---
21698	/* SAT_S_H */	---	21698	/* SAT_S_H */	---
21699	MSA128HOpnd, MSA128HOpnd, uimm4,	---	21699	MSA128HOpnd, MSA128HOpnd, uimm4,	---
21700	/* SAT_S_W */	---	21700	/* SAT_S_W */	---
21701	MSA128WOpnd, MSA128WOpnd, uimm5,	---	21701	MSA128WOpnd, MSA128WOpnd, uimm5,	---
21702	/* SAT_U_B */	---	21702	/* SAT_U_B */	---
21703	MSA128BOpnd, MSA128BOpnd, uimm3,	---	21703	MSA128BOpnd, MSA128BOpnd, uimm3,	---
21704	/* SAT_U_D */	---	21704	/* SAT_U_D */	---
21705	MSA128DOpnd, MSA128DOpnd, uimm6,	---	21705	MSA128DOpnd, MSA128DOpnd, uimm6,	---
21706	/* SAT_U_H */	---	21706	/* SAT_U_H */	---
21707	MSA128HOpnd, MSA128HOpnd, uimm4,	---	21707	MSA128HOpnd, MSA128HOpnd, uimm4,	---
21708	/* SAT_U_W */	---	21708	/* SAT_U_W */	---
21709	MSA128WOpnd, MSA128WOpnd, uimm5,	---	21709	MSA128WOpnd, MSA128WOpnd, uimm5,	---
21710	/* SB */	---	21710	/* SB */	---
21711	GPR32Opnd, -1, simm16,	---	21711	GPR32Opnd, -1, simm16,	---
21712	/* SB16_MM */	---	21712	/* SB16_MM */	---
21713	GPRMM16OpndZero, -1, simm4,	---	21713	GPRMM16OpndZero, -1, simm4,	---
21714	/* SB16_MMR6 */	---	21714	/* SB16_MMR6 */	---
21715	GPRMM16OpndZero, -1, simm4,	---	21715	GPRMM16OpndZero, -1, simm4,	---
21716	/* SB64 */	---	21716	/* SB64 */	---
21717	GPR64Opnd, -1, simm16,	---	21717	GPR64Opnd, -1, simm16,	---
21718	/* SBE */	---	21718	/* SBE */	---
21719	GPR32Opnd, -1, simm9,	---	21719	GPR32Opnd, -1, simm9,	---
21720	/* SBE_MM */	---	21720	/* SBE_MM */	---
21721	GPR32Opnd, -1, simm9,	---	21721	GPR32Opnd, -1, simm9,	---
21722	/* SB_MM */	---	21722	/* SB_MM */	---
21723	GPR32Opnd, -1, simm16,	---	21723	GPR32Opnd, -1, simm16,	---
21724	/* SB_MMR6 */	---	21724	/* SB_MMR6 */	---
21725	GPR32Opnd, -1, simm16,	---	21725	GPR32Opnd, -1, simm16,	---
21726	/* SC */	---	21726	/* SC */	---
21727	GPR32Opnd, GPR32Opnd, -1, simm16,	---	21727	GPR32Opnd, GPR32Opnd, -1, simm16,	---
21728	/* SC64 */	---	21728	/* SC64 */	---
21729	GPR32Opnd, GPR32Opnd, -1, simm16,	---	21729	GPR32Opnd, GPR32Opnd, -1, simm16,	---
21730	/* SC64_R6 */	---	21730	/* SC64_R6 */	---
21731	GPR32Opnd, GPR32Opnd, -1, simm9,	---	21731	GPR32Opnd, GPR32Opnd, -1, simm9,	---
21732	/* SCD */	---	21732	/* SCD */	---
21733	GPR64Opnd, GPR64Opnd, -1, simm16,	---	21733	GPR64Opnd, GPR64Opnd, -1, simm16,	---
21734	/* SCD_R6 */	---	21734	/* SCD_R6 */	---
21735	GPR64Opnd, GPR64Opnd, -1, simm9,	---	21735	GPR64Opnd, GPR64Opnd, -1, simm9,	---
21736	/* SCE */	---	21736	/* SCE */	---
21737	GPR32Opnd, GPR32Opnd, -1, simm9,	---	21737	GPR32Opnd, GPR32Opnd, -1, simm9,	---
21738	/* SCE_MM */	---	21738	/* SCE_MM */	---
21739	GPR32Opnd, GPR32Opnd, -1, simm9,	---	21739	GPR32Opnd, GPR32Opnd, -1, simm9,	---
21740	/* SC_MM */	---	21740	/* SC_MM */	---
21741	GPR32Opnd, GPR32Opnd, -1, simm12,	---	21741	GPR32Opnd, GPR32Opnd, -1, simm12,	---
21742	/* SC_MMR6 */	---	21742	/* SC_MMR6 */	---
21743	GPR32Opnd, GPR32Opnd, -1, simm9,	---	21743	GPR32Opnd, GPR32Opnd, -1, simm9,	---
21744	/* SC_R6 */	---	21744	/* SC_R6 */	---
21745	GPR32Opnd, GPR32Opnd, -1, simm9,	---	21745	GPR32Opnd, GPR32Opnd, -1, simm9,	---
21746	/* SD */	---	21746	/* SD */	---
21747	GPR64Opnd, -1, simm16,	---	21747	GPR64Opnd, -1, simm16,	---
21748	/* SDBBP */	---	21748	/* SDBBP */	---
21749	uimm20,	---	21749	uimm20,	---
21750	/* SDBBP16_MM */	---	21750	/* SDBBP16_MM */	---
21751	uimm4,	---	21751	uimm4,	---
21752	/* SDBBP16_MMR6 */	---	21752	/* SDBBP16_MMR6 */	---
21753	uimm4,	---	21753	uimm4,	---
21754	/* SDBBP_MM */	---	21754	/* SDBBP_MM */	---
21755	uimm10,	---	21755	uimm10,	---
21756	/* SDBBP_MMR6 */	---	21756	/* SDBBP_MMR6 */	---
21757	uimm20,	---	21757	uimm20,	---
21758	/* SDBBP_R6 */	---	21758	/* SDBBP_R6 */	---
21759	uimm20,	---	21759	uimm20,	---
21760	/* SDC1 */	---	21760	/* SDC1 */	---
21761	AFGR64Opnd, -1, simm16,	---	21761	AFGR64Opnd, -1, simm16,	---
21762	/* SDC164 */	---	21762	/* SDC164 */	---
21763	FGR64Opnd, -1, simm16,	---	21763	FGR64Opnd, -1, simm16,	---
21764	/* SDC1_D64_MMR6 */	---	21764	/* SDC1_D64_MMR6 */	---
21765	FGR64Opnd, -1, simm16,	---	21765	FGR64Opnd, -1, simm16,	---
21766	/* SDC1_MM_D32 */	---	21766	/* SDC1_MM_D32 */	---
21767	AFGR64Opnd, -1, simm16,	---	21767	AFGR64Opnd, -1, simm16,	---
21768	/* SDC1_MM_D64 */	---	21768	/* SDC1_MM_D64 */	---
21769	FGR64Opnd, -1, simm16,	---	21769	FGR64Opnd, -1, simm16,	---
21770	/* SDC2 */	---	21770	/* SDC2 */	---
21771	COP2Opnd, -1, simm16,	---	21771	COP2Opnd, -1, simm16,	---
21772	/* SDC2_MMR6 */	---	21772	/* SDC2_MMR6 */	---
21773	COP2Opnd, GPR32, simm11,	---	21773	COP2Opnd, GPR32, simm11,	---
21774	/* SDC2_R6 */	---	21774	/* SDC2_R6 */	---
21775	COP2Opnd, -1, simm11,	---	21775	COP2Opnd, -1, simm11,	---
21776	/* SDC3 */	---	21776	/* SDC3 */	---
21777	COP3Opnd, -1, simm16,	---	21777	COP3Opnd, -1, simm16,	---
21778	/* SDIV */	---	21778	/* SDIV */	---
21779	GPR32Opnd, GPR32Opnd,	---	21779	GPR32Opnd, GPR32Opnd,	---
21780	/* SDIV_MM */	---	21780	/* SDIV_MM */	---
21781	GPR32Opnd, GPR32Opnd,	---	21781	GPR32Opnd, GPR32Opnd,	---
21782	/* SDL */	---	21782	/* SDL */	---
21783	GPR64Opnd, -1, simm16,	---	21783	GPR64Opnd, -1, simm16,	---
21784	/* SDR */	---	21784	/* SDR */	---
21785	GPR64Opnd, -1, simm16,	---	21785	GPR64Opnd, -1, simm16,	---
21786	/* SDXC1 */	---	21786	/* SDXC1 */	---
21787	AFGR64Opnd, -1, -1,	---	21787	AFGR64Opnd, -1, -1,	---
21788	/* SDXC164 */	---	21788	/* SDXC164 */	---
21789	FGR64Opnd, -1, -1,	---	21789	FGR64Opnd, -1, -1,	---
21790	/* SEB */	---	21790	/* SEB */	---
21791	GPR32Opnd, GPR32Opnd,	---	21791	GPR32Opnd, GPR32Opnd,	---
21792	/* SEB64 */	---	21792	/* SEB64 */	---
21793	GPR64Opnd, GPR64Opnd,	---	21793	GPR64Opnd, GPR64Opnd,	---
21794	/* SEB_MM */	---	21794	/* SEB_MM */	---
21795	GPR32Opnd, GPR32Opnd,	---	21795	GPR32Opnd, GPR32Opnd,	---
21796	/* SEH */	---	21796	/* SEH */	---
21797	GPR32Opnd, GPR32Opnd,	---	21797	GPR32Opnd, GPR32Opnd,	---
21798	/* SEH64 */	---	21798	/* SEH64 */	---
21799	GPR64Opnd, GPR64Opnd,	---	21799	GPR64Opnd, GPR64Opnd,	---
21800	/* SEH_MM */	---	21800	/* SEH_MM */	---
21801	GPR32Opnd, GPR32Opnd,	---	21801	GPR32Opnd, GPR32Opnd,	---
21802	/* SELEQZ */	---	21802	/* SELEQZ */	---
21803	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21803	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21804	/* SELEQZ64 */	---	21804	/* SELEQZ64 */	---
21805	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21805	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21806	/* SELEQZ_D */	---	21806	/* SELEQZ_D */	---
21807	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21807	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21808	/* SELEQZ_D_MMR6 */	---	21808	/* SELEQZ_D_MMR6 */	---
21809	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21809	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21810	/* SELEQZ_MMR6 */	---	21810	/* SELEQZ_MMR6 */	---
21811	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21811	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21812	/* SELEQZ_S */	---	21812	/* SELEQZ_S */	---
21813	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21813	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21814	/* SELEQZ_S_MMR6 */	---	21814	/* SELEQZ_S_MMR6 */	---
21815	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21815	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21816	/* SELNEZ */	---	21816	/* SELNEZ */	---
21817	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21817	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21818	/* SELNEZ64 */	---	21818	/* SELNEZ64 */	---
21819	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21819	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21820	/* SELNEZ_D */	---	21820	/* SELNEZ_D */	---
21821	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21821	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21822	/* SELNEZ_D_MMR6 */	---	21822	/* SELNEZ_D_MMR6 */	---
21823	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21823	FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21824	/* SELNEZ_MMR6 */	---	21824	/* SELNEZ_MMR6 */	---
21825	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21825	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21826	/* SELNEZ_S */	---	21826	/* SELNEZ_S */	---
21827	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21827	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21828	/* SELNEZ_S_MMR6 */	---	21828	/* SELNEZ_S_MMR6 */	---
21829	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---	21829	FGR32Opnd, FGR32Opnd, FGR32Opnd,	---
21830	/* SEL_D */	---	21830	/* SEL_D */	---
21831	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21831	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21832	/* SEL_D_MMR6 */	---	21832	/* SEL_D_MMR6 */	---
21833	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---	21833	FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,	---
21834	/* SEL_S */	---	21834	/* SEL_S */	---
21835	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	21835	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
21836	/* SEL_S_MMR6 */	---	21836	/* SEL_S_MMR6 */	---
21837	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---	21837	FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,	---
21838	/* SEQ */	---	21838	/* SEQ */	---
21839	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	21839	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
21840	/* SEQi */	---	21840	/* SEQi */	---
21841	GPR64Opnd, GPR64Opnd, simm10_64,	---	21841	GPR64Opnd, GPR64Opnd, simm10_64,	---
21842	/* SH */	---	21842	/* SH */	---
21843	GPR32Opnd, -1, simm16,	---	21843	GPR32Opnd, -1, simm16,	---
21844	/* SH16_MM */	---	21844	/* SH16_MM */	---
21845	GPRMM16OpndZero, -1, simm4,	---	21845	GPRMM16OpndZero, -1, simm4,	---
21846	/* SH16_MMR6 */	---	21846	/* SH16_MMR6 */	---
21847	GPRMM16OpndZero, -1, simm4,	---	21847	GPRMM16OpndZero, -1, simm4,	---
21848	/* SH64 */	---	21848	/* SH64 */	---
21849	GPR64Opnd, -1, simm16,	---	21849	GPR64Opnd, -1, simm16,	---
21850	/* SHE */	---	21850	/* SHE */	---
21851	GPR32Opnd, -1, simm9,	---	21851	GPR32Opnd, -1, simm9,	---
21852	/* SHE_MM */	---	21852	/* SHE_MM */	---
21853	GPR32Opnd, -1, simm9,	---	21853	GPR32Opnd, -1, simm9,	---
21854	/* SHF_B */	---	21854	/* SHF_B */	---
21855	MSA128BOpnd, MSA128BOpnd, uimm8,	---	21855	MSA128BOpnd, MSA128BOpnd, uimm8,	---
21856	/* SHF_H */	---	21856	/* SHF_H */	---
21857	MSA128HOpnd, MSA128HOpnd, uimm8,	---	21857	MSA128HOpnd, MSA128HOpnd, uimm8,	---
21858	/* SHF_W */	---	21858	/* SHF_W */	---
21859	MSA128WOpnd, MSA128WOpnd, uimm8,	---	21859	MSA128WOpnd, MSA128WOpnd, uimm8,	---
21860	/* SHILO */	---	21860	/* SHILO */	---
21861	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	---	21861	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	---
21862	/* SHILOV */	---	21862	/* SHILOV */	---
21863	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---	21863	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---
21864	/* SHILOV_MM */	---	21864	/* SHILOV_MM */	---
21865	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---	21865	ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,	---
21866	/* SHILO_MM */	---	21866	/* SHILO_MM */	---
21867	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	---	21867	ACC64DSPOpnd, simm6, ACC64DSPOpnd,	---
21868	/* SHLLV_PH */	---	21868	/* SHLLV_PH */	---
21869	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21869	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21870	/* SHLLV_PH_MM */	---	21870	/* SHLLV_PH_MM */	---
21871	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21871	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21872	/* SHLLV_QB */	---	21872	/* SHLLV_QB */	---
21873	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21873	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21874	/* SHLLV_QB_MM */	---	21874	/* SHLLV_QB_MM */	---
21875	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21875	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21876	/* SHLLV_S_PH */	---	21876	/* SHLLV_S_PH */	---
21877	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21877	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21878	/* SHLLV_S_PH_MM */	---	21878	/* SHLLV_S_PH_MM */	---
21879	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21879	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21880	/* SHLLV_S_W */	---	21880	/* SHLLV_S_W */	---
21881	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21881	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21882	/* SHLLV_S_W_MM */	---	21882	/* SHLLV_S_W_MM */	---
21883	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21883	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21884	/* SHLL_PH */	---	21884	/* SHLL_PH */	---
21885	DSPROpnd, DSPROpnd, uimm4,	---	21885	DSPROpnd, DSPROpnd, uimm4,	---
21886	/* SHLL_PH_MM */	---	21886	/* SHLL_PH_MM */	---
21887	DSPROpnd, DSPROpnd, uimm4,	---	21887	DSPROpnd, DSPROpnd, uimm4,	---
21888	/* SHLL_QB */	---	21888	/* SHLL_QB */	---
21889	DSPROpnd, DSPROpnd, uimm3,	---	21889	DSPROpnd, DSPROpnd, uimm3,	---
21890	/* SHLL_QB_MM */	---	21890	/* SHLL_QB_MM */	---
21891	DSPROpnd, DSPROpnd, uimm3,	---	21891	DSPROpnd, DSPROpnd, uimm3,	---
21892	/* SHLL_S_PH */	---	21892	/* SHLL_S_PH */	---
21893	DSPROpnd, DSPROpnd, uimm4,	---	21893	DSPROpnd, DSPROpnd, uimm4,	---
21894	/* SHLL_S_PH_MM */	---	21894	/* SHLL_S_PH_MM */	---
21895	DSPROpnd, DSPROpnd, uimm4,	---	21895	DSPROpnd, DSPROpnd, uimm4,	---
21896	/* SHLL_S_W */	---	21896	/* SHLL_S_W */	---
21897	GPR32Opnd, GPR32Opnd, uimm5,	---	21897	GPR32Opnd, GPR32Opnd, uimm5,	---
21898	/* SHLL_S_W_MM */	---	21898	/* SHLL_S_W_MM */	---
21899	GPR32Opnd, GPR32Opnd, uimm5,	---	21899	GPR32Opnd, GPR32Opnd, uimm5,	---
21900	/* SHRAV_PH */	---	21900	/* SHRAV_PH */	---
21901	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21901	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21902	/* SHRAV_PH_MM */	---	21902	/* SHRAV_PH_MM */	---
21903	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21903	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21904	/* SHRAV_QB */	---	21904	/* SHRAV_QB */	---
21905	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21905	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21906	/* SHRAV_QB_MMR2 */	---	21906	/* SHRAV_QB_MMR2 */	---
21907	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21907	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21908	/* SHRAV_R_PH */	---	21908	/* SHRAV_R_PH */	---
21909	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21909	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21910	/* SHRAV_R_PH_MM */	---	21910	/* SHRAV_R_PH_MM */	---
21911	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21911	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21912	/* SHRAV_R_QB */	---	21912	/* SHRAV_R_QB */	---
21913	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21913	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21914	/* SHRAV_R_QB_MMR2 */	---	21914	/* SHRAV_R_QB_MMR2 */	---
21915	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21915	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21916	/* SHRAV_R_W */	---	21916	/* SHRAV_R_W */	---
21917	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21917	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21918	/* SHRAV_R_W_MM */	---	21918	/* SHRAV_R_W_MM */	---
21919	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21919	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
21920	/* SHRA_PH */	---	21920	/* SHRA_PH */	---
21921	DSPROpnd, DSPROpnd, uimm4,	---	21921	DSPROpnd, DSPROpnd, uimm4,	---
21922	/* SHRA_PH_MM */	---	21922	/* SHRA_PH_MM */	---
21923	DSPROpnd, DSPROpnd, uimm4,	---	21923	DSPROpnd, DSPROpnd, uimm4,	---
21924	/* SHRA_QB */	---	21924	/* SHRA_QB */	---
21925	DSPROpnd, DSPROpnd, uimm3,	---	21925	DSPROpnd, DSPROpnd, uimm3,	---
21926	/* SHRA_QB_MMR2 */	---	21926	/* SHRA_QB_MMR2 */	---
21927	DSPROpnd, DSPROpnd, uimm3,	---	21927	DSPROpnd, DSPROpnd, uimm3,	---
21928	/* SHRA_R_PH */	---	21928	/* SHRA_R_PH */	---
21929	DSPROpnd, DSPROpnd, uimm4,	---	21929	DSPROpnd, DSPROpnd, uimm4,	---
21930	/* SHRA_R_PH_MM */	---	21930	/* SHRA_R_PH_MM */	---
21931	DSPROpnd, DSPROpnd, uimm4,	---	21931	DSPROpnd, DSPROpnd, uimm4,	---
21932	/* SHRA_R_QB */	---	21932	/* SHRA_R_QB */	---
21933	DSPROpnd, DSPROpnd, uimm3,	---	21933	DSPROpnd, DSPROpnd, uimm3,	---
21934	/* SHRA_R_QB_MMR2 */	---	21934	/* SHRA_R_QB_MMR2 */	---
21935	DSPROpnd, DSPROpnd, uimm3,	---	21935	DSPROpnd, DSPROpnd, uimm3,	---
21936	/* SHRA_R_W */	---	21936	/* SHRA_R_W */	---
21937	GPR32Opnd, GPR32Opnd, uimm5,	---	21937	GPR32Opnd, GPR32Opnd, uimm5,	---
21938	/* SHRA_R_W_MM */	---	21938	/* SHRA_R_W_MM */	---
21939	GPR32Opnd, GPR32Opnd, uimm5,	---	21939	GPR32Opnd, GPR32Opnd, uimm5,	---
21940	/* SHRLV_PH */	---	21940	/* SHRLV_PH */	---
21941	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21941	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21942	/* SHRLV_PH_MMR2 */	---	21942	/* SHRLV_PH_MMR2 */	---
21943	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21943	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21944	/* SHRLV_QB */	---	21944	/* SHRLV_QB */	---
21945	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21945	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21946	/* SHRLV_QB_MM */	---	21946	/* SHRLV_QB_MM */	---
21947	DSPROpnd, DSPROpnd, GPR32Opnd,	---	21947	DSPROpnd, DSPROpnd, GPR32Opnd,	---
21948	/* SHRL_PH */	---	21948	/* SHRL_PH */	---
21949	DSPROpnd, DSPROpnd, uimm4,	---	21949	DSPROpnd, DSPROpnd, uimm4,	---
21950	/* SHRL_PH_MMR2 */	---	21950	/* SHRL_PH_MMR2 */	---
21951	DSPROpnd, DSPROpnd, uimm4,	---	21951	DSPROpnd, DSPROpnd, uimm4,	---
21952	/* SHRL_QB */	---	21952	/* SHRL_QB */	---
21953	DSPROpnd, DSPROpnd, uimm3,	---	21953	DSPROpnd, DSPROpnd, uimm3,	---
21954	/* SHRL_QB_MM */	---	21954	/* SHRL_QB_MM */	---
21955	DSPROpnd, DSPROpnd, uimm3,	---	21955	DSPROpnd, DSPROpnd, uimm3,	---
21956	/* SH_MM */	---	21956	/* SH_MM */	---
21957	GPR32Opnd, -1, simm16,	---	21957	GPR32Opnd, -1, simm16,	---
21958	/* SH_MMR6 */	---	21958	/* SH_MMR6 */	---
21959	GPR32Opnd, -1, simm16,	---	21959	GPR32Opnd, -1, simm16,	---
21960	/* SIGRIE */	---	21960	/* SIGRIE */	---
21961	uimm16,	---	21961	uimm16,	---
21962	/* SIGRIE_MMR6 */	---	21962	/* SIGRIE_MMR6 */	---
21963	uimm16,	---	21963	uimm16,	---
21964	/* SLDI_B */	---	21964	/* SLDI_B */	---
21965	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,	---	21965	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,	---
21966	/* SLDI_D */	---	21966	/* SLDI_D */	---
21967	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,	---	21967	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,	---
21968	/* SLDI_H */	---	21968	/* SLDI_H */	---
21969	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,	---	21969	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,	---
21970	/* SLDI_W */	---	21970	/* SLDI_W */	---
21971	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,	---	21971	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,	---
21972	/* SLD_B */	---	21972	/* SLD_B */	---
21973	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	---	21973	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	---
21974	/* SLD_D */	---	21974	/* SLD_D */	---
21975	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	---	21975	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	---
21976	/* SLD_H */	---	21976	/* SLD_H */	---
21977	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	---	21977	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	---
21978	/* SLD_W */	---	21978	/* SLD_W */	---
21979	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	---	21979	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	---
21980	/* SLL */	---	21980	/* SLL */	---
21981	GPR32Opnd, GPR32Opnd, uimm5,	---	21981	GPR32Opnd, GPR32Opnd, uimm5,	---
21982	/* SLL16_MM */	---	21982	/* SLL16_MM */	---
21983	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---	21983	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---
21984	/* SLL16_MMR6 */	---	21984	/* SLL16_MMR6 */	---
21985	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---	21985	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---
21986	/* SLL64_32 */	---	21986	/* SLL64_32 */	---
21987	GPR64, GPR32,	---	21987	GPR64, GPR32,	---
21988	/* SLL64_64 */	---	21988	/* SLL64_64 */	---
21989	GPR64, GPR64,	---	21989	GPR64, GPR64,	---
21990	/* SLLI_B */	---	21990	/* SLLI_B */	---
21991	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	21991	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
21992	/* SLLI_D */	---	21992	/* SLLI_D */	---
21993	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	21993	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
21994	/* SLLI_H */	---	21994	/* SLLI_H */	---
21995	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	21995	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
21996	/* SLLI_W */	---	21996	/* SLLI_W */	---
21997	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	21997	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
21998	/* SLLV */	---	21998	/* SLLV */	---
21999	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	21999	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22000	/* SLLV_MM */	---	22000	/* SLLV_MM */	---
22001	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22001	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22002	/* SLL_B */	---	22002	/* SLL_B */	---
22003	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22003	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22004	/* SLL_D */	---	22004	/* SLL_D */	---
22005	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22005	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22006	/* SLL_H */	---	22006	/* SLL_H */	---
22007	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22007	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22008	/* SLL_MM */	---	22008	/* SLL_MM */	---
22009	GPR32Opnd, GPR32Opnd, uimm5,	---	22009	GPR32Opnd, GPR32Opnd, uimm5,	---
22010	/* SLL_MMR6 */	---	22010	/* SLL_MMR6 */	---
22011	GPR32Opnd, GPR32Opnd, uimm5,	---	22011	GPR32Opnd, GPR32Opnd, uimm5,	---
22012	/* SLL_W */	---	22012	/* SLL_W */	---
22013	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22013	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22014	/* SLT */	---	22014	/* SLT */	---
22015	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22015	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22016	/* SLT64 */	---	22016	/* SLT64 */	---
22017	GPR32Opnd, GPR64Opnd, GPR64Opnd,	---	22017	GPR32Opnd, GPR64Opnd, GPR64Opnd,	---
22018	/* SLT_MM */	---	22018	/* SLT_MM */	---
22019	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22019	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22020	/* SLTi */	---	22020	/* SLTi */	---
22021	GPR32Opnd, GPR32Opnd, simm16,	---	22021	GPR32Opnd, GPR32Opnd, simm16,	---
22022	/* SLTi64 */	---	22022	/* SLTi64 */	---
22023	GPR32Opnd, GPR64Opnd, simm16_64,	---	22023	GPR32Opnd, GPR64Opnd, simm16_64,	---
22024	/* SLTi_MM */	---	22024	/* SLTi_MM */	---
22025	GPR32Opnd, GPR32Opnd, simm16,	---	22025	GPR32Opnd, GPR32Opnd, simm16,	---
22026	/* SLTiu */	---	22026	/* SLTiu */	---
22027	GPR32Opnd, GPR32Opnd, simm16,	---	22027	GPR32Opnd, GPR32Opnd, simm16,	---
22028	/* SLTiu64 */	---	22028	/* SLTiu64 */	---
22029	GPR32Opnd, GPR64Opnd, simm16_64,	---	22029	GPR32Opnd, GPR64Opnd, simm16_64,	---
22030	/* SLTiu_MM */	---	22030	/* SLTiu_MM */	---
22031	GPR32Opnd, GPR32Opnd, simm16,	---	22031	GPR32Opnd, GPR32Opnd, simm16,	---
22032	/* SLTu */	---	22032	/* SLTu */	---
22033	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22033	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22034	/* SLTu64 */	---	22034	/* SLTu64 */	---
22035	GPR32Opnd, GPR64Opnd, GPR64Opnd,	---	22035	GPR32Opnd, GPR64Opnd, GPR64Opnd,	---
22036	/* SLTu_MM */	---	22036	/* SLTu_MM */	---
22037	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22037	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22038	/* SNE */	---	22038	/* SNE */	---
22039	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	22039	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
22040	/* SNEi */	---	22040	/* SNEi */	---
22041	GPR64Opnd, GPR64Opnd, simm10_64,	---	22041	GPR64Opnd, GPR64Opnd, simm10_64,	---
22042	/* SPLATI_B */	---	22042	/* SPLATI_B */	---
22043	MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,	---	22043	MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,	---
22044	/* SPLATI_D */	---	22044	/* SPLATI_D */	---
22045	MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,	---	22045	MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,	---
22046	/* SPLATI_H */	---	22046	/* SPLATI_H */	---
22047	MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,	---	22047	MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,	---
22048	/* SPLATI_W */	---	22048	/* SPLATI_W */	---
22049	MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,	---	22049	MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,	---
22050	/* SPLAT_B */	---	22050	/* SPLAT_B */	---
22051	MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	---	22051	MSA128BOpnd, MSA128BOpnd, GPR32Opnd,	---
22052	/* SPLAT_D */	---	22052	/* SPLAT_D */	---
22053	MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	---	22053	MSA128DOpnd, MSA128DOpnd, GPR32Opnd,	---
22054	/* SPLAT_H */	---	22054	/* SPLAT_H */	---
22055	MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	---	22055	MSA128HOpnd, MSA128HOpnd, GPR32Opnd,	---
22056	/* SPLAT_W */	---	22056	/* SPLAT_W */	---
22057	MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	---	22057	MSA128WOpnd, MSA128WOpnd, GPR32Opnd,	---
22058	/* SRA */	---	22058	/* SRA */	---
22059	GPR32Opnd, GPR32Opnd, uimm5,	---	22059	GPR32Opnd, GPR32Opnd, uimm5,	---
22060	/* SRAI_B */	---	22060	/* SRAI_B */	---
22061	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	22061	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
22062	/* SRAI_D */	---	22062	/* SRAI_D */	---
22063	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	22063	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
22064	/* SRAI_H */	---	22064	/* SRAI_H */	---
22065	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	22065	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
22066	/* SRAI_W */	---	22066	/* SRAI_W */	---
22067	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	22067	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
22068	/* SRARI_B */	---	22068	/* SRARI_B */	---
22069	MSA128BOpnd, MSA128BOpnd, uimm3,	---	22069	MSA128BOpnd, MSA128BOpnd, uimm3,	---
22070	/* SRARI_D */	---	22070	/* SRARI_D */	---
22071	MSA128DOpnd, MSA128DOpnd, uimm6,	---	22071	MSA128DOpnd, MSA128DOpnd, uimm6,	---
22072	/* SRARI_H */	---	22072	/* SRARI_H */	---
22073	MSA128HOpnd, MSA128HOpnd, uimm4,	---	22073	MSA128HOpnd, MSA128HOpnd, uimm4,	---
22074	/* SRARI_W */	---	22074	/* SRARI_W */	---
22075	MSA128WOpnd, MSA128WOpnd, uimm5,	---	22075	MSA128WOpnd, MSA128WOpnd, uimm5,	---
22076	/* SRAR_B */	---	22076	/* SRAR_B */	---
22077	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22077	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22078	/* SRAR_D */	---	22078	/* SRAR_D */	---
22079	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22079	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22080	/* SRAR_H */	---	22080	/* SRAR_H */	---
22081	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22081	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22082	/* SRAR_W */	---	22082	/* SRAR_W */	---
22083	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22083	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22084	/* SRAV */	---	22084	/* SRAV */	---
22085	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22085	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22086	/* SRAV_MM */	---	22086	/* SRAV_MM */	---
22087	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22087	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22088	/* SRA_B */	---	22088	/* SRA_B */	---
22089	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22089	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22090	/* SRA_D */	---	22090	/* SRA_D */	---
22091	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22091	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22092	/* SRA_H */	---	22092	/* SRA_H */	---
22093	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22093	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22094	/* SRA_MM */	---	22094	/* SRA_MM */	---
22095	GPR32Opnd, GPR32Opnd, uimm5,	---	22095	GPR32Opnd, GPR32Opnd, uimm5,	---
22096	/* SRA_W */	---	22096	/* SRA_W */	---
22097	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22097	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22098	/* SRL */	---	22098	/* SRL */	---
22099	GPR32Opnd, GPR32Opnd, uimm5,	---	22099	GPR32Opnd, GPR32Opnd, uimm5,	---
22100	/* SRL16_MM */	---	22100	/* SRL16_MM */	---
22101	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---	22101	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---
22102	/* SRL16_MMR6 */	---	22102	/* SRL16_MMR6 */	---
22103	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---	22103	GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,	---
22104	/* SRLI_B */	---	22104	/* SRLI_B */	---
22105	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---	22105	MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,	---
22106	/* SRLI_D */	---	22106	/* SRLI_D */	---
22107	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---	22107	MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,	---
22108	/* SRLI_H */	---	22108	/* SRLI_H */	---
22109	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---	22109	MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,	---
22110	/* SRLI_W */	---	22110	/* SRLI_W */	---
22111	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	22111	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
22112	/* SRLRI_B */	---	22112	/* SRLRI_B */	---
22113	MSA128BOpnd, MSA128BOpnd, uimm3,	---	22113	MSA128BOpnd, MSA128BOpnd, uimm3,	---
22114	/* SRLRI_D */	---	22114	/* SRLRI_D */	---
22115	MSA128DOpnd, MSA128DOpnd, uimm6,	---	22115	MSA128DOpnd, MSA128DOpnd, uimm6,	---
22116	/* SRLRI_H */	---	22116	/* SRLRI_H */	---
22117	MSA128HOpnd, MSA128HOpnd, uimm4,	---	22117	MSA128HOpnd, MSA128HOpnd, uimm4,	---
22118	/* SRLRI_W */	---	22118	/* SRLRI_W */	---
22119	MSA128WOpnd, MSA128WOpnd, uimm5,	---	22119	MSA128WOpnd, MSA128WOpnd, uimm5,	---
22120	/* SRLR_B */	---	22120	/* SRLR_B */	---
22121	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22121	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22122	/* SRLR_D */	---	22122	/* SRLR_D */	---
22123	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22123	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22124	/* SRLR_H */	---	22124	/* SRLR_H */	---
22125	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22125	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22126	/* SRLR_W */	---	22126	/* SRLR_W */	---
22127	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22127	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22128	/* SRLV */	---	22128	/* SRLV */	---
22129	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22129	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22130	/* SRLV_MM */	---	22130	/* SRLV_MM */	---
22131	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22131	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22132	/* SRL_B */	---	22132	/* SRL_B */	---
22133	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22133	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22134	/* SRL_D */	---	22134	/* SRL_D */	---
22135	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22135	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22136	/* SRL_H */	---	22136	/* SRL_H */	---
22137	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22137	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22138	/* SRL_MM */	---	22138	/* SRL_MM */	---
22139	GPR32Opnd, GPR32Opnd, uimm5,	---	22139	GPR32Opnd, GPR32Opnd, uimm5,	---
22140	/* SRL_W */	---	22140	/* SRL_W */	---
22141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22141	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22142	/* SSNOP */	---	22142	/* SSNOP */	---
22143	/* SSNOP_MM */	---	22143	/* SSNOP_MM */	---
22144	/* SSNOP_MMR6 */	---	22144	/* SSNOP_MMR6 */	---
22145	/* ST_B */	---	22145	/* ST_B */	---
22146	MSA128BOpnd, -1, simm10,	---	22146	MSA128BOpnd, -1, simm10,	---
22147	/* ST_D */	---	22147	/* ST_D */	---
22148	MSA128DOpnd, -1, simm10_lsl3,	---	22148	MSA128DOpnd, -1, simm10_lsl3,	---
22149	/* ST_H */	---	22149	/* ST_H */	---
22150	MSA128HOpnd, -1, simm10_lsl1,	---	22150	MSA128HOpnd, -1, simm10_lsl1,	---
22151	/* ST_W */	---	22151	/* ST_W */	---
22152	MSA128WOpnd, -1, simm10_lsl2,	---	22152	MSA128WOpnd, -1, simm10_lsl2,	---
22153	/* SUB */	---	22153	/* SUB */	---
22154	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22154	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22155	/* SUBQH_PH */	---	22155	/* SUBQH_PH */	---
22156	DSPROpnd, DSPROpnd, DSPROpnd,	---	22156	DSPROpnd, DSPROpnd, DSPROpnd,	---
22157	/* SUBQH_PH_MMR2 */	---	22157	/* SUBQH_PH_MMR2 */	---
22158	DSPROpnd, DSPROpnd, DSPROpnd,	---	22158	DSPROpnd, DSPROpnd, DSPROpnd,	---
22159	/* SUBQH_R_PH */	---	22159	/* SUBQH_R_PH */	---
22160	DSPROpnd, DSPROpnd, DSPROpnd,	---	22160	DSPROpnd, DSPROpnd, DSPROpnd,	---
22161	/* SUBQH_R_PH_MMR2 */	---	22161	/* SUBQH_R_PH_MMR2 */	---
22162	DSPROpnd, DSPROpnd, DSPROpnd,	---	22162	DSPROpnd, DSPROpnd, DSPROpnd,	---
22163	/* SUBQH_R_W */	---	22163	/* SUBQH_R_W */	---
22164	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22164	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22165	/* SUBQH_R_W_MMR2 */	---	22165	/* SUBQH_R_W_MMR2 */	---
22166	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22166	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22167	/* SUBQH_W */	---	22167	/* SUBQH_W */	---
22168	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22168	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22169	/* SUBQH_W_MMR2 */	---	22169	/* SUBQH_W_MMR2 */	---
22170	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22170	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22171	/* SUBQ_PH */	---	22171	/* SUBQ_PH */	---
22172	DSPROpnd, DSPROpnd, DSPROpnd,	---	22172	DSPROpnd, DSPROpnd, DSPROpnd,	---
22173	/* SUBQ_PH_MM */	---	22173	/* SUBQ_PH_MM */	---
22174	DSPROpnd, DSPROpnd, DSPROpnd,	---	22174	DSPROpnd, DSPROpnd, DSPROpnd,	---
22175	/* SUBQ_S_PH */	---	22175	/* SUBQ_S_PH */	---
22176	DSPROpnd, DSPROpnd, DSPROpnd,	---	22176	DSPROpnd, DSPROpnd, DSPROpnd,	---
22177	/* SUBQ_S_PH_MM */	---	22177	/* SUBQ_S_PH_MM */	---
22178	DSPROpnd, DSPROpnd, DSPROpnd,	---	22178	DSPROpnd, DSPROpnd, DSPROpnd,	---
22179	/* SUBQ_S_W */	---	22179	/* SUBQ_S_W */	---
22180	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22180	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22181	/* SUBQ_S_W_MM */	---	22181	/* SUBQ_S_W_MM */	---
22182	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22182	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22183	/* SUBSUS_U_B */	---	22183	/* SUBSUS_U_B */	---
22184	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22184	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22185	/* SUBSUS_U_D */	---	22185	/* SUBSUS_U_D */	---
22186	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22186	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22187	/* SUBSUS_U_H */	---	22187	/* SUBSUS_U_H */	---
22188	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22188	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22189	/* SUBSUS_U_W */	---	22189	/* SUBSUS_U_W */	---
22190	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22190	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22191	/* SUBSUU_S_B */	---	22191	/* SUBSUU_S_B */	---
22192	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22192	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22193	/* SUBSUU_S_D */	---	22193	/* SUBSUU_S_D */	---
22194	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22194	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22195	/* SUBSUU_S_H */	---	22195	/* SUBSUU_S_H */	---
22196	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22196	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22197	/* SUBSUU_S_W */	---	22197	/* SUBSUU_S_W */	---
22198	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22198	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22199	/* SUBS_S_B */	---	22199	/* SUBS_S_B */	---
22200	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22200	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22201	/* SUBS_S_D */	---	22201	/* SUBS_S_D */	---
22202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22202	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22203	/* SUBS_S_H */	---	22203	/* SUBS_S_H */	---
22204	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22204	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22205	/* SUBS_S_W */	---	22205	/* SUBS_S_W */	---
22206	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22206	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22207	/* SUBS_U_B */	---	22207	/* SUBS_U_B */	---
22208	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22208	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22209	/* SUBS_U_D */	---	22209	/* SUBS_U_D */	---
22210	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22210	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22211	/* SUBS_U_H */	---	22211	/* SUBS_U_H */	---
22212	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22212	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22213	/* SUBS_U_W */	---	22213	/* SUBS_U_W */	---
22214	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22214	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22215	/* SUBU16_MM */	---	22215	/* SUBU16_MM */	---
22216	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	22216	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
22217	/* SUBU16_MMR6 */	---	22217	/* SUBU16_MMR6 */	---
22218	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	22218	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
22219	/* SUBUH_QB */	---	22219	/* SUBUH_QB */	---
22220	DSPROpnd, DSPROpnd, DSPROpnd,	---	22220	DSPROpnd, DSPROpnd, DSPROpnd,	---
22221	/* SUBUH_QB_MMR2 */	---	22221	/* SUBUH_QB_MMR2 */	---
22222	DSPROpnd, DSPROpnd, DSPROpnd,	---	22222	DSPROpnd, DSPROpnd, DSPROpnd,	---
22223	/* SUBUH_R_QB */	---	22223	/* SUBUH_R_QB */	---
22224	DSPROpnd, DSPROpnd, DSPROpnd,	---	22224	DSPROpnd, DSPROpnd, DSPROpnd,	---
22225	/* SUBUH_R_QB_MMR2 */	---	22225	/* SUBUH_R_QB_MMR2 */	---
22226	DSPROpnd, DSPROpnd, DSPROpnd,	---	22226	DSPROpnd, DSPROpnd, DSPROpnd,	---
22227	/* SUBU_MMR6 */	---	22227	/* SUBU_MMR6 */	---
22228	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22228	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22229	/* SUBU_PH */	---	22229	/* SUBU_PH */	---
22230	DSPROpnd, DSPROpnd, DSPROpnd,	---	22230	DSPROpnd, DSPROpnd, DSPROpnd,	---
22231	/* SUBU_PH_MMR2 */	---	22231	/* SUBU_PH_MMR2 */	---
22232	DSPROpnd, DSPROpnd, DSPROpnd,	---	22232	DSPROpnd, DSPROpnd, DSPROpnd,	---
22233	/* SUBU_QB */	---	22233	/* SUBU_QB */	---
22234	DSPROpnd, DSPROpnd, DSPROpnd,	---	22234	DSPROpnd, DSPROpnd, DSPROpnd,	---
22235	/* SUBU_QB_MM */	---	22235	/* SUBU_QB_MM */	---
22236	DSPROpnd, DSPROpnd, DSPROpnd,	---	22236	DSPROpnd, DSPROpnd, DSPROpnd,	---
22237	/* SUBU_S_PH */	---	22237	/* SUBU_S_PH */	---
22238	DSPROpnd, DSPROpnd, DSPROpnd,	---	22238	DSPROpnd, DSPROpnd, DSPROpnd,	---
22239	/* SUBU_S_PH_MMR2 */	---	22239	/* SUBU_S_PH_MMR2 */	---
22240	DSPROpnd, DSPROpnd, DSPROpnd,	---	22240	DSPROpnd, DSPROpnd, DSPROpnd,	---
22241	/* SUBU_S_QB */	---	22241	/* SUBU_S_QB */	---
22242	DSPROpnd, DSPROpnd, DSPROpnd,	---	22242	DSPROpnd, DSPROpnd, DSPROpnd,	---
22243	/* SUBU_S_QB_MM */	---	22243	/* SUBU_S_QB_MM */	---
22244	DSPROpnd, DSPROpnd, DSPROpnd,	---	22244	DSPROpnd, DSPROpnd, DSPROpnd,	---
22245	/* SUBVI_B */	---	22245	/* SUBVI_B */	---
22246	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---	22246	MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,	---
22247	/* SUBVI_D */	---	22247	/* SUBVI_D */	---
22248	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---	22248	MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,	---
22249	/* SUBVI_H */	---	22249	/* SUBVI_H */	---
22250	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---	22250	MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,	---
22251	/* SUBVI_W */	---	22251	/* SUBVI_W */	---
22252	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---	22252	MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,	---
22253	/* SUBV_B */	---	22253	/* SUBV_B */	---
22254	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22254	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22255	/* SUBV_D */	---	22255	/* SUBV_D */	---
22256	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22256	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22257	/* SUBV_H */	---	22257	/* SUBV_H */	---
22258	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22258	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22259	/* SUBV_W */	---	22259	/* SUBV_W */	---
22260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22260	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22261	/* SUB_MM */	---	22261	/* SUB_MM */	---
22262	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22262	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22263	/* SUB_MMR6 */	---	22263	/* SUB_MMR6 */	---
22264	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22264	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22265	/* SUBu */	---	22265	/* SUBu */	---
22266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22266	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22267	/* SUBu_MM */	---	22267	/* SUBu_MM */	---
22268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22268	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22269	/* SUXC1 */	---	22269	/* SUXC1 */	---
22270	AFGR64Opnd, -1, -1,	---	22270	AFGR64Opnd, -1, -1,	---
22271	/* SUXC164 */	---	22271	/* SUXC164 */	---
22272	FGR64Opnd, -1, -1,	---	22272	FGR64Opnd, -1, -1,	---
22273	/* SUXC1_MM */	---	22273	/* SUXC1_MM */	---
22274	FGR64Opnd, -1, -1,	---	22274	FGR64Opnd, -1, -1,	---
22275	/* SW */	---	22275	/* SW */	---
22276	GPR32Opnd, -1, simm16,	---	22276	GPR32Opnd, -1, simm16,	---
22277	/* SW16_MM */	---	22277	/* SW16_MM */	---
22278	GPRMM16OpndZero, -1, simm4,	---	22278	GPRMM16OpndZero, -1, simm4,	---
22279	/* SW16_MMR6 */	---	22279	/* SW16_MMR6 */	---
22280	GPRMM16OpndZero, -1, simm4,	---	22280	GPRMM16OpndZero, -1, simm4,	---
22281	/* SW64 */	---	22281	/* SW64 */	---
22282	GPR64Opnd, -1, simm16,	---	22282	GPR64Opnd, -1, simm16,	---
22283	/* SWC1 */	---	22283	/* SWC1 */	---
22284	FGR32Opnd, -1, simm16,	---	22284	FGR32Opnd, -1, simm16,	---
22285	/* SWC1_MM */	---	22285	/* SWC1_MM */	---
22286	FGR32Opnd, -1, simm16,	---	22286	FGR32Opnd, -1, simm16,	---
22287	/* SWC2 */	---	22287	/* SWC2 */	---
22288	COP2Opnd, -1, simm16,	---	22288	COP2Opnd, -1, simm16,	---
22289	/* SWC2_MMR6 */	---	22289	/* SWC2_MMR6 */	---
22290	COP2Opnd, GPR32, simm11,	---	22290	COP2Opnd, GPR32, simm11,	---
22291	/* SWC2_R6 */	---	22291	/* SWC2_R6 */	---
22292	COP2Opnd, -1, simm11,	---	22292	COP2Opnd, -1, simm11,	---
22293	/* SWC3 */	---	22293	/* SWC3 */	---
22294	COP3Opnd, -1, simm16,	---	22294	COP3Opnd, -1, simm16,	---
22295	/* SWDSP */	---	22295	/* SWDSP */	---
22296	DSPROpnd, -1, simm16,	---	22296	DSPROpnd, -1, simm16,	---
22297	/* SWDSP_MM */	---	22297	/* SWDSP_MM */	---
22298	DSPROpnd, -1, simm16,	---	22298	DSPROpnd, -1, simm16,	---
22299	/* SWE */	---	22299	/* SWE */	---
22300	GPR32Opnd, -1, simm9,	---	22300	GPR32Opnd, -1, simm9,	---
22301	/* SWE_MM */	---	22301	/* SWE_MM */	---
22302	GPR32Opnd, -1, simm9,	---	22302	GPR32Opnd, -1, simm9,	---
22303	/* SWL */	---	22303	/* SWL */	---
22304	GPR32Opnd, -1, simm16,	---	22304	GPR32Opnd, -1, simm16,	---
22305	/* SWL64 */	---	22305	/* SWL64 */	---
22306	GPR64Opnd, -1, simm16,	---	22306	GPR64Opnd, -1, simm16,	---
22307	/* SWLE */	---	22307	/* SWLE */	---
22308	GPR32Opnd, -1, simm9,	---	22308	GPR32Opnd, -1, simm9,	---
22309	/* SWLE_MM */	---	22309	/* SWLE_MM */	---
22310	GPR32Opnd, -1, simm9,	---	22310	GPR32Opnd, -1, simm9,	---
22311	/* SWL_MM */	---	22311	/* SWL_MM */	---
22312	GPR32Opnd, -1, simm12,	---	22312	GPR32Opnd, -1, simm12,	---
22313	/* SWM16_MM */	---	22313	/* SWM16_MM */	---
22314	reglist16, -1, uimm8,	---	22314	reglist16, -1, uimm8,	---
22315	/* SWM16_MMR6 */	---	22315	/* SWM16_MMR6 */	---
22316	reglist16, -1, uimm8,	---	22316	reglist16, -1, uimm8,	---
22317	/* SWM32_MM */	---	22317	/* SWM32_MM */	---
22318	reglist, -1, simm12,	---	22318	reglist, -1, simm12,	---
22319	/* SWP_MM */	---	22319	/* SWP_MM */	---
22320	GPR32Opnd, GPR32Opnd, -1, simm12,	---	22320	GPR32Opnd, GPR32Opnd, -1, simm12,	---
22321	/* SWR */	---	22321	/* SWR */	---
22322	GPR32Opnd, -1, simm16,	---	22322	GPR32Opnd, -1, simm16,	---
22323	/* SWR64 */	---	22323	/* SWR64 */	---
22324	GPR64Opnd, -1, simm16,	---	22324	GPR64Opnd, -1, simm16,	---
22325	/* SWRE */	---	22325	/* SWRE */	---
22326	GPR32Opnd, -1, simm9,	---	22326	GPR32Opnd, -1, simm9,	---
22327	/* SWRE_MM */	---	22327	/* SWRE_MM */	---
22328	GPR32Opnd, -1, simm9,	---	22328	GPR32Opnd, -1, simm9,	---
22329	/* SWR_MM */	---	22329	/* SWR_MM */	---
22330	GPR32Opnd, -1, simm12,	---	22330	GPR32Opnd, -1, simm12,	---
22331	/* SWSP_MM */	---	22331	/* SWSP_MM */	---
22332	GPR32Opnd, -1, simm5,	---	22332	GPR32Opnd, -1, simm5,	---
22333	/* SWSP_MMR6 */	---	22333	/* SWSP_MMR6 */	---
22334	GPR32Opnd, -1, simm5,	---	22334	GPR32Opnd, -1, simm5,	---
22335	/* SWXC1 */	---	22335	/* SWXC1 */	---
22336	FGR32Opnd, -1, -1,	---	22336	FGR32Opnd, -1, -1,	---
22337	/* SWXC1_MM */	---	22337	/* SWXC1_MM */	---
22338	FGR32Opnd, -1, -1,	---	22338	FGR32Opnd, -1, -1,	---
22339	/* SW_MM */	---	22339	/* SW_MM */	---
22340	GPR32Opnd, -1, simm16,	---	22340	GPR32Opnd, -1, simm16,	---
22341	/* SW_MMR6 */	---	22341	/* SW_MMR6 */	---
22342	GPR32Opnd, -1, simm16,	---	22342	GPR32Opnd, -1, simm16,	---
22343	/* SYNC */	---	22343	/* SYNC */	---
22344	uimm5,	---	22344	uimm5,	---
22345	/* SYNCI */	---	22345	/* SYNCI */	---
22346	-1, simm16,	---	22346	-1, simm16,	---
22347	/* SYNCI_MM */	---	22347	/* SYNCI_MM */	---
22348	-1, simm16,	---	22348	-1, simm16,	---
22349	/* SYNCI_MMR6 */	---	22349	/* SYNCI_MMR6 */	---
22350	-1, simm16,	---	22350	-1, simm16,	---
22351	/* SYNC_MM */	---	22351	/* SYNC_MM */	---
22352	uimm5,	---	22352	uimm5,	---
22353	/* SYNC_MMR6 */	---	22353	/* SYNC_MMR6 */	---
22354	uimm5,	---	22354	uimm5,	---
22355	/* SYSCALL */	---	22355	/* SYSCALL */	---
22356	uimm20,	---	22356	uimm20,	---
22357	/* SYSCALL_MM */	---	22357	/* SYSCALL_MM */	---
22358	uimm10,	---	22358	uimm10,	---
22359	/* Save16 */	---	22359	/* Save16 */	---
22360	/* SaveX16 */	---	22360	/* SaveX16 */	---
22361	/* SbRxRyOffMemX16 */	---	22361	/* SbRxRyOffMemX16 */	---
22362	CPU16Regs, CPU16Regs, simm16,	---	22362	CPU16Regs, CPU16Regs, simm16,	---
22363	/* SebRx16 */	---	22363	/* SebRx16 */	---
22364	CPU16Regs, CPU16Regs,	---	22364	CPU16Regs, CPU16Regs,	---
22365	/* SehRx16 */	---	22365	/* SehRx16 */	---
22366	CPU16Regs, CPU16Regs,	---	22366	CPU16Regs, CPU16Regs,	---
22367	/* ShRxRyOffMemX16 */	---	22367	/* ShRxRyOffMemX16 */	---
22368	CPU16Regs, CPU16Regs, simm16,	---	22368	CPU16Regs, CPU16Regs, simm16,	---
22369	/* SllX16 */	---	22369	/* SllX16 */	---
22370	CPU16Regs, CPU16Regs, uimm5,	---	22370	CPU16Regs, CPU16Regs, uimm5,	---
22371	/* SllvRxRy16 */	---	22371	/* SllvRxRy16 */	---
22372	CPU16Regs, CPU16Regs, CPU16Regs,	---	22372	CPU16Regs, CPU16Regs, CPU16Regs,	---
22373	/* SltRxRy16 */	---	22373	/* SltRxRy16 */	---
22374	CPU16Regs, CPU16Regs,	---	22374	CPU16Regs, CPU16Regs,	---
22375	/* SltiRxImm16 */	---	22375	/* SltiRxImm16 */	---
22376	CPU16Regs, simm16,	---	22376	CPU16Regs, simm16,	---
22377	/* SltiRxImmX16 */	---	22377	/* SltiRxImmX16 */	---
22378	CPU16Regs, simm16,	---	22378	CPU16Regs, simm16,	---
22379	/* SltiuRxImm16 */	---	22379	/* SltiuRxImm16 */	---
22380	CPU16Regs, simm16,	---	22380	CPU16Regs, simm16,	---
22381	/* SltiuRxImmX16 */	---	22381	/* SltiuRxImmX16 */	---
22382	CPU16Regs, simm16,	---	22382	CPU16Regs, simm16,	---
22383	/* SltuRxRy16 */	---	22383	/* SltuRxRy16 */	---
22384	CPU16Regs, CPU16Regs,	---	22384	CPU16Regs, CPU16Regs,	---
22385	/* SraX16 */	---	22385	/* SraX16 */	---
22386	CPU16Regs, CPU16Regs, uimm5,	---	22386	CPU16Regs, CPU16Regs, uimm5,	---
22387	/* SravRxRy16 */	---	22387	/* SravRxRy16 */	---
22388	CPU16Regs, CPU16Regs, CPU16Regs,	---	22388	CPU16Regs, CPU16Regs, CPU16Regs,	---
22389	/* SrlX16 */	---	22389	/* SrlX16 */	---
22390	CPU16Regs, CPU16Regs, uimm5,	---	22390	CPU16Regs, CPU16Regs, uimm5,	---
22391	/* SrlvRxRy16 */	---	22391	/* SrlvRxRy16 */	---
22392	CPU16Regs, CPU16Regs, CPU16Regs,	---	22392	CPU16Regs, CPU16Regs, CPU16Regs,	---
22393	/* SubuRxRyRz16 */	---	22393	/* SubuRxRyRz16 */	---
22394	CPU16Regs, CPU16Regs, CPU16Regs,	---	22394	CPU16Regs, CPU16Regs, CPU16Regs,	---
22395	/* SwRxRyOffMemX16 */	---	22395	/* SwRxRyOffMemX16 */	---
22396	CPU16Regs, CPU16Regs, simm16,	---	22396	CPU16Regs, CPU16Regs, simm16,	---
22397	/* SwRxSpImmX16 */	---	22397	/* SwRxSpImmX16 */	---
22398	CPU16Regs, CPU16RegsPlusSP, simm16,	---	22398	CPU16Regs, CPU16RegsPlusSP, simm16,	---
22399	/* TEQ */	---	22399	/* TEQ */	---
22400	GPR32Opnd, GPR32Opnd, uimm10,	---	22400	GPR32Opnd, GPR32Opnd, uimm10,	---
22401	/* TEQI */	---	22401	/* TEQI */	---
22402	GPR32Opnd, simm16,	---	22402	GPR32Opnd, simm16,	---
22403	/* TEQI_MM */	---	22403	/* TEQI_MM */	---
22404	GPR32Opnd, simm16,	---	22404	GPR32Opnd, simm16,	---
22405	/* TEQ_MM */	---	22405	/* TEQ_MM */	---
22406	GPR32Opnd, GPR32Opnd, uimm4,	---	22406	GPR32Opnd, GPR32Opnd, uimm4,	---
22407	/* TGE */	---	22407	/* TGE */	---
22408	GPR32Opnd, GPR32Opnd, uimm10,	---	22408	GPR32Opnd, GPR32Opnd, uimm10,	---
22409	/* TGEI */	---	22409	/* TGEI */	---
22410	GPR32Opnd, simm16,	---	22410	GPR32Opnd, simm16,	---
22411	/* TGEIU */	---	22411	/* TGEIU */	---
22412	GPR32Opnd, simm16,	---	22412	GPR32Opnd, simm16,	---
22413	/* TGEIU_MM */	---	22413	/* TGEIU_MM */	---
22414	GPR32Opnd, simm16,	---	22414	GPR32Opnd, simm16,	---
22415	/* TGEI_MM */	---	22415	/* TGEI_MM */	---
22416	GPR32Opnd, simm16,	---	22416	GPR32Opnd, simm16,	---
22417	/* TGEU */	---	22417	/* TGEU */	---
22418	GPR32Opnd, GPR32Opnd, uimm10,	---	22418	GPR32Opnd, GPR32Opnd, uimm10,	---
22419	/* TGEU_MM */	---	22419	/* TGEU_MM */	---
22420	GPR32Opnd, GPR32Opnd, uimm4,	---	22420	GPR32Opnd, GPR32Opnd, uimm4,	---
22421	/* TGE_MM */	---	22421	/* TGE_MM */	---
22422	GPR32Opnd, GPR32Opnd, uimm4,	---	22422	GPR32Opnd, GPR32Opnd, uimm4,	---
22423	/* TLBGINV */	---	22423	/* TLBGINV */	---
22424	/* TLBGINVF */	---	22424	/* TLBGINVF */	---
22425	/* TLBGINVF_MM */	---	22425	/* TLBGINVF_MM */	---
22426	/* TLBGINV_MM */	---	22426	/* TLBGINV_MM */	---
22427	/* TLBGP */	---	22427	/* TLBGP */	---
22428	/* TLBGP_MM */	---	22428	/* TLBGP_MM */	---
22429	/* TLBGR */	---	22429	/* TLBGR */	---
22430	/* TLBGR_MM */	---	22430	/* TLBGR_MM */	---
22431	/* TLBGWI */	---	22431	/* TLBGWI */	---
22432	/* TLBGWI_MM */	---	22432	/* TLBGWI_MM */	---
22433	/* TLBGWR */	---	22433	/* TLBGWR */	---
22434	/* TLBGWR_MM */	---	22434	/* TLBGWR_MM */	---
22435	/* TLBINV */	---	22435	/* TLBINV */	---
22436	/* TLBINVF */	---	22436	/* TLBINVF */	---
22437	/* TLBINVF_MMR6 */	---	22437	/* TLBINVF_MMR6 */	---
22438	/* TLBINV_MMR6 */	---	22438	/* TLBINV_MMR6 */	---
22439	/* TLBP */	---	22439	/* TLBP */	---
22440	/* TLBP_MM */	---	22440	/* TLBP_MM */	---
22441	/* TLBR */	---	22441	/* TLBR */	---
22442	/* TLBR_MM */	---	22442	/* TLBR_MM */	---
22443	/* TLBWI */	---	22443	/* TLBWI */	---
22444	/* TLBWI_MM */	---	22444	/* TLBWI_MM */	---
22445	/* TLBWR */	---	22445	/* TLBWR */	---
22446	/* TLBWR_MM */	---	22446	/* TLBWR_MM */	---
22447	/* TLT */	---	22447	/* TLT */	---
22448	GPR32Opnd, GPR32Opnd, uimm10,	---	22448	GPR32Opnd, GPR32Opnd, uimm10,	---
22449	/* TLTI */	---	22449	/* TLTI */	---
22450	GPR32Opnd, simm16,	---	22450	GPR32Opnd, simm16,	---
22451	/* TLTIU_MM */	---	22451	/* TLTIU_MM */	---
22452	GPR32Opnd, simm16,	---	22452	GPR32Opnd, simm16,	---
22453	/* TLTI_MM */	---	22453	/* TLTI_MM */	---
22454	GPR32Opnd, simm16,	---	22454	GPR32Opnd, simm16,	---
22455	/* TLTU */	---	22455	/* TLTU */	---
22456	GPR32Opnd, GPR32Opnd, uimm10,	---	22456	GPR32Opnd, GPR32Opnd, uimm10,	---
22457	/* TLTU_MM */	---	22457	/* TLTU_MM */	---
22458	GPR32Opnd, GPR32Opnd, uimm4,	---	22458	GPR32Opnd, GPR32Opnd, uimm4,	---
22459	/* TLT_MM */	---	22459	/* TLT_MM */	---
22460	GPR32Opnd, GPR32Opnd, uimm4,	---	22460	GPR32Opnd, GPR32Opnd, uimm4,	---
22461	/* TNE */	---	22461	/* TNE */	---
22462	GPR32Opnd, GPR32Opnd, uimm10,	---	22462	GPR32Opnd, GPR32Opnd, uimm10,	---
22463	/* TNEI */	---	22463	/* TNEI */	---
22464	GPR32Opnd, simm16,	---	22464	GPR32Opnd, simm16,	---
22465	/* TNEI_MM */	---	22465	/* TNEI_MM */	---
22466	GPR32Opnd, simm16,	---	22466	GPR32Opnd, simm16,	---
22467	/* TNE_MM */	---	22467	/* TNE_MM */	---
22468	GPR32Opnd, GPR32Opnd, uimm4,	---	22468	GPR32Opnd, GPR32Opnd, uimm4,	---
22469	/* TRUNC_L_D64 */	---	22469	/* TRUNC_L_D64 */	---
22470	FGR64Opnd, FGR64Opnd,	---	22470	FGR64Opnd, FGR64Opnd,	---
22471	/* TRUNC_L_D_MMR6 */	---	22471	/* TRUNC_L_D_MMR6 */	---
22472	FGR64Opnd, FGR64Opnd,	---	22472	FGR64Opnd, FGR64Opnd,	---
22473	/* TRUNC_L_S */	---	22473	/* TRUNC_L_S */	---
22474	FGR64Opnd, FGR32Opnd,	---	22474	FGR64Opnd, FGR32Opnd,	---
22475	/* TRUNC_L_S_MMR6 */	---	22475	/* TRUNC_L_S_MMR6 */	---
22476	FGR64Opnd, FGR32Opnd,	---	22476	FGR64Opnd, FGR32Opnd,	---
22477	/* TRUNC_W_D32 */	---	22477	/* TRUNC_W_D32 */	---
22478	FGR32Opnd, AFGR64Opnd,	---	22478	FGR32Opnd, AFGR64Opnd,	---
22479	/* TRUNC_W_D64 */	---	22479	/* TRUNC_W_D64 */	---
22480	FGR32Opnd, FGR64Opnd,	---	22480	FGR32Opnd, FGR64Opnd,	---
22481	/* TRUNC_W_D_MMR6 */	---	22481	/* TRUNC_W_D_MMR6 */	---
22482	FGR32Opnd, FGR64Opnd,	---	22482	FGR32Opnd, FGR64Opnd,	---
22483	/* TRUNC_W_MM */	---	22483	/* TRUNC_W_MM */	---
22484	FGR32Opnd, AFGR64Opnd,	---	22484	FGR32Opnd, AFGR64Opnd,	---
22485	/* TRUNC_W_S */	---	22485	/* TRUNC_W_S */	---
22486	FGR32Opnd, FGR32Opnd,	---	22486	FGR32Opnd, FGR32Opnd,	---
22487	/* TRUNC_W_S_MM */	---	22487	/* TRUNC_W_S_MM */	---
22488	FGR32Opnd, FGR32Opnd,	---	22488	FGR32Opnd, FGR32Opnd,	---
22489	/* TRUNC_W_S_MMR6 */	---	22489	/* TRUNC_W_S_MMR6 */	---
22490	FGR32Opnd, FGR32Opnd,	---	22490	FGR32Opnd, FGR32Opnd,	---
22491	/* TTLTIU */	---	22491	/* TTLTIU */	---
22492	GPR32Opnd, simm16,	---	22492	GPR32Opnd, simm16,	---
22493	/* UDIV */	---	22493	/* UDIV */	---
22494	GPR32Opnd, GPR32Opnd,	---	22494	GPR32Opnd, GPR32Opnd,	---
22495	/* UDIV_MM */	---	22495	/* UDIV_MM */	---
22496	GPR32Opnd, GPR32Opnd,	---	22496	GPR32Opnd, GPR32Opnd,	---
22497	/* V3MULU */	---	22497	/* V3MULU */	---
22498	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	22498	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
22499	/* VMM0 */	---	22499	/* VMM0 */	---
22500	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	22500	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
22501	/* VMULU */	---	22501	/* VMULU */	---
22502	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	22502	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
22503	/* VSHF_B */	---	22503	/* VSHF_B */	---
22504	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22504	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22505	/* VSHF_D */	---	22505	/* VSHF_D */	---
22506	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---	22506	MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,	---
22507	/* VSHF_H */	---	22507	/* VSHF_H */	---
22508	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---	22508	MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,	---
22509	/* VSHF_W */	---	22509	/* VSHF_W */	---
22510	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---	22510	MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,	---
22511	/* WAIT */	---	22511	/* WAIT */	---
22512	/* WAIT_MM */	---	22512	/* WAIT_MM */	---
22513	uimm10,	---	22513	uimm10,	---
22514	/* WAIT_MMR6 */	---	22514	/* WAIT_MMR6 */	---
22515	uimm10,	---	22515	uimm10,	---
22516	/* WRDSP */	---	22516	/* WRDSP */	---
22517	GPR32Opnd, uimm10,	---	22517	GPR32Opnd, uimm10,	---
22518	/* WRDSP_MM */	---	22518	/* WRDSP_MM */	---
22519	GPR32Opnd, uimm7,	---	22519	GPR32Opnd, uimm7,	---
22520	/* WRPGPR_MMR6 */	---	22520	/* WRPGPR_MMR6 */	---
22521	GPR32Opnd, GPR32Opnd,	---	22521	GPR32Opnd, GPR32Opnd,	---
22522	/* WSBH */	---	22522	/* WSBH */	---
22523	GPR32Opnd, GPR32Opnd,	---	22523	GPR32Opnd, GPR32Opnd,	---
22524	/* WSBH_MM */	---	22524	/* WSBH_MM */	---
22525	GPR32Opnd, GPR32Opnd,	---	22525	GPR32Opnd, GPR32Opnd,	---
22526	/* WSBH_MMR6 */	---	22526	/* WSBH_MMR6 */	---
22527	GPR32Opnd, GPR32Opnd,	---	22527	GPR32Opnd, GPR32Opnd,	---
22528	/* XOR */	---	22528	/* XOR */	---
22529	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22529	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22530	/* XOR16_MM */	---	22530	/* XOR16_MM */	---
22531	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	22531	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
22532	/* XOR16_MMR6 */	---	22532	/* XOR16_MMR6 */	---
22533	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---	22533	GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,	---
22534	/* XOR64 */	---	22534	/* XOR64 */	---
22535	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---	22535	GPR64Opnd, GPR64Opnd, GPR64Opnd,	---
22536	/* XORI_B */	---	22536	/* XORI_B */	---
22537	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---	22537	MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,	---
22538	/* XORI_MMR6 */	---	22538	/* XORI_MMR6 */	---
22539	GPR32Opnd, GPR32Opnd, uimm16,	---	22539	GPR32Opnd, GPR32Opnd, uimm16,	---
22540	/* XOR_MM */	---	22540	/* XOR_MM */	---
22541	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22541	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22542	/* XOR_MMR6 */	---	22542	/* XOR_MMR6 */	---
22543	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---	22543	GPR32Opnd, GPR32Opnd, GPR32Opnd,	---
22544	/* XOR_V */	---	22544	/* XOR_V */	---
22545	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---	22545	MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,	---
22546	/* XORi */	---	22546	/* XORi */	---
22547	GPR32Opnd, GPR32Opnd, uimm16,	---	22547	GPR32Opnd, GPR32Opnd, uimm16,	---
22548	/* XORi64 */	---	22548	/* XORi64 */	---
22549	GPR64Opnd, GPR64Opnd, uimm16_64,	---	22549	GPR64Opnd, GPR64Opnd, uimm16_64,	---
22550	/* XORi_MM */	---	22550	/* XORi_MM */	---
22551	GPR32Opnd, GPR32Opnd, uimm16,	---	22551	GPR32Opnd, GPR32Opnd, uimm16,	---
22552	/* XorRxRxRy16 */	---	22552	/* XorRxRxRy16 */	---
22553	CPU16Regs, CPU16Regs, CPU16Regs,	---	22553	CPU16Regs, CPU16Regs, CPU16Regs,	---
22554	/* YIELD */	---	22554	/* YIELD */	---
22555	GPR32Opnd, GPR32Opnd,	---	22555	GPR32Opnd, GPR32Opnd,	---
22556	};	---	22556	};	---
22557	return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];	---	22557	return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];	---
22558	}	---	22558	}	---
22559	} // end namespace Mips	---	22559	} // end namespace Mips	---
22560	} // end namespace llvm	---	22560	} // end namespace llvm	---
22561	#endif // GET_INSTRINFO_OPERAND_TYPE	---	22561	#endif // GET_INSTRINFO_OPERAND_TYPE	---
22562		---	22562		---
22563	#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE	---	22563	#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE	---
22564	#undef GET_INSTRINFO_MEM_OPERAND_SIZE	---	22564	#undef GET_INSTRINFO_MEM_OPERAND_SIZE	---
22565	namespace llvm {	---	22565	namespace llvm {	---
22566	namespace Mips {	---	22566	namespace Mips {	---
22567	LLVM_READONLY	---	22567	LLVM_READONLY	---
22568	static int getMemOperandSize(int OpType) {	---	22568	static int getMemOperandSize(int OpType) {	---
22569	switch (OpType) {	---	22569	switch (OpType) {	---
22570	default: return 0;	---	22570	default: return 0;	---
22571	}	---	22571	}	---
22572	}	---	22572	}	---
22573	} // end namespace Mips	---	22573	} // end namespace Mips	---
22574	} // end namespace llvm	---	22574	} // end namespace llvm	---
22575	#endif // GET_INSTRINFO_MEM_OPERAND_SIZE	---	22575	#endif // GET_INSTRINFO_MEM_OPERAND_SIZE	---
22576		---	22576		---
22577	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---	22577	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---
22578	#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---	22578	#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---
22579	namespace llvm {	---	22579	namespace llvm {	---
22580	namespace Mips {	---	22580	namespace Mips {	---
22581	LLVM_READONLY static unsigned	---	22581	LLVM_READONLY static unsigned	---
22582	getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {	---	22582	getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {	---
22583	return LogicalOpIdx;	---	22583	return LogicalOpIdx;	---
22584	}	---	22584	}	---
22585	LLVM_READONLY static inline unsigned	---	22585	LLVM_READONLY static inline unsigned	---
22586	getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {	---	22586	getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {	---
22587	auto S = 0U;	---	22587	auto S = 0U;	---
22588	for (auto i = 0U; i < LogicalOpIdx; ++i)	---	22588	for (auto i = 0U; i < LogicalOpIdx; ++i)	---
22589	S += getLogicalOperandSize(Opcode, i);	---	22589	S += getLogicalOperandSize(Opcode, i);	---
22590	return S;	---	22590	return S;	---
22591	}	---	22591	}	---
22592	} // end namespace Mips	---	22592	} // end namespace Mips	---
22593	} // end namespace llvm	---	22593	} // end namespace llvm	---
22594	#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---	22594	#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP	---
22595		---	22595		---
22596	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---	22596	#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---
22597	#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---	22597	#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---
22598	namespace llvm {	---	22598	namespace llvm {	---
22599	namespace Mips {	---	22599	namespace Mips {	---
22600	LLVM_READONLY static int	---	22600	LLVM_READONLY static int	---
22601	getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {	---	22601	getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {	---
22602	return -1;	---	22602	return -1;	---
22603	}	---	22603	}	---
22604	} // end namespace Mips	---	22604	} // end namespace Mips	---
22605	} // end namespace llvm	---	22605	} // end namespace llvm	---
22606	#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---	22606	#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP	---
22607		---	22607		---
22608	#ifdef GET_INSTRINFO_MC_HELPER_DECLS	---	22608	#ifdef GET_INSTRINFO_MC_HELPER_DECLS	---
22609	#undef GET_INSTRINFO_MC_HELPER_DECLS	---	22609	#undef GET_INSTRINFO_MC_HELPER_DECLS	---
22610		---	22610		---
22611	namespace llvm {	---	22611	namespace llvm {	---
22612	class MCInst;	---	22612	class MCInst;	---
22613	class FeatureBitset;	---	22613	class FeatureBitset;	---
22614		---	22614		---
22615	namespace Mips_MC {	---	22615	namespace Mips_MC {	---
22616		---	22616		---
22617	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);	---	22617	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);	---
22618		---	22618		---
22619	} // end namespace Mips_MC	---	22619	} // end namespace Mips_MC	---
22620	} // end namespace llvm	---	22620	} // end namespace llvm	---
22621		---	22621		---
22622	#endif // GET_INSTRINFO_MC_HELPER_DECLS	---	22622	#endif // GET_INSTRINFO_MC_HELPER_DECLS	---
22623		---	22623		---
22624	#ifdef GET_INSTRINFO_MC_HELPERS	---	22624	#ifdef GET_INSTRINFO_MC_HELPERS	---
22625	#undef GET_INSTRINFO_MC_HELPERS	---	22625	#undef GET_INSTRINFO_MC_HELPERS	---
22626		---	22626		---
22627	namespace llvm {	---	22627	namespace llvm {	---
22628	namespace Mips_MC {	---	22628	namespace Mips_MC {	---
22629		---	22629		---
22630	} // end namespace Mips_MC	---	22630	} // end namespace Mips_MC	---
22631	} // end namespace llvm	---	22631	} // end namespace llvm	---
22632		---	22632		---
22633	#endif // GET_GENISTRINFO_MC_HELPERS	---	22633	#endif // GET_GENISTRINFO_MC_HELPERS	---
22634		---	22634		---
22635	#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)	---	22635	#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)	---
22636	#define GET_COMPUTE_FEATURES	---	22636	#define GET_COMPUTE_FEATURES	---
22637	#endif	---	22637	#endif	---
22638	#ifdef GET_COMPUTE_FEATURES	---	22638	#ifdef GET_COMPUTE_FEATURES	---
22639	#undef GET_COMPUTE_FEATURES	---	22639	#undef GET_COMPUTE_FEATURES	---
22640	namespace llvm {	---	22640	namespace llvm {	---
22641	namespace Mips_MC {	---	22641	namespace Mips_MC {	---
22642		---	22642		---
22643	// Bits for subtarget features that participate in instruction matching.	---	22643	// Bits for subtarget features that participate in instruction matching.	---
22644	enum SubtargetFeatureBits : uint8_t {	---	22644	enum SubtargetFeatureBits : uint8_t {	---
22645	Feature_HasMips2Bit = 11,	---	22645	Feature_HasMips2Bit = 11,	---
22646	Feature_HasMips3_32Bit = 14,	---	22646	Feature_HasMips3_32Bit = 14,	---
22647	Feature_HasMips3_32r2Bit = 15,	---	22647	Feature_HasMips3_32r2Bit = 15,	---
22648	Feature_HasMips3Bit = 12,	---	22648	Feature_HasMips3Bit = 12,	---
22649	Feature_NotMips3Bit = 47,	---	22649	Feature_NotMips3Bit = 47,	---
22650	Feature_HasMips4_32Bit = 16,	---	22650	Feature_HasMips4_32Bit = 16,	---
22651	Feature_NotMips4_32Bit = 48,	---	22651	Feature_NotMips4_32Bit = 48,	---
22652	Feature_HasMips4_32r2Bit = 17,	---	22652	Feature_HasMips4_32r2Bit = 17,	---
22653	Feature_HasMips5_32r2Bit = 18,	---	22653	Feature_HasMips5_32r2Bit = 18,	---
22654	Feature_HasMips32Bit = 19,	---	22654	Feature_HasMips32Bit = 19,	---
22655	Feature_HasMips32r2Bit = 20,	---	22655	Feature_HasMips32r2Bit = 20,	---
22656	Feature_HasMips32r5Bit = 21,	---	22656	Feature_HasMips32r5Bit = 21,	---
22657	Feature_HasMips32r6Bit = 22,	---	22657	Feature_HasMips32r6Bit = 22,	---
22658	Feature_NotMips32r6Bit = 49,	---	22658	Feature_NotMips32r6Bit = 49,	---
22659	Feature_IsGP64bitBit = 33,	---	22659	Feature_IsGP64bitBit = 33,	---
22660	Feature_IsGP32bitBit = 32,	---	22660	Feature_IsGP32bitBit = 32,	---
22661	Feature_IsPTR64bitBit = 37,	---	22661	Feature_IsPTR64bitBit = 37,	---
22662	Feature_IsPTR32bitBit = 36,	---	22662	Feature_IsPTR32bitBit = 36,	---
22663	Feature_HasMips64Bit = 23,	---	22663	Feature_HasMips64Bit = 23,	---
22664	Feature_NotMips64Bit = 50,	---	22664	Feature_NotMips64Bit = 50,	---
22665	Feature_HasMips64r2Bit = 24,	---	22665	Feature_HasMips64r2Bit = 24,	---
22666	Feature_HasMips64r5Bit = 25,	---	22666	Feature_HasMips64r5Bit = 25,	---
22667	Feature_HasMips64r6Bit = 26,	---	22667	Feature_HasMips64r6Bit = 26,	---
22668	Feature_NotMips64r6Bit = 51,	---	22668	Feature_NotMips64r6Bit = 51,	---
22669	Feature_InMips16ModeBit = 30,	---	22669	Feature_InMips16ModeBit = 30,	---
22670	Feature_NotInMips16ModeBit = 46,	---	22670	Feature_NotInMips16ModeBit = 46,	---
22671	Feature_HasCnMipsBit = 1,	---	22671	Feature_HasCnMipsBit = 1,	---
22672	Feature_NotCnMipsBit = 42,	---	22672	Feature_NotCnMipsBit = 42,	---
22673	Feature_HasCnMipsPBit = 2,	---	22673	Feature_HasCnMipsPBit = 2,	---
22674	Feature_NotCnMipsPBit = 43,	---	22674	Feature_NotCnMipsPBit = 43,	---
22675	Feature_IsSym32Bit = 39,	---	22675	Feature_IsSym32Bit = 39,	---
22676	Feature_IsSym64Bit = 40,	---	22676	Feature_IsSym64Bit = 40,	---
22677	Feature_HasStdEncBit = 27,	---	22677	Feature_HasStdEncBit = 27,	---
22678	Feature_InMicroMipsBit = 29,	---	22678	Feature_InMicroMipsBit = 29,	---
22679	Feature_NotInMicroMipsBit = 45,	---	22679	Feature_NotInMicroMipsBit = 45,	---
22680	Feature_HasEVABit = 6,	---	22680	Feature_HasEVABit = 6,	---
22681	Feature_HasMSABit = 8,	---	22681	Feature_HasMSABit = 8,	---
22682	Feature_HasMadd4Bit = 10,	---	22682	Feature_HasMadd4Bit = 10,	---
22683	Feature_HasMTBit = 9,	---	22683	Feature_HasMTBit = 9,	---
22684	Feature_UseIndirectJumpsHazardBit = 52,	---	22684	Feature_UseIndirectJumpsHazardBit = 52,	---
22685	Feature_NoIndirectJumpGuardsBit = 41,	---	22685	Feature_NoIndirectJumpGuardsBit = 41,	---
22686	Feature_HasCRCBit = 0,	---	22686	Feature_HasCRCBit = 0,	---
22687	Feature_HasVirtBit = 28,	---	22687	Feature_HasVirtBit = 28,	---
22688	Feature_HasGINVBit = 7,	---	22688	Feature_HasGINVBit = 7,	---
22689	Feature_IsFP64bitBit = 31,	---	22689	Feature_IsFP64bitBit = 31,	---
22690	Feature_NotFP64bitBit = 44,	---	22690	Feature_NotFP64bitBit = 44,	---
22691	Feature_IsSingleFloatBit = 38,	---	22691	Feature_IsSingleFloatBit = 38,	---
22692	Feature_IsNotSingleFloatBit = 34,	---	22692	Feature_IsNotSingleFloatBit = 34,	---
22693	Feature_IsNotSoftFloatBit = 35,	---	22693	Feature_IsNotSoftFloatBit = 35,	---
22694	Feature_HasMips3DBit = 13,	---	22694	Feature_HasMips3DBit = 13,	---
22695	Feature_HasDSPBit = 3,	---	22695	Feature_HasDSPBit = 3,	---
22696	Feature_HasDSPR2Bit = 4,	---	22696	Feature_HasDSPR2Bit = 4,	---
22697	Feature_HasDSPR3Bit = 5,	---	22697	Feature_HasDSPR3Bit = 5,	---
22698	};	---	22698	};	---
22699		---	22699		---
22700	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {	0	22700	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {	0
22701	FeatureBitset Features;	0	22701	FeatureBitset Features;	0
22702	if (FB[Mips::FeatureMips2])	0	22702	if (FB[Mips::FeatureMips2])	0
22703	Features.set(Feature_HasMips2Bit);	0	22703	Features.set(Feature_HasMips2Bit);	0
22704	if (FB[Mips::FeatureMips3_32])	0	22704	if (FB[Mips::FeatureMips3_32])	0
22705	Features.set(Feature_HasMips3_32Bit);	0	22705	Features.set(Feature_HasMips3_32Bit);	0
22706	if (FB[Mips::FeatureMips3_32r2])	0	22706	if (FB[Mips::FeatureMips3_32r2])	0
22707	Features.set(Feature_HasMips3_32r2Bit);	0	22707	Features.set(Feature_HasMips3_32r2Bit);	0
22708	if (FB[Mips::FeatureMips3])	0	22708	if (FB[Mips::FeatureMips3])	0
22709	Features.set(Feature_HasMips3Bit);	0	22709	Features.set(Feature_HasMips3Bit);	0
22710	if (!FB[Mips::FeatureMips3])	0	22710	if (!FB[Mips::FeatureMips3])	0
22711	Features.set(Feature_NotMips3Bit);	0	22711	Features.set(Feature_NotMips3Bit);	0
22712	if (FB[Mips::FeatureMips4_32])	0	22712	if (FB[Mips::FeatureMips4_32])	0
22713	Features.set(Feature_HasMips4_32Bit);	0	22713	Features.set(Feature_HasMips4_32Bit);	0
22714	if (!FB[Mips::FeatureMips4_32])	0	22714	if (!FB[Mips::FeatureMips4_32])	0
22715	Features.set(Feature_NotMips4_32Bit);	0	22715	Features.set(Feature_NotMips4_32Bit);	0
22716	if (FB[Mips::FeatureMips4_32r2])	0	22716	if (FB[Mips::FeatureMips4_32r2])	0
22717	Features.set(Feature_HasMips4_32r2Bit);	0	22717	Features.set(Feature_HasMips4_32r2Bit);	0
22718	if (FB[Mips::FeatureMips5_32r2])	0	22718	if (FB[Mips::FeatureMips5_32r2])	0
22719	Features.set(Feature_HasMips5_32r2Bit);	0	22719	Features.set(Feature_HasMips5_32r2Bit);	0
22720	if (FB[Mips::FeatureMips32])	0	22720	if (FB[Mips::FeatureMips32])	0
22721	Features.set(Feature_HasMips32Bit);	0	22721	Features.set(Feature_HasMips32Bit);	0
22722	if (FB[Mips::FeatureMips32r2])	0	22722	if (FB[Mips::FeatureMips32r2])	0
22723	Features.set(Feature_HasMips32r2Bit);	0	22723	Features.set(Feature_HasMips32r2Bit);	0
22724	if (FB[Mips::FeatureMips32r5])	0	22724	if (FB[Mips::FeatureMips32r5])	0
22725	Features.set(Feature_HasMips32r5Bit);	0	22725	Features.set(Feature_HasMips32r5Bit);	0
22726	if (FB[Mips::FeatureMips32r6])	0	22726	if (FB[Mips::FeatureMips32r6])	0
22727	Features.set(Feature_HasMips32r6Bit);	0	22727	Features.set(Feature_HasMips32r6Bit);	0
22728	if (!FB[Mips::FeatureMips32r6])	0	22728	if (!FB[Mips::FeatureMips32r6])	0
22729	Features.set(Feature_NotMips32r6Bit);	0	22729	Features.set(Feature_NotMips32r6Bit);	0
22730	if (FB[Mips::FeatureGP64Bit])	0	22730	if (FB[Mips::FeatureGP64Bit])	0
22731	Features.set(Feature_IsGP64bitBit);	0	22731	Features.set(Feature_IsGP64bitBit);	0
22732	if (!FB[Mips::FeatureGP64Bit])	0	22732	if (!FB[Mips::FeatureGP64Bit])	0
22733	Features.set(Feature_IsGP32bitBit);	0	22733	Features.set(Feature_IsGP32bitBit);	0
22734	if (FB[Mips::FeaturePTR64Bit])	0	22734	if (FB[Mips::FeaturePTR64Bit])	0
22735	Features.set(Feature_IsPTR64bitBit);	0	22735	Features.set(Feature_IsPTR64bitBit);	0
22736	if (!FB[Mips::FeaturePTR64Bit])	0	22736	if (!FB[Mips::FeaturePTR64Bit])	0
22737	Features.set(Feature_IsPTR32bitBit);	0	22737	Features.set(Feature_IsPTR32bitBit);	0
22738	if (FB[Mips::FeatureMips64])	0	22738	if (FB[Mips::FeatureMips64])	0
22739	Features.set(Feature_HasMips64Bit);	0	22739	Features.set(Feature_HasMips64Bit);	0
22740	if (!FB[Mips::FeatureMips64])	0	22740	if (!FB[Mips::FeatureMips64])	0
22741	Features.set(Feature_NotMips64Bit);	0	22741	Features.set(Feature_NotMips64Bit);	0
22742	if (FB[Mips::FeatureMips64r2])	0	22742	if (FB[Mips::FeatureMips64r2])	0
22743	Features.set(Feature_HasMips64r2Bit);	0	22743	Features.set(Feature_HasMips64r2Bit);	0
22744	if (FB[Mips::FeatureMips64r5])	0	22744	if (FB[Mips::FeatureMips64r5])	0
22745	Features.set(Feature_HasMips64r5Bit);	0	22745	Features.set(Feature_HasMips64r5Bit);	0
22746	if (FB[Mips::FeatureMips64r6])	0	22746	if (FB[Mips::FeatureMips64r6])	0
22747	Features.set(Feature_HasMips64r6Bit);	0	22747	Features.set(Feature_HasMips64r6Bit);	0
22748	if (!FB[Mips::FeatureMips64r6])	0	22748	if (!FB[Mips::FeatureMips64r6])	0
22749	Features.set(Feature_NotMips64r6Bit);	0	22749	Features.set(Feature_NotMips64r6Bit);	0
22750	if (FB[Mips::FeatureMips16])	0	22750	if (FB[Mips::FeatureMips16])	0
22751	Features.set(Feature_InMips16ModeBit);	0	22751	Features.set(Feature_InMips16ModeBit);	0
22752	if (!FB[Mips::FeatureMips16])	0	22752	if (!FB[Mips::FeatureMips16])	0
22753	Features.set(Feature_NotInMips16ModeBit);	0	22753	Features.set(Feature_NotInMips16ModeBit);	0
22754	if (FB[Mips::FeatureCnMips])	0	22754	if (FB[Mips::FeatureCnMips])	0
22755	Features.set(Feature_HasCnMipsBit);	0	22755	Features.set(Feature_HasCnMipsBit);	0
22756	if (!FB[Mips::FeatureCnMips])	0	22756	if (!FB[Mips::FeatureCnMips])	0
22757	Features.set(Feature_NotCnMipsBit);	0	22757	Features.set(Feature_NotCnMipsBit);	0
22758	if (FB[Mips::FeatureCnMipsP])	0	22758	if (FB[Mips::FeatureCnMipsP])	0
22759	Features.set(Feature_HasCnMipsPBit);	0	22759	Features.set(Feature_HasCnMipsPBit);	0
22760	if (!FB[Mips::FeatureCnMipsP])	0	22760	if (!FB[Mips::FeatureCnMipsP])	0
22761	Features.set(Feature_NotCnMipsPBit);	0	22761	Features.set(Feature_NotCnMipsPBit);	0
22762	if (FB[Mips::FeatureSym32])	0	22762	if (FB[Mips::FeatureSym32])	0
22763	Features.set(Feature_IsSym32Bit);	0	22763	Features.set(Feature_IsSym32Bit);	0
22764	if (!FB[Mips::FeatureSym32])	0	22764	if (!FB[Mips::FeatureSym32])	0
22765	Features.set(Feature_IsSym64Bit);	0	22765	Features.set(Feature_IsSym64Bit);	0
22766	if (!FB[Mips::FeatureMips16])	0	22766	if (!FB[Mips::FeatureMips16])	0
22767	Features.set(Feature_HasStdEncBit);	0	22767	Features.set(Feature_HasStdEncBit);	0
22768	if (FB[Mips::FeatureMicroMips])	0	22768	if (FB[Mips::FeatureMicroMips])	0
22769	Features.set(Feature_InMicroMipsBit);	0	22769	Features.set(Feature_InMicroMipsBit);	0
22770	if (!FB[Mips::FeatureMicroMips])	0	22770	if (!FB[Mips::FeatureMicroMips])	0
22771	Features.set(Feature_NotInMicroMipsBit);	0	22771	Features.set(Feature_NotInMicroMipsBit);	0
22772	if (FB[Mips::FeatureEVA])	0	22772	if (FB[Mips::FeatureEVA])	0
22773	Features.set(Feature_HasEVABit);	0	22773	Features.set(Feature_HasEVABit);	0
22774	if (FB[Mips::FeatureMSA])	0	22774	if (FB[Mips::FeatureMSA])	0
22775	Features.set(Feature_HasMSABit);	0	22775	Features.set(Feature_HasMSABit);	0
22776	if (!FB[Mips::FeatureNoMadd4])	0	22776	if (!FB[Mips::FeatureNoMadd4])	0
22777	Features.set(Feature_HasMadd4Bit);	0	22777	Features.set(Feature_HasMadd4Bit);	0
22778	if (FB[Mips::FeatureMT])	0	22778	if (FB[Mips::FeatureMT])	0
22779	Features.set(Feature_HasMTBit);	0	22779	Features.set(Feature_HasMTBit);	0
22780	if (FB[Mips::FeatureUseIndirectJumpsHazard])	0	22780	if (FB[Mips::FeatureUseIndirectJumpsHazard])	0
22781	Features.set(Feature_UseIndirectJumpsHazardBit);	0	22781	Features.set(Feature_UseIndirectJumpsHazardBit);	0
22782	if (!FB[Mips::FeatureUseIndirectJumpsHazard])	0	22782	if (!FB[Mips::FeatureUseIndirectJumpsHazard])	0
22783	Features.set(Feature_NoIndirectJumpGuardsBit);	0	22783	Features.set(Feature_NoIndirectJumpGuardsBit);	0
22784	if (FB[Mips::FeatureCRC])	0	22784	if (FB[Mips::FeatureCRC])	0
22785	Features.set(Feature_HasCRCBit);	0	22785	Features.set(Feature_HasCRCBit);	0
22786	if (FB[Mips::FeatureVirt])	0	22786	if (FB[Mips::FeatureVirt])	0
22787	Features.set(Feature_HasVirtBit);	0	22787	Features.set(Feature_HasVirtBit);	0
22788	if (FB[Mips::FeatureGINV])	0	22788	if (FB[Mips::FeatureGINV])	0
22789	Features.set(Feature_HasGINVBit);	0	22789	Features.set(Feature_HasGINVBit);	0
22790	if (FB[Mips::FeatureFP64Bit])	0	22790	if (FB[Mips::FeatureFP64Bit])	0
22791	Features.set(Feature_IsFP64bitBit);	0	22791	Features.set(Feature_IsFP64bitBit);	0
22792	if (!FB[Mips::FeatureFP64Bit])	0	22792	if (!FB[Mips::FeatureFP64Bit])	0
22793	Features.set(Feature_NotFP64bitBit);	0	22793	Features.set(Feature_NotFP64bitBit);	0
22794	if (FB[Mips::FeatureSingleFloat])	0	22794	if (FB[Mips::FeatureSingleFloat])	0
22795	Features.set(Feature_IsSingleFloatBit);	0	22795	Features.set(Feature_IsSingleFloatBit);	0
22796	if (!FB[Mips::FeatureSingleFloat])	0	22796	if (!FB[Mips::FeatureSingleFloat])	0
22797	Features.set(Feature_IsNotSingleFloatBit);	0	22797	Features.set(Feature_IsNotSingleFloatBit);	0
22798	if (!FB[Mips::FeatureSoftFloat])	0	22798	if (!FB[Mips::FeatureSoftFloat])	0
22799	Features.set(Feature_IsNotSoftFloatBit);	0	22799	Features.set(Feature_IsNotSoftFloatBit);	0
22800	if (FB[Mips::FeatureMips3D])	0	22800	if (FB[Mips::FeatureMips3D])	0
22801	Features.set(Feature_HasMips3DBit);	0	22801	Features.set(Feature_HasMips3DBit);	0
22802	if (FB[Mips::FeatureDSP])	0	22802	if (FB[Mips::FeatureDSP])	0
22803	Features.set(Feature_HasDSPBit);	0	22803	Features.set(Feature_HasDSPBit);	0
22804	if (FB[Mips::FeatureDSPR2])	0	22804	if (FB[Mips::FeatureDSPR2])	0
22805	Features.set(Feature_HasDSPR2Bit);	0	22805	Features.set(Feature_HasDSPR2Bit);	0
22806	if (FB[Mips::FeatureDSPR3])	0	22806	if (FB[Mips::FeatureDSPR3])	0
22807	Features.set(Feature_HasDSPR3Bit);	0	22807	Features.set(Feature_HasDSPR3Bit);	0
22808	return Features;	0	22808	return Features;	0
22809	}	---	22809	}	---
22810		---	22810		---
22811	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {	0	22811	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {	0
22812	enum : uint8_t {	---	22812	enum : uint8_t {	---
22813	CEFBS_None,	---	22813	CEFBS_None,	---
22814	CEFBS_HasCnMips,	---	22814	CEFBS_HasCnMips,	---
22815	CEFBS_HasCnMipsP,	---	22815	CEFBS_HasCnMipsP,	---
22816	CEFBS_HasDSP,	---	22816	CEFBS_HasDSP,	---
22817	CEFBS_HasDSPR2,	---	22817	CEFBS_HasDSPR2,	---
22818	CEFBS_HasMSA,	---	22818	CEFBS_HasMSA,	---
22819	CEFBS_HasMT,	---	22819	CEFBS_HasMT,	---
22820	CEFBS_InMicroMips,	---	22820	CEFBS_InMicroMips,	---
22821	CEFBS_InMips16Mode,	---	22821	CEFBS_InMips16Mode,	---
22822	CEFBS_IsGP32bit,	---	22822	CEFBS_IsGP32bit,	---
22823	CEFBS_IsGP64bit,	---	22823	CEFBS_IsGP64bit,	---
22824	CEFBS_IsNotSoftFloat,	---	22824	CEFBS_IsNotSoftFloat,	---
22825	CEFBS_NotCnMips,	---	22825	CEFBS_NotCnMips,	---
22826	CEFBS_NotInMips16Mode,	---	22826	CEFBS_NotInMips16Mode,	---
22827	CEFBS_HasDSP_NotInMicroMips,	---	22827	CEFBS_HasDSP_NotInMicroMips,	---
22828	CEFBS_HasStdEnc_HasMSA,	---	22828	CEFBS_HasStdEnc_HasMSA,	---
22829	CEFBS_HasStdEnc_HasMips32,	---	22829	CEFBS_HasStdEnc_HasMips32,	---
22830	CEFBS_HasStdEnc_HasMips32r6,	---	22830	CEFBS_HasStdEnc_HasMips32r6,	---
22831	CEFBS_HasStdEnc_HasMips64,	---	22831	CEFBS_HasStdEnc_HasMips64,	---
22832	CEFBS_HasStdEnc_HasMips64r6,	---	22832	CEFBS_HasStdEnc_HasMips64r6,	---
22833	CEFBS_HasStdEnc_IsNotSoftFloat,	---	22833	CEFBS_HasStdEnc_IsNotSoftFloat,	---
22834	CEFBS_HasStdEnc_NotInMicroMips,	---	22834	CEFBS_HasStdEnc_NotInMicroMips,	---
22835	CEFBS_HasStdEnc_NotMips3,	---	22835	CEFBS_HasStdEnc_NotMips3,	---
22836	CEFBS_HasStdEnc_NotMips4_32,	---	22836	CEFBS_HasStdEnc_NotMips4_32,	---
22837	CEFBS_InMicroMips_HasDSP,	---	22837	CEFBS_InMicroMips_HasDSP,	---
22838	CEFBS_InMicroMips_HasDSPR2,	---	22838	CEFBS_InMicroMips_HasDSPR2,	---
22839	CEFBS_InMicroMips_HasDSPR3,	---	22839	CEFBS_InMicroMips_HasDSPR3,	---
22840	CEFBS_InMicroMips_HasEVA,	---	22840	CEFBS_InMicroMips_HasEVA,	---
22841	CEFBS_InMicroMips_HasMips32r6,	---	22841	CEFBS_InMicroMips_HasMips32r6,	---
22842	CEFBS_InMicroMips_IsNotSoftFloat,	---	22842	CEFBS_InMicroMips_IsNotSoftFloat,	---
22843	CEFBS_InMicroMips_NotMips32r6,	---	22843	CEFBS_InMicroMips_NotMips32r6,	---
22844	CEFBS_IsFP64bit_IsNotSoftFloat,	---	22844	CEFBS_IsFP64bit_IsNotSoftFloat,	---
22845	CEFBS_IsGP32bit_NotInMicroMips,	---	22845	CEFBS_IsGP32bit_NotInMicroMips,	---
22846	CEFBS_NotFP64bit_IsNotSoftFloat,	---	22846	CEFBS_NotFP64bit_IsNotSoftFloat,	---
22847	CEFBS_NotInMips16Mode_HasDSP,	---	22847	CEFBS_NotInMips16Mode_HasDSP,	---
22848	CEFBS_NotInMips16Mode_IsGP64bit,	---	22848	CEFBS_NotInMips16Mode_IsGP64bit,	---
22849	CEFBS_NotInMips16Mode_IsNotSoftFloat,	---	22849	CEFBS_NotInMips16Mode_IsNotSoftFloat,	---
22850	CEFBS_NotInMips16Mode_IsPTR64bit,	---	22850	CEFBS_NotInMips16Mode_IsPTR64bit,	---
22851	CEFBS_HasMips3_NotMips64r6_NotCnMips,	---	22851	CEFBS_HasMips3_NotMips64r6_NotCnMips,	---
22852	CEFBS_HasMips64_HasCnMips_NotInMicroMips,	---	22852	CEFBS_HasMips64_HasCnMips_NotInMicroMips,	---
22853	CEFBS_HasStdEnc_HasMSA_HasMips64,	---	22853	CEFBS_HasStdEnc_HasMSA_HasMips64,	---
22854	CEFBS_HasStdEnc_HasMT_NotInMicroMips,	---	22854	CEFBS_HasStdEnc_HasMT_NotInMicroMips,	---
22855	CEFBS_HasStdEnc_HasMips2_NotInMicroMips,	---	22855	CEFBS_HasStdEnc_HasMips2_NotInMicroMips,	---
22856	CEFBS_HasStdEnc_HasMips3_NotInMicroMips,	---	22856	CEFBS_HasStdEnc_HasMips3_NotInMicroMips,	---
22857	CEFBS_HasStdEnc_HasMips32_NotInMicroMips,	---	22857	CEFBS_HasStdEnc_HasMips32_NotInMicroMips,	---
22858	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,	---	22858	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,	---
22859	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,	---	22859	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,	---
22860	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,	---	22860	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,	---
22861	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,	---	22861	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,	---
22862	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,	---	22862	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,	---
22863	CEFBS_HasStdEnc_HasMips64r5_HasVirt,	---	22863	CEFBS_HasStdEnc_HasMips64r5_HasVirt,	---
22864	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,	---	22864	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,	---
22865	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,	---	22865	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,	---
22866	CEFBS_HasStdEnc_IsGP64bit_HasMips3,	---	22866	CEFBS_HasStdEnc_IsGP64bit_HasMips3,	---
22867	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,	---	22867	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,	---
22868	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,	---	22868	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,	---
22869	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,	---	22869	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,	---
22870	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,	---	22870	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,	---
22871	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,	---	22871	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,	---
22872	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,	---	22872	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,	---
22873	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,	---	22873	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,	---
22874	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,	---	22874	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,	---
22875	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,	---	22875	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,	---
22876	CEFBS_InMicroMips_HasMips32r5_HasVirt,	---	22876	CEFBS_InMicroMips_HasMips32r5_HasVirt,	---
22877	CEFBS_InMicroMips_HasMips32r6_HasGINV,	---	22877	CEFBS_InMicroMips_HasMips32r6_HasGINV,	---
22878	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,	---	22878	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,	---
22879	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,	---	22879	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,	---
22880	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,	---	22880	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,	---
22881	CEFBS_InMicroMips_NotMips32r6_HasDSP,	---	22881	CEFBS_InMicroMips_NotMips32r6_HasDSP,	---
22882	CEFBS_InMicroMips_NotMips32r6_HasEVA,	---	22882	CEFBS_InMicroMips_NotMips32r6_HasEVA,	---
22883	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,	---	22883	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,	---
22884	CEFBS_InMicroMips_NotMips32r6_NotMips64r6,	---	22884	CEFBS_InMicroMips_NotMips32r6_NotMips64r6,	---
22885	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,	---	22885	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,	---
22886	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,	---	22886	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,	---
22887	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,	---	22887	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,	---
22888	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,	---	22888	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,	---
22889	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,	---	22889	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,	---
22890	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,	---	22890	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,	---
22891	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22891	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22892	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,	---	22892	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,	---
22893	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,	---	22893	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,	---
22894	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,	---	22894	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,	---
22895	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,	---	22895	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,	---
22896	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,	---	22896	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,	---
22897	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,	---	22897	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,	---
22898	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,	---	22898	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,	---
22899	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,	---	22899	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,	---
22900	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,	---	22900	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,	---
22901	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,	---	22901	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,	---
22902	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,	---	22902	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,	---
22903	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,	---	22903	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,	---
22904	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	---	22904	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	---
22905	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---	22905	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---
22906	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,	---	22906	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,	---
22907	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,	---	22907	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,	---
22908	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,	---	22908	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,	---
22909	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,	---	22909	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,	---
22910	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,	---	22910	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,	---
22911	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,	---	22911	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,	---
22912	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,	---	22912	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,	---
22913	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22913	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22914	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,	---	22914	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,	---
22915	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,	---	22915	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,	---
22916	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,	---	22916	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,	---
22917	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,	---	22917	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,	---
22918	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22918	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22919	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22919	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22920	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22920	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22921	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---	22921	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---
22922	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22922	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22923	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22923	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22924	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22924	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22925	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---	22925	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---
22926	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---	22926	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---
22927	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22927	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22928	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	---	22928	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	---
22929	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	---	22929	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	---
22930	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,	---	22930	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,	---
22931	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	---	22931	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,	---
22932	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---	22932	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---
22933	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---	22933	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---
22934	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,	---	22934	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,	---
22935	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	---	22935	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,	---
22936	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	---	22936	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,	---
22937	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---	22937	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,	---
22938	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22938	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22939	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,	---	22939	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,	---
22940	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,	---	22940	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,	---
22941	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22941	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,	---	22942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,	---
22943	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22943	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22944	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---	22944	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,	---
22945	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22945	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22946	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22946	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22947	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22947	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22948	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---	22948	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,	---
22949	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22949	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22950	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---	22950	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---
22951	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---	22951	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---
22952	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22952	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22953	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22953	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22954	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---	22954	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---
22955	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---	22955	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---
22956	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,	---	22956	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,	---
22957	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22957	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22958	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22958	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22959	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22959	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22960	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22960	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22961	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22961	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22962	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22962	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22963	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22963	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22964	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---	22964	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---
22965	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---	22965	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---
22966	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---	22966	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,	---
22967	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---	22967	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,	---
22968	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---	22968	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,	---
22969	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---	22969	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,	---
22970	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---	22970	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,	---
22971	};	---	22971	};	---
22972		---	22972		---
22973	static constexpr FeatureBitset FeatureBitsets[] = {	---	22973	static constexpr FeatureBitset FeatureBitsets[] = {	---
22974	{}, // CEFBS_None	---	22974	{}, // CEFBS_None	---
22975	{Feature_HasCnMipsBit, },	---	22975	{Feature_HasCnMipsBit, },	---
22976	{Feature_HasCnMipsPBit, },	---	22976	{Feature_HasCnMipsPBit, },	---
22977	{Feature_HasDSPBit, },	---	22977	{Feature_HasDSPBit, },	---
22978	{Feature_HasDSPR2Bit, },	---	22978	{Feature_HasDSPR2Bit, },	---
22979	{Feature_HasMSABit, },	---	22979	{Feature_HasMSABit, },	---
22980	{Feature_HasMTBit, },	---	22980	{Feature_HasMTBit, },	---
22981	{Feature_InMicroMipsBit, },	---	22981	{Feature_InMicroMipsBit, },	---
22982	{Feature_InMips16ModeBit, },	---	22982	{Feature_InMips16ModeBit, },	---
22983	{Feature_IsGP32bitBit, },	---	22983	{Feature_IsGP32bitBit, },	---
22984	{Feature_IsGP64bitBit, },	---	22984	{Feature_IsGP64bitBit, },	---
22985	{Feature_IsNotSoftFloatBit, },	---	22985	{Feature_IsNotSoftFloatBit, },	---
22986	{Feature_NotCnMipsBit, },	---	22986	{Feature_NotCnMipsBit, },	---
22987	{Feature_NotInMips16ModeBit, },	---	22987	{Feature_NotInMips16ModeBit, },	---
22988	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },	---	22988	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },	---
22989	{Feature_HasStdEncBit, Feature_HasMSABit, },	---	22989	{Feature_HasStdEncBit, Feature_HasMSABit, },	---
22990	{Feature_HasStdEncBit, Feature_HasMips32Bit, },	---	22990	{Feature_HasStdEncBit, Feature_HasMips32Bit, },	---
22991	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, },	---	22991	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, },	---
22992	{Feature_HasStdEncBit, Feature_HasMips64Bit, },	---	22992	{Feature_HasStdEncBit, Feature_HasMips64Bit, },	---
22993	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, },	---	22993	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, },	---
22994	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },	---	22994	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },	---
22995	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },	---	22995	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },	---
22996	{Feature_HasStdEncBit, Feature_NotMips3Bit, },	---	22996	{Feature_HasStdEncBit, Feature_NotMips3Bit, },	---
22997	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },	---	22997	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },	---
22998	{Feature_InMicroMipsBit, Feature_HasDSPBit, },	---	22998	{Feature_InMicroMipsBit, Feature_HasDSPBit, },	---
22999	{Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },	---	22999	{Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },	---
23000	{Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },	---	23000	{Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },	---
23001	{Feature_InMicroMipsBit, Feature_HasEVABit, },	---	23001	{Feature_InMicroMipsBit, Feature_HasEVABit, },	---
23002	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },	---	23002	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },	---
23003	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },	---	23003	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },	---
23004	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },	---	23004	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },	---
23005	{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23005	{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23006	{Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },	---	23006	{Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },	---
23007	{Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23007	{Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23008	{Feature_NotInMips16ModeBit, Feature_HasDSPBit, },	---	23008	{Feature_NotInMips16ModeBit, Feature_HasDSPBit, },	---
23009	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },	---	23009	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },	---
23010	{Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },	---	23010	{Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },	---
23011	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },	---	23011	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },	---
23012	{Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },	---	23012	{Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },	---
23013	{Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },	---	23013	{Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },	---
23014	{Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },	---	23014	{Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },	---
23015	{Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },	---	23015	{Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },	---
23016	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },	---	23016	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },	---
23017	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },	---	23017	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },	---
23018	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },	---	23018	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },	---
23019	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },	---	23019	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },	---
23020	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },	---	23020	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },	---
23021	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---	23021	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---
23022	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },	---	23022	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },	---
23023	{Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },	---	23023	{Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },	---
23024	{Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },	---	23024	{Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },	---
23025	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23025	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23026	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },	---	23026	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },	---
23027	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },	---	23027	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },	---
23028	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },	---	23028	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },	---
23029	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },	---	23029	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },	---
23030	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },	---	23030	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },	---
23031	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23031	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23032	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23032	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23033	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },	---	23033	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },	---
23034	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23034	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23035	{Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },	---	23035	{Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },	---
23036	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23036	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23037	{Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },	---	23037	{Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },	---
23038	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },	---	23038	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },	---
23039	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	---	23039	{Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	---
23040	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23040	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23041	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23041	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23042	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },	---	23042	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },	---
23043	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },	---	23043	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },	---
23044	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---	23044	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---
23045	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23045	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23046	{Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23046	{Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23047	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },	---	23047	{Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },	---
23048	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },	---	23048	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },	---
23049	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },	---	23049	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },	---
23050	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },	---	23050	{Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },	---
23051	{Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---	23051	{Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },	---
23052	{Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23052	{Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23053	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23053	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23054	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	---	23054	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	---
23055	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23055	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23056	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23056	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23057	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23057	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23058	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23058	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23059	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	---	23059	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	---
23060	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---	23060	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },	---
23061	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },	---	23061	{Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },	---
23062	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	---	23062	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	---
23063	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },	---	23063	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },	---
23064	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23064	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23065	{Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23065	{Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23066	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23066	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23067	{Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23067	{Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23068	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	---	23068	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },	---
23069	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23069	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23070	{Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---	23070	{Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---
23071	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---	23071	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },	---
23072	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23072	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23073	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23073	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23074	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23074	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23075	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	---	23075	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },	---
23076	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---	23076	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---
23077	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---	23077	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },	---
23078	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	---	23078	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	---
23079	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23079	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23080	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23080	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23081	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23081	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23082	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23082	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23083	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23083	{Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23084	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23084	{Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23085	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23085	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23086	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---	23086	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---
23087	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23087	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23088	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23088	{Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23089	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23089	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23090	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23090	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23091	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23091	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23092	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23092	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23093	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23093	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23094	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---	23094	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---
23095	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23095	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23096	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23096	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23097	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23097	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23098	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23098	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23099	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23099	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23100	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	---	23100	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },	---
23101	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	---	23101	{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },	---
23102	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23102	{Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23103	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	---	23103	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },	---
23104	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23104	{Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23105	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---	23105	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },	---
23106	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23106	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23107	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23107	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23108	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23108	{Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23109	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---	23109	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },	---
23110	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23110	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23111	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23111	{Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23112	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23112	{Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23113	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23113	{Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23114	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23114	{Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23115	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---	23115	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---
23116	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---	23116	{Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---
23117	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },	---	23117	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },	---
23118	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23118	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23119	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23119	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23120	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23120	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23121	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23121	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23122	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23122	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23123	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23123	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23124	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23124	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23125	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---	23125	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---
23126	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---	23126	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---
23127	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---	23127	{Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },	---
23128	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---	23128	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },	---
23129	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---	23129	{Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },	---
23130	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---	23130	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },	---
23131	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---	23131	{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },	---
23132	};	---	23132	};	---
23133	static uint8_t RequiredFeaturesRefs[] = {	---	23133	static uint8_t RequiredFeaturesRefs[] = {	---
23134	CEFBS_None, // PHI = 0	---	23134	CEFBS_None, // PHI = 0	---
23135	CEFBS_None, // INLINEASM = 1	---	23135	CEFBS_None, // INLINEASM = 1	---
23136	CEFBS_None, // INLINEASM_BR = 2	---	23136	CEFBS_None, // INLINEASM_BR = 2	---
23137	CEFBS_None, // CFI_INSTRUCTION = 3	---	23137	CEFBS_None, // CFI_INSTRUCTION = 3	---
23138	CEFBS_None, // EH_LABEL = 4	---	23138	CEFBS_None, // EH_LABEL = 4	---
23139	CEFBS_None, // GC_LABEL = 5	---	23139	CEFBS_None, // GC_LABEL = 5	---
23140	CEFBS_None, // ANNOTATION_LABEL = 6	---	23140	CEFBS_None, // ANNOTATION_LABEL = 6	---
23141	CEFBS_None, // KILL = 7	---	23141	CEFBS_None, // KILL = 7	---
23142	CEFBS_None, // EXTRACT_SUBREG = 8	---	23142	CEFBS_None, // EXTRACT_SUBREG = 8	---
23143	CEFBS_None, // INSERT_SUBREG = 9	---	23143	CEFBS_None, // INSERT_SUBREG = 9	---
23144	CEFBS_None, // IMPLICIT_DEF = 10	---	23144	CEFBS_None, // IMPLICIT_DEF = 10	---
23145	CEFBS_None, // SUBREG_TO_REG = 11	---	23145	CEFBS_None, // SUBREG_TO_REG = 11	---
23146	CEFBS_None, // COPY_TO_REGCLASS = 12	---	23146	CEFBS_None, // COPY_TO_REGCLASS = 12	---
23147	CEFBS_None, // DBG_VALUE = 13	---	23147	CEFBS_None, // DBG_VALUE = 13	---
23148	CEFBS_None, // DBG_VALUE_LIST = 14	---	23148	CEFBS_None, // DBG_VALUE_LIST = 14	---
23149	CEFBS_None, // DBG_INSTR_REF = 15	---	23149	CEFBS_None, // DBG_INSTR_REF = 15	---
23150	CEFBS_None, // DBG_PHI = 16	---	23150	CEFBS_None, // DBG_PHI = 16	---
23151	CEFBS_None, // DBG_LABEL = 17	---	23151	CEFBS_None, // DBG_LABEL = 17	---
23152	CEFBS_None, // REG_SEQUENCE = 18	---	23152	CEFBS_None, // REG_SEQUENCE = 18	---
23153	CEFBS_None, // COPY = 19	---	23153	CEFBS_None, // COPY = 19	---
23154	CEFBS_None, // BUNDLE = 20	---	23154	CEFBS_None, // BUNDLE = 20	---
23155	CEFBS_None, // LIFETIME_START = 21	---	23155	CEFBS_None, // LIFETIME_START = 21	---
23156	CEFBS_None, // LIFETIME_END = 22	---	23156	CEFBS_None, // LIFETIME_END = 22	---
23157	CEFBS_None, // PSEUDO_PROBE = 23	---	23157	CEFBS_None, // PSEUDO_PROBE = 23	---
23158	CEFBS_None, // ARITH_FENCE = 24	---	23158	CEFBS_None, // ARITH_FENCE = 24	---
23159	CEFBS_None, // STACKMAP = 25	---	23159	CEFBS_None, // STACKMAP = 25	---
23160	CEFBS_None, // FENTRY_CALL = 26	---	23160	CEFBS_None, // FENTRY_CALL = 26	---
23161	CEFBS_None, // PATCHPOINT = 27	---	23161	CEFBS_None, // PATCHPOINT = 27	---
23162	CEFBS_None, // LOAD_STACK_GUARD = 28	---	23162	CEFBS_None, // LOAD_STACK_GUARD = 28	---
23163	CEFBS_None, // PREALLOCATED_SETUP = 29	---	23163	CEFBS_None, // PREALLOCATED_SETUP = 29	---
23164	CEFBS_None, // PREALLOCATED_ARG = 30	---	23164	CEFBS_None, // PREALLOCATED_ARG = 30	---
23165	CEFBS_None, // STATEPOINT = 31	---	23165	CEFBS_None, // STATEPOINT = 31	---
23166	CEFBS_None, // LOCAL_ESCAPE = 32	---	23166	CEFBS_None, // LOCAL_ESCAPE = 32	---
23167	CEFBS_None, // FAULTING_OP = 33	---	23167	CEFBS_None, // FAULTING_OP = 33	---
23168	CEFBS_None, // PATCHABLE_OP = 34	---	23168	CEFBS_None, // PATCHABLE_OP = 34	---
23169	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35	---	23169	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35	---
23170	CEFBS_None, // PATCHABLE_RET = 36	---	23170	CEFBS_None, // PATCHABLE_RET = 36	---
23171	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37	---	23171	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37	---
23172	CEFBS_None, // PATCHABLE_TAIL_CALL = 38	---	23172	CEFBS_None, // PATCHABLE_TAIL_CALL = 38	---
23173	CEFBS_None, // PATCHABLE_EVENT_CALL = 39	---	23173	CEFBS_None, // PATCHABLE_EVENT_CALL = 39	---
23174	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40	---	23174	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40	---
23175	CEFBS_None, // ICALL_BRANCH_FUNNEL = 41	---	23175	CEFBS_None, // ICALL_BRANCH_FUNNEL = 41	---
23176	CEFBS_None, // MEMBARRIER = 42	---	23176	CEFBS_None, // MEMBARRIER = 42	---
23177	CEFBS_None, // G_ASSERT_SEXT = 43	---	23177	CEFBS_None, // G_ASSERT_SEXT = 43	---
23178	CEFBS_None, // G_ASSERT_ZEXT = 44	---	23178	CEFBS_None, // G_ASSERT_ZEXT = 44	---
23179	CEFBS_None, // G_ASSERT_ALIGN = 45	---	23179	CEFBS_None, // G_ASSERT_ALIGN = 45	---
23180	CEFBS_None, // G_ADD = 46	---	23180	CEFBS_None, // G_ADD = 46	---
23181	CEFBS_None, // G_SUB = 47	---	23181	CEFBS_None, // G_SUB = 47	---
23182	CEFBS_None, // G_MUL = 48	---	23182	CEFBS_None, // G_MUL = 48	---
23183	CEFBS_None, // G_SDIV = 49	---	23183	CEFBS_None, // G_SDIV = 49	---
23184	CEFBS_None, // G_UDIV = 50	---	23184	CEFBS_None, // G_UDIV = 50	---
23185	CEFBS_None, // G_SREM = 51	---	23185	CEFBS_None, // G_SREM = 51	---
23186	CEFBS_None, // G_UREM = 52	---	23186	CEFBS_None, // G_UREM = 52	---
23187	CEFBS_None, // G_SDIVREM = 53	---	23187	CEFBS_None, // G_SDIVREM = 53	---
23188	CEFBS_None, // G_UDIVREM = 54	---	23188	CEFBS_None, // G_UDIVREM = 54	---
23189	CEFBS_None, // G_AND = 55	---	23189	CEFBS_None, // G_AND = 55	---
23190	CEFBS_None, // G_OR = 56	---	23190	CEFBS_None, // G_OR = 56	---
23191	CEFBS_None, // G_XOR = 57	---	23191	CEFBS_None, // G_XOR = 57	---
23192	CEFBS_None, // G_IMPLICIT_DEF = 58	---	23192	CEFBS_None, // G_IMPLICIT_DEF = 58	---
23193	CEFBS_None, // G_PHI = 59	---	23193	CEFBS_None, // G_PHI = 59	---
23194	CEFBS_None, // G_FRAME_INDEX = 60	---	23194	CEFBS_None, // G_FRAME_INDEX = 60	---
23195	CEFBS_None, // G_GLOBAL_VALUE = 61	---	23195	CEFBS_None, // G_GLOBAL_VALUE = 61	---
23196	CEFBS_None, // G_CONSTANT_POOL = 62	---	23196	CEFBS_None, // G_CONSTANT_POOL = 62	---
23197	CEFBS_None, // G_EXTRACT = 63	---	23197	CEFBS_None, // G_EXTRACT = 63	---
23198	CEFBS_None, // G_UNMERGE_VALUES = 64	---	23198	CEFBS_None, // G_UNMERGE_VALUES = 64	---
23199	CEFBS_None, // G_INSERT = 65	---	23199	CEFBS_None, // G_INSERT = 65	---
23200	CEFBS_None, // G_MERGE_VALUES = 66	---	23200	CEFBS_None, // G_MERGE_VALUES = 66	---
23201	CEFBS_None, // G_BUILD_VECTOR = 67	---	23201	CEFBS_None, // G_BUILD_VECTOR = 67	---
23202	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 68	---	23202	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 68	---
23203	CEFBS_None, // G_CONCAT_VECTORS = 69	---	23203	CEFBS_None, // G_CONCAT_VECTORS = 69	---
23204	CEFBS_None, // G_PTRTOINT = 70	---	23204	CEFBS_None, // G_PTRTOINT = 70	---
23205	CEFBS_None, // G_INTTOPTR = 71	---	23205	CEFBS_None, // G_INTTOPTR = 71	---
23206	CEFBS_None, // G_BITCAST = 72	---	23206	CEFBS_None, // G_BITCAST = 72	---
23207	CEFBS_None, // G_FREEZE = 73	---	23207	CEFBS_None, // G_FREEZE = 73	---
23208	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 74	---	23208	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 74	---
23209	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 75	---	23209	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 75	---
23210	CEFBS_None, // G_INTRINSIC_TRUNC = 76	---	23210	CEFBS_None, // G_INTRINSIC_TRUNC = 76	---
23211	CEFBS_None, // G_INTRINSIC_ROUND = 77	---	23211	CEFBS_None, // G_INTRINSIC_ROUND = 77	---
23212	CEFBS_None, // G_INTRINSIC_LRINT = 78	---	23212	CEFBS_None, // G_INTRINSIC_LRINT = 78	---
23213	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 79	---	23213	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 79	---
23214	CEFBS_None, // G_READCYCLECOUNTER = 80	---	23214	CEFBS_None, // G_READCYCLECOUNTER = 80	---
23215	CEFBS_None, // G_LOAD = 81	---	23215	CEFBS_None, // G_LOAD = 81	---
23216	CEFBS_None, // G_SEXTLOAD = 82	---	23216	CEFBS_None, // G_SEXTLOAD = 82	---
23217	CEFBS_None, // G_ZEXTLOAD = 83	---	23217	CEFBS_None, // G_ZEXTLOAD = 83	---
23218	CEFBS_None, // G_INDEXED_LOAD = 84	---	23218	CEFBS_None, // G_INDEXED_LOAD = 84	---
23219	CEFBS_None, // G_INDEXED_SEXTLOAD = 85	---	23219	CEFBS_None, // G_INDEXED_SEXTLOAD = 85	---
23220	CEFBS_None, // G_INDEXED_ZEXTLOAD = 86	---	23220	CEFBS_None, // G_INDEXED_ZEXTLOAD = 86	---
23221	CEFBS_None, // G_STORE = 87	---	23221	CEFBS_None, // G_STORE = 87	---
23222	CEFBS_None, // G_INDEXED_STORE = 88	---	23222	CEFBS_None, // G_INDEXED_STORE = 88	---
23223	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89	---	23223	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 89	---
23224	CEFBS_None, // G_ATOMIC_CMPXCHG = 90	---	23224	CEFBS_None, // G_ATOMIC_CMPXCHG = 90	---
23225	CEFBS_None, // G_ATOMICRMW_XCHG = 91	---	23225	CEFBS_None, // G_ATOMICRMW_XCHG = 91	---
23226	CEFBS_None, // G_ATOMICRMW_ADD = 92	---	23226	CEFBS_None, // G_ATOMICRMW_ADD = 92	---
23227	CEFBS_None, // G_ATOMICRMW_SUB = 93	---	23227	CEFBS_None, // G_ATOMICRMW_SUB = 93	---
23228	CEFBS_None, // G_ATOMICRMW_AND = 94	---	23228	CEFBS_None, // G_ATOMICRMW_AND = 94	---
23229	CEFBS_None, // G_ATOMICRMW_NAND = 95	---	23229	CEFBS_None, // G_ATOMICRMW_NAND = 95	---
23230	CEFBS_None, // G_ATOMICRMW_OR = 96	---	23230	CEFBS_None, // G_ATOMICRMW_OR = 96	---
23231	CEFBS_None, // G_ATOMICRMW_XOR = 97	---	23231	CEFBS_None, // G_ATOMICRMW_XOR = 97	---
23232	CEFBS_None, // G_ATOMICRMW_MAX = 98	---	23232	CEFBS_None, // G_ATOMICRMW_MAX = 98	---
23233	CEFBS_None, // G_ATOMICRMW_MIN = 99	---	23233	CEFBS_None, // G_ATOMICRMW_MIN = 99	---
23234	CEFBS_None, // G_ATOMICRMW_UMAX = 100	---	23234	CEFBS_None, // G_ATOMICRMW_UMAX = 100	---
23235	CEFBS_None, // G_ATOMICRMW_UMIN = 101	---	23235	CEFBS_None, // G_ATOMICRMW_UMIN = 101	---
23236	CEFBS_None, // G_ATOMICRMW_FADD = 102	---	23236	CEFBS_None, // G_ATOMICRMW_FADD = 102	---
23237	CEFBS_None, // G_ATOMICRMW_FSUB = 103	---	23237	CEFBS_None, // G_ATOMICRMW_FSUB = 103	---
23238	CEFBS_None, // G_ATOMICRMW_FMAX = 104	---	23238	CEFBS_None, // G_ATOMICRMW_FMAX = 104	---
23239	CEFBS_None, // G_ATOMICRMW_FMIN = 105	---	23239	CEFBS_None, // G_ATOMICRMW_FMIN = 105	---
23240	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 106	---	23240	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 106	---
23241	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 107	---	23241	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 107	---
23242	CEFBS_None, // G_FENCE = 108	---	23242	CEFBS_None, // G_FENCE = 108	---
23243	CEFBS_None, // G_BRCOND = 109	---	23243	CEFBS_None, // G_BRCOND = 109	---
23244	CEFBS_None, // G_BRINDIRECT = 110	---	23244	CEFBS_None, // G_BRINDIRECT = 110	---
23245	CEFBS_None, // G_INVOKE_REGION_START = 111	---	23245	CEFBS_None, // G_INVOKE_REGION_START = 111	---
23246	CEFBS_None, // G_INTRINSIC = 112	---	23246	CEFBS_None, // G_INTRINSIC = 112	---
23247	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 113	---	23247	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 113	---
23248	CEFBS_None, // G_ANYEXT = 114	---	23248	CEFBS_None, // G_ANYEXT = 114	---
23249	CEFBS_None, // G_TRUNC = 115	---	23249	CEFBS_None, // G_TRUNC = 115	---
23250	CEFBS_None, // G_CONSTANT = 116	---	23250	CEFBS_None, // G_CONSTANT = 116	---
23251	CEFBS_None, // G_FCONSTANT = 117	---	23251	CEFBS_None, // G_FCONSTANT = 117	---
23252	CEFBS_None, // G_VASTART = 118	---	23252	CEFBS_None, // G_VASTART = 118	---
23253	CEFBS_None, // G_VAARG = 119	---	23253	CEFBS_None, // G_VAARG = 119	---
23254	CEFBS_None, // G_SEXT = 120	---	23254	CEFBS_None, // G_SEXT = 120	---
23255	CEFBS_None, // G_SEXT_INREG = 121	---	23255	CEFBS_None, // G_SEXT_INREG = 121	---
23256	CEFBS_None, // G_ZEXT = 122	---	23256	CEFBS_None, // G_ZEXT = 122	---
23257	CEFBS_None, // G_SHL = 123	---	23257	CEFBS_None, // G_SHL = 123	---
23258	CEFBS_None, // G_LSHR = 124	---	23258	CEFBS_None, // G_LSHR = 124	---
23259	CEFBS_None, // G_ASHR = 125	---	23259	CEFBS_None, // G_ASHR = 125	---
23260	CEFBS_None, // G_FSHL = 126	---	23260	CEFBS_None, // G_FSHL = 126	---
23261	CEFBS_None, // G_FSHR = 127	---	23261	CEFBS_None, // G_FSHR = 127	---
23262	CEFBS_None, // G_ROTR = 128	---	23262	CEFBS_None, // G_ROTR = 128	---
23263	CEFBS_None, // G_ROTL = 129	---	23263	CEFBS_None, // G_ROTL = 129	---
23264	CEFBS_None, // G_ICMP = 130	---	23264	CEFBS_None, // G_ICMP = 130	---
23265	CEFBS_None, // G_FCMP = 131	---	23265	CEFBS_None, // G_FCMP = 131	---
23266	CEFBS_None, // G_SELECT = 132	---	23266	CEFBS_None, // G_SELECT = 132	---
23267	CEFBS_None, // G_UADDO = 133	---	23267	CEFBS_None, // G_UADDO = 133	---
23268	CEFBS_None, // G_UADDE = 134	---	23268	CEFBS_None, // G_UADDE = 134	---
23269	CEFBS_None, // G_USUBO = 135	---	23269	CEFBS_None, // G_USUBO = 135	---
23270	CEFBS_None, // G_USUBE = 136	---	23270	CEFBS_None, // G_USUBE = 136	---
23271	CEFBS_None, // G_SADDO = 137	---	23271	CEFBS_None, // G_SADDO = 137	---
23272	CEFBS_None, // G_SADDE = 138	---	23272	CEFBS_None, // G_SADDE = 138	---
23273	CEFBS_None, // G_SSUBO = 139	---	23273	CEFBS_None, // G_SSUBO = 139	---
23274	CEFBS_None, // G_SSUBE = 140	---	23274	CEFBS_None, // G_SSUBE = 140	---
23275	CEFBS_None, // G_UMULO = 141	---	23275	CEFBS_None, // G_UMULO = 141	---
23276	CEFBS_None, // G_SMULO = 142	---	23276	CEFBS_None, // G_SMULO = 142	---
23277	CEFBS_None, // G_UMULH = 143	---	23277	CEFBS_None, // G_UMULH = 143	---
23278	CEFBS_None, // G_SMULH = 144	---	23278	CEFBS_None, // G_SMULH = 144	---
23279	CEFBS_None, // G_UADDSAT = 145	---	23279	CEFBS_None, // G_UADDSAT = 145	---
23280	CEFBS_None, // G_SADDSAT = 146	---	23280	CEFBS_None, // G_SADDSAT = 146	---
23281	CEFBS_None, // G_USUBSAT = 147	---	23281	CEFBS_None, // G_USUBSAT = 147	---
23282	CEFBS_None, // G_SSUBSAT = 148	---	23282	CEFBS_None, // G_SSUBSAT = 148	---
23283	CEFBS_None, // G_USHLSAT = 149	---	23283	CEFBS_None, // G_USHLSAT = 149	---
23284	CEFBS_None, // G_SSHLSAT = 150	---	23284	CEFBS_None, // G_SSHLSAT = 150	---
23285	CEFBS_None, // G_SMULFIX = 151	---	23285	CEFBS_None, // G_SMULFIX = 151	---
23286	CEFBS_None, // G_UMULFIX = 152	---	23286	CEFBS_None, // G_UMULFIX = 152	---
23287	CEFBS_None, // G_SMULFIXSAT = 153	---	23287	CEFBS_None, // G_SMULFIXSAT = 153	---
23288	CEFBS_None, // G_UMULFIXSAT = 154	---	23288	CEFBS_None, // G_UMULFIXSAT = 154	---
23289	CEFBS_None, // G_SDIVFIX = 155	---	23289	CEFBS_None, // G_SDIVFIX = 155	---
23290	CEFBS_None, // G_UDIVFIX = 156	---	23290	CEFBS_None, // G_UDIVFIX = 156	---
23291	CEFBS_None, // G_SDIVFIXSAT = 157	---	23291	CEFBS_None, // G_SDIVFIXSAT = 157	---
23292	CEFBS_None, // G_UDIVFIXSAT = 158	---	23292	CEFBS_None, // G_UDIVFIXSAT = 158	---
23293	CEFBS_None, // G_FADD = 159	---	23293	CEFBS_None, // G_FADD = 159	---
23294	CEFBS_None, // G_FSUB = 160	---	23294	CEFBS_None, // G_FSUB = 160	---
23295	CEFBS_None, // G_FMUL = 161	---	23295	CEFBS_None, // G_FMUL = 161	---
23296	CEFBS_None, // G_FMA = 162	---	23296	CEFBS_None, // G_FMA = 162	---
23297	CEFBS_None, // G_FMAD = 163	---	23297	CEFBS_None, // G_FMAD = 163	---
23298	CEFBS_None, // G_FDIV = 164	---	23298	CEFBS_None, // G_FDIV = 164	---
23299	CEFBS_None, // G_FREM = 165	---	23299	CEFBS_None, // G_FREM = 165	---
23300	CEFBS_None, // G_FPOW = 166	---	23300	CEFBS_None, // G_FPOW = 166	---
23301	CEFBS_None, // G_FPOWI = 167	---	23301	CEFBS_None, // G_FPOWI = 167	---
23302	CEFBS_None, // G_FEXP = 168	---	23302	CEFBS_None, // G_FEXP = 168	---
23303	CEFBS_None, // G_FEXP2 = 169	---	23303	CEFBS_None, // G_FEXP2 = 169	---
23304	CEFBS_None, // G_FLOG = 170	---	23304	CEFBS_None, // G_FLOG = 170	---
23305	CEFBS_None, // G_FLOG2 = 171	---	23305	CEFBS_None, // G_FLOG2 = 171	---
23306	CEFBS_None, // G_FLOG10 = 172	---	23306	CEFBS_None, // G_FLOG10 = 172	---
23307	CEFBS_None, // G_FLDEXP = 173	---	23307	CEFBS_None, // G_FLDEXP = 173	---
23308	CEFBS_None, // G_FFREXP = 174	---	23308	CEFBS_None, // G_FFREXP = 174	---
23309	CEFBS_None, // G_FNEG = 175	---	23309	CEFBS_None, // G_FNEG = 175	---
23310	CEFBS_None, // G_FPEXT = 176	---	23310	CEFBS_None, // G_FPEXT = 176	---
23311	CEFBS_None, // G_FPTRUNC = 177	---	23311	CEFBS_None, // G_FPTRUNC = 177	---
23312	CEFBS_None, // G_FPTOSI = 178	---	23312	CEFBS_None, // G_FPTOSI = 178	---
23313	CEFBS_None, // G_FPTOUI = 179	---	23313	CEFBS_None, // G_FPTOUI = 179	---
23314	CEFBS_None, // G_SITOFP = 180	---	23314	CEFBS_None, // G_SITOFP = 180	---
23315	CEFBS_None, // G_UITOFP = 181	---	23315	CEFBS_None, // G_UITOFP = 181	---
23316	CEFBS_None, // G_FABS = 182	---	23316	CEFBS_None, // G_FABS = 182	---
23317	CEFBS_None, // G_FCOPYSIGN = 183	---	23317	CEFBS_None, // G_FCOPYSIGN = 183	---
23318	CEFBS_None, // G_IS_FPCLASS = 184	---	23318	CEFBS_None, // G_IS_FPCLASS = 184	---
23319	CEFBS_None, // G_FCANONICALIZE = 185	---	23319	CEFBS_None, // G_FCANONICALIZE = 185	---
23320	CEFBS_None, // G_FMINNUM = 186	---	23320	CEFBS_None, // G_FMINNUM = 186	---
23321	CEFBS_None, // G_FMAXNUM = 187	---	23321	CEFBS_None, // G_FMAXNUM = 187	---
23322	CEFBS_None, // G_FMINNUM_IEEE = 188	---	23322	CEFBS_None, // G_FMINNUM_IEEE = 188	---
23323	CEFBS_None, // G_FMAXNUM_IEEE = 189	---	23323	CEFBS_None, // G_FMAXNUM_IEEE = 189	---
23324	CEFBS_None, // G_FMINIMUM = 190	---	23324	CEFBS_None, // G_FMINIMUM = 190	---
23325	CEFBS_None, // G_FMAXIMUM = 191	---	23325	CEFBS_None, // G_FMAXIMUM = 191	---
23326	CEFBS_None, // G_PTR_ADD = 192	---	23326	CEFBS_None, // G_PTR_ADD = 192	---
23327	CEFBS_None, // G_PTRMASK = 193	---	23327	CEFBS_None, // G_PTRMASK = 193	---
23328	CEFBS_None, // G_SMIN = 194	---	23328	CEFBS_None, // G_SMIN = 194	---
23329	CEFBS_None, // G_SMAX = 195	---	23329	CEFBS_None, // G_SMAX = 195	---
23330	CEFBS_None, // G_UMIN = 196	---	23330	CEFBS_None, // G_UMIN = 196	---
23331	CEFBS_None, // G_UMAX = 197	---	23331	CEFBS_None, // G_UMAX = 197	---
23332	CEFBS_None, // G_ABS = 198	---	23332	CEFBS_None, // G_ABS = 198	---
23333	CEFBS_None, // G_LROUND = 199	---	23333	CEFBS_None, // G_LROUND = 199	---
23334	CEFBS_None, // G_LLROUND = 200	---	23334	CEFBS_None, // G_LLROUND = 200	---
23335	CEFBS_None, // G_BR = 201	---	23335	CEFBS_None, // G_BR = 201	---
23336	CEFBS_None, // G_BRJT = 202	---	23336	CEFBS_None, // G_BRJT = 202	---
23337	CEFBS_None, // G_INSERT_VECTOR_ELT = 203	---	23337	CEFBS_None, // G_INSERT_VECTOR_ELT = 203	---
23338	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 204	---	23338	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 204	---
23339	CEFBS_None, // G_SHUFFLE_VECTOR = 205	---	23339	CEFBS_None, // G_SHUFFLE_VECTOR = 205	---
23340	CEFBS_None, // G_CTTZ = 206	---	23340	CEFBS_None, // G_CTTZ = 206	---
23341	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 207	---	23341	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 207	---
23342	CEFBS_None, // G_CTLZ = 208	---	23342	CEFBS_None, // G_CTLZ = 208	---
23343	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 209	---	23343	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 209	---
23344	CEFBS_None, // G_CTPOP = 210	---	23344	CEFBS_None, // G_CTPOP = 210	---
23345	CEFBS_None, // G_BSWAP = 211	---	23345	CEFBS_None, // G_BSWAP = 211	---
23346	CEFBS_None, // G_BITREVERSE = 212	---	23346	CEFBS_None, // G_BITREVERSE = 212	---
23347	CEFBS_None, // G_FCEIL = 213	---	23347	CEFBS_None, // G_FCEIL = 213	---
23348	CEFBS_None, // G_FCOS = 214	---	23348	CEFBS_None, // G_FCOS = 214	---
23349	CEFBS_None, // G_FSIN = 215	---	23349	CEFBS_None, // G_FSIN = 215	---
23350	CEFBS_None, // G_FSQRT = 216	---	23350	CEFBS_None, // G_FSQRT = 216	---
23351	CEFBS_None, // G_FFLOOR = 217	---	23351	CEFBS_None, // G_FFLOOR = 217	---
23352	CEFBS_None, // G_FRINT = 218	---	23352	CEFBS_None, // G_FRINT = 218	---
23353	CEFBS_None, // G_FNEARBYINT = 219	---	23353	CEFBS_None, // G_FNEARBYINT = 219	---
23354	CEFBS_None, // G_ADDRSPACE_CAST = 220	---	23354	CEFBS_None, // G_ADDRSPACE_CAST = 220	---
23355	CEFBS_None, // G_BLOCK_ADDR = 221	---	23355	CEFBS_None, // G_BLOCK_ADDR = 221	---
23356	CEFBS_None, // G_JUMP_TABLE = 222	---	23356	CEFBS_None, // G_JUMP_TABLE = 222	---
23357	CEFBS_None, // G_DYN_STACKALLOC = 223	---	23357	CEFBS_None, // G_DYN_STACKALLOC = 223	---
23358	CEFBS_None, // G_STRICT_FADD = 224	---	23358	CEFBS_None, // G_STRICT_FADD = 224	---
23359	CEFBS_None, // G_STRICT_FSUB = 225	---	23359	CEFBS_None, // G_STRICT_FSUB = 225	---
23360	CEFBS_None, // G_STRICT_FMUL = 226	---	23360	CEFBS_None, // G_STRICT_FMUL = 226	---
23361	CEFBS_None, // G_STRICT_FDIV = 227	---	23361	CEFBS_None, // G_STRICT_FDIV = 227	---
23362	CEFBS_None, // G_STRICT_FREM = 228	---	23362	CEFBS_None, // G_STRICT_FREM = 228	---
23363	CEFBS_None, // G_STRICT_FMA = 229	---	23363	CEFBS_None, // G_STRICT_FMA = 229	---
23364	CEFBS_None, // G_STRICT_FSQRT = 230	---	23364	CEFBS_None, // G_STRICT_FSQRT = 230	---
23365	CEFBS_None, // G_STRICT_FLDEXP = 231	---	23365	CEFBS_None, // G_STRICT_FLDEXP = 231	---
23366	CEFBS_None, // G_READ_REGISTER = 232	---	23366	CEFBS_None, // G_READ_REGISTER = 232	---
23367	CEFBS_None, // G_WRITE_REGISTER = 233	---	23367	CEFBS_None, // G_WRITE_REGISTER = 233	---
23368	CEFBS_None, // G_MEMCPY = 234	---	23368	CEFBS_None, // G_MEMCPY = 234	---
23369	CEFBS_None, // G_MEMCPY_INLINE = 235	---	23369	CEFBS_None, // G_MEMCPY_INLINE = 235	---
23370	CEFBS_None, // G_MEMMOVE = 236	---	23370	CEFBS_None, // G_MEMMOVE = 236	---
23371	CEFBS_None, // G_MEMSET = 237	---	23371	CEFBS_None, // G_MEMSET = 237	---
23372	CEFBS_None, // G_BZERO = 238	---	23372	CEFBS_None, // G_BZERO = 238	---
23373	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 239	---	23373	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 239	---
23374	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 240	---	23374	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 240	---
23375	CEFBS_None, // G_VECREDUCE_FADD = 241	---	23375	CEFBS_None, // G_VECREDUCE_FADD = 241	---
23376	CEFBS_None, // G_VECREDUCE_FMUL = 242	---	23376	CEFBS_None, // G_VECREDUCE_FMUL = 242	---
23377	CEFBS_None, // G_VECREDUCE_FMAX = 243	---	23377	CEFBS_None, // G_VECREDUCE_FMAX = 243	---
23378	CEFBS_None, // G_VECREDUCE_FMIN = 244	---	23378	CEFBS_None, // G_VECREDUCE_FMIN = 244	---
23379	CEFBS_None, // G_VECREDUCE_ADD = 245	---	23379	CEFBS_None, // G_VECREDUCE_ADD = 245	---
23380	CEFBS_None, // G_VECREDUCE_MUL = 246	---	23380	CEFBS_None, // G_VECREDUCE_MUL = 246	---
23381	CEFBS_None, // G_VECREDUCE_AND = 247	---	23381	CEFBS_None, // G_VECREDUCE_AND = 247	---
23382	CEFBS_None, // G_VECREDUCE_OR = 248	---	23382	CEFBS_None, // G_VECREDUCE_OR = 248	---
23383	CEFBS_None, // G_VECREDUCE_XOR = 249	---	23383	CEFBS_None, // G_VECREDUCE_XOR = 249	---
23384	CEFBS_None, // G_VECREDUCE_SMAX = 250	---	23384	CEFBS_None, // G_VECREDUCE_SMAX = 250	---
23385	CEFBS_None, // G_VECREDUCE_SMIN = 251	---	23385	CEFBS_None, // G_VECREDUCE_SMIN = 251	---
23386	CEFBS_None, // G_VECREDUCE_UMAX = 252	---	23386	CEFBS_None, // G_VECREDUCE_UMAX = 252	---
23387	CEFBS_None, // G_VECREDUCE_UMIN = 253	---	23387	CEFBS_None, // G_VECREDUCE_UMIN = 253	---
23388	CEFBS_None, // G_SBFX = 254	---	23388	CEFBS_None, // G_SBFX = 254	---
23389	CEFBS_None, // G_UBFX = 255	---	23389	CEFBS_None, // G_UBFX = 255	---
23390	CEFBS_None, // ABSMacro = 256	---	23390	CEFBS_None, // ABSMacro = 256	---
23391	CEFBS_None, // ADJCALLSTACKDOWN = 257	---	23391	CEFBS_None, // ADJCALLSTACKDOWN = 257	---
23392	CEFBS_None, // ADJCALLSTACKUP = 258	---	23392	CEFBS_None, // ADJCALLSTACKUP = 258	---
23393	CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 259	---	23393	CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 259	---
23394	CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 260	---	23394	CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 260	---
23395	CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 261	---	23395	CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 261	---
23396	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 262	---	23396	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 262	---
23397	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 263	---	23397	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 263	---
23398	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 264	---	23398	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 264	---
23399	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 265	---	23399	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 265	---
23400	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 266	---	23400	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 266	---
23401	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 267	---	23401	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 267	---
23402	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 268	---	23402	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 268	---
23403	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 269	---	23403	CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 269	---
23404	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 270	---	23404	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 270	---
23405	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 271	---	23405	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 271	---
23406	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 272	---	23406	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 272	---
23407	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 273	---	23407	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 273	---
23408	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 274	---	23408	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 274	---
23409	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 275	---	23409	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 275	---
23410	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 276	---	23410	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 276	---
23411	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 277	---	23411	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 277	---
23412	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 278	---	23412	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 278	---
23413	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 279	---	23413	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 279	---
23414	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 280	---	23414	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 280	---
23415	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 281	---	23415	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 281	---
23416	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 282	---	23416	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 282	---
23417	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 283	---	23417	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 283	---
23418	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 284	---	23418	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 284	---
23419	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 285	---	23419	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 285	---
23420	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 286	---	23420	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 286	---
23421	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 287	---	23421	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 287	---
23422	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 288	---	23422	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 288	---
23423	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 289	---	23423	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 289	---
23424	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 290	---	23424	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 290	---
23425	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 291	---	23425	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 291	---
23426	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 292	---	23426	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 292	---
23427	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 293	---	23427	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 293	---
23428	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 294	---	23428	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 294	---
23429	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 295	---	23429	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 295	---
23430	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 296	---	23430	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 296	---
23431	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 297	---	23431	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 297	---
23432	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 298	---	23432	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 298	---
23433	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 299	---	23433	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 299	---
23434	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 300	---	23434	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 300	---
23435	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 301	---	23435	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 301	---
23436	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 302	---	23436	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 302	---
23437	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 303	---	23437	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 303	---
23438	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 304	---	23438	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 304	---
23439	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 305	---	23439	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 305	---
23440	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 306	---	23440	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 306	---
23441	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 307	---	23441	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 307	---
23442	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 308	---	23442	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 308	---
23443	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 309	---	23443	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 309	---
23444	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 310	---	23444	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 310	---
23445	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 311	---	23445	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 311	---
23446	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 312	---	23446	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 312	---
23447	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 313	---	23447	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 313	---
23448	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 314	---	23448	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 314	---
23449	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 315	---	23449	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 315	---
23450	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 316	---	23450	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 316	---
23451	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 317	---	23451	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 317	---
23452	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 318	---	23452	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 318	---
23453	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 319	---	23453	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 319	---
23454	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 320	---	23454	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 320	---
23455	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 321	---	23455	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 321	---
23456	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 322	---	23456	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 322	---
23457	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 323	---	23457	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 323	---
23458	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 324	---	23458	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 324	---
23459	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 325	---	23459	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 325	---
23460	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 326	---	23460	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 326	---
23461	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 327	---	23461	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 327	---
23462	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 328	---	23462	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 328	---
23463	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 329	---	23463	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 329	---
23464	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 330	---	23464	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 330	---
23465	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 331	---	23465	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 331	---
23466	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 332	---	23466	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 332	---
23467	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 333	---	23467	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 333	---
23468	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 334	---	23468	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 334	---
23469	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 335	---	23469	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 335	---
23470	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 336	---	23470	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 336	---
23471	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 337	---	23471	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 337	---
23472	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 338	---	23472	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 338	---
23473	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 339	---	23473	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 339	---
23474	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 340	---	23474	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 340	---
23475	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 341	---	23475	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 341	---
23476	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 342	---	23476	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 342	---
23477	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 343	---	23477	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 343	---
23478	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 344	---	23478	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 344	---
23479	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 345	---	23479	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 345	---
23480	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 346	---	23480	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 346	---
23481	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 347	---	23481	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 347	---
23482	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 348	---	23482	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 348	---
23483	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 349	---	23483	CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 349	---
23484	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 350	---	23484	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 350	---
23485	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 351	---	23485	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 351	---
23486	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 352	---	23486	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 352	---
23487	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 353	---	23487	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 353	---
23488	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 354	---	23488	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 354	---
23489	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 355	---	23489	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 355	---
23490	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 356	---	23490	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 356	---
23491	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 357	---	23491	CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 357	---
23492	CEFBS_HasStdEnc_NotInMicroMips, // B = 358	---	23492	CEFBS_HasStdEnc_NotInMicroMips, // B = 358	---
23493	CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 359	---	23493	CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 359	---
23494	CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 360	---	23494	CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 360	---
23495	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 361	---	23495	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 361	---
23496	CEFBS_None, // BGE = 362	---	23496	CEFBS_None, // BGE = 362	---
23497	CEFBS_None, // BGEImmMacro = 363	---	23497	CEFBS_None, // BGEImmMacro = 363	---
23498	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 364	---	23498	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 364	---
23499	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 365	---	23499	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 365	---
23500	CEFBS_None, // BGEU = 366	---	23500	CEFBS_None, // BGEU = 366	---
23501	CEFBS_None, // BGEUImmMacro = 367	---	23501	CEFBS_None, // BGEUImmMacro = 367	---
23502	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 368	---	23502	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 368	---
23503	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 369	---	23503	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 369	---
23504	CEFBS_None, // BGT = 370	---	23504	CEFBS_None, // BGT = 370	---
23505	CEFBS_None, // BGTImmMacro = 371	---	23505	CEFBS_None, // BGTImmMacro = 371	---
23506	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 372	---	23506	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 372	---
23507	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 373	---	23507	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 373	---
23508	CEFBS_None, // BGTU = 374	---	23508	CEFBS_None, // BGTU = 374	---
23509	CEFBS_None, // BGTUImmMacro = 375	---	23509	CEFBS_None, // BGTUImmMacro = 375	---
23510	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 376	---	23510	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 376	---
23511	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 377	---	23511	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 377	---
23512	CEFBS_None, // BLE = 378	---	23512	CEFBS_None, // BLE = 378	---
23513	CEFBS_None, // BLEImmMacro = 379	---	23513	CEFBS_None, // BLEImmMacro = 379	---
23514	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 380	---	23514	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 380	---
23515	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 381	---	23515	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 381	---
23516	CEFBS_None, // BLEU = 382	---	23516	CEFBS_None, // BLEU = 382	---
23517	CEFBS_None, // BLEUImmMacro = 383	---	23517	CEFBS_None, // BLEUImmMacro = 383	---
23518	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 384	---	23518	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 384	---
23519	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 385	---	23519	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 385	---
23520	CEFBS_None, // BLT = 386	---	23520	CEFBS_None, // BLT = 386	---
23521	CEFBS_None, // BLTImmMacro = 387	---	23521	CEFBS_None, // BLTImmMacro = 387	---
23522	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 388	---	23522	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 388	---
23523	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 389	---	23523	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 389	---
23524	CEFBS_None, // BLTU = 390	---	23524	CEFBS_None, // BLTU = 390	---
23525	CEFBS_None, // BLTUImmMacro = 391	---	23525	CEFBS_None, // BLTUImmMacro = 391	---
23526	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 392	---	23526	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 392	---
23527	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 393	---	23527	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 393	---
23528	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 394	---	23528	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 394	---
23529	CEFBS_None, // BPOSGE32_PSEUDO = 395	---	23529	CEFBS_None, // BPOSGE32_PSEUDO = 395	---
23530	CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 396	---	23530	CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 396	---
23531	CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 397	---	23531	CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 397	---
23532	CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 398	---	23532	CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 398	---
23533	CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 399	---	23533	CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 399	---
23534	CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 400	---	23534	CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 400	---
23535	CEFBS_InMicroMips_NotMips32r6, // B_MM = 401	---	23535	CEFBS_InMicroMips_NotMips32r6, // B_MM = 401	---
23536	CEFBS_None, // B_MMR6_Pseudo = 402	---	23536	CEFBS_None, // B_MMR6_Pseudo = 402	---
23537	CEFBS_InMicroMips, // B_MM_Pseudo = 403	---	23537	CEFBS_InMicroMips, // B_MM_Pseudo = 403	---
23538	CEFBS_None, // BeqImm = 404	---	23538	CEFBS_None, // BeqImm = 404	---
23539	CEFBS_None, // BneImm = 405	---	23539	CEFBS_None, // BneImm = 405	---
23540	CEFBS_InMips16Mode, // BteqzT8CmpX16 = 406	---	23540	CEFBS_InMips16Mode, // BteqzT8CmpX16 = 406	---
23541	CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 407	---	23541	CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 407	---
23542	CEFBS_InMips16Mode, // BteqzT8SltX16 = 408	---	23542	CEFBS_InMips16Mode, // BteqzT8SltX16 = 408	---
23543	CEFBS_InMips16Mode, // BteqzT8SltiX16 = 409	---	23543	CEFBS_InMips16Mode, // BteqzT8SltiX16 = 409	---
23544	CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 410	---	23544	CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 410	---
23545	CEFBS_InMips16Mode, // BteqzT8SltuX16 = 411	---	23545	CEFBS_InMips16Mode, // BteqzT8SltuX16 = 411	---
23546	CEFBS_InMips16Mode, // BtnezT8CmpX16 = 412	---	23546	CEFBS_InMips16Mode, // BtnezT8CmpX16 = 412	---
23547	CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 413	---	23547	CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 413	---
23548	CEFBS_InMips16Mode, // BtnezT8SltX16 = 414	---	23548	CEFBS_InMips16Mode, // BtnezT8SltX16 = 414	---
23549	CEFBS_InMips16Mode, // BtnezT8SltiX16 = 415	---	23549	CEFBS_InMips16Mode, // BtnezT8SltiX16 = 415	---
23550	CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 416	---	23550	CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 416	---
23551	CEFBS_InMips16Mode, // BtnezT8SltuX16 = 417	---	23551	CEFBS_InMips16Mode, // BtnezT8SltuX16 = 417	---
23552	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 418	---	23552	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 418	---
23553	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 419	---	23553	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 419	---
23554	CEFBS_HasMT, // CFTC1 = 420	---	23554	CEFBS_HasMT, // CFTC1 = 420	---
23555	CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 421	---	23555	CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 421	---
23556	CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 422	---	23556	CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 422	---
23557	CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 423	---	23557	CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 423	---
23558	CEFBS_HasMT, // CTTC1 = 424	---	23558	CEFBS_HasMT, // CTTC1 = 424	---
23559	CEFBS_InMips16Mode, // Constant32 = 425	---	23559	CEFBS_InMips16Mode, // Constant32 = 425	---
23560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 426	---	23560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 426	---
23561	CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 427	---	23561	CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 427	---
23562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 428	---	23562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 428	---
23563	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 429	---	23563	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 429	---
23564	CEFBS_HasStdEnc_HasMips64, // DROL = 430	---	23564	CEFBS_HasStdEnc_HasMips64, // DROL = 430	---
23565	CEFBS_HasStdEnc_HasMips64, // DROLImm = 431	---	23565	CEFBS_HasStdEnc_HasMips64, // DROLImm = 431	---
23566	CEFBS_HasStdEnc_HasMips64, // DROR = 432	---	23566	CEFBS_HasStdEnc_HasMips64, // DROR = 432	---
23567	CEFBS_HasStdEnc_HasMips64, // DRORImm = 433	---	23567	CEFBS_HasStdEnc_HasMips64, // DRORImm = 433	---
23568	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 434	---	23568	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 434	---
23569	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 435	---	23569	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 435	---
23570	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 436	---	23570	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 436	---
23571	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 437	---	23571	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 437	---
23572	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 438	---	23572	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 438	---
23573	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 439	---	23573	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 439	---
23574	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 440	---	23574	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 440	---
23575	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 441	---	23575	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 441	---
23576	CEFBS_NotInMips16Mode, // ERet = 442	---	23576	CEFBS_NotInMips16Mode, // ERet = 442	---
23577	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 443	---	23577	CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 443	---
23578	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 444	---	23578	CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 444	---
23579	CEFBS_HasStdEnc_HasMSA, // FABS_D = 445	---	23579	CEFBS_HasStdEnc_HasMSA, // FABS_D = 445	---
23580	CEFBS_HasStdEnc_HasMSA, // FABS_W = 446	---	23580	CEFBS_HasStdEnc_HasMSA, // FABS_W = 446	---
23581	CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 447	---	23581	CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 447	---
23582	CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 448	---	23582	CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 448	---
23583	CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 449	---	23583	CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 449	---
23584	CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 450	---	23584	CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 450	---
23585	CEFBS_InMips16Mode, // GotPrologue16 = 451	---	23585	CEFBS_InMips16Mode, // GotPrologue16 = 451	---
23586	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 452	---	23586	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 452	---
23587	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 453	---	23587	CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 453	---
23588	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 454	---	23588	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 454	---
23589	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 455	---	23589	CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 455	---
23590	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 456	---	23590	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 456	---
23591	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 457	---	23591	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 457	---
23592	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 458	---	23592	CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 458	---
23593	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 459	---	23593	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 459	---
23594	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 460	---	23594	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 460	---
23595	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 461	---	23595	CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 461	---
23596	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 462	---	23596	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 462	---
23597	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 463	---	23597	CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 463	---
23598	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 464	---	23598	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 464	---
23599	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 465	---	23599	CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 465	---
23600	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 466	---	23600	CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 466	---
23601	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 467	---	23601	CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 467	---
23602	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 468	---	23602	CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 468	---
23603	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 469	---	23603	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 469	---
23604	CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 470	---	23604	CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 470	---
23605	CEFBS_None, // JalOneReg = 471	---	23605	CEFBS_None, // JalOneReg = 471	---
23606	CEFBS_None, // JalTwoReg = 472	---	23606	CEFBS_None, // JalTwoReg = 472	---
23607	CEFBS_HasStdEnc_NotMips3, // LDMacro = 473	---	23607	CEFBS_HasStdEnc_NotMips3, // LDMacro = 473	---
23608	CEFBS_NotInMips16Mode, // LDR_D = 474	---	23608	CEFBS_NotInMips16Mode, // LDR_D = 474	---
23609	CEFBS_NotInMips16Mode, // LDR_W = 475	---	23609	CEFBS_NotInMips16Mode, // LDR_W = 475	---
23610	CEFBS_HasMSA, // LD_F16 = 476	---	23610	CEFBS_HasMSA, // LD_F16 = 476	---
23611	CEFBS_NotInMips16Mode, // LOAD_ACC128 = 477	---	23611	CEFBS_NotInMips16Mode, // LOAD_ACC128 = 477	---
23612	CEFBS_NotInMips16Mode, // LOAD_ACC64 = 478	---	23612	CEFBS_NotInMips16Mode, // LOAD_ACC64 = 478	---
23613	CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 479	---	23613	CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 479	---
23614	CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 480	---	23614	CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 480	---
23615	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 481	---	23615	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 481	---
23616	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 482	---	23616	CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 482	---
23617	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 483	---	23617	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 483	---
23618	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 484	---	23618	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 484	---
23619	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 485	---	23619	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 485	---
23620	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 486	---	23620	CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 486	---
23621	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 487	---	23621	CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 487	---
23622	CEFBS_InMicroMips, // LWM_MM = 488	---	23622	CEFBS_InMicroMips, // LWM_MM = 488	---
23623	CEFBS_None, // LoadAddrImm32 = 489	---	23623	CEFBS_None, // LoadAddrImm32 = 489	---
23624	CEFBS_None, // LoadAddrImm64 = 490	---	23624	CEFBS_None, // LoadAddrImm64 = 490	---
23625	CEFBS_None, // LoadAddrReg32 = 491	---	23625	CEFBS_None, // LoadAddrReg32 = 491	---
23626	CEFBS_None, // LoadAddrReg64 = 492	---	23626	CEFBS_None, // LoadAddrReg64 = 492	---
23627	CEFBS_None, // LoadImm32 = 493	---	23627	CEFBS_None, // LoadImm32 = 493	---
23628	CEFBS_None, // LoadImm64 = 494	---	23628	CEFBS_None, // LoadImm64 = 494	---
23629	CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 495	---	23629	CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 495	---
23630	CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 496	---	23630	CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 496	---
23631	CEFBS_None, // LoadImmDoubleGPR = 497	---	23631	CEFBS_None, // LoadImmDoubleGPR = 497	---
23632	CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 498	---	23632	CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 498	---
23633	CEFBS_None, // LoadImmSingleGPR = 499	---	23633	CEFBS_None, // LoadImmSingleGPR = 499	---
23634	CEFBS_InMips16Mode, // LwConstant32 = 500	---	23634	CEFBS_InMips16Mode, // LwConstant32 = 500	---
23635	CEFBS_HasMT, // MFTACX = 501	---	23635	CEFBS_HasMT, // MFTACX = 501	---
23636	CEFBS_HasMT, // MFTC0 = 502	---	23636	CEFBS_HasMT, // MFTC0 = 502	---
23637	CEFBS_HasMT, // MFTC1 = 503	---	23637	CEFBS_HasMT, // MFTC1 = 503	---
23638	CEFBS_HasMT, // MFTDSP = 504	---	23638	CEFBS_HasMT, // MFTDSP = 504	---
23639	CEFBS_HasMT, // MFTGPR = 505	---	23639	CEFBS_HasMT, // MFTGPR = 505	---
23640	CEFBS_HasMT, // MFTHC1 = 506	---	23640	CEFBS_HasMT, // MFTHC1 = 506	---
23641	CEFBS_HasMT, // MFTHI = 507	---	23641	CEFBS_HasMT, // MFTHI = 507	---
23642	CEFBS_HasMT, // MFTLO = 508	---	23642	CEFBS_HasMT, // MFTLO = 508	---
23643	CEFBS_None, // MIPSeh_return32 = 509	---	23643	CEFBS_None, // MIPSeh_return32 = 509	---
23644	CEFBS_None, // MIPSeh_return64 = 510	---	23644	CEFBS_None, // MIPSeh_return64 = 510	---
23645	CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 511	---	23645	CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 511	---
23646	CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 512	---	23646	CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 512	---
23647	CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 513	---	23647	CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 513	---
23648	CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 514	---	23648	CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 514	---
23649	CEFBS_HasMT, // MTTACX = 515	---	23649	CEFBS_HasMT, // MTTACX = 515	---
23650	CEFBS_HasMT, // MTTC0 = 516	---	23650	CEFBS_HasMT, // MTTC0 = 516	---
23651	CEFBS_HasMT, // MTTC1 = 517	---	23651	CEFBS_HasMT, // MTTC1 = 517	---
23652	CEFBS_HasMT, // MTTDSP = 518	---	23652	CEFBS_HasMT, // MTTDSP = 518	---
23653	CEFBS_HasMT, // MTTGPR = 519	---	23653	CEFBS_HasMT, // MTTGPR = 519	---
23654	CEFBS_HasMT, // MTTHC1 = 520	---	23654	CEFBS_HasMT, // MTTHC1 = 520	---
23655	CEFBS_HasMT, // MTTHI = 521	---	23655	CEFBS_HasMT, // MTTHI = 521	---
23656	CEFBS_HasMT, // MTTLO = 522	---	23656	CEFBS_HasMT, // MTTLO = 522	---
23657	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 523	---	23657	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 523	---
23658	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 524	---	23658	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 524	---
23659	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 525	---	23659	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 525	---
23660	CEFBS_InMips16Mode, // MultRxRy16 = 526	---	23660	CEFBS_InMips16Mode, // MultRxRy16 = 526	---
23661	CEFBS_InMips16Mode, // MultRxRyRz16 = 527	---	23661	CEFBS_InMips16Mode, // MultRxRyRz16 = 527	---
23662	CEFBS_InMips16Mode, // MultuRxRy16 = 528	---	23662	CEFBS_InMips16Mode, // MultuRxRy16 = 528	---
23663	CEFBS_InMips16Mode, // MultuRxRyRz16 = 529	---	23663	CEFBS_InMips16Mode, // MultuRxRyRz16 = 529	---
23664	CEFBS_HasStdEnc_NotInMicroMips, // NOP = 530	---	23664	CEFBS_HasStdEnc_NotInMicroMips, // NOP = 530	---
23665	CEFBS_IsGP32bit, // NORImm = 531	---	23665	CEFBS_IsGP32bit, // NORImm = 531	---
23666	CEFBS_IsGP64bit, // NORImm64 = 532	---	23666	CEFBS_IsGP64bit, // NORImm64 = 532	---
23667	CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 533	---	23667	CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 533	---
23668	CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 534	---	23668	CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 534	---
23669	CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 535	---	23669	CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 535	---
23670	CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 536	---	23670	CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 536	---
23671	CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 537	---	23671	CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 537	---
23672	CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 538	---	23672	CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 538	---
23673	CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 539	---	23673	CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 539	---
23674	CEFBS_HasDSP, // PseudoCMPU_LE_QB = 540	---	23674	CEFBS_HasDSP, // PseudoCMPU_LE_QB = 540	---
23675	CEFBS_HasDSP, // PseudoCMPU_LT_QB = 541	---	23675	CEFBS_HasDSP, // PseudoCMPU_LT_QB = 541	---
23676	CEFBS_HasDSP, // PseudoCMP_EQ_PH = 542	---	23676	CEFBS_HasDSP, // PseudoCMP_EQ_PH = 542	---
23677	CEFBS_HasDSP, // PseudoCMP_LE_PH = 543	---	23677	CEFBS_HasDSP, // PseudoCMP_LE_PH = 543	---
23678	CEFBS_HasDSP, // PseudoCMP_LT_PH = 544	---	23678	CEFBS_HasDSP, // PseudoCMP_LT_PH = 544	---
23679	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 545	---	23679	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 545	---
23680	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 546	---	23680	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 546	---
23681	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 547	---	23681	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 547	---
23682	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 548	---	23682	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 548	---
23683	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 549	---	23683	CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 549	---
23684	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 550	---	23684	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 550	---
23685	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 551	---	23685	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 551	---
23686	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 552	---	23686	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 552	---
23687	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 553	---	23687	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 553	---
23688	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 554	---	23688	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 554	---
23689	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 555	---	23689	CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 555	---
23690	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 556	---	23690	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 556	---
23691	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 557	---	23691	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 557	---
23692	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 558	---	23692	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 558	---
23693	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 559	---	23693	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 559	---
23694	CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 560	---	23694	CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 560	---
23695	CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 561	---	23695	CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 561	---
23696	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 562	---	23696	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 562	---
23697	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 563	---	23697	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 563	---
23698	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 564	---	23698	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 564	---
23699	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 565	---	23699	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 565	---
23700	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 566	---	23700	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 566	---
23701	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 567	---	23701	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 567	---
23702	CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 568	---	23702	CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 568	---
23703	CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 569	---	23703	CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 569	---
23704	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 570	---	23704	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 570	---
23705	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 571	---	23705	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 571	---
23706	CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 572	---	23706	CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 572	---
23707	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 573	---	23707	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 573	---
23708	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 574	---	23708	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 574	---
23709	CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 575	---	23709	CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 575	---
23710	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 576	---	23710	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 576	---
23711	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 577	---	23711	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 577	---
23712	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 578	---	23712	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 578	---
23713	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 579	---	23713	CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 579	---
23714	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 580	---	23714	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 580	---
23715	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 581	---	23715	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 581	---
23716	CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 582	---	23716	CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 582	---
23717	CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 583	---	23717	CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 583	---
23718	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 584	---	23718	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 584	---
23719	CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 585	---	23719	CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 585	---
23720	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 586	---	23720	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 586	---
23721	CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 587	---	23721	CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 587	---
23722	CEFBS_HasDSP, // PseudoPICK_PH = 588	---	23722	CEFBS_HasDSP, // PseudoPICK_PH = 588	---
23723	CEFBS_HasDSP, // PseudoPICK_QB = 589	---	23723	CEFBS_HasDSP, // PseudoPICK_QB = 589	---
23724	CEFBS_None, // PseudoReturn = 590	---	23724	CEFBS_None, // PseudoReturn = 590	---
23725	CEFBS_IsGP64bit, // PseudoReturn64 = 591	---	23725	CEFBS_IsGP64bit, // PseudoReturn64 = 591	---
23726	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 592	---	23726	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 592	---
23727	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 593	---	23727	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 593	---
23728	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 594	---	23728	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 594	---
23729	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 595	---	23729	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 595	---
23730	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 596	---	23730	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 596	---
23731	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 597	---	23731	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 597	---
23732	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 598	---	23732	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 598	---
23733	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 599	---	23733	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 599	---
23734	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 600	---	23734	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 600	---
23735	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 601	---	23735	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 601	---
23736	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 602	---	23736	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 602	---
23737	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 603	---	23737	CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 603	---
23738	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 604	---	23738	CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 604	---
23739	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 605	---	23739	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 605	---
23740	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 606	---	23740	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 606	---
23741	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 607	---	23741	CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 607	---
23742	CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 608	---	23742	CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 608	---
23743	CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 609	---	23743	CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 609	---
23744	CEFBS_None, // PseudoTRUNC_W_S = 610	---	23744	CEFBS_None, // PseudoTRUNC_W_S = 610	---
23745	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 611	---	23745	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 611	---
23746	CEFBS_None, // ROL = 612	---	23746	CEFBS_None, // ROL = 612	---
23747	CEFBS_None, // ROLImm = 613	---	23747	CEFBS_None, // ROLImm = 613	---
23748	CEFBS_None, // ROR = 614	---	23748	CEFBS_None, // ROR = 614	---
23749	CEFBS_None, // RORImm = 615	---	23749	CEFBS_None, // RORImm = 615	---
23750	CEFBS_NotInMips16Mode, // RetRA = 616	---	23750	CEFBS_NotInMips16Mode, // RetRA = 616	---
23751	CEFBS_InMips16Mode, // RetRA16 = 617	---	23751	CEFBS_InMips16Mode, // RetRA16 = 617	---
23752	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 618	---	23752	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 618	---
23753	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 619	---	23753	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 619	---
23754	CEFBS_HasStdEnc_NotMips3, // SDMacro = 620	---	23754	CEFBS_HasStdEnc_NotMips3, // SDMacro = 620	---
23755	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 621	---	23755	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 621	---
23756	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 622	---	23756	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 622	---
23757	CEFBS_NotCnMips, // SEQIMacro = 623	---	23757	CEFBS_NotCnMips, // SEQIMacro = 623	---
23758	CEFBS_NotCnMips, // SEQMacro = 624	---	23758	CEFBS_NotCnMips, // SEQMacro = 624	---
23759	CEFBS_HasStdEnc_NotInMicroMips, // SGE = 625	---	23759	CEFBS_HasStdEnc_NotInMicroMips, // SGE = 625	---
23760	CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 626	---	23760	CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 626	---
23761	CEFBS_IsGP64bit, // SGEImm64 = 627	---	23761	CEFBS_IsGP64bit, // SGEImm64 = 627	---
23762	CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 628	---	23762	CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 628	---
23763	CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 629	---	23763	CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 629	---
23764	CEFBS_IsGP64bit, // SGEUImm64 = 630	---	23764	CEFBS_IsGP64bit, // SGEUImm64 = 630	---
23765	CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 631	---	23765	CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 631	---
23766	CEFBS_IsGP64bit, // SGTImm64 = 632	---	23766	CEFBS_IsGP64bit, // SGTImm64 = 632	---
23767	CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 633	---	23767	CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 633	---
23768	CEFBS_IsGP64bit, // SGTUImm64 = 634	---	23768	CEFBS_IsGP64bit, // SGTUImm64 = 634	---
23769	CEFBS_HasStdEnc_NotInMicroMips, // SLE = 635	---	23769	CEFBS_HasStdEnc_NotInMicroMips, // SLE = 635	---
23770	CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 636	---	23770	CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 636	---
23771	CEFBS_IsGP64bit, // SLEImm64 = 637	---	23771	CEFBS_IsGP64bit, // SLEImm64 = 637	---
23772	CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 638	---	23772	CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 638	---
23773	CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 639	---	23773	CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 639	---
23774	CEFBS_IsGP64bit, // SLEUImm64 = 640	---	23774	CEFBS_IsGP64bit, // SLEUImm64 = 640	---
23775	CEFBS_IsGP64bit, // SLTImm64 = 641	---	23775	CEFBS_IsGP64bit, // SLTImm64 = 641	---
23776	CEFBS_IsGP64bit, // SLTUImm64 = 642	---	23776	CEFBS_IsGP64bit, // SLTUImm64 = 642	---
23777	CEFBS_NotCnMips, // SNEIMacro = 643	---	23777	CEFBS_NotCnMips, // SNEIMacro = 643	---
23778	CEFBS_NotCnMips, // SNEMacro = 644	---	23778	CEFBS_NotCnMips, // SNEMacro = 644	---
23779	CEFBS_None, // SNZ_B_PSEUDO = 645	---	23779	CEFBS_None, // SNZ_B_PSEUDO = 645	---
23780	CEFBS_None, // SNZ_D_PSEUDO = 646	---	23780	CEFBS_None, // SNZ_D_PSEUDO = 646	---
23781	CEFBS_None, // SNZ_H_PSEUDO = 647	---	23781	CEFBS_None, // SNZ_H_PSEUDO = 647	---
23782	CEFBS_None, // SNZ_V_PSEUDO = 648	---	23782	CEFBS_None, // SNZ_V_PSEUDO = 648	---
23783	CEFBS_None, // SNZ_W_PSEUDO = 649	---	23783	CEFBS_None, // SNZ_W_PSEUDO = 649	---
23784	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 650	---	23784	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 650	---
23785	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 651	---	23785	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 651	---
23786	CEFBS_NotInMips16Mode, // STORE_ACC128 = 652	---	23786	CEFBS_NotInMips16Mode, // STORE_ACC128 = 652	---
23787	CEFBS_NotInMips16Mode, // STORE_ACC64 = 653	---	23787	CEFBS_NotInMips16Mode, // STORE_ACC64 = 653	---
23788	CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 654	---	23788	CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 654	---
23789	CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 655	---	23789	CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 655	---
23790	CEFBS_NotInMips16Mode, // STR_D = 656	---	23790	CEFBS_NotInMips16Mode, // STR_D = 656	---
23791	CEFBS_NotInMips16Mode, // STR_W = 657	---	23791	CEFBS_NotInMips16Mode, // STR_W = 657	---
23792	CEFBS_HasMSA, // ST_F16 = 658	---	23792	CEFBS_HasMSA, // ST_F16 = 658	---
23793	CEFBS_InMicroMips, // SWM_MM = 659	---	23793	CEFBS_InMicroMips, // SWM_MM = 659	---
23794	CEFBS_None, // SZ_B_PSEUDO = 660	---	23794	CEFBS_None, // SZ_B_PSEUDO = 660	---
23795	CEFBS_None, // SZ_D_PSEUDO = 661	---	23795	CEFBS_None, // SZ_D_PSEUDO = 661	---
23796	CEFBS_None, // SZ_H_PSEUDO = 662	---	23796	CEFBS_None, // SZ_H_PSEUDO = 662	---
23797	CEFBS_None, // SZ_V_PSEUDO = 663	---	23797	CEFBS_None, // SZ_V_PSEUDO = 663	---
23798	CEFBS_None, // SZ_W_PSEUDO = 664	---	23798	CEFBS_None, // SZ_W_PSEUDO = 664	---
23799	CEFBS_HasCnMipsP, // SaaAddr = 665	---	23799	CEFBS_HasCnMipsP, // SaaAddr = 665	---
23800	CEFBS_HasCnMipsP, // SaadAddr = 666	---	23800	CEFBS_HasCnMipsP, // SaadAddr = 666	---
23801	CEFBS_InMips16Mode, // SelBeqZ = 667	---	23801	CEFBS_InMips16Mode, // SelBeqZ = 667	---
23802	CEFBS_InMips16Mode, // SelBneZ = 668	---	23802	CEFBS_InMips16Mode, // SelBneZ = 668	---
23803	CEFBS_InMips16Mode, // SelTBteqZCmp = 669	---	23803	CEFBS_InMips16Mode, // SelTBteqZCmp = 669	---
23804	CEFBS_InMips16Mode, // SelTBteqZCmpi = 670	---	23804	CEFBS_InMips16Mode, // SelTBteqZCmpi = 670	---
23805	CEFBS_InMips16Mode, // SelTBteqZSlt = 671	---	23805	CEFBS_InMips16Mode, // SelTBteqZSlt = 671	---
23806	CEFBS_InMips16Mode, // SelTBteqZSlti = 672	---	23806	CEFBS_InMips16Mode, // SelTBteqZSlti = 672	---
23807	CEFBS_InMips16Mode, // SelTBteqZSltiu = 673	---	23807	CEFBS_InMips16Mode, // SelTBteqZSltiu = 673	---
23808	CEFBS_InMips16Mode, // SelTBteqZSltu = 674	---	23808	CEFBS_InMips16Mode, // SelTBteqZSltu = 674	---
23809	CEFBS_InMips16Mode, // SelTBtneZCmp = 675	---	23809	CEFBS_InMips16Mode, // SelTBtneZCmp = 675	---
23810	CEFBS_InMips16Mode, // SelTBtneZCmpi = 676	---	23810	CEFBS_InMips16Mode, // SelTBtneZCmpi = 676	---
23811	CEFBS_InMips16Mode, // SelTBtneZSlt = 677	---	23811	CEFBS_InMips16Mode, // SelTBtneZSlt = 677	---
23812	CEFBS_InMips16Mode, // SelTBtneZSlti = 678	---	23812	CEFBS_InMips16Mode, // SelTBtneZSlti = 678	---
23813	CEFBS_InMips16Mode, // SelTBtneZSltiu = 679	---	23813	CEFBS_InMips16Mode, // SelTBtneZSltiu = 679	---
23814	CEFBS_InMips16Mode, // SelTBtneZSltu = 680	---	23814	CEFBS_InMips16Mode, // SelTBtneZSltu = 680	---
23815	CEFBS_InMips16Mode, // SltCCRxRy16 = 681	---	23815	CEFBS_InMips16Mode, // SltCCRxRy16 = 681	---
23816	CEFBS_InMips16Mode, // SltiCCRxImmX16 = 682	---	23816	CEFBS_InMips16Mode, // SltiCCRxImmX16 = 682	---
23817	CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 683	---	23817	CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 683	---
23818	CEFBS_InMips16Mode, // SltuCCRxRy16 = 684	---	23818	CEFBS_InMips16Mode, // SltuCCRxRy16 = 684	---
23819	CEFBS_InMips16Mode, // SltuRxRyRz16 = 685	---	23819	CEFBS_InMips16Mode, // SltuRxRyRz16 = 685	---
23820	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 686	---	23820	CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 686	---
23821	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 687	---	23821	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 687	---
23822	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 688	---	23822	CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 688	---
23823	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 689	---	23823	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 689	---
23824	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 690	---	23824	CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 690	---
23825	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 691	---	23825	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 691	---
23826	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 692	---	23826	CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 692	---
23827	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 693	---	23827	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 693	---
23828	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 694	---	23828	CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 694	---
23829	CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 695	---	23829	CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 695	---
23830	CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 696	---	23830	CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 696	---
23831	CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 697	---	23831	CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 697	---
23832	CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 698	---	23832	CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 698	---
23833	CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 699	---	23833	CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 699	---
23834	CEFBS_InMicroMips, // TRAP_MM = 700	---	23834	CEFBS_InMicroMips, // TRAP_MM = 700	---
23835	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 701	---	23835	CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 701	---
23836	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 702	---	23836	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 702	---
23837	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 703	---	23837	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 703	---
23838	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 704	---	23838	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 704	---
23839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 705	---	23839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 705	---
23840	CEFBS_None, // Ulh = 706	---	23840	CEFBS_None, // Ulh = 706	---
23841	CEFBS_None, // Ulhu = 707	---	23841	CEFBS_None, // Ulhu = 707	---
23842	CEFBS_None, // Ulw = 708	---	23842	CEFBS_None, // Ulw = 708	---
23843	CEFBS_None, // Ush = 709	---	23843	CEFBS_None, // Ush = 709	---
23844	CEFBS_None, // Usw = 710	---	23844	CEFBS_None, // Usw = 710	---
23845	CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 711	---	23845	CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 711	---
23846	CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 712	---	23846	CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 712	---
23847	CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 713	---	23847	CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 713	---
23848	CEFBS_HasDSP, // ABSQ_S_PH = 714	---	23848	CEFBS_HasDSP, // ABSQ_S_PH = 714	---
23849	CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 715	---	23849	CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 715	---
23850	CEFBS_HasDSPR2, // ABSQ_S_QB = 716	---	23850	CEFBS_HasDSPR2, // ABSQ_S_QB = 716	---
23851	CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 717	---	23851	CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 717	---
23852	CEFBS_HasDSP, // ABSQ_S_W = 718	---	23852	CEFBS_HasDSP, // ABSQ_S_W = 718	---
23853	CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 719	---	23853	CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 719	---
23854	CEFBS_HasStdEnc_NotInMicroMips, // ADD = 720	---	23854	CEFBS_HasStdEnc_NotInMicroMips, // ADD = 720	---
23855	CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 721	---	23855	CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 721	---
23856	CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 722	---	23856	CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 722	---
23857	CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 723	---	23857	CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 723	---
23858	CEFBS_InMicroMips, // ADDIUR1SP_MM = 724	---	23858	CEFBS_InMicroMips, // ADDIUR1SP_MM = 724	---
23859	CEFBS_InMicroMips, // ADDIUR2_MM = 725	---	23859	CEFBS_InMicroMips, // ADDIUR2_MM = 725	---
23860	CEFBS_InMicroMips, // ADDIUS5_MM = 726	---	23860	CEFBS_InMicroMips, // ADDIUS5_MM = 726	---
23861	CEFBS_InMicroMips, // ADDIUSP_MM = 727	---	23861	CEFBS_InMicroMips, // ADDIUSP_MM = 727	---
23862	CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 728	---	23862	CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 728	---
23863	CEFBS_HasDSPR2, // ADDQH_PH = 729	---	23863	CEFBS_HasDSPR2, // ADDQH_PH = 729	---
23864	CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 730	---	23864	CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 730	---
23865	CEFBS_HasDSPR2, // ADDQH_R_PH = 731	---	23865	CEFBS_HasDSPR2, // ADDQH_R_PH = 731	---
23866	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 732	---	23866	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 732	---
23867	CEFBS_HasDSPR2, // ADDQH_R_W = 733	---	23867	CEFBS_HasDSPR2, // ADDQH_R_W = 733	---
23868	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 734	---	23868	CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 734	---
23869	CEFBS_HasDSPR2, // ADDQH_W = 735	---	23869	CEFBS_HasDSPR2, // ADDQH_W = 735	---
23870	CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 736	---	23870	CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 736	---
23871	CEFBS_HasDSP, // ADDQ_PH = 737	---	23871	CEFBS_HasDSP, // ADDQ_PH = 737	---
23872	CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 738	---	23872	CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 738	---
23873	CEFBS_HasDSP, // ADDQ_S_PH = 739	---	23873	CEFBS_HasDSP, // ADDQ_S_PH = 739	---
23874	CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 740	---	23874	CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 740	---
23875	CEFBS_HasDSP, // ADDQ_S_W = 741	---	23875	CEFBS_HasDSP, // ADDQ_S_W = 741	---
23876	CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 742	---	23876	CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 742	---
23877	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 743	---	23877	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 743	---
23878	CEFBS_HasDSP, // ADDSC = 744	---	23878	CEFBS_HasDSP, // ADDSC = 744	---
23879	CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 745	---	23879	CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 745	---
23880	CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 746	---	23880	CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 746	---
23881	CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 747	---	23881	CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 747	---
23882	CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 748	---	23882	CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 748	---
23883	CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 749	---	23883	CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 749	---
23884	CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 750	---	23884	CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 750	---
23885	CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 751	---	23885	CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 751	---
23886	CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 752	---	23886	CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 752	---
23887	CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 753	---	23887	CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 753	---
23888	CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 754	---	23888	CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 754	---
23889	CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 755	---	23889	CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 755	---
23890	CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 756	---	23890	CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 756	---
23891	CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 757	---	23891	CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 757	---
23892	CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 758	---	23892	CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 758	---
23893	CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 759	---	23893	CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 759	---
23894	CEFBS_HasDSPR2, // ADDUH_QB = 760	---	23894	CEFBS_HasDSPR2, // ADDUH_QB = 760	---
23895	CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 761	---	23895	CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 761	---
23896	CEFBS_HasDSPR2, // ADDUH_R_QB = 762	---	23896	CEFBS_HasDSPR2, // ADDUH_R_QB = 762	---
23897	CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 763	---	23897	CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 763	---
23898	CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 764	---	23898	CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 764	---
23899	CEFBS_HasDSPR2, // ADDU_PH = 765	---	23899	CEFBS_HasDSPR2, // ADDU_PH = 765	---
23900	CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 766	---	23900	CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 766	---
23901	CEFBS_HasDSP, // ADDU_QB = 767	---	23901	CEFBS_HasDSP, // ADDU_QB = 767	---
23902	CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 768	---	23902	CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 768	---
23903	CEFBS_HasDSPR2, // ADDU_S_PH = 769	---	23903	CEFBS_HasDSPR2, // ADDU_S_PH = 769	---
23904	CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 770	---	23904	CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 770	---
23905	CEFBS_HasDSP, // ADDU_S_QB = 771	---	23905	CEFBS_HasDSP, // ADDU_S_QB = 771	---
23906	CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 772	---	23906	CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 772	---
23907	CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 773	---	23907	CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 773	---
23908	CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 774	---	23908	CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 774	---
23909	CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 775	---	23909	CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 775	---
23910	CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 776	---	23910	CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 776	---
23911	CEFBS_HasStdEnc_HasMSA, // ADDV_B = 777	---	23911	CEFBS_HasStdEnc_HasMSA, // ADDV_B = 777	---
23912	CEFBS_HasStdEnc_HasMSA, // ADDV_D = 778	---	23912	CEFBS_HasStdEnc_HasMSA, // ADDV_D = 778	---
23913	CEFBS_HasStdEnc_HasMSA, // ADDV_H = 779	---	23913	CEFBS_HasStdEnc_HasMSA, // ADDV_H = 779	---
23914	CEFBS_HasStdEnc_HasMSA, // ADDV_W = 780	---	23914	CEFBS_HasStdEnc_HasMSA, // ADDV_W = 780	---
23915	CEFBS_HasDSP, // ADDWC = 781	---	23915	CEFBS_HasDSP, // ADDWC = 781	---
23916	CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 782	---	23916	CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 782	---
23917	CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 783	---	23917	CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 783	---
23918	CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 784	---	23918	CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 784	---
23919	CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 785	---	23919	CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 785	---
23920	CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 786	---	23920	CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 786	---
23921	CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 787	---	23921	CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 787	---
23922	CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 788	---	23922	CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 788	---
23923	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 789	---	23923	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 789	---
23924	CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 790	---	23924	CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 790	---
23925	CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 791	---	23925	CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 791	---
23926	CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 792	---	23926	CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 792	---
23927	CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 793	---	23927	CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 793	---
23928	CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 794	---	23928	CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 794	---
23929	CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 795	---	23929	CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 795	---
23930	CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 796	---	23930	CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 796	---
23931	CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 797	---	23931	CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 797	---
23932	CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 798	---	23932	CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 798	---
23933	CEFBS_HasStdEnc_NotInMicroMips, // AND = 799	---	23933	CEFBS_HasStdEnc_NotInMicroMips, // AND = 799	---
23934	CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 800	---	23934	CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 800	---
23935	CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 801	---	23935	CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 801	---
23936	CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 802	---	23936	CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 802	---
23937	CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 803	---	23937	CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 803	---
23938	CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 804	---	23938	CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 804	---
23939	CEFBS_HasStdEnc_HasMSA, // ANDI_B = 805	---	23939	CEFBS_HasStdEnc_HasMSA, // ANDI_B = 805	---
23940	CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 806	---	23940	CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 806	---
23941	CEFBS_InMicroMips_NotMips32r6, // AND_MM = 807	---	23941	CEFBS_InMicroMips_NotMips32r6, // AND_MM = 807	---
23942	CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 808	---	23942	CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 808	---
23943	CEFBS_HasStdEnc_HasMSA, // AND_V = 809	---	23943	CEFBS_HasStdEnc_HasMSA, // AND_V = 809	---
23944	CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 810	---	23944	CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 810	---
23945	CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 811	---	23945	CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 811	---
23946	CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 812	---	23946	CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 812	---
23947	CEFBS_HasDSPR2, // APPEND = 813	---	23947	CEFBS_HasDSPR2, // APPEND = 813	---
23948	CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 814	---	23948	CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 814	---
23949	CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 815	---	23949	CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 815	---
23950	CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 816	---	23950	CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 816	---
23951	CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 817	---	23951	CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 817	---
23952	CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 818	---	23952	CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 818	---
23953	CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 819	---	23953	CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 819	---
23954	CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 820	---	23954	CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 820	---
23955	CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 821	---	23955	CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 821	---
23956	CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 822	---	23956	CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 822	---
23957	CEFBS_HasStdEnc_HasMips32r6, // AUI = 823	---	23957	CEFBS_HasStdEnc_HasMips32r6, // AUI = 823	---
23958	CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 824	---	23958	CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 824	---
23959	CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 825	---	23959	CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 825	---
23960	CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 826	---	23960	CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 826	---
23961	CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 827	---	23961	CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 827	---
23962	CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 828	---	23962	CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 828	---
23963	CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 829	---	23963	CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 829	---
23964	CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 830	---	23964	CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 830	---
23965	CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 831	---	23965	CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 831	---
23966	CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 832	---	23966	CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 832	---
23967	CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 833	---	23967	CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 833	---
23968	CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 834	---	23968	CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 834	---
23969	CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 835	---	23969	CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 835	---
23970	CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 836	---	23970	CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 836	---
23971	CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 837	---	23971	CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 837	---
23972	CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 838	---	23972	CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 838	---
23973	CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 839	---	23973	CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 839	---
23974	CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 840	---	23974	CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 840	---
23975	CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 841	---	23975	CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 841	---
23976	CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 842	---	23976	CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 842	---
23977	CEFBS_InMips16Mode, // AddiuRxImmX16 = 843	---	23977	CEFBS_InMips16Mode, // AddiuRxImmX16 = 843	---
23978	CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 844	---	23978	CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 844	---
23979	CEFBS_InMips16Mode, // AddiuRxRxImm16 = 845	---	23979	CEFBS_InMips16Mode, // AddiuRxRxImm16 = 845	---
23980	CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 846	---	23980	CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 846	---
23981	CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 847	---	23981	CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 847	---
23982	CEFBS_InMips16Mode, // AddiuSpImm16 = 848	---	23982	CEFBS_InMips16Mode, // AddiuSpImm16 = 848	---
23983	CEFBS_InMips16Mode, // AddiuSpImmX16 = 849	---	23983	CEFBS_InMips16Mode, // AddiuSpImmX16 = 849	---
23984	CEFBS_InMips16Mode, // AdduRxRyRz16 = 850	---	23984	CEFBS_InMips16Mode, // AdduRxRyRz16 = 850	---
23985	CEFBS_InMips16Mode, // AndRxRxRy16 = 851	---	23985	CEFBS_InMips16Mode, // AndRxRxRy16 = 851	---
23986	CEFBS_InMicroMips, // B16_MM = 852	---	23986	CEFBS_InMicroMips, // B16_MM = 852	---
23987	CEFBS_HasCnMips, // BADDu = 853	---	23987	CEFBS_HasCnMips, // BADDu = 853	---
23988	CEFBS_HasStdEnc_HasMips32r6, // BAL = 854	---	23988	CEFBS_HasStdEnc_HasMips32r6, // BAL = 854	---
23989	CEFBS_HasStdEnc_HasMips32r6, // BALC = 855	---	23989	CEFBS_HasStdEnc_HasMips32r6, // BALC = 855	---
23990	CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 856	---	23990	CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 856	---
23991	CEFBS_HasDSPR2, // BALIGN = 857	---	23991	CEFBS_HasDSPR2, // BALIGN = 857	---
23992	CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 858	---	23992	CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 858	---
23993	CEFBS_HasCnMips, // BBIT0 = 859	---	23993	CEFBS_HasCnMips, // BBIT0 = 859	---
23994	CEFBS_HasCnMips, // BBIT032 = 860	---	23994	CEFBS_HasCnMips, // BBIT032 = 860	---
23995	CEFBS_HasCnMips, // BBIT1 = 861	---	23995	CEFBS_HasCnMips, // BBIT1 = 861	---
23996	CEFBS_HasCnMips, // BBIT132 = 862	---	23996	CEFBS_HasCnMips, // BBIT132 = 862	---
23997	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 863	---	23997	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 863	---
23998	CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 864	---	23998	CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 864	---
23999	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 865	---	23999	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 865	---
24000	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 866	---	24000	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 866	---
24001	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 867	---	24001	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 867	---
24002	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 868	---	24002	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 868	---
24003	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 869	---	24003	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 869	---
24004	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 870	---	24004	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 870	---
24005	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 871	---	24005	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 871	---
24006	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 872	---	24006	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 872	---
24007	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 873	---	24007	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 873	---
24008	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 874	---	24008	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 874	---
24009	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 875	---	24009	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 875	---
24010	CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 876	---	24010	CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 876	---
24011	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 877	---	24011	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 877	---
24012	CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 878	---	24012	CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 878	---
24013	CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 879	---	24013	CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 879	---
24014	CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 880	---	24014	CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 880	---
24015	CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 881	---	24015	CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 881	---
24016	CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 882	---	24016	CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 882	---
24017	CEFBS_HasStdEnc_HasMSA, // BCLR_B = 883	---	24017	CEFBS_HasStdEnc_HasMSA, // BCLR_B = 883	---
24018	CEFBS_HasStdEnc_HasMSA, // BCLR_D = 884	---	24018	CEFBS_HasStdEnc_HasMSA, // BCLR_D = 884	---
24019	CEFBS_HasStdEnc_HasMSA, // BCLR_H = 885	---	24019	CEFBS_HasStdEnc_HasMSA, // BCLR_H = 885	---
24020	CEFBS_HasStdEnc_HasMSA, // BCLR_W = 886	---	24020	CEFBS_HasStdEnc_HasMSA, // BCLR_W = 886	---
24021	CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 887	---	24021	CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 887	---
24022	CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 888	---	24022	CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 888	---
24023	CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 889	---	24023	CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 889	---
24024	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 890	---	24024	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 890	---
24025	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 891	---	24025	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 891	---
24026	CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 892	---	24026	CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 892	---
24027	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 893	---	24027	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 893	---
24028	CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 894	---	24028	CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 894	---
24029	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 895	---	24029	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 895	---
24030	CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 896	---	24030	CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 896	---
24031	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 897	---	24031	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 897	---
24032	CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 898	---	24032	CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 898	---
24033	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 899	---	24033	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 899	---
24034	CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 900	---	24034	CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 900	---
24035	CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 901	---	24035	CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 901	---
24036	CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 902	---	24036	CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 902	---
24037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 903	---	24037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 903	---
24038	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 904	---	24038	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 904	---
24039	CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 905	---	24039	CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 905	---
24040	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 906	---	24040	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 906	---
24041	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 907	---	24041	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 907	---
24042	CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 908	---	24042	CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 908	---
24043	CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 909	---	24043	CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 909	---
24044	CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 910	---	24044	CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 910	---
24045	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 911	---	24045	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 911	---
24046	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 912	---	24046	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 912	---
24047	CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 913	---	24047	CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 913	---
24048	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 914	---	24048	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 914	---
24049	CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 915	---	24049	CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 915	---
24050	CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 916	---	24050	CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 916	---
24051	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 917	---	24051	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 917	---
24052	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 918	---	24052	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 918	---
24053	CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 919	---	24053	CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 919	---
24054	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 920	---	24054	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 920	---
24055	CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 921	---	24055	CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 921	---
24056	CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 922	---	24056	CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 922	---
24057	CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 923	---	24057	CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 923	---
24058	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 924	---	24058	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 924	---
24059	CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 925	---	24059	CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 925	---
24060	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 926	---	24060	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 926	---
24061	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 927	---	24061	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 927	---
24062	CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 928	---	24062	CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 928	---
24063	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 929	---	24063	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 929	---
24064	CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 930	---	24064	CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 930	---
24065	CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 931	---	24065	CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 931	---
24066	CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 932	---	24066	CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 932	---
24067	CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 933	---	24067	CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 933	---
24068	CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 934	---	24068	CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 934	---
24069	CEFBS_HasStdEnc_HasMSA, // BINSL_B = 935	---	24069	CEFBS_HasStdEnc_HasMSA, // BINSL_B = 935	---
24070	CEFBS_HasStdEnc_HasMSA, // BINSL_D = 936	---	24070	CEFBS_HasStdEnc_HasMSA, // BINSL_D = 936	---
24071	CEFBS_HasStdEnc_HasMSA, // BINSL_H = 937	---	24071	CEFBS_HasStdEnc_HasMSA, // BINSL_H = 937	---
24072	CEFBS_HasStdEnc_HasMSA, // BINSL_W = 938	---	24072	CEFBS_HasStdEnc_HasMSA, // BINSL_W = 938	---
24073	CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 939	---	24073	CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 939	---
24074	CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 940	---	24074	CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 940	---
24075	CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 941	---	24075	CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 941	---
24076	CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 942	---	24076	CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 942	---
24077	CEFBS_HasStdEnc_HasMSA, // BINSR_B = 943	---	24077	CEFBS_HasStdEnc_HasMSA, // BINSR_B = 943	---
24078	CEFBS_HasStdEnc_HasMSA, // BINSR_D = 944	---	24078	CEFBS_HasStdEnc_HasMSA, // BINSR_D = 944	---
24079	CEFBS_HasStdEnc_HasMSA, // BINSR_H = 945	---	24079	CEFBS_HasStdEnc_HasMSA, // BINSR_H = 945	---
24080	CEFBS_HasStdEnc_HasMSA, // BINSR_W = 946	---	24080	CEFBS_HasStdEnc_HasMSA, // BINSR_W = 946	---
24081	CEFBS_HasDSP, // BITREV = 947	---	24081	CEFBS_HasDSP, // BITREV = 947	---
24082	CEFBS_InMicroMips_HasDSP, // BITREV_MM = 948	---	24082	CEFBS_InMicroMips_HasDSP, // BITREV_MM = 948	---
24083	CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 949	---	24083	CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 949	---
24084	CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 950	---	24084	CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 950	---
24085	CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 951	---	24085	CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 951	---
24086	CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 952	---	24086	CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 952	---
24087	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 953	---	24087	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 953	---
24088	CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 954	---	24088	CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 954	---
24089	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 955	---	24089	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 955	---
24090	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 956	---	24090	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 956	---
24091	CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 957	---	24091	CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 957	---
24092	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 958	---	24092	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 958	---
24093	CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 959	---	24093	CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 959	---
24094	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 960	---	24094	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 960	---
24095	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 961	---	24095	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 961	---
24096	CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 962	---	24096	CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 962	---
24097	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 963	---	24097	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 963	---
24098	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 964	---	24098	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 964	---
24099	CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 965	---	24099	CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 965	---
24100	CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 966	---	24100	CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 966	---
24101	CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 967	---	24101	CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 967	---
24102	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 968	---	24102	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 968	---
24103	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 969	---	24103	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 969	---
24104	CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 970	---	24104	CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 970	---
24105	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 971	---	24105	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 971	---
24106	CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 972	---	24106	CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 972	---
24107	CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 973	---	24107	CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 973	---
24108	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 974	---	24108	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 974	---
24109	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 975	---	24109	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 975	---
24110	CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 976	---	24110	CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 976	---
24111	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 977	---	24111	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 977	---
24112	CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 978	---	24112	CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 978	---
24113	CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 979	---	24113	CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 979	---
24114	CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 980	---	24114	CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 980	---
24115	CEFBS_HasStdEnc_HasMSA, // BMZI_B = 981	---	24115	CEFBS_HasStdEnc_HasMSA, // BMZI_B = 981	---
24116	CEFBS_HasStdEnc_HasMSA, // BMZ_V = 982	---	24116	CEFBS_HasStdEnc_HasMSA, // BMZ_V = 982	---
24117	CEFBS_HasStdEnc_NotInMicroMips, // BNE = 983	---	24117	CEFBS_HasStdEnc_NotInMicroMips, // BNE = 983	---
24118	CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 984	---	24118	CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 984	---
24119	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 985	---	24119	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 985	---
24120	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 986	---	24120	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 986	---
24121	CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 987	---	24121	CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 987	---
24122	CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 988	---	24122	CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 988	---
24123	CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 989	---	24123	CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 989	---
24124	CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 990	---	24124	CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 990	---
24125	CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 991	---	24125	CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 991	---
24126	CEFBS_HasStdEnc_HasMSA, // BNEG_B = 992	---	24126	CEFBS_HasStdEnc_HasMSA, // BNEG_B = 992	---
24127	CEFBS_HasStdEnc_HasMSA, // BNEG_D = 993	---	24127	CEFBS_HasStdEnc_HasMSA, // BNEG_D = 993	---
24128	CEFBS_HasStdEnc_HasMSA, // BNEG_H = 994	---	24128	CEFBS_HasStdEnc_HasMSA, // BNEG_H = 994	---
24129	CEFBS_HasStdEnc_HasMSA, // BNEG_W = 995	---	24129	CEFBS_HasStdEnc_HasMSA, // BNEG_W = 995	---
24130	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 996	---	24130	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 996	---
24131	CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 997	---	24131	CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 997	---
24132	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 998	---	24132	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 998	---
24133	CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 999	---	24133	CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 999	---
24134	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1000	---	24134	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1000	---
24135	CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1001	---	24135	CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1001	---
24136	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1002	---	24136	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1002	---
24137	CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1003	---	24137	CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1003	---
24138	CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1004	---	24138	CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1004	---
24139	CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1005	---	24139	CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1005	---
24140	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1006	---	24140	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1006	---
24141	CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1007	---	24141	CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1007	---
24142	CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1008	---	24142	CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1008	---
24143	CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1009	---	24143	CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1009	---
24144	CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1010	---	24144	CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1010	---
24145	CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1011	---	24145	CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1011	---
24146	CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1012	---	24146	CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1012	---
24147	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1013	---	24147	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1013	---
24148	CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1014	---	24148	CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1014	---
24149	CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1015	---	24149	CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1015	---
24150	CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1016	---	24150	CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1016	---
24151	CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1017	---	24151	CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1017	---
24152	CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1018	---	24152	CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1018	---
24153	CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1019	---	24153	CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1019	---
24154	CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1020	---	24154	CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1020	---
24155	CEFBS_InMicroMips, // BREAK_MM = 1021	---	24155	CEFBS_InMicroMips, // BREAK_MM = 1021	---
24156	CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1022	---	24156	CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1022	---
24157	CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1023	---	24157	CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1023	---
24158	CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1024	---	24158	CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1024	---
24159	CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1025	---	24159	CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1025	---
24160	CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1026	---	24160	CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1026	---
24161	CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1027	---	24161	CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1027	---
24162	CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1028	---	24162	CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1028	---
24163	CEFBS_HasStdEnc_HasMSA, // BSET_B = 1029	---	24163	CEFBS_HasStdEnc_HasMSA, // BSET_B = 1029	---
24164	CEFBS_HasStdEnc_HasMSA, // BSET_D = 1030	---	24164	CEFBS_HasStdEnc_HasMSA, // BSET_D = 1030	---
24165	CEFBS_HasStdEnc_HasMSA, // BSET_H = 1031	---	24165	CEFBS_HasStdEnc_HasMSA, // BSET_H = 1031	---
24166	CEFBS_HasStdEnc_HasMSA, // BSET_W = 1032	---	24166	CEFBS_HasStdEnc_HasMSA, // BSET_W = 1032	---
24167	CEFBS_HasStdEnc_HasMSA, // BZ_B = 1033	---	24167	CEFBS_HasStdEnc_HasMSA, // BZ_B = 1033	---
24168	CEFBS_HasStdEnc_HasMSA, // BZ_D = 1034	---	24168	CEFBS_HasStdEnc_HasMSA, // BZ_D = 1034	---
24169	CEFBS_HasStdEnc_HasMSA, // BZ_H = 1035	---	24169	CEFBS_HasStdEnc_HasMSA, // BZ_H = 1035	---
24170	CEFBS_HasStdEnc_HasMSA, // BZ_V = 1036	---	24170	CEFBS_HasStdEnc_HasMSA, // BZ_V = 1036	---
24171	CEFBS_HasStdEnc_HasMSA, // BZ_W = 1037	---	24171	CEFBS_HasStdEnc_HasMSA, // BZ_W = 1037	---
24172	CEFBS_InMips16Mode, // BeqzRxImm16 = 1038	---	24172	CEFBS_InMips16Mode, // BeqzRxImm16 = 1038	---
24173	CEFBS_InMips16Mode, // BeqzRxImmX16 = 1039	---	24173	CEFBS_InMips16Mode, // BeqzRxImmX16 = 1039	---
24174	CEFBS_InMips16Mode, // Bimm16 = 1040	---	24174	CEFBS_InMips16Mode, // Bimm16 = 1040	---
24175	CEFBS_InMips16Mode, // BimmX16 = 1041	---	24175	CEFBS_InMips16Mode, // BimmX16 = 1041	---
24176	CEFBS_InMips16Mode, // BnezRxImm16 = 1042	---	24176	CEFBS_InMips16Mode, // BnezRxImm16 = 1042	---
24177	CEFBS_InMips16Mode, // BnezRxImmX16 = 1043	---	24177	CEFBS_InMips16Mode, // BnezRxImmX16 = 1043	---
24178	CEFBS_InMips16Mode, // Break16 = 1044	---	24178	CEFBS_InMips16Mode, // Break16 = 1044	---
24179	CEFBS_InMips16Mode, // Bteqz16 = 1045	---	24179	CEFBS_InMips16Mode, // Bteqz16 = 1045	---
24180	CEFBS_InMips16Mode, // BteqzX16 = 1046	---	24180	CEFBS_InMips16Mode, // BteqzX16 = 1046	---
24181	CEFBS_InMips16Mode, // Btnez16 = 1047	---	24181	CEFBS_InMips16Mode, // Btnez16 = 1047	---
24182	CEFBS_InMips16Mode, // BtnezX16 = 1048	---	24182	CEFBS_InMips16Mode, // BtnezX16 = 1048	---
24183	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1049	---	24183	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1049	---
24184	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1050	---	24184	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1050	---
24185	CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1051	---	24185	CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1051	---
24186	CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1052	---	24186	CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1052	---
24187	CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1053	---	24187	CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1053	---
24188	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1054	---	24188	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1054	---
24189	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1055	---	24189	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1055	---
24190	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1056	---	24190	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1056	---
24191	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1057	---	24191	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1057	---
24192	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1058	---	24192	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1058	---
24193	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1059	---	24193	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1059	---
24194	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1060	---	24194	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1060	---
24195	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1061	---	24195	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1061	---
24196	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1062	---	24196	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1062	---
24197	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1063	---	24197	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1063	---
24198	CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1064	---	24198	CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1064	---
24199	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1065	---	24199	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1065	---
24200	CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1066	---	24200	CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1066	---
24201	CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1067	---	24201	CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1067	---
24202	CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1068	---	24202	CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1068	---
24203	CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1069	---	24203	CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1069	---
24204	CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1070	---	24204	CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1070	---
24205	CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1071	---	24205	CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1071	---
24206	CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1072	---	24206	CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1072	---
24207	CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1073	---	24207	CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1073	---
24208	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1074	---	24208	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1074	---
24209	CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1075	---	24209	CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1075	---
24210	CEFBS_InMicroMips, // CFC2_MM = 1076	---	24210	CEFBS_InMicroMips, // CFC2_MM = 1076	---
24211	CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1077	---	24211	CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1077	---
24212	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1078	---	24212	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1078	---
24213	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1079	---	24213	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1079	---
24214	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1080	---	24214	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1080	---
24215	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1081	---	24215	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1081	---
24216	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1082	---	24216	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1082	---
24217	CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1083	---	24217	CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1083	---
24218	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1084	---	24218	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1084	---
24219	CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1085	---	24219	CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1085	---
24220	CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1086	---	24220	CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1086	---
24221	CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1087	---	24221	CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1087	---
24222	CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1088	---	24222	CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1088	---
24223	CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1089	---	24223	CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1089	---
24224	CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1090	---	24224	CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1090	---
24225	CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1091	---	24225	CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1091	---
24226	CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1092	---	24226	CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1092	---
24227	CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1093	---	24227	CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1093	---
24228	CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1094	---	24228	CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1094	---
24229	CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1095	---	24229	CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1095	---
24230	CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1096	---	24230	CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1096	---
24231	CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1097	---	24231	CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1097	---
24232	CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1098	---	24232	CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1098	---
24233	CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1099	---	24233	CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1099	---
24234	CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1100	---	24234	CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1100	---
24235	CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1101	---	24235	CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1101	---
24236	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1102	---	24236	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1102	---
24237	CEFBS_InMicroMips, // CLO_MM = 1103	---	24237	CEFBS_InMicroMips, // CLO_MM = 1103	---
24238	CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1104	---	24238	CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1104	---
24239	CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1105	---	24239	CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1105	---
24240	CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1106	---	24240	CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1106	---
24241	CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1107	---	24241	CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1107	---
24242	CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1108	---	24242	CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1108	---
24243	CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1109	---	24243	CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1109	---
24244	CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1110	---	24244	CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1110	---
24245	CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1111	---	24245	CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1111	---
24246	CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1112	---	24246	CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1112	---
24247	CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1113	---	24247	CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1113	---
24248	CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1114	---	24248	CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1114	---
24249	CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1115	---	24249	CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1115	---
24250	CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1116	---	24250	CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1116	---
24251	CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1117	---	24251	CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1117	---
24252	CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1118	---	24252	CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1118	---
24253	CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1119	---	24253	CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1119	---
24254	CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1120	---	24254	CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1120	---
24255	CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1121	---	24255	CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1121	---
24256	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1122	---	24256	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1122	---
24257	CEFBS_InMicroMips, // CLZ_MM = 1123	---	24257	CEFBS_InMicroMips, // CLZ_MM = 1123	---
24258	CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1124	---	24258	CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1124	---
24259	CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1125	---	24259	CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1125	---
24260	CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1126	---	24260	CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1126	---
24261	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1127	---	24261	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1127	---
24262	CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1128	---	24262	CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1128	---
24263	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1129	---	24263	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1129	---
24264	CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1130	---	24264	CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1130	---
24265	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1131	---	24265	CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1131	---
24266	CEFBS_HasDSP, // CMPGU_EQ_QB = 1132	---	24266	CEFBS_HasDSP, // CMPGU_EQ_QB = 1132	---
24267	CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1133	---	24267	CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1133	---
24268	CEFBS_HasDSP, // CMPGU_LE_QB = 1134	---	24268	CEFBS_HasDSP, // CMPGU_LE_QB = 1134	---
24269	CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1135	---	24269	CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1135	---
24270	CEFBS_HasDSP, // CMPGU_LT_QB = 1136	---	24270	CEFBS_HasDSP, // CMPGU_LT_QB = 1136	---
24271	CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1137	---	24271	CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1137	---
24272	CEFBS_HasDSP, // CMPU_EQ_QB = 1138	---	24272	CEFBS_HasDSP, // CMPU_EQ_QB = 1138	---
24273	CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1139	---	24273	CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1139	---
24274	CEFBS_HasDSP, // CMPU_LE_QB = 1140	---	24274	CEFBS_HasDSP, // CMPU_LE_QB = 1140	---
24275	CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1141	---	24275	CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1141	---
24276	CEFBS_HasDSP, // CMPU_LT_QB = 1142	---	24276	CEFBS_HasDSP, // CMPU_LT_QB = 1142	---
24277	CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1143	---	24277	CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1143	---
24278	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1144	---	24278	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1144	---
24279	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1145	---	24279	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1145	---
24280	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1146	---	24280	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1146	---
24281	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1147	---	24281	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1147	---
24282	CEFBS_HasDSP, // CMP_EQ_PH = 1148	---	24282	CEFBS_HasDSP, // CMP_EQ_PH = 1148	---
24283	CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1149	---	24283	CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1149	---
24284	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1150	---	24284	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1150	---
24285	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1151	---	24285	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1151	---
24286	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1152	---	24286	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1152	---
24287	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1153	---	24287	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1153	---
24288	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1154	---	24288	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1154	---
24289	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1155	---	24289	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1155	---
24290	CEFBS_HasDSP, // CMP_LE_PH = 1156	---	24290	CEFBS_HasDSP, // CMP_LE_PH = 1156	---
24291	CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1157	---	24291	CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1157	---
24292	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1158	---	24292	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1158	---
24293	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1159	---	24293	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1159	---
24294	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1160	---	24294	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1160	---
24295	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1161	---	24295	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1161	---
24296	CEFBS_HasDSP, // CMP_LT_PH = 1162	---	24296	CEFBS_HasDSP, // CMP_LT_PH = 1162	---
24297	CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1163	---	24297	CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1163	---
24298	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1164	---	24298	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1164	---
24299	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1165	---	24299	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1165	---
24300	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1166	---	24300	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1166	---
24301	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1167	---	24301	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1167	---
24302	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1168	---	24302	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1168	---
24303	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1169	---	24303	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1169	---
24304	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1170	---	24304	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1170	---
24305	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1171	---	24305	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1171	---
24306	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1172	---	24306	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1172	---
24307	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1173	---	24307	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1173	---
24308	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1174	---	24308	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1174	---
24309	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1175	---	24309	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1175	---
24310	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1176	---	24310	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1176	---
24311	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1177	---	24311	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1177	---
24312	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1178	---	24312	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1178	---
24313	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1179	---	24313	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1179	---
24314	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1180	---	24314	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1180	---
24315	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1181	---	24315	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1181	---
24316	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1182	---	24316	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1182	---
24317	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1183	---	24317	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1183	---
24318	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1184	---	24318	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1184	---
24319	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1185	---	24319	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1185	---
24320	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1186	---	24320	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1186	---
24321	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1187	---	24321	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1187	---
24322	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1188	---	24322	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1188	---
24323	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1189	---	24323	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1189	---
24324	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1190	---	24324	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1190	---
24325	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1191	---	24325	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1191	---
24326	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1192	---	24326	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1192	---
24327	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1193	---	24327	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1193	---
24328	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1194	---	24328	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1194	---
24329	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1195	---	24329	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1195	---
24330	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1196	---	24330	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1196	---
24331	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1197	---	24331	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1197	---
24332	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1198	---	24332	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1198	---
24333	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1199	---	24333	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1199	---
24334	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1200	---	24334	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1200	---
24335	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1201	---	24335	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1201	---
24336	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1202	---	24336	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1202	---
24337	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1203	---	24337	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1203	---
24338	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1204	---	24338	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1204	---
24339	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1205	---	24339	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1205	---
24340	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1206	---	24340	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1206	---
24341	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1207	---	24341	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1207	---
24342	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1208	---	24342	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1208	---
24343	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1209	---	24343	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1209	---
24344	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1210	---	24344	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1210	---
24345	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1211	---	24345	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1211	---
24346	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1212	---	24346	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1212	---
24347	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1213	---	24347	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1213	---
24348	CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1214	---	24348	CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1214	---
24349	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1215	---	24349	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1215	---
24350	CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1216	---	24350	CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1216	---
24351	CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1217	---	24351	CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1217	---
24352	CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1218	---	24352	CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1218	---
24353	CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1219	---	24353	CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1219	---
24354	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1220	---	24354	CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1220	---
24355	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1221	---	24355	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1221	---
24356	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1222	---	24356	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1222	---
24357	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1223	---	24357	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1223	---
24358	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1224	---	24358	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1224	---
24359	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1225	---	24359	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1225	---
24360	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1226	---	24360	CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1226	---
24361	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1227	---	24361	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1227	---
24362	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1228	---	24362	CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1228	---
24363	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1229	---	24363	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1229	---
24364	CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1230	---	24364	CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1230	---
24365	CEFBS_InMicroMips, // CTC2_MM = 1231	---	24365	CEFBS_InMicroMips, // CTC2_MM = 1231	---
24366	CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1232	---	24366	CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1232	---
24367	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1233	---	24367	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1233	---
24368	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1234	---	24368	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1234	---
24369	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1235	---	24369	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1235	---
24370	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1236	---	24370	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1236	---
24371	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1237	---	24371	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1237	---
24372	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1238	---	24372	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1238	---
24373	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1239	---	24373	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1239	---
24374	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1240	---	24374	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1240	---
24375	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1241	---	24375	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1241	---
24376	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1242	---	24376	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1242	---
24377	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1243	---	24377	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1243	---
24378	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1244	---	24378	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1244	---
24379	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1245	---	24379	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1245	---
24380	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1246	---	24380	CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1246	---
24381	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1247	---	24381	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1247	---
24382	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1248	---	24382	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1248	---
24383	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1249	---	24383	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1249	---
24384	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1250	---	24384	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1250	---
24385	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1251	---	24385	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1251	---
24386	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1252	---	24386	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1252	---
24387	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1253	---	24387	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1253	---
24388	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1254	---	24388	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1254	---
24389	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1255	---	24389	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1255	---
24390	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1256	---	24390	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1256	---
24391	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1257	---	24391	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1257	---
24392	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1258	---	24392	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1258	---
24393	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1259	---	24393	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1259	---
24394	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1260	---	24394	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1260	---
24395	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1261	---	24395	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1261	---
24396	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1262	---	24396	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1262	---
24397	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1263	---	24397	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1263	---
24398	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1264	---	24398	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1264	---
24399	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1265	---	24399	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1265	---
24400	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1266	---	24400	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1266	---
24401	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1267	---	24401	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1267	---
24402	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1268	---	24402	CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1268	---
24403	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1269	---	24403	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1269	---
24404	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1270	---	24404	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1270	---
24405	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1271	---	24405	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1271	---
24406	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1272	---	24406	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1272	---
24407	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1273	---	24407	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1273	---
24408	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1274	---	24408	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1274	---
24409	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1275	---	24409	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1275	---
24410	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1276	---	24410	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1276	---
24411	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1277	---	24411	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1277	---
24412	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1278	---	24412	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1278	---
24413	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1279	---	24413	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1279	---
24414	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1280	---	24414	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1280	---
24415	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1281	---	24415	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1281	---
24416	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1282	---	24416	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1282	---
24417	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1283	---	24417	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1283	---
24418	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1284	---	24418	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1284	---
24419	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1285	---	24419	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1285	---
24420	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1286	---	24420	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1286	---
24421	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1287	---	24421	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1287	---
24422	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1288	---	24422	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1288	---
24423	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1289	---	24423	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1289	---
24424	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1290	---	24424	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1290	---
24425	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1291	---	24425	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1291	---
24426	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1292	---	24426	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1292	---
24427	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1293	---	24427	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1293	---
24428	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1294	---	24428	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1294	---
24429	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1295	---	24429	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1295	---
24430	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1296	---	24430	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1296	---
24431	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1297	---	24431	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1297	---
24432	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1298	---	24432	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1298	---
24433	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1299	---	24433	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1299	---
24434	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1300	---	24434	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1300	---
24435	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1301	---	24435	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1301	---
24436	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1302	---	24436	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1302	---
24437	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1303	---	24437	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1303	---
24438	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1304	---	24438	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1304	---
24439	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1305	---	24439	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1305	---
24440	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1306	---	24440	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1306	---
24441	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1307	---	24441	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1307	---
24442	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1308	---	24442	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1308	---
24443	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1309	---	24443	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1309	---
24444	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1310	---	24444	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1310	---
24445	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1311	---	24445	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1311	---
24446	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1312	---	24446	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1312	---
24447	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1313	---	24447	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1313	---
24448	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1314	---	24448	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1314	---
24449	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1315	---	24449	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1315	---
24450	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1316	---	24450	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1316	---
24451	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1317	---	24451	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1317	---
24452	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1318	---	24452	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1318	---
24453	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1319	---	24453	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1319	---
24454	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1320	---	24454	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1320	---
24455	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1321	---	24455	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1321	---
24456	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1322	---	24456	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1322	---
24457	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1323	---	24457	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1323	---
24458	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1324	---	24458	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1324	---
24459	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1325	---	24459	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1325	---
24460	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1326	---	24460	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1326	---
24461	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1327	---	24461	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1327	---
24462	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1328	---	24462	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1328	---
24463	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1329	---	24463	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1329	---
24464	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1330	---	24464	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1330	---
24465	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1331	---	24465	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1331	---
24466	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1332	---	24466	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1332	---
24467	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1333	---	24467	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1333	---
24468	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1334	---	24468	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1334	---
24469	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1335	---	24469	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1335	---
24470	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1336	---	24470	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1336	---
24471	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1337	---	24471	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1337	---
24472	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1338	---	24472	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1338	---
24473	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1339	---	24473	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1339	---
24474	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1340	---	24474	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1340	---
24475	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1341	---	24475	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1341	---
24476	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1342	---	24476	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1342	---
24477	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1343	---	24477	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1343	---
24478	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1344	---	24478	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1344	---
24479	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1345	---	24479	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1345	---
24480	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1346	---	24480	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1346	---
24481	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1347	---	24481	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1347	---
24482	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1348	---	24482	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1348	---
24483	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1349	---	24483	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1349	---
24484	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1350	---	24484	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1350	---
24485	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1351	---	24485	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1351	---
24486	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1352	---	24486	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1352	---
24487	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1353	---	24487	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1353	---
24488	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1354	---	24488	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1354	---
24489	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1355	---	24489	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1355	---
24490	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1356	---	24490	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1356	---
24491	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1357	---	24491	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1357	---
24492	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1358	---	24492	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1358	---
24493	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1359	---	24493	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1359	---
24494	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1360	---	24494	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1360	---
24495	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1361	---	24495	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1361	---
24496	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1362	---	24496	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1362	---
24497	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1363	---	24497	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1363	---
24498	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1364	---	24498	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1364	---
24499	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1365	---	24499	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1365	---
24500	CEFBS_InMips16Mode, // CmpRxRy16 = 1366	---	24500	CEFBS_InMips16Mode, // CmpRxRy16 = 1366	---
24501	CEFBS_InMips16Mode, // CmpiRxImm16 = 1367	---	24501	CEFBS_InMips16Mode, // CmpiRxImm16 = 1367	---
24502	CEFBS_InMips16Mode, // CmpiRxImmX16 = 1368	---	24502	CEFBS_InMips16Mode, // CmpiRxImmX16 = 1368	---
24503	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1369	---	24503	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1369	---
24504	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1370	---	24504	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1370	---
24505	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1371	---	24505	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1371	---
24506	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1372	---	24506	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1372	---
24507	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1373	---	24507	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1373	---
24508	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1374	---	24508	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1374	---
24509	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1375	---	24509	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1375	---
24510	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1376	---	24510	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1376	---
24511	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1377	---	24511	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1377	---
24512	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1378	---	24512	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1378	---
24513	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1379	---	24513	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1379	---
24514	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1380	---	24514	CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1380	---
24515	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1381	---	24515	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1381	---
24516	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1382	---	24516	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1382	---
24517	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1383	---	24517	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1383	---
24518	CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1384	---	24518	CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1384	---
24519	CEFBS_InMicroMips, // DERET_MM = 1385	---	24519	CEFBS_InMicroMips, // DERET_MM = 1385	---
24520	CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1386	---	24520	CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1386	---
24521	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1387	---	24521	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1387	---
24522	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1388	---	24522	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1388	---
24523	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1389	---	24523	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1389	---
24524	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1390	---	24524	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1390	---
24525	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1391	---	24525	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1391	---
24526	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1392	---	24526	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1392	---
24527	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1393	---	24527	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1393	---
24528	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1394	---	24528	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1394	---
24529	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1395	---	24529	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1395	---
24530	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1396	---	24530	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1396	---
24531	CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1397	---	24531	CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1397	---
24532	CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1398	---	24532	CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1398	---
24533	CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1399	---	24533	CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1399	---
24534	CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1400	---	24534	CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1400	---
24535	CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1401	---	24535	CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1401	---
24536	CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1402	---	24536	CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1402	---
24537	CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1403	---	24537	CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1403	---
24538	CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1404	---	24538	CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1404	---
24539	CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1405	---	24539	CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1405	---
24540	CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1406	---	24540	CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1406	---
24541	CEFBS_InMicroMips, // DI_MM = 1407	---	24541	CEFBS_InMicroMips, // DI_MM = 1407	---
24542	CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1408	---	24542	CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1408	---
24543	CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1409	---	24543	CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1409	---
24544	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1410	---	24544	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1410	---
24545	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1411	---	24545	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1411	---
24546	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1412	---	24546	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1412	---
24547	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1413	---	24547	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1413	---
24548	CEFBS_HasCnMips, // DMFC2_OCTEON = 1414	---	24548	CEFBS_HasCnMips, // DMFC2_OCTEON = 1414	---
24549	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1415	---	24549	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1415	---
24550	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1416	---	24550	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1416	---
24551	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1417	---	24551	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1417	---
24552	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1418	---	24552	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1418	---
24553	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1419	---	24553	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1419	---
24554	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1420	---	24554	CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1420	---
24555	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1421	---	24555	CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1421	---
24556	CEFBS_HasCnMips, // DMTC2_OCTEON = 1422	---	24556	CEFBS_HasCnMips, // DMTC2_OCTEON = 1422	---
24557	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1423	---	24557	CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1423	---
24558	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1424	---	24558	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1424	---
24559	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1425	---	24559	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1425	---
24560	CEFBS_HasCnMips, // DMUL = 1426	---	24560	CEFBS_HasCnMips, // DMUL = 1426	---
24561	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1427	---	24561	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1427	---
24562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1428	---	24562	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1428	---
24563	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1429	---	24563	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1429	---
24564	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1430	---	24564	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1430	---
24565	CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1431	---	24565	CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1431	---
24566	CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1432	---	24566	CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1432	---
24567	CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1433	---	24567	CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1433	---
24568	CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1434	---	24568	CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1434	---
24569	CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1435	---	24569	CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1435	---
24570	CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1436	---	24570	CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1436	---
24571	CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1437	---	24571	CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1437	---
24572	CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1438	---	24572	CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1438	---
24573	CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1439	---	24573	CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1439	---
24574	CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1440	---	24574	CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1440	---
24575	CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1441	---	24575	CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1441	---
24576	CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1442	---	24576	CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1442	---
24577	CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1443	---	24577	CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1443	---
24578	CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1444	---	24578	CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1444	---
24579	CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1445	---	24579	CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1445	---
24580	CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1446	---	24580	CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1446	---
24581	CEFBS_HasDSP, // DPAQ_SA_L_W = 1447	---	24581	CEFBS_HasDSP, // DPAQ_SA_L_W = 1447	---
24582	CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1448	---	24582	CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1448	---
24583	CEFBS_HasDSP, // DPAQ_S_W_PH = 1449	---	24583	CEFBS_HasDSP, // DPAQ_S_W_PH = 1449	---
24584	CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1450	---	24584	CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1450	---
24585	CEFBS_HasDSP, // DPAU_H_QBL = 1451	---	24585	CEFBS_HasDSP, // DPAU_H_QBL = 1451	---
24586	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1452	---	24586	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1452	---
24587	CEFBS_HasDSP, // DPAU_H_QBR = 1453	---	24587	CEFBS_HasDSP, // DPAU_H_QBR = 1453	---
24588	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1454	---	24588	CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1454	---
24589	CEFBS_HasDSPR2, // DPAX_W_PH = 1455	---	24589	CEFBS_HasDSPR2, // DPAX_W_PH = 1455	---
24590	CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1456	---	24590	CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1456	---
24591	CEFBS_HasDSPR2, // DPA_W_PH = 1457	---	24591	CEFBS_HasDSPR2, // DPA_W_PH = 1457	---
24592	CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1458	---	24592	CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1458	---
24593	CEFBS_HasCnMips, // DPOP = 1459	---	24593	CEFBS_HasCnMips, // DPOP = 1459	---
24594	CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1460	---	24594	CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1460	---
24595	CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1461	---	24595	CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1461	---
24596	CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1462	---	24596	CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1462	---
24597	CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1463	---	24597	CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1463	---
24598	CEFBS_HasDSP, // DPSQ_SA_L_W = 1464	---	24598	CEFBS_HasDSP, // DPSQ_SA_L_W = 1464	---
24599	CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1465	---	24599	CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1465	---
24600	CEFBS_HasDSP, // DPSQ_S_W_PH = 1466	---	24600	CEFBS_HasDSP, // DPSQ_S_W_PH = 1466	---
24601	CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1467	---	24601	CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1467	---
24602	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1468	---	24602	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1468	---
24603	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1469	---	24603	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1469	---
24604	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1470	---	24604	CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1470	---
24605	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1471	---	24605	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1471	---
24606	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1472	---	24606	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1472	---
24607	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1473	---	24607	CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1473	---
24608	CEFBS_HasDSP, // DPSU_H_QBL = 1474	---	24608	CEFBS_HasDSP, // DPSU_H_QBL = 1474	---
24609	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1475	---	24609	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1475	---
24610	CEFBS_HasDSP, // DPSU_H_QBR = 1476	---	24610	CEFBS_HasDSP, // DPSU_H_QBR = 1476	---
24611	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1477	---	24611	CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1477	---
24612	CEFBS_HasDSPR2, // DPSX_W_PH = 1478	---	24612	CEFBS_HasDSPR2, // DPSX_W_PH = 1478	---
24613	CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1479	---	24613	CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1479	---
24614	CEFBS_HasDSPR2, // DPS_W_PH = 1480	---	24614	CEFBS_HasDSPR2, // DPS_W_PH = 1480	---
24615	CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1481	---	24615	CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1481	---
24616	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1482	---	24616	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1482	---
24617	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1483	---	24617	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1483	---
24618	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1484	---	24618	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1484	---
24619	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1485	---	24619	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1485	---
24620	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1486	---	24620	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1486	---
24621	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1487	---	24621	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1487	---
24622	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1488	---	24622	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1488	---
24623	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1489	---	24623	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1489	---
24624	CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1490	---	24624	CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1490	---
24625	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1491	---	24625	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1491	---
24626	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1492	---	24626	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1492	---
24627	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1493	---	24627	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1493	---
24628	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1494	---	24628	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1494	---
24629	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1495	---	24629	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1495	---
24630	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1496	---	24630	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1496	---
24631	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1497	---	24631	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1497	---
24632	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1498	---	24632	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1498	---
24633	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1499	---	24633	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1499	---
24634	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1500	---	24634	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1500	---
24635	CEFBS_HasStdEnc_HasMips32r6, // DVP = 1501	---	24635	CEFBS_HasStdEnc_HasMips32r6, // DVP = 1501	---
24636	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1502	---	24636	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1502	---
24637	CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1503	---	24637	CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1503	---
24638	CEFBS_InMips16Mode, // DivRxRy16 = 1504	---	24638	CEFBS_InMips16Mode, // DivRxRy16 = 1504	---
24639	CEFBS_InMips16Mode, // DivuRxRy16 = 1505	---	24639	CEFBS_InMips16Mode, // DivuRxRy16 = 1505	---
24640	CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1506	---	24640	CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1506	---
24641	CEFBS_InMicroMips, // EHB_MM = 1507	---	24641	CEFBS_InMicroMips, // EHB_MM = 1507	---
24642	CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1508	---	24642	CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1508	---
24643	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1509	---	24643	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1509	---
24644	CEFBS_InMicroMips, // EI_MM = 1510	---	24644	CEFBS_InMicroMips, // EI_MM = 1510	---
24645	CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1511	---	24645	CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1511	---
24646	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1512	---	24646	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1512	---
24647	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1513	---	24647	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1513	---
24648	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1514	---	24648	CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1514	---
24649	CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1515	---	24649	CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1515	---
24650	CEFBS_InMicroMips, // ERET_MM = 1516	---	24650	CEFBS_InMicroMips, // ERET_MM = 1516	---
24651	CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1517	---	24651	CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1517	---
24652	CEFBS_HasStdEnc_HasMips32r6, // EVP = 1518	---	24652	CEFBS_HasStdEnc_HasMips32r6, // EVP = 1518	---
24653	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1519	---	24653	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1519	---
24654	CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1520	---	24654	CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1520	---
24655	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1521	---	24655	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1521	---
24656	CEFBS_HasDSP, // EXTP = 1522	---	24656	CEFBS_HasDSP, // EXTP = 1522	---
24657	CEFBS_HasDSP, // EXTPDP = 1523	---	24657	CEFBS_HasDSP, // EXTPDP = 1523	---
24658	CEFBS_HasDSP, // EXTPDPV = 1524	---	24658	CEFBS_HasDSP, // EXTPDPV = 1524	---
24659	CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1525	---	24659	CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1525	---
24660	CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1526	---	24660	CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1526	---
24661	CEFBS_HasDSP, // EXTPV = 1527	---	24661	CEFBS_HasDSP, // EXTPV = 1527	---
24662	CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1528	---	24662	CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1528	---
24663	CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1529	---	24663	CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1529	---
24664	CEFBS_HasDSP, // EXTRV_RS_W = 1530	---	24664	CEFBS_HasDSP, // EXTRV_RS_W = 1530	---
24665	CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1531	---	24665	CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1531	---
24666	CEFBS_HasDSP, // EXTRV_R_W = 1532	---	24666	CEFBS_HasDSP, // EXTRV_R_W = 1532	---
24667	CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1533	---	24667	CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1533	---
24668	CEFBS_HasDSP, // EXTRV_S_H = 1534	---	24668	CEFBS_HasDSP, // EXTRV_S_H = 1534	---
24669	CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1535	---	24669	CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1535	---
24670	CEFBS_HasDSP, // EXTRV_W = 1536	---	24670	CEFBS_HasDSP, // EXTRV_W = 1536	---
24671	CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1537	---	24671	CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1537	---
24672	CEFBS_HasDSP, // EXTR_RS_W = 1538	---	24672	CEFBS_HasDSP, // EXTR_RS_W = 1538	---
24673	CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1539	---	24673	CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1539	---
24674	CEFBS_HasDSP, // EXTR_R_W = 1540	---	24674	CEFBS_HasDSP, // EXTR_R_W = 1540	---
24675	CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1541	---	24675	CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1541	---
24676	CEFBS_HasDSP, // EXTR_S_H = 1542	---	24676	CEFBS_HasDSP, // EXTR_S_H = 1542	---
24677	CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1543	---	24677	CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1543	---
24678	CEFBS_HasDSP, // EXTR_W = 1544	---	24678	CEFBS_HasDSP, // EXTR_W = 1544	---
24679	CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1545	---	24679	CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1545	---
24680	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1546	---	24680	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1546	---
24681	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1547	---	24681	CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1547	---
24682	CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1548	---	24682	CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1548	---
24683	CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1549	---	24683	CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1549	---
24684	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1550	---	24684	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1550	---
24685	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1551	---	24685	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1551	---
24686	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1552	---	24686	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1552	---
24687	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1553	---	24687	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1553	---
24688	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1554	---	24688	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1554	---
24689	CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1555	---	24689	CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1555	---
24690	CEFBS_HasStdEnc_HasMSA, // FADD_D = 1556	---	24690	CEFBS_HasStdEnc_HasMSA, // FADD_D = 1556	---
24691	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1557	---	24691	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1557	---
24692	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1558	---	24692	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1558	---
24693	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1559	---	24693	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1559	---
24694	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1560	---	24694	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1560	---
24695	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1561	---	24695	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1561	---
24696	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1562	---	24696	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1562	---
24697	CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1563	---	24697	CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1563	---
24698	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1564	---	24698	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1564	---
24699	CEFBS_HasStdEnc_HasMSA, // FADD_W = 1565	---	24699	CEFBS_HasStdEnc_HasMSA, // FADD_W = 1565	---
24700	CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1566	---	24700	CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1566	---
24701	CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1567	---	24701	CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1567	---
24702	CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1568	---	24702	CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1568	---
24703	CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1569	---	24703	CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1569	---
24704	CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1570	---	24704	CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1570	---
24705	CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1571	---	24705	CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1571	---
24706	CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1572	---	24706	CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1572	---
24707	CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1573	---	24707	CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1573	---
24708	CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1574	---	24708	CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1574	---
24709	CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1575	---	24709	CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1575	---
24710	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1576	---	24710	CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1576	---
24711	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1577	---	24711	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1577	---
24712	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1578	---	24712	CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1578	---
24713	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1579	---	24713	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1579	---
24714	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1580	---	24714	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1580	---
24715	CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1581	---	24715	CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1581	---
24716	CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1582	---	24716	CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1582	---
24717	CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1583	---	24717	CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1583	---
24718	CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1584	---	24718	CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1584	---
24719	CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1585	---	24719	CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1585	---
24720	CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1586	---	24720	CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1586	---
24721	CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1587	---	24721	CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1587	---
24722	CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1588	---	24722	CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1588	---
24723	CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1589	---	24723	CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1589	---
24724	CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1590	---	24724	CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1590	---
24725	CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1591	---	24725	CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1591	---
24726	CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1592	---	24726	CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1592	---
24727	CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1593	---	24727	CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1593	---
24728	CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1594	---	24728	CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1594	---
24729	CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1595	---	24729	CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1595	---
24730	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1596	---	24730	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1596	---
24731	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1597	---	24731	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1597	---
24732	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1598	---	24732	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1598	---
24733	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1599	---	24733	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1599	---
24734	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1600	---	24734	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1600	---
24735	CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1601	---	24735	CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1601	---
24736	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1602	---	24736	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1602	---
24737	CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1603	---	24737	CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1603	---
24738	CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1604	---	24738	CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1604	---
24739	CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1605	---	24739	CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1605	---
24740	CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1606	---	24740	CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1606	---
24741	CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1607	---	24741	CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1607	---
24742	CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1608	---	24742	CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1608	---
24743	CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1609	---	24743	CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1609	---
24744	CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1610	---	24744	CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1610	---
24745	CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1611	---	24745	CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1611	---
24746	CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1612	---	24746	CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1612	---
24747	CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1613	---	24747	CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1613	---
24748	CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1614	---	24748	CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1614	---
24749	CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1615	---	24749	CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1615	---
24750	CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1616	---	24750	CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1616	---
24751	CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1617	---	24751	CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1617	---
24752	CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1618	---	24752	CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1618	---
24753	CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1619	---	24753	CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1619	---
24754	CEFBS_HasStdEnc_HasMSA, // FILL_B = 1620	---	24754	CEFBS_HasStdEnc_HasMSA, // FILL_B = 1620	---
24755	CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1621	---	24755	CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1621	---
24756	CEFBS_HasStdEnc_HasMSA, // FILL_H = 1622	---	24756	CEFBS_HasStdEnc_HasMSA, // FILL_H = 1622	---
24757	CEFBS_HasStdEnc_HasMSA, // FILL_W = 1623	---	24757	CEFBS_HasStdEnc_HasMSA, // FILL_W = 1623	---
24758	CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1624	---	24758	CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1624	---
24759	CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1625	---	24759	CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1625	---
24760	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1626	---	24760	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1626	---
24761	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1627	---	24761	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1627	---
24762	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1628	---	24762	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1628	---
24763	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1629	---	24763	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1629	---
24764	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1630	---	24764	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1630	---
24765	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1631	---	24765	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1631	---
24766	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1632	---	24766	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1632	---
24767	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1633	---	24767	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1633	---
24768	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1634	---	24768	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1634	---
24769	CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1635	---	24769	CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1635	---
24770	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1636	---	24770	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1636	---
24771	CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1637	---	24771	CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1637	---
24772	CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1638	---	24772	CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1638	---
24773	CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1639	---	24773	CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1639	---
24774	CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1640	---	24774	CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1640	---
24775	CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1641	---	24775	CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1641	---
24776	CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1642	---	24776	CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1642	---
24777	CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1643	---	24777	CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1643	---
24778	CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1644	---	24778	CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1644	---
24779	CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1645	---	24779	CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1645	---
24780	CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1646	---	24780	CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1646	---
24781	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1647	---	24781	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1647	---
24782	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1648	---	24782	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1648	---
24783	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1649	---	24783	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1649	---
24784	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1650	---	24784	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1650	---
24785	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1651	---	24785	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1651	---
24786	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1652	---	24786	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1652	---
24787	CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1653	---	24787	CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1653	---
24788	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1654	---	24788	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1654	---
24789	CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1655	---	24789	CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1655	---
24790	CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1656	---	24790	CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1656	---
24791	CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1657	---	24791	CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1657	---
24792	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1658	---	24792	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1658	---
24793	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1659	---	24793	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1659	---
24794	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1660	---	24794	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1660	---
24795	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1661	---	24795	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1661	---
24796	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1662	---	24796	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1662	---
24797	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1663	---	24797	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1663	---
24798	CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1664	---	24798	CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1664	---
24799	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1665	---	24799	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1665	---
24800	CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1666	---	24800	CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1666	---
24801	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1667	---	24801	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1667	---
24802	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1668	---	24802	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1668	---
24803	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1669	---	24803	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1669	---
24804	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1670	---	24804	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1670	---
24805	CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1671	---	24805	CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1671	---
24806	CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1672	---	24806	CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1672	---
24807	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1673	---	24807	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1673	---
24808	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1674	---	24808	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1674	---
24809	CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1675	---	24809	CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1675	---
24810	CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1676	---	24810	CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1676	---
24811	CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1677	---	24811	CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1677	---
24812	CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1678	---	24812	CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1678	---
24813	CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1679	---	24813	CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1679	---
24814	CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1680	---	24814	CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1680	---
24815	CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1681	---	24815	CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1681	---
24816	CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1682	---	24816	CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1682	---
24817	CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1683	---	24817	CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1683	---
24818	CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1684	---	24818	CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1684	---
24819	CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1685	---	24819	CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1685	---
24820	CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1686	---	24820	CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1686	---
24821	CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1687	---	24821	CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1687	---
24822	CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1688	---	24822	CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1688	---
24823	CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1689	---	24823	CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1689	---
24824	CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1690	---	24824	CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1690	---
24825	CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1691	---	24825	CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1691	---
24826	CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1692	---	24826	CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1692	---
24827	CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1693	---	24827	CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1693	---
24828	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1694	---	24828	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1694	---
24829	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1695	---	24829	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1695	---
24830	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1696	---	24830	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1696	---
24831	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1697	---	24831	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1697	---
24832	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1698	---	24832	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1698	---
24833	CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1699	---	24833	CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1699	---
24834	CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1700	---	24834	CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1700	---
24835	CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1701	---	24835	CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1701	---
24836	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1702	---	24836	CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1702	---
24837	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1703	---	24837	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1703	---
24838	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1704	---	24838	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1704	---
24839	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1705	---	24839	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1705	---
24840	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1706	---	24840	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1706	---
24841	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1707	---	24841	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1707	---
24842	CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1708	---	24842	CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1708	---
24843	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1709	---	24843	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1709	---
24844	CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1710	---	24844	CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1710	---
24845	CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1711	---	24845	CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1711	---
24846	CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1712	---	24846	CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1712	---
24847	CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1713	---	24847	CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1713	---
24848	CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1714	---	24848	CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1714	---
24849	CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1715	---	24849	CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1715	---
24850	CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1716	---	24850	CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1716	---
24851	CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1717	---	24851	CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1717	---
24852	CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1718	---	24852	CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1718	---
24853	CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1719	---	24853	CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1719	---
24854	CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1720	---	24854	CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1720	---
24855	CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1721	---	24855	CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1721	---
24856	CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1722	---	24856	CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1722	---
24857	CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1723	---	24857	CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1723	---
24858	CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1724	---	24858	CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1724	---
24859	CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1725	---	24859	CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1725	---
24860	CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1726	---	24860	CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1726	---
24861	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1727	---	24861	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1727	---
24862	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1728	---	24862	CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1728	---
24863	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1729	---	24863	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1729	---
24864	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1730	---	24864	CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1730	---
24865	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1731	---	24865	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1731	---
24866	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1732	---	24866	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1732	---
24867	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1733	---	24867	CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1733	---
24868	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1734	---	24868	CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1734	---
24869	CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1735	---	24869	CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1735	---
24870	CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1736	---	24870	CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1736	---
24871	CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1737	---	24871	CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1737	---
24872	CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1738	---	24872	CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1738	---
24873	CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1739	---	24873	CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1739	---
24874	CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1740	---	24874	CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1740	---
24875	CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1741	---	24875	CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1741	---
24876	CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1742	---	24876	CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1742	---
24877	CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1743	---	24877	CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1743	---
24878	CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1744	---	24878	CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1744	---
24879	CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1745	---	24879	CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1745	---
24880	CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1746	---	24880	CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1746	---
24881	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1747	---	24881	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1747	---
24882	CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1748	---	24882	CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1748	---
24883	CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1749	---	24883	CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1749	---
24884	CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1750	---	24884	CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1750	---
24885	CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1751	---	24885	CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1751	---
24886	CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1752	---	24886	CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1752	---
24887	CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1753	---	24887	CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1753	---
24888	CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1754	---	24888	CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1754	---
24889	CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1755	---	24889	CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1755	---
24890	CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1756	---	24890	CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1756	---
24891	CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1757	---	24891	CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1757	---
24892	CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1758	---	24892	CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1758	---
24893	CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1759	---	24893	CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1759	---
24894	CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1760	---	24894	CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1760	---
24895	CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1761	---	24895	CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1761	---
24896	CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1762	---	24896	CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1762	---
24897	CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1763	---	24897	CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1763	---
24898	CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1764	---	24898	CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1764	---
24899	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1765	---	24899	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1765	---
24900	CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1766	---	24900	CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1766	---
24901	CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1767	---	24901	CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1767	---
24902	CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1768	---	24902	CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1768	---
24903	CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1769	---	24903	CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1769	---
24904	CEFBS_HasDSP, // INSV = 1770	---	24904	CEFBS_HasDSP, // INSV = 1770	---
24905	CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1771	---	24905	CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1771	---
24906	CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1772	---	24906	CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1772	---
24907	CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1773	---	24907	CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1773	---
24908	CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1774	---	24908	CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1774	---
24909	CEFBS_InMicroMips_HasDSP, // INSV_MM = 1775	---	24909	CEFBS_InMicroMips_HasDSP, // INSV_MM = 1775	---
24910	CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1776	---	24910	CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1776	---
24911	CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1777	---	24911	CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1777	---
24912	CEFBS_HasStdEnc_NotInMicroMips, // J = 1778	---	24912	CEFBS_HasStdEnc_NotInMicroMips, // J = 1778	---
24913	CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1779	---	24913	CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1779	---
24914	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1780	---	24914	CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1780	---
24915	CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1781	---	24915	CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1781	---
24916	CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1782	---	24916	CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1782	---
24917	CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1783	---	24917	CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1783	---
24918	CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1784	---	24918	CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1784	---
24919	CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1785	---	24919	CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1785	---
24920	CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1786	---	24920	CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1786	---
24921	CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1787	---	24921	CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1787	---
24922	CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1788	---	24922	CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1788	---
24923	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1789	---	24923	CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1789	---
24924	CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1790	---	24924	CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1790	---
24925	CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1791	---	24925	CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1791	---
24926	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1792	---	24926	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1792	---
24927	CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1793	---	24927	CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1793	---
24928	CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1794	---	24928	CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1794	---
24929	CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1795	---	24929	CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1795	---
24930	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1796	---	24930	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1796	---
24931	CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1797	---	24931	CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1797	---
24932	CEFBS_HasStdEnc_HasMips32r6, // JIC = 1798	---	24932	CEFBS_HasStdEnc_HasMips32r6, // JIC = 1798	---
24933	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1799	---	24933	CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1799	---
24934	CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1800	---	24934	CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1800	---
24935	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1801	---	24935	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1801	---
24936	CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1802	---	24936	CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1802	---
24937	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1803	---	24937	CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1803	---
24938	CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1804	---	24938	CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1804	---
24939	CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1805	---	24939	CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1805	---
24940	CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1806	---	24940	CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1806	---
24941	CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1807	---	24941	CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1807	---
24942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1808	---	24942	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1808	---
24943	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1809	---	24943	CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1809	---
24944	CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1810	---	24944	CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1810	---
24945	CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1811	---	24945	CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1811	---
24946	CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1812	---	24946	CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1812	---
24947	CEFBS_InMicroMips_NotMips32r6, // J_MM = 1813	---	24947	CEFBS_InMicroMips_NotMips32r6, // J_MM = 1813	---
24948	CEFBS_InMips16Mode, // Jal16 = 1814	---	24948	CEFBS_InMips16Mode, // Jal16 = 1814	---
24949	CEFBS_InMips16Mode, // JalB16 = 1815	---	24949	CEFBS_InMips16Mode, // JalB16 = 1815	---
24950	CEFBS_InMips16Mode, // JrRa16 = 1816	---	24950	CEFBS_InMips16Mode, // JrRa16 = 1816	---
24951	CEFBS_InMips16Mode, // JrcRa16 = 1817	---	24951	CEFBS_InMips16Mode, // JrcRa16 = 1817	---
24952	CEFBS_InMips16Mode, // JrcRx16 = 1818	---	24952	CEFBS_InMips16Mode, // JrcRx16 = 1818	---
24953	CEFBS_InMips16Mode, // JumpLinkReg16 = 1819	---	24953	CEFBS_InMips16Mode, // JumpLinkReg16 = 1819	---
24954	CEFBS_HasStdEnc_NotInMicroMips, // LB = 1820	---	24954	CEFBS_HasStdEnc_NotInMicroMips, // LB = 1820	---
24955	CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1821	---	24955	CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1821	---
24956	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1822	---	24956	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1822	---
24957	CEFBS_InMicroMips_HasEVA, // LBE_MM = 1823	---	24957	CEFBS_InMicroMips_HasEVA, // LBE_MM = 1823	---
24958	CEFBS_InMicroMips, // LBU16_MM = 1824	---	24958	CEFBS_InMicroMips, // LBU16_MM = 1824	---
24959	CEFBS_HasDSP, // LBUX = 1825	---	24959	CEFBS_HasDSP, // LBUX = 1825	---
24960	CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1826	---	24960	CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1826	---
24961	CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1827	---	24961	CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1827	---
24962	CEFBS_InMicroMips, // LB_MM = 1828	---	24962	CEFBS_InMicroMips, // LB_MM = 1828	---
24963	CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1829	---	24963	CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1829	---
24964	CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1830	---	24964	CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1830	---
24965	CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1831	---	24965	CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1831	---
24966	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1832	---	24966	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1832	---
24967	CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1833	---	24967	CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1833	---
24968	CEFBS_InMicroMips, // LBu_MM = 1834	---	24968	CEFBS_InMicroMips, // LBu_MM = 1834	---
24969	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1835	---	24969	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1835	---
24970	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1836	---	24970	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1836	---
24971	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1837	---	24971	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1837	---
24972	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1838	---	24972	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1838	---
24973	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1839	---	24973	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1839	---
24974	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1840	---	24974	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1840	---
24975	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1841	---	24975	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1841	---
24976	CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1842	---	24976	CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1842	---
24977	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1843	---	24977	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1843	---
24978	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1844	---	24978	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1844	---
24979	CEFBS_HasStdEnc_HasMSA, // LDI_B = 1845	---	24979	CEFBS_HasStdEnc_HasMSA, // LDI_B = 1845	---
24980	CEFBS_HasStdEnc_HasMSA, // LDI_D = 1846	---	24980	CEFBS_HasStdEnc_HasMSA, // LDI_D = 1846	---
24981	CEFBS_HasStdEnc_HasMSA, // LDI_H = 1847	---	24981	CEFBS_HasStdEnc_HasMSA, // LDI_H = 1847	---
24982	CEFBS_HasStdEnc_HasMSA, // LDI_W = 1848	---	24982	CEFBS_HasStdEnc_HasMSA, // LDI_W = 1848	---
24983	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1849	---	24983	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1849	---
24984	CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1850	---	24984	CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1850	---
24985	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1851	---	24985	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1851	---
24986	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1852	---	24986	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1852	---
24987	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1853	---	24987	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1853	---
24988	CEFBS_HasStdEnc_HasMSA, // LD_B = 1854	---	24988	CEFBS_HasStdEnc_HasMSA, // LD_B = 1854	---
24989	CEFBS_HasStdEnc_HasMSA, // LD_D = 1855	---	24989	CEFBS_HasStdEnc_HasMSA, // LD_D = 1855	---
24990	CEFBS_HasStdEnc_HasMSA, // LD_H = 1856	---	24990	CEFBS_HasStdEnc_HasMSA, // LD_H = 1856	---
24991	CEFBS_HasStdEnc_HasMSA, // LD_W = 1857	---	24991	CEFBS_HasStdEnc_HasMSA, // LD_W = 1857	---
24992	CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1858	---	24992	CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1858	---
24993	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1859	---	24993	CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1859	---
24994	CEFBS_InMicroMips, // LEA_ADDiu_MM = 1860	---	24994	CEFBS_InMicroMips, // LEA_ADDiu_MM = 1860	---
24995	CEFBS_HasStdEnc_NotInMicroMips, // LH = 1861	---	24995	CEFBS_HasStdEnc_NotInMicroMips, // LH = 1861	---
24996	CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1862	---	24996	CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1862	---
24997	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1863	---	24997	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1863	---
24998	CEFBS_InMicroMips_HasEVA, // LHE_MM = 1864	---	24998	CEFBS_InMicroMips_HasEVA, // LHE_MM = 1864	---
24999	CEFBS_InMicroMips, // LHU16_MM = 1865	---	24999	CEFBS_InMicroMips, // LHU16_MM = 1865	---
25000	CEFBS_HasDSP, // LHX = 1866	---	25000	CEFBS_HasDSP, // LHX = 1866	---
25001	CEFBS_InMicroMips_HasDSP, // LHX_MM = 1867	---	25001	CEFBS_InMicroMips_HasDSP, // LHX_MM = 1867	---
25002	CEFBS_InMicroMips, // LH_MM = 1868	---	25002	CEFBS_InMicroMips, // LH_MM = 1868	---
25003	CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1869	---	25003	CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1869	---
25004	CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1870	---	25004	CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1870	---
25005	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1871	---	25005	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1871	---
25006	CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1872	---	25006	CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1872	---
25007	CEFBS_InMicroMips, // LHu_MM = 1873	---	25007	CEFBS_InMicroMips, // LHu_MM = 1873	---
25008	CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1874	---	25008	CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1874	---
25009	CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1875	---	25009	CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1875	---
25010	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1876	---	25010	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1876	---
25011	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1877	---	25011	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1877	---
25012	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1878	---	25012	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1878	---
25013	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1879	---	25013	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1879	---
25014	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1880	---	25014	CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1880	---
25015	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1881	---	25015	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1881	---
25016	CEFBS_InMicroMips_HasEVA, // LLE_MM = 1882	---	25016	CEFBS_InMicroMips_HasEVA, // LLE_MM = 1882	---
25017	CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1883	---	25017	CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1883	---
25018	CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1884	---	25018	CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1884	---
25019	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1885	---	25019	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1885	---
25020	CEFBS_HasStdEnc_HasMSA, // LSA = 1886	---	25020	CEFBS_HasStdEnc_HasMSA, // LSA = 1886	---
25021	CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1887	---	25021	CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1887	---
25022	CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1888	---	25022	CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1888	---
25023	CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1889	---	25023	CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1889	---
25024	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1890	---	25024	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1890	---
25025	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1891	---	25025	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1891	---
25026	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1892	---	25026	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1892	---
25027	CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1893	---	25027	CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1893	---
25028	CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1894	---	25028	CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1894	---
25029	CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1895	---	25029	CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1895	---
25030	CEFBS_HasStdEnc_NotInMicroMips, // LW = 1896	---	25030	CEFBS_HasStdEnc_NotInMicroMips, // LW = 1896	---
25031	CEFBS_InMicroMips, // LW16_MM = 1897	---	25031	CEFBS_InMicroMips, // LW16_MM = 1897	---
25032	CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1898	---	25032	CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1898	---
25033	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1899	---	25033	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1899	---
25034	CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1900	---	25034	CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1900	---
25035	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1901	---	25035	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1901	---
25036	CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1902	---	25036	CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1902	---
25037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1903	---	25037	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1903	---
25038	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1904	---	25038	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1904	---
25039	CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1905	---	25039	CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1905	---
25040	CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1906	---	25040	CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1906	---
25041	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1907	---	25041	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1907	---
25042	CEFBS_InMicroMips_HasEVA, // LWE_MM = 1908	---	25042	CEFBS_InMicroMips_HasEVA, // LWE_MM = 1908	---
25043	CEFBS_InMicroMips, // LWGP_MM = 1909	---	25043	CEFBS_InMicroMips, // LWGP_MM = 1909	---
25044	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1910	---	25044	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1910	---
25045	CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1911	---	25045	CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1911	---
25046	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1912	---	25046	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1912	---
25047	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1913	---	25047	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1913	---
25048	CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1914	---	25048	CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1914	---
25049	CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1915	---	25049	CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1915	---
25050	CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1916	---	25050	CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1916	---
25051	CEFBS_InMicroMips, // LWM32_MM = 1917	---	25051	CEFBS_InMicroMips, // LWM32_MM = 1917	---
25052	CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1918	---	25052	CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1918	---
25053	CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1919	---	25053	CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1919	---
25054	CEFBS_InMicroMips, // LWP_MM = 1920	---	25054	CEFBS_InMicroMips, // LWP_MM = 1920	---
25055	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1921	---	25055	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1921	---
25056	CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1922	---	25056	CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1922	---
25057	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1923	---	25057	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1923	---
25058	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1924	---	25058	CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1924	---
25059	CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1925	---	25059	CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1925	---
25060	CEFBS_InMicroMips, // LWSP_MM = 1926	---	25060	CEFBS_InMicroMips, // LWSP_MM = 1926	---
25061	CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1927	---	25061	CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1927	---
25062	CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1928	---	25062	CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1928	---
25063	CEFBS_HasDSP, // LWX = 1929	---	25063	CEFBS_HasDSP, // LWX = 1929	---
25064	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1930	---	25064	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1930	---
25065	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1931	---	25065	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1931	---
25066	CEFBS_InMicroMips, // LWXS_MM = 1932	---	25066	CEFBS_InMicroMips, // LWXS_MM = 1932	---
25067	CEFBS_InMicroMips_HasDSP, // LWX_MM = 1933	---	25067	CEFBS_InMicroMips_HasDSP, // LWX_MM = 1933	---
25068	CEFBS_InMicroMips, // LW_MM = 1934	---	25068	CEFBS_InMicroMips, // LW_MM = 1934	---
25069	CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1935	---	25069	CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1935	---
25070	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1936	---	25070	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1936	---
25071	CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1937	---	25071	CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1937	---
25072	CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1938	---	25072	CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1938	---
25073	CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1939	---	25073	CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1939	---
25074	CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1940	---	25074	CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1940	---
25075	CEFBS_InMips16Mode, // LiRxImm16 = 1941	---	25075	CEFBS_InMips16Mode, // LiRxImm16 = 1941	---
25076	CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1942	---	25076	CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1942	---
25077	CEFBS_InMips16Mode, // LiRxImmX16 = 1943	---	25077	CEFBS_InMips16Mode, // LiRxImmX16 = 1943	---
25078	CEFBS_InMips16Mode, // LwRxPcTcp16 = 1944	---	25078	CEFBS_InMips16Mode, // LwRxPcTcp16 = 1944	---
25079	CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1945	---	25079	CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1945	---
25080	CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1946	---	25080	CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1946	---
25081	CEFBS_InMips16Mode, // LwRxSpImmX16 = 1947	---	25081	CEFBS_InMips16Mode, // LwRxSpImmX16 = 1947	---
25082	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1948	---	25082	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1948	---
25083	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1949	---	25083	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1949	---
25084	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1950	---	25084	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1950	---
25085	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1951	---	25085	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1951	---
25086	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1952	---	25086	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1952	---
25087	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1953	---	25087	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1953	---
25088	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1954	---	25088	CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1954	---
25089	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1955	---	25089	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1955	---
25090	CEFBS_HasDSP, // MADDU_DSP = 1956	---	25090	CEFBS_HasDSP, // MADDU_DSP = 1956	---
25091	CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1957	---	25091	CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1957	---
25092	CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1958	---	25092	CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1958	---
25093	CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1959	---	25093	CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1959	---
25094	CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1960	---	25094	CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1960	---
25095	CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1961	---	25095	CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1961	---
25096	CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1962	---	25096	CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1962	---
25097	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1963	---	25097	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1963	---
25098	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1964	---	25098	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1964	---
25099	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1965	---	25099	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1965	---
25100	CEFBS_HasDSP, // MADD_DSP = 1966	---	25100	CEFBS_HasDSP, // MADD_DSP = 1966	---
25101	CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1967	---	25101	CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1967	---
25102	CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1968	---	25102	CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1968	---
25103	CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1969	---	25103	CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1969	---
25104	CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1970	---	25104	CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1970	---
25105	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1971	---	25105	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1971	---
25106	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1972	---	25106	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1972	---
25107	CEFBS_HasDSP, // MAQ_SA_W_PHL = 1973	---	25107	CEFBS_HasDSP, // MAQ_SA_W_PHL = 1973	---
25108	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1974	---	25108	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1974	---
25109	CEFBS_HasDSP, // MAQ_SA_W_PHR = 1975	---	25109	CEFBS_HasDSP, // MAQ_SA_W_PHR = 1975	---
25110	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1976	---	25110	CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1976	---
25111	CEFBS_HasDSP, // MAQ_S_W_PHL = 1977	---	25111	CEFBS_HasDSP, // MAQ_S_W_PHL = 1977	---
25112	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1978	---	25112	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1978	---
25113	CEFBS_HasDSP, // MAQ_S_W_PHR = 1979	---	25113	CEFBS_HasDSP, // MAQ_S_W_PHR = 1979	---
25114	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1980	---	25114	CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1980	---
25115	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1981	---	25115	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1981	---
25116	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1982	---	25116	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1982	---
25117	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1983	---	25117	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1983	---
25118	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1984	---	25118	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1984	---
25119	CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1985	---	25119	CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1985	---
25120	CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1986	---	25120	CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1986	---
25121	CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1987	---	25121	CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1987	---
25122	CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1988	---	25122	CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1988	---
25123	CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1989	---	25123	CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1989	---
25124	CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1990	---	25124	CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1990	---
25125	CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1991	---	25125	CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1991	---
25126	CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1992	---	25126	CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1992	---
25127	CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1993	---	25127	CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1993	---
25128	CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1994	---	25128	CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1994	---
25129	CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1995	---	25129	CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1995	---
25130	CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1996	---	25130	CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1996	---
25131	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1997	---	25131	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1997	---
25132	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1998	---	25132	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1998	---
25133	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1999	---	25133	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1999	---
25134	CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2000	---	25134	CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2000	---
25135	CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2001	---	25135	CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2001	---
25136	CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2002	---	25136	CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2002	---
25137	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2003	---	25137	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2003	---
25138	CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2004	---	25138	CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2004	---
25139	CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2005	---	25139	CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2005	---
25140	CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2006	---	25140	CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2006	---
25141	CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2007	---	25141	CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2007	---
25142	CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2008	---	25142	CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2008	---
25143	CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2009	---	25143	CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2009	---
25144	CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2010	---	25144	CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2010	---
25145	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2011	---	25145	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2011	---
25146	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2012	---	25146	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2012	---
25147	CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2013	---	25147	CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2013	---
25148	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2014	---	25148	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2014	---
25149	CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2015	---	25149	CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2015	---
25150	CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2016	---	25150	CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2016	---
25151	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2017	---	25151	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2017	---
25152	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2018	---	25152	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2018	---
25153	CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2019	---	25153	CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2019	---
25154	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2020	---	25154	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2020	---
25155	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2021	---	25155	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2021	---
25156	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2022	---	25156	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2022	---
25157	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2023	---	25157	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2023	---
25158	CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2024	---	25158	CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2024	---
25159	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2025	---	25159	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2025	---
25160	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2026	---	25160	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2026	---
25161	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2027	---	25161	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2027	---
25162	CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2028	---	25162	CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2028	---
25163	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2029	---	25163	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2029	---
25164	CEFBS_HasDSP, // MFHI_DSP = 2030	---	25164	CEFBS_HasDSP, // MFHI_DSP = 2030	---
25165	CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2031	---	25165	CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2031	---
25166	CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2032	---	25166	CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2032	---
25167	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2033	---	25167	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2033	---
25168	CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2034	---	25168	CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2034	---
25169	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2035	---	25169	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2035	---
25170	CEFBS_HasDSP, // MFLO_DSP = 2036	---	25170	CEFBS_HasDSP, // MFLO_DSP = 2036	---
25171	CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2037	---	25171	CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2037	---
25172	CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2038	---	25172	CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2038	---
25173	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2039	---	25173	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2039	---
25174	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2040	---	25174	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2040	---
25175	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2041	---	25175	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2041	---
25176	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2042	---	25176	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2042	---
25177	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2043	---	25177	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2043	---
25178	CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2044	---	25178	CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2044	---
25179	CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2045	---	25179	CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2045	---
25180	CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2046	---	25180	CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2046	---
25181	CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2047	---	25181	CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2047	---
25182	CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2048	---	25182	CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2048	---
25183	CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2049	---	25183	CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2049	---
25184	CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2050	---	25184	CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2050	---
25185	CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2051	---	25185	CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2051	---
25186	CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2052	---	25186	CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2052	---
25187	CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2053	---	25187	CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2053	---
25188	CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2054	---	25188	CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2054	---
25189	CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2055	---	25189	CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2055	---
25190	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2056	---	25190	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2056	---
25191	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2057	---	25191	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2057	---
25192	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2058	---	25192	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2058	---
25193	CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2059	---	25193	CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2059	---
25194	CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2060	---	25194	CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2060	---
25195	CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2061	---	25195	CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2061	---
25196	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2062	---	25196	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2062	---
25197	CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2063	---	25197	CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2063	---
25198	CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2064	---	25198	CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2064	---
25199	CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2065	---	25199	CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2065	---
25200	CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2066	---	25200	CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2066	---
25201	CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2067	---	25201	CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2067	---
25202	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2068	---	25202	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2068	---
25203	CEFBS_HasDSP, // MODSUB = 2069	---	25203	CEFBS_HasDSP, // MODSUB = 2069	---
25204	CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2070	---	25204	CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2070	---
25205	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2071	---	25205	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2071	---
25206	CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2072	---	25206	CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2072	---
25207	CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2073	---	25207	CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2073	---
25208	CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2074	---	25208	CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2074	---
25209	CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2075	---	25209	CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2075	---
25210	CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2076	---	25210	CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2076	---
25211	CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2077	---	25211	CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2077	---
25212	CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2078	---	25212	CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2078	---
25213	CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2079	---	25213	CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2079	---
25214	CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2080	---	25214	CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2080	---
25215	CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2081	---	25215	CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2081	---
25216	CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2082	---	25216	CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2082	---
25217	CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2083	---	25217	CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2083	---
25218	CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2084	---	25218	CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2084	---
25219	CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2085	---	25219	CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2085	---
25220	CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2086	---	25220	CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2086	---
25221	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2087	---	25221	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2087	---
25222	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2088	---	25222	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2088	---
25223	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2089	---	25223	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2089	---
25224	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2090	---	25224	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2090	---
25225	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2091	---	25225	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2091	---
25226	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2092	---	25226	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2092	---
25227	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2093	---	25227	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2093	---
25228	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2094	---	25228	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2094	---
25229	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2095	---	25229	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2095	---
25230	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2096	---	25230	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2096	---
25231	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2097	---	25231	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2097	---
25232	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2098	---	25232	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2098	---
25233	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2099	---	25233	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2099	---
25234	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2100	---	25234	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2100	---
25235	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2101	---	25235	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2101	---
25236	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2102	---	25236	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2102	---
25237	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2103	---	25237	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2103	---
25238	CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2104	---	25238	CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2104	---
25239	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2105	---	25239	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2105	---
25240	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2106	---	25240	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2106	---
25241	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2107	---	25241	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2107	---
25242	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2108	---	25242	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2108	---
25243	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2109	---	25243	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2109	---
25244	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2110	---	25244	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2110	---
25245	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2111	---	25245	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2111	---
25246	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2112	---	25246	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2112	---
25247	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2113	---	25247	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2113	---
25248	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2114	---	25248	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2114	---
25249	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2115	---	25249	CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2115	---
25250	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2116	---	25250	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2116	---
25251	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2117	---	25251	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2117	---
25252	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2118	---	25252	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2118	---
25253	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2119	---	25253	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2119	---
25254	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2120	---	25254	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2120	---
25255	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2121	---	25255	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2121	---
25256	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2122	---	25256	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2122	---
25257	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2123	---	25257	CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2123	---
25258	CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2124	---	25258	CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2124	---
25259	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2125	---	25259	CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2125	---
25260	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2126	---	25260	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2126	---
25261	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2127	---	25261	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2127	---
25262	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2128	---	25262	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2128	---
25263	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2129	---	25263	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2129	---
25264	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2130	---	25264	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2130	---
25265	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2131	---	25265	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2131	---
25266	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2132	---	25266	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2132	---
25267	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2133	---	25267	CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2133	---
25268	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2134	---	25268	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2134	---
25269	CEFBS_HasDSP, // MSUBU_DSP = 2135	---	25269	CEFBS_HasDSP, // MSUBU_DSP = 2135	---
25270	CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2136	---	25270	CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2136	---
25271	CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2137	---	25271	CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2137	---
25272	CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2138	---	25272	CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2138	---
25273	CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2139	---	25273	CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2139	---
25274	CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2140	---	25274	CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2140	---
25275	CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2141	---	25275	CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2141	---
25276	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2142	---	25276	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2142	---
25277	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2143	---	25277	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2143	---
25278	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2144	---	25278	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2144	---
25279	CEFBS_HasDSP, // MSUB_DSP = 2145	---	25279	CEFBS_HasDSP, // MSUB_DSP = 2145	---
25280	CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2146	---	25280	CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2146	---
25281	CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2147	---	25281	CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2147	---
25282	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2148	---	25282	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2148	---
25283	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2149	---	25283	CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2149	---
25284	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2150	---	25284	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2150	---
25285	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2151	---	25285	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2151	---
25286	CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2152	---	25286	CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2152	---
25287	CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2153	---	25287	CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2153	---
25288	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2154	---	25288	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2154	---
25289	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2155	---	25289	CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2155	---
25290	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2156	---	25290	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2156	---
25291	CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2157	---	25291	CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2157	---
25292	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2158	---	25292	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2158	---
25293	CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2159	---	25293	CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2159	---
25294	CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2160	---	25294	CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2160	---
25295	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2161	---	25295	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2161	---
25296	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2162	---	25296	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2162	---
25297	CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2163	---	25297	CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2163	---
25298	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2164	---	25298	CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2164	---
25299	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2165	---	25299	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2165	---
25300	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2166	---	25300	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2166	---
25301	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2167	---	25301	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2167	---
25302	CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2168	---	25302	CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2168	---
25303	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2169	---	25303	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2169	---
25304	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2170	---	25304	CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2170	---
25305	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2171	---	25305	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2171	---
25306	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2172	---	25306	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2172	---
25307	CEFBS_HasDSP, // MTHI_DSP = 2173	---	25307	CEFBS_HasDSP, // MTHI_DSP = 2173	---
25308	CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2174	---	25308	CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2174	---
25309	CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2175	---	25309	CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2175	---
25310	CEFBS_HasDSP, // MTHLIP = 2176	---	25310	CEFBS_HasDSP, // MTHLIP = 2176	---
25311	CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2177	---	25311	CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2177	---
25312	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2178	---	25312	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2178	---
25313	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2179	---	25313	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2179	---
25314	CEFBS_HasDSP, // MTLO_DSP = 2180	---	25314	CEFBS_HasDSP, // MTLO_DSP = 2180	---
25315	CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2181	---	25315	CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2181	---
25316	CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2182	---	25316	CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2182	---
25317	CEFBS_HasCnMips, // MTM0 = 2183	---	25317	CEFBS_HasCnMips, // MTM0 = 2183	---
25318	CEFBS_HasCnMips, // MTM1 = 2184	---	25318	CEFBS_HasCnMips, // MTM1 = 2184	---
25319	CEFBS_HasCnMips, // MTM2 = 2185	---	25319	CEFBS_HasCnMips, // MTM2 = 2185	---
25320	CEFBS_HasCnMips, // MTP0 = 2186	---	25320	CEFBS_HasCnMips, // MTP0 = 2186	---
25321	CEFBS_HasCnMips, // MTP1 = 2187	---	25321	CEFBS_HasCnMips, // MTP1 = 2187	---
25322	CEFBS_HasCnMips, // MTP2 = 2188	---	25322	CEFBS_HasCnMips, // MTP2 = 2188	---
25323	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2189	---	25323	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2189	---
25324	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2190	---	25324	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2190	---
25325	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2191	---	25325	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2191	---
25326	CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2192	---	25326	CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2192	---
25327	CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2193	---	25327	CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2193	---
25328	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2194	---	25328	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2194	---
25329	CEFBS_HasDSP, // MULEQ_S_W_PHL = 2195	---	25329	CEFBS_HasDSP, // MULEQ_S_W_PHL = 2195	---
25330	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2196	---	25330	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2196	---
25331	CEFBS_HasDSP, // MULEQ_S_W_PHR = 2197	---	25331	CEFBS_HasDSP, // MULEQ_S_W_PHR = 2197	---
25332	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2198	---	25332	CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2198	---
25333	CEFBS_HasDSP, // MULEU_S_PH_QBL = 2199	---	25333	CEFBS_HasDSP, // MULEU_S_PH_QBL = 2199	---
25334	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2200	---	25334	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2200	---
25335	CEFBS_HasDSP, // MULEU_S_PH_QBR = 2201	---	25335	CEFBS_HasDSP, // MULEU_S_PH_QBR = 2201	---
25336	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2202	---	25336	CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2202	---
25337	CEFBS_HasDSP, // MULQ_RS_PH = 2203	---	25337	CEFBS_HasDSP, // MULQ_RS_PH = 2203	---
25338	CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2204	---	25338	CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2204	---
25339	CEFBS_HasDSPR2, // MULQ_RS_W = 2205	---	25339	CEFBS_HasDSPR2, // MULQ_RS_W = 2205	---
25340	CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2206	---	25340	CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2206	---
25341	CEFBS_HasDSPR2, // MULQ_S_PH = 2207	---	25341	CEFBS_HasDSPR2, // MULQ_S_PH = 2207	---
25342	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2208	---	25342	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2208	---
25343	CEFBS_HasDSPR2, // MULQ_S_W = 2209	---	25343	CEFBS_HasDSPR2, // MULQ_S_W = 2209	---
25344	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2210	---	25344	CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2210	---
25345	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2211	---	25345	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2211	---
25346	CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2212	---	25346	CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2212	---
25347	CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2213	---	25347	CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2213	---
25348	CEFBS_HasDSP, // MULSAQ_S_W_PH = 2214	---	25348	CEFBS_HasDSP, // MULSAQ_S_W_PH = 2214	---
25349	CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2215	---	25349	CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2215	---
25350	CEFBS_HasDSPR2, // MULSA_W_PH = 2216	---	25350	CEFBS_HasDSPR2, // MULSA_W_PH = 2216	---
25351	CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2217	---	25351	CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2217	---
25352	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2218	---	25352	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2218	---
25353	CEFBS_HasDSP, // MULTU_DSP = 2219	---	25353	CEFBS_HasDSP, // MULTU_DSP = 2219	---
25354	CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2220	---	25354	CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2220	---
25355	CEFBS_HasDSP, // MULT_DSP = 2221	---	25355	CEFBS_HasDSP, // MULT_DSP = 2221	---
25356	CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2222	---	25356	CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2222	---
25357	CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2223	---	25357	CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2223	---
25358	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2224	---	25358	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2224	---
25359	CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2225	---	25359	CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2225	---
25360	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2226	---	25360	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2226	---
25361	CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2227	---	25361	CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2227	---
25362	CEFBS_HasStdEnc_HasMSA, // MULV_B = 2228	---	25362	CEFBS_HasStdEnc_HasMSA, // MULV_B = 2228	---
25363	CEFBS_HasStdEnc_HasMSA, // MULV_D = 2229	---	25363	CEFBS_HasStdEnc_HasMSA, // MULV_D = 2229	---
25364	CEFBS_HasStdEnc_HasMSA, // MULV_H = 2230	---	25364	CEFBS_HasStdEnc_HasMSA, // MULV_H = 2230	---
25365	CEFBS_HasStdEnc_HasMSA, // MULV_W = 2231	---	25365	CEFBS_HasStdEnc_HasMSA, // MULV_W = 2231	---
25366	CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2232	---	25366	CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2232	---
25367	CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2233	---	25367	CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2233	---
25368	CEFBS_HasDSPR2, // MUL_PH = 2234	---	25368	CEFBS_HasDSPR2, // MUL_PH = 2234	---
25369	CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2235	---	25369	CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2235	---
25370	CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2236	---	25370	CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2236	---
25371	CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2237	---	25371	CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2237	---
25372	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2238	---	25372	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2238	---
25373	CEFBS_HasDSPR2, // MUL_S_PH = 2239	---	25373	CEFBS_HasDSPR2, // MUL_S_PH = 2239	---
25374	CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2240	---	25374	CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2240	---
25375	CEFBS_InMips16Mode, // Mfhi16 = 2241	---	25375	CEFBS_InMips16Mode, // Mfhi16 = 2241	---
25376	CEFBS_InMips16Mode, // Mflo16 = 2242	---	25376	CEFBS_InMips16Mode, // Mflo16 = 2242	---
25377	CEFBS_InMips16Mode, // Move32R16 = 2243	---	25377	CEFBS_InMips16Mode, // Move32R16 = 2243	---
25378	CEFBS_InMips16Mode, // MoveR3216 = 2244	---	25378	CEFBS_InMips16Mode, // MoveR3216 = 2244	---
25379	CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2245	---	25379	CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2245	---
25380	CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2246	---	25380	CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2246	---
25381	CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2247	---	25381	CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2247	---
25382	CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2248	---	25382	CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2248	---
25383	CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2249	---	25383	CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2249	---
25384	CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2250	---	25384	CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2250	---
25385	CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2251	---	25385	CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2251	---
25386	CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2252	---	25386	CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2252	---
25387	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2253	---	25387	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2253	---
25388	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2254	---	25388	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2254	---
25389	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2255	---	25389	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2255	---
25390	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2256	---	25390	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2256	---
25391	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2257	---	25391	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2257	---
25392	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2258	---	25392	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2258	---
25393	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2259	---	25393	CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2259	---
25394	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2260	---	25394	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2260	---
25395	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2261	---	25395	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2261	---
25396	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2262	---	25396	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2262	---
25397	CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2263	---	25397	CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2263	---
25398	CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2264	---	25398	CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2264	---
25399	CEFBS_HasStdEnc_HasMSA, // NORI_B = 2265	---	25399	CEFBS_HasStdEnc_HasMSA, // NORI_B = 2265	---
25400	CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2266	---	25400	CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2266	---
25401	CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2267	---	25401	CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2267	---
25402	CEFBS_HasStdEnc_HasMSA, // NOR_V = 2268	---	25402	CEFBS_HasStdEnc_HasMSA, // NOR_V = 2268	---
25403	CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2269	---	25403	CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2269	---
25404	CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2270	---	25404	CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2270	---
25405	CEFBS_InMips16Mode, // NegRxRy16 = 2271	---	25405	CEFBS_InMips16Mode, // NegRxRy16 = 2271	---
25406	CEFBS_InMips16Mode, // NotRxRy16 = 2272	---	25406	CEFBS_InMips16Mode, // NotRxRy16 = 2272	---
25407	CEFBS_HasStdEnc_NotInMicroMips, // OR = 2273	---	25407	CEFBS_HasStdEnc_NotInMicroMips, // OR = 2273	---
25408	CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2274	---	25408	CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2274	---
25409	CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2275	---	25409	CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2275	---
25410	CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2276	---	25410	CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2276	---
25411	CEFBS_HasStdEnc_HasMSA, // ORI_B = 2277	---	25411	CEFBS_HasStdEnc_HasMSA, // ORI_B = 2277	---
25412	CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2278	---	25412	CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2278	---
25413	CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2279	---	25413	CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2279	---
25414	CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2280	---	25414	CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2280	---
25415	CEFBS_HasStdEnc_HasMSA, // OR_V = 2281	---	25415	CEFBS_HasStdEnc_HasMSA, // OR_V = 2281	---
25416	CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2282	---	25416	CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2282	---
25417	CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2283	---	25417	CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2283	---
25418	CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2284	---	25418	CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2284	---
25419	CEFBS_InMips16Mode, // OrRxRxRy16 = 2285	---	25419	CEFBS_InMips16Mode, // OrRxRxRy16 = 2285	---
25420	CEFBS_HasDSP, // PACKRL_PH = 2286	---	25420	CEFBS_HasDSP, // PACKRL_PH = 2286	---
25421	CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2287	---	25421	CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2287	---
25422	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2288	---	25422	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2288	---
25423	CEFBS_InMicroMips, // PAUSE_MM = 2289	---	25423	CEFBS_InMicroMips, // PAUSE_MM = 2289	---
25424	CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2290	---	25424	CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2290	---
25425	CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2291	---	25425	CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2291	---
25426	CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2292	---	25426	CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2292	---
25427	CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2293	---	25427	CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2293	---
25428	CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2294	---	25428	CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2294	---
25429	CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2295	---	25429	CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2295	---
25430	CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2296	---	25430	CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2296	---
25431	CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2297	---	25431	CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2297	---
25432	CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2298	---	25432	CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2298	---
25433	CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2299	---	25433	CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2299	---
25434	CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2300	---	25434	CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2300	---
25435	CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2301	---	25435	CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2301	---
25436	CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2302	---	25436	CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2302	---
25437	CEFBS_HasDSP, // PICK_PH = 2303	---	25437	CEFBS_HasDSP, // PICK_PH = 2303	---
25438	CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2304	---	25438	CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2304	---
25439	CEFBS_HasDSP, // PICK_QB = 2305	---	25439	CEFBS_HasDSP, // PICK_QB = 2305	---
25440	CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2306	---	25440	CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2306	---
25441	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2307	---	25441	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2307	---
25442	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2308	---	25442	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2308	---
25443	CEFBS_HasCnMips, // POP = 2309	---	25443	CEFBS_HasCnMips, // POP = 2309	---
25444	CEFBS_HasDSP, // PRECEQU_PH_QBL = 2310	---	25444	CEFBS_HasDSP, // PRECEQU_PH_QBL = 2310	---
25445	CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2311	---	25445	CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2311	---
25446	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2312	---	25446	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2312	---
25447	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2313	---	25447	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2313	---
25448	CEFBS_HasDSP, // PRECEQU_PH_QBR = 2314	---	25448	CEFBS_HasDSP, // PRECEQU_PH_QBR = 2314	---
25449	CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2315	---	25449	CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2315	---
25450	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2316	---	25450	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2316	---
25451	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2317	---	25451	CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2317	---
25452	CEFBS_HasDSP, // PRECEQ_W_PHL = 2318	---	25452	CEFBS_HasDSP, // PRECEQ_W_PHL = 2318	---
25453	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2319	---	25453	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2319	---
25454	CEFBS_HasDSP, // PRECEQ_W_PHR = 2320	---	25454	CEFBS_HasDSP, // PRECEQ_W_PHR = 2320	---
25455	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2321	---	25455	CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2321	---
25456	CEFBS_HasDSP, // PRECEU_PH_QBL = 2322	---	25456	CEFBS_HasDSP, // PRECEU_PH_QBL = 2322	---
25457	CEFBS_HasDSP, // PRECEU_PH_QBLA = 2323	---	25457	CEFBS_HasDSP, // PRECEU_PH_QBLA = 2323	---
25458	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2324	---	25458	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2324	---
25459	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2325	---	25459	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2325	---
25460	CEFBS_HasDSP, // PRECEU_PH_QBR = 2326	---	25460	CEFBS_HasDSP, // PRECEU_PH_QBR = 2326	---
25461	CEFBS_HasDSP, // PRECEU_PH_QBRA = 2327	---	25461	CEFBS_HasDSP, // PRECEU_PH_QBRA = 2327	---
25462	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2328	---	25462	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2328	---
25463	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2329	---	25463	CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2329	---
25464	CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2330	---	25464	CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2330	---
25465	CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2331	---	25465	CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2331	---
25466	CEFBS_HasDSP, // PRECRQ_PH_W = 2332	---	25466	CEFBS_HasDSP, // PRECRQ_PH_W = 2332	---
25467	CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2333	---	25467	CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2333	---
25468	CEFBS_HasDSP, // PRECRQ_QB_PH = 2334	---	25468	CEFBS_HasDSP, // PRECRQ_QB_PH = 2334	---
25469	CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2335	---	25469	CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2335	---
25470	CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2336	---	25470	CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2336	---
25471	CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2337	---	25471	CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2337	---
25472	CEFBS_HasDSPR2, // PRECR_QB_PH = 2338	---	25472	CEFBS_HasDSPR2, // PRECR_QB_PH = 2338	---
25473	CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2339	---	25473	CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2339	---
25474	CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2340	---	25474	CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2340	---
25475	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2341	---	25475	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2341	---
25476	CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2342	---	25476	CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2342	---
25477	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2343	---	25477	CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2343	---
25478	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2344	---	25478	CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2344	---
25479	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2345	---	25479	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2345	---
25480	CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2346	---	25480	CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2346	---
25481	CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2347	---	25481	CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2347	---
25482	CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2348	---	25482	CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2348	---
25483	CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2349	---	25483	CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2349	---
25484	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2350	---	25484	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2350	---
25485	CEFBS_HasDSPR2, // PREPEND = 2351	---	25485	CEFBS_HasDSPR2, // PREPEND = 2351	---
25486	CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2352	---	25486	CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2352	---
25487	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2353	---	25487	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2353	---
25488	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2354	---	25488	CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2354	---
25489	CEFBS_HasDSP, // RADDU_W_QB = 2355	---	25489	CEFBS_HasDSP, // RADDU_W_QB = 2355	---
25490	CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2356	---	25490	CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2356	---
25491	CEFBS_HasDSP, // RDDSP = 2357	---	25491	CEFBS_HasDSP, // RDDSP = 2357	---
25492	CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2358	---	25492	CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2358	---
25493	CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2359	---	25493	CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2359	---
25494	CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2360	---	25494	CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2360	---
25495	CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2361	---	25495	CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2361	---
25496	CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2362	---	25496	CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2362	---
25497	CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2363	---	25497	CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2363	---
25498	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2364	---	25498	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2364	---
25499	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2365	---	25499	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2365	---
25500	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2366	---	25500	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2366	---
25501	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2367	---	25501	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2367	---
25502	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2368	---	25502	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2368	---
25503	CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2369	---	25503	CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2369	---
25504	CEFBS_HasDSP, // REPLV_PH = 2370	---	25504	CEFBS_HasDSP, // REPLV_PH = 2370	---
25505	CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2371	---	25505	CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2371	---
25506	CEFBS_HasDSP, // REPLV_QB = 2372	---	25506	CEFBS_HasDSP, // REPLV_QB = 2372	---
25507	CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2373	---	25507	CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2373	---
25508	CEFBS_HasDSP, // REPL_PH = 2374	---	25508	CEFBS_HasDSP, // REPL_PH = 2374	---
25509	CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2375	---	25509	CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2375	---
25510	CEFBS_HasDSP, // REPL_QB = 2376	---	25510	CEFBS_HasDSP, // REPL_QB = 2376	---
25511	CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2377	---	25511	CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2377	---
25512	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2378	---	25512	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2378	---
25513	CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2379	---	25513	CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2379	---
25514	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2380	---	25514	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2380	---
25515	CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2381	---	25515	CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2381	---
25516	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2382	---	25516	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2382	---
25517	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2383	---	25517	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2383	---
25518	CEFBS_InMicroMips, // ROTRV_MM = 2384	---	25518	CEFBS_InMicroMips, // ROTRV_MM = 2384	---
25519	CEFBS_InMicroMips, // ROTR_MM = 2385	---	25519	CEFBS_InMicroMips, // ROTR_MM = 2385	---
25520	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2386	---	25520	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2386	---
25521	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2387	---	25521	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2387	---
25522	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2388	---	25522	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2388	---
25523	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2389	---	25523	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2389	---
25524	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2390	---	25524	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2390	---
25525	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2391	---	25525	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2391	---
25526	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2392	---	25526	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2392	---
25527	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2393	---	25527	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2393	---
25528	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2394	---	25528	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2394	---
25529	CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2395	---	25529	CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2395	---
25530	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2396	---	25530	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2396	---
25531	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2397	---	25531	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2397	---
25532	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2398	---	25532	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2398	---
25533	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2399	---	25533	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2399	---
25534	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2400	---	25534	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2400	---
25535	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2401	---	25535	CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2401	---
25536	CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2402	---	25536	CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2402	---
25537	CEFBS_InMips16Mode, // Restore16 = 2403	---	25537	CEFBS_InMips16Mode, // Restore16 = 2403	---
25538	CEFBS_InMips16Mode, // RestoreX16 = 2404	---	25538	CEFBS_InMips16Mode, // RestoreX16 = 2404	---
25539	CEFBS_HasCnMipsP, // SAA = 2405	---	25539	CEFBS_HasCnMipsP, // SAA = 2405	---
25540	CEFBS_HasCnMipsP, // SAAD = 2406	---	25540	CEFBS_HasCnMipsP, // SAAD = 2406	---
25541	CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2407	---	25541	CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2407	---
25542	CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2408	---	25542	CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2408	---
25543	CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2409	---	25543	CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2409	---
25544	CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2410	---	25544	CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2410	---
25545	CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2411	---	25545	CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2411	---
25546	CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2412	---	25546	CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2412	---
25547	CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2413	---	25547	CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2413	---
25548	CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2414	---	25548	CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2414	---
25549	CEFBS_HasStdEnc_NotInMicroMips, // SB = 2415	---	25549	CEFBS_HasStdEnc_NotInMicroMips, // SB = 2415	---
25550	CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2416	---	25550	CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2416	---
25551	CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2417	---	25551	CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2417	---
25552	CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2418	---	25552	CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2418	---
25553	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2419	---	25553	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2419	---
25554	CEFBS_InMicroMips_HasEVA, // SBE_MM = 2420	---	25554	CEFBS_InMicroMips_HasEVA, // SBE_MM = 2420	---
25555	CEFBS_InMicroMips, // SB_MM = 2421	---	25555	CEFBS_InMicroMips, // SB_MM = 2421	---
25556	CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2422	---	25556	CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2422	---
25557	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2423	---	25557	CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2423	---
25558	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2424	---	25558	CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2424	---
25559	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2425	---	25559	CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2425	---
25560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2426	---	25560	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2426	---
25561	CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2427	---	25561	CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2427	---
25562	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2428	---	25562	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2428	---
25563	CEFBS_InMicroMips_HasEVA, // SCE_MM = 2429	---	25563	CEFBS_InMicroMips_HasEVA, // SCE_MM = 2429	---
25564	CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2430	---	25564	CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2430	---
25565	CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2431	---	25565	CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2431	---
25566	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2432	---	25566	CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2432	---
25567	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2433	---	25567	CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2433	---
25568	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2434	---	25568	CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2434	---
25569	CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2435	---	25569	CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2435	---
25570	CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2436	---	25570	CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2436	---
25571	CEFBS_InMicroMips, // SDBBP_MM = 2437	---	25571	CEFBS_InMicroMips, // SDBBP_MM = 2437	---
25572	CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2438	---	25572	CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2438	---
25573	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2439	---	25573	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2439	---
25574	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2440	---	25574	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2440	---
25575	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2441	---	25575	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2441	---
25576	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2442	---	25576	CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2442	---
25577	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2443	---	25577	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2443	---
25578	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2444	---	25578	CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2444	---
25579	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2445	---	25579	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2445	---
25580	CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2446	---	25580	CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2446	---
25581	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2447	---	25581	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2447	---
25582	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2448	---	25582	CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2448	---
25583	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2449	---	25583	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2449	---
25584	CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2450	---	25584	CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2450	---
25585	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2451	---	25585	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2451	---
25586	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2452	---	25586	CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2452	---
25587	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2453	---	25587	CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2453	---
25588	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2454	---	25588	CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2454	---
25589	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2455	---	25589	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2455	---
25590	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2456	---	25590	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2456	---
25591	CEFBS_InMicroMips, // SEB_MM = 2457	---	25591	CEFBS_InMicroMips, // SEB_MM = 2457	---
25592	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2458	---	25592	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2458	---
25593	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2459	---	25593	CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2459	---
25594	CEFBS_InMicroMips, // SEH_MM = 2460	---	25594	CEFBS_InMicroMips, // SEH_MM = 2460	---
25595	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2461	---	25595	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2461	---
25596	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2462	---	25596	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2462	---
25597	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2463	---	25597	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2463	---
25598	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2464	---	25598	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2464	---
25599	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2465	---	25599	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2465	---
25600	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2466	---	25600	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2466	---
25601	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2467	---	25601	CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2467	---
25602	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2468	---	25602	CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2468	---
25603	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2469	---	25603	CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2469	---
25604	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2470	---	25604	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2470	---
25605	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2471	---	25605	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2471	---
25606	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2472	---	25606	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2472	---
25607	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2473	---	25607	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2473	---
25608	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2474	---	25608	CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2474	---
25609	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2475	---	25609	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2475	---
25610	CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2476	---	25610	CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2476	---
25611	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2477	---	25611	CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2477	---
25612	CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2478	---	25612	CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2478	---
25613	CEFBS_HasCnMips, // SEQ = 2479	---	25613	CEFBS_HasCnMips, // SEQ = 2479	---
25614	CEFBS_HasCnMips, // SEQi = 2480	---	25614	CEFBS_HasCnMips, // SEQi = 2480	---
25615	CEFBS_HasStdEnc_NotInMicroMips, // SH = 2481	---	25615	CEFBS_HasStdEnc_NotInMicroMips, // SH = 2481	---
25616	CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2482	---	25616	CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2482	---
25617	CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2483	---	25617	CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2483	---
25618	CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2484	---	25618	CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2484	---
25619	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2485	---	25619	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2485	---
25620	CEFBS_InMicroMips_HasEVA, // SHE_MM = 2486	---	25620	CEFBS_InMicroMips_HasEVA, // SHE_MM = 2486	---
25621	CEFBS_HasStdEnc_HasMSA, // SHF_B = 2487	---	25621	CEFBS_HasStdEnc_HasMSA, // SHF_B = 2487	---
25622	CEFBS_HasStdEnc_HasMSA, // SHF_H = 2488	---	25622	CEFBS_HasStdEnc_HasMSA, // SHF_H = 2488	---
25623	CEFBS_HasStdEnc_HasMSA, // SHF_W = 2489	---	25623	CEFBS_HasStdEnc_HasMSA, // SHF_W = 2489	---
25624	CEFBS_HasDSP, // SHILO = 2490	---	25624	CEFBS_HasDSP, // SHILO = 2490	---
25625	CEFBS_HasDSP, // SHILOV = 2491	---	25625	CEFBS_HasDSP, // SHILOV = 2491	---
25626	CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2492	---	25626	CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2492	---
25627	CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2493	---	25627	CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2493	---
25628	CEFBS_HasDSP, // SHLLV_PH = 2494	---	25628	CEFBS_HasDSP, // SHLLV_PH = 2494	---
25629	CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2495	---	25629	CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2495	---
25630	CEFBS_HasDSP, // SHLLV_QB = 2496	---	25630	CEFBS_HasDSP, // SHLLV_QB = 2496	---
25631	CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2497	---	25631	CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2497	---
25632	CEFBS_HasDSP, // SHLLV_S_PH = 2498	---	25632	CEFBS_HasDSP, // SHLLV_S_PH = 2498	---
25633	CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2499	---	25633	CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2499	---
25634	CEFBS_HasDSP, // SHLLV_S_W = 2500	---	25634	CEFBS_HasDSP, // SHLLV_S_W = 2500	---
25635	CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2501	---	25635	CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2501	---
25636	CEFBS_HasDSP, // SHLL_PH = 2502	---	25636	CEFBS_HasDSP, // SHLL_PH = 2502	---
25637	CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2503	---	25637	CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2503	---
25638	CEFBS_HasDSP, // SHLL_QB = 2504	---	25638	CEFBS_HasDSP, // SHLL_QB = 2504	---
25639	CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2505	---	25639	CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2505	---
25640	CEFBS_HasDSP, // SHLL_S_PH = 2506	---	25640	CEFBS_HasDSP, // SHLL_S_PH = 2506	---
25641	CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2507	---	25641	CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2507	---
25642	CEFBS_HasDSP, // SHLL_S_W = 2508	---	25642	CEFBS_HasDSP, // SHLL_S_W = 2508	---
25643	CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2509	---	25643	CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2509	---
25644	CEFBS_HasDSP, // SHRAV_PH = 2510	---	25644	CEFBS_HasDSP, // SHRAV_PH = 2510	---
25645	CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2511	---	25645	CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2511	---
25646	CEFBS_HasDSPR2, // SHRAV_QB = 2512	---	25646	CEFBS_HasDSPR2, // SHRAV_QB = 2512	---
25647	CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2513	---	25647	CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2513	---
25648	CEFBS_HasDSP, // SHRAV_R_PH = 2514	---	25648	CEFBS_HasDSP, // SHRAV_R_PH = 2514	---
25649	CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2515	---	25649	CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2515	---
25650	CEFBS_HasDSPR2, // SHRAV_R_QB = 2516	---	25650	CEFBS_HasDSPR2, // SHRAV_R_QB = 2516	---
25651	CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2517	---	25651	CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2517	---
25652	CEFBS_HasDSP, // SHRAV_R_W = 2518	---	25652	CEFBS_HasDSP, // SHRAV_R_W = 2518	---
25653	CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2519	---	25653	CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2519	---
25654	CEFBS_HasDSP, // SHRA_PH = 2520	---	25654	CEFBS_HasDSP, // SHRA_PH = 2520	---
25655	CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2521	---	25655	CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2521	---
25656	CEFBS_HasDSPR2, // SHRA_QB = 2522	---	25656	CEFBS_HasDSPR2, // SHRA_QB = 2522	---
25657	CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2523	---	25657	CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2523	---
25658	CEFBS_HasDSP, // SHRA_R_PH = 2524	---	25658	CEFBS_HasDSP, // SHRA_R_PH = 2524	---
25659	CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2525	---	25659	CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2525	---
25660	CEFBS_HasDSPR2, // SHRA_R_QB = 2526	---	25660	CEFBS_HasDSPR2, // SHRA_R_QB = 2526	---
25661	CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2527	---	25661	CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2527	---
25662	CEFBS_HasDSP, // SHRA_R_W = 2528	---	25662	CEFBS_HasDSP, // SHRA_R_W = 2528	---
25663	CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2529	---	25663	CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2529	---
25664	CEFBS_HasDSPR2, // SHRLV_PH = 2530	---	25664	CEFBS_HasDSPR2, // SHRLV_PH = 2530	---
25665	CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2531	---	25665	CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2531	---
25666	CEFBS_HasDSP, // SHRLV_QB = 2532	---	25666	CEFBS_HasDSP, // SHRLV_QB = 2532	---
25667	CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2533	---	25667	CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2533	---
25668	CEFBS_HasDSPR2, // SHRL_PH = 2534	---	25668	CEFBS_HasDSPR2, // SHRL_PH = 2534	---
25669	CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2535	---	25669	CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2535	---
25670	CEFBS_HasDSP, // SHRL_QB = 2536	---	25670	CEFBS_HasDSP, // SHRL_QB = 2536	---
25671	CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2537	---	25671	CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2537	---
25672	CEFBS_InMicroMips, // SH_MM = 2538	---	25672	CEFBS_InMicroMips, // SH_MM = 2538	---
25673	CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2539	---	25673	CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2539	---
25674	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2540	---	25674	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2540	---
25675	CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2541	---	25675	CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2541	---
25676	CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2542	---	25676	CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2542	---
25677	CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2543	---	25677	CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2543	---
25678	CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2544	---	25678	CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2544	---
25679	CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2545	---	25679	CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2545	---
25680	CEFBS_HasStdEnc_HasMSA, // SLD_B = 2546	---	25680	CEFBS_HasStdEnc_HasMSA, // SLD_B = 2546	---
25681	CEFBS_HasStdEnc_HasMSA, // SLD_D = 2547	---	25681	CEFBS_HasStdEnc_HasMSA, // SLD_D = 2547	---
25682	CEFBS_HasStdEnc_HasMSA, // SLD_H = 2548	---	25682	CEFBS_HasStdEnc_HasMSA, // SLD_H = 2548	---
25683	CEFBS_HasStdEnc_HasMSA, // SLD_W = 2549	---	25683	CEFBS_HasStdEnc_HasMSA, // SLD_W = 2549	---
25684	CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2550	---	25684	CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2550	---
25685	CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2551	---	25685	CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2551	---
25686	CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2552	---	25686	CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2552	---
25687	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2553	---	25687	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2553	---
25688	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2554	---	25688	CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2554	---
25689	CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2555	---	25689	CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2555	---
25690	CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2556	---	25690	CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2556	---
25691	CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2557	---	25691	CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2557	---
25692	CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2558	---	25692	CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2558	---
25693	CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2559	---	25693	CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2559	---
25694	CEFBS_InMicroMips, // SLLV_MM = 2560	---	25694	CEFBS_InMicroMips, // SLLV_MM = 2560	---
25695	CEFBS_HasStdEnc_HasMSA, // SLL_B = 2561	---	25695	CEFBS_HasStdEnc_HasMSA, // SLL_B = 2561	---
25696	CEFBS_HasStdEnc_HasMSA, // SLL_D = 2562	---	25696	CEFBS_HasStdEnc_HasMSA, // SLL_D = 2562	---
25697	CEFBS_HasStdEnc_HasMSA, // SLL_H = 2563	---	25697	CEFBS_HasStdEnc_HasMSA, // SLL_H = 2563	---
25698	CEFBS_InMicroMips, // SLL_MM = 2564	---	25698	CEFBS_InMicroMips, // SLL_MM = 2564	---
25699	CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2565	---	25699	CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2565	---
25700	CEFBS_HasStdEnc_HasMSA, // SLL_W = 2566	---	25700	CEFBS_HasStdEnc_HasMSA, // SLL_W = 2566	---
25701	CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2567	---	25701	CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2567	---
25702	CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2568	---	25702	CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2568	---
25703	CEFBS_InMicroMips, // SLT_MM = 2569	---	25703	CEFBS_InMicroMips, // SLT_MM = 2569	---
25704	CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2570	---	25704	CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2570	---
25705	CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2571	---	25705	CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2571	---
25706	CEFBS_InMicroMips, // SLTi_MM = 2572	---	25706	CEFBS_InMicroMips, // SLTi_MM = 2572	---
25707	CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2573	---	25707	CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2573	---
25708	CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2574	---	25708	CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2574	---
25709	CEFBS_InMicroMips, // SLTiu_MM = 2575	---	25709	CEFBS_InMicroMips, // SLTiu_MM = 2575	---
25710	CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2576	---	25710	CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2576	---
25711	CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2577	---	25711	CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2577	---
25712	CEFBS_InMicroMips, // SLTu_MM = 2578	---	25712	CEFBS_InMicroMips, // SLTu_MM = 2578	---
25713	CEFBS_HasCnMips, // SNE = 2579	---	25713	CEFBS_HasCnMips, // SNE = 2579	---
25714	CEFBS_HasCnMips, // SNEi = 2580	---	25714	CEFBS_HasCnMips, // SNEi = 2580	---
25715	CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2581	---	25715	CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2581	---
25716	CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2582	---	25716	CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2582	---
25717	CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2583	---	25717	CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2583	---
25718	CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2584	---	25718	CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2584	---
25719	CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2585	---	25719	CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2585	---
25720	CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2586	---	25720	CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2586	---
25721	CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2587	---	25721	CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2587	---
25722	CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2588	---	25722	CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2588	---
25723	CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2589	---	25723	CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2589	---
25724	CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2590	---	25724	CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2590	---
25725	CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2591	---	25725	CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2591	---
25726	CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2592	---	25726	CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2592	---
25727	CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2593	---	25727	CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2593	---
25728	CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2594	---	25728	CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2594	---
25729	CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2595	---	25729	CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2595	---
25730	CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2596	---	25730	CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2596	---
25731	CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2597	---	25731	CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2597	---
25732	CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2598	---	25732	CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2598	---
25733	CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2599	---	25733	CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2599	---
25734	CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2600	---	25734	CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2600	---
25735	CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2601	---	25735	CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2601	---
25736	CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2602	---	25736	CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2602	---
25737	CEFBS_InMicroMips, // SRAV_MM = 2603	---	25737	CEFBS_InMicroMips, // SRAV_MM = 2603	---
25738	CEFBS_HasStdEnc_HasMSA, // SRA_B = 2604	---	25738	CEFBS_HasStdEnc_HasMSA, // SRA_B = 2604	---
25739	CEFBS_HasStdEnc_HasMSA, // SRA_D = 2605	---	25739	CEFBS_HasStdEnc_HasMSA, // SRA_D = 2605	---
25740	CEFBS_HasStdEnc_HasMSA, // SRA_H = 2606	---	25740	CEFBS_HasStdEnc_HasMSA, // SRA_H = 2606	---
25741	CEFBS_InMicroMips, // SRA_MM = 2607	---	25741	CEFBS_InMicroMips, // SRA_MM = 2607	---
25742	CEFBS_HasStdEnc_HasMSA, // SRA_W = 2608	---	25742	CEFBS_HasStdEnc_HasMSA, // SRA_W = 2608	---
25743	CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2609	---	25743	CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2609	---
25744	CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2610	---	25744	CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2610	---
25745	CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2611	---	25745	CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2611	---
25746	CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2612	---	25746	CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2612	---
25747	CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2613	---	25747	CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2613	---
25748	CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2614	---	25748	CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2614	---
25749	CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2615	---	25749	CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2615	---
25750	CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2616	---	25750	CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2616	---
25751	CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2617	---	25751	CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2617	---
25752	CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2618	---	25752	CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2618	---
25753	CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2619	---	25753	CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2619	---
25754	CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2620	---	25754	CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2620	---
25755	CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2621	---	25755	CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2621	---
25756	CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2622	---	25756	CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2622	---
25757	CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2623	---	25757	CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2623	---
25758	CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2624	---	25758	CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2624	---
25759	CEFBS_InMicroMips, // SRLV_MM = 2625	---	25759	CEFBS_InMicroMips, // SRLV_MM = 2625	---
25760	CEFBS_HasStdEnc_HasMSA, // SRL_B = 2626	---	25760	CEFBS_HasStdEnc_HasMSA, // SRL_B = 2626	---
25761	CEFBS_HasStdEnc_HasMSA, // SRL_D = 2627	---	25761	CEFBS_HasStdEnc_HasMSA, // SRL_D = 2627	---
25762	CEFBS_HasStdEnc_HasMSA, // SRL_H = 2628	---	25762	CEFBS_HasStdEnc_HasMSA, // SRL_H = 2628	---
25763	CEFBS_InMicroMips, // SRL_MM = 2629	---	25763	CEFBS_InMicroMips, // SRL_MM = 2629	---
25764	CEFBS_HasStdEnc_HasMSA, // SRL_W = 2630	---	25764	CEFBS_HasStdEnc_HasMSA, // SRL_W = 2630	---
25765	CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2631	---	25765	CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2631	---
25766	CEFBS_InMicroMips, // SSNOP_MM = 2632	---	25766	CEFBS_InMicroMips, // SSNOP_MM = 2632	---
25767	CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2633	---	25767	CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2633	---
25768	CEFBS_HasStdEnc_HasMSA, // ST_B = 2634	---	25768	CEFBS_HasStdEnc_HasMSA, // ST_B = 2634	---
25769	CEFBS_HasStdEnc_HasMSA, // ST_D = 2635	---	25769	CEFBS_HasStdEnc_HasMSA, // ST_D = 2635	---
25770	CEFBS_HasStdEnc_HasMSA, // ST_H = 2636	---	25770	CEFBS_HasStdEnc_HasMSA, // ST_H = 2636	---
25771	CEFBS_HasStdEnc_HasMSA, // ST_W = 2637	---	25771	CEFBS_HasStdEnc_HasMSA, // ST_W = 2637	---
25772	CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2638	---	25772	CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2638	---
25773	CEFBS_HasDSPR2, // SUBQH_PH = 2639	---	25773	CEFBS_HasDSPR2, // SUBQH_PH = 2639	---
25774	CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2640	---	25774	CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2640	---
25775	CEFBS_HasDSPR2, // SUBQH_R_PH = 2641	---	25775	CEFBS_HasDSPR2, // SUBQH_R_PH = 2641	---
25776	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2642	---	25776	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2642	---
25777	CEFBS_HasDSPR2, // SUBQH_R_W = 2643	---	25777	CEFBS_HasDSPR2, // SUBQH_R_W = 2643	---
25778	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2644	---	25778	CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2644	---
25779	CEFBS_HasDSPR2, // SUBQH_W = 2645	---	25779	CEFBS_HasDSPR2, // SUBQH_W = 2645	---
25780	CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2646	---	25780	CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2646	---
25781	CEFBS_HasDSP, // SUBQ_PH = 2647	---	25781	CEFBS_HasDSP, // SUBQ_PH = 2647	---
25782	CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2648	---	25782	CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2648	---
25783	CEFBS_HasDSP, // SUBQ_S_PH = 2649	---	25783	CEFBS_HasDSP, // SUBQ_S_PH = 2649	---
25784	CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2650	---	25784	CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2650	---
25785	CEFBS_HasDSP, // SUBQ_S_W = 2651	---	25785	CEFBS_HasDSP, // SUBQ_S_W = 2651	---
25786	CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2652	---	25786	CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2652	---
25787	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2653	---	25787	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2653	---
25788	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2654	---	25788	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2654	---
25789	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2655	---	25789	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2655	---
25790	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2656	---	25790	CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2656	---
25791	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2657	---	25791	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2657	---
25792	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2658	---	25792	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2658	---
25793	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2659	---	25793	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2659	---
25794	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2660	---	25794	CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2660	---
25795	CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2661	---	25795	CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2661	---
25796	CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2662	---	25796	CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2662	---
25797	CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2663	---	25797	CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2663	---
25798	CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2664	---	25798	CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2664	---
25799	CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2665	---	25799	CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2665	---
25800	CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2666	---	25800	CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2666	---
25801	CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2667	---	25801	CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2667	---
25802	CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2668	---	25802	CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2668	---
25803	CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2669	---	25803	CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2669	---
25804	CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2670	---	25804	CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2670	---
25805	CEFBS_HasDSPR2, // SUBUH_QB = 2671	---	25805	CEFBS_HasDSPR2, // SUBUH_QB = 2671	---
25806	CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2672	---	25806	CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2672	---
25807	CEFBS_HasDSPR2, // SUBUH_R_QB = 2673	---	25807	CEFBS_HasDSPR2, // SUBUH_R_QB = 2673	---
25808	CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2674	---	25808	CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2674	---
25809	CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2675	---	25809	CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2675	---
25810	CEFBS_HasDSPR2, // SUBU_PH = 2676	---	25810	CEFBS_HasDSPR2, // SUBU_PH = 2676	---
25811	CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2677	---	25811	CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2677	---
25812	CEFBS_HasDSP, // SUBU_QB = 2678	---	25812	CEFBS_HasDSP, // SUBU_QB = 2678	---
25813	CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2679	---	25813	CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2679	---
25814	CEFBS_HasDSPR2, // SUBU_S_PH = 2680	---	25814	CEFBS_HasDSPR2, // SUBU_S_PH = 2680	---
25815	CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2681	---	25815	CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2681	---
25816	CEFBS_HasDSP, // SUBU_S_QB = 2682	---	25816	CEFBS_HasDSP, // SUBU_S_QB = 2682	---
25817	CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2683	---	25817	CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2683	---
25818	CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2684	---	25818	CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2684	---
25819	CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2685	---	25819	CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2685	---
25820	CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2686	---	25820	CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2686	---
25821	CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2687	---	25821	CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2687	---
25822	CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2688	---	25822	CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2688	---
25823	CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2689	---	25823	CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2689	---
25824	CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2690	---	25824	CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2690	---
25825	CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2691	---	25825	CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2691	---
25826	CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2692	---	25826	CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2692	---
25827	CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2693	---	25827	CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2693	---
25828	CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2694	---	25828	CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2694	---
25829	CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2695	---	25829	CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2695	---
25830	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2696	---	25830	CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2696	---
25831	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2697	---	25831	CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2697	---
25832	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2698	---	25832	CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2698	---
25833	CEFBS_HasStdEnc_NotInMicroMips, // SW = 2699	---	25833	CEFBS_HasStdEnc_NotInMicroMips, // SW = 2699	---
25834	CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2700	---	25834	CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2700	---
25835	CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2701	---	25835	CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2701	---
25836	CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2702	---	25836	CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2702	---
25837	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2703	---	25837	CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2703	---
25838	CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2704	---	25838	CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2704	---
25839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2705	---	25839	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2705	---
25840	CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2706	---	25840	CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2706	---
25841	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2707	---	25841	CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2707	---
25842	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2708	---	25842	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2708	---
25843	CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2709	---	25843	CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2709	---
25844	CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2710	---	25844	CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2710	---
25845	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2711	---	25845	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2711	---
25846	CEFBS_InMicroMips_HasEVA, // SWE_MM = 2712	---	25846	CEFBS_InMicroMips_HasEVA, // SWE_MM = 2712	---
25847	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2713	---	25847	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2713	---
25848	CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2714	---	25848	CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2714	---
25849	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2715	---	25849	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2715	---
25850	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2716	---	25850	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2716	---
25851	CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2717	---	25851	CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2717	---
25852	CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2718	---	25852	CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2718	---
25853	CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2719	---	25853	CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2719	---
25854	CEFBS_InMicroMips, // SWM32_MM = 2720	---	25854	CEFBS_InMicroMips, // SWM32_MM = 2720	---
25855	CEFBS_InMicroMips, // SWP_MM = 2721	---	25855	CEFBS_InMicroMips, // SWP_MM = 2721	---
25856	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2722	---	25856	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2722	---
25857	CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2723	---	25857	CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2723	---
25858	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2724	---	25858	CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2724	---
25859	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2725	---	25859	CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2725	---
25860	CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2726	---	25860	CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2726	---
25861	CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2727	---	25861	CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2727	---
25862	CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2728	---	25862	CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2728	---
25863	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2729	---	25863	CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2729	---
25864	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2730	---	25864	CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2730	---
25865	CEFBS_InMicroMips, // SW_MM = 2731	---	25865	CEFBS_InMicroMips, // SW_MM = 2731	---
25866	CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2732	---	25866	CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2732	---
25867	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2733	---	25867	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2733	---
25868	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2734	---	25868	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2734	---
25869	CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2735	---	25869	CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2735	---
25870	CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2736	---	25870	CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2736	---
25871	CEFBS_InMicroMips, // SYNC_MM = 2737	---	25871	CEFBS_InMicroMips, // SYNC_MM = 2737	---
25872	CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2738	---	25872	CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2738	---
25873	CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2739	---	25873	CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2739	---
25874	CEFBS_InMicroMips, // SYSCALL_MM = 2740	---	25874	CEFBS_InMicroMips, // SYSCALL_MM = 2740	---
25875	CEFBS_InMips16Mode, // Save16 = 2741	---	25875	CEFBS_InMips16Mode, // Save16 = 2741	---
25876	CEFBS_InMips16Mode, // SaveX16 = 2742	---	25876	CEFBS_InMips16Mode, // SaveX16 = 2742	---
25877	CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2743	---	25877	CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2743	---
25878	CEFBS_InMips16Mode, // SebRx16 = 2744	---	25878	CEFBS_InMips16Mode, // SebRx16 = 2744	---
25879	CEFBS_InMips16Mode, // SehRx16 = 2745	---	25879	CEFBS_InMips16Mode, // SehRx16 = 2745	---
25880	CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2746	---	25880	CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2746	---
25881	CEFBS_InMips16Mode, // SllX16 = 2747	---	25881	CEFBS_InMips16Mode, // SllX16 = 2747	---
25882	CEFBS_InMips16Mode, // SllvRxRy16 = 2748	---	25882	CEFBS_InMips16Mode, // SllvRxRy16 = 2748	---
25883	CEFBS_InMips16Mode, // SltRxRy16 = 2749	---	25883	CEFBS_InMips16Mode, // SltRxRy16 = 2749	---
25884	CEFBS_InMips16Mode, // SltiRxImm16 = 2750	---	25884	CEFBS_InMips16Mode, // SltiRxImm16 = 2750	---
25885	CEFBS_InMips16Mode, // SltiRxImmX16 = 2751	---	25885	CEFBS_InMips16Mode, // SltiRxImmX16 = 2751	---
25886	CEFBS_InMips16Mode, // SltiuRxImm16 = 2752	---	25886	CEFBS_InMips16Mode, // SltiuRxImm16 = 2752	---
25887	CEFBS_InMips16Mode, // SltiuRxImmX16 = 2753	---	25887	CEFBS_InMips16Mode, // SltiuRxImmX16 = 2753	---
25888	CEFBS_InMips16Mode, // SltuRxRy16 = 2754	---	25888	CEFBS_InMips16Mode, // SltuRxRy16 = 2754	---
25889	CEFBS_InMips16Mode, // SraX16 = 2755	---	25889	CEFBS_InMips16Mode, // SraX16 = 2755	---
25890	CEFBS_InMips16Mode, // SravRxRy16 = 2756	---	25890	CEFBS_InMips16Mode, // SravRxRy16 = 2756	---
25891	CEFBS_InMips16Mode, // SrlX16 = 2757	---	25891	CEFBS_InMips16Mode, // SrlX16 = 2757	---
25892	CEFBS_InMips16Mode, // SrlvRxRy16 = 2758	---	25892	CEFBS_InMips16Mode, // SrlvRxRy16 = 2758	---
25893	CEFBS_InMips16Mode, // SubuRxRyRz16 = 2759	---	25893	CEFBS_InMips16Mode, // SubuRxRyRz16 = 2759	---
25894	CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2760	---	25894	CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2760	---
25895	CEFBS_InMips16Mode, // SwRxSpImmX16 = 2761	---	25895	CEFBS_InMips16Mode, // SwRxSpImmX16 = 2761	---
25896	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2762	---	25896	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2762	---
25897	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2763	---	25897	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2763	---
25898	CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2764	---	25898	CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2764	---
25899	CEFBS_InMicroMips, // TEQ_MM = 2765	---	25899	CEFBS_InMicroMips, // TEQ_MM = 2765	---
25900	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2766	---	25900	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2766	---
25901	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2767	---	25901	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2767	---
25902	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2768	---	25902	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2768	---
25903	CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2769	---	25903	CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2769	---
25904	CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2770	---	25904	CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2770	---
25905	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2771	---	25905	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2771	---
25906	CEFBS_InMicroMips, // TGEU_MM = 2772	---	25906	CEFBS_InMicroMips, // TGEU_MM = 2772	---
25907	CEFBS_InMicroMips, // TGE_MM = 2773	---	25907	CEFBS_InMicroMips, // TGE_MM = 2773	---
25908	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2774	---	25908	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2774	---
25909	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2775	---	25909	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2775	---
25910	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2776	---	25910	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2776	---
25911	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2777	---	25911	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2777	---
25912	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2778	---	25912	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2778	---
25913	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2779	---	25913	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2779	---
25914	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2780	---	25914	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2780	---
25915	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2781	---	25915	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2781	---
25916	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2782	---	25916	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2782	---
25917	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2783	---	25917	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2783	---
25918	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2784	---	25918	CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2784	---
25919	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2785	---	25919	CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2785	---
25920	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2786	---	25920	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2786	---
25921	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2787	---	25921	CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2787	---
25922	CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2788	---	25922	CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2788	---
25923	CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2789	---	25923	CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2789	---
25924	CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2790	---	25924	CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2790	---
25925	CEFBS_InMicroMips, // TLBP_MM = 2791	---	25925	CEFBS_InMicroMips, // TLBP_MM = 2791	---
25926	CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2792	---	25926	CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2792	---
25927	CEFBS_InMicroMips, // TLBR_MM = 2793	---	25927	CEFBS_InMicroMips, // TLBR_MM = 2793	---
25928	CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2794	---	25928	CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2794	---
25929	CEFBS_InMicroMips, // TLBWI_MM = 2795	---	25929	CEFBS_InMicroMips, // TLBWI_MM = 2795	---
25930	CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2796	---	25930	CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2796	---
25931	CEFBS_InMicroMips, // TLBWR_MM = 2797	---	25931	CEFBS_InMicroMips, // TLBWR_MM = 2797	---
25932	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2798	---	25932	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2798	---
25933	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2799	---	25933	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2799	---
25934	CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2800	---	25934	CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2800	---
25935	CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2801	---	25935	CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2801	---
25936	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2802	---	25936	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2802	---
25937	CEFBS_InMicroMips, // TLTU_MM = 2803	---	25937	CEFBS_InMicroMips, // TLTU_MM = 2803	---
25938	CEFBS_InMicroMips, // TLT_MM = 2804	---	25938	CEFBS_InMicroMips, // TLT_MM = 2804	---
25939	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2805	---	25939	CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2805	---
25940	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2806	---	25940	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2806	---
25941	CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2807	---	25941	CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2807	---
25942	CEFBS_InMicroMips, // TNE_MM = 2808	---	25942	CEFBS_InMicroMips, // TNE_MM = 2808	---
25943	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2809	---	25943	CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2809	---
25944	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2810	---	25944	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2810	---
25945	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2811	---	25945	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2811	---
25946	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2812	---	25946	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2812	---
25947	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2813	---	25947	CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2813	---
25948	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2814	---	25948	CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2814	---
25949	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2815	---	25949	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2815	---
25950	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2816	---	25950	CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2816	---
25951	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2817	---	25951	CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2817	---
25952	CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2818	---	25952	CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2818	---
25953	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2819	---	25953	CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2819	---
25954	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2820	---	25954	CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2820	---
25955	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2821	---	25955	CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2821	---
25956	CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2822	---	25956	CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2822	---
25957	CEFBS_HasCnMips, // V3MULU = 2823	---	25957	CEFBS_HasCnMips, // V3MULU = 2823	---
25958	CEFBS_HasCnMips, // VMM0 = 2824	---	25958	CEFBS_HasCnMips, // VMM0 = 2824	---
25959	CEFBS_HasCnMips, // VMULU = 2825	---	25959	CEFBS_HasCnMips, // VMULU = 2825	---
25960	CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2826	---	25960	CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2826	---
25961	CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2827	---	25961	CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2827	---
25962	CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2828	---	25962	CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2828	---
25963	CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2829	---	25963	CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2829	---
25964	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2830	---	25964	CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2830	---
25965	CEFBS_InMicroMips, // WAIT_MM = 2831	---	25965	CEFBS_InMicroMips, // WAIT_MM = 2831	---
25966	CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2832	---	25966	CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2832	---
25967	CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2833	---	25967	CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2833	---
25968	CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2834	---	25968	CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2834	---
25969	CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2835	---	25969	CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2835	---
25970	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2836	---	25970	CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2836	---
25971	CEFBS_InMicroMips, // WSBH_MM = 2837	---	25971	CEFBS_InMicroMips, // WSBH_MM = 2837	---
25972	CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2838	---	25972	CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2838	---
25973	CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2839	---	25973	CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2839	---
25974	CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2840	---	25974	CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2840	---
25975	CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2841	---	25975	CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2841	---
25976	CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2842	---	25976	CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2842	---
25977	CEFBS_HasStdEnc_HasMSA, // XORI_B = 2843	---	25977	CEFBS_HasStdEnc_HasMSA, // XORI_B = 2843	---
25978	CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2844	---	25978	CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2844	---
25979	CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2845	---	25979	CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2845	---
25980	CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2846	---	25980	CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2846	---
25981	CEFBS_HasStdEnc_HasMSA, // XOR_V = 2847	---	25981	CEFBS_HasStdEnc_HasMSA, // XOR_V = 2847	---
25982	CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2848	---	25982	CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2848	---
25983	CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2849	---	25983	CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2849	---
25984	CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2850	---	25984	CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2850	---
25985	CEFBS_InMips16Mode, // XorRxRxRy16 = 2851	---	25985	CEFBS_InMips16Mode, // XorRxRxRy16 = 2851	---
25986	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2852	---	25986	CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2852	---
25987	};	---	25987	};	---
25988		---	25988		---
25989	assert(Opcode < 2853);	0	25989	assert(Opcode < 2853);	0
25990	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];	0	25990	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];	0
25991	}	---	25991	}	---
25992		---	25992		---
25993	} // end namespace Mips_MC	---	25993	} // end namespace Mips_MC	---
25994	} // end namespace llvm	---	25994	} // end namespace llvm	---
25995	#endif // GET_COMPUTE_FEATURES	---	25995	#endif // GET_COMPUTE_FEATURES	---
25996		---	25996		---
25997	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER	---	25997	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER	---
25998	#undef ENABLE_INSTR_PREDICATE_VERIFIER	---	25998	#undef ENABLE_INSTR_PREDICATE_VERIFIER	---
25999	#include	---	25999	#include	---
26000		---	26000		---
26001	namespace llvm {	---	26001	namespace llvm {	---
26002	namespace Mips_MC {	---	26002	namespace Mips_MC {	---
26003		---	26003		---
26004	#ifndef NDEBUG	---	26004	#ifndef NDEBUG	---
26005	static const char *SubtargetFeatureNames[] = {	---	26005	static const char *SubtargetFeatureNames[] = {	---
26006	"Feature_HasCRC",	---	26006	"Feature_HasCRC",	---
26007	"Feature_HasCnMips",	---	26007	"Feature_HasCnMips",	---
26008	"Feature_HasCnMipsP",	---	26008	"Feature_HasCnMipsP",	---
26009	"Feature_HasDSP",	---	26009	"Feature_HasDSP",	---
26010	"Feature_HasDSPR2",	---	26010	"Feature_HasDSPR2",	---
26011	"Feature_HasDSPR3",	---	26011	"Feature_HasDSPR3",	---
26012	"Feature_HasEVA",	---	26012	"Feature_HasEVA",	---
26013	"Feature_HasGINV",	---	26013	"Feature_HasGINV",	---
26014	"Feature_HasMSA",	---	26014	"Feature_HasMSA",	---
26015	"Feature_HasMT",	---	26015	"Feature_HasMT",	---
26016	"Feature_HasMadd4",	---	26016	"Feature_HasMadd4",	---
26017	"Feature_HasMips2",	---	26017	"Feature_HasMips2",	---
26018	"Feature_HasMips3",	---	26018	"Feature_HasMips3",	---
26019	"Feature_HasMips3D",	---	26019	"Feature_HasMips3D",	---
26020	"Feature_HasMips3_32",	---	26020	"Feature_HasMips3_32",	---
26021	"Feature_HasMips3_32r2",	---	26021	"Feature_HasMips3_32r2",	---
26022	"Feature_HasMips4_32",	---	26022	"Feature_HasMips4_32",	---
26023	"Feature_HasMips4_32r2",	---	26023	"Feature_HasMips4_32r2",	---
26024	"Feature_HasMips5_32r2",	---	26024	"Feature_HasMips5_32r2",	---
26025	"Feature_HasMips32",	---	26025	"Feature_HasMips32",	---
26026	"Feature_HasMips32r2",	---	26026	"Feature_HasMips32r2",	---
26027	"Feature_HasMips32r5",	---	26027	"Feature_HasMips32r5",	---
26028	"Feature_HasMips32r6",	---	26028	"Feature_HasMips32r6",	---
26029	"Feature_HasMips64",	---	26029	"Feature_HasMips64",	---
26030	"Feature_HasMips64r2",	---	26030	"Feature_HasMips64r2",	---
26031	"Feature_HasMips64r5",	---	26031	"Feature_HasMips64r5",	---
26032	"Feature_HasMips64r6",	---	26032	"Feature_HasMips64r6",	---
26033	"Feature_HasStdEnc",	---	26033	"Feature_HasStdEnc",	---
26034	"Feature_HasVirt",	---	26034	"Feature_HasVirt",	---
26035	"Feature_InMicroMips",	---	26035	"Feature_InMicroMips",	---
26036	"Feature_InMips16Mode",	---	26036	"Feature_InMips16Mode",	---
26037	"Feature_IsFP64bit",	---	26037	"Feature_IsFP64bit",	---
26038	"Feature_IsGP32bit",	---	26038	"Feature_IsGP32bit",	---
26039	"Feature_IsGP64bit",	---	26039	"Feature_IsGP64bit",	---
26040	"Feature_IsNotSingleFloat",	---	26040	"Feature_IsNotSingleFloat",	---
26041	"Feature_IsNotSoftFloat",	---	26041	"Feature_IsNotSoftFloat",	---
26042	"Feature_IsPTR32bit",	---	26042	"Feature_IsPTR32bit",	---
26043	"Feature_IsPTR64bit",	---	26043	"Feature_IsPTR64bit",	---
26044	"Feature_IsSingleFloat",	---	26044	"Feature_IsSingleFloat",	---
26045	"Feature_IsSym32",	---	26045	"Feature_IsSym32",	---
26046	"Feature_IsSym64",	---	26046	"Feature_IsSym64",	---
26047	"Feature_NoIndirectJumpGuards",	---	26047	"Feature_NoIndirectJumpGuards",	---
26048	"Feature_NotCnMips",	---	26048	"Feature_NotCnMips",	---
26049	"Feature_NotCnMipsP",	---	26049	"Feature_NotCnMipsP",	---
26050	"Feature_NotFP64bit",	---	26050	"Feature_NotFP64bit",	---
26051	"Feature_NotInMicroMips",	---	26051	"Feature_NotInMicroMips",	---
26052	"Feature_NotInMips16Mode",	---	26052	"Feature_NotInMips16Mode",	---
26053	"Feature_NotMips3",	---	26053	"Feature_NotMips3",	---
26054	"Feature_NotMips4_32",	---	26054	"Feature_NotMips4_32",	---
26055	"Feature_NotMips32r6",	---	26055	"Feature_NotMips32r6",	---
26056	"Feature_NotMips64",	---	26056	"Feature_NotMips64",	---
26057	"Feature_NotMips64r6",	---	26057	"Feature_NotMips64r6",	---
26058	"Feature_UseIndirectJumpsHazard",	---	26058	"Feature_UseIndirectJumpsHazard",	---
26059	nullptr	---	26059	nullptr	---
26060	};	---	26060	};	---
26061		---	26061		---
26062	#endif // NDEBUG	---	26062	#endif // NDEBUG	---
26063		---	26063		---
26064	void verifyInstructionPredicates(	0	26064	void verifyInstructionPredicates(	0
26065	unsigned Opcode, const FeatureBitset &Features) {	---	26065	unsigned Opcode, const FeatureBitset &Features) {	---
26066	#ifndef NDEBUG	---	26066	#ifndef NDEBUG	---
26067	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);	0	26067	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);	0
26068	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);	0	26068	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);	0
26069	FeatureBitset MissingFeatures =	---	26069	FeatureBitset MissingFeatures =	---
26070	(AvailableFeatures & RequiredFeatures) ^	0	26070	(AvailableFeatures & RequiredFeatures) ^	0
26071	RequiredFeatures;	0	26071	RequiredFeatures;	0
26072	if (MissingFeatures.any()) {	0	26072	if (MissingFeatures.any()) {	0
26073	std::ostringstream Msg;	0	26073	std::ostringstream Msg;	0
26074	Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]	0	26074	Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]	0
26075	<< " instruction but the ";	0	26075	<< " instruction but the ";	0
26076	for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)	0	26076	for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)	0
26077	if (MissingFeatures.test(i))	0	26077	if (MissingFeatures.test(i))	0
26078	Msg << SubtargetFeatureNames[i] << " ";	0	26078	Msg << SubtargetFeatureNames[i] << " ";	0
26079	Msg << "predicate(s) are not met";	0	26079	Msg << "predicate(s) are not met";	0
26080	report_fatal_error(Msg.str().c_str());	0	26080	report_fatal_error(Msg.str().c_str());	0
26081	}	---	26081	}	---
26082	#endif // NDEBUG	---	26082	#endif // NDEBUG	---
26083	}	0	26083	}	0
26084	} // end namespace Mips_MC	---	26084	} // end namespace Mips_MC	---
26085	} // end namespace llvm	---	26085	} // end namespace llvm	---
26086	#endif // ENABLE_INSTR_PREDICATE_VERIFIER	---	26086	#endif // ENABLE_INSTR_PREDICATE_VERIFIER	---
26087		---	26087		---
26088	#ifdef GET_INSTRMAP_INFO	---	26088	#ifdef GET_INSTRMAP_INFO	---
26089	#undef GET_INSTRMAP_INFO	---	26089	#undef GET_INSTRMAP_INFO	---
26090	namespace llvm {	---	26090	namespace llvm {	---
26091		---	26091		---
26092	namespace Mips {	---	26092	namespace Mips {	---
26093		---	26093		---
26094	enum Arch {	---	26094	enum Arch {	---
26095	Arch_dsp,	---	26095	Arch_dsp,	---
26096	Arch_mmdsp,	---	26096	Arch_mmdsp,	---
26097	Arch_mipsr6,	---	26097	Arch_mipsr6,	---
26098	Arch_micromipsr6,	---	26098	Arch_micromipsr6,	---
26099	Arch_se,	---	26099	Arch_se,	---
26100	Arch_micromips	---	26100	Arch_micromips	---
26101	};	---	26101	};	---
26102		---	26102		---
26103	// Dsp2MicroMips	---	26103	// Dsp2MicroMips	---
26104	LLVM_READONLY	---	26104	LLVM_READONLY	---
26105	int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {	---	26105	int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {	---
26106	static const uint16_t Dsp2MicroMipsTable[][3] = {	---	26106	static const uint16_t Dsp2MicroMipsTable[][3] = {	---
26107	{ Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },	---	26107	{ Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },	---
26108	{ Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },	---	26108	{ Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },	---
26109	{ Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },	---	26109	{ Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },	---
26110	{ Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },	---	26110	{ Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },	---
26111	{ Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },	---	26111	{ Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },	---
26112	{ Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },	---	26112	{ Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },	---
26113	{ Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },	---	26113	{ Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },	---
26114	{ Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },	---	26114	{ Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },	---
26115	{ Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },	---	26115	{ Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },	---
26116	{ Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },	---	26116	{ Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },	---
26117	{ Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },	---	26117	{ Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },	---
26118	{ Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },	---	26118	{ Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },	---
26119	{ Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },	---	26119	{ Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },	---
26120	{ Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },	---	26120	{ Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },	---
26121	{ Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },	---	26121	{ Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },	---
26122	{ Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },	---	26122	{ Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },	---
26123	{ Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },	---	26123	{ Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },	---
26124	{ Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },	---	26124	{ Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },	---
26125	{ Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },	---	26125	{ Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },	---
26126	{ Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },	---	26126	{ Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },	---
26127	{ Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },	---	26127	{ Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },	---
26128	{ Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },	---	26128	{ Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },	---
26129	{ Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },	---	26129	{ Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },	---
26130	{ Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },	---	26130	{ Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },	---
26131	{ Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },	---	26131	{ Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },	---
26132	{ Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },	---	26132	{ Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },	---
26133	{ Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },	---	26133	{ Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },	---
26134	{ Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },	---	26134	{ Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },	---
26135	{ Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },	---	26135	{ Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },	---
26136	{ Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },	---	26136	{ Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },	---
26137	{ Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },	---	26137	{ Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },	---
26138	{ Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },	---	26138	{ Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },	---
26139	{ Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },	---	26139	{ Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },	---
26140	{ Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },	---	26140	{ Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },	---
26141	{ Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },	---	26141	{ Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },	---
26142	{ Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },	---	26142	{ Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },	---
26143	{ Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },	---	26143	{ Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },	---
26144	{ Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },	---	26144	{ Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },	---
26145	{ Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },	---	26145	{ Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },	---
26146	{ Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },	---	26146	{ Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },	---
26147	{ Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },	---	26147	{ Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },	---
26148	{ Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },	---	26148	{ Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },	---
26149	{ Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },	---	26149	{ Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },	---
26150	{ Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },	---	26150	{ Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },	---
26151	{ Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },	---	26151	{ Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },	---
26152	{ Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },	---	26152	{ Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },	---
26153	{ Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },	---	26153	{ Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },	---
26154	{ Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },	---	26154	{ Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },	---
26155	{ Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },	---	26155	{ Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },	---
26156	{ Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },	---	26156	{ Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },	---
26157	{ Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },	---	26157	{ Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },	---
26158	{ Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },	---	26158	{ Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },	---
26159	{ Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },	---	26159	{ Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },	---
26160	{ Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },	---	26160	{ Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },	---
26161	{ Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },	---	26161	{ Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },	---
26162	{ Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },	---	26162	{ Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },	---
26163	{ Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },	---	26163	{ Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },	---
26164	{ Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },	---	26164	{ Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },	---
26165	{ Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },	---	26165	{ Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },	---
26166	{ Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },	---	26166	{ Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },	---
26167	{ Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },	---	26167	{ Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },	---
26168	{ Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },	---	26168	{ Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },	---
26169	{ Mips::INSV, Mips::INSV, Mips::INSV_MM },	---	26169	{ Mips::INSV, Mips::INSV, Mips::INSV_MM },	---
26170	{ Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },	---	26170	{ Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },	---
26171	{ Mips::LHX, Mips::LHX, Mips::LHX_MM },	---	26171	{ Mips::LHX, Mips::LHX, Mips::LHX_MM },	---
26172	{ Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },	---	26172	{ Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },	---
26173	{ Mips::LWX, Mips::LWX, Mips::LWX_MM },	---	26173	{ Mips::LWX, Mips::LWX, Mips::LWX_MM },	---
26174	{ Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },	---	26174	{ Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },	---
26175	{ Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },	---	26175	{ Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },	---
26176	{ Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },	---	26176	{ Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },	---
26177	{ Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },	---	26177	{ Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },	---
26178	{ Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },	---	26178	{ Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },	---
26179	{ Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },	---	26179	{ Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },	---
26180	{ Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },	---	26180	{ Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },	---
26181	{ Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },	---	26181	{ Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },	---
26182	{ Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },	---	26182	{ Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },	---
26183	{ Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },	---	26183	{ Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },	---
26184	{ Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },	---	26184	{ Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },	---
26185	{ Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },	---	26185	{ Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },	---
26186	{ Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },	---	26186	{ Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },	---
26187	{ Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },	---	26187	{ Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },	---
26188	{ Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },	---	26188	{ Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },	---
26189	{ Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },	---	26189	{ Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },	---
26190	{ Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },	---	26190	{ Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },	---
26191	{ Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },	---	26191	{ Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },	---
26192	{ Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },	---	26192	{ Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },	---
26193	{ Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },	---	26193	{ Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },	---
26194	{ Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },	---	26194	{ Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },	---
26195	{ Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },	---	26195	{ Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },	---
26196	{ Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },	---	26196	{ Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },	---
26197	{ Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },	---	26197	{ Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },	---
26198	{ Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },	---	26198	{ Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },	---
26199	{ Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },	---	26199	{ Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },	---
26200	{ Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },	---	26200	{ Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },	---
26201	{ Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },	---	26201	{ Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },	---
26202	{ Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },	---	26202	{ Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },	---
26203	{ Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },	---	26203	{ Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },	---
26204	{ Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },	---	26204	{ Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },	---
26205	{ Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },	---	26205	{ Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },	---
26206	{ Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },	---	26206	{ Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },	---
26207	{ Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },	---	26207	{ Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },	---
26208	{ Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },	---	26208	{ Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },	---
26209	{ Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },	---	26209	{ Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },	---
26210	{ Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },	---	26210	{ Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },	---
26211	{ Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },	---	26211	{ Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },	---
26212	{ Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },	---	26212	{ Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },	---
26213	{ Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },	---	26213	{ Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },	---
26214	{ Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },	---	26214	{ Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },	---
26215	{ Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },	---	26215	{ Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },	---
26216	{ Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },	---	26216	{ Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },	---
26217	{ Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },	---	26217	{ Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },	---
26218	{ Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },	---	26218	{ Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },	---
26219	{ Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },	---	26219	{ Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },	---
26220	{ Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },	---	26220	{ Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },	---
26221	{ Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },	---	26221	{ Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },	---
26222	{ Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },	---	26222	{ Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },	---
26223	{ Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },	---	26223	{ Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },	---
26224	{ Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },	---	26224	{ Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },	---
26225	{ Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },	---	26225	{ Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },	---
26226	{ Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },	---	26226	{ Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },	---
26227	{ Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },	---	26227	{ Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },	---
26228	{ Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },	---	26228	{ Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },	---
26229	{ Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },	---	26229	{ Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },	---
26230	{ Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },	---	26230	{ Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },	---
26231	{ Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },	---	26231	{ Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },	---
26232	{ Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },	---	26232	{ Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },	---
26233	{ Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },	---	26233	{ Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },	---
26234	{ Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },	---	26234	{ Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },	---
26235	{ Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },	---	26235	{ Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },	---
26236	{ Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },	---	26236	{ Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },	---
26237	{ Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },	---	26237	{ Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },	---
26238	{ Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },	---	26238	{ Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },	---
26239	{ Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },	---	26239	{ Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },	---
26240	{ Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },	---	26240	{ Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },	---
26241	{ Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },	---	26241	{ Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },	---
26242	{ Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },	---	26242	{ Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },	---
26243	{ Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },	---	26243	{ Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },	---
26244	{ Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },	---	26244	{ Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },	---
26245	{ Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },	---	26245	{ Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },	---
26246	{ Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },	---	26246	{ Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },	---
26247	{ Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },	---	26247	{ Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },	---
26248	{ Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },	---	26248	{ Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },	---
26249	{ Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },	---	26249	{ Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },	---
26250	{ Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },	---	26250	{ Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },	---
26251	{ Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },	---	26251	{ Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },	---
26252	{ Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },	---	26252	{ Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },	---
26253	{ Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },	---	26253	{ Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },	---
26254	{ Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },	---	26254	{ Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },	---
26255	{ Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },	---	26255	{ Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },	---
26256	{ Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },	---	26256	{ Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },	---
26257	{ Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },	---	26257	{ Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },	---
26258	{ Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },	---	26258	{ Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },	---
26259	{ Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },	---	26259	{ Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },	---
26260	{ Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },	---	26260	{ Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },	---
26261	{ Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },	---	26261	{ Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },	---
26262	{ Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },	---	26262	{ Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },	---
26263	{ Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },	---	26263	{ Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },	---
26264	{ Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },	---	26264	{ Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },	---
26265	{ Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },	---	26265	{ Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },	---
26266	{ Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },	---	26266	{ Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },	---
26267	}; // End of Dsp2MicroMipsTable	---	26267	}; // End of Dsp2MicroMipsTable	---
26268		---	26268		---
26269	unsigned mid;	---	26269	unsigned mid;	---
26270	unsigned start = 0;	---	26270	unsigned start = 0;	---
26271	unsigned end = 160;	---	26271	unsigned end = 160;	---
26272	while (start < end) {	---	26272	while (start < end) {	---
26273	mid = start + (end - start) / 2;	---	26273	mid = start + (end - start) / 2;	---
26274	if (Opcode == Dsp2MicroMipsTable[mid][0]) {	---	26274	if (Opcode == Dsp2MicroMipsTable[mid][0]) {	---
26275	break;	---	26275	break;	---
26276	}	---	26276	}	---
26277	if (Opcode < Dsp2MicroMipsTable[mid][0])	---	26277	if (Opcode < Dsp2MicroMipsTable[mid][0])	---
26278	end = mid;	---	26278	end = mid;	---
26279	else	---	26279	else	---
26280	start = mid + 1;	---	26280	start = mid + 1;	---
26281	}	---	26281	}	---
26282	if (start == end)	---	26282	if (start == end)	---
26283	return -1; // Instruction doesn't exist in this table.	---	26283	return -1; // Instruction doesn't exist in this table.	---
26284		---	26284		---
26285	if (inArch == Arch_dsp)	---	26285	if (inArch == Arch_dsp)	---
26286	return Dsp2MicroMipsTable[mid][1];	---	26286	return Dsp2MicroMipsTable[mid][1];	---
26287	if (inArch == Arch_mmdsp)	---	26287	if (inArch == Arch_mmdsp)	---
26288	return Dsp2MicroMipsTable[mid][2];	---	26288	return Dsp2MicroMipsTable[mid][2];	---
26289	return -1;}	---	26289	return -1;}	---
26290		---	26290		---
26291	// MipsR62MicroMipsR6	---	26291	// MipsR62MicroMipsR6	---
26292	LLVM_READONLY	---	26292	LLVM_READONLY	---
26293	int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	---	26293	int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	---
26294	static const uint16_t MipsR62MicroMipsR6Table[][3] = {	---	26294	static const uint16_t MipsR62MicroMipsR6Table[][3] = {	---
26295	{ Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },	---	26295	{ Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },	---
26296	{ Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },	---	26296	{ Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },	---
26297	{ Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },	---	26297	{ Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },	---
26298	{ Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },	---	26298	{ Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },	---
26299	{ Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },	---	26299	{ Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },	---
26300	{ Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },	---	26300	{ Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },	---
26301	{ Mips::BC, Mips::BC, Mips::BC_MMR6 },	---	26301	{ Mips::BC, Mips::BC, Mips::BC_MMR6 },	---
26302	{ Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },	---	26302	{ Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },	---
26303	{ Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },	---	26303	{ Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },	---
26304	{ Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },	---	26304	{ Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },	---
26305	{ Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },	---	26305	{ Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },	---
26306	{ Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },	---	26306	{ Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },	---
26307	{ Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },	---	26307	{ Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },	---
26308	{ Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },	---	26308	{ Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },	---
26309	{ Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },	---	26309	{ Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },	---
26310	{ Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },	---	26310	{ Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },	---
26311	{ Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },	---	26311	{ Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },	---
26312	{ Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },	---	26312	{ Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },	---
26313	{ Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },	---	26313	{ Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },	---
26314	{ Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },	---	26314	{ Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },	---
26315	{ Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },	---	26315	{ Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },	---
26316	{ Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },	---	26316	{ Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },	---
26317	{ Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },	---	26317	{ Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },	---
26318	{ Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },	---	26318	{ Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },	---
26319	{ Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },	---	26319	{ Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },	---
26320	{ Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },	---	26320	{ Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },	---
26321	{ Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },	---	26321	{ Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },	---
26322	{ Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },	---	26322	{ Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },	---
26323	{ Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },	---	26323	{ Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },	---
26324	{ Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },	---	26324	{ Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },	---
26325	{ Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },	---	26325	{ Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },	---
26326	{ Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },	---	26326	{ Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },	---
26327	{ Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },	---	26327	{ Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },	---
26328	{ Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },	---	26328	{ Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },	---
26329	{ Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },	---	26329	{ Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },	---
26330	{ Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },	---	26330	{ Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },	---
26331	{ Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },	---	26331	{ Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },	---
26332	{ Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },	---	26332	{ Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },	---
26333	{ Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },	---	26333	{ Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },	---
26334	{ Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },	---	26334	{ Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },	---
26335	{ Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },	---	26335	{ Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },	---
26336	{ Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },	---	26336	{ Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },	---
26337	{ Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },	---	26337	{ Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },	---
26338	{ Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },	---	26338	{ Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },	---
26339	{ Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },	---	26339	{ Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },	---
26340	{ Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },	---	26340	{ Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },	---
26341	{ Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },	---	26341	{ Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },	---
26342	{ Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },	---	26342	{ Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },	---
26343	{ Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },	---	26343	{ Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },	---
26344	{ Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },	---	26344	{ Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },	---
26345	{ Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },	---	26345	{ Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },	---
26346	{ Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },	---	26346	{ Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },	---
26347	{ Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },	---	26347	{ Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },	---
26348	{ Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },	---	26348	{ Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },	---
26349	{ Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },	---	26349	{ Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },	---
26350	{ Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },	---	26350	{ Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },	---
26351	{ Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },	---	26351	{ Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },	---
26352	{ Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },	---	26352	{ Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },	---
26353	{ Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },	---	26353	{ Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },	---
26354	{ Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },	---	26354	{ Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },	---
26355	{ Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },	---	26355	{ Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },	---
26356	{ Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },	---	26356	{ Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },	---
26357	{ Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },	---	26357	{ Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },	---
26358	{ Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },	---	26358	{ Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },	---
26359	{ Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },	---	26359	{ Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },	---
26360	{ Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },	---	26360	{ Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },	---
26361	{ Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },	---	26361	{ Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },	---
26362	{ Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },	---	26362	{ Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },	---
26363	{ Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },	---	26363	{ Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },	---
26364	{ Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },	---	26364	{ Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },	---
26365	{ Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },	---	26365	{ Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },	---
26366	{ Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },	---	26366	{ Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },	---
26367	{ Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },	---	26367	{ Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },	---
26368	{ Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },	---	26368	{ Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },	---
26369	{ Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },	---	26369	{ Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },	---
26370	{ Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },	---	26370	{ Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },	---
26371	{ Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },	---	26371	{ Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },	---
26372	{ Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },	---	26372	{ Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },	---
26373	{ Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },	---	26373	{ Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },	---
26374	{ Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },	---	26374	{ Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },	---
26375	{ Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },	---	26375	{ Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },	---
26376	{ Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },	---	26376	{ Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },	---
26377	{ Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },	---	26377	{ Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },	---
26378	{ Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },	---	26378	{ Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },	---
26379	{ Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },	---	26379	{ Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },	---
26380	{ Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },	---	26380	{ Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },	---
26381	{ Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },	---	26381	{ Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },	---
26382	{ Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },	---	26382	{ Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },	---
26383	{ Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },	---	26383	{ Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },	---
26384	{ Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },	---	26384	{ Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },	---
26385	{ Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },	---	26385	{ Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },	---
26386	{ Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },	---	26386	{ Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },	---
26387	{ Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },	---	26387	{ Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },	---
26388	{ Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },	---	26388	{ Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },	---
26389	{ Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },	---	26389	{ Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },	---
26390	{ Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },	---	26390	{ Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },	---
26391	}; // End of MipsR62MicroMipsR6Table	---	26391	}; // End of MipsR62MicroMipsR6Table	---
26392		---	26392		---
26393	unsigned mid;	---	26393	unsigned mid;	---
26394	unsigned start = 0;	---	26394	unsigned start = 0;	---
26395	unsigned end = 96;	---	26395	unsigned end = 96;	---
26396	while (start < end) {	---	26396	while (start < end) {	---
26397	mid = start + (end - start) / 2;	---	26397	mid = start + (end - start) / 2;	---
26398	if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {	---	26398	if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {	---
26399	break;	---	26399	break;	---
26400	}	---	26400	}	---
26401	if (Opcode < MipsR62MicroMipsR6Table[mid][0])	---	26401	if (Opcode < MipsR62MicroMipsR6Table[mid][0])	---
26402	end = mid;	---	26402	end = mid;	---
26403	else	---	26403	else	---
26404	start = mid + 1;	---	26404	start = mid + 1;	---
26405	}	---	26405	}	---
26406	if (start == end)	---	26406	if (start == end)	---
26407	return -1; // Instruction doesn't exist in this table.	---	26407	return -1; // Instruction doesn't exist in this table.	---
26408		---	26408		---
26409	if (inArch == Arch_mipsr6)	---	26409	if (inArch == Arch_mipsr6)	---
26410	return MipsR62MicroMipsR6Table[mid][1];	---	26410	return MipsR62MicroMipsR6Table[mid][1];	---
26411	if (inArch == Arch_micromipsr6)	---	26411	if (inArch == Arch_micromipsr6)	---
26412	return MipsR62MicroMipsR6Table[mid][2];	---	26412	return MipsR62MicroMipsR6Table[mid][2];	---
26413	return -1;}	---	26413	return -1;}	---
26414		---	26414		---
26415	// Std2MicroMips	---	26415	// Std2MicroMips	---
26416	LLVM_READONLY	---	26416	LLVM_READONLY	---
26417	int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {	---	26417	int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {	---
26418	static const uint16_t Std2MicroMipsTable[][3] = {	---	26418	static const uint16_t Std2MicroMipsTable[][3] = {	---
26419	{ Mips::ADD, Mips::ADD, Mips::ADD_MM },	---	26419	{ Mips::ADD, Mips::ADD, Mips::ADD_MM },	---
26420	{ Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },	---	26420	{ Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },	---
26421	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },	---	26421	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },	---
26422	{ Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },	---	26422	{ Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },	---
26423	{ Mips::AND, Mips::AND, Mips::AND_MM },	---	26423	{ Mips::AND, Mips::AND, Mips::AND_MM },	---
26424	{ Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },	---	26424	{ Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },	---
26425	{ Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },	---	26425	{ Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },	---
26426	{ Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },	---	26426	{ Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },	---
26427	{ Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },	---	26427	{ Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },	---
26428	{ Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },	---	26428	{ Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },	---
26429	{ Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },	---	26429	{ Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },	---
26430	{ Mips::BEQL, Mips::BEQL, (uint16_t)-1U },	---	26430	{ Mips::BEQL, Mips::BEQL, (uint16_t)-1U },	---
26431	{ Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },	---	26431	{ Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },	---
26432	{ Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },	---	26432	{ Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },	---
26433	{ Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },	---	26433	{ Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },	---
26434	{ Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },	---	26434	{ Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },	---
26435	{ Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },	---	26435	{ Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },	---
26436	{ Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },	---	26436	{ Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },	---
26437	{ Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },	---	26437	{ Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },	---
26438	{ Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },	---	26438	{ Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },	---
26439	{ Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },	---	26439	{ Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },	---
26440	{ Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },	---	26440	{ Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },	---
26441	{ Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },	---	26441	{ Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },	---
26442	{ Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },	---	26442	{ Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },	---
26443	{ Mips::BNE, Mips::BNE, Mips::BNE_MM },	---	26443	{ Mips::BNE, Mips::BNE, Mips::BNE_MM },	---
26444	{ Mips::BNEL, Mips::BNEL, (uint16_t)-1U },	---	26444	{ Mips::BNEL, Mips::BNEL, (uint16_t)-1U },	---
26445	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },	---	26445	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },	---
26446	{ Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },	---	26446	{ Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },	---
26447	{ Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },	---	26447	{ Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },	---
26448	{ Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },	---	26448	{ Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },	---
26449	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },	---	26449	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },	---
26450	{ Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },	---	26450	{ Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },	---
26451	{ Mips::CLO, Mips::CLO, Mips::CLO_MM },	---	26451	{ Mips::CLO, Mips::CLO, Mips::CLO_MM },	---
26452	{ Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },	---	26452	{ Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },	---
26453	{ Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },	---	26453	{ Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },	---
26454	{ Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },	---	26454	{ Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },	---
26455	{ Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },	---	26455	{ Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },	---
26456	{ Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },	---	26456	{ Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },	---
26457	{ Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },	---	26457	{ Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },	---
26458	{ Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },	---	26458	{ Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },	---
26459	{ Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },	---	26459	{ Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },	---
26460	{ Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },	---	26460	{ Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },	---
26461	{ Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },	---	26461	{ Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },	---
26462	{ Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },	---	26462	{ Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },	---
26463	{ Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },	---	26463	{ Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },	---
26464	{ Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },	---	26464	{ Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },	---
26465	{ Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },	---	26465	{ Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },	---
26466	{ Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },	---	26466	{ Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },	---
26467	{ Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },	---	26467	{ Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },	---
26468	{ Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },	---	26468	{ Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },	---
26469	{ Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },	---	26469	{ Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },	---
26470	{ Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },	---	26470	{ Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },	---
26471	{ Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },	---	26471	{ Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },	---
26472	{ Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },	---	26472	{ Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },	---
26473	{ Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },	---	26473	{ Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },	---
26474	{ Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },	---	26474	{ Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },	---
26475	{ Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },	---	26475	{ Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },	---
26476	{ Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },	---	26476	{ Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },	---
26477	{ Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },	---	26477	{ Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },	---
26478	{ Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },	---	26478	{ Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },	---
26479	{ Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },	---	26479	{ Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },	---
26480	{ Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },	---	26480	{ Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },	---
26481	{ Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },	---	26481	{ Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },	---
26482	{ Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },	---	26482	{ Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },	---
26483	{ Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },	---	26483	{ Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },	---
26484	{ Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },	---	26484	{ Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },	---
26485	{ Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },	---	26485	{ Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },	---
26486	{ Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },	---	26486	{ Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },	---
26487	{ Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },	---	26487	{ Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },	---
26488	{ Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },	---	26488	{ Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },	---
26489	{ Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },	---	26489	{ Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },	---
26490	{ Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },	---	26490	{ Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },	---
26491	{ Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },	---	26491	{ Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },	---
26492	{ Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },	---	26492	{ Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },	---
26493	{ Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },	---	26493	{ Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },	---
26494	{ Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },	---	26494	{ Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },	---
26495	{ Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },	---	26495	{ Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },	---
26496	{ Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },	---	26496	{ Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },	---
26497	{ Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },	---	26497	{ Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },	---
26498	{ Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },	---	26498	{ Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },	---
26499	{ Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },	---	26499	{ Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },	---
26500	{ Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },	---	26500	{ Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },	---
26501	{ Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },	---	26501	{ Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },	---
26502	{ Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },	---	26502	{ Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },	---
26503	{ Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },	---	26503	{ Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },	---
26504	{ Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },	---	26504	{ Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },	---
26505	{ Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },	---	26505	{ Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },	---
26506	{ Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },	---	26506	{ Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },	---
26507	{ Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },	---	26507	{ Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },	---
26508	{ Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },	---	26508	{ Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },	---
26509	{ Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },	---	26509	{ Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },	---
26510	{ Mips::DERET, Mips::DERET, Mips::DERET_MM },	---	26510	{ Mips::DERET, Mips::DERET, Mips::DERET_MM },	---
26511	{ Mips::DI, Mips::DI, Mips::DI_MM },	---	26511	{ Mips::DI, Mips::DI, Mips::DI_MM },	---
26512	{ Mips::EHB, Mips::EHB, Mips::EHB_MM },	---	26512	{ Mips::EHB, Mips::EHB, Mips::EHB_MM },	---
26513	{ Mips::EI, Mips::EI, Mips::EI_MM },	---	26513	{ Mips::EI, Mips::EI, Mips::EI_MM },	---
26514	{ Mips::ERET, Mips::ERET, Mips::ERET_MM },	---	26514	{ Mips::ERET, Mips::ERET, Mips::ERET_MM },	---
26515	{ Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },	---	26515	{ Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },	---
26516	{ Mips::EXT, Mips::EXT, Mips::EXT_MM },	---	26516	{ Mips::EXT, Mips::EXT, Mips::EXT_MM },	---
26517	{ Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },	---	26517	{ Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },	---
26518	{ Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },	---	26518	{ Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },	---
26519	{ Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },	---	26519	{ Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },	---
26520	{ Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },	---	26520	{ Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },	---
26521	{ Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },	---	26521	{ Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },	---
26522	{ Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },	---	26522	{ Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },	---
26523	{ Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },	---	26523	{ Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },	---
26524	{ Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },	---	26524	{ Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },	---
26525	{ Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },	---	26525	{ Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },	---
26526	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },	---	26526	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },	---
26527	{ Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },	---	26527	{ Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },	---
26528	{ Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },	---	26528	{ Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },	---
26529	{ Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },	---	26529	{ Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },	---
26530	{ Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },	---	26530	{ Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },	---
26531	{ Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },	---	26531	{ Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },	---
26532	{ Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },	---	26532	{ Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },	---
26533	{ Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },	---	26533	{ Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },	---
26534	{ Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },	---	26534	{ Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },	---
26535	{ Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },	---	26535	{ Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },	---
26536	{ Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },	---	26536	{ Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },	---
26537	{ Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },	---	26537	{ Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },	---
26538	{ Mips::INS, Mips::INS, Mips::INS_MM },	---	26538	{ Mips::INS, Mips::INS, Mips::INS_MM },	---
26539	{ Mips::J, Mips::J, Mips::J_MM },	---	26539	{ Mips::J, Mips::J, Mips::J_MM },	---
26540	{ Mips::JAL, Mips::JAL, Mips::JAL_MM },	---	26540	{ Mips::JAL, Mips::JAL, Mips::JAL_MM },	---
26541	{ Mips::JALX, Mips::JALX, Mips::JALX_MM },	---	26541	{ Mips::JALX, Mips::JALX, Mips::JALX_MM },	---
26542	{ Mips::JR, Mips::JR, Mips::JR_MM },	---	26542	{ Mips::JR, Mips::JR, Mips::JR_MM },	---
26543	{ Mips::LB, Mips::LB, Mips::LB_MM },	---	26543	{ Mips::LB, Mips::LB, Mips::LB_MM },	---
26544	{ Mips::LBE, Mips::LBE, Mips::LBE_MM },	---	26544	{ Mips::LBE, Mips::LBE, Mips::LBE_MM },	---
26545	{ Mips::LBu, Mips::LBu, Mips::LBu_MM },	---	26545	{ Mips::LBu, Mips::LBu, Mips::LBu_MM },	---
26546	{ Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },	---	26546	{ Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },	---
26547	{ Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },	---	26547	{ Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },	---
26548	{ Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },	---	26548	{ Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },	---
26549	{ Mips::LH, Mips::LH, Mips::LH_MM },	---	26549	{ Mips::LH, Mips::LH, Mips::LH_MM },	---
26550	{ Mips::LHE, Mips::LHE, Mips::LHE_MM },	---	26550	{ Mips::LHE, Mips::LHE, Mips::LHE_MM },	---
26551	{ Mips::LHu, Mips::LHu, Mips::LHu_MM },	---	26551	{ Mips::LHu, Mips::LHu, Mips::LHu_MM },	---
26552	{ Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },	---	26552	{ Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },	---
26553	{ Mips::LLE, Mips::LLE, Mips::LLE_MM },	---	26553	{ Mips::LLE, Mips::LLE, Mips::LLE_MM },	---
26554	{ Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },	---	26554	{ Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },	---
26555	{ Mips::LUi, Mips::LUi, Mips::LUi_MM },	---	26555	{ Mips::LUi, Mips::LUi, Mips::LUi_MM },	---
26556	{ Mips::LW, Mips::LW, Mips::LW_MM },	---	26556	{ Mips::LW, Mips::LW, Mips::LW_MM },	---
26557	{ Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },	---	26557	{ Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },	---
26558	{ Mips::LWE, Mips::LWE, Mips::LWE_MM },	---	26558	{ Mips::LWE, Mips::LWE, Mips::LWE_MM },	---
26559	{ Mips::LWL, Mips::LWL, Mips::LWL_MM },	---	26559	{ Mips::LWL, Mips::LWL, Mips::LWL_MM },	---
26560	{ Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },	---	26560	{ Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },	---
26561	{ Mips::LWR, Mips::LWR, Mips::LWR_MM },	---	26561	{ Mips::LWR, Mips::LWR, Mips::LWR_MM },	---
26562	{ Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },	---	26562	{ Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },	---
26563	{ Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },	---	26563	{ Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },	---
26564	{ Mips::LWu, Mips::LWu, Mips::LWU_MM },	---	26564	{ Mips::LWu, Mips::LWu, Mips::LWU_MM },	---
26565	{ Mips::MADD, Mips::MADD, Mips::MADD_MM },	---	26565	{ Mips::MADD, Mips::MADD, Mips::MADD_MM },	---
26566	{ Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },	---	26566	{ Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },	---
26567	{ Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },	---	26567	{ Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },	---
26568	{ Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },	---	26568	{ Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },	---
26569	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },	---	26569	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },	---
26570	{ Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },	---	26570	{ Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },	---
26571	{ Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },	---	26571	{ Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },	---
26572	{ Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },	---	26572	{ Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },	---
26573	{ Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },	---	26573	{ Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },	---
26574	{ Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },	---	26574	{ Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },	---
26575	{ Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },	---	26575	{ Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },	---
26576	{ Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },	---	26576	{ Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },	---
26577	{ Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },	---	26577	{ Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },	---
26578	{ Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },	---	26578	{ Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },	---
26579	{ Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },	---	26579	{ Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },	---
26580	{ Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },	---	26580	{ Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },	---
26581	{ Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },	---	26581	{ Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },	---
26582	{ Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },	---	26582	{ Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },	---
26583	{ Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },	---	26583	{ Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },	---
26584	{ Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },	---	26584	{ Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },	---
26585	{ Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },	---	26585	{ Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },	---
26586	{ Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },	---	26586	{ Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },	---
26587	{ Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },	---	26587	{ Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },	---
26588	{ Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },	---	26588	{ Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },	---
26589	{ Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },	---	26589	{ Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },	---
26590	{ Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },	---	26590	{ Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },	---
26591	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },	---	26591	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },	---
26592	{ Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },	---	26592	{ Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },	---
26593	{ Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },	---	26593	{ Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },	---
26594	{ Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },	---	26594	{ Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },	---
26595	{ Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },	---	26595	{ Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },	---
26596	{ Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },	---	26596	{ Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },	---
26597	{ Mips::MUL, Mips::MUL, Mips::MUL_MM },	---	26597	{ Mips::MUL, Mips::MUL, Mips::MUL_MM },	---
26598	{ Mips::MULT, Mips::MULT, Mips::MULT_MM },	---	26598	{ Mips::MULT, Mips::MULT, Mips::MULT_MM },	---
26599	{ Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },	---	26599	{ Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },	---
26600	{ Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },	---	26600	{ Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },	---
26601	{ Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },	---	26601	{ Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },	---
26602	{ Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },	---	26602	{ Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },	---
26603	{ Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },	---	26603	{ Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },	---
26604	{ Mips::NOR, Mips::NOR, Mips::NOR_MM },	---	26604	{ Mips::NOR, Mips::NOR, Mips::NOR_MM },	---
26605	{ Mips::OR, Mips::OR, Mips::OR_MM },	---	26605	{ Mips::OR, Mips::OR, Mips::OR_MM },	---
26606	{ Mips::ORi, Mips::ORi, Mips::ORi_MM },	---	26606	{ Mips::ORi, Mips::ORi, Mips::ORi_MM },	---
26607	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },	---	26607	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },	---
26608	{ Mips::PREF, Mips::PREF, Mips::PREF_MM },	---	26608	{ Mips::PREF, Mips::PREF, Mips::PREF_MM },	---
26609	{ Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },	---	26609	{ Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },	---
26610	{ Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },	---	26610	{ Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },	---
26611	{ Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },	---	26611	{ Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },	---
26612	{ Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },	---	26612	{ Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },	---
26613	{ Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },	---	26613	{ Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },	---
26614	{ Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },	---	26614	{ Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },	---
26615	{ Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },	---	26615	{ Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },	---
26616	{ Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },	---	26616	{ Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },	---
26617	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },	---	26617	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },	---
26618	{ Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },	---	26618	{ Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },	---
26619	{ Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },	---	26619	{ Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },	---
26620	{ Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },	---	26620	{ Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },	---
26621	{ Mips::SB, Mips::SB, Mips::SB_MM },	---	26621	{ Mips::SB, Mips::SB, Mips::SB_MM },	---
26622	{ Mips::SBE, Mips::SBE, Mips::SBE_MM },	---	26622	{ Mips::SBE, Mips::SBE, Mips::SBE_MM },	---
26623	{ Mips::SCE, Mips::SCE, Mips::SCE_MM },	---	26623	{ Mips::SCE, Mips::SCE, Mips::SCE_MM },	---
26624	{ Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },	---	26624	{ Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },	---
26625	{ Mips::SDC1, Mips::SDC1, (uint16_t)-1U },	---	26625	{ Mips::SDC1, Mips::SDC1, (uint16_t)-1U },	---
26626	{ Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },	---	26626	{ Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },	---
26627	{ Mips::SEB, Mips::SEB, Mips::SEB_MM },	---	26627	{ Mips::SEB, Mips::SEB, Mips::SEB_MM },	---
26628	{ Mips::SEH, Mips::SEH, Mips::SEH_MM },	---	26628	{ Mips::SEH, Mips::SEH, Mips::SEH_MM },	---
26629	{ Mips::SH, Mips::SH, Mips::SH_MM },	---	26629	{ Mips::SH, Mips::SH, Mips::SH_MM },	---
26630	{ Mips::SHE, Mips::SHE, Mips::SHE_MM },	---	26630	{ Mips::SHE, Mips::SHE, Mips::SHE_MM },	---
26631	{ Mips::SLL, Mips::SLL, Mips::SLL_MM },	---	26631	{ Mips::SLL, Mips::SLL, Mips::SLL_MM },	---
26632	{ Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },	---	26632	{ Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },	---
26633	{ Mips::SLT, Mips::SLT, Mips::SLT_MM },	---	26633	{ Mips::SLT, Mips::SLT, Mips::SLT_MM },	---
26634	{ Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },	---	26634	{ Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },	---
26635	{ Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },	---	26635	{ Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },	---
26636	{ Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },	---	26636	{ Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },	---
26637	{ Mips::SRA, Mips::SRA, Mips::SRA_MM },	---	26637	{ Mips::SRA, Mips::SRA, Mips::SRA_MM },	---
26638	{ Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },	---	26638	{ Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },	---
26639	{ Mips::SRL, Mips::SRL, Mips::SRL_MM },	---	26639	{ Mips::SRL, Mips::SRL, Mips::SRL_MM },	---
26640	{ Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },	---	26640	{ Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },	---
26641	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },	---	26641	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },	---
26642	{ Mips::SUB, Mips::SUB, Mips::SUB_MM },	---	26642	{ Mips::SUB, Mips::SUB, Mips::SUB_MM },	---
26643	{ Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },	---	26643	{ Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },	---
26644	{ Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },	---	26644	{ Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },	---
26645	{ Mips::SW, Mips::SW, Mips::SW_MM },	---	26645	{ Mips::SW, Mips::SW, Mips::SW_MM },	---
26646	{ Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },	---	26646	{ Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },	---
26647	{ Mips::SWE, Mips::SWE, Mips::SWE_MM },	---	26647	{ Mips::SWE, Mips::SWE, Mips::SWE_MM },	---
26648	{ Mips::SWL, Mips::SWL, Mips::SWL_MM },	---	26648	{ Mips::SWL, Mips::SWL, Mips::SWL_MM },	---
26649	{ Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },	---	26649	{ Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },	---
26650	{ Mips::SWR, Mips::SWR, Mips::SWR_MM },	---	26650	{ Mips::SWR, Mips::SWR, Mips::SWR_MM },	---
26651	{ Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },	---	26651	{ Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },	---
26652	{ Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },	---	26652	{ Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },	---
26653	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },	---	26653	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },	---
26654	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },	---	26654	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },	---
26655	{ Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },	---	26655	{ Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },	---
26656	{ Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },	---	26656	{ Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },	---
26657	{ Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },	---	26657	{ Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },	---
26658	{ Mips::TGE, Mips::TGE, Mips::TGE_MM },	---	26658	{ Mips::TGE, Mips::TGE, Mips::TGE_MM },	---
26659	{ Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },	---	26659	{ Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },	---
26660	{ Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },	---	26660	{ Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },	---
26661	{ Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },	---	26661	{ Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },	---
26662	{ Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },	---	26662	{ Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },	---
26663	{ Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },	---	26663	{ Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },	---
26664	{ Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },	---	26664	{ Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },	---
26665	{ Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },	---	26665	{ Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },	---
26666	{ Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },	---	26666	{ Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },	---
26667	{ Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },	---	26667	{ Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },	---
26668	{ Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },	---	26668	{ Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },	---
26669	{ Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },	---	26669	{ Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },	---
26670	{ Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },	---	26670	{ Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },	---
26671	{ Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },	---	26671	{ Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },	---
26672	{ Mips::TLT, Mips::TLT, Mips::TLT_MM },	---	26672	{ Mips::TLT, Mips::TLT, Mips::TLT_MM },	---
26673	{ Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },	---	26673	{ Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },	---
26674	{ Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },	---	26674	{ Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },	---
26675	{ Mips::TNE, Mips::TNE, Mips::TNE_MM },	---	26675	{ Mips::TNE, Mips::TNE, Mips::TNE_MM },	---
26676	{ Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },	---	26676	{ Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },	---
26677	{ Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },	---	26677	{ Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },	---
26678	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },	---	26678	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },	---
26679	{ Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },	---	26679	{ Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },	---
26680	{ Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },	---	26680	{ Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },	---
26681	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },	---	26681	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },	---
26682	{ Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },	---	26682	{ Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },	---
26683	{ Mips::XOR, Mips::XOR, Mips::XOR_MM },	---	26683	{ Mips::XOR, Mips::XOR, Mips::XOR_MM },	---
26684	{ Mips::XORi, Mips::XORi, Mips::XORi_MM },	---	26684	{ Mips::XORi, Mips::XORi, Mips::XORi_MM },	---
26685	}; // End of Std2MicroMipsTable	---	26685	}; // End of Std2MicroMipsTable	---
26686		---	26686		---
26687	unsigned mid;	---	26687	unsigned mid;	---
26688	unsigned start = 0;	---	26688	unsigned start = 0;	---
26689	unsigned end = 266;	---	26689	unsigned end = 266;	---
26690	while (start < end) {	---	26690	while (start < end) {	---
26691	mid = start + (end - start) / 2;	---	26691	mid = start + (end - start) / 2;	---
26692	if (Opcode == Std2MicroMipsTable[mid][0]) {	---	26692	if (Opcode == Std2MicroMipsTable[mid][0]) {	---
26693	break;	---	26693	break;	---
26694	}	---	26694	}	---
26695	if (Opcode < Std2MicroMipsTable[mid][0])	---	26695	if (Opcode < Std2MicroMipsTable[mid][0])	---
26696	end = mid;	---	26696	end = mid;	---
26697	else	---	26697	else	---
26698	start = mid + 1;	---	26698	start = mid + 1;	---
26699	}	---	26699	}	---
26700	if (start == end)	---	26700	if (start == end)	---
26701	return -1; // Instruction doesn't exist in this table.	---	26701	return -1; // Instruction doesn't exist in this table.	---
26702		---	26702		---
26703	if (inArch == Arch_se)	---	26703	if (inArch == Arch_se)	---
26704	return Std2MicroMipsTable[mid][1];	---	26704	return Std2MicroMipsTable[mid][1];	---
26705	if (inArch == Arch_micromips)	---	26705	if (inArch == Arch_micromips)	---
26706	return Std2MicroMipsTable[mid][2];	---	26706	return Std2MicroMipsTable[mid][2];	---
26707	return -1;}	---	26707	return -1;}	---
26708		---	26708		---
26709	// Std2MicroMipsR6	---	26709	// Std2MicroMipsR6	---
26710	LLVM_READONLY	---	26710	LLVM_READONLY	---
26711	int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	---	26711	int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {	---
26712	static const uint16_t Std2MicroMipsR6Table[][3] = {	---	26712	static const uint16_t Std2MicroMipsR6Table[][3] = {	---
26713	{ Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },	---	26713	{ Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },	---
26714	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },	---	26714	{ Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },	---
26715	{ Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },	---	26715	{ Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },	---
26716	{ Mips::AND, Mips::AND, Mips::AND_MMR6 },	---	26716	{ Mips::AND, Mips::AND, Mips::AND_MMR6 },	---
26717	{ Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },	---	26717	{ Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },	---
26718	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },	---	26718	{ Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },	---
26719	{ Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },	---	26719	{ Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },	---
26720	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },	---	26720	{ Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },	---
26721	{ Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },	---	26721	{ Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },	---
26722	{ Mips::DI, Mips::DI, Mips::DI_MMR6 },	---	26722	{ Mips::DI, Mips::DI, Mips::DI_MMR6 },	---
26723	{ Mips::EI, Mips::EI, Mips::EI_MMR6 },	---	26723	{ Mips::EI, Mips::EI, Mips::EI_MMR6 },	---
26724	{ Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },	---	26724	{ Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },	---
26725	{ Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },	---	26725	{ Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },	---
26726	{ Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },	---	26726	{ Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },	---
26727	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },	---	26727	{ Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },	---
26728	{ Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },	---	26728	{ Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },	---
26729	{ Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },	---	26729	{ Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },	---
26730	{ Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },	---	26730	{ Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },	---
26731	{ Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },	---	26731	{ Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },	---
26732	{ Mips::INS, Mips::INS, Mips::INS_MMR6 },	---	26732	{ Mips::INS, Mips::INS, Mips::INS_MMR6 },	---
26733	{ Mips::LDC1, Mips::LDC1, (uint16_t)-1U },	---	26733	{ Mips::LDC1, Mips::LDC1, (uint16_t)-1U },	---
26734	{ Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },	---	26734	{ Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },	---
26735	{ Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },	---	26735	{ Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },	---
26736	{ Mips::LW, Mips::LW, Mips::LW_MMR6 },	---	26736	{ Mips::LW, Mips::LW, Mips::LW_MMR6 },	---
26737	{ Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },	---	26737	{ Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },	---
26738	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },	---	26738	{ Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },	---
26739	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },	---	26739	{ Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },	---
26740	{ Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },	---	26740	{ Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },	---
26741	{ Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },	---	26741	{ Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },	---
26742	{ Mips::OR, Mips::OR, Mips::OR_MMR6 },	---	26742	{ Mips::OR, Mips::OR, Mips::OR_MMR6 },	---
26743	{ Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },	---	26743	{ Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },	---
26744	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },	---	26744	{ Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },	---
26745	{ Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },	---	26745	{ Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },	---
26746	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },	---	26746	{ Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },	---
26747	{ Mips::SB, Mips::SB, Mips::SB_MMR6 },	---	26747	{ Mips::SB, Mips::SB, Mips::SB_MMR6 },	---
26748	{ Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },	---	26748	{ Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },	---
26749	{ Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },	---	26749	{ Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },	---
26750	{ Mips::SEB, Mips::SEB, (uint16_t)-1U },	---	26750	{ Mips::SEB, Mips::SEB, (uint16_t)-1U },	---
26751	{ Mips::SEH, Mips::SEH, (uint16_t)-1U },	---	26751	{ Mips::SEH, Mips::SEH, (uint16_t)-1U },	---
26752	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },	---	26752	{ Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },	---
26753	{ Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },	---	26753	{ Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },	---
26754	{ Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },	---	26754	{ Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },	---
26755	{ Mips::SW, Mips::SW, Mips::SW_MMR6 },	---	26755	{ Mips::SW, Mips::SW, Mips::SW_MMR6 },	---
26756	{ Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },	---	26756	{ Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },	---
26757	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },	---	26757	{ Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },	---
26758	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },	---	26758	{ Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },	---
26759	{ Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },	---	26759	{ Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },	---
26760	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },	---	26760	{ Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },	---
26761	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },	---	26761	{ Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },	---
26762	{ Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },	---	26762	{ Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },	---
26763	{ Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },	---	26763	{ Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },	---
26764	}; // End of Std2MicroMipsR6Table	---	26764	}; // End of Std2MicroMipsR6Table	---
26765		---	26765		---
26766	unsigned mid;	---	26766	unsigned mid;	---
26767	unsigned start = 0;	---	26767	unsigned start = 0;	---
26768	unsigned end = 51;	---	26768	unsigned end = 51;	---
26769	while (start < end) {	---	26769	while (start < end) {	---
26770	mid = start + (end - start) / 2;	---	26770	mid = start + (end - start) / 2;	---
26771	if (Opcode == Std2MicroMipsR6Table[mid][0]) {	---	26771	if (Opcode == Std2MicroMipsR6Table[mid][0]) {	---
26772	break;	---	26772	break;	---
26773	}	---	26773	}	---
26774	if (Opcode < Std2MicroMipsR6Table[mid][0])	---	26774	if (Opcode < Std2MicroMipsR6Table[mid][0])	---
26775	end = mid;	---	26775	end = mid;	---
26776	else	---	26776	else	---
26777	start = mid + 1;	---	26777	start = mid + 1;	---
26778	}	---	26778	}	---
26779	if (start == end)	---	26779	if (start == end)	---
26780	return -1; // Instruction doesn't exist in this table.	---	26780	return -1; // Instruction doesn't exist in this table.	---
26781		---	26781		---
26782	if (inArch == Arch_se)	---	26782	if (inArch == Arch_se)	---
26783	return Std2MicroMipsR6Table[mid][1];	---	26783	return Std2MicroMipsR6Table[mid][1];	---
26784	if (inArch == Arch_micromipsr6)	---	26784	if (inArch == Arch_micromipsr6)	---
26785	return Std2MicroMipsR6Table[mid][2];	---	26785	return Std2MicroMipsR6Table[mid][2];	---
26786	return -1;}	---	26786	return -1;}	---
26787		---	26787		---
26788	} // end namespace Mips	---	26788	} // end namespace Mips	---
26789	} // end namespace llvm	---	26789	} // end namespace llvm	---
26790	#endif // GET_INSTRMAP_INFO	---	26790	#endif // GET_INSTRMAP_INFO	---
26791		---	26791		---
26792		---	26792		---

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